From 6a7191b2d99c6048b29ba1c3b94de531dba0547e Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Tue, 24 Dec 2024 17:12:23 +0800 Subject: [PATCH] feat(pmu): support ldo dbias & ocode read from efuse for chip752mp --- .../esp_hw_support/port/esp32c5/ocode_init.c | 3 +- .../esp_hw_support/port/esp32c5/pmu_param.c | 70 +++--- .../esp_hw_support/port/esp32c5/pmu_sleep.c | 72 +++++- .../port/esp32c5/private_include/pmu_param.h | 12 +- components/hal/esp32c5/include/hal/efuse_ll.h | 38 ++- .../soc/esp32c5/register/soc/efuse_reg.h | 126 ++++++++-- .../soc/esp32c5/register/soc/efuse_struct.h | 226 ++++++++++++++++-- 7 files changed, 460 insertions(+), 87 deletions(-) diff --git a/components/esp_hw_support/port/esp32c5/ocode_init.c b/components/esp_hw_support/port/esp32c5/ocode_init.c index e17a972bbb..2c5c5659cc 100644 --- a/components/esp_hw_support/port/esp32c5/ocode_init.c +++ b/components/esp_hw_support/port/esp32c5/ocode_init.c @@ -81,8 +81,9 @@ static void IRAM_ATTR calibrate_ocode(void) void esp_ocode_calib_init(void) { + uint32_t chip_version = efuse_hal_chip_revision(); uint32_t blk_ver = efuse_hal_blk_version(); - if ((blk_ver >= 1) && (blk_ver < 100)) { + if ((chip_version == 1 && blk_ver >= 1) || (chip_version >= 100 && blk_ver >= 2)) { set_ocode_by_efuse(1); ESP_HW_LOGD(TAG, "efuse ocode"); } else { diff --git a/components/esp_hw_support/port/esp32c5/pmu_param.c b/components/esp_hw_support/port/esp32c5/pmu_param.c index 68ed37a63b..1b060f5b2b 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_param.c +++ b/components/esp_hw_support/port/esp32c5/pmu_param.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,11 @@ #include "soc/pmu_icg_mapping.h" #include "esp_private/esp_pmu.h" #include "soc/clk_tree_defs.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "esp_hw_log.h" + +static __attribute__((unused)) const char *TAG = "pmu_param"; #ifndef ARRAY_SIZE #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -419,23 +424,23 @@ uint32_t get_act_hp_dbias(void) { /* hp_cali_dbias is read from efuse to ensure that the hp_active_voltage is close to 1.15V */ + uint32_t chip_version = efuse_hal_chip_revision(); uint32_t hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; - // uint32_t blk_version = efuse_hal_blk_version(); - // if (blk_version >= 3) { - // hp_cali_dbias = efuse_ll_get_active_hp_dbias(); - // if (hp_cali_dbias != 0) { - // //efuse dbias need to add 2 to meet the CPU frequency switching - // if (hp_cali_dbias + 2 > 31) { - // hp_cali_dbias = 31; - // } else { - // hp_cali_dbias += 2; - // } - // } else { - // hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; - // ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version); - // } - // } + uint32_t blk_version = efuse_hal_blk_version(); + uint32_t hp_cali_dbias_efuse = 0; + if ((chip_version == 1 && blk_version >= 1) || (chip_version >= 100 && blk_version >= 2)) { + hp_cali_dbias_efuse = efuse_ll_get_active_hp_dbias(); + } + if (hp_cali_dbias_efuse > 0) { + //efuse dbias need to add 3 to meet the CPU frequency switching + hp_cali_dbias = hp_cali_dbias_efuse + 16 + 3; + if (hp_cali_dbias > 31) { + hp_cali_dbias = 31; + } + } else { + ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default."); + } return hp_cali_dbias; } @@ -443,24 +448,23 @@ uint32_t get_act_lp_dbias(void) { /* lp_cali_dbias is read from efuse to ensure that the lp_active_voltage is close to 1.15V */ + uint32_t chip_version = efuse_hal_chip_revision(); + uint32_t blk_version = efuse_hal_blk_version(); uint32_t lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; - // uint32_t blk_version = efuse_hal_blk_version(); - // if (blk_version >= 3) { - // lp_cali_dbias = efuse_ll_get_active_lp_dbias(); - // if (lp_cali_dbias != 0) { - // //efuse dbias need to add 2 to meet the CPU frequency switching - // if (lp_cali_dbias + 2 > 31) { - // lp_cali_dbias = 31; - // } else { - // lp_cali_dbias += 2; - // } - // } else { - // lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; - // ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version); - // } - // } else { - // ESP_HW_LOGD(TAG, "blk_version is less than 3, act dbias not burnt in efuse\n"); - // } + uint32_t lp_cali_dbias_efuse = 0; + if ((chip_version == 1 && blk_version >= 1) || (chip_version >= 100 && blk_version >= 2)) { + lp_cali_dbias_efuse = efuse_ll_get_active_lp_dbias(); + } + + if (lp_cali_dbias_efuse > 0) { + //efuse dbias need to add 3 to meet the CPU frequency switching + lp_cali_dbias = lp_cali_dbias_efuse + 16 + 3; + if (lp_cali_dbias > 31) { + lp_cali_dbias = 31; + } + } else { + ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default."); + } return lp_cali_dbias; } diff --git a/components/esp_hw_support/port/esp32c5/pmu_sleep.c b/components/esp_hw_support/port/esp32c5/pmu_sleep.c index fd95ecf4af..9310b9f23f 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c5/pmu_sleep.c @@ -19,13 +19,73 @@ #include "hal/efuse_hal.h" #include "esp_private/esp_pmu.h" #include "pmu_param.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "esp_hw_log.h" + +static __attribute__((unused)) const char *TAG = "pmu_sleep"; #define HP(state) (PMU_MODE_HP_ ## state) #define LP(state) (PMU_MODE_LP_ ## state) - static bool s_pmu_sleep_regdma_backup_enabled; +static uint32_t get_lslp_dbg(void) +{ + uint32_t pmu_dbg_atten_lightsleep = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + uint32_t chip_version = efuse_hal_chip_revision(); + uint32_t blk_version = efuse_hal_blk_version(); + if ((chip_version == 1 && blk_version >= 1) || (chip_version >= 100 && blk_version >= 2)) { + pmu_dbg_atten_lightsleep = efuse_ll_get_lslp_dbg(); + } else { + ESP_HW_LOGD(TAG, "lslp dbg not burnt in efuse\n"); + } + + return pmu_dbg_atten_lightsleep; +} + +static uint32_t get_lslp_hp_dbias(void) +{ + uint32_t pmu_hp_dbias_lightsleep_0v6 = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT; + uint32_t chip_version = efuse_hal_chip_revision(); + uint32_t blk_version = efuse_hal_blk_version(); + if ((chip_version == 1 && blk_version >= 1) || (chip_version >= 100 && blk_version >= 2)) { + pmu_hp_dbias_lightsleep_0v6 = efuse_ll_get_lslp_hp_dbias(); + } else { + ESP_HW_LOGD(TAG, "lslp hp dbias not burnt in efuse\n"); + } + + return pmu_hp_dbias_lightsleep_0v6; +} + +static uint32_t get_dslp_dbg(void) +{ + uint32_t pmu_dbg_atten_deepsleep = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT; + uint32_t chip_version = efuse_hal_chip_revision(); + uint32_t blk_version = efuse_hal_blk_version(); + if ((chip_version == 1 && blk_version >= 1) || (chip_version >= 100 && blk_version >= 2)) { + pmu_dbg_atten_deepsleep = efuse_ll_get_dslp_dbg(); + } else { + ESP_HW_LOGD(TAG, "dslp dbg not burnt in efuse\n"); + } + + return pmu_dbg_atten_deepsleep; +} + +static uint32_t get_dslp_lp_dbias(void) +{ + uint32_t pmu_lp_dbias_deepsleep_0v7 = PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT; + uint32_t chip_version = efuse_hal_chip_revision(); + uint32_t blk_version = efuse_hal_blk_version(); + if ((chip_version == 1 && blk_version >= 1) || (chip_version >= 100 && blk_version >= 2)) { + pmu_lp_dbias_deepsleep_0v7 = efuse_ll_get_dslp_lp_dbias(); + } else { + ESP_HW_LOGD(TAG, "dslp lp dbias not burnt in efuse\n"); + } + + return pmu_lp_dbias_deepsleep_0v7; +} + void pmu_sleep_enable_regdma_backup(void) { if(!s_pmu_sleep_regdma_backup_enabled){ @@ -192,22 +252,28 @@ const pmu_sleep_config_t* pmu_sleep_config_default( config->digital = digital_default; pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags); + analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = get_dslp_dbg(); + analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_dslp_lp_dbias(); + config->analog = analog_default; } else { pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags); config->digital = digital_default; pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags); + analog_default.hp_sys.analog.dbg_atten = get_lslp_dbg(); + analog_default.hp_sys.analog.dbias = get_lslp_hp_dbias(); + analog_default.lp_sys[LP(SLEEP)].analog.dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT; if (!(sleep_flags & PMU_SLEEP_PD_XTAL) || !(sleep_flags & PMU_SLEEP_PD_RC_FAST)){ analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON; analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; - analog_default.hp_sys.analog.dbias = HP_CALI_DBIAS_SLP_1V1; + analog_default.hp_sys.analog.dbias = get_act_hp_dbias(); analog_default.hp_sys.analog.dbg_atten = 0; analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON; analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; - analog_default.lp_sys[LP(SLEEP)].analog.dbias = LP_CALI_DBIAS_SLP_1V1; + analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias(); analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = 0; } diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h index 15607ffb88..0d9f67a263 100644 --- a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h @@ -40,8 +40,8 @@ extern "C" { #define PMU_HP_XPD_LIGHTSLEEP 1 #define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT 1 -#define PMU_HP_DBIAS_LIGHTSLEEP_0V6 0 -#define PMU_LP_DBIAS_LIGHTSLEEP_0V7 15 +#define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 0 +#define PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT 15 // FOR DEEPSLEEP #define PMU_DBG_HP_DEEPSLEEP 0 @@ -49,7 +49,7 @@ extern "C" { #define PMU_LP_DRVB_DEEPSLEEP 0 #define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 9 -#define PMU_LP_DBIAS_DEEPSLEEP_0V7 15 +#define PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT 15 uint32_t get_act_hp_dbias(void); uint32_t get_act_lp_dbias(void); @@ -358,7 +358,7 @@ typedef struct { .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .xpd = PMU_HP_XPD_LIGHTSLEEP, \ .dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \ - .dbias = PMU_HP_DBIAS_LIGHTSLEEP_0V6 \ + .dbias = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT \ } \ }, \ .lp_sys[PMU_MODE_LP_SLEEP] = { \ @@ -370,7 +370,7 @@ typedef struct { .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ .xpd = PMU_LP_XPD_SLEEP_DEFAULT, \ .dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \ - .dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7 \ + .dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT \ } \ } \ } @@ -393,7 +393,7 @@ typedef struct { .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ .xpd = PMU_LP_XPD_SLEEP_DEFAULT, \ .dbg_atten = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT, \ - .dbias = PMU_LP_DBIAS_DEEPSLEEP_0V7 \ + .dbias = PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT \ } \ } \ } diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h index fcf80ba519..204e28dce0 100644 --- a/components/hal/esp32c5/include/hal/efuse_ll.h +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -111,8 +111,42 @@ __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecd __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) { - // TODO: IDF-13007 - return 0; + return EFUSE.rd_sys_part1_data4.ocode; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void) +{ + return EFUSE.rd_mac_sys3.active_hp_dbias; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void) +{ + return EFUSE.rd_mac_sys3.active_lp_dbias; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_lslp_dbg(void) +{ + return EFUSE.rd_mac_sys3.lslp_hp_dbg; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_lslp_hp_dbias(void) +{ + return EFUSE.rd_mac_sys3.lslp_hp_dbias; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbg(void) +{ + return EFUSE.rd_mac_sys3.dslp_lp_dbg; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_lp_dbias(void) +{ + return (EFUSE.rd_mac_sys4.dslp_lp_dbias_1 << 4)|EFUSE.rd_mac_sys3.dslp_lp_dbias; +} + +__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) +{ + return EFUSE.rd_mac_sys4.lp_hp_dbias_vol_gap; } /******************* eFuse control functions *************************/ diff --git a/components/soc/esp32c5/register/soc/efuse_reg.h b/components/soc/esp32c5/register/soc/efuse_reg.h index ec17a5b29a..96dbf288e7 100644 --- a/components/soc/esp32c5/register/soc/efuse_reg.h +++ b/components/soc/esp32c5/register/soc/efuse_reg.h @@ -834,33 +834,88 @@ extern "C" { * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. +/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0; + * PADC CAL N bias */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. +#define EFUSE_TRIM_N_BIAS 0x0000001FU +#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S) +#define EFUSE_TRIM_N_BIAS_V 0x0000001FU +#define EFUSE_TRIM_N_BIAS_S 0 +/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0; + * PADC CAL P bias */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_TRIM_P_BIAS 0x0000001FU +#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S) +#define EFUSE_TRIM_P_BIAS_V 0x0000001FU +#define EFUSE_TRIM_P_BIAS_S 5 +/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [13:10]; default: 0; + * Active HP DBIAS of fixed voltage + */ +#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU +#define EFUSE_ACTIVE_HP_DBIAS_S 10 +/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [17:14]; default: 0; + * Active LP DBIAS of fixed voltage + */ +#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_S 14 +/** EFUSE_LSLP_HP_DBG : R; bitpos: [19:18]; default: 0; + * LSLP HP DBG of fixed voltage + */ +#define EFUSE_LSLP_HP_DBG 0x00000003U +#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S) +#define EFUSE_LSLP_HP_DBG_V 0x00000003U +#define EFUSE_LSLP_HP_DBG_S 18 +/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [23:20]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ +#define EFUSE_LSLP_HP_DBIAS 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S) +#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_S 20 +/** EFUSE_DSLP_LP_DBG : R; bitpos: [27:24]; default: 0; + * DSLP LP DBG of fixed voltage + */ +#define EFUSE_DSLP_LP_DBG 0x0000000FU +#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S) +#define EFUSE_DSLP_LP_DBG_V 0x0000000FU +#define EFUSE_DSLP_LP_DBG_S 24 +/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [31:28]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ +#define EFUSE_DSLP_LP_DBIAS 0x0000000FU +#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S) +#define EFUSE_DSLP_LP_DBIAS_V 0x0000000FU +#define EFUSE_DSLP_LP_DBIAS_S 28 /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. +/** EFUSE_DSLP_LP_DBIAS_1 : R; bitpos: [0]; default: 0; + * DSLP LP DBIAS of fixed voltage */ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_S 0 +#define EFUSE_DSLP_LP_DBIAS_1 (BIT(0)) +#define EFUSE_DSLP_LP_DBIAS_1_M (EFUSE_DSLP_LP_DBIAS_1_V << EFUSE_DSLP_LP_DBIAS_1_S) +#define EFUSE_DSLP_LP_DBIAS_1_V 0x00000001U +#define EFUSE_DSLP_LP_DBIAS_1_S 0 +/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [5:1]; default: 0; + * DBIAS gap between LP and HP + */ +#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S) +#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 1 +/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_134 0x03FFFFFFU +#define EFUSE_RESERVED_1_134_M (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S) +#define EFUSE_RESERVED_1_134_V 0x03FFFFFFU +#define EFUSE_RESERVED_1_134_S 6 /** EFUSE_RD_MAC_SYS5_REG register * Represents rd_mac_sys @@ -926,13 +981,34 @@ extern "C" { * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0; + * Temperature calibration data */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU +#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S) +#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU +#define EFUSE_TEMPERATURE_SENSOR_S 0 +/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 9 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0; + * Average initcode of ADC1 atten0 + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0; + * Average initcode of ADC1 atten0 + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27 /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 diff --git a/components/soc/esp32c5/register/soc/efuse_struct.h b/components/soc/esp32c5/register/soc/efuse_struct.h index a94c274ba0..bfa34258f8 100644 --- a/components/soc/esp32c5/register/soc/efuse_struct.h +++ b/components/soc/esp32c5/register/soc/efuse_struct.h @@ -614,15 +614,38 @@ typedef union { */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. + /** trim_n_bias : R; bitpos: [4:0]; default: 0; + * PADC CAL N bias */ - uint32_t mac_reserved_2:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. + uint32_t trim_n_bias:5; + /** trim_p_bias : R; bitpos: [9:5]; default: 0; + * PADC CAL P bias */ - uint32_t sys_data_part0_0:14; + uint32_t trim_p_bias:5; + /** active_hp_dbias : R; bitpos: [13:10]; default: 0; + * Active HP DBIAS of fixed voltage + */ + uint32_t active_hp_dbias:4; + /** active_lp_dbias : R; bitpos: [17:14]; default: 0; + * Active LP DBIAS of fixed voltage + */ + uint32_t active_lp_dbias:4; + /** lslp_hp_dbg : R; bitpos: [19:18]; default: 0; + * LSLP HP DBG of fixed voltage + */ + uint32_t lslp_hp_dbg:2; + /** lslp_hp_dbias : R; bitpos: [23:20]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ + uint32_t lslp_hp_dbias:4; + /** dslp_lp_dbg : R; bitpos: [27:24]; default: 0; + * DSLP LP DBG of fixed voltage + */ + uint32_t dslp_lp_dbg:4; + /** dslp_lp_dbias : R; bitpos: [31:28]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ + uint32_t dslp_lp_dbias:4; }; uint32_t val; } efuse_rd_mac_sys3_reg_t; @@ -632,10 +655,18 @@ typedef union { */ typedef union { struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. + /** dslp_lp_dbias_1 : R; bitpos: [0]; default: 0; + * DSLP LP DBIAS of fixed voltage */ - uint32_t sys_data_part0_1:32; + uint32_t dslp_lp_dbias_1:1; + /** lp_hp_dbias_vol_gap : R; bitpos: [5:1]; default: 0; + * DBIAS gap between LP and HP + */ + uint32_t lp_hp_dbias_vol_gap:5; + /** reserved_1_134 : R; bitpos: [31:6]; default: 0; + * reserved + */ + uint32_t reserved_1_134:26; }; uint32_t val; } efuse_rd_mac_sys4_reg_t; @@ -655,19 +686,173 @@ typedef union { /** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_sys_part1_data0 register + * Represents rd_sys_part1_data0 */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_n:32; + uint32_t optional_unique_id:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_sys_part1_data0_reg_t; +/** Type of rd_sys_part1_data1 register + * Represents rd_sys_part1_data1 + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Represents rd_sys_part1_data2 + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Represents rd_sys_part1_data3 + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Represents rd_sys_part1_data4 + */ +typedef union { + struct { + /** temperature_sensor : R; bitpos: [8:0]; default: 0; + * Temperature calibration data + */ + uint32_t temperature_sensor:9; + /** ocode : R; bitpos: [16:9]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0; + * Average initcode of ADC1 atten0 + */ + uint32_t adc1_ave_initcode_atten0:10; + /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0; + * Average initcode of ADC1 atten0 + */ + uint32_t adc1_ave_initcode_atten1:5; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Represents rd_sys_part1_data5 + */ +typedef union { + struct { + /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0; + * Average initcode of ADC1 atten0 + */ + uint32_t adc1_ave_initcode_atten1_1:5; + /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0; + * Average initcode of ADC1 atten0 + */ + uint32_t adc1_ave_initcode_atten2:10; + /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0; + * Average initcode of ADC1 atten0 + */ + uint32_t adc1_ave_initcode_atten3:10; + /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; + * HI DOUT of ADC1 atten0 + */ + uint32_t adc1_hi_dout_atten0:7; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Represents rd_sys_part1_data6 + */ +typedef union { + struct { + /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; + * HI DOUT of ADC1 atten0 + */ + uint32_t adc1_hi_dout_atten0_1:3; + /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; + * HI DOUT of ADC1 atten1 + */ + uint32_t adc1_hi_dout_atten1:10; + /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; + * HI DOUT of ADC1 atten2 + */ + uint32_t adc1_hi_dout_atten2:10; + /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; + * HI DOUT of ADC1 atten3 + */ + uint32_t adc1_hi_dout_atten3:9; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Represents rd_sys_part1_data7 + */ +typedef union { + struct { + /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; + * HI DOUT of ADC1 atten3 + */ + uint32_t adc1_hi_dout_atten3_1:1; + /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; + * Gap between ADC1 CH0 and average initcode + */ + uint32_t adc1_ch0_atten0_initcode_diff:4; + /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; + * Gap between ADC1 CH1 and average initcode + */ + uint32_t adc1_ch1_atten0_initcode_diff:4; + /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; + * Gap between ADC1 CH2 and average initcode + */ + uint32_t adc1_ch2_atten0_initcode_diff:4; + /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; + * Gap between ADC1 CH3 and average initcode + */ + uint32_t adc1_ch3_atten0_initcode_diff:4; + /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0; + * Gap between ADC1 CH4 and average initcode + */ + uint32_t adc1_ch4_atten0_initcode_diff:4; + /** adc1_ch5_atten0_initcode_diff : R; bitpos: [24:21]; default: 0; + * Gap between ADC1 CH5 and average initcode + */ + uint32_t adc1_ch5_atten0_initcode_diff:4; + /** reserved_2_249 : R; bitpos: [31:25]; default: 0; + * reserved + */ + uint32_t reserved_2_249:7; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; /** Group: block3 registers */ /** Type of rd_usr_datan register @@ -3588,7 +3773,14 @@ typedef struct { volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];