From b16ed57b2e35f82ec1da4d95001a4f101e962aa5 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 13 Apr 2023 11:00:21 +0800 Subject: [PATCH 1/5] esp32h4: removed esp32h4 related files --- .../subproject/main/ld/esp32h4/bootloader.ld | 240 --- .../main/ld/esp32h4/bootloader.rom.ld | 6 - .../src/bootloader_random_esp32h4.c | 24 - components/efuse/esp32h4/esp_efuse_fields.c | 54 - .../efuse/esp32h4/esp_efuse_rtc_calib.c | 94 - components/efuse/esp32h4/esp_efuse_table.c | 1049 ---------- components/efuse/esp32h4/esp_efuse_table.csv | 156 -- components/efuse/esp32h4/esp_efuse_utility.c | 201 -- .../efuse/esp32h4/include/esp_efuse_chip.h | 79 - .../esp32h4/include/esp_efuse_rtc_calib.h | 55 - .../efuse/esp32h4/include/esp_efuse_table.h | 136 -- .../private_include/esp_efuse_utility.h | 21 - components/efuse/esp32h4/sources.cmake | 4 - .../esp32h4/include/adc_cali_schemes.h | 15 - components/esp_pm/include/esp32h4/pm.h | 13 - .../esp_rom/esp32h4/Kconfig.soc_caps.in | 60 - components/esp_rom/esp32h4/esp_rom_caps.h | 22 - .../esp32h4/ld/rev1/esp32h4.rom.api.ld | 63 - .../esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld | 723 ------- .../esp32h4/ld/rev1/esp32h4.rom.libgcc.ld | 111 -- .../ld/rev1/esp32h4.rom.newlib-nano.ld | 33 - .../esp32h4/ld/rev1/esp32h4.rom.newlib.ld | 96 - .../esp32h4/ld/rev1/esp32h4.rom.version.ld | 14 - .../esp32h4/ld/rev2/esp32h4.rom.api.ld | 62 - .../esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld | 1707 ----------------- .../esp32h4/ld/rev2/esp32h4.rom.libgcc.ld | 112 -- .../ld/rev2/esp32h4.rom.newlib-nano.ld | 47 - .../esp32h4/ld/rev2/esp32h4.rom.newlib.ld | 143 -- .../esp32h4/ld/rev2/esp32h4.rom.version.ld | 13 - components/esp_rom/include/esp32h4/rom/aes.h | 46 - .../include/esp32h4/rom/apb_backup_dma.h | 17 - .../esp_rom/include/esp32h4/rom/bigint.h | 35 - .../esp_rom/include/esp32h4/rom/cache.h | 750 -------- components/esp_rom/include/esp32h4/rom/crc.h | 119 -- .../include/esp32h4/rom/digital_signature.h | 142 -- .../esp_rom/include/esp32h4/rom/efuse.h | 337 ---- .../esp_rom/include/esp32h4/rom/esp_flash.h | 46 - .../esp_rom/include/esp32h4/rom/ets_sys.h | 466 ----- components/esp_rom/include/esp32h4/rom/gpio.h | 215 --- components/esp_rom/include/esp32h4/rom/hmac.h | 55 - .../esp_rom/include/esp32h4/rom/libc_stubs.h | 96 - .../esp_rom/include/esp32h4/rom/lldesc.h | 132 -- .../esp_rom/include/esp32h4/rom/md5_hash.h | 43 - .../esp_rom/include/esp32h4/rom/miniz.h | 8 - .../esp_rom/include/esp32h4/rom/rom_layout.h | 51 - .../esp_rom/include/esp32h4/rom/rsa_pss.h | 38 - components/esp_rom/include/esp32h4/rom/rtc.h | 251 --- .../esp_rom/include/esp32h4/rom/secure_boot.h | 105 - components/esp_rom/include/esp32h4/rom/sha.h | 53 - .../esp_rom/include/esp32h4/rom/spi_flash.h | 458 ----- .../esp_rom/include/esp32h4/rom/tjpgd.h | 105 - components/esp_rom/include/esp32h4/rom/uart.h | 343 ---- components/esp_system/ld/esp32h4/memory.ld.in | 121 -- .../esp_system/ld/esp32h4/sections.ld.in | 422 ---- .../port/soc/esp32h4/CMakeLists.txt | 13 - .../esp_system/port/soc/esp32h4/Kconfig.cpu | 27 - .../port/soc/esp32h4/Kconfig.system | 45 - .../port/soc/esp32h4/apb_backup_dma.c | 40 - .../port/soc/esp32h4/cache_err_int.c | 78 - components/esp_system/port/soc/esp32h4/clk.c | 286 --- .../port/soc/esp32h4/reset_reason.c | 114 -- .../port/soc/esp32h4/system_internal.c | 101 - components/heap/port/esp32h4/memory_layout.c | 107 -- .../include/esp32h4/idf_performance_target.h | 37 - components/mbedtls/port/esp32h4/bignum.c | 229 --- .../ble/ble_ancs/sdkconfig.defaults.esp32h4 | 8 - .../sdkconfig.defaults.esp32h4 | 10 - .../ble_eddystone/sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../ble_ibeacon/sdkconfig.defaults.esp32h4 | 10 - .../ble_spp_client/sdkconfig.defaults.esp32h4 | 10 - .../ble_spp_server/sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../gatt_client/sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../gatt_server/sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 7 - .../sdkconfig.defaults.esp32h4 | 7 - .../multi-adv/sdkconfig.defaults.esp32h4 | 7 - .../peroidic_adv/sdkconfig.defaults.esp32h4 | 7 - .../peroidic_sync/sdkconfig.defaults.esp32h4 | 7 - .../nimble/blecent/sdkconfig.defaults.esp32h4 | 10 - .../nimble/bleprph/sdkconfig.defaults.esp32h4 | 8 - .../sdkconfig.defaults.esp32h4 | 10 - .../sdkconfig.defaults.esp32h4 | 10 - .../env_caps/esp32h4/Kconfig.env_caps | 15 - tools/cmake/toolchain-esp32h4.cmake | 18 - 91 files changed, 11138 deletions(-) delete mode 100644 components/bootloader/subproject/main/ld/esp32h4/bootloader.ld delete mode 100644 components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld delete mode 100644 components/bootloader_support/src/bootloader_random_esp32h4.c delete mode 100644 components/efuse/esp32h4/esp_efuse_fields.c delete mode 100644 components/efuse/esp32h4/esp_efuse_rtc_calib.c delete mode 100644 components/efuse/esp32h4/esp_efuse_table.c delete mode 100644 components/efuse/esp32h4/esp_efuse_table.csv delete mode 100644 components/efuse/esp32h4/esp_efuse_utility.c delete mode 100644 components/efuse/esp32h4/include/esp_efuse_chip.h delete mode 100644 components/efuse/esp32h4/include/esp_efuse_rtc_calib.h delete mode 100644 components/efuse/esp32h4/include/esp_efuse_table.h delete mode 100644 components/efuse/esp32h4/private_include/esp_efuse_utility.h delete mode 100644 components/efuse/esp32h4/sources.cmake delete mode 100644 components/esp_adc/esp32h4/include/adc_cali_schemes.h delete mode 100644 components/esp_pm/include/esp32h4/pm.h delete mode 100644 components/esp_rom/esp32h4/Kconfig.soc_caps.in delete mode 100644 components/esp_rom/esp32h4/esp_rom_caps.h delete mode 100644 components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld delete mode 100644 components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld delete mode 100644 components/esp_rom/include/esp32h4/rom/aes.h delete mode 100644 components/esp_rom/include/esp32h4/rom/apb_backup_dma.h delete mode 100644 components/esp_rom/include/esp32h4/rom/bigint.h delete mode 100644 components/esp_rom/include/esp32h4/rom/cache.h delete mode 100644 components/esp_rom/include/esp32h4/rom/crc.h delete mode 100644 components/esp_rom/include/esp32h4/rom/digital_signature.h delete mode 100644 components/esp_rom/include/esp32h4/rom/efuse.h delete mode 100644 components/esp_rom/include/esp32h4/rom/esp_flash.h delete mode 100644 components/esp_rom/include/esp32h4/rom/ets_sys.h delete mode 100644 components/esp_rom/include/esp32h4/rom/gpio.h delete mode 100644 components/esp_rom/include/esp32h4/rom/hmac.h delete mode 100644 components/esp_rom/include/esp32h4/rom/libc_stubs.h delete mode 100644 components/esp_rom/include/esp32h4/rom/lldesc.h delete mode 100644 components/esp_rom/include/esp32h4/rom/md5_hash.h delete mode 100644 components/esp_rom/include/esp32h4/rom/miniz.h delete mode 100644 components/esp_rom/include/esp32h4/rom/rom_layout.h delete mode 100644 components/esp_rom/include/esp32h4/rom/rsa_pss.h delete mode 100644 components/esp_rom/include/esp32h4/rom/rtc.h delete mode 100644 components/esp_rom/include/esp32h4/rom/secure_boot.h delete mode 100644 components/esp_rom/include/esp32h4/rom/sha.h delete mode 100644 components/esp_rom/include/esp32h4/rom/spi_flash.h delete mode 100644 components/esp_rom/include/esp32h4/rom/tjpgd.h delete mode 100644 components/esp_rom/include/esp32h4/rom/uart.h delete mode 100644 components/esp_system/ld/esp32h4/memory.ld.in delete mode 100644 components/esp_system/ld/esp32h4/sections.ld.in delete mode 100644 components/esp_system/port/soc/esp32h4/CMakeLists.txt delete mode 100644 components/esp_system/port/soc/esp32h4/Kconfig.cpu delete mode 100644 components/esp_system/port/soc/esp32h4/Kconfig.system delete mode 100644 components/esp_system/port/soc/esp32h4/apb_backup_dma.c delete mode 100644 components/esp_system/port/soc/esp32h4/cache_err_int.c delete mode 100644 components/esp_system/port/soc/esp32h4/clk.c delete mode 100644 components/esp_system/port/soc/esp32h4/reset_reason.c delete mode 100644 components/esp_system/port/soc/esp32h4/system_internal.c delete mode 100644 components/heap/port/esp32h4/memory_layout.c delete mode 100644 components/idf_test/include/esp32h4/idf_performance_target.h delete mode 100644 components/mbedtls/port/esp32h4/bignum.c delete mode 100644 examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 delete mode 100644 examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 delete mode 100644 examples/common_components/env_caps/esp32h4/Kconfig.env_caps delete mode 100644 tools/cmake/toolchain-esp32h4.cmake diff --git a/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld deleted file mode 100644 index 75c7d6a8fa..0000000000 --- a/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld +++ /dev/null @@ -1,240 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/** Simplified memory map for the bootloader. - * Make sure the bootloader can load into main memory without overwriting itself. - * - * ESP32-H4 ROM static data usage is as follows: - * - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only - * - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup - * - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) - * - * The 2nd stage bootloader can take space up to the end of ROM shared - * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). - */ - -/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ -iram_dram_offset = 0x700000; - -/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, - * and work out iram_seg and iram_loader_seg addresses from there, backwards. - */ - -/* These lengths can be adjusted, if necessary: */ -bootloader_usable_dram_end = 0x3fcdd120; -bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ -bootloader_dram_seg_len = 0x5000; -bootloader_iram_loader_seg_len = 0x7000; -bootloader_iram_seg_len = 0x2000; - -/* Start of the lower region is determined by region size and the end of the higher region */ -bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; -bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; -bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; -bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; - -MEMORY -{ - iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len - iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len - dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len -} - -/* Default entry point: */ -ENTRY(call_start_cpu0); - -SECTIONS -{ - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *liblog.a:(.literal .text .literal.* .text.*) - *libgcc.a:(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) - *libspi_flash.a:*.*(.literal .text .literal.* .text.*) - *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libhal.a:cache_hal.*(.literal .text .literal.* .text.*) - *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) - *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) - *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) - *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) - *libefuse.a:*.*(.literal .text .literal.* .text.*) - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - .iram.text : - { - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - } > iram_seg - - - /* Shared RAM */ - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _dram_start = ABSOLUTE(.); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } > dram_seg - - .dram0.data : - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - _data_end = ABSOLUTE(.); - } > dram_seg - - .dram0.rodata : - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - *(.sdata2 .sdata2.* .srodata .srodata.*) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - *(.eh_frame) - . = (. + 3) & ~ 3; - /* C++ constructor and destructor tables, properly ordered: */ - __init_array_start = ABSOLUTE(.); - KEEP (*crtbegin.*(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __init_array_end = ABSOLUTE(.); - KEEP (*crtbegin.*(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _rodata_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - _dram_end = ABSOLUTE(.); - } > dram_seg - - .iram.text : - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram .iram.*) /* catch stray IRAM_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /** CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - } > iram_seg - -} - -/** - * Appendix: Memory Usage of ROM bootloader - * - * 0x3fccb81c ------------------> _dram0_0_start - * | | - * | | - * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h - * | | - * | | - * 0x3fcdd120 ------------------> __stack_sentry - * | | - * | | 2. Startup pro cpu stack (freed when IDF app is running) - * | | - * 0x3fcdf120 ------------------> __stack (pro cpu) - * | | - * | | - * | | 3. Shared memory only used in startup code or nonos/early boot* - * | | (can be freed when IDF runs) - * | | - * | | - * 0x3fcdfa6c ------------------> _dram0_rtos_reserved_start - * | | - * | | - * | | 4. Shared memory used in startup code and when IDF runs - * | | - * | | - * 0x3fcdfe40 ------------------> _dram0_rtos_reserved_end - * | | - * 0x3fcdfe4c ------------------> _data_start_interface - * | | - * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) - * | | - * 0x3fce0000 ------------------> _data_end_interface - */ diff --git a/components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld deleted file mode 100644 index 34156bcc91..0000000000 --- a/components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld +++ /dev/null @@ -1,6 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* No definition for ESP32-H4 target */ diff --git a/components/bootloader_support/src/bootloader_random_esp32h4.c b/components/bootloader_support/src/bootloader_random_esp32h4.c deleted file mode 100644 index 2d3d086871..0000000000 --- a/components/bootloader_support/src/bootloader_random_esp32h4.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "sdkconfig.h" -#include "bootloader_random.h" -#include "esp_log.h" -#include "soc/syscon_reg.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/apb_saradc_reg.h" -#include "soc/system_reg.h" -#include "esp_private/regi2c_ctrl.h" - -// ESP32H4-TODO: IDF-3381 -void bootloader_random_enable(void) -{ - -} - -void bootloader_random_disable(void) -{ - -} diff --git a/components/efuse/esp32h4/esp_efuse_fields.c b/components/efuse/esp32h4/esp_efuse_fields.c deleted file mode 100644 index a22003560c..0000000000 --- a/components/efuse/esp32h4/esp_efuse_fields.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_efuse.h" -#include "esp_efuse_utility.h" -#include "esp_efuse_table.h" -#include "stdlib.h" -#include "esp_types.h" -#include "esp32h4/rom/efuse.h" -#include "assert.h" -#include "esp_err.h" -#include "esp_log.h" -#include "soc/efuse_periph.h" -#include "sys/param.h" - -static __attribute__((unused)) const char *TAG = "efuse"; - -// Contains functions that provide access to efuse fields which are often used in IDF. - -// Returns chip package from efuse -uint32_t esp_efuse_get_pkg_ver(void) -{ - uint32_t pkg_ver = 0; - esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); - return pkg_ver; -} - - -esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) -{ - int cur_log_scheme = 0; - esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2); - if (!cur_log_scheme) { // not burned yet - return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2); - } else { - return ESP_ERR_INVALID_STATE; - } -} - -esp_err_t esp_efuse_disable_rom_download_mode(void) -{ - return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE); -} - -esp_err_t esp_efuse_enable_rom_secure_download_mode(void) -{ - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; - } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); -} diff --git a/components/efuse/esp32h4/esp_efuse_rtc_calib.c b/components/efuse/esp32h4/esp_efuse_rtc_calib.c deleted file mode 100644 index 5bfd20b019..0000000000 --- a/components/efuse/esp32h4/esp_efuse_rtc_calib.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "esp_efuse.h" -#include "esp_efuse_table.h" - -int esp_efuse_rtc_calib_get_ver(void) -{ - uint32_t result = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3); - return result; -} - -uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten) -{ - assert(version == 1); - const esp_efuse_desc_t** init_code_efuse; - assert(atten < 4); - if (atten == 0) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; - } else if (atten == 1) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; - } else if (atten == 2) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; - } else { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; - } - - int init_code_size = esp_efuse_get_field_size(init_code_efuse); - assert(init_code_size == 10); - - uint32_t init_code = 0; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size)); - return init_code + 1000; // version 1 logic -} - -esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) -{ - const esp_efuse_desc_t** cal_vol_efuse; - uint32_t calib_vol_expected_mv; - if (version != 1) { - return ESP_ERR_INVALID_ARG; - } - if (atten >= 4) { - return ESP_ERR_INVALID_ARG; - } - if (atten == 0) { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0; - calib_vol_expected_mv = 400; - } else if (atten == 1) { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1; - calib_vol_expected_mv = 550; - } else if (atten == 2) { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2; - calib_vol_expected_mv = 750; - } else { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3; - calib_vol_expected_mv = 1370; - } - - assert(cal_vol_efuse[0]->bit_count == 10); - - uint32_t cal_vol = 0; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count)); - - *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol); - *out_vol_mv = calib_vol_expected_mv; - return ESP_OK; -} - -esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) -{ - uint32_t version = esp_efuse_rtc_calib_get_ver(); - if (version != 1) { - *tsens_cal = 0.0; - return ESP_ERR_NOT_SUPPORTED; - } - const esp_efuse_desc_t** cal_temp_efuse; - cal_temp_efuse = ESP_EFUSE_TEMP_CALIB; - int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse); - assert(cal_temp_size == 9); - - uint32_t cal_temp = 0; - esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size); - assert(err == ESP_OK); - (void)err; - // BIT(8) stands for sign: 1: negtive, 0: positive - *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp; - return ESP_OK; -} diff --git a/components/efuse/esp32h4/esp_efuse_table.c b/components/efuse/esp32h4/esp_efuse_table.c deleted file mode 100644 index dd5f5a9f20..0000000000 --- a/components/efuse/esp32h4/esp_efuse_table.c +++ /dev/null @@ -1,1049 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sdkconfig.h" -#include "esp_efuse.h" -#include -#include "esp_efuse_table.h" - -// md5_digest_table 4561606695cfe94477d259619fd723ef -// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. -// If you want to change some fields, you need to change esp_efuse_table.csv file -// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. -// To show efuse_table run the command 'show_efuse_table'. - -static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 32}, // Write protection, -}; - -static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, -}; - -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, -}; - -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL, -}; - -static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, -}; - -static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { - {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, -}; - -static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, -}; - -static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { - {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, -}; - -static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { - {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, -}; - -static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { - {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, -}; - -static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { - {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, -}; - -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, -}; - -static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, -}; - -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, -}; - -static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { - {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, -}; - -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, -}; - -static const esp_efuse_desc_t WR_DIS_KEY1[] = { - {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, -}; - -static const esp_efuse_desc_t WR_DIS_KEY2[] = { - {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, -}; - -static const esp_efuse_desc_t WR_DIS_KEY3[] = { - {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, -}; - -static const esp_efuse_desc_t WR_DIS_KEY4[] = { - {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, -}; - -static const esp_efuse_desc_t WR_DIS_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, -}; - -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // Read protection, -}; - -static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, -}; - -static const esp_efuse_desc_t RD_DIS_KEY1[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, -}; - -static const esp_efuse_desc_t RD_DIS_KEY2[] = { - {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, -}; - -static const esp_efuse_desc_t RD_DIS_KEY3[] = { - {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, -}; - -static const esp_efuse_desc_t RD_DIS_KEY4[] = { - {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, -}; - -static const esp_efuse_desc_t RD_DIS_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, -}; - -static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // Disable Icache, -}; - -static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // Disable USB JTAG, -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode, -}; - -static const esp_efuse_desc_t DIS_USB_DEVICE[] = { - {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE, -}; - -static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, -}; - -static const esp_efuse_desc_t DIS_TWAI[] = { - {EFUSE_BLK0, 46, 1}, // Disable TWAI function, -}; - -static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., -}; - -static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., -}; - -static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., -}; - -static const esp_efuse_desc_t USB_DREFH[] = { - {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., -}; - -static const esp_efuse_desc_t USB_DREFL[] = { - {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., -}; - -static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, -}; - -static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio, -}; - -static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { - {EFUSE_BLK0, 59, 2}, // Enable btlc gpio, -}; - -static const esp_efuse_desc_t POWERGLITCH_EN[] = { - {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function, -}; - -static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = { - {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch, -}; - -static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, -}; - -static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // Key0 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // Key1 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // Key2 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // Key3 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // Key4 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // Key5 purpose, -}; - -static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // Secure boot enable, -}; - -static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, -}; - -static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, -}; - -static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // Disable usb serial jtag print during rom boot, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Disable download through USB-Serial-JTAG, -}; - -static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, -}; - -static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print., -}; - -static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, -}; - -static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, -}; - -static const esp_efuse_desc_t BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 158, 1}, // Fast verify on wake option in ROM for Secure Boot, -}; - -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], -}; - -static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 123, 8}, // Extend MAC addr [0], - {EFUSE_BLK1, 131, 8}, // Extend MAC addr [1], -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, -}; - -static const esp_efuse_desc_t WAFER_VERSION[] = { - {EFUSE_BLK1, 114, 3}, // WAFER version, -}; - -static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32H4, -}; - -static const esp_efuse_desc_t BLOCK1_VERSION[] = { - {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version, -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t BLOCK2_VERSION[] = { - {EFUSE_BLK2, 128, 3}, // Version of BLOCK2, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 131, 9}, // Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 140, 8}, // ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK3, 0, 256}, // User data, -}; - -static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // Custom MAC, -}; - -static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK4, 0, 256}, // Key0 or user data, -}; - -static const esp_efuse_desc_t KEY1[] = { - {EFUSE_BLK5, 0, 256}, // Key1 or user data, -}; - -static const esp_efuse_desc_t KEY2[] = { - {EFUSE_BLK6, 0, 256}, // Key2 or user data, -}; - -static const esp_efuse_desc_t KEY3[] = { - {EFUSE_BLK7, 0, 256}, // Key3 or user data, -}; - -static const esp_efuse_desc_t KEY4[] = { - {EFUSE_BLK8, 0, 256}, // Key4 or user data, -}; - -static const esp_efuse_desc_t KEY5[] = { - {EFUSE_BLK9, 0, 256}, // Key5 or user data, -}; - -static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK10, 0, 256}, // System configuration, -}; - - - - - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { - &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { - &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { - &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { - &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { - &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { - &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { - &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { - &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { - &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { - &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { - &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { - &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { - &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { - &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { - &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { - &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { - &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { - &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { - &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { - &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { - &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // Disable Icache - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // Disable USB JTAG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = { - &DIS_USB_DEVICE[0], // Disable USB_DEVICE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { - &DIS_TWAI[0], // Disable TWAI function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { - &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { - &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // Exchange D+ D- pins - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { - &BTLC_GPIO_ENABLE[0], // Enable btlc gpio - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { - &POWERGLITCH_EN[0], // Set this bit to enable power glitch function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = { - &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { - &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { - &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { - &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // Key0 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // Key1 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // Key2 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // Key3 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // Key4 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // Key5 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Secure boot enable - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // Disable direct boot mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Disable usb serial jtag print during rom boot - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Disable download through USB-Serial-JTAG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[] = { - &BOOT_DISABLE_FAST_WAKE[0], // Fast verify on wake option in ROM for Secure Boot - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // Extend MAC addr [0] - &MAC_EXT[1], // Extend MAC addr [1] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { - &WAFER_VERSION[0], // WAFER version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version 0:ESP32H4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { - &BLOCK1_VERSION[0], // BLOCK1 efuse version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { - &BLOCK2_VERSION[0], // Version of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // Key0 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { - &KEY1[0], // Key1 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { - &KEY2[0], // Key2 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { - &KEY3[0], // Key3 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { - &KEY4[0], // Key4 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { - &KEY5[0], // Key5 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // System configuration - NULL -}; diff --git a/components/efuse/esp32h4/esp_efuse_table.csv b/components/efuse/esp32h4/esp_efuse_table.csv deleted file mode 100644 index cd94d46d37..0000000000 --- a/components/efuse/esp32h4/esp_efuse_table.csv +++ /dev/null @@ -1,156 +0,0 @@ -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1..-) | # -# | EFUSE_BLK1 | |MAX_BLK_LEN*| # -# | ... | | | # -# | EFUSE_BLK10)| | | # -########################################################################## -# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. -# !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# ESP32H4-TODO: IDF-3390 -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 32, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE - WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT - WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 - WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 - WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 - WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 - WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 - WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 - WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 - WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 - WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 - WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN - WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 - WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA - WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 - WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 - WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 - WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 - WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 - WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 - WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 - - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 7, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 - RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 - RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 - RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 - RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 - RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 - RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache - DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode - DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE - DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function - DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function - JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. - SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. - DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. - USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. - USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins - VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio - BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio - POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function - POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch - - # EFUSE_RD_REPEAT_DATA1_REG # - WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key - SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key - SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key - KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose - KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose - - # EFUSE_RD_REPEAT_DATA2_REG # - KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose - KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose - KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose - KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable - SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke - FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - - # EFUSE_RD_REPEAT_DATA3_REG # - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode - DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Disable download through USB-Serial-JTAG - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode - UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. - FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot - SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback - BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Fast verify on wake option in ROM for Secure Boot - - # EFUSE_RD_REPEAT_DATA4_REG # - - -# MAC_SPI_SYS BLOCK# -####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - MAC_EXT, EFUSE_BLK1, 123, 8, Extend MAC addr [0] - , EFUSE_BLK1, 131, 8, Extend MAC addr [1] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version - PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H4 - BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2 - TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data - OCODE, EFUSE_BLK2, 140, 8, ADC OCode - ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 - ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 - ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 - ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 - ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 - ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 - ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 - ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 - -################ -USER_DATA, EFUSE_BLK3, 0, 256, User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC - -################ -KEY0, EFUSE_BLK4, 0, 256, Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration diff --git a/components/efuse/esp32h4/esp_efuse_utility.c b/components/efuse/esp32h4/esp_efuse_utility.c deleted file mode 100644 index 7ce412a8da..0000000000 --- a/components/efuse/esp32h4/esp_efuse_utility.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdkconfig.h" -#include "esp_log.h" -#include "assert.h" -#include "esp_efuse_utility.h" -#include "soc/efuse_periph.h" -#include "hal/efuse_hal.h" - -static const char *TAG = "efuse"; - -#ifdef CONFIG_EFUSE_VIRTUAL -extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; -#endif // CONFIG_EFUSE_VIRTUAL - -/*Range addresses to read blocks*/ -const esp_efuse_range_addr_t range_read_addr_blocks[] = { - {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT - {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M - {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA - {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA - {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 - {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 - {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 - {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 - {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 - {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 - {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 -}; - -static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; - -/*Range addresses to write blocks (it is not real regs, it is buffer) */ -const esp_efuse_range_addr_t range_write_addr_blocks[] = { - {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, -}; - -#ifndef CONFIG_EFUSE_VIRTUAL -// Update Efuse timing configuration -static esp_err_t esp_efuse_set_timing(void) -{ - // efuse clock is fixed. - // An argument (0) is for compatibility and will be ignored. - efuse_hal_set_timing(0); - return ESP_OK; -} -#endif // ifndef CONFIG_EFUSE_VIRTUAL - -// Efuse read operation: copies data from physical efuses to efuse read registers. -void esp_efuse_utility_clear_program_registers(void) -{ - efuse_hal_read(); - efuse_hal_clear_program_registers(); -} - -esp_err_t esp_efuse_utility_check_errors(void) -{ - return ESP_OK; -} - -// Burn values written to the efuse write registers -esp_err_t esp_efuse_utility_burn_chip(void) -{ - esp_err_t error = ESP_OK; -#ifdef CONFIG_EFUSE_VIRTUAL - ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); - for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { - int subblock = 0; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); - } - } -#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - esp_efuse_utility_write_efuses_to_flash(); -#endif -#else // CONFIG_EFUSE_VIRTUAL - if (esp_efuse_set_timing() != ESP_OK) { - ESP_LOGE(TAG, "Efuse fields are not burnt"); - } else { - // Permanently update values written to the efuse write registers - // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. - for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { - bool need_burn_block = false; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - if (REG_READ(addr_wr_block) != 0) { - need_burn_block = true; - break; - } - } - if (!need_burn_block) { - continue; - } - if (error) { - // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) - // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. - ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); - continue; - } - efuse_hal_clear_program_registers(); - if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { - uint8_t block_rs[12]; - efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); - hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); - } - unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); - unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); - memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); - - uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data - hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); - int repeat_burn_op = 1; - bool correct_written_data; - bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block); - if (coding_error_before) { - ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); - } - bool coding_error_occurred; - - do { - ESP_LOGI(TAG, "BURN BLOCK%d", num_block); - efuse_hal_program(num_block); // BURN a block - - bool coding_error_after; - for (unsigned i = 0; i < 5; i++) { - efuse_hal_read(); - coding_error_after = efuse_hal_is_coding_error_in_block(num_block); - if (coding_error_after == true) { - break; - } - } - coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false; - if (coding_error_occurred) { - ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); - } - - correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len); - if (!correct_written_data || coding_error_occurred) { - ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); - hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); - } - - } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); - - if (coding_error_occurred) { - ESP_LOGW(TAG, "Coding error was not fixed"); - if (num_block == 0) { - ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); - error = ESP_FAIL; - } - } - if (!correct_written_data) { - ESP_LOGE(TAG, "Written data are incorrect"); - error = ESP_FAIL; - } - } - } -#endif // CONFIG_EFUSE_VIRTUAL - esp_efuse_utility_reset(); - return error; -} - -// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. -// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. -// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. -// They will be filled during the burn operation. -esp_err_t esp_efuse_utility_apply_new_coding_scheme() -{ - // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. - for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { - if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - if (REG_READ(addr_wr_block)) { - int num_reg = 0; - for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { - if (esp_efuse_utility_read_reg(num_block, num_reg)) { - ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); - return ESP_ERR_CODING; - } - } - break; - } - } - } - } - return ESP_OK; -} diff --git a/components/efuse/esp32h4/include/esp_efuse_chip.h b/components/efuse/esp32h4/include/esp_efuse_chip.h deleted file mode 100644 index c5a67663c1..0000000000 --- a/components/efuse/esp32h4/include/esp_efuse_chip.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Type of eFuse blocks ESP32H4 - */ -typedef enum { - EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ - - EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ - - EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ - EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ - - EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ - EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ - - EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ - EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ - - EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ - EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ - - EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ - EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ - - EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ - EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ - - EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ - EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ - - EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ - EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ - EFUSE_BLK_KEY_MAX = 10, - - EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ - EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ - - EFUSE_BLK_MAX -} esp_efuse_block_t; - -/** - * @brief Type of coding scheme - */ -typedef enum { - EFUSE_CODING_SCHEME_NONE = 0, /**< None */ - EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ -} esp_efuse_coding_scheme_t; - -/** - * @brief Type of key purpose - */ -typedef enum { - ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ - ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ - ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ -} esp_efuse_purpose_t; - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/include/esp_efuse_rtc_calib.h b/components/efuse/esp32h4/include/esp_efuse_rtc_calib.h deleted file mode 100644 index e495669710..0000000000 --- a/components/efuse/esp32h4/include/esp_efuse_rtc_calib.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get the RTC calibration efuse version - * - * @return Version of the stored efuse - */ -int esp_efuse_rtc_calib_get_ver(void); - -/** - * @brief Get the init code in the efuse, for the corresponding attenuation. - * - * @param version Version of the stored efuse - * @param atten Attenuation of the init code - * @return The init code stored in efuse - */ -uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten); - -/** - * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. - * - * @param version Version of the stored efuse - * @param atten Attenuation to use - * @param out_digi Output buffer of the digits - * @param out_vol_mv Output of the voltage, in mV - * @return - * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid - * - ESP_OK: if success - */ -esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); - -/** - * @brief Get the temperature sensor calibration number delta_T stored in the efuse. - * - * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse. - * - * @return ESP_OK if get the calibration value successfully. - * ESP_ERR_INVALID_ARG if can't get the calibration value. - */ -esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal); - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/include/esp_efuse_table.h b/components/efuse/esp32h4/include/esp_efuse_table.h deleted file mode 100644 index 402f995278..0000000000 --- a/components/efuse/esp32h4/include/esp_efuse_table.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "esp_efuse.h" - -// md5_digest_table 4561606695cfe94477d259619fd723ef -// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. -// If you want to change some fields, you need to change esp_efuse_table.csv file -// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. -// To show efuse_table run the command 'show_efuse_table'. - - -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; -extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/private_include/esp_efuse_utility.h b/components/efuse/esp32h4/private_include/esp_efuse_utility.h deleted file mode 100644 index 37573eea8f..0000000000 --- a/components/efuse/esp32h4/private_include/esp_efuse_utility.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ - -#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 - -#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/sources.cmake b/components/efuse/esp32h4/sources.cmake deleted file mode 100644 index 9dffd72008..0000000000 --- a/components/efuse/esp32h4/sources.cmake +++ /dev/null @@ -1,4 +0,0 @@ -set(EFUSE_SOC_SRCS "esp_efuse_table.c" - "esp_efuse_fields.c" - "esp_efuse_rtc_calib.c" - "esp_efuse_utility.c") diff --git a/components/esp_adc/esp32h4/include/adc_cali_schemes.h b/components/esp_adc/esp32h4/include/adc_cali_schemes.h deleted file mode 100644 index 2505fb46f6..0000000000 --- a/components/esp_adc/esp32h4/include/adc_cali_schemes.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file adc_cali_schemes.h - * - * @brief Supported calibration schemes - */ - -//Now no scheme supported diff --git a/components/esp_pm/include/esp32h4/pm.h b/components/esp_pm/include/esp32h4/pm.h deleted file mode 100644 index 1078f77812..0000000000 --- a/components/esp_pm/include/esp32h4/pm.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -#warning "esp_pm_config_esp32h4_t is deprecated, please include esp_pm.h and use esp_pm_config_t instead" - -/* backward compatibility */ -#include "esp_pm.h" diff --git a/components/esp_rom/esp32h4/Kconfig.soc_caps.in b/components/esp_rom/esp32h4/Kconfig.soc_caps.in deleted file mode 100644 index b8f83cc125..0000000000 --- a/components/esp_rom/esp32h4/Kconfig.soc_caps.in +++ /dev/null @@ -1,60 +0,0 @@ -##################################################### -# This file is auto-generated from SoC caps -# using gen_soc_caps_kconfig.py, do not edit manually -##################################################### - -config ESP_ROM_HAS_CRC_LE - bool - default y - -config ESP_ROM_HAS_CRC_BE - bool - default y - -config ESP_ROM_HAS_MZ_CRC32 - bool - default y - -config ESP_ROM_HAS_JPEG_DECODE - bool - default y - -config ESP_ROM_UART_CLK_IS_XTAL - bool - default y - -config ESP_ROM_USB_SERIAL_DEVICE_NUM - int - default 3 - -config ESP_ROM_HAS_RETARGETABLE_LOCKING - bool - default y - -config ESP_ROM_HAS_ERASE_0_REGION_BUG - bool - default y - -config ESP_ROM_GET_CLK_FREQ - bool - default y - -config ESP_ROM_HAS_LAYOUT_TABLE - bool - default y - -config ESP_ROM_HAS_ETS_PRINTF_BUG - bool - default y - -config ESP_ROM_HAS_NEWLIB_NANO_FORMAT - bool - default y - -config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE - bool - default y - -config ESP_ROM_RAM_APP_NEEDS_MMU_INIT - bool - default y diff --git a/components/esp_rom/esp32h4/esp_rom_caps.h b/components/esp_rom/esp32h4/esp_rom_caps.h deleted file mode 100644 index 30336691dc..0000000000 --- a/components/esp_rom/esp32h4/esp_rom_caps.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian -#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian -#define ESP_ROM_HAS_MZ_CRC32 (1) // ROM has mz_crc32 function -#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM -#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. -#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking -#define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug -#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` -#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table -#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register -#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions -#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap -#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld deleted file mode 100644 index b22f07d47d..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** ROM APIs - */ -PROVIDE ( esp_rom_crc32_le = crc32_le ); -PROVIDE ( esp_rom_crc16_le = crc16_le ); -PROVIDE ( esp_rom_crc8_le = crc8_le ); -PROVIDE ( esp_rom_crc32_be = crc32_be ); -PROVIDE ( esp_rom_crc16_be = crc16_be ); -PROVIDE ( esp_rom_crc8_be = crc8_be ); - -PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); -PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); -PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); -PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); -PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); -PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); - -PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); -PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); -PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); -PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); - -PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); -PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); -PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); -PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); -PROVIDE ( esp_rom_uart_rx_string = UartRxString ); -PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); -PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - -PROVIDE ( esp_rom_md5_init = MD5Init ); -PROVIDE ( esp_rom_md5_update = MD5Update ); -PROVIDE ( esp_rom_md5_final = MD5Final ); - -PROVIDE ( esp_rom_software_reset_system = software_reset ); -PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); - -PROVIDE ( esp_rom_printf = ets_printf ); -PROVIDE ( esp_rom_delay_us = ets_delay_us ); -PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); -PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); -PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); -PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); - -PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); -PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); -PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable); -PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); - -PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); -PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); -PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); -PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld deleted file mode 100644 index ffad80955c..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld +++ /dev/null @@ -1,723 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group common - ***************************************/ - -/* Functions */ -rtc_get_reset_reason = 0x40000018; -analog_super_wdt_reset_happened = 0x4000001c; -jtag_cpu_reset_happened = 0x40000020; -rtc_get_wakeup_cause = 0x40000024; -rtc_select_apb_bridge = 0x40000028; -rtc_unhold_all_pads = 0x4000002c; -ets_is_print_boot = 0x40000030; -ets_printf = 0x40000034; -ets_install_putc1 = 0x40000038; -ets_install_uart_printf = 0x4000003c; -ets_install_putc2 = 0x40000040; -PROVIDE( ets_delay_us = 0x40000044 ); -ets_get_stack_info = 0x40000048; -ets_install_lock = 0x4000004c; -ets_backup_dma_copy = 0x40000050; -ets_apb_backup_init_lock_func = 0x40000054; -UartRxString = 0x40000058; -uart_tx_one_char = 0x4000005c; -uart_tx_one_char2 = 0x40000060; -uart_rx_one_char = 0x40000064; -uart_rx_one_char_block = 0x40000068; -uart_rx_readbuff = 0x4000006c; -uartAttach = 0x40000070; -uart_tx_flush = 0x40000074; -uart_tx_wait_idle = 0x40000078; -uart_div_modify = 0x4000007c; -multofup = 0x40000080; -software_reset = 0x40000084; -software_reset_cpu = 0x40000088; -assist_debug_clock_enable = 0x4000008c; -assist_debug_record_enable = 0x40000090; -clear_super_wdt_reset_flag = 0x40000094; -disable_default_watchdog = 0x40000098; -esp_rom_set_rtc_wake_addr = 0x4000009c; -esp_rom_get_rtc_wake_addr = 0x400000a0; -send_packet = 0x400000a4; -recv_packet = 0x400000a8; -GetUartDevice = 0x400000ac; -UartDwnLdProc = 0x400000b0; -Uart_Init = 0x400000b4; -ets_set_user_start = 0x400000b8; -/* Data (.data, .bss, .rodata) */ -ets_rom_layout_p = 0x3ff1fffc; -ets_ops_table_ptr = 0x3fcdfffc; - - -/*************************************** - Group miniz - ***************************************/ - -/* Functions */ -mz_adler32 = 0x400000bc; -mz_crc32 = 0x400000c0; -mz_free = 0x400000c4; -tdefl_compress = 0x400000c8; -tdefl_compress_buffer = 0x400000cc; -tdefl_compress_mem_to_heap = 0x400000d0; -tdefl_compress_mem_to_mem = 0x400000d4; -tdefl_compress_mem_to_output = 0x400000d8; -tdefl_get_adler32 = 0x400000dc; -tdefl_get_prev_return_status = 0x400000e0; -tdefl_init = 0x400000e4; -tdefl_write_image_to_png_file_in_memory = 0x400000e8; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000ec; -tinfl_decompress = 0x400000f0; -tinfl_decompress_mem_to_callback = 0x400000f4; -tinfl_decompress_mem_to_heap = 0x400000f8; -tinfl_decompress_mem_to_mem = 0x400000fc; - - -/*************************************** - Group tjpgd - ***************************************/ - -/* Functions */ -PROVIDE( jd_prepare = 0x40000100 ); -PROVIDE( jd_decomp = 0x40000104 ); - - -/*************************************** - Group esp-dsp - ***************************************/ - -/* Data (.data, .bss, .rodata) */ -dsps_fft2r_w_table_fc32_1024 = 0x3fcdfff8; - - -/*************************************** - Group spiflash_legacy - ***************************************/ - -/* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x40000108 ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000010c ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000110 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000114 ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000118 ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x4000011c ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000120 ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x40000124 ); -PROVIDE( esp_rom_spiflash_write = 0x40000128 ); -PROVIDE( esp_rom_spiflash_read = 0x4000012c ); -PROVIDE( esp_rom_spiflash_config_param = 0x40000130 ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000134 ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000138 ); -PROVIDE( esp_rom_spiflash_unlock = 0x4000013c ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000140 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x40000144 ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000148 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x4000014c ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000150 ); -PROVIDE( esp_rom_spiflash_read_status = 0x40000154 ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000158 ); -PROVIDE( esp_rom_spiflash_write_status = 0x4000015c ); -PROVIDE( spi_flash_attach = 0x40000160 ); -PROVIDE( spi_flash_get_chip_size = 0x40000164 ); -PROVIDE( spi_flash_guard_set = 0x40000168 ); -PROVIDE( spi_flash_guard_get = 0x4000016c ); -PROVIDE( spi_flash_write_config_set = 0x40000170 ); -PROVIDE( spi_flash_write_config_get = 0x40000174 ); -PROVIDE( spi_flash_safe_write_address_func_set = 0x40000178 ); -PROVIDE( spi_flash_unlock = 0x4000017c ); -PROVIDE( spi_flash_erase_range = 0x40000180 ); -PROVIDE( spi_flash_erase_sector = 0x40000184 ); -PROVIDE( spi_flash_write = 0x40000188 ); -PROVIDE( spi_flash_read = 0x4000018c ); -PROVIDE( spi_flash_write_encrypted = 0x40000190 ); -PROVIDE( spi_flash_read_encrypted = 0x40000194 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x40000198 ); -PROVIDE( spi_flash_mmap_page_num_init = 0x4000019c ); -PROVIDE( spi_flash_mmap = 0x400001a0 ); -PROVIDE( spi_flash_mmap_pages = 0x400001a4 ); -PROVIDE( spi_flash_munmap = 0x400001a8 ); -PROVIDE( spi_flash_mmap_dump = 0x400001ac ); -PROVIDE( spi_flash_check_and_flush_cache = 0x400001b0 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b4 ); -PROVIDE( spi_flash_cache2phys = 0x400001b8 ); -PROVIDE( spi_flash_phys2cache = 0x400001bc ); -PROVIDE( spi_flash_disable_cache = 0x400001c0 ); -PROVIDE( spi_flash_restore_cache = 0x400001c4 ); -PROVIDE( spi_flash_cache_enabled = 0x400001c8 ); -PROVIDE( spi_flash_enable_cache = 0x400001cc ); -PROVIDE( spi_cache_mode_switch = 0x400001d0 ); -PROVIDE( spi_common_set_dummy_output = 0x400001d4 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001d8 ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001dc ); -PROVIDE( SPIEraseArea = 0x400001e0 ); -PROVIDE( SPILock = 0x400001e4 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001e8 ); -PROVIDE( SPI_Common_Command = 0x400001ec ); -PROVIDE( SPI_WakeUp = 0x400001f0 ); -PROVIDE( SPI_block_erase = 0x400001f4 ); -PROVIDE( SPI_chip_erase = 0x400001f8 ); -PROVIDE( SPI_init = 0x400001fc ); -PROVIDE( SPI_page_program = 0x40000200 ); -PROVIDE( SPI_read_data = 0x40000204 ); -PROVIDE( SPI_sector_erase = 0x40000208 ); -PROVIDE( SPI_write_enable = 0x4000020c ); -PROVIDE( SelectSpiFunction = 0x40000210 ); -PROVIDE( SetSpiDrvs = 0x40000214 ); -PROVIDE( Wait_SPI_Idle = 0x40000218 ); -PROVIDE( spi_dummy_len_fix = 0x4000021c ); -PROVIDE( Disable_QMode = 0x40000220 ); -PROVIDE( Enable_QMode = 0x40000224 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec ); -PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); - - -/*************************************** - Group hal_soc - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 ); -PROVIDE( spi_flash_hal_device_config = 0x4000022c ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 ); -PROVIDE( spi_flash_hal_common_command = 0x40000234 ); -PROVIDE( spi_flash_hal_read = 0x40000238 ); -PROVIDE( spi_flash_hal_erase_chip = 0x4000023c ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000240 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000244 ); -PROVIDE( spi_flash_hal_program_page = 0x40000248 ); -PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c ); -PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); - - -/*************************************** - Group spi_flash_chips - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000254 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000258 ); -PROVIDE( spi_flash_chip_generic_write = 0x4000025c ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000260 ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000264 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000268 ); -PROVIDE( spi_flash_chip_generic_reset = 0x4000026c ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000270 ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000274 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x40000278 ); -PROVIDE( spi_flash_chip_generic_page_program = 0x4000027c ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000280 ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000284 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x40000288 ); -PROVIDE( spi_flash_chip_generic_yield = 0x4000028c ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x40000290 ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000294 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000298 ); -PROVIDE( spi_flash_chip_generic_read = 0x4000029c ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a0 ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a4 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002a8 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002ac ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b0 ); -PROVIDE( spi_flash_common_set_io_mode = 0x400002b4 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002b8 ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002bc ); -PROVIDE( spi_flash_chip_gd_probe = 0x400002c0 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c4 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 ); - - -/*************************************** - Group memspi_host - ***************************************/ - -/* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x400002c8 ); -PROVIDE( memspi_host_read_status_hs = 0x400002cc ); -PROVIDE( memspi_host_flush_cache = 0x400002d0 ); -PROVIDE( memspi_host_erase_chip = 0x400002d4 ); -PROVIDE( memspi_host_erase_sector = 0x400002d8 ); -PROVIDE( memspi_host_erase_block = 0x400002dc ); -PROVIDE( memspi_host_program_page = 0x400002e0 ); -PROVIDE( memspi_host_read = 0x400002e4 ); -PROVIDE( memspi_host_set_write_protect = 0x400002e8 ); -PROVIDE( memspi_host_set_max_read_len = 0x400002ec ); -PROVIDE( memspi_host_read_data_slicer = 0x400002f0 ); -PROVIDE( memspi_host_write_data_slicer = 0x400002f4 ); - - -/*************************************** - Group esp_flash - ***************************************/ - -/* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x400002f8 ); -PROVIDE( esp_flash_read_id = 0x400002fc ); -PROVIDE( esp_flash_get_size = 0x40000300 ); -PROVIDE( esp_flash_erase_chip = 0x40000304 ); -PROVIDE( rom_esp_flash_erase_region = 0x40000308 ); -PROVIDE( esp_flash_get_chip_write_protect = 0x4000030c ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000310 ); -PROVIDE( esp_flash_get_protectable_regions = 0x40000314 ); -PROVIDE( esp_flash_get_protected_region = 0x40000318 ); -PROVIDE( esp_flash_set_protected_region = 0x4000031c ); -PROVIDE( esp_flash_read = 0x40000320 ); -PROVIDE( esp_flash_write = 0x40000324 ); -PROVIDE( esp_flash_write_encrypted = 0x40000328 ); -PROVIDE( esp_flash_read_encrypted = 0x4000032c ); -PROVIDE( esp_flash_get_io_mode = 0x40000330 ); -PROVIDE( esp_flash_set_io_mode = 0x40000334 ); -PROVIDE( spi_flash_boot_attach = 0x40000338 ); -PROVIDE( spi_flash_dump_counters = 0x4000033c ); -PROVIDE( spi_flash_get_counters = 0x40000340 ); -PROVIDE( spi_flash_op_counters_config = 0x40000344 ); -PROVIDE( spi_flash_reset_counters = 0x40000348 ); -PROVIDE( esp_flash_read_chip_id = 0x4000034c ); -PROVIDE( detect_spi_flash_chip = 0x40000350 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x40000354 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fcdffe4 ); -PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 ); - - -/*************************************** - Group cache - ***************************************/ - -/* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x400004b8 ); -PROVIDE( Cache_Get_Mode = 0x400004bc ); -PROVIDE( Cache_Address_Through_IBus = 0x400004c0 ); -PROVIDE( Cache_Address_Through_DBus = 0x400004c4 ); -PROVIDE( Cache_Set_Default_Mode = 0x400004c8 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004cc ); -PROVIDE( ROM_Boot_Cache_Init = 0x400004d0 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x400004d4 ); -PROVIDE( Cache_Op_Addr = 0x400004d8 ); -PROVIDE( Cache_Invalidate_Addr = 0x400004dc ); -PROVIDE( Cache_Invalidate_ICache_All = 0x400004e0 ); -PROVIDE( Cache_Mask_All = 0x400004e4 ); -PROVIDE( Cache_UnMask_Dram0 = 0x400004e8 ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004ec ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x400004f0 ); -PROVIDE( Cache_Start_ICache_Preload = 0x400004f4 ); -PROVIDE( Cache_ICache_Preload_Done = 0x400004f8 ); -PROVIDE( Cache_End_ICache_Preload = 0x400004fc ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40000500 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x40000504 ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40000508 ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x4000050c ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40000510 ); -PROVIDE( Cache_Lock_ICache_Items = 0x40000514 ); -PROVIDE( Cache_Unlock_ICache_Items = 0x40000518 ); -PROVIDE( Cache_Lock_Addr = 0x4000051c ); -PROVIDE( Cache_Unlock_Addr = 0x40000520 ); -PROVIDE( Cache_Disable_ICache = 0x40000524 ); -PROVIDE( Cache_Enable_ICache = 0x40000528 ); -PROVIDE( Cache_Suspend_ICache = 0x4000052c ); -PROVIDE( Cache_Resume_ICache = 0x40000530 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x40000534 ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40000538 ); -PROVIDE( Cache_Pms_Lock = 0x4000053c ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000540 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000544 ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000548 ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x4000054c ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000550 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x40000554 ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x40000558 ); -PROVIDE( Cache_Owner_Init = 0x4000055c ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000560 ); -PROVIDE( Cache_MMU_Init = 0x40000564 ); -PROVIDE( Cache_Ibus_MMU_Set = 0x40000568 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x4000056c ); -PROVIDE( Cache_Count_Flash_Pages = 0x40000570 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x40000574 ); -PROVIDE( Cache_Get_Virtual_Addr = 0x40000578 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x4000057c ); -PROVIDE( Cache_Get_Memory_Addr = 0x40000580 ); -PROVIDE( Cache_Get_Memory_value = 0x40000584 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fcdffd4 ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 ); - - -/*************************************** - Group clock - ***************************************/ - -/* Functions */ -ets_get_apb_freq = 0x40000588; -ets_get_cpu_frequency = 0x4000058c; -ets_update_cpu_frequency = 0x40000590; -ets_get_printf_channel = 0x40000594; -ets_get_xtal_div = 0x40000598; -ets_set_xtal_div = 0x4000059c; -ets_get_xtal_freq = 0x400005a0; - - -/*************************************** - Group gpio - ***************************************/ - -/* Functions */ -gpio_input_get = 0x400005a4; -gpio_matrix_in = 0x400005a8; -gpio_matrix_out = 0x400005ac; -gpio_output_disable = 0x400005b0; -gpio_output_enable = 0x400005b4; -gpio_output_set = 0x400005b8; -gpio_pad_hold = 0x400005bc; -gpio_pad_input_disable = 0x400005c0; -gpio_pad_input_enable = 0x400005c4; -gpio_pad_pulldown = 0x400005c8; -gpio_pad_pullup = 0x400005cc; -gpio_pad_select_gpio = 0x400005d0; -gpio_pad_set_drv = 0x400005d4; -gpio_pad_unhold = 0x400005d8; -gpio_pin_wakeup_disable = 0x400005dc; -gpio_pin_wakeup_enable = 0x400005e0; -gpio_bypass_matrix_in = 0x400005e4; - - -/*************************************** - Group interrupts - ***************************************/ - -/* Functions */ -esprv_intc_int_set_priority = 0x400005e8; -esprv_intc_int_set_threshold = 0x400005ec; -esprv_intc_int_enable = 0x400005f0; -esprv_intc_int_disable = 0x400005f4; -esprv_intc_int_set_type = 0x400005f8; -intr_matrix_set = 0x400005fc; -ets_intr_lock = 0x40000600; -ets_intr_unlock = 0x40000604; -PROVIDE( intr_handler_set = 0x40000608 ); -ets_isr_attach = 0x4000060c; -ets_isr_mask = 0x40000610; -ets_isr_unmask = 0x40000614; - - -/*************************************** - Group crypto - ***************************************/ - -/* Functions */ -md5_vector = 0x40000618; -MD5Init = 0x4000061c; -MD5Update = 0x40000620; -MD5Final = 0x40000624; -hmac_md5_vector = 0x40000628; -hmac_md5 = 0x4000062c; -crc32_le = 0x40000630; -crc32_be = 0x40000634; -crc16_le = 0x40000638; -crc16_be = 0x4000063c; -crc8_le = 0x40000640; -crc8_be = 0x40000644; -esp_crc8 = 0x40000648; -ets_sha_enable = 0x4000064c; -ets_sha_disable = 0x40000650; -ets_sha_get_state = 0x40000654; -ets_sha_init = 0x40000658; -ets_sha_process = 0x4000065c; -ets_sha_starts = 0x40000660; -ets_sha_update = 0x40000664; -ets_sha_finish = 0x40000668; -ets_sha_clone = 0x4000066c; -ets_hmac_enable = 0x40000670; -ets_hmac_disable = 0x40000674; -ets_hmac_calculate_message = 0x40000678; -ets_hmac_calculate_downstream = 0x4000067c; -ets_hmac_invalidate_downstream = 0x40000680; -ets_jtag_enable_temporarily = 0x40000684; -ets_aes_enable = 0x40000688; -ets_aes_disable = 0x4000068c; -ets_aes_setkey = 0x40000690; -ets_aes_block = 0x40000694; -ets_bigint_enable = 0x40000698; -ets_bigint_disable = 0x4000069c; -ets_bigint_multiply = 0x400006a0; -ets_bigint_modmult = 0x400006a4; -ets_bigint_modexp = 0x400006a8; -ets_bigint_wait_finish = 0x400006ac; -ets_bigint_getz = 0x400006b0; -ets_ds_enable = 0x400006b4; -ets_ds_disable = 0x400006b8; -ets_ds_start_sign = 0x400006bc; -ets_ds_is_busy = 0x400006c0; -ets_ds_finish_sign = 0x400006c4; -ets_ds_encrypt_params = 0x400006c8; -ets_aes_setkey_dec = 0x400006cc; -ets_aes_setkey_enc = 0x400006d0; -ets_mgf1_sha256 = 0x400006d4; - - -/*************************************** - Group efuse - ***************************************/ - -/* Functions */ -ets_efuse_read = 0x400006d8; -ets_efuse_program = 0x400006dc; -ets_efuse_clear_program_registers = 0x400006e0; -ets_efuse_write_key = 0x400006e4; -ets_efuse_get_read_register_address = 0x400006e8; -ets_efuse_get_key_purpose = 0x400006ec; -ets_efuse_key_block_unused = 0x400006f0; -ets_efuse_find_unused_key_block = 0x400006f4; -ets_efuse_rs_calculate = 0x400006f8; -ets_efuse_count_unused_key_blocks = 0x400006fc; -ets_efuse_secure_boot_enabled = 0x40000700; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000704; -ets_efuse_cache_encryption_enabled = 0x40000708; -ets_efuse_download_modes_disabled = 0x4000070c; -ets_efuse_find_purpose = 0x40000710; -ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40000714; -ets_efuse_force_send_resume = 0x40000718; -ets_efuse_get_flash_delay_us = 0x4000071c; -ets_efuse_get_mac = 0x40000720; -ets_efuse_get_spiconfig = 0x40000724; -ets_efuse_usb_print_is_disabled = 0x40000728; -/*ets_efuse_get_uart_print_channel = 0x4000072c;*/ -ets_efuse_usb_serial_jtag_print_is_disabled = 0x4000072c; -ets_efuse_get_uart_print_control = 0x40000730; -ets_efuse_get_wp_pad = 0x40000734; -ets_efuse_direct_boot_mode_disabled = 0x40000738; -ets_efuse_security_download_modes_enabled = 0x4000073c; -ets_efuse_set_timing = 0x40000740; -ets_efuse_jtag_disabled = 0x40000744; -ets_efuse_usb_download_mode_disabled = 0x40000748; -ets_efuse_usb_module_disabled = 0x4000074c; -ets_efuse_usb_device_disabled = 0x40000750; -ets_efuse_secure_boot_fast_wake_enabled = 0x40000754; - - -/*************************************** - Group secureboot - ***************************************/ - -/* Functions */ -ets_emsa_pss_verify = 0x40000758; -ets_rsa_pss_verify = 0x4000075c; -ets_secure_boot_verify_bootloader_with_keys = 0x40000760; -ets_secure_boot_verify_signature = 0x40000764; -ets_secure_boot_read_key_digests = 0x40000768; -ets_secure_boot_revoke_public_key_digest = 0x4000076c; - - -/*************************************** - Group usb_uart - ***************************************/ - -/* Functions */ -PROVIDE( usb_uart_device_rx_one_char = 0x400008d8 ); -PROVIDE( usb_uart_device_rx_one_char_block = 0x400008dc ); -PROVIDE( usb_uart_device_tx_flush = 0x400008e0 ); -PROVIDE( usb_uart_device_tx_one_char = 0x400008e4 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( g_uart_print = 0x3fcdffcd ); -PROVIDE( g_usb_print = 0x3fcdffcc ); - - -/*************************************** - Group rom_phy - ***************************************/ - -/* Functions */ -phy_get_romfuncs = 0x400008e8; -rom_abs_temp = 0x400008ec; -rom_bb_bss_cbw40_dig = 0x400008f0; -rom_bb_wdg_test_en = 0x400008f4; -rom_bb_wdt_get_status = 0x400008f8; -rom_bb_wdt_int_enable = 0x400008fc; -rom_bb_wdt_rst_enable = 0x40000900; -rom_bb_wdt_timeout_clear = 0x40000904; -rom_cbw2040_cfg = 0x40000908; -rom_check_noise_floor = 0x4000090c; -rom_chip_i2c_readReg = 0x40000910; -rom_chip_i2c_writeReg = 0x40000914; -rom_correct_rf_ana_gain = 0x40000918; -rom_dc_iq_est = 0x4000091c; -rom_disable_agc = 0x40000920; -rom_en_pwdet = 0x40000924; -rom_enable_agc = 0x40000928; -rom_get_bbgain_db = 0x4000092c; -rom_get_data_sat = 0x40000930; -rom_get_i2c_read_mask = 0x40000934; -rom_get_pwctrl_correct = 0x40000938; -rom_get_rf_gain_qdb = 0x4000093c; -rom_i2c_readReg = 0x40000940; -rom_i2c_readReg_Mask = 0x40000944; -rom_i2c_writeReg = 0x40000948; -rom_i2c_writeReg_Mask = 0x4000094c; -rom_index_to_txbbgain = 0x40000950; -rom_iq_est_disable = 0x40000954; -rom_iq_est_enable = 0x40000958; -rom_linear_to_db = 0x4000095c; -rom_loopback_mode_en = 0x40000960; -rom_mhz2ieee = 0x40000964; -rom_noise_floor_auto_set = 0x40000968; -rom_pbus_debugmode = 0x4000096c; -rom_pbus_force_mode = 0x40000970; -rom_pbus_force_test = 0x40000974; -rom_pbus_rd = 0x40000978; -rom_pbus_rd_addr = 0x4000097c; -rom_pbus_rd_shift = 0x40000980; -rom_pbus_set_dco = 0x40000984; -rom_pbus_set_rxgain = 0x40000988; -rom_pbus_workmode = 0x4000098c; -rom_pbus_xpd_rx_off = 0x40000990; -rom_pbus_xpd_rx_on = 0x40000994; -rom_pbus_xpd_tx_off = 0x40000998; -rom_pbus_xpd_tx_on = 0x4000099c; -rom_phy_byte_to_word = 0x400009a0; -rom_phy_disable_cca = 0x400009a4; -rom_phy_enable_cca = 0x400009a8; -rom_phy_get_noisefloor = 0x400009ac; -rom_phy_get_rx_freq = 0x400009b0; -rom_phy_set_bbfreq_init = 0x400009b4; -rom_pow_usr = 0x400009b8; -rom_pwdet_sar2_init = 0x400009bc; -rom_read_hw_noisefloor = 0x400009c0; -rom_read_sar_dout = 0x400009c4; -rom_set_cal_rxdc = 0x400009c8; -rom_set_chan_cal_interp = 0x400009cc; -rom_set_loopback_gain = 0x400009d0; -rom_set_noise_floor = 0x400009d4; -rom_set_rxclk_en = 0x400009d8; -rom_set_tx_dig_gain = 0x400009dc; -rom_set_txcap_reg = 0x400009e0; -rom_set_txclk_en = 0x400009e4; -rom_spur_cal = 0x400009e8; -rom_spur_reg_write_one_tone = 0x400009ec; -rom_target_power_add_backoff = 0x400009f0; -rom_tx_pwctrl_bg_init = 0x400009f4; -rom_txbbgain_to_index = 0x400009f8; -rom_wifi_11g_rate_chg = 0x400009fc; -rom_write_gain_mem = 0x40000a00; -chip726_phyrom_version = 0x40000a04; -rom_disable_wifi_agc = 0x40000a08; -rom_enable_wifi_agc = 0x40000a0c; -rom_set_tx_gain_table = 0x40000a10; -rom_bt_index_to_bb = 0x40000a14; -rom_bt_bb_to_index = 0x40000a18; -rom_wr_bt_tx_atten = 0x40000a1c; -rom_wr_bt_tx_gain_mem = 0x40000a20; -rom_spur_coef_cfg = 0x40000a24; -rom_bb_bss_cbw40 = 0x40000a28; -rom_set_cca = 0x40000a2c; -rom_tx_paon_set = 0x40000a30; -rom_i2cmst_reg_init = 0x40000a34; -rom_iq_corr_enable = 0x40000a38; -rom_fe_reg_init = 0x40000a3c; -rom_agc_reg_init = 0x40000a40; -rom_bb_reg_init = 0x40000a44; -rom_mac_enable_bb = 0x40000a48; -rom_bb_wdg_cfg = 0x40000a4c; -rom_force_txon = 0x40000a50; -rom_fe_txrx_reset = 0x40000a54; -rom_set_rx_comp = 0x40000a58; -rom_set_pbus_reg = 0x40000a5c; -rom_write_chan_freq = 0x40000a60; -rom_phy_xpd_rf = 0x40000a64; -rom_set_xpd_sar = 0x40000a68; -rom_write_dac_gain2 = 0x40000a6c; -rom_rtc_sar2_init = 0x40000a70; -rom_get_target_power_offset = 0x40000a74; -rom_write_txrate_power_offset = 0x40000a78; -rom_get_rate_fcc_index = 0x40000a7c; -rom_get_rate_target_power = 0x40000a80; -rom_write_wifi_dig_gain = 0x40000a84; -rom_bt_correct_rf_ana_gain = 0x40000a88; -rom_pkdet_vol_start = 0x40000a8c; -rom_read_sar2_code = 0x40000a90; -rom_get_sar2_vol = 0x40000a94; -rom_get_pll_vol = 0x40000a98; -rom_get_phy_target_power = 0x40000a9c; -rom_temp_to_power = 0x40000aa0; -rom_phy_track_pll_cap = 0x40000aa4; -rom_phy_pwdet_always_en = 0x40000aa8; -rom_phy_pwdet_onetime_en = 0x40000aac; -rom_get_i2c_mst0_mask = 0x40000ab0; -rom_get_i2c_hostid = 0x40000ab4; -rom_enter_critical_phy = 0x40000ab8; -rom_exit_critical_phy = 0x40000abc; -rom_chip_i2c_readReg_org = 0x40000ac0; -rom_i2c_paral_set_mst0 = 0x40000ac4; -rom_i2c_paral_set_read = 0x40000ac8; -rom_i2c_paral_read = 0x40000acc; -rom_i2c_paral_write = 0x40000ad0; -rom_i2c_paral_write_num = 0x40000ad4; -rom_i2c_paral_write_mask = 0x40000ad8; -rom_bb_bss_cbw40_ana = 0x40000adc; -rom_chan_to_freq = 0x40000ae0; -rom_open_i2c_xpd = 0x40000ae4; -rom_dac_rate_set = 0x40000ae8; -rom_tsens_read_init = 0x40000aec; -rom_tsens_code_read = 0x40000af0; -rom_tsens_index_to_dac = 0x40000af4; -rom_tsens_index_to_offset = 0x40000af8; -rom_tsens_dac_cal = 0x40000afc; -rom_code_to_temp = 0x40000b00; -rom_write_pll_cap_mem = 0x40000b04; -rom_pll_correct_dcap = 0x40000b08; -rom_phy_en_hw_set_freq = 0x40000b0c; -rom_phy_dis_hw_set_freq = 0x40000b10; -rom_pll_vol_cal = 0x40000b14; -rom_wrtie_pll_cap = 0x40000b18; -rom_set_tx_gain_mem = 0x40000b1c; -rom_bt_tx_dig_gain = 0x40000b20; -rom_bt_get_tx_gain = 0x40000b24; -rom_get_chan_target_power = 0x40000b28; -rom_get_tx_gain_value = 0x40000b2c; -rom_wifi_tx_dig_gain = 0x40000b30; -rom_wifi_get_tx_gain = 0x40000b34; -rom_fe_i2c_reg_renew = 0x40000b38; -rom_wifi_agc_sat_gain = 0x40000b3c; -rom_i2c_master_reset = 0x40000b40; -rom_bt_filter_reg = 0x40000b44; -rom_phy_bbpll_cal = 0x40000b48; -rom_i2c_sar2_init_code = 0x40000b4c; -rom_phy_param_addr = 0x40000b50; -rom_phy_reg_init = 0x40000b54; -rom_set_chan_reg = 0x40000b58; -rom_phy_wakeup_init = 0x40000b5c; -rom_phy_i2c_init1 = 0x40000b60; -rom_tsens_temp_read = 0x40000b64; -rom_bt_track_pll_cap = 0x40000b68; -rom_wifi_track_pll_cap = 0x40000b6c; -rom_wifi_set_tx_gain = 0x40000b70; -rom_txpwr_cal_track = 0x40000b74; -rom_tx_pwctrl_background = 0x40000b78; -rom_bt_set_tx_gain = 0x40000b7c; -rom_noise_check_loop = 0x40000b80; -rom_phy_close_rf = 0x40000b84; -rom_phy_xpd_tsens = 0x40000b88; -rom_phy_freq_mem_backup = 0x40000b8c; -rom_phy_ant_init = 0x40000b90; -rom_bt_track_tx_power = 0x40000b94; -rom_wifi_track_tx_power = 0x40000b98; -rom_phy_dig_reg_backup = 0x40000b9c; -chip726_phyrom_version_num = 0x40000ba0; -/* Data (.data, .bss, .rodata) */ -phy_param_rom = 0x3fcdffc8; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld deleted file mode 100644 index 49c7131938..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld +++ /dev/null @@ -1,111 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group libgcc - ***************************************/ - -/* Functions */ -__absvdi2 = 0x40000770; -__absvsi2 = 0x40000774; -__adddf3 = 0x40000778; -__addsf3 = 0x4000077c; -__addvdi3 = 0x40000780; -__addvsi3 = 0x40000784; -__ashldi3 = 0x40000788; -__ashrdi3 = 0x4000078c; -__bswapdi2 = 0x40000790; -__bswapsi2 = 0x40000794; -__clear_cache = 0x40000798; -__clrsbdi2 = 0x4000079c; -__clrsbsi2 = 0x400007a0; -__clzdi2 = 0x400007a4; -__clzsi2 = 0x400007a8; -__cmpdi2 = 0x400007ac; -__ctzdi2 = 0x400007b0; -__ctzsi2 = 0x400007b4; -__divdc3 = 0x400007b8; -__divdf3 = 0x400007bc; -__divdi3 = 0x400007c0; -__divsc3 = 0x400007c4; -__divsf3 = 0x400007c8; -__divsi3 = 0x400007cc; -__eqdf2 = 0x400007d0; -__eqsf2 = 0x400007d4; -__extendsfdf2 = 0x400007d8; -__ffsdi2 = 0x400007dc; -__ffssi2 = 0x400007e0; -__fixdfdi = 0x400007e4; -__fixdfsi = 0x400007e8; -__fixsfdi = 0x400007ec; -__fixsfsi = 0x400007f0; -__fixunsdfsi = 0x400007f4; -__fixunssfdi = 0x400007f8; -__fixunssfsi = 0x400007fc; -__floatdidf = 0x40000800; -__floatdisf = 0x40000804; -__floatsidf = 0x40000808; -__floatsisf = 0x4000080c; -__floatundidf = 0x40000810; -__floatundisf = 0x40000814; -__floatunsidf = 0x40000818; -__floatunsisf = 0x4000081c; -__gcc_bcmp = 0x40000820; -__gedf2 = 0x40000824; -__gesf2 = 0x40000828; -__gtdf2 = 0x4000082c; -__gtsf2 = 0x40000830; -__ledf2 = 0x40000834; -__lesf2 = 0x40000838; -__lshrdi3 = 0x4000083c; -__ltdf2 = 0x40000840; -__ltsf2 = 0x40000844; -__moddi3 = 0x40000848; -__modsi3 = 0x4000084c; -__muldc3 = 0x40000850; -__muldf3 = 0x40000854; -__muldi3 = 0x40000858; -__mulsc3 = 0x4000085c; -__mulsf3 = 0x40000860; -__mulsi3 = 0x40000864; -__mulvdi3 = 0x40000868; -__mulvsi3 = 0x4000086c; -__nedf2 = 0x40000870; -__negdf2 = 0x40000874; -__negdi2 = 0x40000878; -__negsf2 = 0x4000087c; -__negvdi2 = 0x40000880; -__negvsi2 = 0x40000884; -__nesf2 = 0x40000888; -__paritysi2 = 0x4000088c; -__popcountdi2 = 0x40000890; -__popcountsi2 = 0x40000894; -__powidf2 = 0x40000898; -__powisf2 = 0x4000089c; -__subdf3 = 0x400008a0; -__subsf3 = 0x400008a4; -__subvdi3 = 0x400008a8; -__subvsi3 = 0x400008ac; -__truncdfsf2 = 0x400008b0; -__ucmpdi2 = 0x400008b4; -__udivdi3 = 0x400008b8; -__udivmoddi4 = 0x400008bc; -__udivsi3 = 0x400008c0; -__udiv_w_sdiv = 0x400008c4; -__umoddi3 = 0x400008c8; -__umodsi3 = 0x400008cc; -__unorddf2 = 0x400008d0; -__unordsf2 = 0x400008d4; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld deleted file mode 100644 index 953c20e02e..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib_nano_format - ***************************************/ - -/* Functions */ -__sprint_r = 0x40000488; -_fiprintf_r = 0x4000048c; -_fprintf_r = 0x40000490; -_printf_common = 0x40000494; -_printf_i = 0x40000498; -_vfiprintf_r = 0x4000049c; -_vfprintf_r = 0x400004a0; -fiprintf = 0x400004a4; -fprintf = 0x400004a8; -printf = 0x400004ac; -vfiprintf = 0x400004b0; -vfprintf = 0x400004b4; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld deleted file mode 100644 index fc9ee8c9de..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld +++ /dev/null @@ -1,96 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib - ***************************************/ - -/* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40000358; -memset = 0x4000035c; -memcpy = 0x40000360; -memmove = 0x40000364; -memcmp = 0x40000368; -strcpy = 0x4000036c; -strncpy = 0x40000370; -strcmp = 0x40000374; -strncmp = 0x40000378; -strlen = 0x4000037c; -strstr = 0x40000380; -bzero = 0x40000384; -sbrk = 0x4000038c; -isalnum = 0x40000390; -isalpha = 0x40000394; -isascii = 0x40000398; -isblank = 0x4000039c; -iscntrl = 0x400003a0; -isdigit = 0x400003a4; -islower = 0x400003a8; -isgraph = 0x400003ac; -isprint = 0x400003b0; -ispunct = 0x400003b4; -isspace = 0x400003b8; -isupper = 0x400003bc; -toupper = 0x400003c0; -tolower = 0x400003c4; -toascii = 0x400003c8; -memccpy = 0x400003cc; -memchr = 0x400003d0; -memrchr = 0x400003d4; -strcasecmp = 0x400003d8; -strcasestr = 0x400003dc; -strcat = 0x400003e0; -strdup = 0x400003e4; -strchr = 0x400003e8; -strcspn = 0x400003ec; -strcoll = 0x400003f0; -strlcat = 0x400003f4; -strlcpy = 0x400003f8; -strlwr = 0x400003fc; -strncasecmp = 0x40000400; -strncat = 0x40000404; -strndup = 0x40000408; -strnlen = 0x4000040c; -strrchr = 0x40000410; -strsep = 0x40000414; -strspn = 0x40000418; -strtok_r = 0x4000041c; -strupr = 0x40000420; -longjmp = 0x40000424; -setjmp = 0x40000428; -abs = 0x4000042c; -div = 0x40000430; -labs = 0x40000434; -ldiv = 0x40000438; -qsort = 0x4000043c; -rand_r = 0x40000440; -rand = 0x40000444; -srand = 0x40000448; -utoa = 0x4000044c; -itoa = 0x40000450; -atoi = 0x40000454; -atol = 0x40000458; -strtol = 0x4000045c; -strtoul = 0x40000460; -PROVIDE( fflush = 0x40000464 ); -PROVIDE( _fflush_r = 0x40000468 ); -PROVIDE( _fwalk = 0x4000046c ); -PROVIDE( _fwalk_reent = 0x40000470 ); -PROVIDE( __swbuf_r = 0x4000047c ); -__swbuf = 0x40000480; -/* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fcdffdc; -_global_impure_ptr = 0x3fcdffd8; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld deleted file mode 100644 index 46dd7a4b49..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld +++ /dev/null @@ -1,14 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM version variables for esp32b1z - * - * These addresses should be compatible with any ROM version for this chip. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ -_rom_chip_id = 0x40000010; -_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld deleted file mode 100644 index 7f03179c06..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld +++ /dev/null @@ -1,62 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** ROM APIs - */ -PROVIDE ( esp_rom_crc32_le = crc32_le ); -PROVIDE ( esp_rom_crc16_le = crc16_le ); -PROVIDE ( esp_rom_crc8_le = crc8_le ); -PROVIDE ( esp_rom_crc32_be = crc32_be ); -PROVIDE ( esp_rom_crc16_be = crc16_be ); -PROVIDE ( esp_rom_crc8_be = crc8_be ); - -PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); -PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); -PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); -PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); -PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); -PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); - -PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); -PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); -PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); -PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); - -PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); -PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); -PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); -PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); -PROVIDE ( esp_rom_uart_rx_string = UartRxString ); -PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); -PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - -PROVIDE ( esp_rom_md5_init = MD5Init ); -PROVIDE ( esp_rom_md5_update = MD5Update ); -PROVIDE ( esp_rom_md5_final = MD5Final ); - -PROVIDE ( esp_rom_software_reset_system = software_reset ); -PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); - -PROVIDE ( esp_rom_printf = ets_printf ); -PROVIDE ( esp_rom_delay_us = ets_delay_us ); -PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); -PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); -PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); -PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); - -PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); -PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable); -PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); - -PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); -PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); -PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); -PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld deleted file mode 100644 index a6dbff60a7..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld +++ /dev/null @@ -1,1707 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group common - ***************************************/ - -/* Functions */ -rtc_get_reset_reason = 0x40000018; -analog_super_wdt_reset_happened = 0x4000001c; -rtc_get_wakeup_cause = 0x40000020; -rtc_select_apb_bridge = 0x40000024; -rtc_unhold_all_pads = 0x40000028; -ets_is_print_boot = 0x4000002c; -ets_printf = 0x40000030; -ets_install_putc1 = 0x40000034; -ets_install_uart_printf = 0x40000038; -ets_install_putc2 = 0x4000003c; -PROVIDE( ets_delay_us = 0x40000040 ); -ets_install_lock = 0x40000044; -ets_backup_dma_copy = 0x40000048; -ets_apb_backup_init_lock_func = 0x4000004c; -UartRxString = 0x40000050; -UartGetCmdLn = 0x40000054; -uart_tx_one_char = 0x40000058; -uart_tx_one_char2 = 0x4000005c; -uart_rx_one_char = 0x40000060; -uart_rx_one_char_block = 0x40000064; -uart_rx_readbuff = 0x40000068; -uartAttach = 0x4000006c; -uart_tx_flush = 0x40000070; -uart_tx_wait_idle = 0x40000074; -uart_div_modify = 0x40000078; -ets_write_char_uart = 0x4000007c; -uart_tx_switch = 0x40000080; -multofup = 0x40000084; -software_reset = 0x40000088; -software_reset_cpu = 0x4000008c; -assist_debug_clock_enable = 0x40000090; -assist_debug_record_enable = 0x40000094; -clear_super_wdt_reset_flag = 0x40000098; -disable_default_watchdog = 0x4000009c; -esp_rom_set_rtc_wake_addr = 0x400000a0; -esp_rom_get_rtc_wake_addr = 0x400000a4; -send_packet = 0x400000a8; -recv_packet = 0x400000ac; -GetUartDevice = 0x400000b0; -UartDwnLdProc = 0x400000b4; -GetSecurityInfoProc = 0x400000b8; -Uart_Init = 0x400000bc; -ets_set_user_start = 0x400000c0; -/* Data (.data, .bss, .rodata) */ -ets_rom_layout_p = 0x3ff1fffc; -ets_ops_table_ptr = 0x3fcdfff8; -g_uart_print = 0x3fcdfffd; -g_usb_print = 0x3fcdfffc; - - -/*************************************** - Group miniz - ***************************************/ - -/* Functions */ -mz_adler32 = 0x400000c4; -mz_free = 0x400000c8; -tdefl_compress = 0x400000cc; -tdefl_compress_buffer = 0x400000d0; -tdefl_compress_mem_to_heap = 0x400000d4; -tdefl_compress_mem_to_mem = 0x400000d8; -tdefl_compress_mem_to_output = 0x400000dc; -tdefl_get_adler32 = 0x400000e0; -tdefl_get_prev_return_status = 0x400000e4; -tdefl_init = 0x400000e8; -tdefl_write_image_to_png_file_in_memory = 0x400000ec; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000f0; -tinfl_decompress = 0x400000f4; -tinfl_decompress_mem_to_callback = 0x400000f8; -tinfl_decompress_mem_to_heap = 0x400000fc; -tinfl_decompress_mem_to_mem = 0x40000100; - - -/*************************************** - Group tjpgd - ***************************************/ - -/* Functions */ -jd_prepare = 0x40000104; -jd_decomp = 0x40000108; - - -/*************************************** - Group spiflash_legacy - ***************************************/ - -/* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 ); -PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000124 ); -PROVIDE( _esp_rom_spiflash_erase_block = 0x40000128 ); -PROVIDE( _esp_rom_spiflash_write = 0x4000012c ); -PROVIDE( _esp_rom_spiflash_read = 0x40000130 ); -PROVIDE( _esp_rom_spiflash_unlock = 0x40000134 ); -PROVIDE( _SPIEraseArea = 0x40000138 ); -PROVIDE( _SPI_write_enable = 0x4000013c ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x40000140 ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000144 ); -PROVIDE( esp_rom_spiflash_write = 0x40000148 ); -PROVIDE( esp_rom_spiflash_read = 0x4000014c ); -PROVIDE( esp_rom_spiflash_unlock = 0x40000150 ); -PROVIDE( SPIEraseArea = 0x40000154 ); -PROVIDE( SPI_write_enable = 0x40000158 ); -PROVIDE( esp_rom_spiflash_config_param = 0x4000015c ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000160 ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000164 ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000168 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x4000016c ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000170 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x40000174 ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000178 ); -PROVIDE( esp_rom_spiflash_read_status = 0x4000017c ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000180 ); -PROVIDE( esp_rom_spiflash_write_status = 0x40000184 ); -PROVIDE( spi_flash_attach = 0x40000188 ); -PROVIDE( spi_flash_get_chip_size = 0x4000018c ); -PROVIDE( spi_flash_guard_set = 0x40000190 ); -PROVIDE( spi_flash_guard_get = 0x40000194 ); -PROVIDE( spi_flash_read_encrypted = 0x40000198 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x4000019c ); -PROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 ); -PROVIDE( spi_flash_mmap = 0x400001a4 ); -PROVIDE( spi_flash_mmap_pages = 0x400001a8 ); -PROVIDE( spi_flash_munmap = 0x400001ac ); -PROVIDE( spi_flash_mmap_dump = 0x400001b0 ); -PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 ); -PROVIDE( spi_flash_cache2phys = 0x400001bc ); -PROVIDE( spi_flash_phys2cache = 0x400001c0 ); -PROVIDE( spi_flash_disable_cache = 0x400001c4 ); -PROVIDE( spi_flash_restore_cache = 0x400001c8 ); -PROVIDE( spi_flash_cache_enabled = 0x400001cc ); -PROVIDE( spi_flash_enable_cache = 0x400001d0 ); -PROVIDE( spi_cache_mode_switch = 0x400001d4 ); -PROVIDE( spi_common_set_dummy_output = 0x400001d8 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001dc ); -PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001e0 ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001e4 ); -PROVIDE( SPILock = 0x400001e8 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001ec ); -PROVIDE( SPI_Common_Command = 0x400001f0 ); -PROVIDE( SPI_WakeUp = 0x400001f4 ); -PROVIDE( SPI_block_erase = 0x400001f8 ); -PROVIDE( SPI_chip_erase = 0x400001fc ); -PROVIDE( SPI_init = 0x40000200 ); -PROVIDE( SPI_page_program = 0x40000204 ); -PROVIDE( SPI_read_data = 0x40000208 ); -PROVIDE( SPI_sector_erase = 0x4000020c ); -PROVIDE( SelectSpiFunction = 0x40000210 ); -PROVIDE( SetSpiDrvs = 0x40000214 ); -PROVIDE( Wait_SPI_Idle = 0x40000218 ); -PROVIDE( spi_dummy_len_fix = 0x4000021c ); -PROVIDE( Disable_QMode = 0x40000220 ); -PROVIDE( Enable_QMode = 0x40000224 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec ); -PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); - - -/*************************************** - Group hal_soc - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 ); -PROVIDE( spi_flash_hal_device_config = 0x4000022c ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 ); -PROVIDE( spi_flash_hal_common_command = 0x40000234 ); -PROVIDE( spi_flash_hal_read = 0x40000238 ); -PROVIDE( spi_flash_hal_erase_chip = 0x4000023c ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000240 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000244 ); -PROVIDE( spi_flash_hal_program_page = 0x40000248 ); -PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c ); -PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); -PROVIDE( spi_flash_hal_check_status = 0x40000254 ); -PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000258 ); -PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000025c ); -PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000260 ); -PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000264 ); -PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000268 ); -PROVIDE( spi_flash_hal_resume = 0x4000026c ); -PROVIDE( spi_flash_hal_suspend = 0x40000270 ); -PROVIDE( spi_flash_encryption_hal_enable = 0x40000274 ); -PROVIDE( spi_flash_encryption_hal_disable = 0x40000278 ); -PROVIDE( spi_flash_encryption_hal_prepare = 0x4000027c ); -PROVIDE( spi_flash_encryption_hal_done = 0x40000280 ); -PROVIDE( spi_flash_encryption_hal_destroy = 0x40000284 ); -PROVIDE( spi_flash_encryption_hal_check = 0x40000288 ); -PROVIDE( wdt_hal_init = 0x4000028c ); -PROVIDE( wdt_hal_deinit = 0x40000290 ); -PROVIDE( wdt_hal_config_stage = 0x40000294 ); -PROVIDE( wdt_hal_write_protect_disable = 0x40000298 ); -PROVIDE( wdt_hal_write_protect_enable = 0x4000029c ); -PROVIDE( wdt_hal_enable = 0x400002a0 ); -PROVIDE( wdt_hal_disable = 0x400002a4 ); -PROVIDE( wdt_hal_handle_intr = 0x400002a8 ); -PROVIDE( wdt_hal_feed = 0x400002ac ); -PROVIDE( wdt_hal_set_flashboot_en = 0x400002b0 ); -PROVIDE( wdt_hal_is_enabled = 0x400002b4 ); -PROVIDE( systimer_hal_init = 0x400002b8 ); -PROVIDE( systimer_hal_get_counter_value = 0x400002bc ); -PROVIDE( systimer_hal_get_time = 0x400002c0 ); -PROVIDE( systimer_hal_set_alarm_target = 0x400002c4 ); -PROVIDE( systimer_hal_set_alarm_period = 0x400002c8 ); -PROVIDE( systimer_hal_get_alarm_value = 0x400002cc ); -PROVIDE( systimer_hal_enable_alarm_int = 0x400002d0 ); -PROVIDE( systimer_hal_on_apb_freq_update = 0x400002d4 ); -PROVIDE( systimer_hal_counter_value_advance = 0x400002d8 ); -PROVIDE( systimer_hal_enable_counter = 0x400002dc ); -PROVIDE( systimer_hal_select_alarm_mode = 0x400002e0 ); -PROVIDE( systimer_hal_connect_alarm_counter = 0x400002e4 ); -PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002e8 ); - - -/*************************************** - Group heap - ***************************************/ - -/* Functions */ -PROVIDE( tlsf_create = 0x400002ec ); -PROVIDE( tlsf_create_with_pool = 0x400002f0 ); -PROVIDE( tlsf_get_pool = 0x400002f4 ); -PROVIDE( tlsf_add_pool = 0x400002f8 ); -PROVIDE( tlsf_remove_pool = 0x400002fc ); -PROVIDE( tlsf_malloc = 0x40000300 ); -PROVIDE( tlsf_memalign = 0x40000304 ); -PROVIDE( tlsf_memalign_offs = 0x40000308 ); -PROVIDE( tlsf_realloc = 0x4000030c ); -PROVIDE( tlsf_free = 0x40000310 ); -PROVIDE( tlsf_block_size = 0x40000314 ); -PROVIDE( tlsf_size = 0x40000318 ); -PROVIDE( tlsf_align_size = 0x4000031c ); -PROVIDE( tlsf_block_size_min = 0x40000320 ); -PROVIDE( tlsf_block_size_max = 0x40000324 ); -PROVIDE( tlsf_pool_overhead = 0x40000328 ); -PROVIDE( tlsf_alloc_overhead = 0x4000032c ); -PROVIDE( tlsf_walk_pool = 0x40000330 ); -PROVIDE( tlsf_check = 0x40000334 ); -PROVIDE( tlsf_check_pool = 0x40000338 ); -PROVIDE( tlsf_poison_fill_pfunc_set = 0x4000033c ); -PROVIDE( multi_heap_get_block_address_impl = 0x40000340 ); -PROVIDE( multi_heap_get_allocated_size_impl = 0x40000344 ); -PROVIDE( multi_heap_register_impl = 0x40000348 ); -PROVIDE( multi_heap_set_lock = 0x4000034c ); -PROVIDE( multi_heap_mutex_init = 0x40000350 ); -PROVIDE( multi_heap_internal_lock = 0x40000354 ); -PROVIDE( multi_heap_internal_unlock = 0x40000358 ); -PROVIDE( multi_heap_get_first_block = 0x4000035c ); -PROVIDE( multi_heap_get_next_block = 0x40000360 ); -PROVIDE( multi_heap_is_free = 0x40000364 ); -PROVIDE( multi_heap_malloc_impl = 0x40000368 ); -PROVIDE( multi_heap_free_impl = 0x4000036c ); -PROVIDE( multi_heap_realloc_impl = 0x40000370 ); -PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000374 ); -PROVIDE( multi_heap_aligned_alloc_impl = 0x40000378 ); -PROVIDE( multi_heap_check = 0x4000037c ); -PROVIDE( multi_heap_dump = 0x40000380 ); -PROVIDE( multi_heap_free_size_impl = 0x40000384 ); -PROVIDE( multi_heap_minimum_free_size_impl = 0x40000388 ); -PROVIDE( multi_heap_get_info_impl = 0x4000038c ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( heap_tlsf_table_ptr = 0x3fcdffe8 ); - - -/*************************************** - Group spi_flash_chips - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000390 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000394 ); -PROVIDE( spi_flash_chip_generic_write = 0x40000398 ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000039c ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x400003a0 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x400003a4 ); -PROVIDE( spi_flash_chip_generic_reset = 0x400003a8 ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x400003ac ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x400003b0 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x400003b4 ); -PROVIDE( spi_flash_chip_generic_page_program = 0x400003b8 ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003bc ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003c0 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x400003c4 ); -PROVIDE( spi_flash_chip_generic_yield = 0x400003c8 ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x400003cc ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003d0 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003d4 ); -PROVIDE( spi_flash_chip_generic_read = 0x400003d8 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003dc ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003e0 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003e4 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003e8 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003ec ); -PROVIDE( spi_flash_common_set_io_mode = 0x400003f0 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003f4 ); -PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003f8 ); -PROVIDE( spi_flash_chip_generic_get_caps = 0x400003fc ); -PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x40000400 ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40000404 ); -PROVIDE( spi_flash_chip_gd_probe = 0x40000408 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x4000040c ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe4 ); -PROVIDE( spi_flash_encryption = 0x3fcdffe0 ); - - -/*************************************** - Group memspi_host - ***************************************/ - -/* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x40000410 ); -PROVIDE( memspi_host_read_status_hs = 0x40000414 ); -PROVIDE( memspi_host_flush_cache = 0x40000418 ); -PROVIDE( memspi_host_erase_chip = 0x4000041c ); -PROVIDE( memspi_host_erase_sector = 0x40000420 ); -PROVIDE( memspi_host_erase_block = 0x40000424 ); -PROVIDE( memspi_host_program_page = 0x40000428 ); -PROVIDE( memspi_host_read = 0x4000042c ); -PROVIDE( memspi_host_set_write_protect = 0x40000430 ); -PROVIDE( memspi_host_set_max_read_len = 0x40000434 ); -PROVIDE( memspi_host_read_data_slicer = 0x40000438 ); -PROVIDE( memspi_host_write_data_slicer = 0x4000043c ); - - -/*************************************** - Group esp_flash - ***************************************/ - -/* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x40000440 ); -PROVIDE( esp_flash_read_id = 0x40000444 ); -PROVIDE( esp_flash_get_size = 0x40000448 ); -PROVIDE( esp_flash_erase_chip = 0x4000044c ); -PROVIDE( esp_flash_erase_region = 0x40000450 ); -PROVIDE( esp_flash_get_chip_write_protect = 0x40000454 ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000458 ); -PROVIDE( esp_flash_get_protectable_regions = 0x4000045c ); -PROVIDE( esp_flash_get_protected_region = 0x40000460 ); -PROVIDE( esp_flash_set_protected_region = 0x40000464 ); -PROVIDE( esp_flash_read = 0x40000468 ); -PROVIDE( esp_flash_write = 0x4000046c ); -PROVIDE( esp_flash_write_encrypted = 0x40000470 ); -PROVIDE( esp_flash_read_encrypted = 0x40000474 ); -PROVIDE( esp_flash_get_io_mode = 0x40000478 ); -PROVIDE( esp_flash_set_io_mode = 0x4000047c ); -PROVIDE( spi_flash_boot_attach = 0x40000480 ); -PROVIDE( esp_flash_read_chip_id = 0x40000484 ); -PROVIDE( detect_spi_flash_chip = 0x40000488 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x4000048c ); -PROVIDE( esp_flash_suspend_cmd_init = 0x40000490 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fcdffdc ); -PROVIDE( esp_flash_api_funcs = 0x3fcdffd8 ); - - -/*************************************** - Group cache - ***************************************/ - -/* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x400006f0 ); -PROVIDE( Cache_Get_Mode = 0x400006f4 ); -PROVIDE( Cache_Address_Through_IBus = 0x400006f8 ); -PROVIDE( Cache_Address_Through_DBus = 0x400006fc ); -PROVIDE( Cache_Set_Default_Mode = 0x40000700 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x40000704 ); -PROVIDE( ROM_Boot_Cache_Init = 0x40000708 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x4000070c ); -PROVIDE( Cache_Op_Addr = 0x40000710 ); -PROVIDE( Cache_Invalidate_Addr = 0x40000714 ); -PROVIDE( Cache_Invalidate_ICache_All = 0x40000718 ); -PROVIDE( Cache_Mask_All = 0x4000071c ); -PROVIDE( Cache_UnMask_Dram0 = 0x40000720 ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x40000724 ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x40000728 ); -PROVIDE( Cache_Start_ICache_Preload = 0x4000072c ); -PROVIDE( Cache_ICache_Preload_Done = 0x40000730 ); -PROVIDE( Cache_End_ICache_Preload = 0x40000734 ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40000738 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x4000073c ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40000740 ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x40000744 ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40000748 ); -PROVIDE( Cache_Lock_ICache_Items = 0x4000074c ); -PROVIDE( Cache_Unlock_ICache_Items = 0x40000750 ); -PROVIDE( Cache_Lock_Addr = 0x40000754 ); -PROVIDE( Cache_Unlock_Addr = 0x40000758 ); -PROVIDE( Cache_Disable_ICache = 0x4000075c ); -PROVIDE( Cache_Enable_ICache = 0x40000760 ); -PROVIDE( Cache_Suspend_ICache = 0x40000764 ); -PROVIDE( Cache_Resume_ICache = 0x40000768 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x4000076c ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40000770 ); -PROVIDE( Cache_Pms_Lock = 0x40000774 ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000778 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000077c ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000780 ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000784 ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000788 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x4000078c ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x40000790 ); -PROVIDE( Cache_Owner_Init = 0x40000794 ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000798 ); -PROVIDE( Cache_MMU_Init = 0x4000079c ); -PROVIDE( Cache_Ibus_MMU_Set = 0x400007a0 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x400007a4 ); -PROVIDE( Cache_Count_Flash_Pages = 0x400007a8 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x400007ac ); -PROVIDE( Cache_Get_Virtual_Addr = 0x400007b0 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x400007b4 ); -PROVIDE( Cache_Get_Memory_Addr = 0x400007b8 ); -PROVIDE( Cache_Get_Memory_value = 0x400007bc ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fcdffcc ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffc8 ); - - -/*************************************** - Group clock - ***************************************/ - -/* Functions */ -ets_get_apb_freq = 0x400007c0; -ets_get_cpu_frequency = 0x400007c4; -ets_update_cpu_frequency = 0x400007c8; -ets_get_printf_channel = 0x400007cc; -ets_get_xtal_div = 0x400007d0; -ets_set_xtal_div = 0x400007d4; -ets_get_xtal_freq = 0x400007d8; - - -/*************************************** - Group gpio - ***************************************/ - -/* Functions */ -gpio_input_get = 0x400007dc; -gpio_matrix_in = 0x400007e0; -gpio_matrix_out = 0x400007e4; -gpio_output_disable = 0x400007e8; -gpio_output_enable = 0x400007ec; -gpio_output_set = 0x400007f0; -gpio_pad_hold = 0x400007f4; -gpio_pad_input_disable = 0x400007f8; -gpio_pad_input_enable = 0x400007fc; -gpio_pad_pulldown = 0x40000800; -gpio_pad_pullup = 0x40000804; -gpio_pad_select_gpio = 0x40000808; -gpio_pad_set_drv = 0x4000080c; -gpio_pad_unhold = 0x40000810; -gpio_pin_wakeup_disable = 0x40000814; -gpio_pin_wakeup_enable = 0x40000818; -gpio_bypass_matrix_in = 0x4000081c; - - -/*************************************** - Group interrupts - ***************************************/ - -/* Functions */ -esprv_intc_int_set_priority = 0x40000820; -esprv_intc_int_set_threshold = 0x40000824; -esprv_intc_int_enable = 0x40000828; -esprv_intc_int_disable = 0x4000082c; -esprv_intc_int_set_type = 0x40000830; -PROVIDE( intr_handler_set = 0x40000834 ); -intr_matrix_set = 0x40000838; -ets_intr_lock = 0x4000083c; -ets_intr_unlock = 0x40000840; -ets_isr_attach = 0x40000844; -ets_isr_mask = 0x40000848; -ets_isr_unmask = 0x4000084c; - - -/*************************************** - Group crypto - ***************************************/ - -/* Functions */ -md5_vector = 0x40000850; -MD5Init = 0x40000854; -MD5Update = 0x40000858; -MD5Final = 0x4000085c; -crc32_le = 0x40000860; -crc16_le = 0x40000864; -crc8_le = 0x40000868; -crc32_be = 0x4000086c; -crc16_be = 0x40000870; -crc8_be = 0x40000874; -esp_crc8 = 0x40000878; -ets_sha_enable = 0x4000087c; -ets_sha_disable = 0x40000880; -ets_sha_get_state = 0x40000884; -ets_sha_init = 0x40000888; -ets_sha_process = 0x4000088c; -ets_sha_starts = 0x40000890; -ets_sha_update = 0x40000894; -ets_sha_finish = 0x40000898; -ets_sha_clone = 0x4000089c; -ets_hmac_enable = 0x400008a0; -ets_hmac_disable = 0x400008a4; -ets_hmac_calculate_message = 0x400008a8; -ets_hmac_calculate_downstream = 0x400008ac; -ets_hmac_invalidate_downstream = 0x400008b0; -ets_jtag_enable_temporarily = 0x400008b4; -ets_aes_enable = 0x400008b8; -ets_aes_disable = 0x400008bc; -ets_aes_setkey = 0x400008c0; -ets_aes_block = 0x400008c4; -ets_aes_setkey_dec = 0x400008c8; -ets_aes_setkey_enc = 0x400008cc; -ets_bigint_enable = 0x400008d0; -ets_bigint_disable = 0x400008d4; -ets_bigint_multiply = 0x400008d8; -ets_bigint_modmult = 0x400008dc; -ets_bigint_modexp = 0x400008e0; -ets_bigint_wait_finish = 0x400008e4; -ets_bigint_getz = 0x400008e8; -ets_ds_enable = 0x400008ec; -ets_ds_disable = 0x400008f0; -ets_ds_start_sign = 0x400008f4; -ets_ds_is_busy = 0x400008f8; -ets_ds_finish_sign = 0x400008fc; -ets_ds_encrypt_params = 0x40000900; -ets_mgf1_sha256 = 0x40000904; -/* Data (.data, .bss, .rodata) */ -crc32_le_table_ptr = 0x3ff1fff8; -crc16_le_table_ptr = 0x3ff1fff4; -crc8_le_table_ptr = 0x3ff1fff0; -crc32_be_table_ptr = 0x3ff1ffec; -crc16_be_table_ptr = 0x3ff1ffe8; -crc8_be_table_ptr = 0x3ff1ffe4; - - -/*************************************** - Group efuse - ***************************************/ - -/* Functions */ -ets_efuse_read = 0x40000908; -ets_efuse_program = 0x4000090c; -ets_efuse_clear_program_registers = 0x40000910; -ets_efuse_write_key = 0x40000914; -ets_efuse_get_read_register_address = 0x40000918; -ets_efuse_get_key_purpose = 0x4000091c; -ets_efuse_key_block_unused = 0x40000920; -ets_efuse_find_unused_key_block = 0x40000924; -ets_efuse_rs_calculate = 0x40000928; -ets_efuse_count_unused_key_blocks = 0x4000092c; -ets_efuse_secure_boot_enabled = 0x40000930; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000934; -ets_efuse_cache_encryption_enabled = 0x40000938; -ets_efuse_download_modes_disabled = 0x4000093c; -ets_efuse_find_purpose = 0x40000940; -ets_efuse_force_send_resume = 0x40000944; -ets_efuse_get_flash_delay_us = 0x40000948; -ets_efuse_get_mac = 0x4000094c; -ets_efuse_get_uart_print_control = 0x40000950; -ets_efuse_direct_boot_mode_disabled = 0x40000954; -ets_efuse_security_download_modes_enabled = 0x40000958; -ets_efuse_set_timing = 0x4000095c; -ets_efuse_jtag_disabled = 0x40000960; -ets_efuse_get_spiconfig = 0x40000964; -ets_efuse_get_wp_pad = 0x40000968; -ets_efuse_usb_print_is_disabled = 0x4000096c; -ets_efuse_usb_download_mode_disabled = 0x40000970; -ets_efuse_usb_module_disabled = 0x40000974; -ets_efuse_usb_device_disabled = 0x40000978; -ets_efuse_secure_boot_fast_wake_enabled = 0x4000097c; - - -/*************************************** - Group secureboot - ***************************************/ - -/* Functions */ -ets_emsa_pss_verify = 0x40000980; -ets_rsa_pss_verify = 0x40000984; -ets_secure_boot_verify_bootloader_with_keys = 0x40000988; -ets_secure_boot_verify_signature = 0x4000098c; -ets_secure_boot_read_key_digests = 0x40000990; -ets_secure_boot_revoke_public_key_digest = 0x40000994; - - -/*************************************** - Group btdm - ***************************************/ - -/* Functions */ -/* -ble_controller_rom_data_init = 0x40000b08; -ble_osi_coex_funcs_register = 0x40000b0c; -bt_rf_coex_cfg_get_default = 0x40000b10; -bt_rf_coex_dft_pti_get_default = 0x40000b14; -bt_rf_coex_hooks_p_set = 0x40000b18; -r__os_mbuf_copypkthdr = 0x40000b1c; -r__os_msys_find_pool = 0x40000b20; -r_ble_controller_get_rom_compile_version = 0x40000b24; -r_ble_hci_ram_hs_acl_tx = 0x40000b28; -r_ble_hci_ram_hs_cmd_tx = 0x40000b2c; -r_ble_hci_ram_ll_acl_tx = 0x40000b30; -r_ble_hci_ram_ll_evt_tx = 0x40000b34; -r_ble_hci_ram_reset = 0x40000b38; -r_ble_hci_ram_set_acl_free_cb = 0x40000b3c; -r_ble_hci_trans_acl_buf_alloc = 0x40000b40; -r_ble_hci_trans_buf_alloc = 0x40000b44; -r_ble_hci_trans_buf_free = 0x40000b48; -r_ble_hci_trans_cfg_hs = 0x40000b4c; -r_ble_hci_trans_cfg_ll = 0x40000b50; -r_ble_hci_trans_deinit = 0x40000b54; -r_ble_hci_trans_env_init = 0x40000b58; -r_ble_hci_trans_init = 0x40000b5c; -r_ble_hci_uart_acl_tx = 0x40000b60; -r_ble_hci_uart_cmdevt_tx = 0x40000b64; -r_ble_hci_uart_config = 0x40000b68; -r_ble_hci_uart_free_pkt = 0x40000b6c; -r_ble_hci_uart_hs_acl_tx = 0x40000b70; -r_ble_hci_uart_hs_cmd_tx = 0x40000b74; -r_ble_hci_uart_ll_acl_tx = 0x40000b78; -r_ble_hci_uart_ll_evt_tx = 0x40000b7c; -r_ble_hci_uart_rx_acl = 0x40000b80; -r_ble_hci_uart_rx_char = 0x40000b84; -r_ble_hci_uart_rx_cmd = 0x40000b88; -r_ble_hci_uart_rx_evt = 0x40000b8c; -r_ble_hci_uart_rx_evt_cb = 0x40000b90; -r_ble_hci_uart_rx_le_evt = 0x40000b94; -r_ble_hci_uart_rx_pkt_type = 0x40000b98; -r_ble_hci_uart_rx_skip_acl = 0x40000b9c; -r_ble_hci_uart_rx_skip_cmd = 0x40000ba0; -r_ble_hci_uart_rx_skip_evt = 0x40000ba4; -r_ble_hci_uart_rx_sync_loss = 0x40000ba8; -r_ble_hci_uart_set_acl_free_cb = 0x40000bac; -r_ble_hci_uart_sync_lost = 0x40000bb0; -r_ble_hci_uart_trans_reset = 0x40000bb4; -r_ble_hci_uart_tx_char = 0x40000bb8; -r_ble_hci_uart_tx_pkt_type = 0x40000bbc; -r_ble_hw_driver_deinit = 0x40000bc0; -r_ble_hw_driver_env_init = 0x40000bc4; -r_ble_hw_encrypt_block = 0x40000bc8; -r_ble_hw_get_public_addr = 0x40000bcc; -r_ble_hw_get_static_addr = 0x40000bd0; -r_ble_hw_periodiclist_add = 0x40000bd4; -r_ble_hw_periodiclist_clear = 0x40000bd8; -r_ble_hw_periodiclist_rmv = 0x40000bdc; -r_ble_hw_resolv_list_cur_entry = 0x40000be0; -r_ble_hw_resolv_list_match = 0x40000be4; -r_ble_hw_resolv_list_set = 0x40000be8; -r_ble_hw_rng_init = 0x40000bec; -r_ble_hw_rng_start = 0x40000bf0; -r_ble_hw_rng_stop = 0x40000bf4; -r_ble_hw_rx_local_is_rpa = 0x40000bf8; -r_ble_hw_whitelist_add = 0x40000bfc; -r_ble_hw_whitelist_clear = 0x40000c00; -r_ble_hw_whitelist_dev_num = 0x40000c04; -r_ble_hw_whitelist_get_base = 0x40000c08; -r_ble_hw_whitelist_rmv = 0x40000c0c; -r_ble_hw_whitelist_search = 0x40000c10; -r_ble_hw_whitelist_sort = 0x40000c14; -r_ble_ll_acl_data_in = 0x40000c18; -r_ble_ll_addr_is_id = 0x40000c1c; -r_ble_ll_addr_subtype = 0x40000c20; -r_ble_ll_adv_active_chanset_clear = 0x40000c24; -r_ble_ll_adv_active_chanset_is_pri = 0x40000c28; -r_ble_ll_adv_active_chanset_is_sec = 0x40000c2c; -r_ble_ll_adv_active_chanset_set_pri = 0x40000c30; -r_ble_ll_adv_active_chanset_set_sec = 0x40000c34; -r_ble_ll_adv_aux_calculate = 0x40000c38; -r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000c3c; -r_ble_ll_adv_aux_pdu_make = 0x40000c40; -r_ble_ll_adv_aux_scannable_pdu_make = 0x40000c44; -r_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000c48; -r_ble_ll_adv_aux_schedule = 0x40000c4c; -r_ble_ll_adv_aux_schedule_first = 0x40000c50; -r_ble_ll_adv_aux_schedule_next = 0x40000c54; -r_ble_ll_adv_aux_scheduled = 0x40000c58; -r_ble_ll_adv_aux_set_start_time = 0x40000c5c; -r_ble_ll_adv_aux_txed = 0x40000c60; -r_ble_ll_adv_can_chg_whitelist = 0x40000c64; -r_ble_ll_adv_chk_rpa_timeout = 0x40000c68; -r_ble_ll_adv_clear_all = 0x40000c6c; -r_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000c70; -r_ble_ll_adv_coex_dpc_process_pri = 0x40000c74; -r_ble_ll_adv_coex_dpc_process_sec = 0x40000c78; -r_ble_ll_adv_coex_dpc_pti_get = 0x40000c7c; -r_ble_ll_adv_coex_dpc_update = 0x40000c80; -r_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000c84; -r_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000c88; -r_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000c8c; -r_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000c90; -r_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000c94; -r_ble_ll_adv_conn_req_rxd = 0x40000c98; -r_ble_ll_adv_deinit = 0x40000c9c; -r_ble_ll_adv_done = 0x40000ca0; -r_ble_ll_adv_drop_event = 0x40000ca4; -r_ble_ll_adv_enabled = 0x40000ca8; -r_ble_ll_adv_env_init = 0x40000cac; -r_ble_ll_adv_event_done = 0x40000cb0; -r_ble_ll_adv_event_rmvd_from_sched = 0x40000cb4; -r_ble_ll_adv_ext_estimate_data_itvl = 0x40000cb8; -r_ble_ll_adv_ext_set_adv_data = 0x40000cbc; -r_ble_ll_adv_ext_set_enable = 0x40000cc0; -r_ble_ll_adv_ext_set_param = 0x40000cc4; -r_ble_ll_adv_ext_set_scan_rsp = 0x40000cc8; -r_ble_ll_adv_final_chan = 0x40000ccc; -r_ble_ll_adv_first_chan = 0x40000cd0; -r_ble_ll_adv_flags_clear = 0x40000cd4; -r_ble_ll_adv_flags_set = 0x40000cd8; -r_ble_ll_adv_get_local_rpa = 0x40000cdc; -r_ble_ll_adv_get_peer_rpa = 0x40000ce0; -r_ble_ll_adv_get_sec_pdu_len = 0x40000ce4; -r_ble_ll_adv_halt = 0x40000ce8; -r_ble_ll_adv_hci_set_random_addr = 0x40000cec; -r_ble_ll_adv_init = 0x40000cf0; -r_ble_ll_adv_legacy_pdu_make = 0x40000cf4; -r_ble_ll_adv_make_done = 0x40000cf8; -r_ble_ll_adv_pdu_make = 0x40000cfc; -r_ble_ll_adv_periodic_check_data_itvl = 0x40000d00; -r_ble_ll_adv_periodic_done = 0x40000d04; -r_ble_ll_adv_periodic_enable = 0x40000d08; -r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000d0c; -r_ble_ll_adv_periodic_event_done = 0x40000d10; -r_ble_ll_adv_periodic_rmvd_from_sched = 0x40000d14; -r_ble_ll_adv_periodic_schedule_first = 0x40000d18; -r_ble_ll_adv_periodic_schedule_next = 0x40000d1c; -r_ble_ll_adv_periodic_send_sync_ind = 0x40000d20; -r_ble_ll_adv_periodic_set_data = 0x40000d24; -r_ble_ll_adv_periodic_set_info_transfer = 0x40000d28; -r_ble_ll_adv_periodic_set_param = 0x40000d2c; -r_ble_ll_adv_put_aux_ptr = 0x40000d30; -r_ble_ll_adv_put_syncinfo = 0x40000d34; -r_ble_ll_adv_rd_max_adv_data_len = 0x40000d38; -r_ble_ll_adv_rd_sup_adv_sets = 0x40000d3c; -r_ble_ll_adv_read_txpwr = 0x40000d40; -r_ble_ll_adv_remove = 0x40000d44; -r_ble_ll_adv_reschedule_event = 0x40000d48; -r_ble_ll_adv_reschedule_periodic_event = 0x40000d4c; -r_ble_ll_adv_reset = 0x40000d50; -r_ble_ll_adv_rpa_timeout = 0x40000d54; -r_ble_ll_adv_rpa_update = 0x40000d58; -r_ble_ll_adv_rx_isr_end = 0x40000d5c; -r_ble_ll_adv_rx_isr_start = 0x40000d60; -r_ble_ll_adv_rx_pkt_in = 0x40000d64; -r_ble_ll_adv_rx_req = 0x40000d68; -r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000d6c; -r_ble_ll_adv_scan_rsp_pdu_make = 0x40000d70; -r_ble_ll_adv_scheduled = 0x40000d74; -r_ble_ll_adv_sec_done = 0x40000d78; -r_ble_ll_adv_sec_event_done = 0x40000d7c; -r_ble_ll_adv_secondary_tx_start_cb = 0x40000d80; -r_ble_ll_adv_send_conn_comp_ev = 0x40000d84; -r_ble_ll_adv_set_adv_data = 0x40000d88; -r_ble_ll_adv_set_adv_params = 0x40000d8c; -r_ble_ll_adv_set_enable = 0x40000d90; -r_ble_ll_adv_set_random_addr = 0x40000d94; -r_ble_ll_adv_set_scan_rsp_data = 0x40000d98; -r_ble_ll_adv_set_sched = 0x40000d9c; -r_ble_ll_adv_sm_deinit = 0x40000da0; -r_ble_ll_adv_sm_event_init = 0x40000da4; -r_ble_ll_adv_sm_event_restore = 0x40000da8; -r_ble_ll_adv_sm_event_store = 0x40000dac; -r_ble_ll_adv_sm_find_configured = 0x40000db0; -r_ble_ll_adv_sm_get = 0x40000db4; -r_ble_ll_adv_sm_init = 0x40000db8; -r_ble_ll_adv_sm_reset = 0x40000dbc; -r_ble_ll_adv_sm_start = 0x40000dc0; -r_ble_ll_adv_sm_start_periodic = 0x40000dc4; -r_ble_ll_adv_sm_stop = 0x40000dc8; -r_ble_ll_adv_sm_stop_limit_reached = 0x40000dcc; -r_ble_ll_adv_sm_stop_periodic = 0x40000dd0; -r_ble_ll_adv_sm_stop_timeout = 0x40000dd4; -r_ble_ll_adv_sync_calculate = 0x40000dd8; -r_ble_ll_adv_sync_get_pdu_len = 0x40000ddc; -r_ble_ll_adv_sync_next_scheduled = 0x40000de0; -r_ble_ll_adv_sync_pdu_make = 0x40000de4; -r_ble_ll_adv_sync_schedule = 0x40000de8; -r_ble_ll_adv_sync_tx_done = 0x40000dec; -r_ble_ll_adv_sync_tx_end = 0x40000df0; -r_ble_ll_adv_sync_tx_start_cb = 0x40000df4; -r_ble_ll_adv_tx_done = 0x40000df8; -r_ble_ll_adv_tx_start_cb = 0x40000dfc; -r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000e00; -r_ble_ll_adv_update_data_mbuf = 0x40000e04; -r_ble_ll_adv_update_did = 0x40000e08; -r_ble_ll_adv_update_periodic_data = 0x40000e0c; -r_ble_ll_adv_update_rsp_offset = 0x40000e10; -r_ble_ll_adv_wfr_timer_exp = 0x40000e14; -r_ble_ll_arr_pool_init = 0x40000e18; -r_ble_ll_auth_pyld_tmo_event_send = 0x40000e1c; -r_ble_ll_aux_scan_cb = 0x40000e20; -r_ble_ll_aux_scan_drop = 0x40000e24; -r_ble_ll_aux_scan_drop_event_cb = 0x40000e28; -r_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000e2c; -r_ble_ll_calc_session_key = 0x40000e30; -r_ble_ll_calc_ticks_per_slot = 0x40000e34; -r_ble_ll_calc_us_convert_tick_unit = 0x40000e38; -r_ble_ll_check_scan_params = 0x40000e3c; -r_ble_ll_chk_txrx_octets = 0x40000e40; -r_ble_ll_chk_txrx_time = 0x40000e44; -r_ble_ll_conn_adjust_pyld_len = 0x40000e48; -r_ble_ll_conn_auth_pyld_timer_cb = 0x40000e4c; -r_ble_ll_conn_auth_pyld_timer_start = 0x40000e50; -r_ble_ll_conn_calc_dci = 0x40000e54; -r_ble_ll_conn_calc_dci_csa1 = 0x40000e58; -r_ble_ll_conn_calc_itvl_ticks = 0x40000e5c; -r_ble_ll_conn_can_send_next_pdu = 0x40000e60; -r_ble_ll_conn_chk_csm_flags = 0x40000e64; -r_ble_ll_conn_chk_phy_upd_start = 0x40000e68; -r_ble_ll_conn_coex_dpc_process = 0x40000e6c; -r_ble_ll_conn_coex_dpc_pti_get = 0x40000e70; -r_ble_ll_conn_coex_dpc_update = 0x40000e74; -r_ble_ll_conn_coex_dpc_update_on_event_scheduled = 0x40000e78; -r_ble_ll_conn_comp_event_send = 0x40000e7c; -r_ble_ll_conn_connect_ind_pdu_make = 0x40000e80; -r_ble_ll_conn_create = 0x40000e84; -r_ble_ll_conn_create_cancel = 0x40000e88; -r_ble_ll_conn_created = 0x40000e8c; -r_ble_ll_conn_cth_flow_alloc_credit = 0x40000e90; -r_ble_ll_conn_cth_flow_enable = 0x40000e94; -r_ble_ll_conn_cth_flow_error_fn = 0x40000e98; -r_ble_ll_conn_cth_flow_free_credit = 0x40000e9c; -r_ble_ll_conn_cth_flow_have_credit = 0x40000ea0; -r_ble_ll_conn_cth_flow_is_enabled = 0x40000ea4; -r_ble_ll_conn_cth_flow_process_cmd = 0x40000ea8; -r_ble_ll_conn_cth_flow_set_buffers = 0x40000eac; -r_ble_ll_conn_cur_pducb = 0x40000eb0; -r_ble_ll_conn_current_sm_over = 0x40000eb4; -r_ble_ll_conn_end = 0x40000eb8; -r_ble_ll_conn_enqueue_pkt = 0x40000ebc; -r_ble_ll_conn_env_init = 0x40000ec0; -r_ble_ll_conn_event_end = 0x40000ec4; -r_ble_ll_conn_event_end_timer_cb = 0x40000ec8; -r_ble_ll_conn_event_halt = 0x40000ecc; -r_ble_ll_conn_event_is_over = 0x40000ed0; -r_ble_ll_conn_event_start_cb = 0x40000ed4; -r_ble_ll_conn_ext_master_init = 0x40000ed8; -r_ble_ll_conn_ext_set_params = 0x40000edc; -r_ble_ll_conn_find_active_conn = 0x40000ee0; -r_ble_ll_conn_get_anchor = 0x40000ee4; -r_ble_ll_conn_get_ce_end_time = 0x40000ee8; -r_ble_ll_conn_get_new_pdu = 0x40000eec; -r_ble_ll_conn_get_next_sched_time = 0x40000ef0; -r_ble_ll_conn_halt = 0x40000ef4; -r_ble_ll_conn_hcc_params_set_fallback = 0x40000ef8; -r_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000efc; -r_ble_ll_conn_hci_chk_conn_params = 0x40000f00; -r_ble_ll_conn_hci_chk_scan_params = 0x40000f04; -r_ble_ll_conn_hci_disconnect_cmd = 0x40000f08; -r_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000f0c; -r_ble_ll_conn_hci_le_ltk_reply = 0x40000f10; -r_ble_ll_conn_hci_le_rd_phy = 0x40000f14; -r_ble_ll_conn_hci_le_set_phy = 0x40000f18; -r_ble_ll_conn_hci_le_start_encrypt = 0x40000f1c; -r_ble_ll_conn_hci_param_nrr = 0x40000f20; -r_ble_ll_conn_hci_param_rr = 0x40000f24; -r_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000f28; -r_ble_ll_conn_hci_rd_chan_map = 0x40000f2c; -r_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000f30; -r_ble_ll_conn_hci_rd_rssi = 0x40000f34; -r_ble_ll_conn_hci_read_rem_features = 0x40000f38; -r_ble_ll_conn_hci_set_chan_class = 0x40000f3c; -r_ble_ll_conn_hci_set_data_len = 0x40000f40; -r_ble_ll_conn_hci_update = 0x40000f44; -r_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000f48; -r_ble_ll_conn_init_pending_aux_conn_rsp = 0x40000f4c; -r_ble_ll_conn_init_phy = 0x40000f50; -r_ble_ll_conn_init_wfr_timer_exp = 0x40000f54; -r_ble_ll_conn_is_empty_pdu = 0x40000f58; -r_ble_ll_conn_is_lru = 0x40000f5c; -r_ble_ll_conn_master_common_init = 0x40000f60; -r_ble_ll_conn_master_init = 0x40000f64; -r_ble_ll_conn_module_deinit = 0x40000f68; -r_ble_ll_conn_module_init = 0x40000f6c; -r_ble_ll_conn_module_reset = 0x40000f70; -r_ble_ll_conn_new_pducb = 0x40000f74; -r_ble_ll_conn_next_event = 0x40000f78; -r_ble_ll_conn_num_comp_pkts_event_send = 0x40000f7c; -r_ble_ll_conn_process_conn_params = 0x40000f80; -r_ble_ll_conn_recv_ack = 0x40000f84; -r_ble_ll_conn_reset_pending_aux_conn_rsp = 0x40000f88; -r_ble_ll_conn_rx_data_pdu = 0x40000f8c; -r_ble_ll_conn_rx_isr_end = 0x40000f90; -r_ble_ll_conn_rx_isr_start = 0x40000f94; -r_ble_ll_conn_rxend_unencrypt = 0x40000f98; -r_ble_ll_conn_set_csa = 0x40000f9c; -r_ble_ll_conn_set_global_chanmap = 0x40000fa0; -r_ble_ll_conn_set_md_flag = 0x40000fa4; -r_ble_ll_conn_set_phy = 0x40000fa8; -r_ble_ll_conn_set_slave_flow_control = 0x40000fac; -r_ble_ll_conn_set_txpwr_by_handle = 0x40000fb0; -r_ble_ll_conn_set_unknown_rx_octets = 0x40000fb4; -r_ble_ll_conn_slave_start = 0x40000fb8; -r_ble_ll_conn_sm_get = 0x40000fbc; -r_ble_ll_conn_sm_new = 0x40000fc0; -r_ble_ll_conn_sm_npl_deinit = 0x40000fc4; -r_ble_ll_conn_sm_npl_init = 0x40000fc8; -r_ble_ll_conn_start_rx_encrypt = 0x40000fcc; -r_ble_ll_conn_start_rx_unencrypt = 0x40000fd0; -r_ble_ll_conn_timeout = 0x40000fd4; -r_ble_ll_conn_tx_pdu = 0x40000fd8; -r_ble_ll_conn_tx_pkt_in = 0x40000fdc; -r_ble_ll_conn_txend_encrypt = 0x40000fe0; -r_ble_ll_conn_update_conn_params = 0x40000fe4; -r_ble_ll_conn_update_eff_data_len = 0x40000fe8; -r_ble_ll_conn_update_new_pdu_len = 0x40000fec; -r_ble_ll_conn_wait_txend = 0x40000ff0; -r_ble_ll_conn_wfr_timer_exp = 0x40000ff4; -r_ble_ll_copy_data = 0x40000ff8; -r_ble_ll_ctrl_chanmap_req_make = 0x40000ffc; -r_ble_ll_ctrl_chk_proc_start = 0x40001000; -r_ble_ll_ctrl_conn_param_pdu_make = 0x40001004; -r_ble_ll_ctrl_conn_param_pdu_proc = 0x40001008; -r_ble_ll_ctrl_conn_param_reply = 0x4000100c; -r_ble_ll_ctrl_conn_upd_make = 0x40001010; -r_ble_ll_ctrl_datalen_upd_make = 0x40001014; -r_ble_ll_ctrl_enc_allowed_pdu = 0x40001018; -r_ble_ll_ctrl_enc_allowed_pdu_rx = 0x4000101c; -r_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40001020; -r_ble_ll_ctrl_enc_req_make = 0x40001024; -r_ble_ll_ctrl_find_new_phy = 0x40001028; -r_ble_ll_ctrl_initiate_dle = 0x4000102c; -r_ble_ll_ctrl_is_start_enc_rsp = 0x40001030; -r_ble_ll_ctrl_is_terminate_ind = 0x40001034; -r_ble_ll_ctrl_len_proc = 0x40001038; -r_ble_ll_ctrl_phy_from_phy_mask = 0x4000103c; -r_ble_ll_ctrl_phy_req_rsp_make = 0x40001040; -r_ble_ll_ctrl_phy_tx_transition_get = 0x40001044; -r_ble_ll_ctrl_phy_update_cancel = 0x40001048; -r_ble_ll_ctrl_phy_update_ind_make = 0x4000104c; -r_ble_ll_ctrl_phy_update_proc_complete = 0x40001050; -r_ble_ll_ctrl_proc_init = 0x40001054; -r_ble_ll_ctrl_proc_rsp_timer_cb = 0x40001058; -r_ble_ll_ctrl_proc_start = 0x4000105c; -r_ble_ll_ctrl_proc_stop = 0x40001060; -r_ble_ll_ctrl_proc_unk_rsp = 0x40001064; -r_ble_ll_ctrl_proc_with_instant_initiated = 0x40001068; -r_ble_ll_ctrl_rej_ext_ind_make = 0x4000106c; -r_ble_ll_ctrl_reject_ind_send = 0x40001070; -r_ble_ll_ctrl_rx_chanmap_req = 0x40001074; -r_ble_ll_ctrl_rx_conn_param_req = 0x40001078; -r_ble_ll_ctrl_rx_conn_param_rsp = 0x4000107c; -r_ble_ll_ctrl_rx_conn_update = 0x40001080; -r_ble_ll_ctrl_rx_enc_req = 0x40001084; -r_ble_ll_ctrl_rx_enc_rsp = 0x40001088; -r_ble_ll_ctrl_rx_feature_req = 0x4000108c; -r_ble_ll_ctrl_rx_feature_rsp = 0x40001090; -r_ble_ll_ctrl_rx_pause_enc_req = 0x40001094; -r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40001098; -r_ble_ll_ctrl_rx_pdu = 0x4000109c; -r_ble_ll_ctrl_rx_periodic_sync_ind = 0x400010a0; -r_ble_ll_ctrl_rx_phy_req = 0x400010a4; -r_ble_ll_ctrl_rx_phy_rsp = 0x400010a8; -r_ble_ll_ctrl_rx_phy_update_ind = 0x400010ac; -r_ble_ll_ctrl_rx_ping_rsp = 0x400010b0; -r_ble_ll_ctrl_rx_reject_ind = 0x400010b4; -r_ble_ll_ctrl_rx_start_enc_req = 0x400010b8; -r_ble_ll_ctrl_rx_start_enc_rsp = 0x400010bc; -r_ble_ll_ctrl_rx_version_ind = 0x400010c0; -r_ble_ll_ctrl_start_enc_send = 0x400010c4; -r_ble_ll_ctrl_start_rsp_timer = 0x400010c8; -r_ble_ll_ctrl_terminate_start = 0x400010cc; -r_ble_ll_ctrl_tx_done = 0x400010d0; -r_ble_ll_ctrl_update_features = 0x400010d4; -r_ble_ll_ctrl_version_ind_make = 0x400010d8; -r_ble_ll_data_buffer_overflow = 0x400010dc; -r_ble_ll_deinit = 0x400010e0; -r_ble_ll_disconn_comp_event_send = 0x400010e4; -r_ble_ll_dtm_calculate_itvl = 0x400010e8; -r_ble_ll_dtm_ctx_free = 0x400010ec; -r_ble_ll_dtm_deinit = 0x400010f0; -r_ble_ll_dtm_end_test = 0x400010f4; -r_ble_ll_dtm_ev_rx_restart_cb = 0x400010f8; -r_ble_ll_dtm_ev_tx_resched_cb = 0x400010fc; -r_ble_ll_dtm_init = 0x40001100; -r_ble_ll_dtm_reset = 0x40001104; -r_ble_ll_dtm_rx_create_ctx = 0x40001108; -r_ble_ll_dtm_rx_isr_end = 0x4000110c; -r_ble_ll_dtm_rx_isr_start = 0x40001110; -r_ble_ll_dtm_rx_pkt_in = 0x40001114; -r_ble_ll_dtm_rx_sched_cb = 0x40001118; -r_ble_ll_dtm_rx_start = 0x4000111c; -r_ble_ll_dtm_rx_test = 0x40001120; -r_ble_ll_dtm_set_next = 0x40001124; -r_ble_ll_dtm_tx_create_ctx = 0x40001128; -r_ble_ll_dtm_tx_done = 0x4000112c; -r_ble_ll_dtm_tx_sched_cb = 0x40001130; -r_ble_ll_dtm_tx_test = 0x40001134; -r_ble_ll_dtm_wfr_timer_exp = 0x40001138; -r_ble_ll_env_init = 0x4000113c; -r_ble_ll_event_comp_pkts = 0x40001140; -r_ble_ll_event_dbuf_overflow = 0x40001144; -r_ble_ll_event_rx_pkt = 0x40001148; -r_ble_ll_event_send = 0x4000114c; -r_ble_ll_event_tx_pkt = 0x40001150; -r_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40001154; -r_ble_ll_ext_conn_create = 0x40001158; -r_ble_ll_ext_scan_coex_dpc_process = 0x4000115c; -r_ble_ll_ext_scan_coex_dpc_pti_get = 0x40001160; -r_ble_ll_ext_scan_coex_dpc_update = 0x40001164; -r_ble_ll_ext_scan_coex_dpc_update_on_start = 0x40001168; -r_ble_ll_ext_scan_parse_adv_info = 0x4000116c; -r_ble_ll_ext_scan_parse_aux_ptr = 0x40001170; -r_ble_ll_flush_pkt_queue = 0x40001174; -r_ble_ll_generic_data_init = 0x40001178; -r_ble_ll_get_addr_type = 0x4000117c; -r_ble_ll_get_chan_to_scan = 0x40001180; -r_ble_ll_get_our_devaddr = 0x40001184; -r_ble_ll_get_tx_pwr_compensation = 0x40001188; -r_ble_ll_hci_acl_rx = 0x4000118c; -r_ble_ll_hci_adv_mode_ext = 0x40001190; -r_ble_ll_hci_adv_set_enable = 0x40001194; -r_ble_ll_hci_cb_host_buf_size = 0x40001198; -r_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x4000119c; -r_ble_ll_hci_cb_set_event_mask = 0x400011a0; -r_ble_ll_hci_cb_set_event_mask2 = 0x400011a4; -r_ble_ll_hci_chk_phy_masks = 0x400011a8; -r_ble_ll_hci_cmd_proc = 0x400011ac; -r_ble_ll_hci_cmd_rx = 0x400011b0; -r_ble_ll_hci_ctlr_bb_cmd_proc = 0x400011b4; -r_ble_ll_hci_deinit = 0x400011b8; -r_ble_ll_hci_disconnect = 0x400011bc; -r_ble_ll_hci_dtm_rx_test = 0x400011c0; -r_ble_ll_hci_dtm_rx_test_v2 = 0x400011c4; -r_ble_ll_hci_dtm_tx_test = 0x400011c8; -r_ble_ll_hci_dtm_tx_test_ext = 0x400011cc; -r_ble_ll_hci_dtm_tx_test_v2 = 0x400011d0; -r_ble_ll_hci_dtm_tx_test_v2_ext = 0x400011d4; -r_ble_ll_hci_env_init = 0x400011d8; -r_ble_ll_hci_ev_conn_update = 0x400011dc; -r_ble_ll_hci_ev_databuf_overflow = 0x400011e0; -r_ble_ll_hci_ev_datalen_chg = 0x400011e4; -r_ble_ll_hci_ev_encrypt_chg = 0x400011e8; -r_ble_ll_hci_ev_hw_err = 0x400011ec; -r_ble_ll_hci_ev_le_csa = 0x400011f0; -r_ble_ll_hci_ev_ltk_req = 0x400011f4; -r_ble_ll_hci_ev_phy_update = 0x400011f8; -r_ble_ll_hci_ev_rd_rem_used_feat = 0x400011fc; -r_ble_ll_hci_ev_rd_rem_ver = 0x40001200; -r_ble_ll_hci_ev_rem_conn_parm_req = 0x40001204; -r_ble_ll_hci_ev_send_adv_set_terminated = 0x40001208; -r_ble_ll_hci_ev_send_scan_req_recv = 0x4000120c; -r_ble_ll_hci_ev_send_scan_timeout = 0x40001210; -r_ble_ll_hci_ev_send_vendor_err = 0x40001214; -r_ble_ll_hci_event_send = 0x40001218; -r_ble_ll_hci_ext_scan_set_enable = 0x4000121c; -r_ble_ll_hci_get_num_cmd_pkts = 0x40001220; -r_ble_ll_hci_info_params_cmd_proc = 0x40001224; -r_ble_ll_hci_init = 0x40001228; -r_ble_ll_hci_is_event_enabled = 0x4000122c; -r_ble_ll_hci_is_le_event_enabled = 0x40001230; -r_ble_ll_hci_le_cmd_proc = 0x40001234; -r_ble_ll_hci_le_cmd_send_cmd_status = 0x40001238; -r_ble_ll_hci_le_encrypt = 0x4000123c; -r_ble_ll_hci_le_rand = 0x40001240; -r_ble_ll_hci_le_rd_max_data_len = 0x40001244; -r_ble_ll_hci_le_rd_sugg_data_len = 0x40001248; -r_ble_ll_hci_le_read_bufsize = 0x4000124c; -r_ble_ll_hci_le_read_local_features = 0x40001250; -r_ble_ll_hci_le_read_supp_states = 0x40001254; -r_ble_ll_hci_le_set_def_phy = 0x40001258; -r_ble_ll_hci_le_wr_sugg_data_len = 0x4000125c; -r_ble_ll_hci_link_ctrl_cmd_proc = 0x40001260; -r_ble_ll_hci_npl_init = 0x40001264; -r_ble_ll_hci_rd_bd_addr = 0x40001268; -r_ble_ll_hci_rd_local_supp_cmd = 0x4000126c; -r_ble_ll_hci_rd_local_supp_feat = 0x40001270; -r_ble_ll_hci_rd_local_version = 0x40001274; -r_ble_ll_hci_scan_set_enable = 0x40001278; -r_ble_ll_hci_send_adv_report = 0x4000127c; -r_ble_ll_hci_send_dir_adv_report = 0x40001280; -r_ble_ll_hci_send_ext_adv_report = 0x40001284; -r_ble_ll_hci_send_legacy_ext_adv_report = 0x40001288; -r_ble_ll_hci_send_noop = 0x4000128c; -r_ble_ll_hci_set_adv_data = 0x40001290; -r_ble_ll_hci_set_le_event_mask = 0x40001294; -r_ble_ll_hci_set_scan_rsp_data = 0x40001298; -r_ble_ll_hci_status_params_cmd_proc = 0x4000129c; -r_ble_ll_hci_vs_cmd_proc = 0x400012a0; -r_ble_ll_hci_vs_rd_static_addr = 0x400012a4; -r_ble_ll_hw_err_timer_cb = 0x400012a8; -r_ble_ll_hw_error = 0x400012ac; -r_ble_ll_init = 0x400012b0; -r_ble_ll_init_alloc_conn_comp_ev = 0x400012b4; -r_ble_ll_init_get_conn_comp_ev = 0x400012b8; -r_ble_ll_init_rx_isr_end = 0x400012bc; -r_ble_ll_init_rx_isr_start = 0x400012c0; -r_ble_ll_init_rx_pkt_in = 0x400012c4; -r_ble_ll_is_addr_empty = 0x400012c8; -r_ble_ll_is_controller_busy = 0x400012cc; -r_ble_ll_is_on_resolv_list = 0x400012d0; -r_ble_ll_is_our_devaddr = 0x400012d4; -r_ble_ll_is_rpa = 0x400012d8; -r_ble_ll_is_valid_adv_mode = 0x400012dc; -r_ble_ll_is_valid_own_addr_type = 0x400012e0; -r_ble_ll_is_valid_public_addr = 0x400012e4; -r_ble_ll_is_valid_random_addr = 0x400012e8; -r_ble_ll_mbuf_init = 0x400012ec; -r_ble_ll_misc_options_set = 0x400012f0; -r_ble_ll_pdu_max_tx_octets_get = 0x400012f4; -r_ble_ll_pdu_tx_time_get = 0x400012f8; -r_ble_ll_per_adv_coex_dpc_calc_pti_update_itvl = 0x400012fc; -r_ble_ll_per_adv_coex_dpc_process = 0x40001300; -r_ble_ll_per_adv_coex_dpc_pti_get = 0x40001304; -r_ble_ll_per_adv_coex_dpc_update = 0x40001308; -r_ble_ll_per_adv_coex_dpc_update_on_data_updated = 0x4000130c; -r_ble_ll_per_adv_coex_dpc_update_on_scheduled = 0x40001310; -r_ble_ll_per_adv_coex_dpc_update_on_start = 0x40001314; -r_ble_ll_phy_to_phy_mode = 0x40001318; -r_ble_ll_process_rx_data = 0x4000131c; -r_ble_ll_qa_enable = 0x40001320; -r_ble_ll_rand = 0x40001324; -r_ble_ll_rand_data_get = 0x40001328; -r_ble_ll_rand_deinit = 0x4000132c; -r_ble_ll_rand_env_init = 0x40001330; -r_ble_ll_rand_init = 0x40001334; -r_ble_ll_rand_prand_get = 0x40001338; -r_ble_ll_rand_sample = 0x4000133c; -r_ble_ll_rand_start = 0x40001340; -r_ble_ll_read_rf_path_compensation = 0x40001344; -r_ble_ll_read_supp_features = 0x40001348; -r_ble_ll_read_supp_states = 0x4000134c; -r_ble_ll_read_tx_power = 0x40001350; -r_ble_ll_reset = 0x40001354; -r_ble_ll_resolv_clear_all_pl_bit = 0x40001358; -r_ble_ll_resolv_clear_all_wl_bit = 0x4000135c; -r_ble_ll_resolv_deinit = 0x40001360; -r_ble_ll_resolv_enable_cmd = 0x40001364; -r_ble_ll_resolv_enabled = 0x40001368; -r_ble_ll_resolv_env_init = 0x4000136c; -r_ble_ll_resolv_gen_priv_addr = 0x40001370; -r_ble_ll_resolv_gen_rpa = 0x40001374; -r_ble_ll_resolv_get_addr_pointer = 0x40001378; -r_ble_ll_resolv_get_entry = 0x4000137c; -r_ble_ll_resolv_get_index = 0x40001380; -r_ble_ll_resolv_get_irk_pointer = 0x40001384; -r_ble_ll_resolv_get_list = 0x40001388; -r_ble_ll_resolv_get_priv_addr = 0x4000138c; -r_ble_ll_resolv_get_rpa_tmo = 0x40001390; -r_ble_ll_resolv_init = 0x40001394; -r_ble_ll_resolv_irk_nonzero = 0x40001398; -r_ble_ll_resolv_list_add = 0x4000139c; -r_ble_ll_resolv_list_chg_allowed = 0x400013a0; -r_ble_ll_resolv_list_clr = 0x400013a4; -r_ble_ll_resolv_list_find = 0x400013a8; -r_ble_ll_resolv_list_read_size = 0x400013ac; -r_ble_ll_resolv_list_reset = 0x400013b0; -r_ble_ll_resolv_list_rmv = 0x400013b4; -r_ble_ll_resolv_local_addr_rd = 0x400013b8; -r_ble_ll_resolv_peer_addr_rd = 0x400013bc; -r_ble_ll_resolv_peer_rpa_any = 0x400013c0; -r_ble_ll_resolv_reset = 0x400013c4; -r_ble_ll_resolv_rpa = 0x400013c8; -r_ble_ll_resolv_rpa_timer_cb = 0x400013cc; -r_ble_ll_resolv_set_local_rpa = 0x400013d0; -r_ble_ll_resolv_set_peer_rpa = 0x400013d4; -r_ble_ll_resolv_set_rpa_tmo = 0x400013d8; -r_ble_ll_resolve_set_priv_mode = 0x400013dc; -r_ble_ll_rfmgmt_controller_sleep_en = 0x400013e0; -r_ble_ll_rfmgmt_deinit = 0x400013e4; -r_ble_ll_rfmgmt_disable = 0x400013e8; -r_ble_ll_rfmgmt_enable = 0x400013ec; -r_ble_ll_rfmgmt_enable_now = 0x400013f0; -r_ble_ll_rfmgmt_init = 0x400013f4; -r_ble_ll_rfmgmt_is_enabled = 0x400013f8; -r_ble_ll_rfmgmt_release = 0x400013fc; -r_ble_ll_rfmgmt_release_ev = 0x40001400; -r_ble_ll_rfmgmt_reset = 0x40001404; -r_ble_ll_rfmgmt_scan_changed = 0x40001408; -r_ble_ll_rfmgmt_sched_changed = 0x4000140c; -r_ble_ll_rfmgmt_set_sleep_cb = 0x40001410; -r_ble_ll_rfmgmt_ticks_to_enabled = 0x40001414; -r_ble_ll_rfmgmt_timer_exp = 0x40001418; -r_ble_ll_rfmgmt_timer_reschedule = 0x4000141c; -r_ble_ll_rx_end = 0x40001420; -r_ble_ll_rx_pdu_in = 0x40001424; -r_ble_ll_rx_pkt_in = 0x40001428; -r_ble_ll_rx_start = 0x4000142c; -r_ble_ll_rxpdu_alloc = 0x40001430; -r_ble_ll_scan_add_scan_rsp_adv = 0x40001434; -r_ble_ll_scan_adv_decode_addr = 0x40001438; -r_ble_ll_scan_aux_data_free = 0x4000143c; -r_ble_ll_scan_aux_data_ref = 0x40001440; -r_ble_ll_scan_aux_data_unref = 0x40001444; -r_ble_ll_scan_can_chg_whitelist = 0x40001448; -r_ble_ll_scan_check_periodic_sync = 0x4000144c; -r_ble_ll_scan_chk_resume = 0x40001450; -r_ble_ll_scan_clean_cur_aux_data = 0x40001454; -r_ble_ll_scan_common_init = 0x40001458; -r_ble_ll_scan_continue_en = 0x4000145c; -r_ble_ll_scan_deinit = 0x40001460; -r_ble_ll_scan_dup_check_ext = 0x40001464; -r_ble_ll_scan_dup_check_legacy = 0x40001468; -r_ble_ll_scan_dup_move_to_head = 0x4000146c; -r_ble_ll_scan_dup_new = 0x40001470; -r_ble_ll_scan_dup_update_ext = 0x40001474; -r_ble_ll_scan_dup_update_legacy = 0x40001478; -r_ble_ll_scan_duration_period_timers_restart = 0x4000147c; -r_ble_ll_scan_duration_timer_cb = 0x40001480; -r_ble_ll_scan_enabled = 0x40001484; -r_ble_ll_scan_end_adv_evt = 0x40001488; -r_ble_ll_scan_env_init = 0x4000148c; -r_ble_ll_scan_event_proc = 0x40001490; -r_ble_ll_scan_ext_adv_init = 0x40001494; -r_ble_ll_scan_ext_initiator_start = 0x40001498; -r_ble_ll_scan_get_addr_data_from_legacy = 0x4000149c; -r_ble_ll_scan_get_addr_from_ext_adv = 0x400014a0; -r_ble_ll_scan_get_cur_sm = 0x400014a4; -r_ble_ll_scan_get_ext_adv_report = 0x400014a8; -r_ble_ll_scan_get_local_rpa = 0x400014ac; -r_ble_ll_scan_get_next_adv_prim_chan = 0x400014b0; -r_ble_ll_scan_get_pdu_data = 0x400014b4; -r_ble_ll_scan_get_peer_rpa = 0x400014b8; -r_ble_ll_scan_halt = 0x400014bc; -r_ble_ll_scan_has_sent_scan_req = 0x400014c0; -r_ble_ll_scan_have_rxd_scan_rsp = 0x400014c4; -r_ble_ll_scan_init = 0x400014c8; -r_ble_ll_scan_initiator_start = 0x400014cc; -r_ble_ll_scan_interrupted = 0x400014d0; -r_ble_ll_scan_interrupted_event_cb = 0x400014d4; -r_ble_ll_scan_is_inside_window = 0x400014d8; -r_ble_ll_scan_move_window_to = 0x400014dc; -r_ble_ll_scan_npl_init = 0x400014e0; -r_ble_ll_scan_npl_reset = 0x400014e4; -r_ble_ll_scan_npl_restore = 0x400014e8; -r_ble_ll_scan_npl_store = 0x400014ec; -r_ble_ll_scan_parse_ext_hdr = 0x400014f0; -r_ble_ll_scan_period_timer_cb = 0x400014f4; -r_ble_ll_scan_record_new_adv = 0x400014f8; -r_ble_ll_scan_refresh_nrpa = 0x400014fc; -r_ble_ll_scan_req_backoff = 0x40001500; -r_ble_ll_scan_reset = 0x40001504; -r_ble_ll_scan_rx_filter = 0x40001508; -r_ble_ll_scan_rx_isr_end = 0x4000150c; -r_ble_ll_scan_rx_isr_on_aux = 0x40001510; -r_ble_ll_scan_rx_isr_on_legacy = 0x40001514; -r_ble_ll_scan_rx_isr_start = 0x40001518; -r_ble_ll_scan_rx_pkt_in = 0x4000151c; -r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001520; -r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001524; -r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001528; -r_ble_ll_scan_rxed = 0x4000152c; -r_ble_ll_scan_sched_remove = 0x40001530; -r_ble_ll_scan_send_adv_report = 0x40001534; -r_ble_ll_scan_send_truncated = 0x40001538; -r_ble_ll_scan_set_enable = 0x4000153c; -r_ble_ll_scan_set_peer_rpa = 0x40001540; -r_ble_ll_scan_set_scan_params = 0x40001544; -r_ble_ll_scan_sm_start = 0x40001548; -r_ble_ll_scan_sm_stop = 0x4000154c; -r_ble_ll_scan_start = 0x40001550; -r_ble_ll_scan_time_hci_to_ticks = 0x40001554; -r_ble_ll_scan_timer_cb = 0x40001558; -r_ble_ll_scan_update_aux_data = 0x4000155c; -r_ble_ll_scan_wfr_timer_exp = 0x40001560; -r_ble_ll_scan_whitelist_enabled = 0x40001564; -r_ble_ll_sched_adv_new = 0x40001568; -r_ble_ll_sched_adv_resched_pdu = 0x4000156c; -r_ble_ll_sched_adv_reschedule = 0x40001570; -r_ble_ll_sched_aux_scan = 0x40001574; -r_ble_ll_sched_conn_overlap = 0x40001578; -r_ble_ll_sched_conn_reschedule = 0x4000157c; -r_ble_ll_sched_deinit = 0x40001580; -r_ble_ll_sched_dtm = 0x40001584; -r_ble_ll_sched_env_init = 0x40001588; -r_ble_ll_sched_execute_item = 0x4000158c; -r_ble_ll_sched_init = 0x40001590; -r_ble_ll_sched_insert_if_empty = 0x40001594; -r_ble_ll_sched_is_overlap = 0x40001598; -r_ble_ll_sched_master_new = 0x4000159c; -r_ble_ll_sched_next_time = 0x400015a0; -r_ble_ll_sched_overlaps_current = 0x400015a4; -r_ble_ll_sched_periodic_adv = 0x400015a8; -r_ble_ll_sched_rmv_elem = 0x400015ac; -r_ble_ll_sched_rmv_elem_type = 0x400015b0; -r_ble_ll_sched_run = 0x400015b4; -r_ble_ll_sched_scan_req_over_aux_ptr = 0x400015b8; -r_ble_ll_sched_slave_new = 0x400015bc; -r_ble_ll_sched_stop = 0x400015c0; -r_ble_ll_sched_sync = 0x400015c4; -r_ble_ll_sched_sync_overlaps_current = 0x400015c8; -r_ble_ll_sched_sync_reschedule = 0x400015cc; -r_ble_ll_set_default_privacy_mode = 0x400015d0; -r_ble_ll_set_default_sync_transfer_params = 0x400015d4; -r_ble_ll_set_ext_scan_params = 0x400015d8; -r_ble_ll_set_host_feat = 0x400015dc; -r_ble_ll_set_public_addr = 0x400015e0; -r_ble_ll_set_random_addr = 0x400015e4; -r_ble_ll_set_sync_transfer_params = 0x400015e8; -r_ble_ll_slave_rx_isr_end = 0x400015ec; -r_ble_ll_state_get = 0x400015f0; -r_ble_ll_state_set = 0x400015f4; -r_ble_ll_sync_adjust_ext_hdr = 0x400015f8; -r_ble_ll_sync_cancel = 0x400015fc; -r_ble_ll_sync_cancel_complete_event = 0x40001600; -r_ble_ll_sync_chain_start_cb = 0x40001604; -r_ble_ll_sync_check_acad = 0x40001608; -r_ble_ll_sync_check_failed = 0x4000160c; -r_ble_ll_sync_coex_dpc_process = 0x40001610; -r_ble_ll_sync_coex_dpc_pti_get = 0x40001614; -r_ble_ll_sync_coex_dpc_update = 0x40001618; -r_ble_ll_sync_create = 0x4000161c; -r_ble_ll_sync_current_sm_over = 0x40001620; -r_ble_ll_sync_deinit = 0x40001624; -r_ble_ll_sync_enabled = 0x40001628; -r_ble_ll_sync_env_init = 0x4000162c; -r_ble_ll_sync_est_event_failed = 0x40001630; -r_ble_ll_sync_est_event_success = 0x40001634; -r_ble_ll_sync_established = 0x40001638; -r_ble_ll_sync_event_end = 0x4000163c; -r_ble_ll_sync_event_start_cb = 0x40001640; -r_ble_ll_sync_filter_enabled = 0x40001644; -r_ble_ll_sync_find = 0x40001648; -r_ble_ll_sync_get_cur_sm = 0x4000164c; -r_ble_ll_sync_get_event_end_time = 0x40001650; -r_ble_ll_sync_get_handle = 0x40001654; -r_ble_ll_sync_halt = 0x40001658; -r_ble_ll_sync_has_been_reported = 0x4000165c; -r_ble_ll_sync_info_event = 0x40001660; -r_ble_ll_sync_init = 0x40001664; -r_ble_ll_sync_list_add = 0x40001668; -r_ble_ll_sync_list_clear = 0x4000166c; -r_ble_ll_sync_list_empty = 0x40001670; -r_ble_ll_sync_list_get_free = 0x40001674; -r_ble_ll_sync_list_remove = 0x40001678; -r_ble_ll_sync_list_search = 0x4000167c; -r_ble_ll_sync_list_size = 0x40001680; -r_ble_ll_sync_lost_event = 0x40001684; -r_ble_ll_sync_next_event = 0x40001688; -r_ble_ll_sync_on_list = 0x4000168c; -r_ble_ll_sync_parse_aux_ptr = 0x40001690; -r_ble_ll_sync_parse_ext_hdr = 0x40001694; -r_ble_ll_sync_periodic_ind = 0x40001698; -r_ble_ll_sync_phy_mode_to_aux_phy = 0x4000169c; -r_ble_ll_sync_phy_mode_to_hci = 0x400016a0; -r_ble_ll_sync_put_syncinfo = 0x400016a4; -r_ble_ll_sync_reserve = 0x400016a8; -r_ble_ll_sync_reset = 0x400016ac; -r_ble_ll_sync_reset_sm = 0x400016b0; -r_ble_ll_sync_rmvd_from_sched = 0x400016b4; -r_ble_ll_sync_rx_isr_end = 0x400016b8; -r_ble_ll_sync_rx_isr_start = 0x400016bc; -r_ble_ll_sync_rx_pkt_in = 0x400016c0; -r_ble_ll_sync_schedule_chain = 0x400016c4; -r_ble_ll_sync_send_per_adv_rpt = 0x400016c8; -r_ble_ll_sync_send_sync_ind = 0x400016cc; -r_ble_ll_sync_send_truncated_per_adv_rpt = 0x400016d0; -r_ble_ll_sync_sm_clear = 0x400016d4; -r_ble_ll_sync_terminate = 0x400016d8; -r_ble_ll_sync_transfer = 0x400016dc; -r_ble_ll_sync_transfer_get = 0x400016e0; -r_ble_ll_sync_transfer_received = 0x400016e4; -r_ble_ll_sync_wfr_timer_exp = 0x400016e8; -r_ble_ll_task = 0x400016ec; -r_ble_ll_trace_set_func = 0x400016f0; -r_ble_ll_trace_u32 = 0x400016f4; -r_ble_ll_trace_u32x2 = 0x400016f8; -r_ble_ll_trace_u32x3 = 0x400016fc; -r_ble_ll_tx_flat_mbuf_pducb = 0x40001700; -r_ble_ll_tx_mbuf_pducb = 0x40001704; -r_ble_ll_tx_pkt_in = 0x40001708; -r_ble_ll_update_max_tx_octets_phy_mode = 0x4000170c; -r_ble_ll_usecs_to_ticks_round_up = 0x40001710; -r_ble_ll_utils_calc_access_addr = 0x40001714; -r_ble_ll_utils_calc_dci_csa2 = 0x40001718; -r_ble_ll_utils_calc_num_used_chans = 0x4000171c; -r_ble_ll_utils_calc_window_widening = 0x40001720; -r_ble_ll_utils_csa2_perm = 0x40001724; -r_ble_ll_utils_csa2_prng = 0x40001728; -r_ble_ll_utils_remapped_channel = 0x4000172c; -r_ble_ll_wfr_timer_exp = 0x40001730; -r_ble_ll_whitelist_add = 0x40001734; -r_ble_ll_whitelist_chg_allowed = 0x40001738; -r_ble_ll_whitelist_clear = 0x4000173c; -r_ble_ll_whitelist_read_size = 0x40001740; -r_ble_ll_whitelist_rmv = 0x40001744; -r_ble_ll_whitelist_search = 0x40001748; -r_ble_ll_write_rf_path_compensation = 0x4000174c; -r_ble_phy_access_addr_get = 0x40001750; -r_ble_phy_bb_bug_is_triggered = 0x40001754; -r_ble_phy_calculate_rxtx_ifs = 0x40001758; -r_ble_phy_calculate_rxwindow = 0x4000175c; -r_ble_phy_calculate_txrx_ifs = 0x40001760; -r_ble_phy_config_access_addr = 0x40001764; -r_ble_phy_data_make = 0x40001768; -r_ble_phy_disable = 0x4000176c; -r_ble_phy_disable_irq = 0x40001770; -r_ble_phy_disable_whitening = 0x40001774; -r_ble_phy_enable_scan_seq_immediately = 0x40001778; -r_ble_phy_enable_whitening = 0x4000177c; -r_ble_phy_encrypt_disable = 0x40001780; -r_ble_phy_env_init = 0x40001784; -r_ble_phy_get_current_phy = 0x40001788; -r_ble_phy_get_packet_counter = 0x4000178c; -r_ble_phy_get_packet_status = 0x40001790; -r_ble_phy_get_pyld_time_offset = 0x40001794; -r_ble_phy_get_rx_phy_mode = 0x40001798; -r_ble_phy_init = 0x4000179c; -r_ble_phy_isr = 0x400017a0; -r_ble_phy_max_data_pdu_pyld = 0x400017a4; -r_ble_phy_mode_config = 0x400017a8; -r_ble_phy_mode_convert = 0x400017ac; -r_ble_phy_mode_write = 0x400017b0; -r_ble_phy_module_deinit = 0x400017b4; -r_ble_phy_module_init = 0x400017b8; -r_ble_phy_monitor_bb_sync = 0x400017bc; -r_ble_phy_need_to_report = 0x400017c0; -r_ble_phy_pkt_received = 0x400017c4; -r_ble_phy_reset_bb_monitor = 0x400017c8; -r_ble_phy_resolv_list_disable = 0x400017cc; -r_ble_phy_resolv_list_enable = 0x400017d0; -r_ble_phy_restart_sequence = 0x400017d4; -r_ble_phy_rfclk_disable = 0x400017d8; -r_ble_phy_rfclk_enable = 0x400017dc; -r_ble_phy_rx_is_expected = 0x400017e0; -r_ble_phy_rxpdu_copy = 0x400017e4; -r_ble_phy_scan_set_start_time = 0x400017e8; -r_ble_phy_seq_encrypt_enable = 0x400017ec; -r_ble_phy_seq_encrypt_set_pkt_cntr = 0x400017f0; -r_ble_phy_sequence_adv_end = 0x400017f4; -r_ble_phy_sequence_copy_rx_flags = 0x400017f8; -r_ble_phy_sequence_end_isr = 0x400017fc; -r_ble_phy_sequence_get_mode = 0x40001800; -r_ble_phy_sequence_get_state = 0x40001804; -r_ble_phy_sequence_init_end = 0x40001808; -r_ble_phy_sequence_is_running = 0x4000180c; -r_ble_phy_sequence_is_waiting_rsp = 0x40001810; -r_ble_phy_sequence_isr_copy_data = 0x40001814; -r_ble_phy_sequence_master_end = 0x40001818; -r_ble_phy_sequence_rx_end_isr = 0x4000181c; -r_ble_phy_sequence_scan_end = 0x40001820; -r_ble_phy_sequence_single_end = 0x40001824; -r_ble_phy_sequence_slave_end = 0x40001828; -r_ble_phy_sequence_tx_end_invoke = 0x4000182c; -r_ble_phy_sequence_update_conn_params = 0x40001830; -r_ble_phy_set_adv_sequence = 0x40001834; -r_ble_phy_set_coex_pti = 0x40001838; -r_ble_phy_set_dev_address = 0x4000183c; -r_ble_phy_set_master_sequence = 0x40001840; -r_ble_phy_set_rx_pwr_compensation = 0x40001844; -r_ble_phy_set_rxhdr_flags = 0x40001848; -r_ble_phy_set_rxhdr_info = 0x4000184c; -r_ble_phy_set_scan_sequence = 0x40001850; -r_ble_phy_set_single_packet_rx_sequence = 0x40001854; -r_ble_phy_set_single_packet_tx_sequence = 0x40001858; -r_ble_phy_set_slave_sequence = 0x4000185c; -r_ble_phy_set_txend_cb = 0x40001860; -r_ble_phy_setchan = 0x40001864; -r_ble_phy_slave_set_start_time = 0x40001868; -r_ble_phy_state_get = 0x4000186c; -r_ble_phy_timer_config_start_time = 0x40001870; -r_ble_phy_timer_start_now = 0x40001874; -r_ble_phy_timer_stop = 0x40001878; -r_ble_phy_tx_set_start_time = 0x4000187c; -r_ble_phy_txpower_round = 0x40001880; -r_ble_phy_txpwr_set = 0x40001884; -r_ble_phy_wfr_enable = 0x40001888; -r_ble_phy_xcvr_state_get = 0x4000188c; -r_ble_plf_set_log_level = 0x40001890; -r_ble_vendor_hci_register = 0x40001894; -r_bleonly_os_tick_init = 0x40001898; -r_bt_rf_coex_cfg_set = 0x4000189c; -r_bt_rf_coex_coded_txrx_time_upper_lim = 0x400018a0; -r_bt_rf_coex_dft_pti_set = 0x400018a4; -r_bt_rf_coex_hook_deinit = 0x400018a8; -r_bt_rf_coex_hook_init = 0x400018ac; -r_bt_rf_coex_hook_st_set = 0x400018b0; -r_bt_rf_coex_hooks_p_set_default = 0x400018b4; -r_btdm_disable_adv_delay = 0x400018b8; -r_btdm_switch_phy_coded = 0x400018bc; -r_esp_wait_disabled = 0x400018c0; -r_get_be16 = 0x400018c4; -r_get_be24 = 0x400018c8; -r_get_be32 = 0x400018cc; -r_get_be64 = 0x400018d0; -r_get_le16 = 0x400018d4; -r_get_le24 = 0x400018d8; -r_get_le32 = 0x400018dc; -r_get_le64 = 0x400018e0; -r_get_local_irk_offset = 0x400018e4; -r_get_local_rpa_offset = 0x400018e8; -r_get_max_skip = 0x400018ec; -r_get_peer_id_offset = 0x400018f0; -r_get_peer_irk_offset = 0x400018f4; -r_get_peer_rpa_offset = 0x400018f8; -r_hal_os_tick_read_tick = 0x400018fc; -r_hal_os_tick_set_exp_tick = 0x40001900; -r_hal_rtc_intr_init = 0x40001904; -r_hal_rtc_irq_handler = 0x40001908; -r_hal_timer_deinit = 0x4000190c; -r_hal_timer_disable_irq = 0x40001910; -r_hal_timer_env_init = 0x40001914; -r_hal_timer_init = 0x40001918; -r_hal_timer_process = 0x4000191c; -r_hal_timer_read = 0x40001920; -r_hal_timer_read_tick = 0x40001924; -r_hal_timer_set_cb = 0x40001928; -r_hal_timer_set_exp_tick = 0x4000192c; -r_hal_timer_start = 0x40001930; -r_hal_timer_start_at = 0x40001934; -r_hal_timer_stop = 0x40001938; -r_hal_timer_task_start = 0x4000193c; -r_ll_assert = 0x40001940; -r_mem_init_mbuf_pool = 0x40001944; -r_mem_malloc_mbuf_pool = 0x40001948; -r_mem_malloc_mbufpkt_pool = 0x4000194c; -r_mem_malloc_mempool = 0x40001950; -r_mem_malloc_mempool_ext = 0x40001954; -r_mem_malloc_mempool_gen = 0x40001958; -r_mem_pullup_obj = 0x4000195c; -r_mem_split_frag = 0x40001960; -r_os_cputime_delay_ticks = 0x40001964; -r_os_cputime_delay_usecs = 0x40001968; -r_os_cputime_get32 = 0x4000196c; -r_os_cputime_ticks_to_usecs = 0x40001970; -r_os_cputime_timer_init = 0x40001974; -r_os_cputime_timer_relative = 0x40001978; -r_os_cputime_timer_start = 0x4000197c; -r_os_cputime_timer_stop = 0x40001980; -r_os_cputime_usecs_to_ticks = 0x40001984; -r_os_mbuf_adj = 0x40001988; -r_os_mbuf_append = 0x4000198c; -r_os_mbuf_appendfrom = 0x40001990; -r_os_mbuf_cmpf = 0x40001994; -r_os_mbuf_cmpm = 0x40001998; -r_os_mbuf_concat = 0x4000199c; -r_os_mbuf_copydata = 0x400019a0; -r_os_mbuf_copyinto = 0x400019a4; -r_os_mbuf_dup = 0x400019a8; -r_os_mbuf_extend = 0x400019ac; -r_os_mbuf_free = 0x400019b0; -r_os_mbuf_free_chain = 0x400019b4; -r_os_mbuf_get = 0x400019b8; -r_os_mbuf_get_pkthdr = 0x400019bc; -r_os_mbuf_len = 0x400019c0; -r_os_mbuf_off = 0x400019c4; -r_os_mbuf_pack_chains = 0x400019c8; -r_os_mbuf_pool_init = 0x400019cc; -r_os_mbuf_prepend = 0x400019d0; -r_os_mbuf_prepend_pullup = 0x400019d4; -r_os_mbuf_pullup = 0x400019d8; -r_os_mbuf_trim_front = 0x400019dc; -r_os_mbuf_widen = 0x400019e0; -r_os_memblock_from = 0x400019e4; -r_os_memblock_get = 0x400019e8; -r_os_memblock_put = 0x400019ec; -r_os_memblock_put_from_cb = 0x400019f0; -r_os_mempool_clear = 0x400019f4; -r_os_mempool_ext_clear = 0x400019f8; -r_os_mempool_ext_init = 0x400019fc; -r_os_mempool_info_get_next = 0x40001a00; -r_os_mempool_init = 0x40001a04; -r_os_mempool_init_internal = 0x40001a08; -r_os_mempool_is_sane = 0x40001a0c; -r_os_mempool_module_init = 0x40001a10; -r_os_mempool_unregister = 0x40001a14; -r_os_mqueue_get = 0x40001a18; -r_os_mqueue_init = 0x40001a1c; -r_os_mqueue_put = 0x40001a20; -r_os_msys_count = 0x40001a24; -r_os_msys_get = 0x40001a28; -r_os_msys_get_pkthdr = 0x40001a2c; -r_os_msys_num_free = 0x40001a30; -r_os_msys_register = 0x40001a34; -r_os_msys_reset = 0x40001a38; -r_os_tick_idle = 0x40001a3c; -r_pri_phy_valid = 0x40001a40; -r_put_be16 = 0x40001a44; -r_put_be24 = 0x40001a48; -r_put_be32 = 0x40001a4c; -r_put_be64 = 0x40001a50; -r_put_le16 = 0x40001a54; -r_put_le24 = 0x40001a58; -r_put_le32 = 0x40001a5c; -r_put_le64 = 0x40001a60; -r_rtc0_timer_handler = 0x40001a64; -r_rtc1_timer_handler = 0x40001a68; -r_sdkconfig_get_opts = 0x40001a6c; -r_sdkconfig_set_opts = 0x40001a70; -r_sec_phy_valid = 0x40001a74; -r_sub24 = 0x40001a78; -r_swap_buf = 0x40001a7c; -r_swap_in_place = 0x40001a80; -*/ -/* Data (.data, .bss, .rodata) */ -/* -ble_hci_uart_reset_cmd = 0x3ff1ffe0; -ble_hci_trans_env_p = 0x3fcdffc4; -ble_hci_trans_mode = 0x3fcdfebc; -ble_ll_adv_env_p = 0x3fcdffc0; -ble_ll_conn_env_p = 0x3fcdffbc; -g_ble_ll_conn_cth_flow = 0x3fcdffb4; -g_ble_ll_conn_cth_flow_error_ev = 0x3fcdffb0; -g_ble_ll_ctrl_pkt_lengths_ro = 0x3ff1ffbc; -ble_ll_dtm_module_env_p = 0x3fcdffac; -channel_rf_to_index = 0x3ff1ff94; -g_ble_ll_dtm_prbs15_data = 0x3ff1fe94; -g_ble_ll_dtm_prbs9_data = 0x3ff1fd94; -ble_ll_hci_env_p = 0x3fcdffa8; -ble_ll_rand_env_p = 0x3fcdffa4; -ble_ll_resolv_env_p = 0x3fcdffa0; -g_ble_ll_resolve_hdr = 0x3fcdff98; -g_device_mode_default = 0x3fcdfeba; -g_ble_ll_rfmgmt_data = 0x3fcdff50; -g_ble_sleep_enter_cb = 0x3fcdff4c; -g_ble_sleep_exit_cb = 0x3fcdff48; -g_rfclk_enabled = 0x3fcdff44; -ble_ll_scan_env_p = 0x3fcdff40; -ble_ll_sched_env_p = 0x3fcdff3c; -g_ble_ll_supp_cmds_ro = 0x3ff1fd64; -ble_ll_sync_env_p = 0x3fcdff38; -g_ble_sca_ppm_tbl_ro = 0x3ff1fd54; -ble_ll_env_p = 0x3fcdff34; -g_ble_ll_pdu_header_tx_time_ro = 0x3ff1fd4c; -priv_config_opts = 0x3fcdfea4; -ble_hci_trans_funcs_ptr = 0x3fcdff30; -r_ble_stub_funcs_ptr = 0x3fcdff2c; -r_ext_funcs_p = 0x3fcdff28; -r_npl_funcs = 0x3fcdff24; -ble_hw_env_p = 0x3fcdff20; -ble_phy_module_env_p = 0x3fcdff1c; -g_ble_phy_chan_freq_ro = 0x3ff1fd24; -g_ble_phy_mode_pkt_start_off_ro = 0x3ff1fd1c; -g_ble_phy_rxtx_ifs_compensation_ro = 0x3ff1fd0c; -g_ble_phy_t_rxaddrdelay_ro = 0x3ff1fd08; -g_ble_phy_t_rxenddelay_ro = 0x3ff1fd04; -g_ble_phy_t_txdelay_ro = 0x3ff1fd00; -g_ble_phy_t_txenddelay_ro = 0x3ff1fcfc; -g_ble_phy_txrx_ifs_compensation_ro = 0x3ff1fcec; -hal_timer_env_p = 0x3fcdff18; -g_hal_os_tick = 0x3fcdff0c; -r_osi_coex_funcs_p = 0x3fcdff08; -bt_rf_coex_hooks = 0x3fcdff00; -bt_rf_coex_hooks_p = 0x3fcdfefc; -coex_hook_st_group_tab = 0x3ff1fce0; -coex_hook_st_group_to_coex_schm_st_tab = 0x3ff1fcdc; -s_ble_act_count_by_group = 0x3fcdfef8; -s_ble_coex_st_map = 0x3fcdfee4; -bt_rf_coex_cfg_cb = 0x3fcdfec8; -bt_rf_coex_cfg_p = 0x3fcdfec4; -bt_rf_coex_cfg_rom = 0x3ff1fcc0; -bt_rf_coex_pti_dft_p = 0x3fcdfec0; -bt_rf_coex_pti_dft_rom = 0x3fcdfe64; -conn_dynamic_pti_param_rom = 0x3ff1fca8; -conn_phy_coded_max_data_time_param_rom = 0x3ff1fca4; -ext_adv_dynamic_pti_param_rom = 0x3ff1fc70; -ext_scan_dynamic_param_rom = 0x3ff1fc38; -legacy_adv_dynamic_pti_param_rom = 0x3ff1fc18; -per_adv_dynamic_pti_param_rom = 0x3ff1fbfc; -sync_dynamic_param_rom = 0x3ff1fbe4; -g_ble_plf_log_level = 0x3fcdfe60; -g_msys_pool_list = 0x3fcdfe58; -g_os_mempool_list = 0x3fcdfe50; -*/ - -/*************************************** - Group rom_phy - ***************************************/ - -/* Functions */ -phy_param_addr = 0x40001a84; -phy_get_romfuncs = 0x40001a88; -chip729_phyrom_version = 0x40001a8c; -chip729_phyrom_version_num = 0x40001a90; -rom_get_i2c_read_mask = 0x40001c6c; -rom_get_i2c_mst0_mask = 0x40001c70; -rom_get_i2c_hostid = 0x40001c74; -rom_chip_i2c_readReg_org = 0x40001c78; -rom_chip_i2c_readReg = 0x40001c7c; -rom_i2c_paral_set_mst0 = 0x40001c80; -rom_i2c_paral_set_read = 0x40001c84; -rom_i2c_paral_read = 0x40001c88; -rom_i2c_paral_write = 0x40001c8c; -rom_i2c_paral_write_num = 0x40001c90; -rom_i2c_paral_write_mask = 0x40001c94; -rom_i2c_readReg = 0x40001c98; -rom_chip_i2c_writeReg = 0x40001c9c; -rom_i2c_writeReg = 0x40001ca0; -rom_i2c_readReg_Mask = 0x40001ca4; -rom_i2c_writeReg_Mask = 0x40001ca8; -/* Data (.data, .bss, .rodata) */ -phy_param_rom = 0x3fcdfe4c; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld deleted file mode 100644 index d7374c7510..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld +++ /dev/null @@ -1,112 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group libgcc - ***************************************/ - -/* Functions */ -__absvdi2 = 0x40000998; -__absvsi2 = 0x4000099c; -__adddf3 = 0x400009a0; -__addsf3 = 0x400009a4; -__addvdi3 = 0x400009a8; -__addvsi3 = 0x400009ac; -__ashldi3 = 0x400009b0; -__ashrdi3 = 0x400009b4; -__bswapdi2 = 0x400009b8; -__bswapsi2 = 0x400009bc; -__clear_cache = 0x400009c0; -__clrsbdi2 = 0x400009c4; -__clrsbsi2 = 0x400009c8; -__clzdi2 = 0x400009cc; -__clzsi2 = 0x400009d0; -__cmpdi2 = 0x400009d4; -__ctzdi2 = 0x400009d8; -__ctzsi2 = 0x400009dc; -__divdc3 = 0x400009e0; -__divdf3 = 0x400009e4; -__divdi3 = 0x400009e8; -__divsc3 = 0x400009ec; -__divsf3 = 0x400009f0; -__divsi3 = 0x400009f4; -__eqdf2 = 0x400009f8; -__eqsf2 = 0x400009fc; -__extendsfdf2 = 0x40000a00; -__ffsdi2 = 0x40000a04; -__ffssi2 = 0x40000a08; -__fixdfdi = 0x40000a0c; -__fixdfsi = 0x40000a10; -__fixsfdi = 0x40000a14; -__fixsfsi = 0x40000a18; -__fixunsdfsi = 0x40000a1c; -__fixunssfdi = 0x40000a20; -__fixunssfsi = 0x40000a24; -__floatdidf = 0x40000a28; -__floatdisf = 0x40000a2c; -__floatsidf = 0x40000a30; -__floatsisf = 0x40000a34; -__floatundidf = 0x40000a38; -__floatundisf = 0x40000a3c; -__floatunsidf = 0x40000a40; -__floatunsisf = 0x40000a44; -__gcc_bcmp = 0x40000a48; -__gedf2 = 0x40000a4c; -__gesf2 = 0x40000a50; -__gtdf2 = 0x40000a54; -__gtsf2 = 0x40000a58; -__ledf2 = 0x40000a5c; -__lesf2 = 0x40000a60; -__lshrdi3 = 0x40000a64; -__ltdf2 = 0x40000a68; -__ltsf2 = 0x40000a6c; -__moddi3 = 0x40000a70; -__modsi3 = 0x40000a74; -__muldc3 = 0x40000a78; -__muldf3 = 0x40000a7c; -__muldi3 = 0x40000a80; -__mulsc3 = 0x40000a84; -__mulsf3 = 0x40000a88; -__mulsi3 = 0x40000a8c; -__mulvdi3 = 0x40000a90; -__mulvsi3 = 0x40000a94; -__nedf2 = 0x40000a98; -__negdf2 = 0x40000a9c; -__negdi2 = 0x40000aa0; -__negsf2 = 0x40000aa4; -__negvdi2 = 0x40000aa8; -__negvsi2 = 0x40000aac; -__nesf2 = 0x40000ab0; -__paritysi2 = 0x40000ab4; -__popcountdi2 = 0x40000ab8; -__popcountsi2 = 0x40000abc; -__powidf2 = 0x40000ac0; -__powisf2 = 0x40000ac4; -__subdf3 = 0x40000ac8; -__subsf3 = 0x40000acc; -__subvdi3 = 0x40000ad0; -__subvsi3 = 0x40000ad4; -__truncdfsf2 = 0x40000ad8; -__ucmpdi2 = 0x40000adc; -__udivdi3 = 0x40000ae0; -__udivmoddi4 = 0x40000ae4; -__udivsi3 = 0x40000ae8; -__udiv_w_sdiv = 0x40000aec; -__umoddi3 = 0x40000af0; -__umodsi3 = 0x40000af4; -__unorddf2 = 0x40000af8; -__unordsf2 = 0x40000afc; -__extenddftf2 = 0x40000b00; -__trunctfdf2 = 0x40000b04; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld deleted file mode 100644 index ab7bbb3eab..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld +++ /dev/null @@ -1,47 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib_nano_format - ***************************************/ - -/* Functions */ -__sprint_r = 0x40000684; -_fiprintf_r = 0x40000688; -_fprintf_r = 0x4000068c; -_printf_common = 0x40000690; -_printf_i = 0x40000694; -_vfiprintf_r = 0x40000698; -_vfprintf_r = 0x4000069c; -fiprintf = 0x400006a0; -fprintf = 0x400006a4; -printf = 0x400006a8; -vfiprintf = 0x400006ac; -vfprintf = 0x400006b0; -asprintf = 0x400006b4; -sprintf = 0x400006b8; -snprintf = 0x400006bc; -siprintf = 0x400006c0; -sniprintf = 0x400006c4; -vprintf = 0x400006c8; -viprintf = 0x400006cc; -vsnprintf = 0x400006d0; -vsniprintf = 0x400006d4; -_printf_float = 0x400006d8; -_scanf_float = 0x400006dc; -_scanf_i = 0x400006e0; -_scanf_chars = 0x400006e4; -sscanf = 0x400006e8; -siscanf = 0x400006ec; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld deleted file mode 100644 index 141a85d09f..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld +++ /dev/null @@ -1,143 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.newlib.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib - ***************************************/ - -/* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40000494; -memset = 0x40000498; -memcpy = 0x4000049c; -memmove = 0x400004a0; -memcmp = 0x400004a4; -strcpy = 0x400004a8; -strncpy = 0x400004ac; -strcmp = 0x400004b0; -strncmp = 0x400004b4; -strlen = 0x400004b8; -strstr = 0x400004bc; -bzero = 0x400004c0; -sbrk = 0x400004c8; -isalnum = 0x400004cc; -isalpha = 0x400004d0; -isascii = 0x400004d4; -isblank = 0x400004d8; -iscntrl = 0x400004dc; -isdigit = 0x400004e0; -islower = 0x400004e4; -isgraph = 0x400004e8; -isprint = 0x400004ec; -ispunct = 0x400004f0; -isspace = 0x400004f4; -isupper = 0x400004f8; -toupper = 0x400004fc; -tolower = 0x40000500; -toascii = 0x40000504; -memccpy = 0x40000508; -memchr = 0x4000050c; -memrchr = 0x40000510; -strcasecmp = 0x40000514; -strcasestr = 0x40000518; -strcat = 0x4000051c; -strdup = 0x40000520; -strchr = 0x40000524; -strcspn = 0x40000528; -strcoll = 0x4000052c; -strlcat = 0x40000530; -strlcpy = 0x40000534; -strlwr = 0x40000538; -strncasecmp = 0x4000053c; -strncat = 0x40000540; -strndup = 0x40000544; -strnlen = 0x40000548; -strrchr = 0x4000054c; -strsep = 0x40000550; -strspn = 0x40000554; -strtok_r = 0x40000558; -strupr = 0x4000055c; -longjmp = 0x40000560; -setjmp = 0x40000564; -abs = 0x40000568; -div = 0x4000056c; -labs = 0x40000570; -ldiv = 0x40000574; -qsort = 0x40000578; -rand_r = 0x4000057c; -rand = 0x40000580; -srand = 0x40000584; -utoa = 0x40000588; -itoa = 0x4000058c; -atoi = 0x40000590; -atol = 0x40000594; -strtol = 0x40000598; -strtoul = 0x4000059c; -fflush = 0x400005a0; -_fflush_r = 0x400005a4; -_fwalk = 0x400005a8; -_fwalk_reent = 0x400005ac; -__swbuf_r = 0x400005b8; -__swbuf = 0x400005bc; -_strtod_l = 0x400005c4; -_strtod_r = 0x400005c8; -strtod_l = 0x400005cc; -strtod = 0x400005d0; -strtof_l = 0x400005d4; -strtof = 0x400005d8; -_strtol_r = 0x400005dc; -strtol_l = 0x400005e0; -_strtoul_r = 0x400005e4; -strtoul_l = 0x400005e8; -__match = 0x400005ec; -__hexnan = 0x400005f0; -__hexdig_fun = 0x400005f4; -__gethex = 0x400005f8; -_Balloc = 0x400005fc; -_Bfree = 0x40000600; -__multadd = 0x40000604; -__s2b = 0x40000608; -__hi0bits = 0x4000060c; -__lo0bits = 0x40000610; -__i2b = 0x40000614; -__multiply = 0x40000618; -__pow5mult = 0x4000061c; -__lshift = 0x40000620; -__mcmp = 0x40000624; -__mdiff = 0x40000628; -__ulp = 0x4000062c; -__b2d = 0x40000630; -__d2b = 0x40000634; -__ratio = 0x40000638; -_mprec_log10 = 0x4000063c; -__copybits = 0x40000640; -__any_on = 0x40000644; -asctime = 0x40000648; -asctime_r = 0x4000064c; -atof = 0x40000650; -atoff = 0x40000654; -_dtoa_r = 0x40000658; -_wctomb_r = 0x4000065c; -__ascii_wctomb = 0x40000660; -_mbtowc_r = 0x40000664; -__ascii_mbtowc = 0x40000668; -puts = 0x4000066c; -putc = 0x40000670; -putchar = 0x40000674; -nan = 0x40000678; -nanf = 0x4000067c; -__errno = 0x40000680; -/* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fcdffd4; -_global_impure_ptr = 0x3fcdffd0; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld deleted file mode 100644 index fbe937c345..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM version variables for esp32h4 - * - * These addresses should be compatible with any ROM version for this chip. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ -_rom_chip_id = 0x40000010; -_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/include/esp32h4/rom/aes.h b/components/esp_rom/include/esp32h4/rom/aes.h deleted file mode 100644 index e593c7b940..0000000000 --- a/components/esp_rom/include/esp32h4/rom/aes.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_AES_H_ -#define _ROM_AES_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define AES_BLOCK_SIZE 16 - -enum AES_TYPE { - AES_ENC, - AES_DEC, -}; - -enum AES_BITS { - AES128, - AES192, - AES256 -}; - -void ets_aes_enable(void); - -void ets_aes_disable(void); - -int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); - -int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); - -int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); - -void ets_aes_block(const void *input, void *output); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_AES_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/apb_backup_dma.h b/components/esp_rom/include/esp32h4/rom/apb_backup_dma.h deleted file mode 100644 index 14948bbde1..0000000000 --- a/components/esp_rom/include/esp32h4/rom/apb_backup_dma.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void)); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/bigint.h b/components/esp_rom/include/esp32h4/rom/bigint.h deleted file mode 100644 index a25f36a9fd..0000000000 --- a/components/esp_rom/include/esp32h4/rom/bigint.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_BIGINT_H_ -#define _ROM_BIGINT_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void ets_bigint_enable(void); - -void ets_bigint_disable(void); - -int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); - -int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); - -int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); - -void ets_bigint_wait_finish(void); - -int ets_bigint_getz(uint32_t *z, uint32_t len_words); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_BIGINT_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/cache.h b/components/esp_rom/include/esp32h4/rom/cache.h deleted file mode 100644 index 4bf5b854c5..0000000000 --- a/components/esp_rom/include/esp32h4/rom/cache.h +++ /dev/null @@ -1,750 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_CACHE_H_ -#define _ROM_CACHE_H_ - -#include -#include "esp_bit_defs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup cache_apis, cache operation related apis - * @brief cache apis - */ - -/** @addtogroup cache_apis - * @{ - */ -#define MIN_ICACHE_SIZE 16384 -#define MAX_ICACHE_SIZE 16384 -#define MIN_ICACHE_WAYS 8 -#define MAX_ICACHE_WAYS 8 -#define MAX_CACHE_WAYS 8 -#define MIN_CACHE_LINE_SIZE 32 -#define TAG_SIZE 4 -#define MIN_ICACHE_BANK_NUM 1 -#define MAX_ICACHE_BANK_NUM 1 -#define CACHE_MEMORY_BANK_NUM 1 -#define CACHE_MEMORY_IBANK_SIZE 0x4000 - -#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) -#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) -#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) -#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) - -typedef enum { - CACHE_DCACHE = 0, - CACHE_ICACHE0 = 1, - CACHE_ICACHE1 = 2, -} cache_t; - -typedef enum { - CACHE_MEMORY_INVALID = 0, - CACHE_MEMORY_IBANK0 = BIT(0), - CACHE_MEMORY_IBANK1 = BIT(1), - CACHE_MEMORY_IBANK2 = BIT(2), - CACHE_MEMORY_IBANK3 = BIT(3), - CACHE_MEMORY_DBANK0 = BIT(0), - CACHE_MEMORY_DBANK1 = BIT(1), - CACHE_MEMORY_DBANK2 = BIT(2), - CACHE_MEMORY_DBANK3 = BIT(3), -} cache_array_t; - -#define ICACHE_SIZE_16KB CACHE_SIZE_HALF -#define ICACHE_SIZE_32KB CACHE_SIZE_FULL -#define DCACHE_SIZE_32KB CACHE_SIZE_HALF -#define DCACHE_SIZE_64KB CACHE_SIZE_FULL - -typedef enum { - CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ - CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ -} cache_size_t; - -typedef enum { - CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ - CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ -} cache_ways_t; - -typedef enum { - CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ - CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ - CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ -} cache_line_size_t; - -typedef enum { - CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ - CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ -} cache_autoload_order_t; - -#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) - -typedef enum { - CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ - CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ - CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ -} cache_autoload_trigger_t; - -typedef enum { - CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ - CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ -} cache_freeze_mode_t; - -struct cache_mode { - uint32_t cache_size; /*!< cache size in byte */ - uint16_t cache_line_size; /*!< cache line size in byte */ - uint8_t cache_ways; /*!< cache ways, always 4 */ - uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ -}; - -struct icache_tag_item { - uint32_t valid:1; /*!< the tag item is valid or not */ - uint32_t lock:1; /*!< the cache line is locked or not */ - uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ - uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ - uint32_t reserved:14; -}; - -struct autoload_config { - uint8_t order; /*!< autoload step is positive or negative */ - uint8_t trigger; /*!< autoload trigger */ - uint8_t ena0; /*!< autoload region0 enable */ - uint8_t ena1; /*!< autoload region1 enable */ - uint32_t addr0; /*!< autoload region0 start address */ - uint32_t size0; /*!< autoload region0 size */ - uint32_t addr1; /*!< autoload region1 start address */ - uint32_t size1; /*!< autoload region1 size */ -}; - -struct tag_group_info { - struct cache_mode mode; /*!< cache and cache mode */ - uint32_t filter_addr; /*!< the address that used to generate the struct */ - uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ - uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ - uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ -}; - -struct lock_config { - uint32_t addr; /*!< manual lock address*/ - uint16_t size; /*!< manual lock size*/ - uint16_t group; /*!< manual lock group, 0 or 1*/ -}; - -struct cache_internal_stub_table { - uint32_t (* icache_line_size)(void); - uint32_t (* icache_addr)(uint32_t addr); - uint32_t (* dcache_addr)(uint32_t addr); - void (* invalidate_icache_items)(uint32_t addr, uint32_t items); - void (* lock_icache_items)(uint32_t addr, uint32_t items); - void (* unlock_icache_items)(uint32_t addr, uint32_t items); - uint32_t (* suspend_icache_autoload)(void); - void (* resume_icache_autoload)(uint32_t autoload); - void (* freeze_icache_enable)(cache_freeze_mode_t mode); - void (* freeze_icache_disable)(void); - int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); -}; - -/* Defined in the interface file, default value is rom_default_cache_internal_table */ -extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; - -typedef void (* cache_op_start)(void); -typedef void (* cache_op_end)(void); - -typedef struct { - cache_op_start start; - cache_op_end end; -} cache_op_cb_t; - -/* Defined in the interface file, default value is NULL */ -extern const cache_op_cb_t* rom_cache_op_cb; - -#define ESP_ROM_ERR_INVALID_ARG 1 -#define MMU_SET_ADDR_ALIGNED_ERROR 2 -#define MMU_SET_PASE_SIZE_ERROR 3 -#define MMU_SET_VADDR_OUT_RANGE 4 - -#define CACHE_OP_ICACHE_Y 1 -#define CACHE_OP_ICACHE_N 0 - -/** - * @brief Initialise cache mmu, mark all entries as invalid. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_MMU_Init(void); - -/** - * @brief Set ICache mmu mapping. - * Please do not call this function in your SDK application. - * - * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In - * esp32h4, external memory is always flash - * - * @param uint32_t vaddr : virtual address in CPU address space. - * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. - * Should be aligned by psize. - * - * @param uint32_t paddr : physical address in external memory. - * Should be aligned by psize. - * - * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. - * - * @param uint32_t num : pages to be set. - * - * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. - * - * @return uint32_t: error status - * 0 : mmu set success - * 2 : vaddr or paddr is not aligned - * 3 : psize error - * 4 : vaddr is out of range - */ -int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); - -/** - * @brief Set DCache mmu mapping. - * Please do not call this function in your SDK application. - * - * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In - * esp32h4, external memory is always flash - * - * @param uint32_t vaddr : virtual address in CPU address space. - * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. - * Should be aligned by psize. - * - * @param uint32_t paddr : physical address in external memory. - * Should be aligned by psize. - * - * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. - * - * @param uint32_t num : pages to be set. - - * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. - * - * @return uint32_t: error status - * 0 : mmu set success - * 2 : vaddr or paddr is not aligned - * 3 : psize error - * 4 : vaddr is out of range - */ -int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); - -/** - * @brief Count the pages in the bus room address which map to Flash. - * Please do not call this function in your SDK application. - * - * @param uint32_t bus : the bus to count with. - * - * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. - * - * return uint32_t : the number of pages which map to Flash. - */ -uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); - -/** - * @brief allocate memory to used by ICache. - * Please do not call this function in your SDK application. - * - * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0 - * - * return none - */ -void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); - -/** - * @brief Get cache mode of ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field - * - * return none - */ -void Cache_Get_Mode(struct cache_mode * mode); - -/** - * @brief Init Cache for ROM boot, including resetting the Icache, initializing Owner, MMU, setting ICache mode, Enabling ICache, unmasking bus. - * - * @param None - * - * @return None - */ -void ROM_Boot_Cache_Init(void); - -/** - * @brief Init mmu owner register to make i/d cache use half mmu entries. - * - * @param None - * - * @return None - */ -void Cache_Owner_Init(void); - -/** - * @brief Invalidate the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to invalidate - * - * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Invalidate the Cache items in the region from ICache or DCache. - * If the region is not in Cache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : invalidated region start address. - * - * @param uint32_t size : invalidated region size. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Invalidate all cache items in ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Invalidate_ICache_All(void); - -/** - * @brief Mask all buses through ICache and DCache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Mask_All(void); - -/** - * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : 0 for ICache not auto preload before suspend. - */ -uint32_t Cache_Suspend_ICache_Autoload(void); - -/** - * @brief Resume ICache auto preload operation after some ICache operations. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : 0 for ICache not auto preload before suspend. - * - * @return None. - */ -void Cache_Resume_ICache_Autoload(uint32_t autoload); - -/** - * @brief Start an ICache manual preload, will suspend auto preload of ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of the preload region. - * - * @param uint32_t size : size of the preload region, should not exceed the size of ICache. - * - * @param uint32_t order : the preload order, 0 for positive, other for negative - * - * @return uint32_t : 0 for ICache not auto preload before manual preload. - */ -uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); - -/** - * @brief Return if the ICache manual preload done. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : 0 for ICache manual preload not done. - */ -uint32_t Cache_ICache_Preload_Done(void); - -/** - * @brief End the ICache manual preload to resume auto preload of ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. - * - * @return None - */ -void Cache_End_ICache_Preload(uint32_t autoload); - -/** - * @brief Config autoload parameters of ICache. - * Please do not call this function in your SDK application. - * - * @param struct autoload_config * config : autoload parameters. - * - * @return None - */ -void Cache_Config_ICache_Autoload(const struct autoload_config * config); - -/** - * @brief Enable auto preload for ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Enable_ICache_Autoload(void); - -/** - * @brief Disable auto preload for ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Disable_ICache_Autoload(void); - -/** - * @brief Config a group of prelock parameters of ICache. - * Please do not call this function in your SDK application. - * - * @param struct lock_config * config : a group of lock parameters. - * - * @return None - */ - -void Cache_Enable_ICache_PreLock(const struct lock_config *config); - -/** - * @brief Disable a group of prelock parameters for ICache. - * However, the locked data will not be released. - * Please do not call this function in your SDK application. - * - * @param uint16_t group : 0 for group0, 1 for group1. - * - * @return None - */ -void Cache_Disable_ICache_PreLock(uint16_t group); - -/** - * @brief Lock the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to lock - * - * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Unlock the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to unlock - * - * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Lock the cache items in tag memory for ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of lock region. - * - * @param uint32_t size : size of lock region. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Lock_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Unlock the cache items in tag memory for ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of unlock region. - * - * @param uint32_t size : size of unlock region. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Unlock_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Disable ICache access for the cpu. - * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. - * Please do not call this function in your SDK application. - * - * @return uint32_t : auto preload enabled before - */ -uint32_t Cache_Disable_ICache(void); - -/** - * @brief Enable ICache access for the cpu. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : ICache will preload then. - * - * @return None - */ -void Cache_Enable_ICache(uint32_t autoload); - -/** - * @brief Suspend ICache access for the cpu. - * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. - * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : auto preload enabled before - */ -uint32_t Cache_Suspend_ICache(void); - -/** - * @brief Resume ICache access for the cpu. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : ICache will preload then. - * - * @return None - */ -void Cache_Resume_ICache(uint32_t autoload); - -/** - * @brief Get ICache cache line size - * - * @param None - * - * @return uint32_t: 16, 32, 64 Byte - */ -uint32_t Cache_Get_ICache_Line_Size(void); - -/** - * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. - * - * @param None - * - * @return None - */ -void Cache_Set_Default_Mode(void); - -/** - * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. - * - * @param None - * - * @return None - */ -void Cache_Enable_Defalut_ICache_Mode(void); - -/** - * @brief Enable freeze for ICache. - * Any miss request will be rejected, including cpu miss and preload/autoload miss. - * Please do not call this function in your SDK application. - * - * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit - * - * @return None - */ -void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); - -/** - * @brief Disable freeze for ICache. - * Please do not call this function in your SDK application. - * - * @return None - */ -void Cache_Freeze_ICache_Disable(void); - -/** - * @brief Travel tag memory to run a call back function. - * ICache and DCache are suspend when doing this. - * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the cache to check and the cache mode. - * - * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. - * 0 for do not filter, all cache lines will be returned. - * - * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. - * - * @return None - */ -void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); - -/** - * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. - * - * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. - * - * @param uint32_t addr_offset : the virtual address offset of the cache ways. - * - * @return uint32_t : the virtual address. - */ -uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); - -/** - * @brief Get cache memory block base address. - * Please do not call this function in your SDK application. - * - * @param uint32_t icache : 0 for dcache, other for icache. - * - * @param uint32_t bank_no : 0 ~ 3 bank. - * - * @return uint32_t : the cache memory block base address, 0 if the block not used. - */ -uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no); - -/** - * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. - * - * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. - * - * @param uint32_t addr_offset : the virtual address offset of the cache ways. - * - * @return uint32_t : the virtual address. - */ -uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); - -/** - * @brief Get the cache memory value by DRAM address. - * Please do not call this function in your SDK application. - * - * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. - * - * @return uint32_t : the word value of the address. - */ -uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); -/** - * @} - */ - -/** - * @brief Get the cache MMU IROM end address. - * Please do not call this function in your SDK application. - * - * @param void - * - * @return uint32_t : the word value of the address. - */ -uint32_t Cache_Get_IROM_MMU_End(void); - -/** - * @brief Get the cache MMU DROM end address. - * Please do not call this function in your SDK application. - * - * @param void - * - * @return uint32_t : the word value of the address. - */ -uint32_t Cache_Get_DROM_MMU_End(void); - -/** - * @brief Configure cache MMU page size according to instruction and rodata size - * - * @param irom_size The instruction cache MMU page size - * @param drom_size The rodata data cache MMU page size - */ -void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); - -/** - * @brief Lock the permission control section configuration. After lock, any - * configuration modification will be bypass. Digital reset will clear the lock! - * Please do not call this function in your SDK application. - * - * @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms - * - * @return None - */ -void Cache_Pms_Lock(int ibus); - -/** - * @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2. - * Please do not call this function in your SDK application. - * - * @param uint32_t ibus_boundary0_addr : vaddress for split line0 - * - * @param uint32_t ibus_boundary1_addr : vaddress for split line1 - * - * @param uint32_t ibus_boundary2_addr : vaddress for split line2 - * - * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success - */ -int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr); - -/** - * @brief Set three ibus pms attribute, which will determine pms in different section and world. - * Please do not call this function in your SDK application. - * - * @param uint32_t ibus_pms_sct2_attr : attr for section2 - * - * @param uint32_t ibus_pms_sct1_attr : attr for section1 - * - * @return None - */ -void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr); - -/** - * @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2. - * Please do not call this function in your SDK application. - * - * @param uint32_t dbus_boundary0_addr : vaddress for split line0 - * - * @param uint32_t dbus_boundary1_addr : vaddress for split line1 - * - * @param uint32_t dbus_boundary2_addr : vaddress for split line2 - * - * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success - */ -int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr); - -/** - * @brief Set three dbus pms attribute, which will determine pms in different section and world. - * Please do not call this function in your SDK application. - * - * @param uint32_t dbus_pms_sct2_attr : attr for section2 - * - * @param uint32_t dbus_pms_sct1_attr : attr for section1 - * - * @return None - */ -void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_CACHE_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/crc.h b/components/esp_rom/include/esp32h4/rom/crc.h deleted file mode 100644 index a651ce2db6..0000000000 --- a/components/esp_rom/include/esp32h4/rom/crc.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ROM_CRC_H -#define ROM_CRC_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup crc_apis, uart configuration and communication related apis - * @brief crc apis - */ - -/** @addtogroup crc_apis - * @{ - */ - - -/* Standard CRC8/16/32 algorithms. */ -// CRC-8 x8+x2+x1+1 0x07 -// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS -// CRC32: -//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 -//If your buf is not continuous, you can use the first result to be the second parameter. - -/** - * @brief Crc32 value that is in little endian. - * - * @param uint32_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc32 value that is in big endian. - * - * @param uint32_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc16 value that is in little endian. - * - * @param uint16_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc16 value that is in big endian. - * - * @param uint16_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc8 value that is in little endian. - * - * @param uint8_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc8 value that is in big endian. - * - * @param uint32_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/components/esp_rom/include/esp32h4/rom/digital_signature.h b/components/esp_rom/include/esp32h4/rom/digital_signature.h deleted file mode 100644 index 3b8ad1a376..0000000000 --- a/components/esp_rom/include/esp32h4/rom/digital_signature.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#define ETS_DS_MAX_BITS 3072 - -#define ETS_DS_IV_LEN 16 - -/* Length of parameter 'C' stored in flash (not including IV) - - Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8) - - Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware -*/ -#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8) - -/* Encrypted ETS data. Recommended to store in flash in this format. - */ -typedef struct { - /* RSA LENGTH register parameters - * (number of words in RSA key & operands, minus one). - * - * - * This value must match the length field encrypted and stored in 'c', - * or invalid results will be returned. (The DS peripheral will - * always use the value in 'c', not this value, so an attacker can't - * alter the DS peripheral results this way, it will just truncate or - * extend the message and the resulting signature in software.) - */ - unsigned rsa_length; - - /* IV value used to encrypt 'c' */ - uint8_t iv[ETS_DS_IV_LEN]; - - /* Encrypted Digital Signature parameters. Result of AES-CBC encryption - of plaintext values. Includes an encrypted message digest. - */ - uint8_t c[ETS_DS_C_LEN]; -} ets_ds_data_t; - -typedef enum { - ETS_DS_OK, - ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ - ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ - ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ - ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ -} ets_ds_result_t; - -void ets_ds_enable(void); - -void ets_ds_disable(void); - - -/* - * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral - * - * - @param message Pointer to message (or padded digest) containing the message to sign. Should be - * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data - * in flash. - * - * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling - * this function, and is responsible for calling ets_ds_finish_sign() and then - * ets_hmac_invalidate_downstream() afterwards. - * - * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, - * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. - */ -ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); - - -/* - * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() - * - * A result of false indicates that a call to ets_ds_finish_sign() will not block. - * - * Only valid if ets_ds_enable() has been called. - */ -bool ets_ds_is_busy(void); - - -/* @brief Finish signing a message using the Digital Signature peripheral - * - * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until - * peripheral is no longer busy. - * - * - @param signature Pointer to buffer to contain the signature. Should be - * (data->rsa_length + 1)*4 bytes long. - * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() - * - * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, - * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the - * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a - * digest is produced anyhow.) - */ -ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); - - -/* Plaintext parameters used by Digital Signature. - - Not used for signing with DS peripheral, but can be encrypted - in-device by calling ets_ds_encrypt_params() -*/ -typedef struct { - uint32_t Y[ETS_DS_MAX_BITS / 32]; - uint32_t M[ETS_DS_MAX_BITS / 32]; - uint32_t Rb[ETS_DS_MAX_BITS / 32]; - uint32_t M_prime; - uint32_t length; -} ets_ds_p_data_t; - -typedef enum { - ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ - ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ -} ets_ds_key_t; - -/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral - * - * @param data Output buffer to store encrypted data, suitable for later use generating signatures. - * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. - * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. - * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. - * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) - * - * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. - */ -ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); - - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/efuse.h b/components/esp_rom/include/esp32h4/rom/efuse.h deleted file mode 100644 index 5117ffadf3..0000000000 --- a/components/esp_rom/include/esp32h4/rom/efuse.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_EFUSE_H_ -#define _ROM_EFUSE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** \defgroup efuse_APIs efuse APIs - * @brief ESP32 efuse read/write APIs - * @attention - * - */ - -/** @addtogroup efuse_APIs - * @{ - */ - -typedef enum { - ETS_EFUSE_KEY_PURPOSE_USER = 0, - ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, - ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, - ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, - ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, - ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, - ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, - ETS_EFUSE_KEY_PURPOSE_MAX, -} ets_efuse_purpose_t; - -typedef enum { - ETS_EFUSE_BLOCK0 = 0, - ETS_EFUSE_MAC_SPI_SYS_0 = 1, - ETS_EFUSE_BLOCK_SYS_DATA = 2, - ETS_EFUSE_BLOCK_USR_DATA = 3, - ETS_EFUSE_BLOCK_KEY0 = 4, - ETS_EFUSE_BLOCK_KEY1 = 5, - ETS_EFUSE_BLOCK_KEY2 = 6, - ETS_EFUSE_BLOCK_KEY3 = 7, - ETS_EFUSE_BLOCK_KEY4 = 8, - ETS_EFUSE_BLOCK_KEY5 = 9, - ETS_EFUSE_BLOCK_KEY6 = 10, - ETS_EFUSE_BLOCK_MAX, -} ets_efuse_block_t; - -/** - * @brief set timing accroding the apb clock, so no read error or write error happens. - * - * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. - * - * @return : 0 if success, others if clock not accepted - */ -int ets_efuse_set_timing(uint32_t clock); - -/** - * @brief Efuse read operation: copies data from physical efuses to efuse read registers. - * - * @param null - * - * @return : 0 if success, others if apb clock is not accepted - */ -int ets_efuse_read(void); - -/** - * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. - * - * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. - * - * @return : 0 if success, others if apb clock is not accepted - */ -int ets_efuse_program(ets_efuse_block_t block); - -/** - * @brief Set all Efuse program registers to zero. - * - * Call this before writing new data to the program registers. - */ -void ets_efuse_clear_program_registers(void); - -/** - * @brief Program a block of key data to an efuse block - * - * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). - * @param purpose Purpose to set for this key. Purpose must be already unset. - * @param data Pointer to data to write. - * @param data_len Length of data to write. - * - * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) - */ -int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); - - -/* @brief Return the address of a particular efuse block's first read register - * - * @param block Index of efuse block to look up - * - * @return 0 if block is invalid, otherwise a numeric read register address - * of the first word in the block. - */ -uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); - -/** - * @brief Return the current purpose set for an efuse key block - * - * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. - */ -ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); - -/** - * @brief Find a key block with the particular purpose set - * - * @param purpose Purpose to search for. - * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. - * @return true if found, false if not found. If false, value at key_block pointer is unchanged. - */ -bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); - -/** - * Return true if the key block is unused, false otherwise. - * - * An unused key block is all zero content, not read or write protected, - * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) - * - * @param key_block key block to check. - * - * @return true if key block is unused, false if key block or used - * or the specified block index is not a key block. - */ -bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); - - -/** - * @brief Search for an unused key block and return the first one found. - * - * See @ref ets_efuse_key_block_unused for a description of an unused key block. - * - * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. - */ -ets_efuse_block_t ets_efuse_find_unused_key_block(void); - -/** - * @brief Return the number of unused efuse key blocks (0-6) - */ -unsigned ets_efuse_count_unused_key_blocks(void); - -/** - * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. - * - * @param data Pointer to data buffer (length 32 bytes) - * @param rs_values Pointer to write encoded data to (length 12 bytes) - */ -void ets_efuse_rs_calculate(const void *data, void *rs_values); - -/** - * @brief Read spi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - 1 for default HSPI pins. - * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, - * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. - * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. - */ -uint32_t ets_efuse_get_spiconfig(void); - -/** - * @brief Read spi flash wp pad from Efuse - * - * @return - * - 0x3f for invalid. - * - 0~46 is valid. - */ -uint32_t ets_efuse_get_wp_pad(void); - -/** - * @brief Read if download mode disabled from Efuse - * - * @return - * - true for efuse disable download mode. - * - false for efuse doesn't disable download mode. - */ -bool ets_efuse_download_modes_disabled(void); - -/** - * @brief Read if uart print control value from Efuse - * - * @return - * - 0 for uart force print. - * - 1 for uart print when GPIO8 is low when digital reset. - * 2 for uart print when GPIO8 is high when digital reset. - * 3 for uart force slient - */ -uint32_t ets_efuse_get_uart_print_control(void); - -/** - * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse - * - * @return - * - 1 for efuse disable USB-Serial-JTAG print during rom boot. - * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. - */ -uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); - -/** - * @brief Read if usb download mode disabled from Efuse - * - * (Also returns true if security download mode is enabled, as this mode - * disables USB download.) - * - * @return - * - true for efuse disable usb download mode. - * - false for efuse doesn't disable usb download mode. - */ -bool ets_efuse_usb_download_mode_disabled(void); - - -/** - * @brief Read if usb module disabled from Efuse - * - * @return - * - true for efuse disable usb module. - * - false for efuse doesn't disable usb module. - */ -bool ets_efuse_usb_module_disabled(void); - -/** - * @brief Read if security download modes enabled from Efuse - * - * @return - * - true for efuse enable security download mode. - * - false for efuse doesn't enable security download mode. - */ -bool ets_efuse_security_download_modes_enabled(void); - -/** - * @brief Return true if secure boot is enabled in EFuse - */ -bool ets_efuse_secure_boot_enabled(void); - -/** - * @brief Return true if secure boot aggressive revoke is enabled in EFuse - */ -bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); - -/** - * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse - */ -bool ets_efuse_cache_encryption_enabled(void); - -/** - * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU - */ -bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); - -/** - * @brief Return true if EFuse indicates to send a flash resume command. - */ -bool ets_efuse_force_send_resume(void); - -/** - * @brief return the time in us ROM boot need wait flash to power on from Efuse - * - * @return - * - uint32_t the time in us. - */ -uint32_t ets_efuse_get_flash_delay_us(void); - -#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 -#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 - -#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 -#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) - -#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 -#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) - -#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 -#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) - -#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 -#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) - - -#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 -#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) - -/** - * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into - * the JTAG_CTRL registers. - * - * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. - * - * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. - * - * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. - * @param key_block Index of a key block containing the source for this key. - * - * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. - */ -int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); - -/** - * @brief A crc8 algorithm used for MAC addresses in efuse - * - * @param unsigned char const *p : Pointer to original data. - * - * @param unsigned int len : Data length in byte. - * - * @return unsigned char: Crc value. - */ -unsigned char esp_crc8(unsigned char const *p, unsigned int len); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_EFUSE_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/esp_flash.h b/components/esp_rom/include/esp32h4/rom/esp_flash.h deleted file mode 100644 index 85b4ae8755..0000000000 --- a/components/esp_rom/include/esp32h4/rom/esp_flash.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function - just adds ROM-specific parts -*/ - -struct spi_flash_chip_t; -typedef struct esp_flash_t esp_flash_t; - -/* Structure to wrap "global" data used by esp_flash in ROM */ -typedef struct { - /* Default SPI flash chip, ie main chip attached to the MCU - This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL - */ - esp_flash_t *default_chip; - - /* Global API OS notification start/end/chip_check functions - - These are used by ROM if no other host functions are configured. - */ - struct { - esp_err_t (*start)(esp_flash_t *chip); - esp_err_t (*end)(esp_flash_t *chip, esp_err_t err); - esp_err_t (*chip_check)(esp_flash_t **inout_chip); - } api_funcs; -} esp_flash_rom_global_data_t; - -/** Access a pointer to the global data used by the ROM spi_flash driver - */ -esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/ets_sys.h b/components/esp_rom/include/esp32h4/rom/ets_sys.h deleted file mode 100644 index 91544de628..0000000000 --- a/components/esp_rom/include/esp32h4/rom/ets_sys.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_ETS_SYS_H_ -#define _ROM_ETS_SYS_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup ets_sys_apis, ets system related apis - * @brief ets system apis - */ - -/** @addtogroup ets_sys_apis - * @{ - */ - -/************************************************************************ - * NOTE - * Many functions in this header files can't be run in FreeRTOS. - * Please see the comment of the Functions. - * There are also some functions that doesn't work on FreeRTOS - * without listed in the header, such as: - * xtos functions start with "_xtos_" in ld file. - * - *********************************************************************** - */ - -/** \defgroup ets_apis, Espressif Task Scheduler related apis - * @brief ets apis - */ - -/** @addtogroup ets_apis - * @{ - */ - -typedef enum { - ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1, /**< return failed in ets*/ - ETS_PENDING = 2, - ETS_BUSY = 3, - ETS_CANCEL = 4, -} ETS_STATUS; - -typedef ETS_STATUS ets_status_t; - -typedef uint32_t ETSSignal; -typedef uint32_t ETSParam; - -typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ - -struct ETSEventTag { - ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ - ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ -}; - -typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ -typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ - - - - - -/** - * @} - */ - -/** \defgroup ets_boot_apis, Boot routing related apis - * @brief ets boot apis - */ - -/** @addtogroup ets_apis - * @{ - */ - -extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ - -/** - * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. - * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the PRO Entry code address value in uint32_t - * - * @return None - */ -void ets_set_user_start(uint32_t start); - - -/** - * @} - */ - -/** \defgroup ets_printf_apis, ets_printf related apis used in ets - * @brief ets printf apis - */ - -/** @addtogroup ets_printf_apis - * @{ - */ - -/** - * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. - * Can not print float point data format, or longlong data format. - * So we maybe only use this in ROM. - * - * @param const char *fmt : See printf. - * - * @param ... : See printf. - * - * @return int : the length printed to the output device. - */ -int ets_printf(const char *fmt, ...); - -/** - * @brief Get the uart channel of ets_printf(uart_tx_one_char). - * - * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). - */ -uint8_t ets_get_printf_channel(void); - -/** - * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. - * Can not print float point data format, or longlong data format - * - * @param char c : char to output. - * - * @return None - */ -void ets_write_char_uart(char c); - -/** - * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. - * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. - * - * @param void (*)(char) p: Output function to install. - * - * @return None - */ -void ets_install_putc1(void (*p)(char c)); - -/** - * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. - * To install putc2, which is defaulted installed as NULL. - * - * @param void (*)(char) p: Output function to install. - * - * @return None - */ -void ets_install_putc2(void (*p)(char c)); - -/** - * @brief Install putc1 as ets_write_char_uart. - * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. - * - * @param None - * - * @return None - */ -void ets_install_uart_printf(void); - -#define ETS_PRINTF(...) ets_printf(...) - -#define ETS_ASSERT(v) do { \ - if (!(v)) { \ - ets_printf("%s %u \n", __FILE__, __LINE__); \ - while (1) {}; \ - } \ -} while (0); - -/** - * @} - */ - -/** \defgroup ets_timer_apis, ets_timer related apis used in ets - * @brief ets timer apis - */ - -/** @addtogroup ets_timer_apis - * @{ - */ -typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ - -typedef struct _ETSTIMER_ { - struct _ETSTIMER_ *timer_next; /**< timer linker*/ - uint32_t timer_expire; /**< abstruct time when timer expire*/ - uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ - ETSTimerFunc *timer_func; /**< timer handler*/ - void *timer_arg; /**< timer handler argument*/ -} ETSTimer; - -/** - * @brief Init ets timer, this timer range is 640 us to 429496 ms - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_timer_init(void); - -/** - * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_timer_deinit(void); - -/** - * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. - * - * @param bool repeat : Timer is periodic repeated. - * - * @return None - */ -void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); - -/** - * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. - * - * @param bool repeat : Timer is periodic repeated. - * - * @return None - */ -void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); - -/** - * @brief Disarm an ets timer. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @return None - */ -void ets_timer_disarm(ETSTimer *timer); - -/** - * @brief Set timer callback and argument. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @param ETSTimerFunc *pfunction : Timer callback. - * - * @param void *parg : Timer callback argument. - * - * @return None - */ -void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); - -/** - * @brief Unset timer callback and argument to NULL. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @return None - */ -void ets_timer_done(ETSTimer *ptimer); - -/** - * @brief CPU do while loop for some time. - * In FreeRTOS task, please call FreeRTOS apis. - * - * @param uint32_t us : Delay time in us. - * - * @return None - */ -void ets_delay_us(uint32_t us); - -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * Call this function when CPU frequency is changed. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency(uint32_t ticks_per_us); - - - -/** - * @brief Get the real CPU ticks per us to the ets. - * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. - * - * @param None - * - * @return uint32_t : CPU ticks per us record in ets. - */ -uint32_t ets_get_cpu_frequency(void); - -/** - * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if stored in efuse(not 0) - * clock = ets_efuse_get_xtal_freq() * 1000000; - * else if analog_8M in efuse - * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); - * else clock = 40M. - */ -uint32_t ets_get_xtal_freq(void); - -/** - * @brief Get the apb divior by xtal frequency. - * When any types of reset happen, the default value is 2. - * - * @param None - * - * @return uint32_t : 1 or 2. - */ -uint32_t ets_get_xtal_div(void); - -/** - * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. - * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; - * else store ets_get_detected_xtal_freq() in. - */ -uint32_t ets_get_apb_freq(void); - -/** - * @} - */ - -/** \defgroup ets_intr_apis, ets interrupt configure related apis - * @brief ets intr apis - */ - -/** @addtogroup ets_intr_apis - * @{ - */ - -typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ - -/** - * @brief Attach a interrupt handler to a CPU interrupt number. - * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param int i : CPU interrupt number. - * - * @param ets_isr_t func : Interrupt handler. - * - * @param void *arg : argument of the handler. - * - * @return None - */ -void ets_isr_attach(int i, ets_isr_t func, void *arg); - -/** - * @brief Mask the interrupts which show in mask bits. - * This function equals to _xtos_ints_off(mask). - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. - * - * @return None - */ -void ets_isr_mask(uint32_t mask); - -/** - * @brief Unmask the interrupts which show in mask bits. - * This function equals to _xtos_ints_on(mask). - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. - * - * @return None - */ -void ets_isr_unmask(uint32_t unmask); - -/** - * @brief Lock the interrupt to level 2. - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_intr_lock(void); - -/** - * @brief Unlock the interrupt to level 0. - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_intr_unlock(void); - -/** - * @brief Attach an CPU interrupt to a hardware source. - * We have 4 steps to use an interrupt: - * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); - * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); - * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); - * 4.Enable interrupt in the module. - * - * @param int cpu_no : The CPU which the interrupt number belongs. - * - * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. - * - * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. - * - * @return None - */ -void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); - -/** - * @} - */ - -#ifndef MAC2STR -#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] -#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" -#endif - -#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) - -#ifdef ESP_PLATFORM -// Remove in IDF v6.0 (IDF-7044) -typedef enum { - OK = 0, - FAIL, - PENDING, - BUSY, - CANCEL, -} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); -#endif - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_ETS_SYS_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/gpio.h b/components/esp_rom/include/esp32h4/rom/gpio.h deleted file mode 100644 index 3285d6caa7..0000000000 --- a/components/esp_rom/include/esp32h4/rom/gpio.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "soc/gpio_reg.h" -#include "sdkconfig.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup gpio_apis, uart configuration and communication related apis - * @brief gpio apis - */ - -/** @addtogroup gpio_apis - * @{ - */ - -#define GPIO_REG_READ(reg) READ_PERI_REG(reg) -#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) -#define GPIO_ID_PIN0 0 -#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) -#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -#define GPIO_FUNC_IN_HIGH 0x38 -#define GPIO_FUNC_IN_LOW 0x3C -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -#define GPIO_FUNC_IN_HIGH 0x1E -#define GPIO_FUNC_IN_LOW 0x1F -#endif - -#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ - ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) - -#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) - -typedef enum { - GPIO_PIN_INTR_DISABLE = 0, - GPIO_PIN_INTR_POSEDGE = 1, - GPIO_PIN_INTR_NEGEDGE = 2, - GPIO_PIN_INTR_ANYEDGE = 3, - GPIO_PIN_INTR_LOLEVEL = 4, - GPIO_PIN_INTR_HILEVEL = 5 -} GPIO_INT_TYPE; - - -/** - * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). - * There is no particular ordering guaranteed; so if the order of writes is significant, - * calling code should divide a single call into multiple calls. - * - * @param uint32_t set_mask : the gpios that need high level. - * - * @param uint32_t clear_mask : the gpios that need low level. - * - * @param uint32_t enable_mask : the gpios that need be changed. - * - * @param uint32_t disable_mask : the gpios that need diable output. - * - * @return None - */ -void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); - -/** - * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. - * - * @param None - * - * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. - */ -uint32_t gpio_input_get(void); - -/** - * @brief Set GPIO to wakeup the ESP32. - * Please do not call this function in SDK. - * - * @param uint32_t i: gpio number. - * - * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used - * - * @return None - */ -void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); - -/** - * @brief disable GPIOs to wakeup the ESP32. - * Please do not call this function in SDK. - * - * @param None - * - * @return None - */ -void gpio_pin_wakeup_disable(void); - -/** - * @brief set gpio input to a signal, one gpio can input to several signals. - * - * @param uint32_t gpio : gpio number, 0~0x2f - * gpio == 0x3C, input 0 to signal - * gpio == 0x3A, input nothing to signal - * gpio == 0x38, input 1 to signal - * - * @param uint32_t signal_idx : signal index. - * - * @param bool inv : the signal is inv or not - * - * @return None - */ -void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); - -/** - * @brief set signal output to gpio, one signal can output to several gpios. - * - * @param uint32_t gpio : gpio number, 0~0x2f - * - * @param uint32_t signal_idx : signal index. - * signal_idx == 0x100, cancel output put to the gpio - * - * @param bool out_inv : the signal output is invert or not - * - * @param bool oen_inv : the signal output enable is invert or not - * - * @return None - */ -void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); - -/** - * @brief Select pad as a gpio function from IOMUX. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_select_gpio(uint32_t gpio_num); - -/** - * @brief Set pad driver capability. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @param uint32_t drv : 0-3 - * - * @return None - */ -void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); - -/** - * @brief Pull up the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_pullup(uint32_t gpio_num); - -/** - * @brief Pull down the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_pulldown(uint32_t gpio_num); - -/** - * @brief Unhold the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_unhold(uint32_t gpio_num); - -/** - * @brief Hold the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_hold(uint32_t gpio_num); - -/** - * @brief enable gpio pad input. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_input_enable(uint32_t gpio_num); - -/** - * @brief disable gpio pad input. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_input_disable(uint32_t gpio_num); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/hmac.h b/components/esp_rom/include/esp32h4/rom/hmac.h deleted file mode 100644 index 8f110328e9..0000000000 --- a/components/esp_rom/include/esp32h4/rom/hmac.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_HMAC_H_ -#define _ROM_HMAC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "efuse.h" - -void ets_hmac_enable(void); - -void ets_hmac_disable(void); - -/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) - to digest a message. -*/ -int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); - -/* Calculate a downstream HMAC message to temporarily enable JTAG, or - to generate a Digital Signature data decryption key. - - - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE - or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG - - - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. - This efuse block must have the corresponding purpose set in "purpose", or - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. - - The result of this HMAC calculation is only made available "downstream" to the - corresponding hardware module, and cannot be accessed by software. -*/ -int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); - -/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). - * - * - purpose must match a previous call to ets_hmac_calculate_downstream(). - * - * After this function is called, the corresponding internal operation (JTAG or DS) will no longer - * have access to the generated key. - */ -int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); - -#ifdef __cplusplus -} -#endif - -#endif // _ROM_HMAC_H_ diff --git a/components/esp_rom/include/esp32h4/rom/libc_stubs.h b/components/esp_rom/include/esp32h4/rom/libc_stubs.h deleted file mode 100644 index 0836f39cd9..0000000000 --- a/components/esp_rom/include/esp32h4/rom/libc_stubs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _ROM_LIBC_STUBS_H_ -#define _ROM_LIBC_STUBS_H_ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* -ESP32 ROM code contains implementations of some of C library functions. -Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall -implementation defined in the following struct. - -The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to -set the address - -So, before using any of the C library functions (except for pure functions and memcpy/memset functions), -application must allocate syscall table structure for each CPU being used, and populate it with pointers -to actual implementations of corresponding syscalls. -*/ - -struct syscall_stub_table -{ - struct _reent* (*__getreent)(void); - void* (*_malloc_r)(struct _reent *r, size_t); - void (*_free_r)(struct _reent *r, void*); - void* (*_realloc_r)(struct _reent *r, void*, size_t); - void* (*_calloc_r)(struct _reent *r, size_t, size_t); - void (*_abort)(void); - int (*_system_r)(struct _reent *r, const char*); - int (*_rename_r)(struct _reent *r, const char*, const char*); - clock_t (*_times_r)(struct _reent *r, struct tms *); - int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); - void (*_raise_r)(struct _reent *r); - int (*_unlink_r)(struct _reent *r, const char*); - int (*_link_r)(struct _reent *r, const char*, const char*); - int (*_stat_r)(struct _reent *r, const char*, struct stat *); - int (*_fstat_r)(struct _reent *r, int, struct stat *); - void* (*_sbrk_r)(struct _reent *r, ptrdiff_t); - int (*_getpid_r)(struct _reent *r); - int (*_kill_r)(struct _reent *r, int, int); - void (*_exit_r)(struct _reent *r, int); - int (*_close_r)(struct _reent *r, int); - int (*_open_r)(struct _reent *r, const char *, int, int); - int (*_write_r)(struct _reent *r, int, const void *, int); - int (*_lseek_r)(struct _reent *r, int, int, int); - int (*_read_r)(struct _reent *r, int, void *, int); -#ifdef _RETARGETABLE_LOCKING - void (*_retarget_lock_init)(_LOCK_T *lock); - void (*_retarget_lock_init_recursive)(_LOCK_T *lock); - void (*_retarget_lock_close)(_LOCK_T lock); - void (*_retarget_lock_close_recursive)(_LOCK_T lock); - void (*_retarget_lock_acquire)(_LOCK_T lock); - void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); - int (*_retarget_lock_try_acquire)(_LOCK_T lock); - int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); - void (*_retarget_lock_release)(_LOCK_T lock); - void (*_retarget_lock_release_recursive)(_LOCK_T lock); -#else - void (*_lock_init)(_lock_t *lock); - void (*_lock_init_recursive)(_lock_t *lock); - void (*_lock_close)(_lock_t *lock); - void (*_lock_close_recursive)(_lock_t *lock); - void (*_lock_acquire)(_lock_t *lock); - void (*_lock_acquire_recursive)(_lock_t *lock); - int (*_lock_try_acquire)(_lock_t *lock); - int (*_lock_try_acquire_recursive)(_lock_t *lock); - void (*_lock_release)(_lock_t *lock); - void (*_lock_release_recursive)(_lock_t *lock); -#endif - int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap); - int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); - void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn)); - void (*__sinit) (struct _reent *r); - void (*_cleanup_r) (struct _reent* r); -}; - -extern struct syscall_stub_table *syscall_table_ptr; - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif /* _ROM_LIBC_STUBS_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/lldesc.h b/components/esp_rom/include/esp32h4/rom/lldesc.h deleted file mode 100644 index f2db37edfd..0000000000 --- a/components/esp_rom/include/esp32h4/rom/lldesc.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_LLDESC_H_ -#define _ROM_LLDESC_H_ - -#include - -#include "sys/queue.h" -#include "esp_rom_lldesc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define LLDESC_TX_MBLK_SIZE 268 /* */ -#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ -#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ -#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ -#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ -#ifdef ESP_MAC_5 -#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ -#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ -#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 -#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 -#else -#ifdef SBUF_RXTX -#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ -#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ -#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ -#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ -#endif -#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ - -#ifdef IEEE80211_RX_AMPDU -#define LLDESC_RX_MBLK_NUM 30 -#else -#define LLDESC_RX_MBLK_NUM 10 -#endif /*IEEE80211_RX_AMPDU*/ - -#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 -#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 -#endif /* !ESP_MAC_5 */ - -typedef struct tx_ampdu_entry_s { - uint32_t sub_len : 12, - dili_num : 7, - : 1, - null_byte: 2, - data : 1, - enc : 1, - seq : 8; -} tx_ampdu_entry_t; - -typedef struct lldesc_chain_s { - lldesc_t *head; - lldesc_t *tail; -} lldesc_chain_t; - -#ifdef SBUF_RXTX -enum sbuf_mask_s { - SBUF_MOVE_NO = 0, - SBUF_MOVE_TX2RX, - SBUF_MOVE_RX2TX, -} ; - -#define SBUF_MOVE_STEP 8 -#endif -#define LLDESC_SIZE sizeof(struct lldesc_s) - -/* SLC Descriptor */ -#define LLDESC_OWNER_MASK 0x80000000 -#define LLDESC_OWNER_SHIFT 31 -#define LLDESC_SW_OWNED 0 -#define LLDESC_HW_OWNED 1 - -#define LLDESC_EOF_MASK 0x40000000 -#define LLDESC_EOF_SHIFT 30 - -#define LLDESC_SOSF_MASK 0x20000000 -#define LLDESC_SOSF_SHIFT 29 - -#define LLDESC_LENGTH_MASK 0x00fff000 -#define LLDESC_LENGTH_SHIFT 12 - -#define LLDESC_SIZE_MASK 0x00000fff -#define LLDESC_SIZE_SHIFT 0 - -#define LLDESC_ADDR_MASK 0x000fffff - -static inline uint32_t lldesc_get_chain_length(lldesc_t *head) -{ - lldesc_t *ds = head; - uint32_t len = 0; - - while (ds) { - len += ds->length; - ds = STAILQ_NEXT(ds, qe); - } - - return len; -} - -static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) -{ - ds->owner = owner; - ds->eof = eof; - ds->sosf = sosf; - ds->length = len; -} - -#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \ - (_desc)->owner = (_owner); \ - (_desc)->eof = (_eof); \ - (_desc)->sosf = (_sosf); \ - (_desc)->length = (_len); \ -} while(0) - -#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) - -#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) - -#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_LLDESC_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/md5_hash.h b/components/esp_rom/include/esp32h4/rom/md5_hash.h deleted file mode 100644 index 3c5e10d1bf..0000000000 --- a/components/esp_rom/include/esp32h4/rom/md5_hash.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* - * MD5 internal definitions - * Copyright (c) 2003-2005, Jouni Malinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Alternatively, this software may be distributed under the terms of BSD - * license. - * - * See README and COPYING for more details. - */ - -#ifndef _ROM_MD5_HASH_H_ -#define _ROM_MD5_HASH_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct MD5Context { - uint32_t buf[4]; - uint32_t bits[2]; - uint8_t in[64]; -}; - -void MD5Init(struct MD5Context *context); -void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); -void MD5Final(unsigned char digest[16], struct MD5Context *context); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_MD5_HASH_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/miniz.h b/components/esp_rom/include/esp32h4/rom/miniz.h deleted file mode 100644 index f0baecabdc..0000000000 --- a/components/esp_rom/include/esp32h4/rom/miniz.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead" -#include "../../miniz.h" diff --git a/components/esp_rom/include/esp32h4/rom/rom_layout.h b/components/esp_rom/include/esp32h4/rom/rom_layout.h deleted file mode 100644 index 39d80438af..0000000000 --- a/components/esp_rom/include/esp32h4/rom/rom_layout.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Structure and functions for returning ROM global layout - * - * This is for address symbols defined in the linker script, which may change during ECOs. - */ -typedef struct { - void *dram0_stack_shared_mem_start; - void *dram0_rtos_reserved_start; - void *stack_sentry; - void *stack; - - /* BTDM data */ - void *data_start_btdm; - void *data_end_btdm; - void *bss_start_btdm; - void *bss_end_btdm; - void *data_start_btdm_rom; - void *data_end_btdm_rom; - void *data_start_interface_btdm; - void *data_end_interface_btdm; - void *bss_start_interface_btdm; - void *bss_end_interface_btdm; - - void *dram_start_phyrom; - void *dram_end_phyrom; - - void *dram_start_usbdev_rom; - void *dram_end_usbdev_rom; - void *dram_start_uart_rom; - void *dram_end_uart_rom; - -} ets_rom_layout_t; - -extern const ets_rom_layout_t * const ets_rom_layout_p; - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/rsa_pss.h b/components/esp_rom/include/esp32h4/rom/rsa_pss.h deleted file mode 100644 index 2ee06a8ef0..0000000000 --- a/components/esp_rom/include/esp32h4/rom/rsa_pss.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_RSA_PSS_H_ -#define _ROM_RSA_PSS_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define ETS_SIG_LEN 384 /* Bytes */ -#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ - -typedef struct { - uint8_t n[384]; /* Public key modulus */ - uint32_t e; /* Public key exponent */ - uint8_t rinv[384]; - uint32_t mdash; -} ets_rsa_pubkey_t; - -bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); - -void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); - -bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/components/esp_rom/include/esp32h4/rom/rtc.h b/components/esp_rom/include/esp32h4/rom/rtc.h deleted file mode 100644 index ed529a5e40..0000000000 --- a/components/esp_rom/include/esp32h4/rom/rtc.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "esp_assert.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/reset_reasons.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup rtc_apis, rtc registers and memory related apis - * @brief rtc apis - */ - -/** @addtogroup rtc_apis - * @{ - */ - -/************************************************************************************** - * Note: * - * Some Rtc memory and registers are used, in ROM or in internal library. * - * Please do not use reserved or used rtc memory or registers. * - * * - ************************************************************************************* - * RTC Memory & Store Register usage - ************************************************************************************* - * rtc memory addr type size usage - * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry - * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP - * - * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code - * - ************************************************************************************* - * RTC store registers usage - * RTC_CNTL_STORE0_REG Reserved - * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value - * RTC_CNTL_STORE2_REG Boot time, low word - * RTC_CNTL_STORE3_REG Boot time, high word - * RTC_CNTL_STORE4_REG External XTAL frequency - * RTC_CNTL_STORE5_REG APB bus frequency - * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY - * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC - ************************************************************************************* - */ - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG -#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG -#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG -#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG -#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG -#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG -#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG -#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG - -#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. - -typedef enum { - AWAKE = 0, // -#include -#include "ets_sys.h" -#include "rsa_pss.h" -#include "esp_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; -typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; -typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; - -/* Anti-FI measure: use full words for success/fail, instead of - 0/non-zero -*/ -typedef enum { - SB_SUCCESS = 0x3A5A5AA5, - SB_FAILED = 0x7533885E, -} ets_secure_boot_status_t; - -/* Verify bootloader image (reconfigures cache to map), - with key digests provided as parameters.) - - Can be used to verify secure boot status before enabling - secure boot permanently. - - If stage_load parameter is true, bootloader is copied into staging - buffer in RAM at the same time. - - If result is SB_SUCCESS, the "simple hash" of the bootloader is - copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); - -/* Read key digests from efuse. Any revoked/missing digests will be - marked as NULL -*/ -ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); - -/* Verify supplied signature against supplied digest, using - supplied trusted key digests. - - Doesn't reconfigure cache or any other hardware access except for RSA peripheral. - - If result is SB_SUCCESS, the image_digest value is copied into verified_digest. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); - -/* Revoke a public key digest in efuse. - @param index Digest to revoke. Must be 0, 1 or 2. - */ -void ets_secure_boot_revoke_public_key_digest(int index); - -#define CRC_SIGN_BLOCK_LEN 1196 -#define SIG_BLOCK_PADDING 4096 -#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 - -/* Secure Boot V2 signature block - - (Up to 3 in a signature sector are appended to the image) - */ -struct ets_secure_boot_sig_block { - uint8_t magic_byte; - uint8_t version; - uint8_t _reserved1; - uint8_t _reserved2; - uint8_t image_digest[32]; - ets_rsa_pubkey_t key; - uint8_t signature[384]; - uint32_t block_crc; - uint8_t _padding[16]; -}; - -ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); - -#define SECURE_BOOT_NUM_BLOCKS 3 - -/* V2 Secure boot signature sector (up to 3 blocks) */ -struct ets_secure_boot_signature { - ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; - uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; -}; - -ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); - -#define MAX_KEY_DIGESTS 3 - -struct ets_secure_boot_key_digests { - const void *key_digests[MAX_KEY_DIGESTS]; - bool allow_key_revoke; -}; - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/sha.h b/components/esp_rom/include/esp32h4/rom/sha.h deleted file mode 100644 index 80a8ac9335..0000000000 --- a/components/esp_rom/include/esp32h4/rom/sha.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _ROM_SHA_H_ -#define _ROM_SHA_H_ - -#include -#include -#include "ets_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SHA1 = 0, - SHA2_224, - SHA2_256, - SHA_TYPE_MAX -} SHA_TYPE; - -typedef struct SHAContext { - bool start; - bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved - SHA_TYPE type; - uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 - unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 - uint32_t total_bits[4]; -} SHA_CTX; - -void ets_sha_enable(void); - -void ets_sha_disable(void); - -ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); - -ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); - -void ets_sha_get_state(SHA_CTX *ctx); - -void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); - -void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); - -ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_SHA_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/spi_flash.h b/components/esp_rom/include/esp32h4/rom/spi_flash.h deleted file mode 100644 index 6915de9671..0000000000 --- a/components/esp_rom/include/esp32h4/rom/spi_flash.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "esp_attr.h" -#include "esp_rom_spiflash.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) -#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) -#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) -#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) -#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) -#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) -#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) -#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) -#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) - -#define SPI0_R_QIO_DUMMY_CYCLELEN 5 -#define SPI0_R_QIO_ADDR_BITSLEN 23 -#define SPI0_R_FAST_DUMMY_CYCLELEN 7 -#define SPI0_R_DIO_DUMMY_CYCLELEN 3 -#define SPI0_R_FAST_ADDR_BITSLEN 23 -#define SPI0_R_SIO_ADDR_BITSLEN 23 - -#define SPI1_R_QIO_DUMMY_CYCLELEN 5 -#define SPI1_R_QIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_DUMMY_CYCLELEN 7 -#define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_ADDR_BITSLEN 23 -#define SPI1_R_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B - -//SPI address register -#define ESP_ROM_SPIFLASH_BYTES_LEN 24 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf - -typedef void (* spi_flash_func_t)(void); -typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); -typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); -typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); -typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); -typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); -typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); -typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); - -typedef struct { - uint8_t pp_addr_bit_len; - uint8_t se_addr_bit_len; - uint8_t be_addr_bit_len; - uint8_t rd_addr_bit_len; - uint32_t read_sub_len; - uint32_t write_sub_len; - spi_flash_op_t unlock; - spi_flash_erase_t erase_sector; - spi_flash_erase_t erase_block; - spi_flash_rd_t read; - spi_flash_wr_t write; - spi_flash_ewr_t encrypt_write; - spi_flash_func_t check_sus; - spi_flash_wren_t wren; - spi_flash_op_t wait_idle; - spi_flash_erase_area_t erase_area; -} spiflash_legacy_funcs_t; - -typedef struct { - uint8_t data_length; - uint8_t read_cmd0; - uint8_t read_cmd1; - uint8_t write_cmd; - uint16_t data_mask; - uint16_t data; -} esp_rom_spiflash_common_cmd_t; - -/** - * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t *status : The pointer to which to return the Flash status value. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); - -/** - * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t *status : The pointer to which to return the Flash status value. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); - -/** - * @brief Write status to Flash status register. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t status_value : Value to . - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); - -/** - * @brief Use a command to Read Flash status register. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t*status : The pointer to which to return the Flash status value. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); - -/** - * @brief Config SPI Flash read mode when init. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. - * - * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : config error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); - -/** - * @brief Config SPI Flash clock divisor. - * Please do not call this function in SDK. - * - * @param uint8_t freqdiv: clock divisor. - * - * @param uint8_t spi: 0 for SPI0, 1 for SPI1. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : config error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); - -/** - * @brief Clear all SR bits except QE bit. - * Please do not call this function in SDK. - * - * @param None. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); - -/** - * @brief Clear all SR bits except QE bit. - * Please do not call this function in SDK. - * - * @param None. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); - -/** - * @brief Update SPI Flash parameter. - * Please do not call this function in SDK. - * - * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. - * - * @param uint32_t chip_size : The Flash size. - * - * @param uint32_t block_size : The Flash block size. - * - * @param uint32_t sector_size : The Flash sector size. - * - * @param uint32_t page_size : The Flash page size. - * - * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, - uint32_t sector_size, uint32_t page_size, uint32_t status_mask); - -/** - * @brief Erase whole flash chip. - * Please do not call this function in SDK. - * - * @param None - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); - -/** - * @brief Erase a 64KB block of flash - * Uses SPI flash command D8H. - * Please do not call this function in SDK. - * - * @param uint32_t block_num : Which block to erase. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); - -/** - * @brief Erase a sector of flash. - * Uses SPI flash command 20H. - * Please do not call this function in SDK. - * - * @param uint32_t sector_num : Which sector to erase. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); - -/** - * @brief Erase some sectors. - * Please do not call this function in SDK. - * - * @param uint32_t start_addr : Start addr to erase, should be sector aligned. - * - * @param uint32_t area_len : Length to erase, should be sector aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); - -/** - * @brief Write Data to Flash, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. - * - * @param const uint32_t *src : The pointer to data which is to write. - * - * @param uint32_t len : Length to write, should be 4 bytes aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); - -/** - * @brief Read Data from Flash, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. - * - * @param uint32_t *dest : The buf to read the data. - * - * @param uint32_t len : Length to read, should be 4 bytes aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); - -/** - * @brief SPI1 go into encrypto mode. - * Please do not call this function in SDK. - * - * @param None - * - * @return None - */ -void esp_rom_spiflash_write_encrypted_enable(void); - -/** - * @brief SPI1 go out of encrypto mode. - * Please do not call this function in SDK. - * - * @param None - * - * @return None - */ -void esp_rom_spiflash_write_encrypted_disable(void); - -/** - * @brief Write data to flash with transparent encryption. - * @note Sectors to be written should already be erased. - * - * @note Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. - * - * @param uint32_t *data : The pointer to data to write. Note, this pointer must - * be 32 bit aligned and the content of the data will be - * modified by the encryption function. - * - * @param uint32_t len : Length to write, should be 32 bytes aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. - * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); - - -/** @brief Wait until SPI flash write operation is complete - * - * @note Please do not call this function in SDK. - * - * Reads the Write In Progress bit of the SPI flash status register, - * repeats until this bit is zero (indicating write complete). - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete - * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); - - -/** @brief Enable Quad I/O pin functions - * - * @note Please do not call this function in SDK. - * - * Sets the HD & WP pin functions for Quad I/O modes, based on the - * efuse SPI pin configuration. - * - * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. - * - * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). - * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. - * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. - * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used - * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). - * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. - */ -void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); - -/** - * @brief Clear WEL bit unconditionally. - * - * @return always ESP_ROM_SPIFLASH_RESULT_OK - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); - -/** - * @brief Set WREN bit. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @return always ESP_ROM_SPIFLASH_RESULT_OK - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); - -/** - * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. - * Please do not call this function in SDK. - * - * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). - * - * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. - * - * @return None - */ -void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); - -/** - * @brief Set SPI Flash pad drivers. - * Please do not call this function in SDK. - * - * @param uint8_t wp_gpio_num: WP gpio number. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid - * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. - * Values usually read from falsh by rom code, function usually callde by rom code. - * if value with bit(3) set, the value is valid, bit[2:0] is the real value. - * - * @return None - */ -void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); - -/** - * @brief Select SPI Flash function for pads. - * Please do not call this function in SDK. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @return None - */ -void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); - -/** - * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. - * - * @return uint16_t 0 : do not send command any more. - * 1 : go to the next command. - * n > 1 : skip (n - 1) commands. - */ -uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); - -extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/tjpgd.h b/components/esp_rom/include/esp32h4/rom/tjpgd.h deleted file mode 100644 index 46527e1f11..0000000000 --- a/components/esp_rom/include/esp32h4/rom/tjpgd.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/*----------------------------------------------------------------------------/ -/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012 -/----------------------------------------------------------------------------*/ -#ifndef _TJPGDEC -#define _TJPGDEC -/*---------------------------------------------------------------------------*/ -/* System Configurations */ - -#define JD_SZBUF 512 /* Size of stream input buffer */ -#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ -#define JD_USE_SCALE 1 /* Use descaling feature for output */ -#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ - -/*---------------------------------------------------------------------------*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* These types must be 16-bit, 32-bit or larger integer */ -typedef int INT; -typedef unsigned int UINT; - -/* These types must be 8-bit integer */ -typedef char CHAR; -typedef unsigned char UCHAR; -typedef unsigned char BYTE; - -/* These types must be 16-bit integer */ -typedef short SHORT; -typedef unsigned short USHORT; -typedef unsigned short WORD; -typedef unsigned short WCHAR; - -/* These types must be 32-bit integer */ -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long DWORD; - - -/* Error code */ -typedef enum { - JDR_OK = 0, /* 0: Succeeded */ - JDR_INTR, /* 1: Interrupted by output function */ - JDR_INP, /* 2: Device error or wrong termination of input stream */ - JDR_MEM1, /* 3: Insufficient memory pool for the image */ - JDR_MEM2, /* 4: Insufficient stream input buffer */ - JDR_PAR, /* 5: Parameter error */ - JDR_FMT1, /* 6: Data format error (may be damaged data) */ - JDR_FMT2, /* 7: Right format but not supported */ - JDR_FMT3 /* 8: Not supported JPEG standard */ -} JRESULT; - - - -/* Rectangular structure */ -typedef struct { - WORD left, right, top, bottom; -} JRECT; - - - -/* Decompressor object structure */ -typedef struct JDEC JDEC; -struct JDEC { - UINT dctr; /* Number of bytes available in the input buffer */ - BYTE *dptr; /* Current data read ptr */ - BYTE *inbuf; /* Bit stream input buffer */ - BYTE dmsk; /* Current bit in the current read byte */ - BYTE scale; /* Output scaling ratio */ - BYTE msx, msy; /* MCU size in unit of block (width, height) */ - BYTE qtid[3]; /* Quantization table ID of each component */ - SHORT dcv[3]; /* Previous DC element of each component */ - WORD nrst; /* Restart inverval */ - UINT width, height; /* Size of the input image (pixel) */ - BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ - WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */ - BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ - LONG *qttbl[4]; /* Dequaitizer tables [id] */ - void *workbuf; /* Working buffer for IDCT and RGB output */ - BYTE *mcubuf; /* Working buffer for the MCU */ - void *pool; /* Pointer to available memory pool */ - UINT sz_pool; /* Size of momory pool (bytes available) */ - UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */ - void *device; /* Pointer to I/O device identifiler for the session */ -}; - - - -/* TJpgDec API functions */ -JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *); -JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE); - - -#ifdef __cplusplus -} -#endif - -#endif /* _TJPGDEC */ diff --git a/components/esp_rom/include/esp32h4/rom/uart.h b/components/esp_rom/include/esp32h4/rom/uart.h deleted file mode 100644 index 28677ac409..0000000000 --- a/components/esp_rom/include/esp32h4/rom/uart.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_UART_H_ -#define _ROM_UART_H_ - -#include "esp_types.h" -#include "esp_attr.h" -#include "ets_sys.h" -#include "soc/soc.h" -#include "soc/uart_reg.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup uart_apis, uart configuration and communication related apis - * @brief uart apis - */ - -/** @addtogroup uart_apis - * @{ - */ - -#define RX_BUFF_SIZE 0x400 -#define TX_BUFF_SIZE 100 - -//uart int enalbe register ctrl bits -#define UART_RCV_INTEN BIT0 -#define UART_TRX_INTEN BIT1 -#define UART_LINE_STATUS_INTEN BIT2 - -//uart int identification ctrl bits -#define UART_INT_FLAG_MASK 0x0E - -//uart fifo ctrl bits -#define UART_CLR_RCV_FIFO BIT1 -#define UART_CLR_TRX_FIFO BIT2 -#define UART_RCVFIFO_TRG_LVL_BITS BIT6 - -//uart line control bits -#define UART_DIV_LATCH_ACCESS_BIT BIT7 - -//uart line status bits -#define UART_RCV_DATA_RDY_FLAG BIT0 -#define UART_RCV_OVER_FLOW_FLAG BIT1 -#define UART_RCV_PARITY_ERR_FLAG BIT2 -#define UART_RCV_FRAME_ERR_FLAG BIT3 -#define UART_BRK_INT_FLAG BIT4 -#define UART_TRX_FIFO_EMPTY_FLAG BIT5 -#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg -#define UART_RCV_ERR_FLAG BIT7 - -//send and receive message frame head -#define FRAME_FLAG 0x7E - -typedef enum { - UART_LINE_STATUS_INT_FLAG = 0x06, - UART_RCV_FIFO_INT_FLAG = 0x04, - UART_RCV_TMOUT_INT_FLAG = 0x0C, - UART_TXBUFF_EMPTY_INT_FLAG = 0x02 -} UartIntType; //consider bit0 for int_flag - -typedef enum { - RCV_ONE_BYTE = 0x0, - RCV_FOUR_BYTE = 0x1, - RCV_EIGHT_BYTE = 0x2, - RCV_FOURTEEN_BYTE = 0x3 -} UartRcvFifoTrgLvl; - -typedef enum { - FIVE_BITS = 0x0, - SIX_BITS = 0x1, - SEVEN_BITS = 0x2, - EIGHT_BITS = 0x3 -} UartBitsNum4Char; - -typedef enum { - ONE_STOP_BIT = 1, - ONE_HALF_STOP_BIT = 2, - TWO_STOP_BIT = 3 -} UartStopBitsNum; - -typedef enum { - NONE_BITS = 0, - ODD_BITS = 2, - EVEN_BITS = 3 - -} UartParityMode; - -typedef enum { - STICK_PARITY_DIS = 0, - STICK_PARITY_EN = 2 -} UartExistParity; - -typedef enum { - BIT_RATE_9600 = 9600, - BIT_RATE_19200 = 19200, - BIT_RATE_38400 = 38400, - BIT_RATE_57600 = 57600, - BIT_RATE_115200 = 115200, - BIT_RATE_230400 = 230400, - BIT_RATE_460800 = 460800, - BIT_RATE_921600 = 921600 -} UartBautRate; - -typedef enum { - NONE_CTRL, - HARDWARE_CTRL, - XON_XOFF_CTRL -} UartFlowCtrl; - -typedef enum { - EMPTY, - UNDER_WRITE, - WRITE_OVER -} RcvMsgBuffState; - -typedef struct { - uint8_t *pRcvMsgBuff; - uint8_t *pWritePos; - uint8_t *pReadPos; - uint8_t TrigLvl; - RcvMsgBuffState BuffState; -} RcvMsgBuff; - -typedef struct { - uint32_t TrxBuffSize; - uint8_t *pTrxBuff; -} TrxMsgBuff; - -typedef enum { - BAUD_RATE_DET, - WAIT_SYNC_FRM, - SRCH_MSG_HEAD, - RCV_MSG_BODY, - RCV_ESC_CHAR, -} RcvMsgState; - -typedef struct { - UartBautRate baut_rate; - UartBitsNum4Char data_bits; - UartExistParity exist_parity; - UartParityMode parity; // chip size in byte - UartStopBitsNum stop_bits; - UartFlowCtrl flow_ctrl; - uint8_t buff_uart_no; //indicate which uart use tx/rx buffer - RcvMsgBuff rcv_buff; -// TrxMsgBuff trx_buff; - RcvMsgState rcv_state; - int received; -} UartDevice; - -/** - * @brief Init uart device struct value and reset uart0/uart1 rx. - * Please do not call this function in SDK. - * - * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL - * - * @return None - */ -void uartAttach(void *rxBuffer); - -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, else for UART1. - * - * @param uint32_t clock : clock used by uart module, to adjust baudrate. - * - * @return None - */ -void Uart_Init(uint8_t uart_no, uint32_t clock); - -/** - * @brief Modify uart baudrate. - * This function will reset RX/TX fifo for uart. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint32_t DivLatchValue : (clock << 4)/baudrate. - * - * @return None - */ -void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); - -/** - * @brief Switch printf channel of uart_tx_one_char. - * Please do not call this function when printf. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_tx_switch(uint8_t uart_no); - -/** - * @brief Output a char to printf channel, wait until fifo not full. - * - * @param None - * - * @return OK. - */ -ETS_STATUS uart_tx_one_char(uint8_t TxChar); - -/** - * @brief Output a char to message exchange channel, wait until fifo not full. - * Please do not call this function in SDK. - * - * @param None - * - * @return OK. - */ -ETS_STATUS uart_tx_one_char2(uint8_t TxChar); - -/** - * @brief Wait until uart tx full empty. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None. - */ -void uart_tx_flush(uint8_t uart_no); - -/** - * @brief Wait until uart tx full empty and the last char send ok. - * - * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2 - * - * The function defined in ROM code has a bug, so we define the correct version - * here for compatibility. - */ -void uart_tx_wait_idle(uint8_t uart_no); - -/** - * @brief Get an input char from message channel. - * Please do not call this function in SDK. - * - * @param uint8_t *pRxChar : the pointer to store the char. - * - * @return OK for successful. - * FAIL for failed. - */ -ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); - -/** - * @brief Get an input char from message channel, wait until successful. - * Please do not call this function in SDK. - * - * @param None - * - * @return char : input char value. - */ -char uart_rx_one_char_block(void); - -/** - * @brief Get an input string line from message channel. - * Please do not call this function in SDK. - * - * @param uint8_t *pString : the pointer to store the string. - * - * @param uint8_t MaxStrlen : the max string length, incude '\0'. - * - * @return OK. - */ -ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); - -/** - * @brief Get an char from receive buffer. - * Please do not call this function in SDK. - * - * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. - * - * @param uint8_t *pRxByte : the pointer to store the char. - * - * @return OK for successful. - * FAIL for failed. - */ -ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); - -/** - * @brief Get all chars from receive buffer. - * Please do not call this function in SDK. - * - * @param uint8_t *pCmdLn : the pointer to store the string. - * - * @return OK for successful. - * FAIL for failed. - */ -ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); - -/** - * @brief Get uart configuration struct. - * Please do not call this function in SDK. - * - * @param None - * - * @return UartDevice * : uart configuration struct pointer. - */ -UartDevice *GetUartDevice(void); - -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *p : the pointer to output string. - * - * @param int len : the string length. - * - * @return None. - */ -void send_packet(uint8_t *p, int len); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *p : the pointer to input string. - * - * @param int len : If string length > len, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return int : the length of the string. - */ -int recv_packet(uint8_t *p, int len, uint8_t is_sync); - -extern UartDevice UartDev; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_UART_H_ */ diff --git a/components/esp_system/ld/esp32h4/memory.ld.in b/components/esp_system/ld/esp32h4/memory.ld.in deleted file mode 100644 index c51df7b808..0000000000 --- a/components/esp_system/ld/esp32h4/memory.ld.in +++ /dev/null @@ -1,121 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * ESP32-H4 Linker Script Memory Layout - * This file describes the memory layout (memory blocks) by virtual memory addresses. - * This linker script is passed through the C preprocessor to include configuration options. - * Please use preprocessor features sparingly! - * Restrict to simple macros with numeric values, and/or #if/#endif blocks. - */ - -#include "sdkconfig.h" -#include "ld.common" - -#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM -#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC -#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) -#else -#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) -#endif // not CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC -#else -#define ESP_BOOTLOADER_RESERVE_RTC 0 -#endif // not CONFIG_BOOTLOADER_RESERVE_RTC_MEM - -#define SRAM_IRAM_START 0x4037C000 -#define SRAM_DRAM_START 0x3FC7C000 -#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ - -#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) -#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) - -#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG - -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -MEMORY -{ - /** - * All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - * of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - * are connected to the data port of the CPU and eg allow byte-wise access. - */ - - /* IRAM for PRO CPU. */ - iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - /* Flash mapped instruction data */ - iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20 - - /** - * (0x20 offset above is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB).) - */ -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - - /** - * Shared data RAM, excluding memory reserved for ROM bss/data/stack. - * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. - */ - dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - /* Flash mapped constant data */ - drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20 - - /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - - /** - * RTC fast memory (executable). Persists over deep sleep. - */ - rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC -} - -/* Heap ends at top of dram0_0_seg */ -_heap_end = 0x40000000; - -_data_seg_org = ORIGIN(rtc_data_seg); - -/** - * The lines below define location alias for .rtc.data section - * As C3 only has RTC fast memory, this is not configurable like on other targets - */ -REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); -REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); -REGION_ALIAS("rtc_data_location", rtc_iram_seg ); - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - REGION_ALIAS("default_code_seg", iram0_2_seg); -#else - REGION_ALIAS("default_code_seg", iram0_0_seg); -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - REGION_ALIAS("default_rodata_seg", drom0_0_seg); -#else - REGION_ALIAS("default_rodata_seg", dram0_0_seg); -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - -/** - * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must - * also be first in the segment. - */ -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), - ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") -#endif - -#if CONFIG_ESP_SYSTEM_USE_EH_FRAME - ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!"); - ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!"); -#endif diff --git a/components/esp_system/ld/esp32h4/sections.ld.in b/components/esp_system/ld/esp32h4/sections.ld.in deleted file mode 100644 index 43fbf0cb1f..0000000000 --- a/components/esp_system/ld/esp32h4/sections.ld.in +++ /dev/null @@ -1,422 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default entry point */ -ENTRY(call_start_cpu0); - -SECTIONS -{ - /** - * RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - _rtc_fast_start = ABSOLUTE(.); - - mapping[rtc_text] - - *rtc_wake_stub*.*(.literal .text .literal.* .text.*) - *(.rtc_text_end_test) - - /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(4); - - _rtc_text_end = ABSOLUTE(.); - } > rtc_iram_seg - - /** - * This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : - { - . = ALIGN(4); - _rtc_force_fast_start = ABSOLUTE(.); - - mapping[rtc_force_fast] - - *(.rtc.force_fast .rtc.force_fast.*) - . = ALIGN(4) ; - _rtc_force_fast_end = ABSOLUTE(.); - } > rtc_data_seg - - /** - * RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. - * The memory location of the data is dependent on - * CONFIG_ESP32H4_RTCDATA_IN_FAST_MEM option. - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - - mapping[rtc_data] - - *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*) - _rtc_data_end = ABSOLUTE(.); - } > rtc_data_location - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*) - *rtc_wake_stub*.*(COMMON) - - mapping[rtc_bss] - - _rtc_bss_end = ABSOLUTE(.); - } > rtc_data_location - - /** - * This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - * The memory location of the data is dependent on CONFIG_ESP32H4_RTCDATA_IN_FAST_MEM option. - */ - .rtc_noinit (NOLOAD): - { - . = ALIGN(4); - _rtc_noinit_start = ABSOLUTE(.); - *(.rtc_noinit .rtc_noinit.*) - . = ALIGN(4) ; - _rtc_noinit_end = ABSOLUTE(.); - } > rtc_data_location - - /** - * This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg - - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) - ? (_rtc_force_slow_end - _rtc_data_start) - : (_rtc_force_slow_end - _rtc_force_slow_start); - - _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) - ? (_rtc_force_fast_end - _rtc_fast_start) - : (_rtc_noinit_end - _rtc_fast_start); - - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), - "RTC_SLOW segment data does not fit.") - - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), - "RTC_FAST segment data does not fit.") - - .iram0.text : - { - _iram_start = ABSOLUTE(.); - /* Vectors go to start of IRAM */ - ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); - KEEP(*(.exception_vectors.text)); - . = ALIGN(4); - - _invalid_pc_placeholder = ABSOLUTE(.); - - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - - mapping[iram0_text] - - } > iram0_0_seg - - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - .dram0.dummy (NOLOAD): - { - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } > dram0_0_seg - - .dram0.data : - { - _data_start = ABSOLUTE(.); - *(.gnu.linkonce.d.*) - *(.data1) - __global_pointer$ = . + 0x800; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - - mapping[dram0_data] - - _data_end = ABSOLUTE(.); - . = ALIGN(4); - } > dram0_0_seg - - /** - * This section holds data that should not be initialized at power up. - * The section located in Internal SRAM memory region. The macro _NOINIT - * can be used as attribute to place data into this section. - * See the "esp_attr.h" file for more information. - */ - .noinit (NOLOAD): - { - . = ALIGN(4); - _noinit_start = ABSOLUTE(.); - *(.noinit .noinit.*) - . = ALIGN(4) ; - _noinit_end = ABSOLUTE(.); - } > dram0_0_seg - - /* Shared RAM */ - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - - mapping[dram0_bss] - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.share.mem) - *(.gnu.linkonce.b.*) - - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } > dram0_0_seg - - ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - - .flash.text : - { - _stext = .; - _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ - _text_start = ABSOLUTE(.); - - mapping[flash_text] - - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /** CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ - _etext = .; - - /** - * Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } > default_code_seg - - /** - * This dummy section represents the .flash.text section but in default_rodata_seg. - * Thus, it must have its alignment and (at least) its size. - */ - .flash_rodata_dummy (NOLOAD): - { - _flash_rodata_dummy_start = .; - /* Start at the same alignment constraint than .flash.text */ - . = ALIGN(ALIGNOF(.flash.text)); - /* Create an empty gap as big as .flash.text section */ - . = . + SIZEOF(.flash.text); - /* Prepare the alignment of the section above. Few bytes (0x20) must be - * added for the mapping header. */ - . = ALIGN(_esp_mmu_block_size) + 0x20; - } > default_rodata_seg - - .flash.appdesc : ALIGN(0x10) - { - _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - /* Create an empty gap within this section. Thanks to this, the end of this - * section will match .flash.rodata's begin address. Thus, both sections - * will be merged when creating the final bin image. */ - . = ALIGN(ALIGNOF(.flash.rodata)); - } >default_rodata_seg - - .flash.rodata : ALIGN(0x10) - { - _flash_rodata_start = ABSOLUTE(.); - - mapping[flash_rodata] - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 7) & ~ 3; - /* - * C++ constructor and destructor tables - * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt. - * - * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead. - * But the init_priority sections will be sorted for iteration in ascending order during startup. - * The rest of the init_array sections is sorted for iteration in descending order during startup, however. - * Hence a different section is generated for the init_priority functions which is iterated in - * ascending order during startup. The corresponding code can be found in startup.c. - */ - __init_priority_array_start = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) - __init_priority_array_end = ABSOLUTE(.); - __init_array_start = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) - __init_array_end = ABSOLUTE(.); - KEEP (*crtbegin.*(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ - soc_reserved_memory_region_start = ABSOLUTE(.); - KEEP (*(.reserved_memory_address)) - soc_reserved_memory_region_end = ABSOLUTE(.); - /* System init functions registered via ESP_SYSTEM_INIT_FN */ - _esp_system_init_fn_array_start = ABSOLUTE(.); - KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) - _esp_system_init_fn_array_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) - _thread_local_end = ABSOLUTE(.); - . = ALIGN(ALIGNOF(.eh_frame)); - } > default_rodata_seg - - /* Keep this section shall be at least aligned on 4 */ - .eh_frame : ALIGN(4) - { - __eh_frame = ABSOLUTE(.); - KEEP (*(.eh_frame)) - __eh_frame_end = ABSOLUTE(.); - /* Guarantee that this section and the next one will be merged by making - * them adjacent. */ - . = ALIGN(ALIGNOF(.eh_frame_hdr)); - } > default_rodata_seg - - /* To avoid any exception in C++ exception frame unwinding code, this section - * shall be aligned on 8. */ - .eh_frame_hdr : ALIGN(8) - { - __eh_frame_hdr = ABSOLUTE(.); - KEEP (*(.eh_frame_hdr)) - __eh_frame_hdr_end = ABSOLUTE(.); - } > default_rodata_seg - - /* - This section is a place where we dump all the rodata which aren't used at runtime, - so as to avoid binary size increase - */ - .flash.rodata_noload (NOLOAD) : - { - /* - This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address - We don't need to include the noload rodata in this section - */ - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN (4); - } > default_rodata_seg - - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) - - /* ESP32-H4 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - - _iram_text_end = ABSOLUTE(.); - } > iram0_0_seg - - .iram0.data : - { - . = ALIGN(16); - _iram_data_start = ABSOLUTE(.); - - mapping[iram0_data] - - _iram_data_end = ABSOLUTE(.); - } > iram0_0_seg - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - _iram_bss_start = ABSOLUTE(.); - - mapping[iram0_bss] - - _iram_bss_end = ABSOLUTE(.); - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } > iram0_0_seg - - /* Marks the end of data, bss and possibly rodata */ - .dram0.heap_start (NOLOAD) : - { - . = ALIGN (16); - _heap_start = ABSOLUTE(.); - } > dram0_0_seg -} - -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), - "DRAM segment data does not fit.") diff --git a/components/esp_system/port/soc/esp32h4/CMakeLists.txt b/components/esp_system/port/soc/esp32h4/CMakeLists.txt deleted file mode 100644 index a8034a3b9d..0000000000 --- a/components/esp_system/port/soc/esp32h4/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -set(srcs "clk.c" - "reset_reason.c" - "system_internal.c" - "cache_err_int.c" - "apb_backup_dma.c" - "../../arch/riscv/expression_with_stack.c" - "../../arch/riscv/expression_with_stack_asm.S" - "../../arch/riscv/panic_arch.c" - "../../arch/riscv/debug_stubs.c") - -add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs}) - -target_sources(${COMPONENT_LIB} PRIVATE ${srcs}) diff --git a/components/esp_system/port/soc/esp32h4/Kconfig.cpu b/components/esp_system/port/soc/esp32h4/Kconfig.cpu deleted file mode 100644 index 565e50ff57..0000000000 --- a/components/esp_system/port/soc/esp32h4/Kconfig.cpu +++ /dev/null @@ -1,27 +0,0 @@ -choice ESP_DEFAULT_CPU_FREQ_MHZ - prompt "CPU frequency" - default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA - default ESP_DEFAULT_CPU_FREQ_MHZ_96 if !IDF_ENV_FPGA - help - CPU frequency to be set on application startup. - - config ESP_DEFAULT_CPU_FREQ_MHZ_16 - bool "16 MHz" - depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786 - config ESP_DEFAULT_CPU_FREQ_MHZ_32 - bool "32 MHz" - depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786 - config ESP_DEFAULT_CPU_FREQ_MHZ_64 - bool "64 MHz" - depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786 - config ESP_DEFAULT_CPU_FREQ_MHZ_96 - bool "96 MHz" - depends on !IDF_ENV_FPGA -endchoice - -config ESP_DEFAULT_CPU_FREQ_MHZ - int - default 16 if ESP_DEFAULT_CPU_FREQ_MHZ_16 - default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32 - default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64 - default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96 diff --git a/components/esp_system/port/soc/esp32h4/Kconfig.system b/components/esp_system/port/soc/esp32h4/Kconfig.system deleted file mode 100644 index 95ec81ea7e..0000000000 --- a/components/esp_system/port/soc/esp32h4/Kconfig.system +++ /dev/null @@ -1,45 +0,0 @@ -menu "Brownout Detector" - - config ESP_BROWNOUT_DET - bool "Hardware brownout detect & reset" - default y - help - The ESP32-H4 has a built-in brownout detector which can detect if the voltage is lower than - a specific value. If this happens, it will reset the chip in order to prevent unintended - behaviour. - - choice ESP_BROWNOUT_DET_LVL_SEL - prompt "Brownout voltage level" - depends on ESP_BROWNOUT_DET - default ESP_BROWNOUT_DET_LVL_SEL_7 - help - The brownout detector will reset the chip when the supply voltage is approximately - below this level. Note that there may be some variation of brownout voltage level - between each chip. - - #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages - #of the brownout threshold levels. - config ESP_BROWNOUT_DET_LVL_SEL_7 - bool "2.51V" - config ESP_BROWNOUT_DET_LVL_SEL_6 - bool "2.64V" - config ESP_BROWNOUT_DET_LVL_SEL_5 - bool "2.76V" - config ESP_BROWNOUT_DET_LVL_SEL_4 - bool "2.92V" - config ESP_BROWNOUT_DET_LVL_SEL_3 - bool "3.10V" - config ESP_BROWNOUT_DET_LVL_SEL_2 - bool "3.27V" - endchoice - - config ESP_BROWNOUT_DET_LVL - int - default 2 if ESP_BROWNOUT_DET_LVL_SEL_2 - default 3 if ESP_BROWNOUT_DET_LVL_SEL_3 - default 4 if ESP_BROWNOUT_DET_LVL_SEL_4 - default 5 if ESP_BROWNOUT_DET_LVL_SEL_5 - default 6 if ESP_BROWNOUT_DET_LVL_SEL_6 - default 7 if ESP_BROWNOUT_DET_LVL_SEL_7 - -endmenu diff --git a/components/esp_system/port/soc/esp32h4/apb_backup_dma.c b/components/esp_system/port/soc/esp32h4/apb_backup_dma.c deleted file mode 100644 index 5f14c456d7..0000000000 --- a/components/esp_system/port/soc/esp32h4/apb_backup_dma.c +++ /dev/null @@ -1,40 +0,0 @@ - -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/soc_caps.h" - -#if SOC_APB_BACKUP_DMA -#include "esp_attr.h" -#include "freertos/FreeRTOS.h" -#include "freertos/portmacro.h" -#include "esp32h4/rom/apb_backup_dma.h" - -static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED; - -static void IRAM_ATTR apb_backup_dma_lock(void) -{ - if (xPortInIsrContext()) { - portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex); - } else { - portENTER_CRITICAL(&s_apb_backup_dma_mutex); - } -} - -static void IRAM_ATTR apb_backup_dma_unlock(void) -{ - if (xPortInIsrContext()) { - portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex); - } else { - portEXIT_CRITICAL(&s_apb_backup_dma_mutex); - } -} - -void esp_apb_backup_dma_lock_init(void) -{ - ets_apb_backup_init_lock_func(apb_backup_dma_lock, apb_backup_dma_unlock); -} -#endif diff --git a/components/esp_system/port/soc/esp32h4/cache_err_int.c b/components/esp_system/port/soc/esp32h4/cache_err_int.c deleted file mode 100644 index 5c24fed65b..0000000000 --- a/components/esp_system/port/soc/esp32h4/cache_err_int.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - The cache has an interrupt that can be raised as soon as an access to a cached - region (flash) is done without the cache being enabled. We use that here - to panic the CPU, which from a debugging perspective is better than grabbing bad - data from the bus. -*/ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "esp_log.h" -#include "esp_intr_alloc.h" -#include "soc/periph_defs.h" -#include "riscv/interrupt.h" -#include "hal/cache_ll.h" - -static const char *TAG = "CACHE_ERR"; - -void esp_cache_err_int_init(void) -{ - const uint32_t core_id = 0; - - /* Disable cache interrupts if enabled. */ - ESP_INTR_DISABLE(ETS_CACHEERR_INUM); - - /** - * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with - * them in handler by different types - * I) Cache access error - * 1. dbus trying to write to icache - * 2. dbus authentication fail - * 3. cpu access icache while dbus is disabled [1] - * 4. ibus authentication fail - * 5. ibus trying to write icache - * 6. cpu access icache while ibus is disabled - * II) Cache illegal error - * 1. dbus counter overflow - * 2. ibus counter overflow - * 3. mmu entry fault - * 4. icache preload configurations fault - * 5. icache sync configuration fault - * - * [1]: On ESP32H4 boards, the caches are shared but buses are still - * distinct. So, we have an ibus and a dbus sharing the same cache. - * This error can occur if the dbus performs a request but the icache - * (or simply cache) is disabled. - */ - esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM); - esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); - - /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); - esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); - - ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); - /* On the hardware side, start by clearing all the bits reponsible for cache access error */ - cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Then enable cache access error interrupts. */ - cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - - /* Same goes for cache illegal error: start by clearing the bits and then - * set them back. */ - ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - - /* Enable the interrupts for cache error. */ - ESP_INTR_ENABLE(ETS_CACHEERR_INUM); -} - -int esp_cache_err_get_cpuid(void) -{ - return 0; -} diff --git a/components/esp_system/port/soc/esp32h4/clk.c b/components/esp_system/port/soc/esp32h4/clk.c deleted file mode 100644 index cb6c0a073a..0000000000 --- a/components/esp_system/port/soc/esp32h4/clk.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include "sdkconfig.h" -#include "esp_attr.h" -#include "esp_log.h" -#include "esp_cpu.h" -#include "esp_clk_internal.h" -#include "esp32h4/rom/ets_sys.h" -#include "esp32h4/rom/uart.h" -#include "esp32h4/rom/rtc.h" -#include "soc/system_reg.h" -#include "soc/soc.h" -#include "soc/rtc.h" -#include "soc/rtc_periph.h" -#include "soc/i2s_reg.h" -#include "hal/wdt_hal.h" -#include "esp_private/periph_ctrl.h" -#include "esp_private/esp_clk.h" -#include "bootloader_clock.h" -#include "soc/syscon_reg.h" -#include "esp_rom_uart.h" - -/* Number of cycles to wait from the 32k XTAL oscillator to consider it running. - * Larger values increase startup delay. Smaller values may cause false positive - * detection (i.e. oscillator runs for a few cycles and then stops). - */ -#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES - -#define MHZ (1000000) - -/* Indicates that this 32k oscillator gets input from external oscillator, rather - * than a crystal. - */ -#define EXT_OSC_FLAG BIT(3) - -/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define - * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. - */ -typedef enum { - SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator - SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL - SLOW_CLK_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32 KHz RC oscillator - SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin -} slow_clk_sel_t; - -static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); - -static const char *TAG = "clk"; - - - __attribute__((weak)) void esp_clk_init(void) -{ - rtc_config_t cfg = RTC_CONFIG_DEFAULT(); - soc_reset_reason_t rst_reas; - rst_reas = esp_rom_get_reset_reason(0); - if (rst_reas == RESET_REASON_CHIP_POWER_ON) { - cfg.cali_ocode = 1; - } - rtc_init(cfg); - - assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M); - - rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); - -#ifdef CONFIG_BOOTLOADER_WDT_ENABLE - // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. - // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times. - // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec). - // This prevents excessive delay before resetting in case the supply voltage is drawdown. - // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec). - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_feed(&rtc_wdt_ctx); - //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#endif - -#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS) - select_rtc_slow_clk(SLOW_CLK_32K_XTAL); -#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) - select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC); -#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K) - select_rtc_slow_clk(SLOW_CLK_RC32K); -#else - select_rtc_slow_clk(SLOW_CLK_RTC); -#endif - -#ifdef CONFIG_BOOTLOADER_WDT_ENABLE - // After changing a frequency WDT timeout needs to be set for new frequency. - stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_feed(&rtc_wdt_ctx); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#endif - - rtc_cpu_freq_config_t old_config, new_config; - rtc_clk_cpu_freq_get_config(&old_config); - const uint32_t old_freq_mhz = old_config.freq_mhz; - const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ; - - bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config); - assert(res); - - // Wait for UART TX to finish, otherwise some UART output will be lost - // when switching APB frequency - esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); - - if (res) { - rtc_clk_cpu_freq_set_config(&new_config); - } - - // Re calculate the ccount to make time calculation correct. - esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz ); -} - -static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) -{ - soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; - uint32_t cal_val = 0; - /* number of times to repeat 32k XTAL calibration - * before giving up and switching to the internal RC - */ - int retry_32k_xtal = 3; - - do { - if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - /* 32k XTAL oscillator needs to be enabled and running before it can - * be used. Hardware doesn't have a direct way of checking if the - * oscillator is running. Here we use rtc_clk_cal function to count - * the number of main XTAL cycles in the given number of 32k XTAL - * oscillator cycles. If the 32k XTAL has not started up, calibration - * will time out, returning 0. - */ - ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); - if (slow_clk == SLOW_CLK_32K_XTAL) { - rtc_clk_32k_enable(true); - } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) { - rtc_clk_32k_enable_external(); - } - // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. - if (SLOW_CLK_CAL_CYCLES > 0) { - cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0) { - if (retry_32k_xtal-- > 0) { - continue; - } - ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); - rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; - } - } - } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); - } - rtc_clk_slow_src_set(rtc_slow_clk_src); - - if (SLOW_CLK_CAL_CYCLES > 0) { - /* TODO: 32k XTAL oscillator has some frequency drift at startup. - * Improve calibration routine to wait until the frequency is stable. - */ - cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); - } else { - const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; - cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz()); - } - } while (cal_val == 0); - ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val); - esp_clk_slowclk_cal_set(cal_val); -} - -void rtc_clk_select_rtc_slow_clk(void) -{ - select_rtc_slow_clk(SLOW_CLK_32K_XTAL); -} - -/* This function is not exposed as an API at this point. - * All peripheral clocks are default enabled after chip is powered on. - * This function disables some peripheral clocks when cpu starts. - * These peripheral clocks are enabled when the peripherals are initialized - * and disabled when they are de-initialized. - */ -__attribute__((weak)) void esp_perip_clk_init(void) -{ - uint32_t common_perip_clk, hwcrypto_perip_clk = 0; - uint32_t common_perip_clk1 = 0; - - soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - - /* For reason that only reset CPU, do not disable the clocks - * that have been enabled before reset. - */ - if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || - rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1 || - rst_reason == RESET_REASON_CPU0_JTAG) { - common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); - } else { - common_perip_clk = SYSTEM_WDG_CLK_EN | - SYSTEM_I2S0_CLK_EN | -#if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | -#endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_LEDC_CLK_EN | - SYSTEM_TIMERGROUP1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_TWAI_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - - common_perip_clk1 = 0; - hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | - SYSTEM_CRYPTO_SHA_CLK_EN | - SYSTEM_CRYPTO_RSA_CLK_EN; - } - - //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. - common_perip_clk |= SYSTEM_I2S0_CLK_EN | -#if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | -#endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_UHCI1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - common_perip_clk1 = 0; - - /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, - * the current is not reduced when disable I2S clock. - */ - // TOCK(check replacement) - // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - - /* Disable some peripheral clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); - - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1); - - /* Disable hardware crypto clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk); - - /* Enable RNG clock. */ - periph_module_enable(PERIPH_RNG_MODULE); - - /* Enable TimerGroup 0 clock to ensure its reference counter will never - * be decremented to 0 during normal operation and preventing it from - * being disabled. - * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog - * registers (Flashboot protection included) will be reenabled, and some - * seconds later, will trigger an unintended reset. - */ - periph_module_enable(PERIPH_TIMG0_MODULE); -} diff --git a/components/esp_system/port/soc/esp32h4/reset_reason.c b/components/esp_system/port/soc/esp32h4/reset_reason.c deleted file mode 100644 index 3bebada459..0000000000 --- a/components/esp_system/port/soc/esp32h4/reset_reason.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_system.h" -#include "esp_rom_sys.h" -#include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" -#include "esp32h4/rom/rtc.h" - -static void esp_reset_reason_clear_hint(void); - -static esp_reset_reason_t s_reset_reason; - -static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint) -{ - switch (rtc_reset_reason) { - case RESET_REASON_CHIP_POWER_ON: - return ESP_RST_POWERON; - - case RESET_REASON_CPU0_SW: - case RESET_REASON_CORE_SW: - if (reset_reason_hint == ESP_RST_PANIC || - reset_reason_hint == ESP_RST_BROWNOUT || - reset_reason_hint == ESP_RST_TASK_WDT || - reset_reason_hint == ESP_RST_INT_WDT) { - return reset_reason_hint; - } - return ESP_RST_SW; - - case RESET_REASON_CORE_DEEP_SLEEP: - return ESP_RST_DEEPSLEEP; - - case RESET_REASON_CORE_MWDT0: - return ESP_RST_TASK_WDT; - - case RESET_REASON_CORE_MWDT1: - return ESP_RST_INT_WDT; - - case RESET_REASON_CORE_RTC_WDT: - case RESET_REASON_SYS_RTC_WDT: - case RESET_REASON_SYS_SUPER_WDT: - case RESET_REASON_CPU0_RTC_WDT: - case RESET_REASON_CPU0_MWDT0: - case RESET_REASON_CPU0_MWDT1: - return ESP_RST_WDT; - - case RESET_REASON_SYS_BROWN_OUT: - return ESP_RST_BROWNOUT; - - case RESET_REASON_CORE_USB_UART: - case RESET_REASON_CORE_USB_JTAG: - return ESP_RST_USB; - - default: - return ESP_RST_UNKNOWN; - } -} - -static void __attribute__((constructor)) esp_reset_reason_init(void) -{ - esp_reset_reason_t hint = esp_reset_reason_get_hint(); - s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint); - if (hint != ESP_RST_UNKNOWN) { - esp_reset_reason_clear_hint(); - } -} - -esp_reset_reason_t esp_reset_reason(void) -{ - return s_reset_reason; -} - -/* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG, - * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the - * deep sleep wake stub entry address and for reset reason hint, since wake stub - * is only used for deep sleep reset, and in this case the reason provided by - * esp_rom_get_reset_reason is unambiguous. - * - * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): - * the value is replicated in low and high half-words. In addition to that, - * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains - * deep sleep wake stub address. - */ - -#define RST_REASON_BIT 0x80000000 -#define RST_REASON_MASK 0x7FFF -#define RST_REASON_SHIFT 16 - -/* in IRAM, can be called from panic handler */ -void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint) -{ - assert((hint & (~RST_REASON_MASK)) == 0); - uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT; - REG_WRITE(RTC_RESET_CAUSE_REG, val); -} - -/* in IRAM, can be called from panic handler */ -esp_reset_reason_t esp_reset_reason_get_hint(void) -{ - uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); - uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; - uint32_t low = reset_reason_hint & RST_REASON_MASK; - if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) { - return ESP_RST_UNKNOWN; - } - return (esp_reset_reason_t) low; -} -static inline void esp_reset_reason_clear_hint(void) -{ - REG_WRITE(RTC_RESET_CAUSE_REG, 0); -} diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c deleted file mode 100644 index b6c3b72ca7..0000000000 --- a/components/esp_system/port/soc/esp32h4/system_internal.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdkconfig.h" -#include "esp_system.h" -#include "esp_private/system_internal.h" -#include "esp_attr.h" -#include "esp_efuse.h" -#include "esp_log.h" -#include "riscv/rv_utils.h" -#include "esp_rom_uart.h" -#include "soc/gpio_reg.h" -#include "soc/timer_group_reg.h" -#include "esp_cpu.h" -#include "soc/rtc.h" -#include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" -#include "soc/syscon_reg.h" -#include "soc/system_reg.h" -#include "hal/wdt_hal.h" -#include "esp_private/cache_err_int.h" - -#include "esp32h4/rom/cache.h" -#include "esp32h4/rom/rtc.h" - -/* "inner" restart function for after RTOS, interrupts & anything else on this - * core are already stopped. Stalls other core, resets hardware, - * triggers restart. -*/ -void IRAM_ATTR esp_restart_noos(void) -{ - // Disable interrupts - rv_utils_intr_global_disable(); - // Enable RTC watchdog for 1 second - wdt_hal_context_t rtc_wdt_ctx; - wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); - uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT. - wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - - // Disable TG0/TG1 watchdogs - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - // Disable cache - Cache_Disable_ICache(); - - // 2nd stage bootloader reconfigures SPI flash signals. - // Reset them to the defaults expected by ROM. - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - // Reset timer/spi/uart - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, - SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST | - SYSTEM_BT_RST | SYSTEM_BTMAC_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | - SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST - ); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0); - - // Reset dma - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader. -#if !CONFIG_IDF_ENV_FPGA - rtc_clk_cpu_set_to_default_config(); -#endif - - // Reset CPU - esp_rom_software_reset_cpu(0); - while (true) { - ; - } -} diff --git a/components/heap/port/esp32h4/memory_layout.c b/components/heap/port/esp32h4/memory_layout.c deleted file mode 100644 index d0875728c5..0000000000 --- a/components/heap/port/esp32h4/memory_layout.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "esp_attr.h" -#include "sdkconfig.h" -#include "soc/soc.h" -#include "heap_memory_layout.h" -#include "esp_heap_caps.h" - -/** - * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. - * Each type of memory map consists of one or more regions in the address space. - * Each type contains an array of prioritized capabilities. - * Types with later entries are only taken if earlier ones can't fulfill the memory request. - * - * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. - * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. - * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. - * - Most other malloc caps only fit in one region anyway. - * - */ -/* Index of memory in `soc_memory_types[]` */ -enum { - SOC_MEMORY_TYPE_DRAM = 0, - SOC_MEMORY_TYPE_STACK_DRAM = 1, - SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_STACK_DIRAM = 3, - SOC_MEMORY_TYPE_RTCRAM = 4, - SOC_MEMORY_TYPE_NUM, -}; - -const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { - // Type 0: DRAM - [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, - // Type 1: DRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, - // Type 2: DRAM which has an alias on the I-port - [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: DIRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, - // Type 4: RTCRAM - [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, -}; - -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE -#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM -#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM -#else -#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM -#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM -#endif - -const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); - -/** - * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. - * - * @note Because of requirements in the coalescing code which merges adjacent regions, - * this list should always be sorted from low to high by start address. - * - */ - -/** - * Register the shared buffer area of the last memory block into the heap during heap initialization - */ -#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) - -const soc_memory_region_t soc_memory_regions[] = { - { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory - { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory - { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) -#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory -#endif -}; - -const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); - - -extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; - -/** - * Reserved memory regions. - * These are removed from the soc_memory_regions array when heaps are created. - * - */ - -// Static data region. DRAM used by data+bss and possibly rodata -SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); - -// Target has a big D/IRAM region, the part used by code is reserved -// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address -#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) -SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); - -#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP -/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW - region on H4, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. -*/ -SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); -#endif diff --git a/components/idf_test/include/esp32h4/idf_performance_target.h b/components/idf_test/include/esp32h4/idf_performance_target.h deleted file mode 100644 index 8e3a78e259..0000000000 --- a/components/idf_test/include/esp32h4/idf_performance_target.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 43 - -// SHA256 hardware throughput at 160 MHz, threshold set lower than worst case -#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90 -// esp_sha() time to process 32KB of input data from RAM -#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 560 - -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000 -#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000 -#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 670000 - -#define IDF_PERFORMANCE_MAX_ECP_P192_POINT_MULTIPLY_OP 9000 -#define IDF_PERFORMANCE_MAX_ECP_P192_POINT_VERIFY_OP 300 -#define IDF_PERFORMANCE_MAX_ECP_P256_POINT_MULTIPLY_OP 14000 -#define IDF_PERFORMANCE_MAX_ECP_P256_POINT_VERIFY_OP 300 - -#define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 32000 -#define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 49000 - -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 - -// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) -#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 -#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/mbedtls/port/esp32h4/bignum.c b/components/mbedtls/port/esp32h4/bignum.c deleted file mode 100644 index 4a674ee8b0..0000000000 --- a/components/mbedtls/port/esp32h4/bignum.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Multi-precision integer library - * ESP32 H4 hardware accelerated parts based on mbedTLS implementation - * - * SPDX-FileCopyrightText: The Mbed TLS Contributors - * - * SPDX-License-Identifier: Apache-2.0 - * - * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD - */ -#include -#include -#include "soc/hwcrypto_periph.h" -#include "esp_private/periph_ctrl.h" -#include "mbedtls/bignum.h" -#include "bignum_impl.h" -#include "soc/system_reg.h" -#include "soc/periph_defs.h" -#include "esp_crypto_lock.h" - - -size_t esp_mpi_hardware_words(size_t words) -{ - return words; -} - -void esp_mpi_enable_hardware_hw_op( void ) -{ - esp_crypto_mpi_lock_acquire(); - - /* Enable RSA hardware */ - periph_module_enable(PERIPH_RSA_MODULE); - - REG_CLR_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD); - - while (REG_READ(RSA_QUERY_CLEAN_REG) != 1) { - } - // Note: from enabling RSA clock to here takes about 1.3us - - REG_WRITE(RSA_INTERRUPT_REG, 0); -} - -void esp_mpi_disable_hardware_hw_op( void ) -{ - REG_SET_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD); - - /* Disable RSA hardware */ - periph_module_disable(PERIPH_RSA_MODULE); - - esp_crypto_mpi_lock_release(); -} - -void esp_mpi_interrupt_enable( bool enable ) -{ - REG_WRITE(RSA_INTERRUPT_REG, enable); -} - -void esp_mpi_interrupt_clear( void ) -{ - REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); -} - -/* Copy mbedTLS MPI bignum 'mpi' to hardware memory block at 'mem_base'. - - If num_words is higher than the number of words in the bignum then - these additional words will be zeroed in the memory buffer. -*/ -static inline void mpi_to_mem_block(uint32_t mem_base, const mbedtls_mpi *mpi, size_t num_words) -{ - uint32_t *pbase = (uint32_t *)mem_base; - uint32_t copy_words = MIN(num_words, mpi->MBEDTLS_PRIVATE(n)); - - /* Copy MPI data to memory block registers */ - for (int i = 0; i < copy_words; i++) { - pbase[i] = mpi->MBEDTLS_PRIVATE(p)[i]; - } - - /* Zero any remaining memory block data */ - for (int i = copy_words; i < num_words; i++) { - pbase[i] = 0; - } -} - -/* Read mbedTLS MPI bignum back from hardware memory block. - - Reads num_words words from block. -*/ -static inline void mem_block_to_mpi(mbedtls_mpi *x, uint32_t mem_base, int num_words) -{ - - /* Copy data from memory block registers */ - const size_t REG_WIDTH = sizeof(uint32_t); - for (size_t i = 0; i < num_words; i++) { - x->MBEDTLS_PRIVATE(p)[i] = REG_READ(mem_base + (i * REG_WIDTH)); - } - /* Zero any remaining limbs in the bignum, if the buffer is bigger - than num_words */ - for (size_t i = num_words; i < x->MBEDTLS_PRIVATE(n); i++) { - x->MBEDTLS_PRIVATE(p)[i] = 0; - } -} - - - -/* Begin an RSA operation. op_reg specifies which 'START' register - to write to. -*/ -static inline void start_op(uint32_t op_reg) -{ - /* Clear interrupt status */ - REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); - - /* Note: above REG_WRITE includes a memw, so we know any writes - to the memory blocks are also complete. */ - - REG_WRITE(op_reg, 1); -} - -/* Wait for an RSA operation to complete. -*/ -static inline void wait_op_complete(void) -{ - while (REG_READ(RSA_QUERY_INTERRUPT_REG) != 1) - { } - - /* clear the interrupt */ - REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); -} - - -/* Read result from last MPI operation */ -void esp_mpi_read_result_hw_op(mbedtls_mpi *Z, size_t z_words) -{ - wait_op_complete(); - mem_block_to_mpi(Z, RSA_MEM_Z_BLOCK_BASE, z_words); -} - - -/* Z = (X * Y) mod M - - Not an mbedTLS function -*/ -void esp_mpi_mul_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words) -{ - REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); - - /* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); - mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); - mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); - REG_WRITE(RSA_M_DASH_REG, Mprime); - - start_op(RSA_MOD_MULT_START_REG); -} - -/* Z = (X ^ Y) mod M -*/ -void esp_mpi_exp_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words) -{ - size_t y_bits = mbedtls_mpi_bitlen(Y); - - REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); - - /* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); - mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); - mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); - REG_WRITE(RSA_M_DASH_REG, Mprime); - - /* Enable acceleration options */ - REG_WRITE(RSA_CONSTANT_TIME_REG, 0); - REG_WRITE(RSA_SEARCH_ENABLE_REG, 1); - REG_WRITE(RSA_SEARCH_POS_REG, y_bits - 1); - - /* Execute first stage montgomery multiplication */ - start_op(RSA_MODEXP_START_REG); - - REG_WRITE(RSA_SEARCH_ENABLE_REG, 0); -} - - -/* Z = X * Y */ -void esp_mpi_mul_mpi_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words) -{ - /* Copy X (right-extended) & Y (left-extended) to memory block */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Z_BLOCK_BASE + num_words * 4, Y, num_words); - /* NB: as Y is left-extended, we don't zero the bottom words_mult words of Y block. - This is OK for now because zeroing is done by hardware when we do esp_mpi_acquire_hardware(). - */ - REG_WRITE(RSA_LENGTH_REG, (num_words * 2 - 1)); - start_op(RSA_MULT_START_REG); -} - - - -/** - * @brief Special-case of (X * Y), where we use hardware montgomery mod - multiplication to calculate result where either A or B are >2048 bits so - can't use the standard multiplication method. - * - */ -void esp_mpi_mult_mpi_failover_mod_mult_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words) -{ - /* M = 2^num_words - 1, so block is entirely FF */ - for (int i = 0; i < num_words; i++) { - REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); - } - - /* Mprime = 1 */ - REG_WRITE(RSA_M_DASH_REG, 1); - REG_WRITE(RSA_LENGTH_REG, num_words - 1); - - /* Load X & Y */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); - - /* Rinv = 1, write first word */ - REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); - - /* Zero out rest of the Rinv words */ - for (int i = 1; i < num_words; i++) { - REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); - } - - start_op(RSA_MOD_MULT_START_REG); -} diff --git a/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 deleted file mode 100644 index f72ed64fd0..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,8 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 1587bd33f2..0000000000 --- a/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_ESPTOOLPY_FLASHMODE_QIO=y -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_EXT_ADV=y -CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 3e24e0e3cf..0000000000 --- a/examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,8 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE=70 -CONFIG_BT_NIMBLE_EXT_ADV=y diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 deleted file mode 100644 index a6723d3f65..0000000000 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_ESPTOOLPY_FLASHMODE_QIO=y -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_USE_ESP_TIMER=n -CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 deleted file mode 100644 index a6723d3f65..0000000000 --- a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_ESPTOOLPY_FLASHMODE_QIO=y -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_USE_ESP_TIMER=n -CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/common_components/env_caps/esp32h4/Kconfig.env_caps b/examples/common_components/env_caps/esp32h4/Kconfig.env_caps deleted file mode 100644 index 193652111b..0000000000 --- a/examples/common_components/env_caps/esp32h4/Kconfig.env_caps +++ /dev/null @@ -1,15 +0,0 @@ -config ENV_GPIO_RANGE_MIN - int - default 0 - -config ENV_GPIO_RANGE_MAX - int - default 25 - -config ENV_GPIO_IN_RANGE_MAX - int - default ENV_GPIO_RANGE_MAX - -config ENV_GPIO_OUT_RANGE_MAX - int - default ENV_GPIO_RANGE_MAX diff --git a/tools/cmake/toolchain-esp32h4.cmake b/tools/cmake/toolchain-esp32h4.cmake deleted file mode 100644 index 2eb3a62d64..0000000000 --- a/tools/cmake/toolchain-esp32h4.cmake +++ /dev/null @@ -1,18 +0,0 @@ -include($ENV{IDF_PATH}/tools/cmake/utilities.cmake) - -set(CMAKE_SYSTEM_NAME Generic) - -set(CMAKE_C_COMPILER riscv32-esp-elf-gcc) -set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) -set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) -set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) - -remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) -set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) -set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) - -remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ - ${CMAKE_EXE_LINKER_FLAGS}" - UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) -set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) From bf2a7b2df61d1ea973bf621a2dc7ca591e7da6aa Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 13 Apr 2023 14:32:25 +0800 Subject: [PATCH 2/5] esp32h4: removed esp32h4 related codes --- Kconfig | 24 - components/app_update/esp_ota_ops.c | 2 - components/app_update/include/esp_ota_ops.h | 2 +- .../include/esp_app_format.h | 6 - .../private_include/bootloader_signature.h | 2 - .../bootloader_support/src/bootloader_efuse.c | 3 - .../src/bootloader_utility.c | 6 - .../bootloader_support/src/esp_image_format.c | 2 - .../secure_boot_signature_priv.h | 2 - components/bt/CMakeLists.txt | 13 - components/bt/controller/esp32h4/Kconfig.in | 392 ------ components/bt/controller/esp32h4/bt.c | 1169 ----------------- .../driver/test_apps/ledc/main/test_ledc.c | 2 +- .../spi/master/main/test_spi_bus_lock.c | 2 +- .../test_apps/spi/slave/main/test_spi_slave.c | 2 +- .../spi/slave_hd/main/test_spi_slave_hd.c | 2 +- components/efuse/efuse_table_gen.py | 2 +- components/esp_coex/CMakeLists.txt | 21 +- components/esp_phy/CMakeLists.txt | 11 +- components/esp_phy/src/phy_init_esp32hxx.c | 4 +- components/esp_pm/include/esp_pm.h | 1 - components/esp_pm/pm_impl.c | 2 - components/esp_pm/pm_trace.c | 2 +- .../esp_pm/test_apps/esp_pm/main/test_pm.c | 2 - components/esp_rom/CMakeLists.txt | 23 +- components/esp_rom/README.md | 2 - components/esp_system/Kconfig | 3 +- components/esp_system/crosscore_int.c | 8 +- components/esp_system/fpga_overrides.c | 4 - .../include/esp_private/crosscore_int.h | 4 +- components/esp_system/port/cpu_start.c | 5 - components/esp_system/system_time.c | 2 - .../main/test_reset_reason.c | 2 +- components/esp_timer/src/esp_timer.c | 2 - components/esp_timer/src/ets_timer_legacy.c | 2 - components/esp_timer/src/system_time.c | 2 - .../esp_timer/test_apps/main/test_ets_timer.c | 4 +- components/esp_wifi/Kconfig | 1 - components/esptool_py/Kconfig.projbuild | 1 - components/esptool_py/project_include.cmake | 8 - components/freertos/Kconfig | 2 +- components/heap/port/memory_layout_utils.c | 2 - .../mbedtls/port/esp_ds/esp_rsa_sign_alt.c | 2 - components/mbedtls/port/sha/dma/sha.c | 2 - components/newlib/newlib_init.c | 6 +- components/newlib/port/esp_time_impl.c | 3 - components/newlib/test/test_newlib.c | 4 +- components/newlib/test/test_time.c | 2 - .../openthread/port/esp_openthread_radio.c | 12 - components/spi_flash/cache_utils.c | 10 +- components/spi_flash/spi_flash_os_func_noos.c | 6 +- .../wpa_supplicant/src/utils/includes.h | 2 - docs/en/api-guides/openthread.rst | 8 +- docs/en/api-reference/peripherals/ledc.rst | 21 +- docs/zh_CN/api-reference/peripherals/ledc.rst | 21 +- examples/bluetooth/.build-test-rules.yml | 66 +- .../bluedroid/ble/ble_ancs/README.md | 6 +- .../ble/ble_compatibility_test/README.md | 6 +- .../bluedroid/ble/ble_eddystone/README.md | 6 +- .../ble/ble_hid_device_demo/README.md | 6 +- .../bluedroid/ble/ble_ibeacon/README.md | 4 +- .../bluedroid/ble/ble_spp_client/README.md | 4 +- .../bluedroid/ble/ble_spp_server/README.md | 6 +- .../throughput_client/README.md | 6 +- .../throughput_server/README.md | 6 +- .../bluedroid/ble/gatt_client/README.md | 6 +- .../ble/gatt_security_client/README.md | 6 +- .../ble/gatt_security_server/README.md | 6 +- .../bluedroid/ble/gatt_server/README.md | 6 +- .../ble/gatt_server_service_table/README.md | 6 +- .../ble/gattc_multi_connect/README.md | 6 +- .../ble_50/ble50_security_client/README.md | 6 +- .../ble_50/ble50_security_server/README.md | 6 +- .../bluedroid/ble_50/multi-adv/README.md | 6 +- .../bluedroid/ble_50/peroidic_adv/README.md | 6 +- .../bluedroid/ble_50/peroidic_sync/README.md | 6 +- .../bluedroid/coex/gattc_gatts_coex/README.md | 4 +- .../main/ble_mesh_console_main.c | 2 - .../ble_l2cap_coc/coc_blecent/README.md | 4 +- .../ble_l2cap_coc/coc_bleprph/README.md | 4 +- .../bluetooth/nimble/ble_multi_adv/README.md | 6 +- .../nimble/ble_periodic_adv/README.md | 10 +- .../nimble/ble_periodic_sync/README.md | 16 +- .../nimble/ble_phy/phy_cent/README.md | 4 +- .../nimble/ble_phy/phy_prph/README.md | 4 +- .../nimble/ble_spp/spp_client/README.md | 6 +- .../nimble/ble_spp/spp_server/README.md | 6 +- examples/bluetooth/nimble/blecent/README.md | 8 +- examples/bluetooth/nimble/blehr/README.md | 6 +- examples/bluetooth/nimble/bleprph/README.md | 6 +- .../ethernet_init/Kconfig.projbuild | 9 +- .../ethernet/enc28j60/main/Kconfig.projbuild | 5 - examples/openthread/README.md | 6 +- examples/openthread/ot_cli/sdkconfig.defaults | 2 +- .../i2s_es8311/main/example_config.h | 6 +- .../main/ext_flash_fatfs_example_main.c | 2 +- examples/storage/semihost_vfs/README.md | 2 +- .../system/deep_sleep/main/Kconfig.projbuild | 6 +- examples/system/esp_timer/sdkconfig.ci.rtc | 1 - examples/system/gcov/main/Kconfig.projbuild | 2 +- .../system/light_sleep/main/gpio_wakeup.c | 2 +- examples/zigbee/light_sample/README.md | 4 +- tools/ci/check_public_headers_exceptions.txt | 1 - tools/ci/python_packages/ttfw_idf/IDFDUT.py | 11 +- tools/ci/python_packages/ttfw_idf/__init__.py | 3 +- tools/cmake/dfu.cmake | 2 - tools/cmake/uf2.cmake | 2 - tools/gdb_panic_server.py | 2 - tools/idf_py_actions/constants.py | 2 +- tools/test_apps/system/eh_frame/README.md | 2 +- 110 files changed, 195 insertions(+), 1997 deletions(-) delete mode 100644 components/bt/controller/esp32h4/Kconfig.in delete mode 100644 components/bt/controller/esp32h4/bt.c diff --git a/Kconfig b/Kconfig index 7fdc422815..8cf51af062 100644 --- a/Kconfig +++ b/Kconfig @@ -66,28 +66,6 @@ mainmenu "Espressif IoT Development Framework Configuration" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV - config IDF_TARGET_ESP32H4 - bool - default "y" if IDF_TARGET="esp32h4" - select FREERTOS_UNICORE - select IDF_TARGET_ARCH_RISCV - - choice IDF_TARGET_ESP32H4_BETA_VERSION - prompt "ESP32-H4 beta version" - depends on IDF_TARGET_ESP32H4 - default IDF_TARGET_ESP32H4_BETA_VERSION_2 - help - Currently ESP32-H4 has several beta versions for internal use only. - Select the one that matches your chip model. - - config IDF_TARGET_ESP32H4_BETA_VERSION_1 - bool - prompt "ESP32-H4 beta1" - config IDF_TARGET_ESP32H4_BETA_VERSION_2 - bool - prompt "ESP32-H4 beta2" - endchoice - config IDF_TARGET_ESP32C2 bool default "y" if IDF_TARGET="esp32c2" @@ -116,10 +94,8 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x0002 if IDF_TARGET_ESP32S2 default 0x0005 if IDF_TARGET_ESP32C3 default 0x0009 if IDF_TARGET_ESP32S3 - default 0x000A if IDF_TARGET_ESP32H4_BETA_VERSION_1 default 0x000C if IDF_TARGET_ESP32C2 default 0x000D if IDF_TARGET_ESP32C6 - default 0x000E if IDF_TARGET_ESP32H4_BETA_VERSION_2 # ESP32-TODO: IDF-3475 default 0x0010 if IDF_TARGET_ESP32H2 default 0xFFFF diff --git a/components/app_update/esp_ota_ops.c b/components/app_update/esp_ota_ops.c index 80a07af5fa..6b80abab30 100644 --- a/components/app_update/esp_ota_ops.c +++ b/components/app_update/esp_ota_ops.c @@ -37,8 +37,6 @@ #include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/app_update/include/esp_ota_ops.h b/components/app_update/include/esp_ota_ops.h index 7809f2dc52..86f7ceca02 100644 --- a/components/app_update/include/esp_ota_ops.h +++ b/components/app_update/include/esp_ota_ops.h @@ -334,7 +334,7 @@ typedef enum { /** * @brief Revokes the old signature digest. To be called in the application after the rollback logic. * - * Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-H4 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1). + * Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1). * When key \#N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key \#N-1 & Key \#N. * After successfully booting the OTA app should call this function to revoke Key \#N-1. * diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 611269f73b..242d243cf1 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -17,12 +17,6 @@ typedef enum { ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */ ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */ ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */ - ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */ -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - ESP_CHIP_ID_ESP32H4 = 0x000E, /*!< chip ID: ESP32-H4 Beta2*/ // ESP32H4-TODO: IDF-3475 -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 - ESP_CHIP_ID_ESP32H4 = 0x000A, /*!< chip ID: ESP32-H4 Beta1 */ -#endif ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/bootloader_support/private_include/bootloader_signature.h b/components/bootloader_support/private_include/bootloader_signature.h index 9af5c7a51e..ac4c713f86 100644 --- a/components/bootloader_support/private_include/bootloader_signature.h +++ b/components/bootloader_support/private_include/bootloader_signature.h @@ -17,8 +17,6 @@ #include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c index 7c811768cb..605a20deb9 100644 --- a/components/bootloader_support/src/bootloader_efuse.c +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -27,9 +27,6 @@ int bootloader_clock_get_rated_freq_mhz(void) #elif CONFIG_IDF_TARGET_ESP32C3 return 160; -#elif CONFIG_IDF_TARGET_ESP32H4 - return 96; - #elif CONFIG_IDF_TARGET_ESP32C6 return 160; diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 29c7f32c9c..715ef610a3 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -28,12 +28,6 @@ #include "esp32c3/rom/uart.h" #include "esp32c3/rom/gpio.h" #include "esp32c3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/efuse.h" -#include "esp32h4/rom/crc.h" -#include "esp32h4/rom/uart.h" -#include "esp32h4/rom/gpio.h" -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/efuse.h" #include "esp32c2/rom/crc.h" diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index ef96101db0..af40d2ab23 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -29,8 +29,6 @@ #include "esp32s3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rom/secure_boot.h" diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h b/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h index 540b18aebf..8e8bd43a09 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h @@ -13,8 +13,6 @@ #include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 15a8052f9a..f04ef4191d 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -17,10 +17,6 @@ if(CONFIG_BT_ENABLED) list(APPEND srcs "controller/esp32c3/bt.c") list(APPEND include_dirs include/esp32c3/include) - elseif(CONFIG_IDF_TARGET_ESP32H4) - list(APPEND srcs "controller/esp32h4/bt.c") - list(APPEND include_dirs include/esp32h4/include) - elseif(CONFIG_IDF_TARGET_ESP32C2) list(APPEND srcs "controller/esp32c2/bt.c") list(APPEND include_dirs include/esp32c2/include) @@ -716,15 +712,6 @@ if(CONFIG_BT_ENABLED) target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3") target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app) - elseif(CONFIG_IDF_TARGET_ESP32H4) - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - # TODO: rename esp32h2 to esp32h4 [BT-2875] - add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta1/libble_app.a") - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - # TODO: rename esp32h2 to esp32h4 [BT-2875] - add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta2/libble_app.a") - endif() - target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app) elseif(CONFIG_IDF_TARGET_ESP32C2) add_prebuilt_library(libble_app "controller/lib_esp32c2/esp32c2-bt-lib/libble_app.a") target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app) diff --git a/components/bt/controller/esp32h4/Kconfig.in b/components/bt/controller/esp32h4/Kconfig.in deleted file mode 100644 index 9f5c226a0f..0000000000 --- a/components/bt/controller/esp32h4/Kconfig.in +++ /dev/null @@ -1,392 +0,0 @@ - -menu "HCI Config" - - choice BT_LE_HCI_INTERFACE - prompt "Select HCI interface" - default BT_LE_HCI_INTERFACE_USE_RAM - - config BT_LE_HCI_INTERFACE_USE_RAM - bool "ram" - help - Use RAM as HCI interface - config BT_LE_HCI_INTERFACE_USE_UART - bool "uart" - help - Use UART as HCI interface - endchoice - - config BT_LE_HCI_UART_PORT - int "HCI UART port" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 1 - help - Set the port number of HCI UART - - config BT_LE_HCI_UART_FLOWCTRL - bool "HCI uart Hardware Flow ctrl" - depends on BT_LE_HCI_INTERFACE_USE_UART - default n - - config BT_LE_HCI_UART_TX_PIN - int "HCI uart Tx gpio" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 19 - - config BT_LE_HCI_UART_RX_PIN - int "HCI uart Rx gpio" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 10 - - config BT_LE_HCI_UART_RTS_PIN - int "HCI uart RTS gpio" - depends on BT_LE_HCI_UART_FLOWCTRL - default 4 - - config BT_LE_HCI_UART_CTS_PIN - int "HCI uart CTS gpio" - depends on BT_LE_HCI_UART_FLOWCTRL - default 5 - - config BT_LE_HCI_UART_BAUD - int "HCI uart baudrate" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 921600 - help - HCI uart baud rate 115200 ~ 1000000 - - choice BT_LE_HCI_UART_PARITY - prompt "select uart parity" - depends on BT_LE_HCI_INTERFACE_USE_UART - default BT_LE_HCI_UART_UART_PARITY_DISABLE - - config BT_LE_HCI_UART_UART_PARITY_DISABLE - bool "PARITY_DISABLE" - help - UART_PARITY_DISABLE - config BT_LE_HCI_UART_UART_PARITY_EVEN - bool "PARITY_EVEN" - help - UART_PARITY_EVEN - config BT_LE_HCI_UART_UART_PARITY_ODD - bool "PARITY_ODD" - help - UART_PARITY_ODD - endchoice - - config BT_LE_HCI_UART_TASK_STACK_SIZE - int "HCI uart task stack size" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 1000 - help - Set the size of uart task stack -endmenu - -config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT - bool - default y - help - Enable NPL porting for controller. - - -menuconfig BT_LE_50_FEATURE_SUPPORT - bool "Enable BLE 5 feature" - depends on !BT_NIMBLE_ENABLED - default y - help - Enable BLE 5 feature - -config BT_LE_LL_CFG_FEAT_LE_2M_PHY - bool "Enable 2M Phy" - depends on BT_LE_50_FEATURE_SUPPORT - default y - help - Enable 2M-PHY - -config BT_LE_LL_CFG_FEAT_LE_CODED_PHY - bool "Enable coded Phy" - depends on BT_LE_50_FEATURE_SUPPORT - default y - help - Enable coded-PHY - -config BT_LE_EXT_ADV - bool "Enable extended advertising" - depends on BT_LE_50_FEATURE_SUPPORT - default y - help - Enable this option to do extended advertising. Extended advertising - will be supported from BLE 5.0 onwards. - -if BT_LE_EXT_ADV - config BT_LE_MAX_EXT_ADV_INSTANCES - int "Maximum number of extended advertising instances." - range 0 4 - default 1 - depends on BT_LE_EXT_ADV - help - Change this option to set maximum number of extended advertising - instances. Minimum there is always one instance of - advertising. Enter how many more advertising instances you - want. - Each extended advertising instance will take about 0.5k DRAM. - - config BT_LE_EXT_ADV_MAX_SIZE - int "Maximum length of the advertising data." - range 0 1650 - default 1650 - depends on BT_LE_EXT_ADV - help - Defines the length of the extended adv data. The value should not - exceed 1650. - - config BT_LE_ENABLE_PERIODIC_ADV - bool "Enable periodic advertisement." - default y - depends on BT_LE_EXT_ADV - help - Enable this option to start periodic advertisement. - - config BT_LE_PERIODIC_ADV_SYNC_TRANSFER - bool "Enable Transer Sync Events" - depends on BT_LE_ENABLE_PERIODIC_ADV - default y - help - This enables controller transfer periodic sync events to host - -endif - -config BT_LE_MAX_PERIODIC_SYNCS - int "Maximum number of periodic advertising syncs" - depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED - - range 0 8 - default 1 if BT_LE_ENABLE_PERIODIC_ADV - default 0 - help - Set this option to set the upper limit for number of periodic sync - connections. This should be less than maximum connections allowed by - controller. - -config BT_LE_MAX_PERIODIC_ADVERTISER_LIST - int "Maximum number of periodic advertiser list" - depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED - range 1 5 - default 5 - help - Set this option to set the upper limit for number of periodic advertiser list. - -menu "Memory Settings" - depends on !BT_NIMBLE_ENABLED - - config BT_LE_MSYS_1_BLOCK_COUNT - int "MSYS_1 Block Count" - default 12 - help - MSYS is a system level mbuf registry. For prepare write & prepare - responses MBUFs are allocated out of msys_1 pool. For NIMBLE_MESH - enabled cases, this block count is increased by 8 than user defined - count. - - config BT_LE_MSYS_1_BLOCK_SIZE - int "MSYS_1 Block Size" - default 256 - help - Dynamic memory size of block 1 - - config BT_LE_MSYS_2_BLOCK_COUNT - int "MSYS_2 Block Count" - default 24 - help - Dynamic memory count - - config BT_LE_MSYS_2_BLOCK_SIZE - int "MSYS_2 Block Size" - default 320 - help - Dynamic memory size of block 2 - - config BT_LE_ACL_BUF_COUNT - int "ACL Buffer count" - default 10 - help - The number of ACL data buffers. - - config BT_LE_ACL_BUF_SIZE - int "ACL Buffer size" - default 517 - help - This is the maximum size of the data portion of HCI ACL data packets. - It does not include the HCI data header (of 4 bytes) - - config BT_LE_HCI_EVT_BUF_SIZE - int "HCI Event Buffer size" - default 257 if BT_LE_EXT_ADV - default 70 - help - This is the size of each HCI event buffer in bytes. In case of - extended advertising, packets can be fragmented. 257 bytes is the - maximum size of a packet. - - config BT_LE_HCI_EVT_HI_BUF_COUNT - int "High Priority HCI Event Buffer count" - default 30 - help - This is the high priority HCI events' buffer size. High-priority - event buffers are for everything except advertising reports. If there - are no free high-priority event buffers then host will try to allocate a - low-priority buffer instead - - config BT_LE_HCI_EVT_LO_BUF_COUNT - int "Low Priority HCI Event Buffer count" - default 8 - help - This is the low priority HCI events' buffer size. Low-priority event - buffers are only used for advertising reports. If there are no free - low-priority event buffers, then an incoming advertising report will - get dropped -endmenu - -config BT_LE_CONTROLLER_TASK_STACK_SIZE - int "Controller task stack size" - default 5120 if BLE_MESH - default 4096 - help - This configures stack size of NimBLE controller task - -config BT_LE_LL_RESOLV_LIST_SIZE - int "BLE LL Resolving list size" - range 1 5 - default 4 - help - Configure the size of resolving list used in link layer. - -menuconfig BT_LE_SECURITY_ENABLE - bool "Enable BLE SM feature" - depends on !BT_NIMBLE_ENABLED - default y - help - Enable BLE sm feature - -config BT_LE_SM_LEGACY - bool "Security manager legacy pairing" - depends on BT_LE_SECURITY_ENABLE - default y - help - Enable security manager legacy pairing - -config BT_LE_SM_SC - bool "Security manager secure connections (4.2)" - depends on BT_LE_SECURITY_ENABLE - default y - help - Enable security manager secure connections - -config BT_LE_SM_SC_DEBUG_KEYS - bool "Use predefined public-private key pair" - default n - depends on BT_LE_SECURITY_ENABLE && BT_LE_SM_SC - help - If this option is enabled, SM uses predefined DH key pair as described - in Core Specification, Vol. 3, Part H, 2.3.5.6.1. This allows to - decrypt air traffic easily and thus should only be used for debugging. - -config BT_LE_LL_CFG_FEAT_LE_ENCRYPTION - bool "Enable LE encryption" - depends on BT_LE_SECURITY_ENABLE - default y - help - Enable encryption connection - -config BT_LE_CRYPTO_STACK_MBEDTLS - bool "Override TinyCrypt with mbedTLS for crypto computations" - default y - depends on !BT_NIMBLE_ENABLED - select MBEDTLS_ECP_RESTARTABLE - select MBEDTLS_CMAC_C - help - Enable this option to choose mbedTLS instead of TinyCrypt for crypto - computations. - -config BT_LE_WHITELIST_SIZE - int "BLE white list size" - range 1 15 - default 12 - depends on !BT_NIMBLE_ENABLED - - help - BLE list size - -config BT_LE_LL_DUP_SCAN_LIST_COUNT - int "BLE duplicate scan list count" - range 1 100 - default 20 - help - config the max count of duplicate scan list - -config BT_LE_LL_SCA - int "BLE Sleep clock accuracy" - range 0 500 - default 60 - help - Sleep clock accuracy of our device (in ppm) - -config BT_LE_MAX_CONNECTIONS - int "Maximum number of concurrent connections" - depends on !BT_NIMBLE_ENABLED - range 1 9 - default 3 - help - Defines maximum number of concurrent BLE connections. For ESP32, user - is expected to configure BTDM_CTRL_BLE_MAX_CONN from controller menu - along with this option. Similarly for ESP32-C3 or ESP32-S3, user is expected to - configure BT_CTRL_BLE_MAX_ACT from controller menu. - Each connection will take about 1k DRAM. - -choice BT_LE_COEX_PHY_CODED_TX_RX_TLIM - prompt "Coexistence: limit on MAX Tx/Rx time for coded-PHY connection" - default BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS - depends on !BT_NIMBLE_ENABLED - help - When using PHY-Coded in BLE connection, limitation on max tx/rx time can be applied to - better avoid dramatic performance deterioration of Wi-Fi. - - config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN - bool "Force Enable" - help - Always enable the limitation on max tx/rx time for Coded-PHY connection - - config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS - bool "Force Disable" - help - Disable the limitation on max tx/rx time for Coded-PHY connection -endchoice - -config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF - int - depends on !BT_NIMBLE_ENABLED - default 1 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN - default 0 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS - -config BT_LE_SLEEP_ENABLE - bool "Enable BLE sleep" - default n - help - Enable BLE sleep - -choice BT_LE_WAKEUP_SOURCE - prompt "BLE light sleep wakeup source" - depends on BT_LE_SLEEP_ENABLE - default BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - config BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - bool "Use ESP timer to wakeup CPU" - help - Use esp timer to wakeup CPU -endchoice - -config BT_LE_USE_ESP_TIMER - bool "Use Esp Timer for callout" - depends on !BT_NIMBLE_ENABLED - default y - help - Set this option to use Esp Timer which has higher priority timer - instead of FreeRTOS timer diff --git a/components/bt/controller/esp32h4/bt.c b/components/bt/controller/esp32h4/bt.c deleted file mode 100644 index cfd912e2e5..0000000000 --- a/components/bt/controller/esp32h4/bt.c +++ /dev/null @@ -1,1169 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include "esp_random.h" -#include - -#include "sdkconfig.h" - -#include "nimble/nimble_port.h" -#include "nimble/nimble_port_freertos.h" - -#ifdef ESP_PLATFORM -#include "esp_log.h" -#endif - -#if CONFIG_SW_COEXIST_ENABLE -#include "esp_coexist_internal.h" -#endif - -#include "nimble/nimble_npl_os.h" -#include "nimble/ble_hci_trans.h" -#include "os/endian.h" - -#include "esp_bt.h" -#include "esp_intr_alloc.h" -#include "esp_sleep.h" -#include "esp_pm.h" -#include "esp_phy_init.h" -#include "soc/system_reg.h" -#include "soc/clkrst_reg.h" - -#include "hci_uart.h" -#include "bt_osi_mem.h" - -#ifdef CONFIG_BT_BLUEDROID_ENABLED -#include "hci/hci_hal.h" -#endif - -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" - -#include "esp_private/periph_ctrl.h" -#include "esp_sleep.h" - -#include "soc/syscon_reg.h" -#include "soc/dport_access.h" - -/* Macro definition - ************************************************************************ - */ - -#define NIMBLE_PORT_LOG_TAG "BLE_INIT" -#define OSI_COEX_VERSION 0x00010006 -#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD - -#define EXT_FUNC_VERSION 0x20221122 -#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 - -#define BT_ASSERT_PRINT ets_printf - -#ifdef CONFIG_BT_BLUEDROID_ENABLED -/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */ -#define ACL_DATA_MBUF_LEADINGSPCAE 4 -#endif - -/* Types definition - ************************************************************************ - */ - -struct osi_coex_funcs_t { - uint32_t _magic; - uint32_t _version; - void (* _coex_wifi_sleep_set)(bool sleep); - int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high); - void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); - void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); -}; - -struct ext_funcs_t { - uint32_t ext_version; - int (*_esp_intr_alloc)(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle); - int (*_esp_intr_free)(void **ret_handle); - void *(* _malloc)(size_t size); - void (*_free)(void *p); - void (*_hal_uart_start_tx)(int); - int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *); - int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t); - int (*_hal_uart_close)(int); - void (*_hal_uart_blocking_tx)(int, uint8_t); - int (*_hal_uart_init)(int, void *); - int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id); - void (* _task_delete)(void *task_handle); - void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2); - uint32_t (* _os_random)(void); - int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv); - int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y, const uint8_t *local_priv_key, uint8_t *dhkey); - void (* _esp_reset_rpa_moudle)(void); - uint32_t magic; -}; - - -/* External functions or variables - ************************************************************************ - */ - -extern int ble_plf_set_log_level(int level); -extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs); -extern int ble_controller_init(esp_bt_controller_config_t *cfg); -extern int ble_controller_deinit(void); -extern int ble_controller_enable(uint8_t mode); -extern int ble_controller_disable(void); -extern int esp_register_ext_funcs (struct ext_funcs_t *); -extern void esp_unregister_ext_funcs (void); -extern int esp_ble_ll_set_public_addr(const uint8_t *addr); -extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func); -extern void esp_unregister_npl_funcs (void); -extern void npl_freertos_mempool_deinit(void); -extern int os_msys_buf_alloc(void); -extern uint32_t r_os_cputime_get32(void); -extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks); -extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled); -extern void r_ble_rtc_wake_up_state_clr(void); -extern int os_msys_init(void); -extern void os_msys_buf_free(void); -extern void bt_bb_set_le_tx_on_delay(uint32_t delay_us); -extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, - const uint8_t *peer_pub_key_y, - const uint8_t *our_priv_key, uint8_t *out_dhkey); -extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv); -extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); -extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); -extern uint32_t _bt_bss_start; -extern uint32_t _bt_bss_end; -extern uint32_t _nimble_bss_start; -extern uint32_t _nimble_bss_end; -extern uint32_t _nimble_data_start; -extern uint32_t _nimble_data_end; -extern uint32_t _bt_data_start; -extern uint32_t _bt_data_end; - -/* Local Function Declaration - ********************************************************************* - */ -static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status); -static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status); -static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id); -static void task_delete_wrapper(void *task_handle); -#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART -static void hci_uart_start_tx_wrapper(int uart_no); -static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func, - hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg); -static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits, - uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl); -static int hci_uart_close_wrapper(int uart_no); -static void hci_uart_blocking_tx_wrapper(int port, uint8_t data); -static int hci_uart_init_wrapper(int uart_no, void *cfg); -#endif -static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in); -static int esp_intr_free_wrapper(void **ret_handle); -static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2); -static uint32_t osi_random_wrapper(void); - -static void esp_reset_rpa_moudle(void); - - -/* Local variable definition - *************************************************************************** - */ - -/* Static variable declare */ -static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; - -/* This variable tells if BLE is running */ -static bool s_ble_active = false; -#ifdef CONFIG_PM_ENABLE -static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL; - -#define BTDM_MIN_TIMER_UNCERTAINTY_US (200) -#endif /* #ifdef CONFIG_PM_ENABLE */ - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER -#define BLE_RTC_DELAY_US (1100) -#endif - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -#define BLE_RTC_DELAY_US (0) -static void ble_sleep_timer_callback(void *arg); -static DRAM_ATTR esp_timer_handle_t s_ble_sleep_timer = NULL; -#endif - - -static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = { - ._magic = OSI_COEX_MAGIC_VALUE, - ._version = OSI_COEX_VERSION, - ._coex_wifi_sleep_set = NULL, - ._coex_core_ble_conn_dyn_prio_get = NULL, - ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, - ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, -}; - -struct ext_funcs_t ext_funcs_ro = { - .ext_version = EXT_FUNC_VERSION, - ._esp_intr_alloc = esp_intr_alloc_wrapper, - ._esp_intr_free = esp_intr_free_wrapper, - ._malloc = bt_osi_mem_malloc_internal, - ._free = bt_osi_mem_free, -#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART - ._hal_uart_start_tx = hci_uart_start_tx_wrapper, - ._hal_uart_init_cbs = hci_uart_init_cbs_wrapper, - ._hal_uart_config = hci_uart_config_wrapper, - ._hal_uart_close = hci_uart_close_wrapper, - ._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper, - ._hal_uart_init = hci_uart_init_wrapper, -#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART - ._task_create = task_create_wrapper, - ._task_delete = task_delete_wrapper, - ._osi_assert = osi_assert_wrapper, - ._os_random = osi_random_wrapper, - ._ecc_gen_key_pair = ble_sm_alg_gen_key_pair, - ._ecc_gen_dh_key = ble_sm_alg_gen_dhkey, - ._esp_reset_rpa_moudle = esp_reset_rpa_moudle, - .magic = EXT_FUNC_MAGIC_VALUE, -}; - -static void IRAM_ATTR esp_reset_rpa_moudle(void) -{ - DPORT_SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_BAH_RST); - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_BAH_RST); - -} - -static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2) -{ - BT_ASSERT_PRINT("BLE assert: line %d in function %s, param: 0x%x, 0x%x", ln, fn, param1, param2); - assert(0); -} - -static uint32_t IRAM_ATTR osi_random_wrapper(void) -{ - return esp_random(); -} - -static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) -{ -#if CONFIG_SW_COEXIST_ENABLE - coex_schm_status_bit_set(type, status); -#endif -} - -static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status) -{ -#if CONFIG_SW_COEXIST_ENABLE - coex_schm_status_bit_clear(type, status); -#endif -} -#ifdef CONFIG_BT_BLUEDROID_ENABLED - -bool esp_vhci_host_check_send_available(void) -{ - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - return false; - } - return true; -} - -/** - * Allocates an mbuf for use by the nimble host. - */ -static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space) -{ - struct os_mbuf *om; - int rc; - - om = os_msys_get_pkthdr(0, 0); - if (om == NULL) { - return NULL; - } - - if (om->om_omp->omp_databuf_len < leading_space) { - rc = os_mbuf_free_chain(om); - assert(rc == 0); - return NULL; - } - - om->om_data += leading_space; - - return om; -} - -/** - * Allocates an mbuf suitable for an HCI ACL data packet. - * - * @return An empty mbuf on success; null on memory - * exhaustion. - */ -struct os_mbuf *ble_hs_mbuf_acl_pkt(void) -{ - return ble_hs_mbuf_gen_pkt(4 + 1); -} - -void esp_vhci_host_send_packet(uint8_t *data, uint16_t len) -{ - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - return; - } - - if (*(data) == DATA_TYPE_COMMAND) { - struct ble_hci_cmd *cmd = NULL; - cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD); - memcpy((uint8_t *)cmd, data + 1, len - 1); - ble_hci_trans_hs_cmd_tx((uint8_t *)cmd); - } - - if (*(data) == DATA_TYPE_ACL) { - struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE); - assert(om); - assert(os_mbuf_append(om, &data[1], len - 1) == 0); - ble_hci_trans_hs_acl_tx(om); - } - -} - -esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback) -{ - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - return ESP_FAIL; - } - - ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL); - - return ESP_OK; -} - -#endif -static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id) -{ - return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle, (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY)); -} - -static void task_delete_wrapper(void *task_handle) -{ - vTaskDelete(task_handle); -} - -#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART -static void hci_uart_start_tx_wrapper(int uart_no) -{ - hci_uart_start_tx(uart_no); -} - -static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func, - hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg) -{ - int rc = -1; - rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg); - return rc; -} - - -static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits, uint8_t stop_bits, - uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl) -{ - int rc = -1; - rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl); - return rc; -} - -static int hci_uart_close_wrapper(int uart_no) -{ - int rc = -1; - rc = hci_uart_close(uart_no); - return rc; -} - -static void hci_uart_blocking_tx_wrapper(int port, uint8_t data) -{ - //This function is nowhere to use. -} - -static int hci_uart_init_wrapper(int uart_no, void *cfg) -{ - //This function is nowhere to use. - return 0; -} - -#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART - -static int ble_hci_unregistered_hook(void*, void*) -{ - ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__); - return 0; -} - -static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in) -{ - int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, arg, (intr_handle_t *)ret_handle_in); - return rc; -} - -static int esp_intr_free_wrapper(void **ret_handle) -{ - int rc = 0; - rc = esp_intr_free((intr_handle_t) * ret_handle); - *ret_handle = NULL; - return rc; -} - -IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) -{ - if (!s_ble_active) { - return; - } -#ifdef CONFIG_PM_ENABLE -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - uint32_t delta_tick; - uint32_t us_to_sleep; - uint32_t sleep_tick; - uint32_t tick_invalid = *(uint32_t*)(arg); - assert(arg != NULL); - if (!tick_invalid) { - sleep_tick = r_os_cputime_get32(); - // start a timer to wake up and acquire the pm_lock before modem_sleep awakes - delta_tick = enable_tick - sleep_tick; - if (delta_tick & 0x80000000) { - return; - } - us_to_sleep = r_os_cputime_ticks_to_usecs(delta_tick); - if (us_to_sleep <= BTDM_MIN_TIMER_UNCERTAINTY_US) { - return; - } - esp_err_t err = esp_timer_start_once(s_ble_sleep_timer, us_to_sleep - BTDM_MIN_TIMER_UNCERTAINTY_US); - if (err != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ESP timer start failed\n"); - return; - } - } -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - r_ble_rtc_wake_up_state_clr(); -#endif - esp_pm_lock_release(s_pm_lock); -#endif // CONFIG_PM_ENABLE - esp_phy_disable(); - s_ble_active = false; -} - -IRAM_ATTR void controller_wakeup_cb(void *arg) -{ - if (s_ble_active) { - return; - } - esp_phy_enable(); - // need to check if need to call pm lock here -#ifdef CONFIG_PM_ENABLE - esp_pm_lock_acquire(s_pm_lock); -#endif //CONFIG_PM_ENABLE - s_ble_active = true; -} - -#ifdef CONFIG_PM_ENABLE -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -static void ble_sleep_timer_callback(void * arg) -{ - -} - -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -#endif // CONFIG_PM_ENABLE - -esp_err_t controller_sleep_init(void) -{ - esp_err_t rc = 0; -#ifdef CONFIG_BT_LE_SLEEP_ENABLE - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled\n"); - r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US); - -#ifdef CONFIG_PM_ENABLE - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); -#endif // CONFIG_PM_ENABLE - -#endif // CONFIG_BT_LE_SLEEP_ENABLE - - // enable light sleep -#ifdef CONFIG_PM_ENABLE - rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock); - if (rc != ESP_OK) { - goto error; - } - esp_pm_lock_acquire(s_pm_lock); -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - esp_timer_create_args_t create_args = { - .callback = ble_sleep_timer_callback, - .arg = NULL, - .name = "btSlp" - }; - rc = esp_timer_create(&create_args, &s_ble_sleep_timer); - if (rc != ESP_OK) { - goto error; - } - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is ESP timer"); -#endif //CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - esp_sleep_enable_bt_wakeup(); - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer"); -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - - return rc; - -error: - /*lock should release first and then delete*/ - if (s_pm_lock != NULL) { - esp_pm_lock_release(s_pm_lock); - esp_pm_lock_delete(s_pm_lock); - s_pm_lock = NULL; - } -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - if (s_ble_sleep_timer != NULL) { - esp_timer_stop(s_ble_sleep_timer); - esp_timer_delete(s_ble_sleep_timer); - s_ble_sleep_timer = NULL; - } -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - esp_sleep_disable_bt_wakeup(); -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - -#endif //CONFIG_PM_ENABLE - return rc; -} - -void controller_sleep_deinit(void) -{ -#ifdef CONFIG_PM_ENABLE -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - r_ble_rtc_wake_up_state_clr(); - esp_sleep_disable_bt_wakeup(); -#endif //CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO); - - /*lock should release first and then delete*/ - if (s_ble_active) { - esp_pm_lock_release(s_pm_lock); - } - - esp_pm_lock_delete(s_pm_lock); - s_pm_lock = NULL; -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - if (s_ble_sleep_timer != NULL) { - esp_timer_stop(s_ble_sleep_timer); - esp_timer_delete(s_ble_sleep_timer); - s_ble_sleep_timer = NULL; - } -#endif //CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -#endif //CONFIG_PM_ENABLE -} - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -void periph_module_etm_active(void) -{ - /*This part for esp32h4 beta2*/ - REG_SET_BIT(SYSTEM_MODCLK_CONF_REG, SYSTEM_ETM_CLK_SEL | SYSTEM_ETM_CLK_ACTIVE ); //Active ETM clock -} -#endif - -esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) -{ - esp_err_t ret = ESP_OK; - ble_npl_count_info_t npl_info; - memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); - - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_ERR_INVALID_STATE; - } - - if (!cfg) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "cfg is NULL"); - return ESP_ERR_INVALID_ARG; - } - - ret = esp_register_ext_funcs(&ext_funcs_ro); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "register extend functions failed"); - return ret; - } - - /* Initialize the function pointers for OS porting */ - npl_freertos_funcs_init(); - struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get(); - if (!p_npl_funcs) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions get failed"); - return ESP_ERR_INVALID_ARG; - } - - ret = esp_register_npl_funcs(p_npl_funcs); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions register failed"); - goto free_mem; - } - - ble_get_npl_element_info(cfg, &npl_info); - npl_freertos_set_controller_npl_info(&npl_info); - if (npl_freertos_mempool_init() != 0) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed"); - ret = ESP_ERR_INVALID_ARG; - goto free_mem; - } - - /* Initialize the global memory pool */ - ret = os_msys_buf_alloc(); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "os msys alloc failed"); - goto free_mem; - } - - os_msys_init(); -#if CONFIG_BT_NIMBLE_ENABLED - // ble_npl_eventq_init() need to use npl function in rom and must be called after esp_bt_controller_init() - /* Initialize default event queue */ - ble_npl_eventq_init(nimble_port_get_dflt_eventq()); -#endif - - periph_module_enable(PERIPH_BT_MODULE); -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - // only use for esp32h4 beta2 - periph_module_etm_active(); -#endif - - // init phy - esp_phy_enable(); - esp_btbb_enable(); - s_ble_active = true; - // set bb delay - bt_bb_set_le_tx_on_delay(50); - - if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed"); - ret = ESP_ERR_INVALID_ARG; - goto free_controller; - } - -#if CONFIG_SW_COEXIST_ENABLE - coex_init(); -#endif - ret = ble_controller_init(cfg); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); - goto free_controller; - } - - ret = controller_sleep_init(); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret); - goto free_controller; - } - - uint8_t mac[6]; - ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT)); - - swap_in_place(mac, 6); - - esp_ble_ll_set_public_addr(mac); - - ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - - ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL, - (ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL); - return ESP_OK; -free_controller: - controller_sleep_deinit(); - ble_controller_deinit(); - esp_btbb_disable(); - esp_phy_disable(); -#if CONFIG_BT_NIMBLE_ENABLED - ble_npl_eventq_deinit(nimble_port_get_dflt_eventq()); -#endif // CONFIG_BT_NIMBLE_ENABLED -free_mem: - os_msys_buf_free(); - npl_freertos_mempool_deinit(); - esp_unregister_npl_funcs(); - npl_freertos_funcs_deinit(); - esp_unregister_ext_funcs(); - return ret; -} - -esp_err_t esp_bt_controller_deinit(void) -{ - if ((ble_controller_status < ESP_BT_CONTROLLER_STATUS_INITED) || (ble_controller_status >= ESP_BT_CONTROLLER_STATUS_ENABLED)) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_FAIL; - } - - controller_sleep_deinit(); - - esp_btbb_disable(); - - if (s_ble_active) { - esp_phy_disable(); - s_ble_active = false; - } - - ble_controller_deinit(); - -#if CONFIG_BT_NIMBLE_ENABLED - /* De-initialize default event queue */ - ble_npl_eventq_deinit(nimble_port_get_dflt_eventq()); -#endif - os_msys_buf_free(); - - esp_unregister_npl_funcs(); - - esp_unregister_ext_funcs(); - - /* De-initialize npl functions */ - npl_freertos_funcs_deinit(); - - npl_freertos_mempool_deinit(); - - ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; - - return ESP_OK; -} - -esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) -{ - if (mode != ESP_BT_MODE_BLE) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller mode"); - return ESP_FAIL; - } - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_FAIL; - } -#if CONFIG_SW_COEXIST_ENABLE - coex_enable(); -#endif - if (ble_controller_enable(mode) != 0) { - return ESP_FAIL; - } - ble_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; - return ESP_OK; -} - -esp_err_t esp_bt_controller_disable(void) -{ - if (ble_controller_status < ESP_BT_CONTROLLER_STATUS_ENABLED) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_FAIL; - } - if (ble_controller_disable() != 0) { - return ESP_FAIL; - } - ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - return ESP_OK; -} - -esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode) -{ - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__); - return ESP_OK; -} - -static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end) -{ - /* TODO */ - int ret = ESP_ERR_INVALID_SIZE; - /* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is - * is too small to fit a heap. This cannot be termed as a fatal error and hence - * we replace it by ESP_OK - */ - if (ret == ESP_ERR_INVALID_SIZE) { - return ESP_OK; - } - return ret; -} - -esp_err_t esp_bt_mem_release(esp_bt_mode_t mode) -{ - intptr_t mem_start, mem_end; - - if (mode & ESP_BT_MODE_BLE) { - mem_start = (intptr_t)&_bt_bss_start; - mem_end = (intptr_t)&_bt_bss_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - - mem_start = (intptr_t)&_bt_data_start; - mem_end = (intptr_t)&_bt_data_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - - mem_start = (intptr_t)&_nimble_bss_start; - mem_end = (intptr_t)&_nimble_bss_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - - mem_start = (intptr_t)&_nimble_data_start; - mem_end = (intptr_t)&_nimble_data_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - } - - return ESP_OK; -} - - -esp_bt_controller_status_t esp_bt_controller_get_status(void) -{ - return ble_controller_status; -} - -/* extra functions */ -esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level) -{ - esp_err_t stat = ESP_FAIL; - - switch (power_type) { - case ESP_BLE_PWR_TYPE_DEFAULT: - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { - stat = ESP_OK; - } - break; - case ESP_BLE_PWR_TYPE_CONN_HDL0: - case ESP_BLE_PWR_TYPE_CONN_HDL1: - case ESP_BLE_PWR_TYPE_CONN_HDL2: - case ESP_BLE_PWR_TYPE_CONN_HDL3: - case ESP_BLE_PWR_TYPE_CONN_HDL4: - case ESP_BLE_PWR_TYPE_CONN_HDL5: - case ESP_BLE_PWR_TYPE_CONN_HDL6: - case ESP_BLE_PWR_TYPE_CONN_HDL7: - case ESP_BLE_PWR_TYPE_CONN_HDL8: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { - stat = ESP_OK; - } - break; - default: - stat = ESP_ERR_NOT_SUPPORTED; - break; - } - - return stat; -} - -esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle, esp_power_level_t power_level) -{ - esp_err_t stat = ESP_FAIL; - switch (power_type) { - case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: - case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: - case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { - stat = ESP_OK; - } - break; - case ESP_BLE_ENHANCED_PWR_TYPE_ADV: - case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - if (ble_txpwr_set(power_type, handle, power_level) == 0) { - stat = ESP_OK; - } - break; - default: - stat = ESP_ERR_NOT_SUPPORTED; - break; - } - - return stat; -} - -esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) -{ - int tx_level = 0; - - switch (power_type) { - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: - case ESP_BLE_PWR_TYPE_DEFAULT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); - break; - case ESP_BLE_PWR_TYPE_CONN_HDL0: - case ESP_BLE_PWR_TYPE_CONN_HDL1: - case ESP_BLE_PWR_TYPE_CONN_HDL2: - case ESP_BLE_PWR_TYPE_CONN_HDL3: - case ESP_BLE_PWR_TYPE_CONN_HDL4: - case ESP_BLE_PWR_TYPE_CONN_HDL5: - case ESP_BLE_PWR_TYPE_CONN_HDL6: - case ESP_BLE_PWR_TYPE_CONN_HDL7: - case ESP_BLE_PWR_TYPE_CONN_HDL8: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); - break; - default: - return ESP_PWR_LVL_INVALID; - } - - if (tx_level < 0) { - return ESP_PWR_LVL_INVALID; - } - - return (esp_power_level_t)tx_level; -} - -esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle) -{ - int tx_level = 0; - - switch (power_type) { - case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: - case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: - case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); - break; - case ESP_BLE_ENHANCED_PWR_TYPE_ADV: - case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - tx_level = ble_txpwr_get(power_type, handle); - break; - default: - return ESP_PWR_LVL_INVALID; - } - - if (tx_level < 0) { - return ESP_PWR_LVL_INVALID; - } - - return (esp_power_level_t)tx_level; -} - - -#if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED == true) - -#define BLE_SM_KEY_ERR 0x17 - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS -#include "mbedtls/aes.h" - -#if CONFIG_BT_LE_SM_SC -#include "mbedtls/cipher.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ctr_drbg.h" -#include "mbedtls/cmac.h" -#include "mbedtls/ecdh.h" -#include "mbedtls/ecp.h" -#endif - -#else -#include "tinycrypt/aes.h" -#include "tinycrypt/constants.h" -#include "tinycrypt/utils.h" - -#if CONFIG_BT_LE_SM_SC -#include "tinycrypt/cmac_mode.h" -#include "tinycrypt/ecc_dh.h" -#endif - -#endif - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS -#if CONFIG_BT_LE_SM_SC -static mbedtls_ecp_keypair keypair; -#endif -#endif - -int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, - const uint8_t *our_priv_key, uint8_t *out_dhkey) -{ - uint8_t dh[32]; - uint8_t pk[64]; - uint8_t priv[32]; - int rc = BLE_SM_KEY_ERR; - - swap_buf(pk, peer_pub_key_x, 32); - swap_buf(&pk[32], peer_pub_key_y, 32); - swap_buf(priv, our_priv_key, 32); - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS - struct mbedtls_ecp_point pt = {0}, Q = {0}; - mbedtls_mpi z = {0}, d = {0}; - mbedtls_ctr_drbg_context ctr_drbg = {0}; - mbedtls_entropy_context entropy = {0}; - - uint8_t pub[65] = {0}; - /* Hardcoded first byte of pub key for MBEDTLS_ECP_PF_UNCOMPRESSED */ - pub[0] = 0x04; - memcpy(&pub[1], pk, 64); - - /* Initialize the required structures here */ - mbedtls_ecp_point_init(&pt); - mbedtls_ecp_point_init(&Q); - mbedtls_ctr_drbg_init(&ctr_drbg); - mbedtls_entropy_init(&entropy); - mbedtls_mpi_init(&d); - mbedtls_mpi_init(&z); - - /* Below 3 steps are to validate public key on curve secp256r1 */ - if (mbedtls_ecp_group_load(&keypair.MBEDTLS_PRIVATE(grp), MBEDTLS_ECP_DP_SECP256R1) != 0) { - goto exit; - } - - if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &pt, pub, 65) != 0) { - goto exit; - } - - if (mbedtls_ecp_check_pubkey(&keypair.MBEDTLS_PRIVATE(grp), &pt) != 0) { - goto exit; - } - - /* Set PRNG */ - if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, - NULL, 0)) != 0) { - goto exit; - } - - /* Prepare point Q from pub key */ - if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &Q, pub, 65) != 0) { - goto exit; - } - - if (mbedtls_mpi_read_binary(&d, priv, 32) != 0) { - goto exit; - } - - rc = mbedtls_ecdh_compute_shared(&keypair.MBEDTLS_PRIVATE(grp), &z, &Q, &d, - mbedtls_ctr_drbg_random, &ctr_drbg); - if (rc != 0) { - goto exit; - } - - rc = mbedtls_mpi_write_binary(&z, dh, 32); - if (rc != 0) { - goto exit; - } - -exit: - mbedtls_ecp_point_free(&pt); - mbedtls_mpi_free(&z); - mbedtls_mpi_free(&d); - mbedtls_ecp_point_free(&Q); - mbedtls_entropy_free(&entropy); - mbedtls_ctr_drbg_free(&ctr_drbg); - if (rc != 0) { - return BLE_SM_KEY_ERR; - } - -#else - if (uECC_valid_public_key(pk, &curve_secp256r1) < 0) { - return BLE_SM_KEY_ERR; - } - - rc = uECC_shared_secret(pk, priv, dh, &curve_secp256r1); - if (rc == TC_CRYPTO_FAIL) { - return BLE_SM_KEY_ERR; - } -#endif - - swap_buf(out_dhkey, dh, 32); - return 0; -} - -/* based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */ -static const uint8_t ble_sm_alg_dbg_priv_key[32] = { - 0x3f, 0x49, 0xf6, 0xd4, 0xa3, 0xc5, 0x5f, 0x38, 0x74, 0xc9, 0xb3, 0xe3, - 0xd2, 0x10, 0x3f, 0x50, 0x4a, 0xff, 0x60, 0x7b, 0xeb, 0x40, 0xb7, 0x99, - 0x58, 0x99, 0xb8, 0xa6, 0xcd, 0x3c, 0x1a, 0xbd -}; - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS -static int mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key) -{ - int rc = BLE_SM_KEY_ERR; - mbedtls_entropy_context entropy = {0}; - mbedtls_ctr_drbg_context ctr_drbg = {0}; - - mbedtls_entropy_init(&entropy); - mbedtls_ctr_drbg_init(&ctr_drbg); - mbedtls_ecp_keypair_init(&keypair); - - if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, - NULL, 0)) != 0) { - goto exit; - } - - if ((rc = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, &keypair, - mbedtls_ctr_drbg_random, &ctr_drbg)) != 0) { - goto exit; - } - - if ((rc = mbedtls_mpi_write_binary(&keypair.MBEDTLS_PRIVATE(d), private_key, 32)) != 0) { - goto exit; - } - - size_t olen = 0; - uint8_t pub[65] = {0}; - - if ((rc = mbedtls_ecp_point_write_binary(&keypair.MBEDTLS_PRIVATE(grp), &keypair.MBEDTLS_PRIVATE(Q), MBEDTLS_ECP_PF_UNCOMPRESSED, - &olen, pub, 65)) != 0) { - goto exit; - } - - memcpy(public_key, &pub[1], 64); - -exit: - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); - if (rc != 0) { - mbedtls_ecp_keypair_free(&keypair); - return BLE_SM_KEY_ERR; - } - - return 0; -} -#endif - -/** - * pub: 64 bytes - * priv: 32 bytes - */ -int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv) -{ -#if CONFIG_BT_LE_SM_SC_DEBUG_KEYS - swap_buf(pub, ble_sm_alg_dbg_pub_key, 32); - swap_buf(&pub[32], &ble_sm_alg_dbg_pub_key[32], 32); - swap_buf(priv, ble_sm_alg_dbg_priv_key, 32); -#else - uint8_t pk[64]; - - do { - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS - if (mbedtls_gen_keypair(pk, priv) != 0) { - return BLE_SM_KEY_ERR; - } -#else - if (uECC_make_key(pk, priv, &curve_secp256r1) != TC_CRYPTO_SUCCESS) { - return BLE_SM_KEY_ERR; - } -#endif - - /* Make sure generated key isn't debug key. */ - } while (memcmp(priv, ble_sm_alg_dbg_priv_key, 32) == 0); - - swap_buf(pub, pk, 32); - swap_buf(&pub[32], &pk[32], 32); - swap_in_place(priv, 32); -#endif - - return 0; -} - -#endif diff --git a/components/driver/test_apps/ledc/main/test_ledc.c b/components/driver/test_apps/ledc/main/test_ledc.c index 9b72359bdb..8b5a0ebbf2 100644 --- a/components/driver/test_apps/ledc/main/test_ledc.c +++ b/components/driver/test_apps/ledc/main/test_ledc.c @@ -467,7 +467,7 @@ TEST_CASE("LEDC multi fade test", "[ledc]") } #endif // SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED -#if SOC_PCNT_SUPPORTED // Note. C3, C2, H4 do not have PCNT peripheral, the following test cases cannot be tested +#if SOC_PCNT_SUPPORTED // Note. C3, C2 do not have PCNT peripheral, the following test cases cannot be tested #include "driver/pulse_cnt.h" diff --git a/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c b/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c index 80c70aadd4..ba3f5bfc1c 100644 --- a/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c +++ b/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c @@ -33,7 +33,7 @@ #endif -// H4 and C2 will not support external flash. +// H2 and C2 will not support external flash. #define TEST_FLASH_FREQ_MHZ 5 typedef struct { diff --git a/components/driver/test_apps/spi/slave/main/test_spi_slave.c b/components/driver/test_apps/spi/slave/main/test_spi_slave.c index 658259018d..130c7b6cce 100644 --- a/components/driver/test_apps/spi/slave/main/test_spi_slave.c +++ b/components/driver/test_apps/spi/slave/main/test_spi_slave.c @@ -273,7 +273,7 @@ TEST_CASE("test slave send unaligned", "[spi]") /******************************************************************************** * Test By Master & Slave (2 boards) * - * Master (C3, C2, H4) && Slave (C3, C2, H4): + * Master (C3, C2, H2) && Slave (C3, C2, H2): * PIN | Master | Slave | * ----| --------- | --------- | * CS | 10 | 10 | diff --git a/components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c b/components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c index 49999fabdc..c8da4316d4 100644 --- a/components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c +++ b/components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c @@ -583,7 +583,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]" /******************************************************************************** * Test By Master & Slave (2 boards) * - * Master (C3, C2, H4) && Slave (C3, C2, H4): + * Master (C3, C2, H2) && Slave (C3, C2, H2): * PIN | Master | Slave | * ----| --------- | --------- | * CS | 10 | 10 | diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 498f50721d..24a9257bb5 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -498,7 +498,7 @@ def main(): parser = argparse.ArgumentParser(description='ESP32 eFuse Manager') parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3', - 'esp32h4', 'esp32c2', 'esp32c6', 'esp32h2'], default='esp32') + 'esp32c2', 'esp32c6', 'esp32h2'], default='esp32') parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true') parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false') parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true') diff --git a/components/esp_coex/CMakeLists.txt b/components/esp_coex/CMakeLists.txt index 9ea06f892f..55c482ced6 100644 --- a/components/esp_coex/CMakeLists.txt +++ b/components/esp_coex/CMakeLists.txt @@ -8,17 +8,8 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE) set(link_binary_libs 1) set(ldfragments "linker.lf") endif() - - # TODO: need to remove these logic when unsupport esp32h4. - if(IDF_TARGET STREQUAL "esp32h4") - set(srcs - "src/coexist.c" - "esp32h2/esp_coex_adapter.c") - else() - set(srcs - "src/coexist.c" - "${idf_target}/esp_coex_adapter.c") - endif() + set(srcs "src/coexist.c" + "${idf_target}/esp_coex_adapter.c") endif() if(CONFIG_ESP_WIFI_ENABLED) @@ -38,14 +29,8 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE) if(link_binary_libs) set(blob coexist) - # TODO: need to remove these logic when unsupport esp32h4. - if(IDF_TARGET STREQUAL "esp32h4") - add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h2/lib${blob}.a" + add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/lib${blob}.a" REQUIRES ${COMPONENT_NAME}) - else() - add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/lib${blob}.a" - REQUIRES ${COMPONENT_NAME}) - endif() target_link_libraries(${COMPONENT_LIB} PUBLIC ${blob}) endif() diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index 77bdc3d238..6b68cc9596 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -47,16 +47,7 @@ idf_component_register(SRCS "${srcs}" ) set(target_name "${idf_target}") -if(IDF_TARGET STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h4/rev2") - endif() - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h4/rev1") - endif() -else() - target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}") -endif() +target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}") # Override functions in PHY lib with the functions in 'phy_override.c' target_link_libraries(${COMPONENT_LIB} INTERFACE "-u include_esp_phy_override") diff --git a/components/esp_phy/src/phy_init_esp32hxx.c b/components/esp_phy/src/phy_init_esp32hxx.c index d1ac1f454f..faaf3bc6cb 100644 --- a/components/esp_phy/src/phy_init_esp32hxx.c +++ b/components/esp_phy/src/phy_init_esp32hxx.c @@ -54,10 +54,10 @@ void esp_phy_enable(void) s_phy_access_ref++; _lock_release(&s_phy_access_lock); - // ESP32H4-TODO: enable common clk. + // ESP32H2-TODO: enable common clk. } void esp_phy_disable(void) { - // ESP32H4-TODO: close rf and disable clk for modem sleep and light sleep + // ESP32H2-TODO: close rf and disable clk for modem sleep and light sleep } diff --git a/components/esp_pm/include/esp_pm.h b/components/esp_pm/include/esp_pm.h index f64bdd93cf..7e34b21380 100644 --- a/components/esp_pm/include/esp_pm.h +++ b/components/esp_pm/include/esp_pm.h @@ -33,7 +33,6 @@ typedef esp_pm_config_t esp_pm_config_esp32_t __attribute__((deprecated("pleas typedef esp_pm_config_t esp_pm_config_esp32s2_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32s3_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32c3_t __attribute__((deprecated("please use esp_pm_config_t instead"))); -typedef esp_pm_config_t esp_pm_config_esp32h4_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32c2_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32c6_t __attribute__((deprecated("please use esp_pm_config_t instead"))); diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index d4ff1804a8..13343f48f4 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -73,8 +73,6 @@ #define REF_CLK_DIV_MIN 2 // TODO: IDF-5660 #elif CONFIG_IDF_TARGET_ESP32C3 #define REF_CLK_DIV_MIN 2 -#elif CONFIG_IDF_TARGET_ESP32H4 -#define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32C2 #define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_pm/pm_trace.c b/components/esp_pm/pm_trace.c index c77e77ffb3..c23d10e099 100644 --- a/components/esp_pm/pm_trace.c +++ b/components/esp_pm/pm_trace.c @@ -15,7 +15,7 @@ * Feel free to change when debugging. */ static const int DRAM_ATTR s_trace_io[] = { -#if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32H4) && !defined(CONFIG_IDF_TARGET_ESP32C2) +#if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32C2) BIT(4), BIT(5), // ESP_PM_TRACE_IDLE BIT(16), BIT(17), // ESP_PM_TRACE_TICK BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c index 7678d46d81..43f9df74e6 100644 --- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c +++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c @@ -67,8 +67,6 @@ static const int test_freqs[] = {40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, 40, 80 #elif CONFIG_IDF_TARGET_ESP32C2 static const int test_freqs[] = {CONFIG_XTAL_FREQ, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, CONFIG_XTAL_FREQ, 80, CONFIG_XTAL_FREQ / 2, CONFIG_XTAL_FREQ}; // C2 xtal has 40/26MHz option -#elif CONFIG_IDF_TARGET_ESP32H4 -static const int test_freqs[] = {32, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 32} // TODO: IDF-3786 #else static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40}; #endif diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 73e8e31894..1d06eb69c7 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -51,15 +51,7 @@ idf_component_register(SRCS ${sources} PRIV_REQUIRES ${private_required_comp} LDFRAGMENTS linker.lf) -if(target STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - set(ld_folder "ld/rev1") - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - set(ld_folder "ld/rev2") - endif() -else() - set(ld_folder "ld") -endif() +set(ld_folder "ld") # Append a target linker script at the target-specific path, # only the 'name' part is different for each script @@ -108,9 +100,6 @@ if(BOOTLOADER_BUILD) elseif(target STREQUAL "esp32c3") rom_linker_script("newlib") - elseif(target STREQUAL "esp32h4") - rom_linker_script("newlib") - elseif(target STREQUAL "esp32c2") rom_linker_script("newlib") rom_linker_script("mbedtls") @@ -215,16 +204,6 @@ else() # Regular app build rom_linker_script("eco3") endif() - elseif(target STREQUAL "esp32h4") - rom_linker_script("newlib") - rom_linker_script("version") - - if(CONFIG_NEWLIB_NANO_FORMAT AND time_t_size EQUAL 4) - # nano formatting functions in ROM are built for 32-bit time_t, - # only link them if the toolchain is also using 32-bit time_t and nano formatting was requested. - rom_linker_script("newlib-nano") - endif() - elseif(target STREQUAL "esp32c2") rom_linker_script("newlib") rom_linker_script("version") diff --git a/components/esp_rom/README.md b/components/esp_rom/README.md index 3cef0e4c82..e1f7f4385e 100644 --- a/components/esp_rom/README.md +++ b/components/esp_rom/README.md @@ -17,8 +17,6 @@ When using ROM functions in esp-idf, the including convention is `/rom/< #include "esp32c3/rom/uart.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/uart.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/uart.h" ... ``` diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index e8ed1f928c..3205775cbd 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -99,7 +99,6 @@ menu "ESP System Settings" default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 - default y if IDF_TARGET_ESP32H4 default y if IDF_TARGET_ESP32C6 default n if IDF_TARGET_ESP32H2 # IDF-5667 depends on SOC_RTC_FAST_MEM_SUPPORTED @@ -280,7 +279,7 @@ menu "ESP System Settings" config ESP_CONSOLE_MULTIPLE_UART bool - default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 + default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 choice ESP_CONSOLE_UART_NUM prompt "UART peripheral to use for console output (0-1)" diff --git a/components/esp_system/crosscore_int.c b/components/esp_system/crosscore_int.c index ceede38f66..d9102a16ed 100644 --- a/components/esp_system/crosscore_int.c +++ b/components/esp_system/crosscore_int.c @@ -29,7 +29,7 @@ #define REASON_FREQ_SWITCH BIT(1) #define REASON_GDB_CALL BIT(3) -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 +#if !CONFIG_IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 #define REASON_PRINT_BACKTRACE BIT(2) #define REASON_TWDT_ABORT BIT(4) #endif @@ -66,7 +66,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) { } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); #endif @@ -147,7 +147,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); #endif } @@ -167,7 +167,7 @@ void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id) esp_crosscore_int_send(core_id, REASON_GDB_CALL); } -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 +#if !CONFIG_IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id) { esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE); diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c index 0f7c92057d..24e5e2f909 100644 --- a/components/esp_system/fpga_overrides.c +++ b/components/esp_system/fpga_overrides.c @@ -17,8 +17,6 @@ #include "esp32s3/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 @@ -47,8 +45,6 @@ void bootloader_clock_configure(void) uint32_t xtal_freq_mhz = 40; #ifdef CONFIG_IDF_TARGET_ESP32S2 uint32_t apb_freq_hz = 20000000; -#elif CONFIG_IDF_TARGET_ESP32H4 - uint32_t apb_freq_hz = 32000000; #else uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000; #endif // CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/esp_system/include/esp_private/crosscore_int.h b/components/esp_system/include/esp_private/crosscore_int.h index 823794453a..652290eed2 100644 --- a/components/esp_system/include/esp_private/crosscore_int.h +++ b/components/esp_system/include/esp_private/crosscore_int.h @@ -50,7 +50,7 @@ void esp_crosscore_int_send_freq_switch(int core_id); void esp_crosscore_int_send_gdb_call(int core_id); -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 /** * Send an interrupt to a CPU indicating it should print its current backtrace * @@ -75,7 +75,7 @@ void esp_crosscore_int_send_print_backtrace(int core_id); void esp_crosscore_int_send_twdt_abort(int core_id); #endif // CONFIG_ESP_TASK_WDT_EN -#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 +#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 #ifdef __cplusplus } diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index a930c63db9..d3fdbc77d3 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -56,11 +56,6 @@ #include "esp32h2/rtc.h" #include "esp32h2/rom/cache.h" #include "esp_memprot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" -#include "esp32h4/rom/cache.h" -#include "esp32h4/rom/secure_boot.h" -#include "esp_memprot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #include "esp32c2/rom/cache.h" diff --git a/components/esp_system/system_time.c b/components/esp_system/system_time.c index 8b130dce78..2ff7107978 100644 --- a/components/esp_system/system_time.c +++ b/components/esp_system/system_time.c @@ -21,8 +21,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c index 7d6bafbefb..e28134f7c8 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c @@ -43,7 +43,7 @@ #define BROWNOUT "BROWN_OUT_RST" #define STORE_ERROR "StoreProhibited" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #define DEEPSLEEP "DSLEEP" #define LOAD_STORE_ERROR "Store access fault" #define RESET "RTC_SW_CPU_RST" diff --git a/components/esp_timer/src/esp_timer.c b/components/esp_timer/src/esp_timer.c index 27dcf35c69..138bf18a08 100644 --- a/components/esp_timer/src/esp_timer.c +++ b/components/esp_timer/src/esp_timer.c @@ -31,8 +31,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_timer/src/ets_timer_legacy.c b/components/esp_timer/src/ets_timer_legacy.c index e21012f98d..5ba2868e1d 100644 --- a/components/esp_timer/src/ets_timer_legacy.c +++ b/components/esp_timer/src/ets_timer_legacy.c @@ -32,8 +32,6 @@ #include "esp32c3/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32H2 diff --git a/components/esp_timer/src/system_time.c b/components/esp_timer/src/system_time.c index 6f811d59de..e7844a2ccd 100644 --- a/components/esp_timer/src/system_time.c +++ b/components/esp_timer/src/system_time.c @@ -25,8 +25,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_timer/test_apps/main/test_ets_timer.c b/components/esp_timer/test_apps/main/test_ets_timer.c index 7585b4f2ef..6745e850b9 100644 --- a/components/esp_timer/test_apps/main/test_ets_timer.c +++ b/components/esp_timer/test_apps/main/test_ets_timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,8 +23,6 @@ #include "esp32s3/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_wifi/Kconfig b/components/esp_wifi/Kconfig index 46e1f98be9..7e528b4ed0 100644 --- a/components/esp_wifi/Kconfig +++ b/components/esp_wifi/Kconfig @@ -1,6 +1,5 @@ menu "Wi-Fi" - visible if !IDF_TARGET_ESP32H4 config ESP_WIFI_ENABLED bool diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index e59c2fbc04..abb0cf52df 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -91,7 +91,6 @@ menu "Serial flasher config" default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2 - default ESPTOOLPY_FLASHFREQ_48M if IDF_TARGET_ESP32H4 config ESPTOOLPY_FLASHFREQ_120M bool "120 MHz" select SPI_FLASH_HPM_ENABLE diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index a492887535..064a0825c0 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -6,14 +6,6 @@ idf_build_get_property(python PYTHON) idf_build_get_property(idf_path IDF_PATH) set(chip_model ${target}) -# TODO: remove this if block when esp32h4 beta1 is no longer supported and we have h4 target in esptool -if(target STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - set(chip_model esp32h2beta1) - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - set(chip_model esp32h2beta2) - endif() -endif() set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model}) set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py") diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig index fa8791abf8..28c8be4d00 100644 --- a/components/freertos/Kconfig +++ b/components/freertos/Kconfig @@ -366,7 +366,7 @@ menu "FreeRTOS" config FREERTOS_TICK_SUPPORT_SYSTIMER bool default y if !FREERTOS_TICK_SUPPORT_CORETIMER - # ESP32-S3, ESP32-C3 and ESP32-H4 can use Systimer for FreeRTOS SysTick + # ESP32-S3 and ESP32-C3 can use Systimer for FreeRTOS SysTick # ESP32S2 also has SYSTIMER but it can not be used for the FreeRTOS SysTick because: # - It has only one counter, which already in use esp_timer. # A counter for SysTick should be stall in debug mode but work esp_timer. diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c index e10aa48209..b9c6def99e 100644 --- a/components/heap/port/memory_layout_utils.c +++ b/components/heap/port/memory_layout_utils.c @@ -15,8 +15,6 @@ #include "esp32c3/rom/rom_layout.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/rom_layout.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rom_layout.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rom_layout.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c b/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c index 320775d90e..cbe30e1cf7 100644 --- a/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c +++ b/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c @@ -12,8 +12,6 @@ #include "esp32s2/rom/digital_signature.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/digital_signature.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/digital_signature.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/digital_signature.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/mbedtls/port/sha/dma/sha.c b/components/mbedtls/port/sha/dma/sha.c index 59ad40e887..35e76be8ae 100644 --- a/components/mbedtls/port/sha/dma/sha.c +++ b/components/mbedtls/port/sha/dma/sha.c @@ -54,8 +54,6 @@ #include "esp32s3/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32s3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" #endif diff --git a/components/newlib/newlib_init.c b/components/newlib/newlib_init.c index 9b5bf18474..ffad04c20b 100644 --- a/components/newlib/newlib_init.c +++ b/components/newlib/newlib_init.c @@ -29,8 +29,6 @@ #include "esp32s3/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/libc_stubs.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C6 @@ -113,7 +111,7 @@ static struct syscall_stub_table s_stub_table = { ._printf_float = NULL, ._scanf_float = NULL, #endif -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 \ +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 \ || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 /* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM assertion failures (as function names & source file names will be similar) @@ -137,7 +135,7 @@ void esp_newlib_init(void) syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table; #elif CONFIG_IDF_TARGET_ESP32S2 syscall_table_ptr_pro = &s_stub_table; -#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 \ +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 \ || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 syscall_table_ptr = &s_stub_table; #endif diff --git a/components/newlib/port/esp_time_impl.c b/components/newlib/port/esp_time_impl.c index 3a068ce283..79fc8b8d2a 100644 --- a/components/newlib/port/esp_time_impl.c +++ b/components/newlib/port/esp_time_impl.c @@ -33,9 +33,6 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rtc.h" diff --git a/components/newlib/test/test_newlib.c b/components/newlib/test/test_newlib.c index 6c1160ea16..d6d9ddbf90 100644 --- a/components/newlib/test/test_newlib.c +++ b/components/newlib/test/test_newlib.c @@ -139,7 +139,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]") TEST_ASSERT_FALSE(fn_in_rom(vfprintf)); #endif // CONFIG_NEWLIB_NANO_FORMAT || ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT -#if (CONFIG_NEWLIB_NANO_FORMAT && (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4)) || ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT +#if (CONFIG_NEWLIB_NANO_FORMAT && (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2)) || ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT TEST_ASSERT(fn_in_rom(sscanf)); #else TEST_ASSERT_FALSE(fn_in_rom(sscanf)); @@ -148,7 +148,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]") #if defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_SPIRAM) TEST_ASSERT(fn_in_rom(atoi)); TEST_ASSERT(fn_in_rom(strtol)); -#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H4)\ +#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) \ || defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C6) /* S3 and C3 always use these from ROM */ TEST_ASSERT(fn_in_rom(atoi)); diff --git a/components/newlib/test/test_time.c b/components/newlib/test/test_time.c index e4f8f5879f..6ba8a7998a 100644 --- a/components/newlib/test/test_time.c +++ b/components/newlib/test/test_time.c @@ -35,8 +35,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/openthread/port/esp_openthread_radio.c b/components/openthread/port/esp_openthread_radio.c index 1d376ec48d..5dd4161954 100644 --- a/components/openthread/port/esp_openthread_radio.c +++ b/components/openthread/port/esp_openthread_radio.c @@ -298,9 +298,6 @@ otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) aFrame->mPsdu[-1] = aFrame->mLength; // lenth locates one byte before the psdu (esp_openthread_radio_tx_psdu); -// TODO: remove this macro check when esp32h4 unsupported. -#if !CONFIG_IDF_TARGET_ESP32H4 - // esp32h4 do not support tx security if (otMacFrameIsSecurityEnabled(aFrame) && !aFrame->mInfo.mTxInfo.mIsSecurityProcessed) { otMacFrameSetFrameCounter(aFrame, s_mac_frame_counter++); if (otMacFrameIsKeyIdMode1(aFrame)) { @@ -314,12 +311,10 @@ otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) esp_ieee802154_set_transmit_security(&aFrame->mPsdu[-1], s_security_key, s_security_addr); } - // esp32h4 do not support transmit at if (aFrame->mInfo.mTxInfo.mTxDelay != 0) { esp_ieee802154_transmit_at(&aFrame->mPsdu[-1], aFrame->mInfo.mTxInfo.mCsmaCaEnabled, (aFrame->mInfo.mTxInfo.mTxDelayBaseTime + aFrame->mInfo.mTxInfo.mTxDelay)); } else -#endif { esp_ieee802154_transmit(&aFrame->mPsdu[-1], aFrame->mInfo.mTxInfo.mCsmaCaEnabled); } @@ -342,22 +337,15 @@ int8_t otPlatRadioGetRssi(otInstance *aInstance) otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) { return (otRadioCaps)(OT_RADIO_CAPS_ENERGY_SCAN | -// TODO: remove this macro check when esp32h4 unsupported. -#if !CONFIG_IDF_TARGET_ESP32H4 OT_RADIO_CAPS_TRANSMIT_SEC | OT_RADIO_CAPS_RECEIVE_TIMING | OT_RADIO_CAPS_TRANSMIT_TIMING | -#endif OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_SLEEP_TO_TX); } -// TODO: remove this macro check when esp32h4 unsupported. -#if !CONFIG_IDF_TARGET_ESP32H4 -// esp32h4 do not support receive at otError otPlatRadioReceiveAt(otInstance *aInstance, uint8_t aChannel, uint32_t aStart, uint32_t aDuration) { esp_ieee802154_receive_at((aStart + aDuration)); return OT_ERROR_NONE; } -#endif bool otPlatRadioGetPromiscuous(otInstance *aInstance) { diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index d81237360d..f91817d69b 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -417,7 +417,7 @@ void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state) #elif CONFIG_IDF_TARGET_ESP32S3 Cache_Resume_DCache(saved_state & 0xffff); Cache_Resume_ICache(saved_state >> 16); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 Cache_Resume_ICache(saved_state >> 16); #elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 Cache_Resume_ICache(saved_state); @@ -434,7 +434,7 @@ IRAM_ATTR bool spi_flash_cache_enabled(void) #endif #elif CONFIG_IDF_TARGET_ESP32S2 bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); -#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0); #elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 bool result = s_cache_enabled; @@ -551,7 +551,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable int i; bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true; uint32_t drom0_in_icache = 1;//always 1 in esp32s2 -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 drom0_in_icache = 0; #endif @@ -938,7 +938,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable } #endif -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache) { @@ -979,7 +979,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable) } return ESP_OK; } -#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid) { diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index c902839a1d..b912460c42 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -40,7 +40,7 @@ typedef struct { } spi_noos_arg_t; static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 typedef struct { uint32_t icache_autoload; } spi_noos_arg_t; @@ -57,7 +57,7 @@ static IRAM_ATTR esp_err_t start(void *arg) spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); spi_arg->dcache_autoload = Cache_Suspend_DCache(); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); #endif @@ -74,7 +74,7 @@ static IRAM_ATTR esp_err_t end(void *arg) Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); Cache_Resume_DCache(spi_arg->dcache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 spi_noos_arg_t *spi_arg = arg; Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); diff --git a/components/wpa_supplicant/src/utils/includes.h b/components/wpa_supplicant/src/utils/includes.h index 8ca7fe32c2..368a0fe0ce 100644 --- a/components/wpa_supplicant/src/utils/includes.h +++ b/components/wpa_supplicant/src/utils/includes.h @@ -69,8 +69,6 @@ #include "esp32c3/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32H2 diff --git a/docs/en/api-guides/openthread.rst b/docs/en/api-guides/openthread.rst index 85c35c8dc3..4b0d5b354c 100644 --- a/docs/en/api-guides/openthread.rst +++ b/docs/en/api-guides/openthread.rst @@ -11,12 +11,12 @@ OpenThread can run under the following modes on Espressif chips: Standalone node +++++++++++++++ -The full OpenThread stack and the application layer runs on the same chip. This mode is available on chips with 15.4 radio such as ESP32-H4. +The full OpenThread stack and the application layer runs on the same chip. This mode is available on chips with 15.4 radio such as ESP32-H2. Radio Co-Processor (RCP) ++++++++++++++++++++++++ -The chip will be connected to another host running the OpenThread IP stack. It will send and received 15.4 packets on behalf of the host. This mode is available on chips with 15.4 radio such as ESP32-H4. The underlying transport between the chip and the host can be SPI or UART. For sake of latency, we recommend to use SPI as the underlying transport. +The chip will be connected to another host running the OpenThread IP stack. It will send and received 15.4 packets on behalf of the host. This mode is available on chips with 15.4 radio such as ESP32-H2. The underlying transport between the chip and the host can be SPI or UART. For sake of latency, we recommend to use SPI as the underlying transport. OpenThread host +++++++++++++++ @@ -38,8 +38,8 @@ For chips without 15.4 radio, it can be connected to an RCP and run OpenThread u # node labels HOST_NODE [label="OpenThread \nhost\n(ESP32)", fontsize=14]; - RCP [label="Radio \nCo-Processor\n(ESP32-H4)", fontsize=14]; - STANDALONE [label="Standalone \nnode\n (ESP32-H4)", fontsize=14]; + RCP [label="Radio \nCo-Processor\n(ESP32-H2)", fontsize=14]; + STANDALONE [label="Standalone \nnode\n (ESP32-H2)", fontsize=14]; # node connections + labels RCP -> STANDALONE [label="15.4 radio", dir=both, style=dashed]; diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index 916b76d316..dde1cc45d3 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -189,25 +189,6 @@ The source clock can also limit the PWM frequency. The higher the source clock f - 32 MHz - Dynamic Frequency Scaling compatible -.. only:: esp32h2 - - .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks - :widths: 15 15 30 - :header-rows: 1 - - * - Clock name - - Clock freq - - Clock capabilities - * - APB_CLK - - 96 MHz - - / - * - RC_FAST_CLK - - ~8 MHz - - Dynamic Frequency Scaling compatible, Light sleep compatible - * - XTAL_CLK - - 32 MHz - - Dynamic Frequency Scaling compatible - .. note:: .. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION @@ -220,7 +201,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f .. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX - 2. For {IDF_TARGET_NAME}, all timers share one clock source. In other words, it is impossible to use different clock sources for different timers. + 1. For {IDF_TARGET_NAME}, all timers share one clock source. In other words, it is impossible to use different clock sources for different timers. When a timer is no longer needed by any channel, it can be deconfigured by calling the same function :cpp:func:`ledc_timer_config`. The configuration structure :cpp:type:`ledc_timer_config_t` passes in should be: diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index ec552ea7db..9011630ff1 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -189,25 +189,6 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - 32 MHz - 支持动态调频（DFS）功能 -.. only:: esp32h2 - - .. list-table:: {IDF_TARGET_NAME} LEDC 时钟源特性 - :widths: 10 10 30 - :header-rows: 1 - - * - 时钟名称 - - 时钟频率 - - 时钟功能 - * - APB_CLK - - 96 MHz - - / - * - RC_FAST_CLK - - ~8 MHz - - 支持动态调频（DFS）功能，支持Light-sleep模式 - * - XTAL_CLK - - 32 MHz - - 支持动态调频（DFS）功能 - .. note:: .. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION @@ -220,7 +201,7 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 .. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX - 2. {IDF_TARGET_NAME} 的所有定时器共用一个时钟源。因此 {IDF_TARGET_NAME} 不支持给不同的定时器配置不同的时钟源。 + 1. {IDF_TARGET_NAME} 的所有定时器共用一个时钟源。因此 {IDF_TARGET_NAME} 不支持给不同的定时器配置不同的时钟源。 当一个定时器不再被任何通道所需要时，可以通过调用相同的函数 :cpp:func:`ledc_timer_config` 来重置这个定时器。此时，函数入参的配置结构体需要指定： diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml index 06c76d42ba..a934695505 100644 --- a/examples/bluetooth/.build-test-rules.yml +++ b/examples/bluetooth/.build-test-rules.yml @@ -2,31 +2,31 @@ examples/bluetooth/bluedroid/ble: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet examples/bluetooth/bluedroid/ble_50: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet examples/bluetooth/bluedroid/ble_50/multi-adv: enable: - - if: IDF_TARGET in ["esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet @@ -44,11 +44,11 @@ examples/bluetooth/bluedroid/coex/a2dp_gatts_coex: examples/bluetooth/bluedroid/coex/gattc_gatts_coex: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet @@ -58,7 +58,7 @@ examples/bluetooth/blufi: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -68,7 +68,7 @@ examples/bluetooth/esp_ble_mesh: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -78,7 +78,7 @@ examples/bluetooth/esp_ble_mesh/aligenie_demo: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -88,7 +88,7 @@ examples/bluetooth/esp_ble_mesh/ble_mesh_coex_test: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -138,23 +138,23 @@ examples/bluetooth/nimble: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_l2cap_coc: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2" , "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2" , "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_multi_adv: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32h4", "esp32s3"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3"] temporary: true reason: the other targets are not tested yet disable_test: @@ -164,61 +164,61 @@ examples/bluetooth/nimble/ble_multi_adv: examples/bluetooth/nimble/ble_periodic_adv: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_periodic_sync: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_phy: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32h4", "esp32s3" ] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_spp: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32h4", "esp32s3" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/blecent: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/blehr: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -228,17 +228,17 @@ examples/bluetooth/nimble/blemesh: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/bleprph: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -248,7 +248,7 @@ examples/bluetooth/nimble/bleprph_wifi_coex: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -258,6 +258,6 @@ examples/bluetooth/nimble/hci: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet diff --git a/examples/bluetooth/bluedroid/ble/ble_ancs/README.md b/examples/bluetooth/bluedroid/ble/ble_ancs/README.md index 40e05711c2..8b10feb42e 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ancs/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_ancs/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE ANCS Example @@ -28,7 +28,7 @@ All these characteristics require authorization for access. ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md index f074d148ab..2a68837a19 100644 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE Compatibility Test Example @@ -23,7 +23,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md b/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md index 0539a5542f..116c866cea 100644 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Eddystone Example @@ -20,7 +20,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md index ac7665365c..ee29a3a354 100644 --- a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE HID Example @@ -23,7 +23,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md b/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md index 8b8d9f6f38..3292da3322 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF iBeacon demo diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md b/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md index 4975ee3d54..1f592e56ee 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF SPP GATT CLIENT demo diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md b/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md index 8641951a86..e05a0c73a8 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | ## ESP-IDF GATT SERVER SPP Example @@ -15,7 +15,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-S3/ESP32-C2/ESP32-H4 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-S3/ESP32-C2/ESP32-H2 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md index 85a88ff79c..2db13d9e46 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE throughput GATT CLIENT Test @@ -27,7 +27,7 @@ please set: `idf.py menuconfig --> Component config --> Example 'GATT CLIENT THR ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md index 57010cde2d..287aa57a70 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE throughput GATT SERVER Test @@ -26,7 +26,7 @@ please set: `idf.py menuconfig --> Component config --> Example 'GATT CLIENT THR ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/README.md b/examples/bluetooth/bluedroid/ble/gatt_client/README.md index 3cd6b4650e..f7962c3ef8 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_client/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Client Example @@ -21,7 +21,7 @@ Please, check this [tutorial](tutorial/Gatt_Client_Example_Walkthrough.md) for m ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md b/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md index 593907bc76..dbc54c0b85 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Client Example @@ -24,7 +24,7 @@ Please, check this [tutorial](tutorial/Gatt_Security_Client_Example_Walkthrough. ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md b/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md index 8206d2711c..0c9904ca7b 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Server Example @@ -23,7 +23,7 @@ There are some important points for this demo: ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 Soc (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 Soc (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/README.md b/examples/bluetooth/bluedroid/ble/gatt_server/README.md index bf44eec10f..e75dbbe843 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Server Example @@ -23,7 +23,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md index e43019e555..9da98027db 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Server Service Table Example @@ -17,7 +17,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md index 424c6acfd5..576feac667 100644 --- a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md +++ b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Client Multi Connection Example @@ -21,7 +21,7 @@ The code can be modified to connect to more devices (up to 4 devices by default) ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md index 67e933dde7..bbe23c5089 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Client Example @@ -26,7 +26,7 @@ Please, check this [tutorial](tutorial/ble50_security_client_Example_Walkthrough ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3 SoC, ESP32-C2/ESP32-H4 SoC and BT5.0 supported chip (e.g., ESP32-C3-DevKitC-1 etc.) +* A development board with ESP32-C3 SoC, ESP32-S3 SoC, ESP32-C2/ESP32-H2 SoC and BT5.0 supported chip (e.g., ESP32-C3-DevKitC-1 etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md index 39e0851b9d..4feedb799c 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE50 Security Server Example @@ -24,7 +24,7 @@ There are some important points for this demo: ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2/ESP32-H4 SoC and BLE5.0 supoorted chips. (e.g., ESP32-C3-DevKitC-1, etc.) +* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2/ESP32-H2 SoC and BLE5.0 supoorted chips. (e.g., ESP32-C3-DevKitC-1, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md b/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md index e3c5f35c99..a9938f5ad1 100644 --- a/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md +++ b/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | #ESP-IDF Multi Adv Example @@ -17,7 +17,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H4/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) +* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H2/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md index 9c561bac2a..250886bcc7 100644 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md +++ b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP_IDF Periodic Adv Example @@ -21,7 +21,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H4 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) +* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H2 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md index 74a3fad22f..3fa038f99e 100644 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md +++ b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Periodic Sync Example @@ -19,7 +19,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H4 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) +* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H2 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md index 886dd7e17c..a79a893887 100644 --- a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md +++ b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | ESP-IDF Gattc and Gatts Coexistence example ============================================== diff --git a/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c index 9b8bd3fdc8..cf6252a59d 100644 --- a/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c +++ b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c @@ -63,8 +63,6 @@ void app_main(void) repl_config.prompt = "esp32c3>"; #elif CONFIG_IDF_TARGET_ESP32S3 repl_config.prompt = "esp32s3>"; -#elif CONFIG_IDF_TARGET_ESP32H4 - repl_config.prompt = "esp32h4>"; #else repl_config.prompt = "esp32>"; #endif diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md index 7fdfb503b4..56b4588316 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Central L2CAP COC Example diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md index 1d8aafbde0..c40df5ee0f 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Central L2CAP COC Example diff --git a/examples/bluetooth/nimble/ble_multi_adv/README.md b/examples/bluetooth/nimble/ble_multi_adv/README.md index 48bebaf34a..780c5a23df 100644 --- a/examples/bluetooth/nimble/ble_multi_adv/README.md +++ b/examples/bluetooth/nimble/ble_multi_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Multi Adv Example @@ -34,7 +34,7 @@ To configure number of advertising instances: ### Hardware Required -* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H4/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) +* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H2/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/nimble/ble_periodic_adv/README.md b/examples/bluetooth/nimble/ble_periodic_adv/README.md index 2ca24cdbe3..60873a4e34 100644 --- a/examples/bluetooth/nimble/ble_periodic_adv/README.md +++ b/examples/bluetooth/nimble/ble_periodic_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Periodic Advertiser Example @@ -30,7 +30,7 @@ idf.py set-target ### Configure the project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig @@ -60,9 +60,9 @@ I (353) system_api: read default base MAC address from EFUSE I (353) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:14:8e I (363) NimBLE_BLE_PERIODIC_ADV: BLE Host Task Started -I (373) NimBLE: Device Address: +I (373) NimBLE: Device Address: I (373) NimBLE: d0:42:3a:95:84:05 -I (373) NimBLE: +I (373) NimBLE: I (383) NimBLE: instance 1 started (periodic) ``` diff --git a/examples/bluetooth/nimble/ble_periodic_sync/README.md b/examples/bluetooth/nimble/ble_periodic_sync/README.md index 2977d607bf..c8e2d3aff4 100644 --- a/examples/bluetooth/nimble/ble_periodic_sync/README.md +++ b/examples/bluetooth/nimble/ble_periodic_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Periodic Sync Example @@ -37,7 +37,7 @@ See [Development Boards](https://www.espressif.com/en/products/devkits) for more ### Configure the Project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig @@ -67,15 +67,15 @@ I (351) system_api: read default base MAC address from EFUSE I (351) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:14:8e I (361) NimBLE_BLE_PERIODIC_SYNC: BLE Host Task Started -I (941) NimBLE: Periodic sync event : +I (941) NimBLE: Periodic sync event : -I (941) NimBLE: Periodic adv report event: +I (941) NimBLE: Periodic adv report event: -I (4241) NimBLE: Periodic adv report event: +I (4241) NimBLE: Periodic adv report event: -I (7541) NimBLE: Periodic adv report event: +I (7541) NimBLE: Periodic adv report event: -I (10841) NimBLE: Periodic adv report event: +I (10841) NimBLE: Periodic adv report event: ``` diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md index b41cc01cf2..72d297a8b7 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Central PHY Example diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md index d723a212d1..687b7c8a95 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral PHY Example diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/README.md b/examples/bluetooth/nimble/ble_spp/spp_client/README.md index 047ec3e5f2..f517ab9e55 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/README.md +++ b/examples/bluetooth/nimble/ble_spp/spp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE SPP central example @@ -108,7 +108,7 @@ I (487) NimBLE_SPP_BLE_CENT: BLE Host Task Started GAP procedure initiated: stop advertising. GAP procedure initiated: discovery; own_addr_type=0 filter_policy=0 passive=1 limited=0 filter_duplicates=1 duration=forever GAP procedure initiated: connect; peer_addr_type=0 peer_addr=7c:df:a1:40:3e:fa scan_itvl=16 scan_window=16 itvl_min=24 itvl_max=40 latency=0 supervision_timeout=256 min_ce_len=0 max_ce_len=0 own_addr_type=0 -Connection established +Connection established GATT procedure initiated: discover all services GATT procedure initiated: discover all characteristics; start_handle=1 end_handle=5 GATT procedure initiated: discover all characteristics; start_handle=6 end_handle=9 diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/README.md b/examples/bluetooth/nimble/ble_spp/spp_server/README.md index 38775429f3..e206735eed 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/README.md +++ b/examples/bluetooth/nimble/ble_spp/spp_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE SPP peripheral example @@ -106,7 +106,7 @@ GAP procedure initiated: advertise; disc_mode=2 adv_channel_map=0 own_addr_type= connection established; status=0 handle=1 our_ota_addr_type=0 our_ota_addr=7c:df:a1:40:3e:fa our_id_addr_type=0 our_id_addr=7c:df:a1:40:3e:fa peer_ota_addr_type=0 peer_ota_addr=7c:df:a1:c2:19:92 peer_id_addr_type=0 peer_id_addr=7c:df:a1:c2:19:92 conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 I (6924) NimBLE_SPP_BLE_PRPH: Data received in write event,conn_handle = 1,attr_handle = 11 -1b5b41I +1b5b41I (10824) NimBLE_SPP_BLE_PRPH: Notification sent successfully ``` diff --git a/examples/bluetooth/nimble/blecent/README.md b/examples/bluetooth/nimble/blecent/README.md index e1026bf6c3..32bd991fcf 100644 --- a/examples/bluetooth/nimble/blecent/README.md +++ b/examples/bluetooth/nimble/blecent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Central Example @@ -31,7 +31,7 @@ This example aims at understanding BLE service discovery, connection, encryption To test this demo, use any BLE GATT server app that advertises support for the Alert Notification service (0x1811) and includes it in the GATT database. -A Python based utility `blecent_test.py` is also provided (which will run as a BLE GATT server) and can be used to test this example. +A Python based utility `blecent_test.py` is also provided (which will run as a BLE GATT server) and can be used to test this example. Note : @@ -55,7 +55,7 @@ See [Development Boards](https://www.espressif.com/en/products/devkits) for more ### Configure the Project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig diff --git a/examples/bluetooth/nimble/blehr/README.md b/examples/bluetooth/nimble/blehr/README.md index 91ac4bf59f..92dc5fdf62 100644 --- a/examples/bluetooth/nimble/blehr/README.md +++ b/examples/bluetooth/nimble/blehr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Heart Rate Measurement Example @@ -13,7 +13,7 @@ This example aims at understanding notification subscriptions and sending notifi To test this demo, any BLE scanner app can be used. -A Python based utility `blehr_test.py` is also provided (which will run as a BLE GATT Client) and can be used to test this example. +A Python based utility `blehr_test.py` is also provided (which will run as a BLE GATT Client) and can be used to test this example. Note : diff --git a/examples/bluetooth/nimble/bleprph/README.md b/examples/bluetooth/nimble/bleprph/README.md index 07cf4fda74..9692af72b0 100644 --- a/examples/bluetooth/nimble/bleprph/README.md +++ b/examples/bluetooth/nimble/bleprph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral Example @@ -34,7 +34,7 @@ idf.py set-target ### Configure the project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig diff --git a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild index 9e84fb73ec..ce79cb4e23 100644 --- a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild +++ b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild @@ -142,7 +142,6 @@ menu "Example Ethernet Configuration" default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 4 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI SCLK. @@ -152,7 +151,6 @@ menu "Example Ethernet Configuration" default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 5 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI MOSI. @@ -162,14 +160,13 @@ menu "Example Ethernet Configuration" default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 0 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI MISO. config EXAMPLE_ETH_SPI_CLOCK_MHZ int "SPI clock speed (MHz)" range 5 80 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4 + default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 help Set the clock speed (MHz) of SPI interface. @@ -179,7 +176,6 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 - default 1 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI CS0, i.e. Chip Select associated with the first SPI Eth module). @@ -191,7 +187,6 @@ menu "Example Ethernet Configuration" default 7 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 8 if IDF_TARGET_ESP32C3 default 3 if IDF_TARGET_ESP32C2 - default 11 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI CS1, i.e. Chip Select associated with the second SPI Eth module. @@ -200,7 +195,6 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 - default 9 if IDF_TARGET_ESP32H4 help Set the GPIO number used by the first SPI Ethernet module interrupt line. @@ -210,7 +204,6 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 33 if IDF_TARGET_ESP32 default 5 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 - default 10 if IDF_TARGET_ESP32H4 help Set the GPIO number used by the second SPI Ethernet module interrupt line. diff --git a/examples/ethernet/enc28j60/main/Kconfig.projbuild b/examples/ethernet/enc28j60/main/Kconfig.projbuild index 9223777db2..60001d4ed1 100644 --- a/examples/ethernet/enc28j60/main/Kconfig.projbuild +++ b/examples/ethernet/enc28j60/main/Kconfig.projbuild @@ -15,7 +15,6 @@ menu "Example Configuration" default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 4 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI SCLK. @@ -25,7 +24,6 @@ menu "Example Configuration" default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 5 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI MOSI. @@ -35,7 +33,6 @@ menu "Example Configuration" default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 0 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI MISO. @@ -44,7 +41,6 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 - default 1 if IDF_TARGET_ESP32H4 help Set the GPIO number used by SPI CS. @@ -60,7 +56,6 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 - default 9 if IDF_TARGET_ESP32H4 help Set the GPIO number used by ENC28J60 interrupt. diff --git a/examples/openthread/README.md b/examples/openthread/README.md index ae0709fca7..1c7728835e 100644 --- a/examples/openthread/README.md +++ b/examples/openthread/README.md @@ -6,8 +6,8 @@ See the [README.md](../README.md) file in the upper level [examples](../) direct In this folder, it contains following OpenThread examples: -* [ot_cli](ot_cli) is an OpenThread Command Line example, in addition to the features listed in [OpenThread CLI](https://github.com/openthread/openthread/blob/master/src/cli/README.md), it supports some additional features such as TCP, UDP and Iperf over lwIP. It runs on an 802.15.4 SoC like ESP32-H4. +* [ot_cli](ot_cli) is an OpenThread Command Line example, in addition to the features listed in [OpenThread CLI](https://github.com/openthread/openthread/blob/master/src/cli/README.md), it supports some additional features such as TCP, UDP and Iperf over lwIP. It runs on an 802.15.4 SoC like ESP32-H2. -* [ot_rcp](ot_rcp) is an [OpenThread RCP](https://openthread.io/platforms/co-processor) example. It runs on an 802.15.4 SoC like ESP32-H4, to extend 802.15.4 radio. +* [ot_rcp](ot_rcp) is an [OpenThread RCP](https://openthread.io/platforms/co-processor) example. It runs on an 802.15.4 SoC like ESP32-H2, to extend 802.15.4 radio. -* [ot_br](ot_br) is an [OpenThread Border Router](https://openthread.io/guides/border-router) example. It runs on a Wi-Fi SoC such as ESP32, ESP32-C3 and ESP32-S3. It needs an 802.15.4 SoC like ESP32-H4 running [ot_rcp](ot_rcp) example to provide 802.15.4 radio. +* [ot_br](ot_br) is an [OpenThread Border Router](https://openthread.io/guides/border-router) example. It runs on a Wi-Fi SoC such as ESP32, ESP32-C3 and ESP32-S3. It needs an 802.15.4 SoC like ESP32-H2 running [ot_rcp](ot_rcp) example to provide 802.15.4 radio. diff --git a/examples/openthread/ot_cli/sdkconfig.defaults b/examples/openthread/ot_cli/sdkconfig.defaults index cfc1abd08c..9ea24974eb 100644 --- a/examples/openthread/ot_cli/sdkconfig.defaults +++ b/examples/openthread/ot_cli/sdkconfig.defaults @@ -19,7 +19,7 @@ CONFIG_PARTITION_TABLE_MD5=y # # mbedTLS # -# ESP32H4-TODO: enable HW acceleration +# ESP32H2-TODO: enable HW acceleration CONFIG_MBEDTLS_HARDWARE_AES=n CONFIG_MBEDTLS_HARDWARE_MPI=n CONFIG_MBEDTLS_HARDWARE_SHA=n diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h index 72835af592..73e49bebb4 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h @@ -26,12 +26,12 @@ #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define I2C_SCL_IO (GPIO_NUM_16) #define I2C_SDA_IO (GPIO_NUM_17) +#elif CONFIG_IDF_TARGET_ESP32C3 +#define I2C_SCL_IO (GPIO_NUM_6) +#define I2C_SDA_IO (GPIO_NUM_7) #elif CONFIG_IDF_TARGET_ESP32H2 #define I2C_SCL_IO (GPIO_NUM_8) #define I2C_SDA_IO (GPIO_NUM_9) -#else -#define I2C_SCL_IO (GPIO_NUM_6) -#define I2C_SDA_IO (GPIO_NUM_7) #endif /* I2S port and GPIOs */ diff --git a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c b/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c index dab15b180e..ea5667e0b5 100644 --- a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c +++ b/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c @@ -22,7 +22,7 @@ #include "esp_system.h" #include "soc/spi_pins.h" -// h4 and c2 will not support external flash +// h2 and c2 will not support external flash #define EXAMPLE_FLASH_FREQ_MHZ 40 static const char *TAG = "example"; diff --git a/examples/storage/semihost_vfs/README.md b/examples/storage/semihost_vfs/README.md index bfd840dc3d..28c5b3a42d 100644 --- a/examples/storage/semihost_vfs/README.md +++ b/examples/storage/semihost_vfs/README.md @@ -73,7 +73,7 @@ openocd -c "set ESP_SEMIHOST_BASEDIR %IDF_PATH%/examples/storage/semihost_vfs/da The above command will set `ESP_SEMIHOST_BASEDIR` variable to `examples/storage/semihost_vfs/data` subdirectory of ESP-IDF. With that, it is not necessary to run OpenOCD from that specific directory. -> Note: This feature is not available for RISC-V based SoCs (ESP32-C3, ESP32-H4). To set the semihosting base directory, change into the required directory before running `openocd` command. +> Note: This feature is not available for RISC-V based SoCs (ESP32-C3, ESP32-H2). To set the semihosting base directory, change into the required directory before running `openocd` command. ## Example output diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index 5e1cdbb36b..d410ea169c 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -60,11 +60,9 @@ menu "Example Configuration" config EXAMPLE_GPIO_WAKEUP_PIN int "Enable wakeup from GPIO" - default 0 if !IDF_TARGET_ESP32H4_BETA_VERSION_2 - default 7 if IDF_TARGET_ESP32H4_BETA_VERSION_2 + default 0 range 0 7 if IDF_TARGET_ESP32C6 - range 0 5 if !IDF_TARGET_ESP32H4_BETA_VERSION_2 - range 7 12 if IDF_TARGET_ESP32H4_BETA_VERSION_2 + range 0 5 config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL bool "Enable GPIO high-level wakeup" diff --git a/examples/system/esp_timer/sdkconfig.ci.rtc b/examples/system/esp_timer/sdkconfig.ci.rtc index f0f3c7eae2..0b0237ec75 100644 --- a/examples/system/esp_timer/sdkconfig.ci.rtc +++ b/examples/system/esp_timer/sdkconfig.ci.rtc @@ -7,4 +7,3 @@ CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC=y CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC=y CONFIG_ESP32C2_TIME_SYSCALL_USE_RTC=y CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC=y -CONFIG_ESP32H4_TIME_SYSCALL_USE_RTC=y diff --git a/examples/system/gcov/main/Kconfig.projbuild b/examples/system/gcov/main/Kconfig.projbuild index 8b3d5d4d8a..bd13a5eb16 100644 --- a/examples/system/gcov/main/Kconfig.projbuild +++ b/examples/system/gcov/main/Kconfig.projbuild @@ -5,7 +5,7 @@ menu "Example Configuration" config BLINK_GPIO int "Blink GPIO number" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 8 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32C2 + default 8 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 default 18 if IDF_TARGET_ESP32S2 default 48 if IDF_TARGET_ESP32S3 default 5 diff --git a/examples/system/light_sleep/main/gpio_wakeup.c b/examples/system/light_sleep/main/gpio_wakeup.c index d60ec0e380..1ed997b091 100644 --- a/examples/system/light_sleep/main/gpio_wakeup.c +++ b/examples/system/light_sleep/main/gpio_wakeup.c @@ -12,7 +12,7 @@ /* Most development boards have "boot" button attached to GPIO0. * You can also change this to another pin. */ -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 \ +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 \ || CONFIG_IDF_TARGET_ESP32C6 #define BOOT_BUTTON_NUM 9 #else diff --git a/examples/zigbee/light_sample/README.md b/examples/zigbee/light_sample/README.md index 4534f278f4..2ef76b5b03 100644 --- a/examples/zigbee/light_sample/README.md +++ b/examples/zigbee/light_sample/README.md @@ -6,7 +6,7 @@ The folder contains examples demonstrating Zigbee Coordinator and End-Device roles -* [HA_on_off_light](HA_on_off_light) is a standard HA on-off light bulb example demonstrating Zigbee End-device. It provides a simple on/off condition for a Zigbee light. It runs on an 802.15.4 SoC like ESP32-H4. For more details see the example readme file. +* [HA_on_off_light](HA_on_off_light) is a standard HA on-off light bulb example demonstrating Zigbee End-device. It provides a simple on/off condition for a Zigbee light. It runs on an 802.15.4 SoC like ESP32-H2. For more details see the example readme file. -* [HA_on_off_switch](HA_on_off_switch) is a standard HA on-off switch example demonstrating Zigbee Coordinator role. It provides an on/off toggle to control a Zigbee HA on off light. It runs on an 802.15.4 SoC like ESP32-H4. For more details to see the example readme file. +* [HA_on_off_switch](HA_on_off_switch) is a standard HA on-off switch example demonstrating Zigbee Coordinator role. It provides an on/off toggle to control a Zigbee HA on off light. It runs on an 802.15.4 SoC like ESP32-H2. For more details to see the example readme file. diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index b2a06e8e5a..25cbc39b67 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -106,7 +106,6 @@ components/esp_rom/include/esp32/rom/rtc.h components/esp_rom/include/esp32c3/rom/rtc.h components/esp_rom/include/esp32s2/rom/rtc.h components/esp_rom/include/esp32s3/rom/rtc.h -components/esp_rom/include/esp32h4/rom/rtc.h components/esp_rom/include/esp32c2/rom/rtc.h components/esp_rom/include/esp32c6/rom/rtc.h components/esp_rom/include/esp32h2/rom/rtc.h diff --git a/tools/ci/python_packages/ttfw_idf/IDFDUT.py b/tools/ci/python_packages/ttfw_idf/IDFDUT.py index 4653331ba9..49ae306f6f 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFDUT.py +++ b/tools/ci/python_packages/ttfw_idf/IDFDUT.py @@ -640,15 +640,6 @@ class ESP32H2DUT(IDFDUT): return targets.ESP32H2ROM -class ESP32H4DUT(IDFDUT): - TARGET = 'esp32h4' - TOOLCHAIN_PREFIX = 'riscv32-esp-elf-' - - @classmethod - def get_rom(cls): - return targets.ESP32H4ROM - - class ESP8266DUT(IDFDUT): TARGET = 'esp8266' TOOLCHAIN_PREFIX = 'xtensa-lx106-elf-' @@ -659,7 +650,7 @@ class ESP8266DUT(IDFDUT): def get_target_by_rom_class(cls): - for c in [ESP32DUT, ESP32S2DUT, ESP32S3DUT, ESP32C2DUT, ESP32C3DUT, ESP32C6DUT, ESP32H2DUT, ESP32H4DUT, ESP8266DUT, IDFQEMUDUT]: + for c in [ESP32DUT, ESP32S2DUT, ESP32S3DUT, ESP32C2DUT, ESP32C3DUT, ESP32C6DUT, ESP32H2DUT, ESP8266DUT, IDFQEMUDUT]: if c.get_rom() == cls: return c.TARGET return None diff --git a/tools/ci/python_packages/ttfw_idf/__init__.py b/tools/ci/python_packages/ttfw_idf/__init__.py index 8e48f4ad64..b3a3eac068 100644 --- a/tools/ci/python_packages/ttfw_idf/__init__.py +++ b/tools/ci/python_packages/ttfw_idf/__init__.py @@ -14,7 +14,7 @@ from tiny_test_fw import TinyFW, Utility from .IDFApp import UT, ComponentUTApp, Example, IDFApp, LoadableElfTestApp, TestApp # noqa: export all Apps for users from .IDFDUT import (ESP32C2DUT, ESP32C3DUT, ESP32C3FPGADUT, ESP32C6DUT, ESP32DUT, # noqa: export DUTs for users - ESP32H2DUT, ESP32H4DUT, ESP32QEMUDUT, ESP32S2DUT, ESP32S3DUT, ESP32S3FPGADUT, ESP8266DUT, IDFDUT) + ESP32H2DUT, ESP32QEMUDUT, ESP32S2DUT, ESP32S3DUT, ESP32S3FPGADUT, ESP8266DUT, IDFDUT) from .unity_test_parser import TestFormat, TestResults # pass TARGET_DUT_CLS_DICT to Env.py to avoid circular dependency issue. @@ -27,7 +27,6 @@ TARGET_DUT_CLS_DICT = { 'ESP32C3FPGA': ESP32C3FPGADUT, 'ESP32S3FPGA': ESP32S3FPGADUT, 'ESP32C6': ESP32C6DUT, - 'ESP32H4': ESP32H4DUT, 'ESP32H2': ESP32H2DUT, } diff --git a/tools/cmake/dfu.cmake b/tools/cmake/dfu.cmake index 677d1c16f1..f1ecd940e9 100644 --- a/tools/cmake/dfu.cmake +++ b/tools/cmake/dfu.cmake @@ -11,8 +11,6 @@ function(__add_dfu_targets) set(dfu_pid "9") elseif("${target}" STREQUAL "esp32c3") return() - elseif("${target}" STREQUAL "esp32h4") - return() elseif("${target}" STREQUAL "esp32c2") return() elseif("${target}" STREQUAL "esp32c6") diff --git a/tools/cmake/uf2.cmake b/tools/cmake/uf2.cmake index aa00d5df3c..4e80d8decf 100644 --- a/tools/cmake/uf2.cmake +++ b/tools/cmake/uf2.cmake @@ -12,8 +12,6 @@ function(__add_uf2_targets) set(uf2_family_id "0xc47e5767") elseif("${target}" STREQUAL "esp32h2") set(uf2_family_id "0x332726f6") - elseif("${target}" STREQUAL "esp32h4") - return() elseif("${target}" STREQUAL "esp32c2") set(uf2_family_id "0x2b88d29c") elseif("${target}" STREQUAL "esp32c6") # TODO: IDF-5626 diff --git a/tools/gdb_panic_server.py b/tools/gdb_panic_server.py index 4b5edf26ea..fc429dbe8d 100644 --- a/tools/gdb_panic_server.py +++ b/tools/gdb_panic_server.py @@ -59,7 +59,6 @@ GDB_REGS_INFO_RISCV_ILP32 = [ GDB_REGS_INFO = { 'esp32c3': GDB_REGS_INFO_RISCV_ILP32, 'esp32c2': GDB_REGS_INFO_RISCV_ILP32, - 'esp32h4': GDB_REGS_INFO_RISCV_ILP32, 'esp32c6': GDB_REGS_INFO_RISCV_ILP32, 'esp32h2': GDB_REGS_INFO_RISCV_ILP32 } @@ -155,7 +154,6 @@ def parse_idf_riscv_panic_output(panic_text): # type: (str) -> PanicInfo PANIC_OUTPUT_PARSERS = { 'esp32c3': parse_idf_riscv_panic_output, 'esp32c2': parse_idf_riscv_panic_output, - 'esp32h4': parse_idf_riscv_panic_output, 'esp32c6': parse_idf_riscv_panic_output, 'esp32h2': parse_idf_riscv_panic_output } diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py index 46344fbdb7..ebb7a789f6 100644 --- a/tools/idf_py_actions/constants.py +++ b/tools/idf_py_actions/constants.py @@ -33,7 +33,7 @@ if os.name != 'nt': URL_TO_DOC = 'https://docs.espressif.com/projects/esp-idf' SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2'] -PREVIEW_TARGETS = ['linux', 'esp32h4'] +PREVIEW_TARGETS = ['linux'] OPENOCD_TAGET_CONFIG_DEFAULT = '-f interface/ftdi/esp32_devkitj_v1.cfg -f target/{target}.cfg' OPENOCD_TAGET_CONFIG: Dict[str, str] = { diff --git a/tools/test_apps/system/eh_frame/README.md b/tools/test_apps/system/eh_frame/README.md index ac429be8bd..59a65262c1 100644 --- a/tools/test_apps/system/eh_frame/README.md +++ b/tools/test_apps/system/eh_frame/README.md @@ -10,7 +10,7 @@ Thus, as soon as this example compiles we can considered it passed. However, it In order to build and run the example, use the following commands: ``` -idf.py set-target +idf.py set-target idf.py build idf.py flash monitor ``` From 49f16eefbb3ffe5c51c2d38ffb24ea13b540b850 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 13 Apr 2023 17:06:40 +0800 Subject: [PATCH 3/5] esp32h4: checked all the corner stuffs of the removal --- components/app_update/include/esp_ota_ops.h | 2 +- .../bootloader_support/include/esp_app_format.h | 1 + .../test_apps/spi/master/main/test_spi_bus_lock.c | 1 - components/esp_system/Kconfig | 2 +- components/esp_system/crosscore_int.c | 8 ++++---- .../esp_system_unity_tests/main/test_reset_reason.c | 2 +- components/esp_wifi/Kconfig | 2 ++ components/freertos/Kconfig | 2 +- components/ieee802154/CMakeLists.txt | 13 +------------ docs/en/api-guides/openthread.rst | 4 ++-- docs/en/api-reference/peripherals/ledc.rst | 2 +- docs/zh_CN/api-reference/peripherals/ledc.rst | 2 +- .../ble/ble_throughput/throughput_server/README.md | 2 +- .../components/ethernet_init/Kconfig.projbuild | 9 ++++++++- examples/ethernet/enc28j60/main/Kconfig.projbuild | 5 +++++ .../i2s/i2s_codec/i2s_es8311/main/example_config.h | 6 +++--- examples/system/deep_sleep/main/Kconfig.projbuild | 6 ++++-- examples/system/gcov/main/Kconfig.projbuild | 2 +- examples/system/light_sleep/main/gpio_wakeup.c | 2 +- tools/ci/check_build_test_rules.py | 2 -- 20 files changed, 39 insertions(+), 36 deletions(-) diff --git a/components/app_update/include/esp_ota_ops.h b/components/app_update/include/esp_ota_ops.h index 86f7ceca02..1364b543a8 100644 --- a/components/app_update/include/esp_ota_ops.h +++ b/components/app_update/include/esp_ota_ops.h @@ -334,7 +334,7 @@ typedef enum { /** * @brief Revokes the old signature digest. To be called in the application after the rollback logic. * - * Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1). + * Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6, ESP32-H2 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1). * When key \#N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key \#N-1 & Key \#N. * After successfully booting the OTA app should call this function to revoke Key \#N-1. * diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 242d243cf1..14c3917181 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -17,6 +17,7 @@ typedef enum { ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */ ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */ ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */ + ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */ ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c b/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c index ba3f5bfc1c..3a513cc7e4 100644 --- a/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c +++ b/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c @@ -33,7 +33,6 @@ #endif -// H2 and C2 will not support external flash. #define TEST_FLASH_FREQ_MHZ 5 typedef struct { diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index 3205775cbd..3006f40b60 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -279,7 +279,7 @@ menu "ESP System Settings" config ESP_CONSOLE_MULTIPLE_UART bool - default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 + default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 choice ESP_CONSOLE_UART_NUM prompt "UART peripheral to use for console output (0-1)" diff --git a/components/esp_system/crosscore_int.c b/components/esp_system/crosscore_int.c index d9102a16ed..03e0fa650f 100644 --- a/components/esp_system/crosscore_int.c +++ b/components/esp_system/crosscore_int.c @@ -29,7 +29,7 @@ #define REASON_FREQ_SWITCH BIT(1) #define REASON_GDB_CALL BIT(3) -#if !CONFIG_IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ARCH_XTENSA #define REASON_PRINT_BACKTRACE BIT(2) #define REASON_TWDT_ABORT BIT(4) #endif @@ -66,7 +66,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) { } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0); } -#elif CONFIG_IDF_TARGET_ESP32C3|| CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ARCH_RISCV WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); #endif @@ -147,7 +147,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ARCH_RISCV WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); #endif } @@ -167,7 +167,7 @@ void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id) esp_crosscore_int_send(core_id, REASON_GDB_CALL); } -#if !CONFIG_IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 +#if CONFIG_IDF_TARGET_ARCH_XTENSA void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id) { esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE); diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c index e28134f7c8..f040254069 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c @@ -43,7 +43,7 @@ #define BROWNOUT "BROWN_OUT_RST" #define STORE_ERROR "StoreProhibited" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 #define DEEPSLEEP "DSLEEP" #define LOAD_STORE_ERROR "Store access fault" #define RESET "RTC_SW_CPU_RST" diff --git a/components/esp_wifi/Kconfig b/components/esp_wifi/Kconfig index 7e528b4ed0..bc42da9f2d 100644 --- a/components/esp_wifi/Kconfig +++ b/components/esp_wifi/Kconfig @@ -1,5 +1,7 @@ menu "Wi-Fi" + # TODO: Disable WIFI support on ESP32-H2 (WIFI-5796) + # visible if SOC_WIFI_SUPPORTED config ESP_WIFI_ENABLED bool diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig index 28c8be4d00..4ff819a91c 100644 --- a/components/freertos/Kconfig +++ b/components/freertos/Kconfig @@ -366,7 +366,7 @@ menu "FreeRTOS" config FREERTOS_TICK_SUPPORT_SYSTIMER bool default y if !FREERTOS_TICK_SUPPORT_CORETIMER - # ESP32-S3 and ESP32-C3 can use Systimer for FreeRTOS SysTick + # All targets except ESP32 and ESP32S2 can use Systimer for FreeRTOS SysTick # ESP32S2 also has SYSTIMER but it can not be used for the FreeRTOS SysTick because: # - It has only one counter, which already in use esp_timer. # A counter for SysTick should be stall in debug mode but work esp_timer. diff --git a/components/ieee802154/CMakeLists.txt b/components/ieee802154/CMakeLists.txt index 4826838b6e..55a1ec7b09 100644 --- a/components/ieee802154/CMakeLists.txt +++ b/components/ieee802154/CMakeLists.txt @@ -13,18 +13,7 @@ if(CONFIG_IEEE802154_ENABLED) target_link_libraries(${COMPONENT_LIB} INTERFACE $ $ libphy.a libbtbb.a $) else() - if(IDF_TARGET STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - target_link_libraries(${COMPONENT_LIB} INTERFACE - "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}/rev1") - endif() - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - target_link_libraries(${COMPONENT_LIB} INTERFACE - "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}/rev2") - endif() - else() - target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}") - endif() + target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}") target_link_libraries(${COMPONENT_LIB} INTERFACE $ lib802154.a libphy.a libbtbb.a $ $) endif() diff --git a/docs/en/api-guides/openthread.rst b/docs/en/api-guides/openthread.rst index 4b0d5b354c..ceb12fc463 100644 --- a/docs/en/api-guides/openthread.rst +++ b/docs/en/api-guides/openthread.rst @@ -11,12 +11,12 @@ OpenThread can run under the following modes on Espressif chips: Standalone node +++++++++++++++ -The full OpenThread stack and the application layer runs on the same chip. This mode is available on chips with 15.4 radio such as ESP32-H2. +The full OpenThread stack and the application layer runs on the same chip. This mode is available on chips with 15.4 radio such as {IDF_TARGET}. Radio Co-Processor (RCP) ++++++++++++++++++++++++ -The chip will be connected to another host running the OpenThread IP stack. It will send and received 15.4 packets on behalf of the host. This mode is available on chips with 15.4 radio such as ESP32-H2. The underlying transport between the chip and the host can be SPI or UART. For sake of latency, we recommend to use SPI as the underlying transport. +The chip will be connected to another host running the OpenThread IP stack. It will send and received 15.4 packets on behalf of the host. This mode is available on chips with 15.4 radio such as {IDF_TARGET}. The underlying transport between the chip and the host can be SPI or UART. For sake of latency, we recommend to use SPI as the underlying transport. OpenThread host +++++++++++++++ diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index dde1cc45d3..7aba0a1ad4 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -201,7 +201,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f .. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX - 1. For {IDF_TARGET_NAME}, all timers share one clock source. In other words, it is impossible to use different clock sources for different timers. + 2. For {IDF_TARGET_NAME}, all timers share one clock source. In other words, it is impossible to use different clock sources for different timers. When a timer is no longer needed by any channel, it can be deconfigured by calling the same function :cpp:func:`ledc_timer_config`. The configuration structure :cpp:type:`ledc_timer_config_t` passes in should be: diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 9011630ff1..09c45d2024 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -201,7 +201,7 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 .. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX - 1. {IDF_TARGET_NAME} 的所有定时器共用一个时钟源。因此 {IDF_TARGET_NAME} 不支持给不同的定时器配置不同的时钟源。 + 2. {IDF_TARGET_NAME} 的所有定时器共用一个时钟源。因此 {IDF_TARGET_NAME} 不支持给不同的定时器配置不同的时钟源。 当一个定时器不再被任何通道所需要时，可以通过调用相同的函数 :cpp:func:`ledc_timer_config` 来重置这个定时器。此时，函数入参的配置结构体需要指定： diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md index 287aa57a70..4bd56e2fea 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md @@ -26,7 +26,7 @@ please set: `idf.py menuconfig --> Component config --> Example 'GATT CLIENT THR ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with supported SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild index ce79cb4e23..a3d7b9cf22 100644 --- a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild +++ b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild @@ -142,6 +142,7 @@ menu "Example Ethernet Configuration" default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 4 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI SCLK. @@ -151,6 +152,7 @@ menu "Example Ethernet Configuration" default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 5 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MOSI. @@ -160,13 +162,14 @@ menu "Example Ethernet Configuration" default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 0 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MISO. config EXAMPLE_ETH_SPI_CLOCK_MHZ int "SPI clock speed (MHz)" range 5 80 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 help Set the clock speed (MHz) of SPI interface. @@ -176,6 +179,7 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 + default 1 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI CS0, i.e. Chip Select associated with the first SPI Eth module). @@ -187,6 +191,7 @@ menu "Example Ethernet Configuration" default 7 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 8 if IDF_TARGET_ESP32C3 default 3 if IDF_TARGET_ESP32C2 + default 11 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI CS1, i.e. Chip Select associated with the second SPI Eth module. @@ -195,6 +200,7 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 + default 9 if IDF_TARGET_ESP32H2 help Set the GPIO number used by the first SPI Ethernet module interrupt line. @@ -204,6 +210,7 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 33 if IDF_TARGET_ESP32 default 5 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 + default 10 if IDF_TARGET_ESP32H2 help Set the GPIO number used by the second SPI Ethernet module interrupt line. diff --git a/examples/ethernet/enc28j60/main/Kconfig.projbuild b/examples/ethernet/enc28j60/main/Kconfig.projbuild index 60001d4ed1..c33f4b97e7 100644 --- a/examples/ethernet/enc28j60/main/Kconfig.projbuild +++ b/examples/ethernet/enc28j60/main/Kconfig.projbuild @@ -15,6 +15,7 @@ menu "Example Configuration" default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 4 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI SCLK. @@ -24,6 +25,7 @@ menu "Example Configuration" default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 5 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MOSI. @@ -33,6 +35,7 @@ menu "Example Configuration" default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 0 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MISO. @@ -41,6 +44,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 + default 1 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI CS. @@ -56,6 +60,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 + default 9 if IDF_TARGET_ESP32H2 help Set the GPIO number used by ENC28J60 interrupt. diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h index 73e49bebb4..72835af592 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h @@ -26,12 +26,12 @@ #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define I2C_SCL_IO (GPIO_NUM_16) #define I2C_SDA_IO (GPIO_NUM_17) -#elif CONFIG_IDF_TARGET_ESP32C3 -#define I2C_SCL_IO (GPIO_NUM_6) -#define I2C_SDA_IO (GPIO_NUM_7) #elif CONFIG_IDF_TARGET_ESP32H2 #define I2C_SCL_IO (GPIO_NUM_8) #define I2C_SDA_IO (GPIO_NUM_9) +#else +#define I2C_SCL_IO (GPIO_NUM_6) +#define I2C_SDA_IO (GPIO_NUM_7) #endif /* I2S port and GPIOs */ diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index d410ea169c..97793a8209 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -60,9 +60,11 @@ menu "Example Configuration" config EXAMPLE_GPIO_WAKEUP_PIN int "Enable wakeup from GPIO" - default 0 + default 0 if !IDF_TARGET_ESP32H2 + default 7 if IDF_TARGET_ESP32H2 range 0 7 if IDF_TARGET_ESP32C6 - range 0 5 + range 7 14 if IDF_TARGET_ESP32H2 + range 0 5 if !IDF_TARGET_ESP32C6 && !IDF_TARGET_ESP32H2 config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL bool "Enable GPIO high-level wakeup" diff --git a/examples/system/gcov/main/Kconfig.projbuild b/examples/system/gcov/main/Kconfig.projbuild index bd13a5eb16..a5ff55cf83 100644 --- a/examples/system/gcov/main/Kconfig.projbuild +++ b/examples/system/gcov/main/Kconfig.projbuild @@ -5,7 +5,7 @@ menu "Example Configuration" config BLINK_GPIO int "Blink GPIO number" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 8 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 + default 8 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C2 default 18 if IDF_TARGET_ESP32S2 default 48 if IDF_TARGET_ESP32S3 default 5 diff --git a/examples/system/light_sleep/main/gpio_wakeup.c b/examples/system/light_sleep/main/gpio_wakeup.c index 1ed997b091..a4e86386de 100644 --- a/examples/system/light_sleep/main/gpio_wakeup.c +++ b/examples/system/light_sleep/main/gpio_wakeup.c @@ -12,7 +12,7 @@ /* Most development boards have "boot" button attached to GPIO0. * You can also change this to another pin. */ -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 \ +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 \ || CONFIG_IDF_TARGET_ESP32C6 #define BOOT_BUTTON_NUM 9 #else diff --git a/tools/ci/check_build_test_rules.py b/tools/ci/check_build_test_rules.py index adf422b251..66fdceb298 100755 --- a/tools/ci/check_build_test_rules.py +++ b/tools/ci/check_build_test_rules.py @@ -32,7 +32,6 @@ USUAL_TO_FORMAL = { 'esp32c2': 'ESP32-C2', 'esp32c6': 'ESP32-C6', 'esp32h2': 'ESP32-H2', - 'esp32h4': 'ESP32-H4', 'linux': 'Linux', } @@ -44,7 +43,6 @@ FORMAL_TO_USUAL = { 'ESP32-C2': 'esp32c2', 'ESP32-C6': 'esp32c6', 'ESP32-H2': 'esp32h2', - 'ESP32-H4': 'esp32h4', 'Linux': 'linux', } From c05b9403f72411e2cda4cd608df27af35c42ff05 Mon Sep 17 00:00:00 2001 From: zhangwenxu Date: Wed, 19 Apr 2023 16:36:43 +0800 Subject: [PATCH 4/5] ieee802154: remove libieee802154.a for target esp32h4 --- components/ieee802154/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/ieee802154/lib b/components/ieee802154/lib index 54ceb75476..102b03c809 160000 --- a/components/ieee802154/lib +++ b/components/ieee802154/lib @@ -1 +1 @@ -Subproject commit 54ceb75476f7bdbb8a2557d2a8a012a9342e7a37 +Subproject commit 102b03c8095de8a337c293f79dce189be63186f3 From 1d101f67e446e22e3ec8d414d3e30a3f987e4638 Mon Sep 17 00:00:00 2001 From: zhangwenxu Date: Thu, 20 Apr 2023 10:59:27 +0800 Subject: [PATCH 5/5] esp_phy: remove esp32h4 phylib --- components/esp_phy/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 03c270c901..0e8bbc5b3e 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 03c270c901c1106931ea6299523928c64d457b91 +Subproject commit 0e8bbc5b3e9d8aa99b00a2eba5acfd29f5fd3a66