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feat(esp_hw_support): support cpu domain powered down during sleep for esp32c5

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This commit is contained in:
Lou Tianhao
2024-06-20 16:42:21 +08:00
parent 8d9b3cfb2f
commit 6c9ed891ee
5 changed files with 17 additions and 11 deletions
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2
components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/rvsleep-frames.h
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@@ -173,7 +173,7 @@ STRUCT_BEGIN
STRUCT_FIELD (long, 4, RV_SLP_CTX_MCYCLE, mcycle) STRUCT_FIELD (long, 4, RV_SLP_CTX_MCYCLE, mcycle)
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT, mtvt) STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT, mtvt)
STRUCT_FIELD (long, 4, RV_SLP_CTX_MNXTI, mnxti) STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh)
STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTSTATUS, mintstatus) STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTSTATUS, mintstatus)
STRUCT_FIELD (long, 4, RV_SLP_CTX_MXSTATUS, mxstatus) STRUCT_FIELD (long, 4, RV_SLP_CTX_MXSTATUS, mxstatus)
STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR, mhcr) STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR, mhcr)

17
components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c
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@@ -68,8 +68,7 @@ typedef struct {
static DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention; static DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention;
#define CUSTOM_CSR_MTVT (0x307) #define CUSTOM_CSR_MTVT (0x307)
#define CUSTOM_CSR_MNXTI (0x345) #define CUSTOM_CSR_MINTTHRESH (0x347)
#define CUSTOM_CSR_MINTSTATUS (0x346)
#define CUSTOM_CSR_MXSTATUS (0x7c0) #define CUSTOM_CSR_MXSTATUS (0x7c0)
#define CUSTOM_CSR_MHCR (0x7c1) #define CUSTOM_CSR_MHCR (0x7c1)
#define CUSTOM_CSR_MHINT (0x7c5) #define CUSTOM_CSR_MHINT (0x7c5)
@@ -104,8 +103,7 @@ static void * cpu_domain_dev_sleep_frame_alloc_and_init(const cpu_domain_dev_reg
static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void) static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void)
{ {
const static cpu_domain_dev_regs_region_t regions[] = { const static cpu_domain_dev_regs_region_t regions[] = {
{ .start = CACHE_L1_CACHE_CTRL_REG, .end = CACHE_L1_CACHE_CTRL_REG + 4 }, { .start = CACHE_L1_ICACHE_CTRL_REG, .end = CACHE_L1_BYPASS_CACHE_CONF_REG + 4 }
{ .start = CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG, .end = CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG + 4 }
}; };
return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
} }
@@ -113,7 +111,10 @@ static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void)
static inline void * cpu_domain_clint_sleep_frame_alloc_and_init(void) static inline void * cpu_domain_clint_sleep_frame_alloc_and_init(void)
{ {
const static cpu_domain_dev_regs_region_t regions[] = { const static cpu_domain_dev_regs_region_t regions[] = {
{ .start = CLINT_MINT_SIP_REG, .end = CLINT_MINT_MTIMECMP_H_REG + 4 }, { .start = CLINT_MINT_SIP_REG, .end = CLINT_MINT_SIP_REG + 4 },
{ .start = CLINT_MINT_MTIMECMP_L_REG, .end = CLINT_MINT_MTIMECMP_H_REG + 4 },
{ .start = CLINT_MINT_TIMECTL_REG, .end = CLINT_MINT_TIMECTL_REG + 4 },
{ .start = CLINT_MINT_MTIME_L_REG, .end = CLINT_MINT_MTIME_H_REG + 4 }
}; };
return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
} }
@@ -275,8 +276,7 @@ static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(voi
frame->mcycle = RV_READ_CSR(mcycle); frame->mcycle = RV_READ_CSR(mcycle);
frame->mtvt = RV_READ_CSR(CUSTOM_CSR_MTVT); frame->mtvt = RV_READ_CSR(CUSTOM_CSR_MTVT);
frame->mnxti = RV_READ_CSR(CUSTOM_CSR_MNXTI); frame->mintthresh = RV_READ_CSR(CUSTOM_CSR_MINTTHRESH);
frame->mintstatus = RV_READ_CSR(CUSTOM_CSR_MINTSTATUS);
frame->mxstatus = RV_READ_CSR(CUSTOM_CSR_MXSTATUS); frame->mxstatus = RV_READ_CSR(CUSTOM_CSR_MXSTATUS);
frame->mhcr = RV_READ_CSR(CUSTOM_CSR_MHCR); frame->mhcr = RV_READ_CSR(CUSTOM_CSR_MHCR);
frame->mhint = RV_READ_CSR(CUSTOM_CSR_MHINT); frame->mhint = RV_READ_CSR(CUSTOM_CSR_MHINT);
@@ -351,8 +351,7 @@ static IRAM_ATTR void rv_core_noncritical_regs_restore(RvCoreNonCriticalSleepFra
RV_WRITE_CSR(mcycle, frame->mcycle); RV_WRITE_CSR(mcycle, frame->mcycle);
RV_WRITE_CSR(CUSTOM_CSR_MTVT, frame->mtvt); RV_WRITE_CSR(CUSTOM_CSR_MTVT, frame->mtvt);
RV_WRITE_CSR(CUSTOM_CSR_MNXTI, frame->mnxti); RV_WRITE_CSR(CUSTOM_CSR_MINTTHRESH, frame->mintthresh);
RV_WRITE_CSR(CUSTOM_CSR_MINTSTATUS, frame->mintstatus);
RV_WRITE_CSR(CUSTOM_CSR_MXSTATUS, frame->mxstatus); RV_WRITE_CSR(CUSTOM_CSR_MXSTATUS, frame->mxstatus);
RV_WRITE_CSR(CUSTOM_CSR_MHCR, frame->mhcr); RV_WRITE_CSR(CUSTOM_CSR_MHCR, frame->mhcr);
RV_WRITE_CSR(CUSTOM_CSR_MHINT, frame->mhint); RV_WRITE_CSR(CUSTOM_CSR_MHINT, frame->mhint);

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -1179,6 +1179,10 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int int
default 12 default 12
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_MODEM_PD config SOC_PM_SUPPORT_MODEM_PD
bool bool
default y default y

2
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -538,7 +538,7 @@
// #define SOC_PM_SUPPORT_BT_WAKEUP (1) // #define SOC_PM_SUPPORT_BT_WAKEUP (1)
// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) // #define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */ // #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
// #define SOC_PM_SUPPORT_CPU_PD (1) #define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1) #define SOC_PM_SUPPORT_MODEM_PD (1)
#define SOC_PM_SUPPORT_XTAL32K_PD (1) #define SOC_PM_SUPPORT_XTAL32K_PD (1)
// #define SOC_PM_SUPPORT_RC32K_PD (1) // #define SOC_PM_SUPPORT_RC32K_PD (1)

3
examples/system/README.md
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@@ -1,3 +1,6 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# System Examples # System Examples
Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates), deep sleep logging, and event loops. Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates), deep sleep logging, and event loops.