forked from espressif/esp-idf
refactor(freertos): Refactor usage of portBASE_TYPE to BaseType_t
portBASE_TYPE is an internal macro defined by the porting layer. This commit changes all references to BaseType_t which is the official type exposed by FreeRTOS.
This commit is contained in:
@@ -367,7 +367,7 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg)
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static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx)
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static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx)
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{
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{
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portBASE_TYPE taskAwoken = 0;
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BaseType_t taskAwoken = 0;
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BaseType_t ret;
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BaseType_t ret;
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adc_hal_dma_desc_status_t status = false;
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adc_hal_dma_desc_status_t status = false;
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uint8_t *finished_buffer = NULL;
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uint8_t *finished_buffer = NULL;
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -159,8 +159,8 @@ __attribute__((weak)) esp_err_t i2s_platform_release_occupation(int id);
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static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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{
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i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
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i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
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portBASE_TYPE need_awoke = 0;
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BaseType_t need_awoke = 0;
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portBASE_TYPE tmp = 0;
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BaseType_t tmp = 0;
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int dummy;
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int dummy;
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i2s_event_t i2s_event;
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i2s_event_t i2s_event;
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uint32_t finish_desc;
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uint32_t finish_desc;
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@@ -191,8 +191,8 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
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static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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{
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i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
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i2s_obj_t *p_i2s = (i2s_obj_t *) user_data;
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portBASE_TYPE need_awoke = 0;
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BaseType_t need_awoke = 0;
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portBASE_TYPE tmp = 0;
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BaseType_t tmp = 0;
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int dummy;
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int dummy;
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i2s_event_t i2s_event;
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i2s_event_t i2s_event;
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uint32_t finish_desc;
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uint32_t finish_desc;
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@@ -235,8 +235,8 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
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i2s_event_t i2s_event;
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i2s_event_t i2s_event;
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int dummy;
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int dummy;
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portBASE_TYPE need_awoke = 0;
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BaseType_t need_awoke = 0;
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portBASE_TYPE tmp = 0;
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BaseType_t tmp = 0;
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uint32_t finish_desc = 0;
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uint32_t finish_desc = 0;
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if ((status & I2S_LL_EVENT_TX_DSCR_ERR) || (status & I2S_LL_EVENT_RX_DSCR_ERR)) {
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if ((status & I2S_LL_EVENT_TX_DSCR_ERR) || (status & I2S_LL_EVENT_RX_DSCR_ERR)) {
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ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08x", status);
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ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08x", status);
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@@ -719,7 +719,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg)
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rmt_item32_t *addr = NULL;
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rmt_item32_t *addr = NULL;
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uint8_t channel = 0;
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uint8_t channel = 0;
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rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
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rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
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portBASE_TYPE HPTaskAwoken = pdFALSE;
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BaseType_t HPTaskAwoken = pdFALSE;
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// Tx end interrupt
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// Tx end interrupt
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status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
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status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -229,7 +229,7 @@ static i2c_clk_alloc_t i2c_clk_alloc[] = {
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static i2c_obj_t *p_i2c_obj[I2C_NUM_MAX] = {0};
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static i2c_obj_t *p_i2c_obj[I2C_NUM_MAX] = {0};
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static void i2c_isr_handler_default(void *arg);
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static void i2c_isr_handler_default(void *arg);
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static void i2c_master_cmd_begin_static(i2c_port_t i2c_num, portBASE_TYPE* HPTaskAwoken);
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static void i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t* HPTaskAwoken);
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static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num);
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static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num);
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static void i2c_hw_disable(i2c_port_t i2c_num)
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static void i2c_hw_disable(i2c_port_t i2c_num)
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@@ -536,8 +536,8 @@ static void IRAM_ATTR i2c_isr_handler_default(void *arg)
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return;
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return;
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}
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}
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i2c_intr_event_t evt_type = I2C_INTR_EVENT_ERR;
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i2c_intr_event_t evt_type = I2C_INTR_EVENT_ERR;
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portBASE_TYPE HPTaskAwoken = pdFALSE;
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BaseType_t HPTaskAwoken = pdFALSE;
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portBASE_TYPE HPTaskAwokenCallee = pdFALSE;
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BaseType_t HPTaskAwokenCallee = pdFALSE;
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if (p_i2c->mode == I2C_MODE_MASTER) {
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if (p_i2c->mode == I2C_MODE_MASTER) {
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if (p_i2c->status == I2C_STATUS_WRITE) {
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if (p_i2c->status == I2C_STATUS_WRITE) {
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i2c_hal_master_handle_tx_event(&(i2c_context[i2c_num].hal), &evt_type);
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i2c_hal_master_handle_tx_event(&(i2c_context[i2c_num].hal), &evt_type);
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@@ -1357,7 +1357,7 @@ static inline bool i2c_cmd_is_single_byte(const i2c_cmd_t *cmd) {
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return cmd->total_bytes == 1;
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return cmd->total_bytes == 1;
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}
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}
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static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, portBASE_TYPE* HPTaskAwoken)
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static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t* HPTaskAwoken)
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{
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{
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i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
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i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
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i2c_cmd_evt_t evt = { 0 };
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i2c_cmd_evt_t evt = { 0 };
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@@ -1504,7 +1504,7 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
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esp_err_t ret = ESP_FAIL;
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esp_err_t ret = ESP_FAIL;
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i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
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i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
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TickType_t ticks_start = xTaskGetTickCount();
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TickType_t ticks_start = xTaskGetTickCount();
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portBASE_TYPE res = xSemaphoreTake(p_i2c->cmd_mux, ticks_to_wait);
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BaseType_t res = xSemaphoreTake(p_i2c->cmd_mux, ticks_to_wait);
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if (res == pdFALSE) {
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if (res == pdFALSE) {
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return ESP_ERR_TIMEOUT;
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return ESP_ERR_TIMEOUT;
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}
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}
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@@ -1554,7 +1554,7 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
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// In master mode, since we don't have an interrupt to detective bus error or FSM state, what we do here is to make
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// In master mode, since we don't have an interrupt to detective bus error or FSM state, what we do here is to make
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// sure the interrupt mechanism for master mode is still working.
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// sure the interrupt mechanism for master mode is still working.
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// If the command sending is not finished and there is no interrupt any more, the bus is probably dead caused by external noise.
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// If the command sending is not finished and there is no interrupt any more, the bus is probably dead caused by external noise.
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portBASE_TYPE evt_res = xQueueReceive(p_i2c->cmd_evt_queue, &evt, wait_time);
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BaseType_t evt_res = xQueueReceive(p_i2c->cmd_evt_queue, &evt, wait_time);
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if (evt_res == pdTRUE) {
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if (evt_res == pdTRUE) {
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if (evt.type == I2C_CMD_EVT_DONE) {
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if (evt.type == I2C_CMD_EVT_DONE) {
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if (p_i2c->status == I2C_STATUS_TIMEOUT) {
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if (p_i2c->status == I2C_STATUS_TIMEOUT) {
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@@ -1602,7 +1602,7 @@ int i2c_slave_write_buffer(i2c_port_t i2c_num, const uint8_t *data, int size, Ti
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ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num]->mode == I2C_MODE_SLAVE, ESP_FAIL, I2C_TAG, I2C_MODE_SLAVE_ERR_STR);
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ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num]->mode == I2C_MODE_SLAVE, ESP_FAIL, I2C_TAG, I2C_MODE_SLAVE_ERR_STR);
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i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
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i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
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portBASE_TYPE res;
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BaseType_t res;
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int cnt = 0;
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int cnt = 0;
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TickType_t ticks_end = xTaskGetTickCount() + ticks_to_wait;
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TickType_t ticks_end = xTaskGetTickCount() + ticks_to_wait;
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -504,9 +504,9 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
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static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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{
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i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
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i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
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portBASE_TYPE need_yield1 = 0;
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BaseType_t need_yield1 = 0;
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portBASE_TYPE need_yield2 = 0;
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BaseType_t need_yield2 = 0;
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portBASE_TYPE user_need_yield = 0;
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BaseType_t user_need_yield = 0;
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lldesc_t *finish_desc;
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lldesc_t *finish_desc;
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uint32_t dummy;
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uint32_t dummy;
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@@ -533,9 +533,9 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
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static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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{
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i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
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i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
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portBASE_TYPE need_yield1 = 0;
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BaseType_t need_yield1 = 0;
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portBASE_TYPE need_yield2 = 0;
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BaseType_t need_yield2 = 0;
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portBASE_TYPE user_need_yield = 0;
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BaseType_t user_need_yield = 0;
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lldesc_t *finish_desc;
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lldesc_t *finish_desc;
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uint32_t dummy;
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uint32_t dummy;
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@@ -567,9 +567,9 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
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static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
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static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
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{
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{
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portBASE_TYPE need_yield1 = 0;
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BaseType_t need_yield1 = 0;
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portBASE_TYPE need_yield2 = 0;
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BaseType_t need_yield2 = 0;
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portBASE_TYPE user_need_yield = 0;
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BaseType_t user_need_yield = 0;
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lldesc_t *finish_desc = NULL;
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lldesc_t *finish_desc = NULL;
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i2s_event_data_t evt;
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i2s_event_data_t evt;
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i2s_chan_handle_t handle = (i2s_chan_handle_t)arg;
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i2s_chan_handle_t handle = (i2s_chan_handle_t)arg;
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@@ -605,9 +605,9 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
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static void IRAM_ATTR i2s_dma_tx_callback(void *arg)
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static void IRAM_ATTR i2s_dma_tx_callback(void *arg)
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{
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{
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portBASE_TYPE need_yield1 = 0;
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BaseType_t need_yield1 = 0;
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portBASE_TYPE need_yield2 = 0;
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BaseType_t need_yield2 = 0;
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portBASE_TYPE user_need_yield = 0;
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BaseType_t user_need_yield = 0;
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lldesc_t *finish_desc = NULL;
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lldesc_t *finish_desc = NULL;
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i2s_event_data_t evt;
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i2s_event_data_t evt;
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i2s_chan_handle_t handle = (i2s_chan_handle_t)arg;
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i2s_chan_handle_t handle = (i2s_chan_handle_t)arg;
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@@ -862,7 +862,7 @@ static inline void IRAM_ATTR ledc_calc_fade_end_channel(uint32_t *fade_end_statu
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void IRAM_ATTR ledc_fade_isr(void *arg)
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void IRAM_ATTR ledc_fade_isr(void *arg)
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{
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{
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bool cb_yield = false;
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bool cb_yield = false;
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portBASE_TYPE HPTaskAwoken = pdFALSE;
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BaseType_t HPTaskAwoken = pdFALSE;
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uint32_t speed_mode = 0;
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uint32_t speed_mode = 0;
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uint32_t channel = 0;
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uint32_t channel = 0;
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uint32_t intr_status = 0;
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uint32_t intr_status = 0;
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -455,7 +455,7 @@ static void sdio_intr_host(void *arg)
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{
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{
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sdio_slave_ll_slvint_t int_val;
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sdio_slave_ll_slvint_t int_val;
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sdio_slave_hal_slvint_fetch_clear(context.hal, &int_val);
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sdio_slave_hal_slvint_fetch_clear(context.hal, &int_val);
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portBASE_TYPE yield = pdFALSE;
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BaseType_t yield = pdFALSE;
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for (int i = 0; i < 8; i++) {
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for (int i = 0; i < 8; i++) {
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if (BIT(i) & int_val) {
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if (BIT(i) & int_val) {
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if (context.config.event_cb != NULL) {
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if (context.config.event_cb != NULL) {
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@@ -545,14 +545,14 @@ esp_err_t sdio_slave_send_host_int(uint8_t pos)
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static void sdio_intr_send(void *arg)
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static void sdio_intr_send(void *arg)
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{
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{
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ESP_EARLY_LOGV(TAG, "intr_send");
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ESP_EARLY_LOGV(TAG, "intr_send");
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portBASE_TYPE yield = pdFALSE;
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BaseType_t yield = pdFALSE;
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// this interrupt is abused to get ISR invoked by app
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// this interrupt is abused to get ISR invoked by app
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sdio_slave_hal_send_handle_isr_invoke(context.hal);
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sdio_slave_hal_send_handle_isr_invoke(context.hal);
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uint32_t returned_cnt;
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uint32_t returned_cnt;
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if (sdio_slave_hal_send_eof_happened(context.hal)) {
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if (sdio_slave_hal_send_eof_happened(context.hal)) {
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portBASE_TYPE ret __attribute__((unused));
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BaseType_t ret __attribute__((unused));
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esp_err_t err;
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esp_err_t err;
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while (1) {
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while (1) {
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@@ -587,7 +587,7 @@ esp_err_t sdio_slave_send_queue(uint8_t *addr, size_t len, void *arg, TickType_t
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SDIO_SLAVE_CHECK(esp_ptr_dma_capable(addr) && (uint32_t)addr % 4 == 0, "buffer to send should be DMA capable and 32-bit aligned",
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SDIO_SLAVE_CHECK(esp_ptr_dma_capable(addr) && (uint32_t)addr % 4 == 0, "buffer to send should be DMA capable and 32-bit aligned",
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ESP_ERR_INVALID_ARG);
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ESP_ERR_INVALID_ARG);
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portBASE_TYPE cnt_ret = xSemaphoreTake(context.remain_cnt, wait);
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BaseType_t cnt_ret = xSemaphoreTake(context.remain_cnt, wait);
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if (cnt_ret != pdTRUE) {
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if (cnt_ret != pdTRUE) {
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return ESP_ERR_TIMEOUT;
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return ESP_ERR_TIMEOUT;
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}
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}
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@@ -605,7 +605,7 @@ esp_err_t sdio_slave_send_queue(uint8_t *addr, size_t len, void *arg, TickType_t
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|||||||
esp_err_t sdio_slave_send_get_finished(void **out_arg, TickType_t wait)
|
esp_err_t sdio_slave_send_get_finished(void **out_arg, TickType_t wait)
|
||||||
{
|
{
|
||||||
void *arg = NULL;
|
void *arg = NULL;
|
||||||
portBASE_TYPE err = xQueueReceive(context.ret_queue, &arg, wait);
|
BaseType_t err = xQueueReceive(context.ret_queue, &arg, wait);
|
||||||
if (out_arg) {
|
if (out_arg) {
|
||||||
*out_arg = arg;
|
*out_arg = arg;
|
||||||
}
|
}
|
||||||
@@ -637,7 +637,7 @@ esp_err_t sdio_slave_transmit(uint8_t *addr, size_t len)
|
|||||||
static esp_err_t send_flush_data(void)
|
static esp_err_t send_flush_data(void)
|
||||||
{
|
{
|
||||||
esp_err_t err;
|
esp_err_t err;
|
||||||
portBASE_TYPE ret __attribute__((unused));
|
BaseType_t ret __attribute__((unused));
|
||||||
|
|
||||||
while (1) {
|
while (1) {
|
||||||
void *finished_arg;
|
void *finished_arg;
|
||||||
@@ -684,7 +684,7 @@ static inline void critical_exit_recv(void)
|
|||||||
static esp_err_t recv_flush_data(void)
|
static esp_err_t recv_flush_data(void)
|
||||||
{
|
{
|
||||||
while (1) {
|
while (1) {
|
||||||
portBASE_TYPE ret = xSemaphoreTake(context.recv_event, 0);
|
BaseType_t ret = xSemaphoreTake(context.recv_event, 0);
|
||||||
if (ret == pdFALSE) {
|
if (ret == pdFALSE) {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@@ -697,7 +697,7 @@ static esp_err_t recv_flush_data(void)
|
|||||||
|
|
||||||
static void sdio_intr_recv(void *arg)
|
static void sdio_intr_recv(void *arg)
|
||||||
{
|
{
|
||||||
portBASE_TYPE yield = 0;
|
BaseType_t yield = 0;
|
||||||
bool triggered = sdio_slave_hal_recv_done(context.hal);
|
bool triggered = sdio_slave_hal_recv_done(context.hal);
|
||||||
while (triggered) {
|
while (triggered) {
|
||||||
portENTER_CRITICAL_ISR(&context.recv_spinlock);
|
portENTER_CRITICAL_ISR(&context.recv_spinlock);
|
||||||
@@ -771,7 +771,7 @@ esp_err_t sdio_slave_recv(sdio_slave_buf_handle_t *handle_ret, uint8_t **out_add
|
|||||||
esp_err_t sdio_slave_recv_packet(sdio_slave_buf_handle_t *handle_ret, TickType_t wait)
|
esp_err_t sdio_slave_recv_packet(sdio_slave_buf_handle_t *handle_ret, TickType_t wait)
|
||||||
{
|
{
|
||||||
SDIO_SLAVE_CHECK(handle_ret != NULL, "handle address cannot be 0", ESP_ERR_INVALID_ARG);
|
SDIO_SLAVE_CHECK(handle_ret != NULL, "handle address cannot be 0", ESP_ERR_INVALID_ARG);
|
||||||
portBASE_TYPE err = xSemaphoreTake(context.recv_event, wait);
|
BaseType_t err = xSemaphoreTake(context.recv_event, wait);
|
||||||
if (err == pdFALSE) {
|
if (err == pdFALSE) {
|
||||||
return ESP_ERR_TIMEOUT;
|
return ESP_ERR_TIMEOUT;
|
||||||
}
|
}
|
||||||
|
@@ -838,7 +838,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
|
|||||||
int rx_fifo_len = 0;
|
int rx_fifo_len = 0;
|
||||||
uint32_t uart_intr_status = 0;
|
uint32_t uart_intr_status = 0;
|
||||||
uart_event_t uart_event;
|
uart_event_t uart_event;
|
||||||
portBASE_TYPE HPTaskAwoken = 0;
|
BaseType_t HPTaskAwoken = 0;
|
||||||
bool need_yield = false;
|
bool need_yield = false;
|
||||||
static uint8_t pat_flg = 0;
|
static uint8_t pat_flg = 0;
|
||||||
BaseType_t sent = pdFALSE;
|
BaseType_t sent = pdFALSE;
|
||||||
|
@@ -45,7 +45,7 @@ static void usb_serial_jtag_write_and_flush(const uint8_t *buf, uint32_t wr_len)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static void usb_serial_jtag_isr_handler_default(void *arg) {
|
static void usb_serial_jtag_isr_handler_default(void *arg) {
|
||||||
portBASE_TYPE xTaskWoken = 0;
|
BaseType_t xTaskWoken = 0;
|
||||||
uint32_t usbjtag_intr_status = 0;
|
uint32_t usbjtag_intr_status = 0;
|
||||||
usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask();
|
usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask();
|
||||||
|
|
||||||
|
@@ -288,7 +288,7 @@ static IRAM_ATTR void adc_dma_intr_handler(void *arg)
|
|||||||
|
|
||||||
static IRAM_ATTR bool s_adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
|
static IRAM_ATTR bool s_adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
|
||||||
{
|
{
|
||||||
portBASE_TYPE taskAwoken = 0;
|
BaseType_t taskAwoken = 0;
|
||||||
bool need_yield = false;
|
bool need_yield = false;
|
||||||
BaseType_t ret;
|
BaseType_t ret;
|
||||||
adc_hal_dma_desc_status_t status = false;
|
adc_hal_dma_desc_status_t status = false;
|
||||||
|
@@ -118,7 +118,7 @@ static void esp_ipc_init(void)
|
|||||||
task_name[3] = i + (char)'0';
|
task_name[3] = i + (char)'0';
|
||||||
s_ipc_mutex[i] = xSemaphoreCreateMutexStatic(&s_ipc_mutex_buffer[i]);
|
s_ipc_mutex[i] = xSemaphoreCreateMutexStatic(&s_ipc_mutex_buffer[i]);
|
||||||
s_ipc_ack[i] = xSemaphoreCreateBinaryStatic(&s_ipc_ack_buffer[i]);
|
s_ipc_ack[i] = xSemaphoreCreateBinaryStatic(&s_ipc_ack_buffer[i]);
|
||||||
portBASE_TYPE res = xTaskCreatePinnedToCore(ipc_task, task_name, IPC_STACK_SIZE, (void*) i,
|
BaseType_t res = xTaskCreatePinnedToCore(ipc_task, task_name, IPC_STACK_SIZE, (void*) i,
|
||||||
configMAX_PRIORITIES - 1, &s_ipc_task_handle[i], i);
|
configMAX_PRIORITIES - 1, &s_ipc_task_handle[i], i);
|
||||||
assert(res == pdTRUE);
|
assert(res == pdTRUE);
|
||||||
(void)res;
|
(void)res;
|
||||||
|
@@ -61,7 +61,7 @@ extern "C" {
|
|||||||
|
|
||||||
typedef portSTACK_TYPE StackType_t;
|
typedef portSTACK_TYPE StackType_t;
|
||||||
typedef portBASE_TYPE BaseType_t;
|
typedef portBASE_TYPE BaseType_t;
|
||||||
typedef unsigned long UBaseType_t;
|
typedef unsigned portBASE_TYPE UBaseType_t;
|
||||||
|
|
||||||
typedef unsigned long TickType_t;
|
typedef unsigned long TickType_t;
|
||||||
#define portMAX_DELAY ( TickType_t ) ULONG_MAX
|
#define portMAX_DELAY ( TickType_t ) ULONG_MAX
|
||||||
@@ -174,11 +174,11 @@ extern void vTaskExitCritical( void );
|
|||||||
#define portEXIT_CRITICAL(...) CHOOSE_MACRO_VA_ARG(portEXIT_CRITICAL_IDF, portEXIT_CRITICAL_SMP, ##__VA_ARGS__)(__VA_ARGS__)
|
#define portEXIT_CRITICAL(...) CHOOSE_MACRO_VA_ARG(portEXIT_CRITICAL_IDF, portEXIT_CRITICAL_SMP, ##__VA_ARGS__)(__VA_ARGS__)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
extern portBASE_TYPE xPortSetInterruptMask( void );
|
extern BaseType_t xPortSetInterruptMask( void );
|
||||||
extern void vPortClearInterruptMask( portBASE_TYPE xMask );
|
extern void vPortClearInterruptMask( BaseType_t xMask );
|
||||||
|
|
||||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ({ \
|
#define portSET_INTERRUPT_MASK_FROM_ISR() ({ \
|
||||||
portBASE_TYPE cur_level; \
|
BaseType_t cur_level; \
|
||||||
cur_level = xPortSetInterruptMask(); \
|
cur_level = xPortSetInterruptMask(); \
|
||||||
vTaskEnterCritical(); \
|
vTaskEnterCritical(); \
|
||||||
cur_level; \
|
cur_level; \
|
||||||
|
@@ -105,12 +105,12 @@ static sigset_t xSchedulerOriginalSignalMask;
|
|||||||
static pthread_t hMainThread = ( pthread_t )NULL;
|
static pthread_t hMainThread = ( pthread_t )NULL;
|
||||||
|
|
||||||
// These are saved as part of a thread's state in prvSwitchThread()
|
// These are saved as part of a thread's state in prvSwitchThread()
|
||||||
static volatile portBASE_TYPE uxCriticalNestingIDF = 0; /* Track nesting calls for IDF style critical sections. FreeRTOS critical section nesting is maintained in the TCB. */
|
static volatile BaseType_t uxCriticalNestingIDF = 0; /* Track nesting calls for IDF style critical sections. FreeRTOS critical section nesting is maintained in the TCB. */
|
||||||
static volatile UBaseType_t uxInterruptNesting = 0; /* Tracks if we are currently in an interrupt. */
|
static volatile UBaseType_t uxInterruptNesting = 0; /* Tracks if we are currently in an interrupt. */
|
||||||
static volatile portBASE_TYPE uxInterruptLevel = 0; /* Tracks the current level (i.e., interrupt mask) */
|
static volatile BaseType_t uxInterruptLevel = 0; /* Tracks the current level (i.e., interrupt mask) */
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
static portBASE_TYPE xSchedulerEnd = pdFALSE;
|
static BaseType_t xSchedulerEnd = pdFALSE;
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
static void prvSetupSignalsAndSchedulerPolicy( void );
|
static void prvSetupSignalsAndSchedulerPolicy( void );
|
||||||
@@ -188,7 +188,7 @@ void vPortStartFirstTask( void )
|
|||||||
/*
|
/*
|
||||||
* See header file for description.
|
* See header file for description.
|
||||||
*/
|
*/
|
||||||
portBASE_TYPE xPortStartScheduler( void )
|
BaseType_t xPortStartScheduler( void )
|
||||||
{
|
{
|
||||||
int iSignal;
|
int iSignal;
|
||||||
sigset_t xSignals;
|
sigset_t xSignals;
|
||||||
@@ -320,18 +320,18 @@ void vPortYield( void )
|
|||||||
Hence, we need to call vPortDisableInterrupts() and vPortEnableInterrupts(), otherwise interrupts
|
Hence, we need to call vPortDisableInterrupts() and vPortEnableInterrupts(), otherwise interrupts
|
||||||
are never disabled/enabled. */
|
are never disabled/enabled. */
|
||||||
|
|
||||||
portBASE_TYPE xPortSetInterruptMask( void )
|
BaseType_t xPortSetInterruptMask( void )
|
||||||
{
|
{
|
||||||
if (uxInterruptLevel == 0 && uxCriticalNestingIDF == 0) {
|
if (uxInterruptLevel == 0 && uxCriticalNestingIDF == 0) {
|
||||||
vPortDisableInterrupts();
|
vPortDisableInterrupts();
|
||||||
}
|
}
|
||||||
portBASE_TYPE prev_intr_level = uxInterruptLevel;
|
BaseType_t prev_intr_level = uxInterruptLevel;
|
||||||
uxInterruptLevel++;
|
uxInterruptLevel++;
|
||||||
return prev_intr_level;
|
return prev_intr_level;
|
||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
void vPortClearInterruptMask( portBASE_TYPE xMask )
|
void vPortClearInterruptMask( BaseType_t xMask )
|
||||||
{
|
{
|
||||||
// Only reenable interrupts if xMask is 0
|
// Only reenable interrupts if xMask is 0
|
||||||
uxInterruptLevel = xMask;
|
uxInterruptLevel = xMask;
|
||||||
@@ -646,7 +646,7 @@ int main(int argc, const char **argv)
|
|||||||
|
|
||||||
usleep(1000);
|
usleep(1000);
|
||||||
|
|
||||||
portBASE_TYPE res;
|
BaseType_t res;
|
||||||
|
|
||||||
#if ( configNUM_CORES > 1 )
|
#if ( configNUM_CORES > 1 )
|
||||||
res = xTaskCreateAffinitySet(&main_task, "main",
|
res = xTaskCreateAffinitySet(&main_task, "main",
|
||||||
|
@@ -58,8 +58,8 @@ extern "C" {
|
|||||||
#define portPOINTER_SIZE_TYPE intptr_t
|
#define portPOINTER_SIZE_TYPE intptr_t
|
||||||
|
|
||||||
typedef portSTACK_TYPE StackType_t;
|
typedef portSTACK_TYPE StackType_t;
|
||||||
typedef long BaseType_t;
|
typedef portBASE_TYPE BaseType_t;
|
||||||
typedef unsigned long UBaseType_t;
|
typedef unsigned portBASE_TYPE UBaseType_t;
|
||||||
|
|
||||||
typedef unsigned long TickType_t;
|
typedef unsigned long TickType_t;
|
||||||
#define portMAX_DELAY ( TickType_t ) ULONG_MAX
|
#define portMAX_DELAY ( TickType_t ) ULONG_MAX
|
||||||
@@ -91,8 +91,8 @@ extern void vPortEnableInterrupts( void );
|
|||||||
#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() )
|
#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() )
|
||||||
#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() )
|
#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() )
|
||||||
|
|
||||||
extern portBASE_TYPE xPortSetInterruptMask( void );
|
extern BaseType_t xPortSetInterruptMask( void );
|
||||||
extern void vPortClearInterruptMask( portBASE_TYPE xMask );
|
extern void vPortClearInterruptMask( BaseType_t xMask );
|
||||||
|
|
||||||
extern void vPortEnterCritical( void );
|
extern void vPortEnterCritical( void );
|
||||||
extern void vPortExitCritical( void );
|
extern void vPortExitCritical( void );
|
||||||
|
@@ -98,10 +98,10 @@ static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT;
|
|||||||
static sigset_t xAllSignals;
|
static sigset_t xAllSignals;
|
||||||
static sigset_t xSchedulerOriginalSignalMask;
|
static sigset_t xSchedulerOriginalSignalMask;
|
||||||
static pthread_t hMainThread = ( pthread_t )NULL;
|
static pthread_t hMainThread = ( pthread_t )NULL;
|
||||||
static volatile portBASE_TYPE uxCriticalNesting;
|
static volatile BaseType_t uxCriticalNesting;
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
static portBASE_TYPE xSchedulerEnd = pdFALSE;
|
static BaseType_t xSchedulerEnd = pdFALSE;
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
static void prvSetupSignalsAndSchedulerPolicy( void );
|
static void prvSetupSignalsAndSchedulerPolicy( void );
|
||||||
@@ -179,7 +179,7 @@ void vPortStartFirstTask( void )
|
|||||||
/*
|
/*
|
||||||
* See header file for description.
|
* See header file for description.
|
||||||
*/
|
*/
|
||||||
portBASE_TYPE xPortStartScheduler( void )
|
BaseType_t xPortStartScheduler( void )
|
||||||
{
|
{
|
||||||
int iSignal;
|
int iSignal;
|
||||||
sigset_t xSignals;
|
sigset_t xSignals;
|
||||||
@@ -307,7 +307,7 @@ void vPortEnableInterrupts( void )
|
|||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
portBASE_TYPE xPortSetInterruptMask( void )
|
BaseType_t xPortSetInterruptMask( void )
|
||||||
{
|
{
|
||||||
/* Interrupts are always disabled inside ISRs (signals
|
/* Interrupts are always disabled inside ISRs (signals
|
||||||
handlers). */
|
handlers). */
|
||||||
@@ -315,7 +315,7 @@ portBASE_TYPE xPortSetInterruptMask( void )
|
|||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
void vPortClearInterruptMask( portBASE_TYPE xMask )
|
void vPortClearInterruptMask( BaseType_t xMask )
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
@@ -55,7 +55,7 @@ int main(int argc, const char **argv)
|
|||||||
setvbuf(stdout, NULL, _IOLBF, 0);
|
setvbuf(stdout, NULL, _IOLBF, 0);
|
||||||
|
|
||||||
usleep(1000);
|
usleep(1000);
|
||||||
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
|
BaseType_t res = xTaskCreatePinnedToCore(&main_task, "main",
|
||||||
ESP_TASK_MAIN_STACK, NULL,
|
ESP_TASK_MAIN_STACK, NULL,
|
||||||
ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE);
|
ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE);
|
||||||
assert(res == pdTRUE);
|
assert(res == pdTRUE);
|
||||||
|
@@ -147,7 +147,7 @@ static bool test_clear_bits;
|
|||||||
|
|
||||||
static bool on_timer_alarm_cb(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx)
|
static bool on_timer_alarm_cb(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx)
|
||||||
{
|
{
|
||||||
portBASE_TYPE task_woken = pdFALSE;
|
BaseType_t task_woken = pdFALSE;
|
||||||
|
|
||||||
gptimer_stop(timer);
|
gptimer_stop(timer);
|
||||||
|
|
||||||
|
@@ -187,7 +187,7 @@ static void button_press_serial_cb(void* tmr)
|
|||||||
static void button_gpio_isr_handler(void* arg)
|
static void button_gpio_isr_handler(void* arg)
|
||||||
{
|
{
|
||||||
button_dev_t* btn = (button_dev_t*) arg;
|
button_dev_t* btn = (button_dev_t*) arg;
|
||||||
portBASE_TYPE HPTaskAwoken = pdFALSE;
|
BaseType_t HPTaskAwoken = pdFALSE;
|
||||||
int level = gpio_get_level(btn->io_num);
|
int level = gpio_get_level(btn->io_num);
|
||||||
if (level == btn->active_level) {
|
if (level == btn->active_level) {
|
||||||
if (btn->tap_psh_cb.tmr) {
|
if (btn->tap_psh_cb.tmr) {
|
||||||
|
@@ -69,7 +69,7 @@
|
|||||||
*/
|
*/
|
||||||
static IRAM_ATTR bool cb_ledc_fade_end_event(const ledc_cb_param_t *param, void *user_arg)
|
static IRAM_ATTR bool cb_ledc_fade_end_event(const ledc_cb_param_t *param, void *user_arg)
|
||||||
{
|
{
|
||||||
portBASE_TYPE taskAwoken = pdFALSE;
|
BaseType_t taskAwoken = pdFALSE;
|
||||||
|
|
||||||
if (param->event == LEDC_FADE_END_EVT) {
|
if (param->event == LEDC_FADE_END_EVT) {
|
||||||
SemaphoreHandle_t counting_sem = (SemaphoreHandle_t) user_arg;
|
SemaphoreHandle_t counting_sem = (SemaphoreHandle_t) user_arg;
|
||||||
|
Reference in New Issue
Block a user