From 754c8fcaa5f33fe1cceb150e61759d5e43a93cf3 Mon Sep 17 00:00:00 2001 From: Renz Bagaporo Date: Wed, 31 Mar 2021 17:12:00 +0800 Subject: [PATCH 1/2] ci: modify ulp_riscv example to detect unintended wake --- examples/system/ulp_riscv/example_test.py | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/examples/system/ulp_riscv/example_test.py b/examples/system/ulp_riscv/example_test.py index 17a3a83286..735fdb7aaa 100644 --- a/examples/system/ulp_riscv/example_test.py +++ b/examples/system/ulp_riscv/example_test.py @@ -1,11 +1,14 @@ from __future__ import unicode_literals import re + +import tiny_test_fw import ttfw_idf +from tiny_test_fw import DUT @ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2']) -def test_examples_ulp_riscv(env, extra_data): +def test_examples_ulp_riscv(env, extra_data): # type: (tiny_test_fw.Env.Env, None) -> None # pylint: disable=unused-argument dut = env.get_dut('ulp_riscv', 'examples/system/ulp_riscv') dut.start_app() @@ -16,17 +19,26 @@ def test_examples_ulp_riscv(env, extra_data): # Run two times to make sure device sleep # and wake up properly for i in range(0, 2): - # Pulling GPIO0 low using DTR - dut.port_inst.setDTR(True) + # Set GPIO0 using DTR + dut.port_inst.setDTR(i % 2 == 0) dut.expect('ULP-RISC-V woke up the main CPU!', timeout=5) - # We pulled GPIO0 low previously - dut.expect(re.compile(r'ULP-RISC-V read changes in GPIO_0 current is: Low'), timeout=5) + # Check GPIO state + state = 'Low' if i % 2 == 0 else 'High' + dut.expect(re.compile(r'ULP-RISC-V read changes in GPIO_0 current is: %s' % state), timeout=5) # Go back to sleep dut.expect('Entering in deep sleep', timeout=5) + try: + # We expect a timeout here, otherwise it means that + # the main CPU woke up unexpectedly! + dut.expect('ULP-RISC-V woke up the main CPU!', timeout=20) + raise Exception('Main CPU woke up unexpectedly!') + except DUT.ExpectTimeout: + pass + if __name__ == '__main__': test_examples_ulp_riscv() From 3639c2322b1e5464968478cb0a16608eead28eab Mon Sep 17 00:00:00 2001 From: Renz Bagaporo Date: Wed, 24 Mar 2021 19:58:12 +0800 Subject: [PATCH 2/2] ulp: clear rtc int at initialization Closes https://github.com/espressif/esp-idf/issues/6654 --- components/bootloader_support/src/bootloader_clock_init.c | 3 +++ components/esp_hw_support/port/esp32/rtc_init.c | 3 +++ components/esp_hw_support/port/esp32c3/rtc_init.c | 3 +++ components/esp_hw_support/port/esp32s2/rtc_init.c | 3 +++ components/esp_hw_support/port/esp32s3/rtc_init.c | 3 +++ components/esp_system/port/brownout.c | 1 + 6 files changed, 16 insertions(+) diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index db1a736d12..dee8bf201b 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -80,4 +80,7 @@ __attribute__((weak)) void bootloader_clock_configure(void) rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES); } #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL + + REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); + REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); } diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c index 9b2911d42d..f86811a99f 100644 --- a/components/esp_hw_support/port/esp32/rtc_init.c +++ b/components/esp_hw_support/port/esp32/rtc_init.c @@ -96,6 +96,9 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); } + + REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); + REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); } rtc_vddsdio_config_t rtc_vddsdio_get_config(void) diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index cfefb9ea79..fa4125ab7b 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -148,6 +148,9 @@ void rtc_init(rtc_config_t cfg) calibrate_ocode(); } } + + REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); + REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); } rtc_vddsdio_config_t rtc_vddsdio_get_config(void) diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index a71251eb61..d54a51ba16 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -160,6 +160,9 @@ void rtc_init(rtc_config_t cfg) calibrate_ocode(); } } + + REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); + REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); } rtc_vddsdio_config_t rtc_vddsdio_get_config(void) diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index ff8f0e7e88..72a9b67e9c 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -196,6 +196,9 @@ void rtc_init(rtc_config_t cfg) } rtc_clk_cpu_freq_set_config(&old_config); } + + REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); + REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); } rtc_vddsdio_config_t rtc_vddsdio_get_config(void) diff --git a/components/esp_system/port/brownout.c b/components/esp_system/port/brownout.c index 91eea5eecc..f65d31de5e 100644 --- a/components/esp_system/port/brownout.c +++ b/components/esp_system/port/brownout.c @@ -79,6 +79,7 @@ void esp_brownout_init(void) brownout_hal_config(&cfg); + #ifndef SOC_BROWNOUT_RESET_SUPPORTED rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M);