From 70ee85d38b45a43060347b219eb0ef74644e4d8d Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 14 Sep 2022 11:34:56 +0800 Subject: [PATCH] mcpwm: check sync direction is valid --- components/driver/deprecated/driver/mcpwm.h | 4 ++-- components/driver/mcpwm/mcpwm_timer.c | 12 ++++++++++++ components/soc/esp32s3/include/soc/clk_tree_defs.h | 2 +- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/components/driver/deprecated/driver/mcpwm.h b/components/driver/deprecated/driver/mcpwm.h index e8ff38778f..a85c1951bb 100644 --- a/components/driver/deprecated/driver/mcpwm.h +++ b/components/driver/deprecated/driver/mcpwm.h @@ -344,8 +344,8 @@ esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time * @param mcpwm_num set MCPWM unit(0-1) * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers * @param dt_mode set deadtime mode - * @param red set rising edge delay = red*100ns - * @param fed set rising edge delay = fed*100ns + * @param red set rising edge delay = (red + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`) + * @param fed set rising edge delay = (fed + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`) * * @return * - ESP_OK Success diff --git a/components/driver/mcpwm/mcpwm_timer.c b/components/driver/mcpwm/mcpwm_timer.c index 31ff2ded68..6d516a9256 100644 --- a/components/driver/mcpwm/mcpwm_timer.c +++ b/components/driver/mcpwm/mcpwm_timer.c @@ -273,6 +273,18 @@ esp_err_t mcpwm_timer_set_phase_on_sync(mcpwm_timer_handle_t timer, const mcpwm_ int group_id = group->group_id; int timer_id = timer->timer_id; mcpwm_sync_handle_t sync_source = config->sync_src; + // check if the sync direction is valid + bool valid_direction = true; + if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_UP) { + valid_direction = config->direction == MCPWM_TIMER_DIRECTION_UP; + } else if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_DOWN) { + valid_direction = config->direction == MCPWM_TIMER_DIRECTION_DOWN; + } else if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_PAUSE) { + valid_direction = false; + } else { + valid_direction = true; + } + ESP_RETURN_ON_FALSE(valid_direction, ESP_ERR_INVALID_ARG, TAG, "invalid sync direction"); // enable sync feature and set sync phase if (sync_source) { diff --git a/components/soc/esp32s3/include/soc/clk_tree_defs.h b/components/soc/esp32s3/include/soc/clk_tree_defs.h index f3dceb9f86..4a55c25b75 100644 --- a/components/soc/esp32s3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s3/include/soc/clk_tree_defs.h @@ -224,7 +224,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of MCPWM Timer */ -#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_D2} +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M} /** * @brief Type of MCPWM timer clock source