forked from espressif/esp-idf
refactor(esp_driver_spi): reformat code with astyle_py
This commit is contained in:
@@ -62,7 +62,6 @@ typedef struct {
|
|||||||
*/
|
*/
|
||||||
} spi_slave_interface_config_t;
|
} spi_slave_interface_config_t;
|
||||||
|
|
||||||
|
|
||||||
#define SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO (1<<0) ///< Automatically re-malloc dma buffer if user buffer doesn't meet hardware alignment or dma_capable, this process may loss some memory and performance
|
#define SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO (1<<0) ///< Automatically re-malloc dma buffer if user buffer doesn't meet hardware alignment or dma_capable, this process may loss some memory and performance
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@@ -326,8 +326,12 @@ void spi_get_timing(bool gpio_is_used, int input_delay_ns, int eff_clk, int* dum
|
|||||||
int timing_miso_delay;
|
int timing_miso_delay;
|
||||||
|
|
||||||
spi_hal_cal_timing(APB_CLK_FREQ, eff_clk, gpio_is_used, input_delay_ns, &timing_dummy, &timing_miso_delay);
|
spi_hal_cal_timing(APB_CLK_FREQ, eff_clk, gpio_is_used, input_delay_ns, &timing_dummy, &timing_miso_delay);
|
||||||
if (dummy_o) *dummy_o = timing_dummy;
|
if (dummy_o) {
|
||||||
if (cycles_remain_o) *cycles_remain_o = timing_miso_delay;
|
*dummy_o = timing_dummy;
|
||||||
|
}
|
||||||
|
if (cycles_remain_o) {
|
||||||
|
*cycles_remain_o = timing_miso_delay;
|
||||||
|
}
|
||||||
#else
|
#else
|
||||||
//TODO: IDF-6578
|
//TODO: IDF-6578
|
||||||
ESP_LOGW(SPI_TAG, "This func temporary not supported for current target!");
|
ESP_LOGW(SPI_TAG, "This func temporary not supported for current target!");
|
||||||
@@ -428,7 +432,9 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
|
|||||||
|
|
||||||
//Allocate memory for device
|
//Allocate memory for device
|
||||||
dev = malloc(sizeof(spi_device_t));
|
dev = malloc(sizeof(spi_device_t));
|
||||||
if (dev == NULL) goto nomem;
|
if (dev == NULL) {
|
||||||
|
goto nomem;
|
||||||
|
}
|
||||||
memset(dev, 0, sizeof(spi_device_t));
|
memset(dev, 0, sizeof(spi_device_t));
|
||||||
|
|
||||||
dev->id = freecs;
|
dev->id = freecs;
|
||||||
@@ -492,8 +498,12 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
|
|||||||
|
|
||||||
nomem:
|
nomem:
|
||||||
if (dev) {
|
if (dev) {
|
||||||
if (dev->trans_queue) vQueueDelete(dev->trans_queue);
|
if (dev->trans_queue) {
|
||||||
if (dev->ret_queue) vQueueDelete(dev->ret_queue);
|
vQueueDelete(dev->trans_queue);
|
||||||
|
}
|
||||||
|
if (dev->ret_queue) {
|
||||||
|
vQueueDelete(dev->ret_queue);
|
||||||
|
}
|
||||||
spi_bus_lock_unregister_dev(dev->dev_lock);
|
spi_bus_lock_unregister_dev(dev->dev_lock);
|
||||||
}
|
}
|
||||||
free(dev);
|
free(dev);
|
||||||
@@ -519,11 +529,17 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
|
|||||||
|
|
||||||
//return
|
//return
|
||||||
int spics_io_num = handle->cfg.spics_io_num;
|
int spics_io_num = handle->cfg.spics_io_num;
|
||||||
if (spics_io_num >= 0) spicommon_cs_free_io(spics_io_num);
|
if (spics_io_num >= 0) {
|
||||||
|
spicommon_cs_free_io(spics_io_num);
|
||||||
|
}
|
||||||
|
|
||||||
//Kill queues
|
//Kill queues
|
||||||
if (handle->trans_queue) vQueueDelete(handle->trans_queue);
|
if (handle->trans_queue) {
|
||||||
if (handle->ret_queue) vQueueDelete(handle->ret_queue);
|
vQueueDelete(handle->trans_queue);
|
||||||
|
}
|
||||||
|
if (handle->ret_queue) {
|
||||||
|
vQueueDelete(handle->ret_queue);
|
||||||
|
}
|
||||||
spi_bus_lock_unregister_dev(handle->dev_lock);
|
spi_bus_lock_unregister_dev(handle->dev_lock);
|
||||||
|
|
||||||
assert(handle->host->device[handle->id] == handle);
|
assert(handle->host->device[handle->id] == handle);
|
||||||
@@ -568,7 +584,9 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev)
|
|||||||
static SPI_MASTER_ISR_ATTR spi_device_t *get_acquiring_dev(spi_host_t *host)
|
static SPI_MASTER_ISR_ATTR spi_device_t *get_acquiring_dev(spi_host_t *host)
|
||||||
{
|
{
|
||||||
spi_bus_lock_dev_handle_t dev_lock = spi_bus_lock_get_acquiring_dev(host->bus_attr->lock);
|
spi_bus_lock_dev_handle_t dev_lock = spi_bus_lock_get_acquiring_dev(host->bus_attr->lock);
|
||||||
if (!dev_lock) return NULL;
|
if (!dev_lock) {
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
return host->device[spi_bus_lock_get_dev_id(dev_lock)];
|
return host->device[spi_bus_lock_get_dev_id(dev_lock)];
|
||||||
}
|
}
|
||||||
@@ -652,7 +670,9 @@ static void SPI_MASTER_ISR_ATTR spi_new_trans(spi_device_t *dev, spi_trans_priv_
|
|||||||
spi_hal_prepare_data(hal, hal_dev, &hal_trans);
|
spi_hal_prepare_data(hal, hal_dev, &hal_trans);
|
||||||
|
|
||||||
//Call pre-transmission callback, if any
|
//Call pre-transmission callback, if any
|
||||||
if (dev->cfg.pre_cb) dev->cfg.pre_cb(trans);
|
if (dev->cfg.pre_cb) {
|
||||||
|
dev->cfg.pre_cb(trans);
|
||||||
|
}
|
||||||
//Kick off transfer
|
//Kick off transfer
|
||||||
spi_hal_user_start(hal);
|
spi_hal_user_start(hal);
|
||||||
}
|
}
|
||||||
@@ -666,7 +686,9 @@ static void SPI_MASTER_ISR_ATTR spi_post_trans(spi_host_t *host)
|
|||||||
spi_hal_fetch_result(&host->hal);
|
spi_hal_fetch_result(&host->hal);
|
||||||
//Call post-transaction callback, if any
|
//Call post-transaction callback, if any
|
||||||
spi_device_t* dev = host->device[host->cur_cs];
|
spi_device_t* dev = host->device[host->cur_cs];
|
||||||
if (dev->cfg.post_cb) dev->cfg.post_cb(cur_trans);
|
if (dev->cfg.post_cb) {
|
||||||
|
dev->cfg.post_cb(cur_trans);
|
||||||
|
}
|
||||||
|
|
||||||
host->cur_cs = DEV_NUM_MAX;
|
host->cur_cs = DEV_NUM_MAX;
|
||||||
}
|
}
|
||||||
@@ -734,7 +756,6 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
|
|||||||
spi_bus_lock_handle_t lock = host->bus_attr->lock;
|
spi_bus_lock_handle_t lock = host->bus_attr->lock;
|
||||||
BaseType_t trans_found = pdFALSE;
|
BaseType_t trans_found = pdFALSE;
|
||||||
|
|
||||||
|
|
||||||
// There should be remaining requests
|
// There should be remaining requests
|
||||||
BUS_LOCK_DEBUG_EXECUTE_CHECK(spi_bus_lock_bg_req_exist(lock));
|
BUS_LOCK_DEBUG_EXECUTE_CHECK(spi_bus_lock_bg_req_exist(lock));
|
||||||
|
|
||||||
@@ -781,7 +802,9 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
|
|||||||
// or resume acquiring device task (if quit due to bus acquiring).
|
// or resume acquiring device task (if quit due to bus acquiring).
|
||||||
} while (!spi_bus_lock_bg_exit(lock, trans_found, &do_yield));
|
} while (!spi_bus_lock_bg_exit(lock, trans_found, &do_yield));
|
||||||
|
|
||||||
if (do_yield) portYIELD_FROM_ISR();
|
if (do_yield) {
|
||||||
|
portYIELD_FROM_ISR();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handle, spi_transaction_t *trans_desc)
|
static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handle, spi_transaction_t *trans_desc)
|
||||||
@@ -936,7 +959,9 @@ clean_up:
|
|||||||
esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
||||||
{
|
{
|
||||||
esp_err_t ret = check_trans_valid(handle, trans_desc);
|
esp_err_t ret = check_trans_valid(handle, trans_desc);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
spi_host_t *host = handle->host;
|
spi_host_t *host = handle->host;
|
||||||
|
|
||||||
@@ -950,7 +975,9 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi
|
|||||||
|
|
||||||
spi_trans_priv_t trans_buf = { .trans = trans_desc, };
|
spi_trans_priv_t trans_buf = { .trans = trans_desc, };
|
||||||
ret = setup_priv_desc(host, &trans_buf);
|
ret = setup_priv_desc(host, &trans_buf);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_PM_ENABLE
|
#ifdef CONFIG_PM_ENABLE
|
||||||
// though clock source is selectable, read/write reg and mem of spi peripherial still use APB
|
// though clock source is selectable, read/write reg and mem of spi peripherial still use APB
|
||||||
@@ -1015,10 +1042,14 @@ esp_err_t SPI_MASTER_ATTR spi_device_transmit(spi_device_handle_t handle, spi_tr
|
|||||||
spi_transaction_t *ret_trans;
|
spi_transaction_t *ret_trans;
|
||||||
//ToDo: check if any spi transfers in flight
|
//ToDo: check if any spi transfers in flight
|
||||||
ret = spi_device_queue_trans(handle, trans_desc, portMAX_DELAY);
|
ret = spi_device_queue_trans(handle, trans_desc, portMAX_DELAY);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
ret = spi_device_get_trans_result(handle, &ret_trans, portMAX_DELAY);
|
ret = spi_device_get_trans_result(handle, &ret_trans, portMAX_DELAY);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
assert(ret_trans == trans_desc);
|
assert(ret_trans == trans_desc);
|
||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
@@ -1093,13 +1124,17 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_start(spi_device_handle_t handl
|
|||||||
esp_err_t ret;
|
esp_err_t ret;
|
||||||
SPI_CHECK(ticks_to_wait == portMAX_DELAY, "currently timeout is not available for polling transactions", ESP_ERR_INVALID_ARG);
|
SPI_CHECK(ticks_to_wait == portMAX_DELAY, "currently timeout is not available for polling transactions", ESP_ERR_INVALID_ARG);
|
||||||
ret = check_trans_valid(handle, trans_desc);
|
ret = check_trans_valid(handle, trans_desc);
|
||||||
if (ret!=ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot send polling transaction while the previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE);
|
SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot send polling transaction while the previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE);
|
||||||
|
|
||||||
spi_host_t *host = handle->host;
|
spi_host_t *host = handle->host;
|
||||||
spi_trans_priv_t priv_polling_trans = { .trans = trans_desc, };
|
spi_trans_priv_t priv_polling_trans = { .trans = trans_desc, };
|
||||||
ret = setup_priv_desc(host, &priv_polling_trans);
|
ret = setup_priv_desc(host, &priv_polling_trans);
|
||||||
if (ret!=ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
/* If device_acquiring_lock is set to handle, it means that the user has already
|
/* If device_acquiring_lock is set to handle, it means that the user has already
|
||||||
* acquired the bus thanks to the function `spi_device_acquire_bus()`.
|
* acquired the bus thanks to the function `spi_device_acquire_bus()`.
|
||||||
@@ -1182,7 +1217,9 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_transmit(spi_device_handle_t ha
|
|||||||
{
|
{
|
||||||
esp_err_t ret;
|
esp_err_t ret;
|
||||||
ret = spi_device_polling_start(handle, trans_desc, portMAX_DELAY);
|
ret = spi_device_polling_start(handle, trans_desc, portMAX_DELAY);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
return spi_device_polling_end(handle, portMAX_DELAY);
|
return spi_device_polling_end(handle, portMAX_DELAY);
|
||||||
}
|
}
|
||||||
|
@@ -36,7 +36,6 @@ static const char *SPI_TAG = "spi_slave";
|
|||||||
|
|
||||||
#define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, SPI_TAG, str)
|
#define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, SPI_TAG, str)
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
|
#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
|
||||||
#define SPI_SLAVE_ISR_ATTR IRAM_ATTR
|
#define SPI_SLAVE_ISR_ATTR IRAM_ATTR
|
||||||
#else
|
#else
|
||||||
@@ -181,7 +180,9 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
|
|||||||
|
|
||||||
//See how many dma descriptors we need and allocate them
|
//See how many dma descriptors we need and allocate them
|
||||||
int dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN;
|
int dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN;
|
||||||
if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given
|
if (dma_desc_ct == 0) {
|
||||||
|
dma_desc_ct = 1; //default to 4k when max is not given
|
||||||
|
}
|
||||||
spihost[host]->max_transfer_sz = dma_desc_ct * SPI_MAX_DMA_LEN;
|
spihost[host]->max_transfer_sz = dma_desc_ct * SPI_MAX_DMA_LEN;
|
||||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||||
size_t alignment;
|
size_t alignment;
|
||||||
@@ -216,7 +217,9 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
|
|||||||
}
|
}
|
||||||
|
|
||||||
// The slave DMA suffers from unexpected transactions. Forbid reading if DMA is enabled by disabling the CS line.
|
// The slave DMA suffers from unexpected transactions. Forbid reading if DMA is enabled by disabling the CS line.
|
||||||
if (spihost[host]->dma_enabled) freeze_cs(spihost[host]);
|
if (spihost[host]->dma_enabled) {
|
||||||
|
freeze_cs(spihost[host]);
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_PM_ENABLE
|
#ifdef CONFIG_PM_ENABLE
|
||||||
err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_slave",
|
err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_slave",
|
||||||
@@ -282,8 +285,12 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
|
|||||||
|
|
||||||
cleanup:
|
cleanup:
|
||||||
if (spihost[host]) {
|
if (spihost[host]) {
|
||||||
if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
|
if (spihost[host]->trans_queue) {
|
||||||
if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
|
vQueueDelete(spihost[host]->trans_queue);
|
||||||
|
}
|
||||||
|
if (spihost[host]->ret_queue) {
|
||||||
|
vQueueDelete(spihost[host]->ret_queue);
|
||||||
|
}
|
||||||
#ifdef CONFIG_PM_ENABLE
|
#ifdef CONFIG_PM_ENABLE
|
||||||
if (spihost[host]->pm_lock) {
|
if (spihost[host]->pm_lock) {
|
||||||
esp_pm_lock_release(spihost[host]->pm_lock);
|
esp_pm_lock_release(spihost[host]->pm_lock);
|
||||||
@@ -309,8 +316,12 @@ esp_err_t spi_slave_free(spi_host_device_t host)
|
|||||||
{
|
{
|
||||||
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
|
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
|
||||||
SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
|
SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
|
||||||
if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
|
if (spihost[host]->trans_queue) {
|
||||||
if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
|
vQueueDelete(spihost[host]->trans_queue);
|
||||||
|
}
|
||||||
|
if (spihost[host]->ret_queue) {
|
||||||
|
vQueueDelete(spihost[host]->ret_queue);
|
||||||
|
}
|
||||||
if (spihost[host]->dma_enabled) {
|
if (spihost[host]->dma_enabled) {
|
||||||
spicommon_dma_chan_free(host);
|
spicommon_dma_chan_free(host);
|
||||||
free(spihost[host]->hal.dmadesc_tx);
|
free(spihost[host]->hal.dmadesc_tx);
|
||||||
@@ -406,7 +417,9 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi
|
|||||||
SPI_CHECK(ESP_OK == spi_slave_setup_priv_trans(host, &priv_trans), "slave setup priv_trans failed", ESP_ERR_NO_MEM);
|
SPI_CHECK(ESP_OK == spi_slave_setup_priv_trans(host, &priv_trans), "slave setup priv_trans failed", ESP_ERR_NO_MEM);
|
||||||
|
|
||||||
r = xQueueSend(spihost[host]->trans_queue, (void *)&priv_trans, ticks_to_wait);
|
r = xQueueSend(spihost[host]->trans_queue, (void *)&priv_trans, ticks_to_wait);
|
||||||
if (!r) return ESP_ERR_TIMEOUT;
|
if (!r) {
|
||||||
|
return ESP_ERR_TIMEOUT;
|
||||||
|
}
|
||||||
esp_intr_enable(spihost[host]->intr);
|
esp_intr_enable(spihost[host]->intr);
|
||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
@@ -512,23 +525,28 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_
|
|||||||
|
|
||||||
spi_slave_trans_priv_t priv_trans;
|
spi_slave_trans_priv_t priv_trans;
|
||||||
r = xQueueReceive(spihost[host]->ret_queue, (void *)&priv_trans, ticks_to_wait);
|
r = xQueueReceive(spihost[host]->ret_queue, (void *)&priv_trans, ticks_to_wait);
|
||||||
if (!r) return ESP_ERR_TIMEOUT;
|
if (!r) {
|
||||||
|
return ESP_ERR_TIMEOUT;
|
||||||
|
}
|
||||||
|
|
||||||
spi_slave_uninstall_priv_trans(host, &priv_trans);
|
spi_slave_uninstall_priv_trans(host, &priv_trans);
|
||||||
*trans_desc = priv_trans.trans;
|
*trans_desc = priv_trans.trans;
|
||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
||||||
{
|
{
|
||||||
esp_err_t ret;
|
esp_err_t ret;
|
||||||
spi_slave_transaction_t *ret_trans;
|
spi_slave_transaction_t *ret_trans;
|
||||||
//ToDo: check if any spi transfers in flight
|
//ToDo: check if any spi transfers in flight
|
||||||
ret = spi_slave_queue_trans(host, trans_desc, ticks_to_wait);
|
ret = spi_slave_queue_trans(host, trans_desc, ticks_to_wait);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
ret = spi_slave_get_trans_result(host, &ret_trans, ticks_to_wait);
|
ret = spi_slave_get_trans_result(host, &ret_trans, ticks_to_wait);
|
||||||
if (ret != ESP_OK) return ret;
|
if (ret != ESP_OK) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
assert(ret_trans == trans_desc);
|
assert(ret_trans == trans_desc);
|
||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
@@ -556,7 +574,9 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
|
|||||||
bool use_dma = host->dma_enabled;
|
bool use_dma = host->dma_enabled;
|
||||||
if (host->cur_trans.trans) {
|
if (host->cur_trans.trans) {
|
||||||
// When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready.
|
// When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready.
|
||||||
if (use_dma) freeze_cs(host);
|
if (use_dma) {
|
||||||
|
freeze_cs(host);
|
||||||
|
}
|
||||||
|
|
||||||
spi_slave_hal_store_result(hal);
|
spi_slave_hal_store_result(hal);
|
||||||
host->cur_trans.trans->trans_len = spi_slave_hal_get_rcv_bitlen(hal);
|
host->cur_trans.trans->trans_len = spi_slave_hal_get_rcv_bitlen(hal);
|
||||||
@@ -579,7 +599,9 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
|
|||||||
assert(ret == ESP_OK);
|
assert(ret == ESP_OK);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans.trans);
|
if (host->cfg.post_trans_cb) {
|
||||||
|
host->cfg.post_trans_cb(host->cur_trans.trans);
|
||||||
|
}
|
||||||
|
|
||||||
if (!(host->cfg.flags & SPI_SLAVE_NO_RETURN_RESULT)) {
|
if (!(host->cfg.flags & SPI_SLAVE_NO_RETURN_RESULT)) {
|
||||||
xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield);
|
xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield);
|
||||||
@@ -595,7 +617,9 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
|
|||||||
if (spicommon_dmaworkaround_reset_in_progress()) {
|
if (spicommon_dmaworkaround_reset_in_progress()) {
|
||||||
//We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr.
|
//We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr.
|
||||||
esp_intr_disable(host->intr);
|
esp_intr_disable(host->intr);
|
||||||
if (do_yield) portYIELD_FROM_ISR();
|
if (do_yield) {
|
||||||
|
portYIELD_FROM_ISR();
|
||||||
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@@ -637,7 +661,11 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
|
|||||||
|
|
||||||
//Kick off transfer
|
//Kick off transfer
|
||||||
spi_slave_hal_user_start(hal);
|
spi_slave_hal_user_start(hal);
|
||||||
if (host->cfg.post_setup_cb) host->cfg.post_setup_cb(priv_trans.trans);
|
if (host->cfg.post_setup_cb) {
|
||||||
|
host->cfg.post_setup_cb(priv_trans.trans);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (do_yield) {
|
||||||
|
portYIELD_FROM_ISR();
|
||||||
}
|
}
|
||||||
if (do_yield) portYIELD_FROM_ISR();
|
|
||||||
}
|
}
|
||||||
|
@@ -1591,7 +1591,6 @@ void test_add_device_slave(void)
|
|||||||
|
|
||||||
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test multiple devices", "[spi_ms]", test_add_device_master, test_add_device_slave);
|
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test multiple devices", "[spi_ms]", test_add_device_master, test_add_device_slave);
|
||||||
|
|
||||||
|
|
||||||
#if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
|
#if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
|
||||||
|
|
||||||
#define TEST_ISR_CNT 100
|
#define TEST_ISR_CNT 100
|
||||||
|
Reference in New Issue
Block a user