diff --git a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c index 7b0fffabd8..9a97b96597 100644 --- a/components/esp_hw_support/port/esp32c61/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c61/cpu_region_protect.c @@ -56,17 +56,13 @@ static void esp_cpu_configure_invalid_regions(void) // This entry is also required to be set using PMA because the region needs to be configured as cacheable. PMA_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX); - // 6. Gap between D_Cache & LP_RAM + // 6. Gap between D_Cache & peripheral addresses PMA_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(9, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE); + PMA_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE); - // 7. Gap between LP memory & peripheral addresses - PMA_ENTRY_SET_TOR(10, SOC_RTC_IRAM_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(11, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE); - - // 8. End of address space - PMA_ENTRY_SET_TOR(12, SOC_PERIPHERAL_HIGH, PMA_NONE); - PMA_ENTRY_SET_TOR(13, UINT32_MAX, PMA_TOR | PMA_NONE); + // 7. End of address space + PMA_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE); + PMA_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE); } void esp_cpu_configure_region_protection(void) @@ -186,26 +182,8 @@ void esp_cpu_configure_region_protection(void) _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I/D_Cache region"); #endif - // 5. LP memory -#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD - extern int _rtc_text_end; - /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits - * Bootloader might have given extra permissions and those won't be cleared - */ - PMP_ENTRY_CFG_RESET(10); - PMP_ENTRY_CFG_RESET(11); - PMP_ENTRY_CFG_RESET(12); - PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE); - PMP_ENTRY_SET(11, (int)&_rtc_text_end, PMP_TOR | RX); - PMP_ENTRY_SET(12, SOC_RTC_IRAM_HIGH, PMP_TOR | RW); -#else - const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH); - PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | CONDITIONAL_RWX); - _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region"); -#endif - - // 6. Peripheral addresses - const uint32_t pmpaddr13 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH); - PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | RW); + // 5. Peripheral addresses + const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH); + PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | RW); _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region"); } diff --git a/components/esp_system/ld/esp32c61/memory.ld.in b/components/esp_system/ld/esp32c61/memory.ld.in index 845c9d55a9..011f755f9d 100644 --- a/components/esp_system/ld/esp32c61/memory.ld.in +++ b/components/esp_system/ld/esp32c61/memory.ld.in @@ -60,20 +60,6 @@ MEMORY /* (See irom_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - /** - * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 - */ - lp_ram_seg(RW) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM - - /* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value. - It reserves the amount of LP memory that we use for this memory segment. - This segment is intended for keeping: - - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). - - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). - The aim of this is to keep data that will not be moved around and have a fixed address. - */ - lp_reserved_seg(RW) : org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM - /* PSRAM seg */ extern_ram_seg(RWX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 } @@ -81,19 +67,6 @@ MEMORY /* Heap ends at top of sram_seg */ _heap_end = 0x40000000; -_data_seg_org = ORIGIN(rtc_data_seg); - -/** - * The lines below define location alias for .rtc.data section - * C61 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section - * Thus, the following region segments are not configurable like on other targets - */ -REGION_ALIAS("rtc_iram_seg", lp_ram_seg ); -REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); -REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); -REGION_ALIAS("rtc_data_location", rtc_iram_seg ); -REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg ); - #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("default_code_seg", irom_seg); #else diff --git a/components/esp_system/ld/esp32c61/sections.ld.in b/components/esp_system/ld/esp32c61/sections.ld.in index 19514c8f7b..f69dd45f7f 100644 --- a/components/esp_system/ld/esp32c61/sections.ld.in +++ b/components/esp_system/ld/esp32c61/sections.ld.in @@ -11,148 +11,6 @@ ENTRY(call_start_cpu0); SECTIONS { - /** - * RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - /* Align the start of RTC code region as per PMP granularity - * this ensures we do not overwrite the permissions for any potential previous - * region regardless of its end alignment - */ - ALIGNED_SYMBOL(_esp_pmp_align_size, _rtc_fast_start) - ALIGNED_SYMBOL(_esp_pmp_align_size, _rtc_text_start) - - *(.rtc.entry.text) - - mapping[rtc_text] - - *rtc_wake_stub*.*(.text .text.*) - *(.rtc_text_end_test) - - /* Align the end of RTC code region as per PMP granularity */ - . = ALIGN(_esp_pmp_align_size); - - _rtc_text_end = ABSOLUTE(.); - } > lp_ram_seg - - /** - * This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : - { - ALIGNED_SYMBOL(4, _rtc_force_fast_start) - - mapping[rtc_force_fast] - - *(.rtc.force_fast .rtc.force_fast.*) - - ALIGNED_SYMBOL(4, _rtc_force_fast_end) - } > lp_ram_seg - - /** - * RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - - mapping[rtc_data] - - *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*) - - _rtc_data_end = ABSOLUTE(.); - } > lp_ram_seg - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - - *rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*) - *rtc_wake_stub*.*(COMMON) - - mapping[rtc_bss] - - _rtc_bss_end = ABSOLUTE(.); - } > lp_ram_seg - - /** - * This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - */ - .rtc_noinit (NOLOAD): - { - ALIGNED_SYMBOL(4, _rtc_noinit_start) - - *(.rtc_noinit .rtc_noinit.*) - - ALIGNED_SYMBOL(4, _rtc_noinit_end) - } > lp_ram_seg - - /** - * This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - ALIGNED_SYMBOL(4, _rtc_force_slow_start) - - *(.rtc.force_slow .rtc.force_slow.*) - - ALIGNED_SYMBOL(4, _rtc_force_slow_end) - } > lp_ram_seg - - /** - * This section holds RTC data that should have fixed addresses. - * The data are not initialized at power-up and are retained during deep - * sleep. - */ - .rtc_reserved (NOLOAD): - { - ALIGNED_SYMBOL(4, _rtc_reserved_start) - - /** - * New data can only be added here to ensure existing data are not moved. - * Because data have adhered to the end of the segment and code is relied - * on it. - * >> put new data here << - */ - - *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) - KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) - - _rtc_reserved_end = ABSOLUTE(.); - } > rtc_reserved_seg - - _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; - ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), - "RTC reserved segment data does not fit.") - - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) - ? (_rtc_force_slow_end - _rtc_data_start) - : (_rtc_force_slow_end - _rtc_force_slow_start); - - _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) - ? (_rtc_force_fast_end - _rtc_fast_start) - : (_rtc_noinit_end - _rtc_fast_start); - - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), - "RTC_SLOW segment data does not fit.") - - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), - "RTC_FAST segment data does not fit.") - .iram0.text : { _iram_start = ABSOLUTE(.); diff --git a/components/hal/esp32c61/include/hal/clk_tree_ll.h b/components/hal/esp32c61/include/hal/clk_tree_ll.h index 69af5794c8..ff20c963f1 100644 --- a/components/hal/esp32c61/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c61/include/hal/clk_tree_ll.h @@ -547,6 +547,28 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v return REG_READ(RTC_SLOW_CLK_CAL_REG); } +/** + * @brief Store rtc_fix_us in RTC storage register + * + * @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes + */ +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) +{ + // TODO IDF-11022 + return; +} + +/** + * @brief Load the rtc_fix_ticks from RTC storage register + * + * @return The value used to correct the time obtained from the rtc timer when the calibration value changes + */ +static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) +{ + // TODO IDF-11022 + return 0; +} + #ifdef __cplusplus } #endif diff --git a/components/heap/port/esp32c61/memory_layout.c b/components/heap/port/esp32c61/memory_layout.c index 8d574127e9..31fe2689ea 100644 --- a/components/heap/port/esp32c61/memory_layout.c +++ b/components/heap/port/esp32c61/memory_layout.c @@ -77,7 +77,6 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_m extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; -extern int _rtc_reserved_start, _rtc_reserved_end; /** * Reserved memory regions. @@ -90,9 +89,3 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d // Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code); - -#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP -SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); -#endif - -SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index ea4d47d64f..7ff622e2f5 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -51,14 +51,6 @@ config SOC_EFUSE_SUPPORTED bool default y -config SOC_RTC_FAST_MEM_SUPPORTED - bool - default y - -config SOC_RTC_MEM_SUPPORTED - bool - default y - config SOC_GPSPI_SUPPORTED bool default y diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index 01ed3d40db..09740fe84a 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -160,12 +160,6 @@ #define SOC_IRAM_HIGH 0x40850000 #define SOC_DRAM_LOW 0x40800000 #define SOC_DRAM_HIGH 0x40850000 -#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C61 only has 16k LP memory -#define SOC_RTC_IRAM_HIGH 0x50004000 -#define SOC_RTC_DRAM_LOW 0x50000000 -#define SOC_RTC_DRAM_HIGH 0x50004000 -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50004000 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40800000 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 3980dedbcb..00f1b32b98 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -33,8 +33,6 @@ #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_SUPPORTED 1 -#define SOC_RTC_FAST_MEM_SUPPORTED 1 -#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274 // \#define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313 #define SOC_GPSPI_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1