feat(mcpwm): add support for ESP32P4

components/driver/Kconfig

@@ -398,39 +398,7 @@ menu "Driver Configurations"
                 Note that, this option only controls the RMT driver log, won't affect other drivers.
     endmenu # RMT Configuration
 
-    menu "MCPWM Configuration"
+    orsource "./mcpwm/Kconfig.mcpwm"
-        depends on SOC_MCPWM_SUPPORTED
-        config MCPWM_ISR_IRAM_SAFE
-            bool "Place MCPWM ISR function into IRAM"
-            default n
-            help
-                This will ensure the MCPWM interrupt handle is IRAM-Safe, allow to avoid flash
-                cache misses, and also be able to run whilst the cache is disabled.
-                (e.g. SPI Flash write)
-
-        config MCPWM_CTRL_FUNC_IN_IRAM
-            bool "Place MCPWM control functions into IRAM"
-            default n
-            help
-                Place MCPWM control functions (like set_compare_value) into IRAM,
-                so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
-                Enabling this option can improve driver performance as well.
-
-        config MCPWM_SUPPRESS_DEPRECATE_WARN
-            bool "Suppress leagcy driver deprecated warning"
-            default n
-            help
-                Wether to suppress the deprecation warnings when using legacy MCPWM driver (driver/mcpwm.h).
-                If you want to continue using the legacy driver, and don't want to see related deprecation warnings,
-                you can enable this option.
-
-        config MCPWM_ENABLE_DEBUG_LOG
-            bool "Enable debug log"
-            default n
-            help
-                Wether to enable the debug log message for MCPWM driver.
-                Note that, this option only controls the MCPWM driver log, won't affect other drivers.
-    endmenu # MCPWM Configuration
 
     menu "I2S Configuration"
         depends on SOC_I2S_SUPPORTED

components/driver/mcpwm/Kconfig.mcpwm

@@ -0,0 +1,33 @@
+menu "MCPWM Configuration"
+    depends on SOC_MCPWM_SUPPORTED
+    config MCPWM_ISR_IRAM_SAFE
+        bool "Place MCPWM ISR function into IRAM"
+        default n
+        help
+            This will ensure the MCPWM interrupt handle is IRAM-Safe, allow to avoid flash
+            cache misses, and also be able to run whilst the cache is disabled.
+            (e.g. SPI Flash write)
+
+    config MCPWM_CTRL_FUNC_IN_IRAM
+        bool "Place MCPWM control functions into IRAM"
+        default n
+        help
+            Place MCPWM control functions (like set_compare_value) into IRAM,
+            so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
+            Enabling this option can improve driver performance as well.
+
+    config MCPWM_SUPPRESS_DEPRECATE_WARN
+        bool "Suppress leagcy driver deprecated warning"
+        default n
+        help
+            Wether to suppress the deprecation warnings when using legacy MCPWM driver (driver/mcpwm.h).
+            If you want to continue using the legacy driver, and don't want to see related deprecation warnings,
+            you can enable this option.
+
+    config MCPWM_ENABLE_DEBUG_LOG
+        bool "Enable debug log"
+        default n
+        help
+            Wether to enable the debug log message for MCPWM driver.
+            Note that, this option only controls the MCPWM driver log, won't affect other drivers.
+endmenu # MCPWM Configuration

components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -111,9 +111,9 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]")
 
     printf("simulate GPIO capture signal\r\n");
     gpio_set_level(cap_gpio, 1);
-    vTaskDelay(pdMS_TO_TICKS(10));
+    esp_rom_delay_us(10 * 1000);
     gpio_set_level(cap_gpio, 0);
-    vTaskDelay(pdMS_TO_TICKS(10));
+    esp_rom_delay_us(10 * 1000);
     printf("capture value: Pos=%"PRIu32", Neg=%"PRIu32"\r\n", cap_value[0], cap_value[1]);
     uint32_t clk_src_res;
     TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res));
@@ -176,10 +176,9 @@ TEST_CASE("mcpwm_capture_software_catch", "[mcpwm]")
 
     printf("trigger software catch\r\n");
     TEST_ESP_OK(mcpwm_capture_channel_trigger_soft_catch(cap_channel));
-    vTaskDelay(pdMS_TO_TICKS(10));
+    esp_rom_delay_us(10 * 1000);
     TEST_ESP_OK(mcpwm_capture_channel_trigger_soft_catch(cap_channel));
-    vTaskDelay(pdMS_TO_TICKS(10));
+    esp_rom_delay_us(10 * 1000);
-
     // check user data
     TEST_ASSERT_EQUAL(2, test_callback_data.cap_data_index);
     uint32_t delta = test_callback_data.cap_data[1] - test_callback_data.cap_data[0];

components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c

@@ -100,7 +100,7 @@ TEST_CASE("mcpwm_comparator_event_callback", "[mcpwm]")
     TEST_ESP_OK(mcpwm_timer_enable(timer));
     TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
 
-    vTaskDelay(pdMS_TO_TICKS(1000));
+    esp_rom_delay_us(1000 * 1000);
     TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY));
     printf("compare_counts=%"PRIu32"\r\n", compare_counts);
     // the timer period is 10ms, the expected compare_counts = 1s/10ms = 100

components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c

@@ -169,7 +169,7 @@ TEST_CASE("mcpwm_timer_event_callbacks", "[mcpwm]")
     TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
 
     printf("wait for full and empty events\r\n");
-    bits = xEventGroupWaitBits(event_group, TEST_MCPWM_TIMER_EVENT_BIT_FULL | TEST_MCPWM_TIMER_EVENT_BIT_EMPTY, pdTRUE, pdTRUE, pdMS_TO_TICKS(1050));
+    bits = xEventGroupWaitBits(event_group, TEST_MCPWM_TIMER_EVENT_BIT_FULL | TEST_MCPWM_TIMER_EVENT_BIT_EMPTY, pdTRUE, pdTRUE, pdMS_TO_TICKS(1300));
     TEST_ASSERT_EQUAL(TEST_MCPWM_TIMER_EVENT_BIT_FULL | TEST_MCPWM_TIMER_EVENT_BIT_EMPTY, bits);
 
     printf("stop timer and wait for event\r\n");

components/hal/esp32p4/include/hal/clk_gate_ll.h

@@ -77,9 +77,9 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
     case PERIPH_CAM_MODULE:
         return HP_SYS_CLKRST_REG_CAM_CLK_EN;
     case PERIPH_MCPWM0_MODULE:
-        return HP_SYS_CLKRST_REG_MCPWM0_CLK_EN;
+        return HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN;
     case PERIPH_MCPWM1_MODULE:
-        return HP_SYS_CLKRST_REG_MCPWM1_CLK_EN;
+        return HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN;
     case PERIPH_TIMG0_MODULE:
         return HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN;
     case PERIPH_TIMG1_MODULE:
@@ -264,6 +264,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
         return HP_SYS_CLKRST_PERI_CLK_CTRL119_REG;
     case PERIPH_MCPWM0_MODULE:
     case PERIPH_MCPWM1_MODULE:
+        return HP_SYS_CLKRST_SOC_CLK_CTRL2_REG;
     case PERIPH_TIMG0_MODULE:
         return HP_SYS_CLKRST_PERI_CLK_CTRL20_REG;
     case PERIPH_TIMG1_MODULE:

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -23,6 +23,10 @@ config SOC_GPTIMER_SUPPORTED
     bool
     default y
 
+config SOC_MCPWM_SUPPORTED
+    bool
+    default y
+
 config SOC_ASYNC_MEMCPY_SUPPORTED
     bool
     default y
@@ -485,7 +489,7 @@ config SOC_RMT_SUPPORT_RC_FAST
 
 config SOC_MCPWM_GROUPS
     int
-    default 1
+    default 2
 
 config SOC_MCPWM_TIMERS_PER_GROUP
     int

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -228,6 +228,52 @@ typedef enum {
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of MCPWM Timer
+ */
+#if SOC_CLK_TREE_SUPPORTED
+#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+#else
+#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_XTAL}
+#endif
+
+/**
+ * @brief Type of MCPWM timer clock source
+ */
+typedef enum {
+    MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    MCPWM_TIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
+    MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+#if SOC_CLK_TREE_SUPPORTED
+    MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
+#else
+    MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default choice */
+#endif // SOC_CLK_TREE_SUPPORTED
+} soc_periph_mcpwm_timer_clk_src_t;
+
+/**
+ * @brief Array initializer for all supported clock sources of MCPWM Capture Timer
+ */
+#if SOC_CLK_TREE_SUPPORTED
+#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+#else
+#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_XTAL}
+#endif
+
+/**
+ * @brief Type of MCPWM capture clock source
+ */
+typedef enum {
+    MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    MCPWM_CAPTURE_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
+    MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+#if SOC_CLK_TREE_SUPPORTED
+    MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,  /*!< Select PLL_F160M as the default choice */
+#else
+    MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default choice */
+#endif // SOC_CLK_TREE_SUPPORTED
+} soc_periph_mcpwm_capture_clk_src_t;
+
 ///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

components/soc/esp32p4/include/soc/soc_caps.h

@@ -34,7 +34,7 @@
 #define SOC_AXI_GDMA_SUPPORTED          1
 #define SOC_GPTIMER_SUPPORTED           1
 // #define SOC_PCNT_SUPPORTED              1  //TODO: IDF-7475
-// #define SOC_MCPWM_SUPPORTED             1  //TODO: IDF-7493
+#define SOC_MCPWM_SUPPORTED                1
 // #define SOC_TWAI_SUPPORTED              1  //TODO: IDF-7470
 // #define SOC_ETM_SUPPORTED               1  //TODO: IDF-7478
 // #define SOC_PARLIO_SUPPORTED            1  //TODO: IDF-7471, TODO: IDF-7472
@@ -273,7 +273,7 @@
 #define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
 
 /*-------------------------- MCPWM CAPS --------------------------------------*/
-#define SOC_MCPWM_GROUPS                     (1U)   ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
+#define SOC_MCPWM_GROUPS                     (2U)   ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
 #define SOC_MCPWM_TIMERS_PER_GROUP           (3)    ///< The number of timers that each group has
 #define SOC_MCPWM_OPERATORS_PER_GROUP        (3)    ///< The number of operators that each group has
 #define SOC_MCPWM_COMPARATORS_PER_OPERATOR   (2)    ///< The number of comparators that each operator has

components/soc/esp32p4/mcpwm_periph.c

@@ -9,5 +9,144 @@
 #include "soc/gpio_sig_map.h"
 
 const mcpwm_signal_conn_t mcpwm_periph_signals = {
-
+    .groups = {
+        [0] = {
+            .module = PERIPH_MCPWM0_MODULE,
+            .irq_id = ETS_PWM0_INTR_SOURCE,
+            .operators = {
+                [0] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = PWM0_CH0_A_PAD_OUT_IDX
+                        },
+                        [1] = {
+                            .pwm_sig = PWM0_CH0_B_PAD_OUT_IDX
+                        }
+                    }
+                },
+                [1] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = PWM0_CH1_A_PAD_OUT_IDX
+                        },
+                        [1] = {
+                            .pwm_sig = PWM0_CH1_B_PAD_OUT_IDX
+                        }
+                    }
+                },
+                [2] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = PWM0_CH2_A_PAD_OUT_IDX
+                        },
+                        [1] = {
+                            .pwm_sig = PWM0_CH2_B_PAD_OUT_IDX
+                        }
+                    }
+                }
+            },
+            .gpio_faults = {
+                [0] = {
+                    .fault_sig = PWM0_F0_PAD_IN_IDX
+                },
+                [1] = {
+                    .fault_sig = PWM0_F1_PAD_IN_IDX
+                },
+                [2] = {
+                    .fault_sig = PWM0_F2_PAD_IN_IDX
+                }
+            },
+            .captures = {
+                [0] = {
+                    .cap_sig = PWM0_CAP0_PAD_IN_IDX
+                },
+                [1] = {
+                    .cap_sig = PWM0_CAP1_PAD_IN_IDX
+                },
+                [2] = {
+                    .cap_sig = PWM0_CAP2_PAD_IN_IDX
+                }
+            },
+            .gpio_synchros = {
+                [0] = {
+                    .sync_sig = PWM0_SYNC0_PAD_IN_IDX
+                },
+                [1] = {
+                    .sync_sig = PWM0_SYNC1_PAD_IN_IDX
+                },
+                [2] = {
+                    .sync_sig = PWM0_SYNC2_PAD_IN_IDX
+                }
+            }
+        },
+        [1] = {
+            .module = PERIPH_MCPWM1_MODULE,
+            .irq_id = ETS_PWM1_INTR_SOURCE,
+            .operators = {
+                [0] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = PWM1_CH0_A_PAD_OUT_IDX
+                        },
+                        [1] = {
+                            .pwm_sig = PWM1_CH0_B_PAD_OUT_IDX
+                        }
+                    }
+                },
+                [1] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = PWM1_CH1_A_PAD_OUT_IDX
+                        },
+                        [1] = {
+                            .pwm_sig = PWM1_CH1_B_PAD_OUT_IDX
+                        }
+                    }
+                },
+                [2] = {
+                    .generators = {
+                        [0] = {
+                            .pwm_sig = PWM1_CH2_A_PAD_OUT_IDX
+                        },
+                        [1] = {
+                            .pwm_sig = PWM1_CH2_B_PAD_OUT_IDX
+                        }
+                    }
+                }
+            },
+            .gpio_faults = {
+                [0] = {
+                    .fault_sig = PWM1_F0_PAD_IN_IDX
+                },
+                [1] = {
+                    .fault_sig = PWM1_F1_PAD_IN_IDX
+                },
+                [2] = {
+                    .fault_sig = PWM1_F2_PAD_IN_IDX
+                }
+            },
+            .captures = {
+                [0] = {
+                    .cap_sig = PWM1_CAP0_PAD_IN_IDX
+                },
+                [1] = {
+                    .cap_sig = PWM1_CAP1_PAD_IN_IDX
+                },
+                [2] = {
+                    .cap_sig = PWM1_CAP2_PAD_IN_IDX
+                }
+            },
+            .gpio_synchros = {
+                [0] = {
+                    .sync_sig = PWM1_SYNC0_PAD_IN_IDX
+                },
+                [1] = {
+                    .sync_sig = PWM1_SYNC1_PAD_IN_IDX
+                },
+                [2] = {
+                    .sync_sig = PWM1_SYNC2_PAD_IN_IDX
+                }
+            }
+        }
+    }
 };