diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h b/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h
index 2f88538f45..f5b32abb40 100644
--- a/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h
+++ b/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h
@@ -94,6 +94,8 @@ typedef enum {
     USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core (hp system)*/
     USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core (hp system)*/
     JTAG_RESET             = 24,    /**<24, jtag reset CPU*/
+    RTC_PWR_GLITCH_RESET   = 25,    /**<25, RTC power glitch reset system*/
+    CPU_LOCKUP_RESET       = 26,    /**<26, cpu lockup reset*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -114,6 +116,8 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC
 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
 ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_PWR_GLITCH_RESET == RESET_REASON_RTC_BROWN_OUT, "RTC_PWR_GLITCH_RESET != RESET_REASON_RTC_BROWN_OUT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU_LOCKUP");
 
 typedef enum {
     NO_SLEEP        = 0,
diff --git a/components/esp_system/port/soc/esp32c61/reset_reason.c b/components/esp_system/port/soc/esp32c61/reset_reason.c
index 458cb0f585..cb485e9323 100644
--- a/components/esp_system/port/soc/esp32c61/reset_reason.c
+++ b/components/esp_system/port/soc/esp32c61/reset_reason.c
@@ -49,6 +49,7 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
     case RESET_REASON_CPU0_MWDT1:
         return ESP_RST_WDT;
 
+    case RESET_REASON_RTC_BROWN_OUT:
     case RESET_REASON_SYS_BROWN_OUT:
         return ESP_RST_BROWNOUT;
 
@@ -62,6 +63,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
     case RESET_REASON_CPU0_JTAG:
         return ESP_RST_JTAG;
 
+    case RESET_REASON_CPU_LOCKUP:
+        return ESP_RST_CPU_LOCKUP;
+
     default:
         return ESP_RST_UNKNOWN;
     }
diff --git a/components/soc/esp32c61/include/soc/reset_reasons.h b/components/soc/esp32c61/include/soc/reset_reasons.h
index d9e12683d2..e2a7c55024 100644
--- a/components/soc/esp32c61/include/soc/reset_reasons.h
+++ b/components/soc/esp32c61/include/soc/reset_reasons.h
@@ -46,6 +46,8 @@ typedef enum {
     RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core (hp system)
     RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core (hp system)
     RESET_REASON_CPU0_JTAG       = 0x18, // JTAG resets the CPU 0
+    RESET_REASON_RTC_BROWN_OUT   = 0x19, // RTC power glitch resets system
+    RESET_REASON_CPU_LOCKUP      = 0x1A, // CPU lockup resets
 } soc_reset_reason_t;