From b1bd9987fece786bffc0fd6072726cba180ae99a Mon Sep 17 00:00:00 2001 From: xuxiao Date: Tue, 12 Mar 2024 15:17:31 +0800 Subject: [PATCH 1/4] feat(phy): add esp32c5 beta3 phy support --- .../esp_coex/esp32c5/esp_coex_adapter.c | 164 +++++++++++++++ components/esp_phy/CMakeLists.txt | 2 +- .../esp32c5/include/btbb_retention_reg.h | 24 +++ .../esp_phy/esp32c5/include/phy_init_data.h | 199 ++++++++++++++++++ .../esp32c5/phy_multiple_init_data.bin | Bin 0 -> 1072 bytes components/esp_phy/lib | 2 +- components/esp_phy/src/phy_init.c | 11 +- components/esp_phy/src/phy_override.c | 10 + 8 files changed, 409 insertions(+), 3 deletions(-) create mode 100644 components/esp_coex/esp32c5/esp_coex_adapter.c create mode 100644 components/esp_phy/esp32c5/include/btbb_retention_reg.h create mode 100644 components/esp_phy/esp32c5/include/phy_init_data.h create mode 100644 components/esp_phy/esp32c5/phy_multiple_init_data.bin diff --git a/components/esp_coex/esp32c5/esp_coex_adapter.c b/components/esp_coex/esp32c5/esp_coex_adapter.c new file mode 100644 index 0000000000..1c41974a90 --- /dev/null +++ b/components/esp_coex/esp32c5/esp_coex_adapter.c @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/queue.h" +#include "freertos/semphr.h" +#include "freertos/portmacro.h" +#include "esp_heap_caps.h" +#include "esp_timer.h" +#include "soc/rtc.h" +#include "esp_private/esp_clk.h" +#include "private/esp_coexist_adapter.h" +#include "esp32c5/rom/ets_sys.h" + +#define TAG "esp_coex_adapter" + +#define OSI_FUNCS_TIME_BLOCKING 0xffffffff + +bool IRAM_ATTR esp_coex_common_env_is_chip_wrapper(void) +{ +#ifdef CONFIG_IDF_ENV_FPGA + return false; +#else + return true; +#endif +} + +void *esp_coex_common_spin_lock_create_wrapper(void) +{ + portMUX_TYPE tmp = portMUX_INITIALIZER_UNLOCKED; + void *mux = malloc(sizeof(portMUX_TYPE)); + + if (mux) { + memcpy(mux, &tmp, sizeof(portMUX_TYPE)); + return mux; + } + return NULL; +} + +uint32_t IRAM_ATTR esp_coex_common_int_disable_wrapper(void *wifi_int_mux) +{ + if (xPortInIsrContext()) { + portENTER_CRITICAL_ISR(wifi_int_mux); + } else { + portENTER_CRITICAL(wifi_int_mux); + } + + return 0; +} + +void IRAM_ATTR esp_coex_common_int_restore_wrapper(void *wifi_int_mux, uint32_t tmp) +{ + if (xPortInIsrContext()) { + portEXIT_CRITICAL_ISR(wifi_int_mux); + } else { + portEXIT_CRITICAL(wifi_int_mux); + } +} + +void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void) +{ + portYIELD_FROM_ISR(); +} + +void *esp_coex_common_semphr_create_wrapper(uint32_t max, uint32_t init) +{ + return (void *)xSemaphoreCreateCounting(max, init); +} + +void esp_coex_common_semphr_delete_wrapper(void *semphr) +{ + vSemaphoreDelete(semphr); +} + +int32_t esp_coex_common_semphr_take_wrapper(void *semphr, uint32_t block_time_tick) +{ + if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) { + return (int32_t)xSemaphoreTake(semphr, portMAX_DELAY); + } else { + return (int32_t)xSemaphoreTake(semphr, block_time_tick); + } +} + +int32_t esp_coex_common_semphr_give_wrapper(void *semphr) +{ + return (int32_t)xSemaphoreGive(semphr); +} + +void IRAM_ATTR esp_coex_common_timer_disarm_wrapper(void *timer) +{ + ets_timer_disarm(timer); +} + +void esp_coex_common_timer_done_wrapper(void *ptimer) +{ + ets_timer_done(ptimer); +} + +void esp_coex_common_timer_setfn_wrapper(void *ptimer, void *pfunction, void *parg) +{ + ets_timer_setfn(ptimer, pfunction, parg); +} + +void IRAM_ATTR esp_coex_common_timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repeat) +{ + ets_timer_arm_us(ptimer, us, repeat); +} + +uint32_t esp_coex_common_clk_slowclk_cal_get_wrapper(void) +{ + /* The bit width of WiFi light sleep clock calibration is 12 while the one of + * system is 19. It should shift 19 - 12 = 7. + */ + return (esp_clk_slowclk_cal_get() >> (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH)); +} + +void *IRAM_ATTR esp_coex_common_malloc_internal_wrapper(size_t size) +{ + return heap_caps_malloc(size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); +} + +/* static wrapper */ + +static int32_t IRAM_ATTR esp_coex_semphr_take_from_isr_wrapper(void *semphr, void *hptw) +{ + return (int32_t)xSemaphoreTakeFromISR(semphr, hptw); +} + +static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, void *hptw) +{ + return (int32_t)xSemaphoreGiveFromISR(semphr, hptw); +} + +coex_adapter_funcs_t g_coex_adapter_funcs = { + ._version = COEX_ADAPTER_VERSION, + ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, + ._semphr_create = esp_coex_common_semphr_create_wrapper, + ._semphr_delete = esp_coex_common_semphr_delete_wrapper, + ._semphr_take_from_isr = esp_coex_semphr_take_from_isr_wrapper, + ._semphr_give_from_isr = esp_coex_semphr_give_from_isr_wrapper, + ._semphr_take = esp_coex_common_semphr_take_wrapper, + ._semphr_give = esp_coex_common_semphr_give_wrapper, + ._is_in_isr = xPortInIsrContext, + ._malloc_internal = esp_coex_common_malloc_internal_wrapper, + ._free = free, + ._esp_timer_get_time = esp_timer_get_time, + ._env_is_chip = esp_coex_common_env_is_chip_wrapper, + ._timer_disarm = esp_coex_common_timer_disarm_wrapper, + ._timer_done = esp_coex_common_timer_done_wrapper, + ._timer_setfn = esp_coex_common_timer_setfn_wrapper, + ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, + ._magic = COEX_ADAPTER_MAGIC, +}; diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index 11c4b10e0c..d542d6ab51 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -4,7 +4,7 @@ if(${idf_target} STREQUAL "linux") return() # This component is not supported by the POSIX/Linux simulator endif() -if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c5" OR IDF_TARGET STREQUAL "esp32c61") +if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c61") # TODO: IDF-7460, IDF-8851, IDF-9553 return() endif() diff --git a/components/esp_phy/esp32c5/include/btbb_retention_reg.h b/components/esp_phy/esp32c5/include/btbb_retention_reg.h new file mode 100644 index 0000000000..fbb3997296 --- /dev/null +++ b/components/esp_phy/esp32c5/include/btbb_retention_reg.h @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// btbb sleep retention reg + +#define BB_PART_0_SIZE 93 +#define BB_PART_1_SIZE 62 +#define BB_PART_2_SIZE 19 +#define BB_PART_0_ADDR 0x600A2000 +#define BB_PART_1_ADDR 0x600A2800 +#define BB_PART_2_ADDR 0x600A2C00 + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_phy/esp32c5/include/phy_init_data.h b/components/esp_phy/esp32c5/include/phy_init_data.h new file mode 100644 index 0000000000..112b4e9a00 --- /dev/null +++ b/components/esp_phy/esp32c5/include/phy_init_data.h @@ -0,0 +1,199 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef PHY_INIT_DATA_H +#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */ +#include "esp_phy_init.h" +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// constrain a value between 'low' and 'high', inclusive +#define LIMIT(val, low, high) ((val < low) ? low : (val > high) ? high : val) + +#define PHY_INIT_MAGIC "PHYINIT" + +// define the lowest tx power as LOWEST_PHY_TX_POWER +#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52) +#define PHY_TX_POWER_OFFSET 2 +#define PHY_TX_POWER_NUM 14 + +#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN +#define PHY_CRC_ALGORITHM 1 +#define PHY_COUNTRY_CODE_LEN 2 +#define PHY_INIT_DATA_TYPE_OFFSET 126 +#define PHY_SUPPORT_MULTIPLE_BIN_OFFSET 125 +#endif + + +static const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_MAGIC; + +/** + * @brief Structure containing default recommended PHY initialization parameters. + */ +static const esp_phy_init_data_t phy_init_data= { { + 0x01, + 0x00, + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + 0x00, + 0x00, + 0x00, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0x70 +} }; + +static const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC; + +#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN +/** + * @brief PHY init data control infomation structure + */ +typedef struct { + uint8_t control_info_checksum[4]; /*!< 4-byte control infomation checksum */ + uint8_t multiple_bin_checksum[4]; /*!< 4-byte multiple bin checksum */ + uint8_t check_algorithm; /*!< check algorithm */ + uint8_t version; /*!< PHY init data bin version */ + uint8_t number; /*!< PHY init data bin number */ + uint8_t length[2]; /*!< Length of each PHY init data bin */ + uint8_t reserved[19]; /*!< 19-byte reserved */ +} __attribute__ ((packed)) phy_control_info_data_t; + +/** + * @brief Country corresponds to PHY init data type structure + */ +typedef struct { + char cc[PHY_COUNTRY_CODE_LEN]; + uint8_t type; +} phy_country_to_bin_type_t; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PHY_INIT_DATA_H */ diff --git a/components/esp_phy/esp32c5/phy_multiple_init_data.bin b/components/esp_phy/esp32c5/phy_multiple_init_data.bin new file mode 100644 index 0000000000000000000000000000000000000000..0f754a2c496b5cf7b712c49b15e83a02082692f4 GIT binary patch literal 1072 zcmWIWi1hUH3}Ikk2nY!9@$vBS@Nn^Rb8}+&PdZ>A7cep`gSlh6%ptaIvLd;R4D1XI zSj|IsC!-rO`0s!WaPhDjOjwYSF%~nN7;SuDz{bYrzljG7n3$NL^ISl{#KeTKRajLp zGJVBnzYP-jj~p0oxOiAiCoIUwY>3T%nD>2X?tc~yEcPQuxC1U9gMtN-8VGw8s|rTe k1z79{#VH))wO Date: Tue, 26 Mar 2024 13:52:25 +0800 Subject: [PATCH 2/4] fix(esp_hw_support): fix zb/bt shared bb dependency for ieee154 --- components/esp_hw_support/modem_clock.c | 19 +++++++++++++------ components/esp_hw_support/periph_ctrl.c | 2 +- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index 19749c11ba..b48f550210 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -31,7 +31,9 @@ typedef enum { MODEM_CLOCK_ETM, #if SOC_BT_SUPPORTED MODEM_CLOCK_BLE_MAC, - MODEM_CLOCK_BLE_BB, +#endif +#if SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED + MODEM_CLOCK_BT_I154_COMMON_BB, #endif #if SOC_IEEE802154_SUPPORTED MODEM_CLOCK_802154_MAC, @@ -79,13 +81,16 @@ static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, modem_syscon_ll_enable_ble_timer_clock(ctx->hal->syscon_dev, enable); } -static void IRAM_ATTR modem_clock_ble_bb_configure(modem_clock_context_t *ctx, bool enable) +#endif // SOC_BT_SUPPORTED +#if SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED + +static void IRAM_ATTR modem_clock_ble_i154_bb_configure(modem_clock_context_t *ctx, bool enable) { modem_syscon_ll_enable_bt_apb_clock(ctx->hal->syscon_dev, enable); modem_syscon_ll_enable_bt_clock(ctx->hal->syscon_dev, enable); } -#endif // SOC_BT_SUPPORTED +#endif // SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED #if SOC_IEEE802154_SUPPORTED static void IRAM_ATTR modem_clock_ieee802154_mac_configure(modem_clock_context_t *ctx, bool enable) @@ -144,7 +149,9 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi [MODEM_CLOCK_ETM] = { .refs = 0, .configure = modem_clock_etm_configure }, #if SOC_BT_SUPPORTED [MODEM_CLOCK_BLE_MAC] = { .refs = 0, .configure = modem_clock_ble_mac_configure }, - [MODEM_CLOCK_BLE_BB] = { .refs = 0, .configure = modem_clock_ble_bb_configure }, +#endif +#if SOC_IEEE802154_SUPPORTED || SOC_BT_SUPPORTED + [MODEM_CLOCK_BT_I154_COMMON_BB] = { .refs = 0, .configure = modem_clock_ble_i154_bb_configure }, #endif #if SOC_IEEE802154_SUPPORTED [MODEM_CLOCK_802154_MAC] = { .refs = 0, .configure = modem_clock_ieee802154_mac_configure }, @@ -253,8 +260,8 @@ void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module) } #define WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_COEXIST)) -#define BLE_CLOCK_DEPS (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST)) -#define IEEE802154_CLOCK_DEPS (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST)) +#define BLE_CLOCK_DEPS (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_BT_I154_COMMON_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST)) +#define IEEE802154_CLOCK_DEPS (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_BT_I154_COMMON_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST)) #define COEXIST_CLOCK_DEPS (BIT(MODEM_CLOCK_COEXIST)) #define PHY_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_MODEM_ADC_COMMON_FE) | BIT(MODEM_CLOCK_MODEM_PRIVATE_FE)) #define I2C_ANA_MST_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER)) diff --git a/components/esp_hw_support/periph_ctrl.c b/components/esp_hw_support/periph_ctrl.c index 51aeb2ae48..238d56cf04 100644 --- a/components/esp_hw_support/periph_ctrl.c +++ b/components/esp_hw_support/periph_ctrl.c @@ -92,7 +92,7 @@ void periph_module_reset(periph_module_t periph) } #if !SOC_IEEE802154_BLE_ONLY -#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED +#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED IRAM_ATTR void wifi_bt_common_module_enable(void) { #if SOC_MODEM_CLOCK_IS_INDEPENDENT From d69c25b9972a4beab3e0e4f7d36f4a8ce62a5fee Mon Sep 17 00:00:00 2001 From: xuxiao Date: Thu, 28 Mar 2024 18:31:03 +0800 Subject: [PATCH 3/4] fix(phy): update esp32c5 phy init data --- .../esp_phy/esp32c5/include/phy_init_data.h | 272 +++++++++++++----- components/esp_phy/include/esp_phy_init.h | 10 +- 2 files changed, 207 insertions(+), 75 deletions(-) diff --git a/components/esp_phy/esp32c5/include/phy_init_data.h b/components/esp_phy/esp32c5/include/phy_init_data.h index 112b4e9a00..87734819db 100644 --- a/components/esp_phy/esp32c5/include/phy_init_data.h +++ b/components/esp_phy/esp32c5/include/phy_init_data.h @@ -26,8 +26,8 @@ extern "C" { #if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN #define PHY_CRC_ALGORITHM 1 #define PHY_COUNTRY_CODE_LEN 2 -#define PHY_INIT_DATA_TYPE_OFFSET 126 -#define PHY_SUPPORT_MULTIPLE_BIN_OFFSET 125 +#define PHY_INIT_DATA_TYPE_OFFSET 254 +#define PHY_SUPPORT_MULTIPLE_BIN_OFFSET 253 #endif @@ -44,69 +44,213 @@ static const esp_phy_init_data_t phy_init_data= { { LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, 0x00, 0x00, 0x00, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, 0, 0, 0, @@ -148,23 +292,7 @@ static const esp_phy_init_data_t phy_init_data= { { 0, 0, 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0x70 + 0x5A } }; static const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC; diff --git a/components/esp_phy/include/esp_phy_init.h b/components/esp_phy/include/esp_phy_init.h index 27041b4dae..8e0a6cf8f7 100644 --- a/components/esp_phy/include/esp_phy_init.h +++ b/components/esp_phy/include/esp_phy_init.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,11 @@ extern "C" { * @brief Structure holding PHY init parameters */ typedef struct { - uint8_t params[128]; /*!< opaque PHY initialization parameters */ +#if CONFIG_IDF_TARGET_ESP32C5 + uint8_t params[256]; /*!< opaque PHY initialization parameters */ +#else + uint8_t params[128]; /*!< opaque PHY initialization parameters */ +#endif } esp_phy_init_data_t; /** @@ -181,7 +185,7 @@ void esp_btbb_enable(void); /** * @brief Disable BTBB module * - * Dsiable BTBB module, used by IEEE802154 or Bluetooth. + * Disable BTBB module, used by IEEE802154 or Bluetooth. * Users should not call this API in their application. * */ From d2e0b9419f345785c0a1adeecc68569619baed7d Mon Sep 17 00:00:00 2001 From: zwx Date: Tue, 26 Mar 2024 19:22:47 +0800 Subject: [PATCH 4/4] fix(CI): fix CI to pass fast build app --- components/esp_coex/esp32c5/esp_coex_adapter.c | 1 - components/esp_phy/esp32c5/include/phy_init_data.h | 5 +++-- components/esp_phy/include/esp_phy_init.h | 1 + components/esp_phy/src/phy_init.c | 4 ++-- components/hal/include/hal/modem_clock_hal.h | 2 ++ tools/ci/check_public_headers_exceptions.txt | 1 + 6 files changed, 9 insertions(+), 5 deletions(-) diff --git a/components/esp_coex/esp32c5/esp_coex_adapter.c b/components/esp_coex/esp32c5/esp_coex_adapter.c index 1c41974a90..a3a27d288d 100644 --- a/components/esp_coex/esp32c5/esp_coex_adapter.c +++ b/components/esp_coex/esp32c5/esp_coex_adapter.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/components/esp_phy/esp32c5/include/phy_init_data.h b/components/esp_phy/esp32c5/include/phy_init_data.h index 87734819db..2dac61b92b 100644 --- a/components/esp_phy/esp32c5/include/phy_init_data.h +++ b/components/esp_phy/esp32c5/include/phy_init_data.h @@ -6,6 +6,7 @@ #ifndef PHY_INIT_DATA_H #define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */ +#include #include "esp_phy_init.h" #include "sdkconfig.h" @@ -299,10 +300,10 @@ static const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PH #if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN /** - * @brief PHY init data control infomation structure + * @brief PHY init data control information structure */ typedef struct { - uint8_t control_info_checksum[4]; /*!< 4-byte control infomation checksum */ + uint8_t control_info_checksum[4]; /*!< 4-byte control information checksum */ uint8_t multiple_bin_checksum[4]; /*!< 4-byte multiple bin checksum */ uint8_t check_algorithm; /*!< check algorithm */ uint8_t version; /*!< PHY init data bin version */ diff --git a/components/esp_phy/include/esp_phy_init.h b/components/esp_phy/include/esp_phy_init.h index 8e0a6cf8f7..95756568b4 100644 --- a/components/esp_phy/include/esp_phy_init.h +++ b/components/esp_phy/include/esp_phy_init.h @@ -8,6 +8,7 @@ #include #include #include "esp_err.h" +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 3bfbb4f47a..685f04f039 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -315,7 +315,7 @@ void esp_phy_disable(esp_phy_modem_t modem) #endif } #if CONFIG_IDF_TARGET_ESP32 - // Update WiFi MAC time before disalbe WiFi/BT common peripheral clock + // Update WiFi MAC time before disable WiFi/BT common peripheral clock phy_update_wifi_mac_time(true, esp_timer_get_time()); #endif // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware RNG @@ -912,7 +912,7 @@ static uint8_t phy_find_bin_type_according_country(const char* country) if (i == sizeof(s_country_code_map_type_table)/sizeof(phy_country_to_bin_type_t)) { phy_init_data_type = ESP_PHY_INIT_DATA_TYPE_DEFAULT; - ESP_LOGW(TAG, "Use the default certification code beacuse %c%c doesn't have a certificate", country[0], country[1]); + ESP_LOGW(TAG, "Use the default certification code because %c%c doesn't have a certificate", country[0], country[1]); } return phy_init_data_type; diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index 713e458ca6..e5c23df268 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -19,10 +19,12 @@ extern "C" { #endif +#if !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION typedef struct { modem_syscon_dev_t *syscon_dev; modem_lpcon_dev_t *lpcon_dev; } modem_clock_hal_context_t; +#endif #if !CONFIG_IDF_TARGET_ESP32H2 //TODO: PM-92 void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 36924700a8..72e9476416 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -31,6 +31,7 @@ components/esp_phy/esp32s2/include/phy_init_data.h components/esp_phy/esp32s3/include/phy_init_data.h components/esp_phy/esp32c3/include/phy_init_data.h components/esp_phy/esp32c2/include/phy_init_data.h +components/esp_phy/esp32c5/include/phy_init_data.h components/esp_phy/esp32c6/include/phy_init_data.h components/spi_flash/include/spi_flash_chip_issi.h