From 75ff8d7ff8cec11ad8eb438d4b4d92397ff45815 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Wed, 18 Mar 2020 12:21:08 +0800 Subject: [PATCH] spi_flash: add unit tests for qio mode --- components/spi_flash/test/test_esp_flash.c | 11 +++++-- components/spi_flash/test/test_spi_flash.c | 34 ++++++++++++++++++++ tools/unit-test-app/configs/spi_flash_qio | 2 ++ tools/unit-test-app/configs/spi_flash_qio_s2 | 3 ++ 4 files changed, 47 insertions(+), 3 deletions(-) create mode 100644 tools/unit-test-app/configs/spi_flash_qio create mode 100644 tools/unit-test-app/configs/spi_flash_qio_s2 diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/test_esp_flash.c index 6adf95fc6c..84ce6ffc73 100644 --- a/components/spi_flash/test/test_esp_flash.c +++ b/components/spi_flash/test/test_esp_flash.c @@ -13,7 +13,6 @@ #include -#include "unity.h" #include "driver/gpio.h" #include "soc/io_mux_reg.h" #include "sdkconfig.h" @@ -21,6 +20,12 @@ #include "hal/spi_flash_hal.h" #include "ccomp_timer.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/ets_sys.h" +#endif + #define FUNC_SPI 1 static uint8_t sector_buf[4096]; @@ -549,7 +554,7 @@ static bool is_mxic_chip(esp_flash_t* chip) return (spi_flash_chip_mxic_probe(chip, flash_id)==ESP_OK); } -static void test_toggle_qe(esp_flash_t* chip) +IRAM_ATTR NOINLINE_ATTR static void test_toggle_qe(esp_flash_t* chip) { bool qe; if (chip == NULL) { @@ -562,7 +567,7 @@ static void test_toggle_qe(esp_flash_t* chip) bool allow_failure = is_winbond_chip(chip) || is_mxic_chip(chip); for (int i = 0; i < 4; i ++) { - ESP_LOGI(TAG, "write qe: %d->%d", qe, !qe); + ets_printf(DRAM_STR("write qe: %d->%d\n"), qe, !qe); qe = !qe; chip->read_mode = qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD; ret = esp_flash_set_io_mode(chip, qe); diff --git a/components/spi_flash/test/test_spi_flash.c b/components/spi_flash/test/test_spi_flash.c index 8a680952fc..cb2e4d155e 100644 --- a/components/spi_flash/test/test_spi_flash.c +++ b/components/spi_flash/test/test_spi_flash.c @@ -15,6 +15,13 @@ #include "bootloader_flash.h" //for bootloader_flash_xmc_startup +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/spi_flash.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/spi_flash.h" +#endif + struct flash_test_ctx { uint32_t offset; bool fail; @@ -375,6 +382,33 @@ TEST_CASE("spi_flash deadlock with high priority busy-waiting task", "[spi_flash } #endif // portNUM_PROCESSORS > 1 +TEST_CASE("WEL is cleared after boot", "[spi_flash]") +{ + extern esp_rom_spiflash_chip_t g_rom_spiflash_chip; + uint32_t status; + esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status); + + TEST_ASSERT((status & 0x2) == 0); +} + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO +// ISSI chip has its QE bit on other chips' BP4, which may get cleared by accident +TEST_CASE("rom unlock will not erase QE bit", "[spi_flash]") +{ + extern esp_rom_spiflash_chip_t g_rom_spiflash_chip; + uint32_t status; + printf("dev_id: %08X \n", g_rom_spiflash_chip.device_id); + + if (((g_rom_spiflash_chip.device_id >> 16) & 0xff) != 0x9D) { + TEST_IGNORE_MESSAGE("This test is only for ISSI chips. Ignore."); + } + esp_rom_spiflash_unlock(); + esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status); + printf("status: %08x\n", status); + + TEST_ASSERT(status & 0x40); +} +#endif static IRAM_ATTR NOINLINE_ATTR void test_xmc_startup(void) { diff --git a/tools/unit-test-app/configs/spi_flash_qio b/tools/unit-test-app/configs/spi_flash_qio new file mode 100644 index 0000000000..106bae7d66 --- /dev/null +++ b/tools/unit-test-app/configs/spi_flash_qio @@ -0,0 +1,2 @@ +TEST_COMPONENTS=spi_flash +CONFIG_ESPTOOLPY_FLASHMODE_QIO=y diff --git a/tools/unit-test-app/configs/spi_flash_qio_s2 b/tools/unit-test-app/configs/spi_flash_qio_s2 new file mode 100644 index 0000000000..0eb8da2367 --- /dev/null +++ b/tools/unit-test-app/configs/spi_flash_qio_s2 @@ -0,0 +1,3 @@ +TEST_COMPONENTS=spi_flash +CONFIG_ESPTOOLPY_FLASHMODE_QIO=y +CONFIG_IDF_TARGET="esp32s2"