diff --git a/components/esp_hw_support/port/esp32s3/regi2c_ctrl.h b/components/esp_hw_support/port/esp32s3/regi2c_ctrl.h
index 11f6c1fc95..f5107a69b4 100644
--- a/components/esp_hw_support/port/esp32s3/regi2c_ctrl.h
+++ b/components/esp_hw_support/port/esp32s3/regi2c_ctrl.h
@@ -19,6 +19,10 @@
 #include "regi2c_dig_reg.h"
 
 /* Analog function control register */
+#define I2C_MST_ANA_CONF0_REG  0x6000E040
+#define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
+#define I2C_MST_BBPLL_STOP_FORCE_LOW  (BIT(3))
+
 #define ANA_CONFIG_REG  0x6000E044
 #define ANA_CONFIG_S    (8)
 #define ANA_CONFIG_M    (0x3FF)
diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c
index 09b8ac78fe..ae67528183 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c
@@ -204,6 +204,9 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
     uint8_t dcur;
     uint8_t dbias;
 
+    CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+
     if (pll_freq == RTC_PLL_FREQ_480M) {
         /* Set this register to let the digital part know 480M PLL is used */
         SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);