diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml index 1dbe91f913..859b46f7aa 100644 --- a/components/bootloader_support/test_apps/.build-test-rules.yml +++ b/components/bootloader_support/test_apps/.build-test-rules.yml @@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section: enable: - if: SOC_RTC_MEM_SUPPORTED == 1 reason: this feature is supported on chips that have RTC memory + disable: + - if: IDF_TARGET == "esp32c61" + temporary: true + reason: IDF-9260 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in new file mode 100644 index 0000000000..be1a58170f --- /dev/null +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,1144 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_UART_SUPPORTED + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_SUPPORTED + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_SPI_FLASH_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_40M + bool + default y + +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_ADC_DIG_CTRL_SUPPORTED + bool + default y + +config SOC_ADC_DIG_IIR_FILTER_SUPPORTED + bool + default y + +config SOC_ADC_MONITOR_SUPPORTED + bool + default y + +config SOC_ADC_DMA_SUPPORTED + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 7 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_IIR_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_CALIBRATION_V1_SUPPORTED + bool + default y + +config SOC_ADC_SELF_HW_CALI_SUPPORTED + bool + default y + +config SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED + bool + default y + +config SOC_ADC_TEMPERATURE_SHARE_INTR + bool + default y + +config SOC_ADC_SHARED_POWER + bool + default y + +config SOC_APB_BACKUP_DMA + bool + default n + +config SOC_BROWNOUT_RESET_SUPPORTED + bool + default y + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_PLIC_SUPPORTED + bool + default n + +config SOC_INT_CLIC_SUPPORTED + bool + default y + +config SOC_INT_HW_NESTED_SUPPORTED + bool + default y + +config SOC_BRANCH_PREDICTOR_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE + hex + default 0x80000000 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + +config SOC_DS_SIGNATURE_MAX_BIT_LEN + int + default 3072 + +config SOC_DS_KEY_PARAM_MD_IV_LENGTH + int + default 16 + +config SOC_DS_KEY_CHECK_MAX_WAIT_US + int + default 1100 + +config SOC_AHB_GDMA_VERSION + int + default 1 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 3 + +config SOC_GDMA_SUPPORT_ETM + bool + default y + +config SOC_ETM_GROUPS + int + default 1 + +config SOC_ETM_CHANNELS_PER_GROUP + int + default 50 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 31 + +config SOC_GPIO_ETM_EVENTS_PER_GROUP + int + default 8 + +config SOC_GPIO_ETM_TASKS_PER_GROUP + int + default 8 + +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT + bool + default y + +config SOC_GPIO_IN_RANGE_MAX + int + default 30 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 30 + +config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK + int + default 0 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000000007FFFFF00 + +config SOC_GPIO_SUPPORT_FORCE_HOLD + bool + default y + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y + +config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX + bool + default y + +config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_GPIO_IN_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_PERIPH_ALWAYS_ENABLE + bool + default y + +config SOC_I2C_NUM + int + default 1 + +config SOC_I2C_FIFO_LEN + int + default 32 + +config SOC_I2C_CMD_REG_NUM + int + default 8 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_HW_FSM_RST + bool + default y + +config SOC_I2C_SUPPORT_HW_CLR_BUS + bool + default y + +config SOC_I2C_SUPPORT_XTAL + bool + default y + +config SOC_I2C_SUPPORT_RTC + bool + default y + +config SOC_I2C_SUPPORT_10BIT_ADDR + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_BROADCAST + bool + default y + +config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH + bool + default y + +config SOC_LP_I2C_NUM + int + default 1 + +config SOC_LP_I2C_FIFO_LEN + int + default 16 + +config SOC_I2S_NUM + int + default 1 + +config SOC_I2S_HW_VERSION_2 + bool + default y + +config SOC_I2S_SUPPORTS_XTAL + bool + default y + +config SOC_I2S_SUPPORTS_PLL_F160M + bool + default y + +config SOC_I2S_SUPPORTS_PCM + bool + default y + +config SOC_I2S_SUPPORTS_PDM + bool + default y + +config SOC_I2S_SUPPORTS_PDM_TX + bool + default y + +config SOC_I2S_PDM_MAX_TX_LINES + int + default 2 + +config SOC_I2S_SUPPORTS_TDM + bool + default y + +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_CHANNEL_NUM + int + default 6 + +config SOC_LEDC_TIMER_BIT_WIDTH + int + default 20 + +config SOC_LEDC_SUPPORT_FADE_STOP + bool + default y + +config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED + bool + default y + +config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + int + default 16 + +config SOC_LEDC_FADE_PARAMS_BIT_WIDTH + int + default 10 + +config SOC_MMU_PAGE_SIZE_CONFIGURABLE + bool + default y + +config SOC_MMU_PERIPH_NUM + int + default 1 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 1 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED + bool + default n + +config SOC_MPU_MIN_REGION_SIZE + hex + default 0x20000000 + +config SOC_MPU_REGIONS_MAX_NUM + int + default 8 + +config SOC_MPU_REGION_RO_SUPPORTED + bool + default n + +config SOC_MPU_REGION_WO_SUPPORTED + bool + default n + +config SOC_PCNT_GROUPS + int + default 1 + +config SOC_PCNT_UNITS_PER_GROUP + int + default 4 + +config SOC_PCNT_CHANNELS_PER_UNIT + int + default 2 + +config SOC_PCNT_THRES_POINT_PER_UNIT + int + default 2 + +config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE + bool + default y + +config SOC_RMT_GROUPS + int + default 1 + +config SOC_RMT_TX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_RX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_CHANNELS_PER_GROUP + int + default 4 + +config SOC_RMT_MEM_WORDS_PER_CHANNEL + int + default 48 + +config SOC_RMT_SUPPORT_RX_PINGPONG + bool + default y + +config SOC_RMT_SUPPORT_RX_DEMODULATION + bool + default y + +config SOC_RMT_SUPPORT_TX_ASYNC_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_COUNT + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_SYNCHRO + bool + default y + +config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY + bool + default y + +config SOC_RMT_SUPPORT_XTAL + bool + default y + +config SOC_RMT_SUPPORT_RC_FAST + bool + default y + +config SOC_MCPWM_GROUPS + int + default 1 + +config SOC_MCPWM_TIMERS_PER_GROUP + int + default 3 + +config SOC_MCPWM_OPERATORS_PER_GROUP + int + default 3 + +config SOC_MCPWM_COMPARATORS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_GENERATORS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_TRIGGERS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_GPIO_FAULTS_PER_GROUP + int + default 3 + +config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP + bool + default y + +config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER + int + default 3 + +config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP + int + default 3 + +config SOC_MCPWM_SWSYNC_CAN_PROPAGATE + bool + default y + +config SOC_MCPWM_SUPPORT_ETM + bool + default y + +config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP + bool + default y + +config SOC_PARLIO_GROUPS + int + default 1 + +config SOC_PARLIO_TX_UNITS_PER_GROUP + int + default 1 + +config SOC_PARLIO_RX_UNITS_PER_GROUP + int + default 1 + +config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH + int + default 16 + +config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH + int + default 16 + +config SOC_PARLIO_TX_RX_SHARE_INTERRUPT + bool + default y + +config SOC_MPI_MEM_BLOCKS_NUM + int + default 4 + +config SOC_MPI_OPERATIONS_NUM + int + default 3 + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SDM_GROUPS + int + default 1 + +config SOC_SDM_CHANNELS_PER_GROUP + int + default 4 + +config SOC_SDM_CLK_SUPPORT_PLL_F80M + bool + default y + +config SOC_SDM_CLK_SUPPORT_XTAL + bool + default y + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + +config SOC_SPI_SUPPORT_CLK_PLL_F80M + bool + default y + +config SOC_SPI_SUPPORT_CLK_RC_FAST + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 16 + +config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_RESUME + bool + default y + +config SOC_SPI_MEM_SUPPORT_IDLE_INTR + bool + default y + +config SOC_SPI_MEM_SUPPORT_SW_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_CHECK_SUS + bool + default y + +config SOC_SPI_MEM_SUPPORT_WRAP + bool + default y + +config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + +config SOC_LP_TIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_LP_TIMER_BIT_WIDTH_HI + int + default 16 + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_SUPPORT_RC_FAST + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_TIMER_SUPPORT_ETM + bool + default y + +config SOC_MWDT_SUPPORT_XTAL + bool + default y + +config SOC_TWAI_CONTROLLER_NUM + int + default 2 + +config SOC_TWAI_CLK_SUPPORT_XTAL + bool + default y + +config SOC_TWAI_BRP_MIN + int + default 2 + +config SOC_TWAI_BRP_MAX + int + default 32768 + +config SOC_TWAI_SUPPORTS_RX_STATUS + bool + default y + +config SOC_EFUSE_DIS_DOWNLOAD_ICACHE + bool + default y + +config SOC_EFUSE_DIS_PAD_JTAG + bool + default y + +config SOC_EFUSE_DIS_USB_JTAG + bool + default y + +config SOC_EFUSE_DIS_DIRECT_BOOT + bool + default y + +config SOC_EFUSE_SOFT_DIS_JTAG + bool + default y + +config SOC_EFUSE_DIS_ICACHE + bool + default y + +config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK + bool + default y + +config SOC_SECURE_BOOT_V2_RSA + bool + default n + +config SOC_SECURE_BOOT_V2_ECC + bool + default y + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS + bool + default y + +config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + bool + default y + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 64 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED + bool + default y + +config SOC_UART_NUM + int + default 3 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_LP_NUM + int + default 1 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_LP_UART_FIFO_LEN + int + default 16 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_PLL_F80M_CLK + bool + default y + +config SOC_UART_SUPPORT_RTC_CLK + bool + default y + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_SUPPORT_WAKEUP_INT + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_COEX_HW_PTI + bool + default y + +config SOC_EXTERNAL_COEX_ADVANCE + bool + default y + +config SOC_EXTERNAL_COEX_LEADER_TX_LINE + bool + default n + +config SOC_PHY_DIG_REGS_MEM_SIZE + int + default 21 + +config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH + int + default 12 + +config SOC_PM_SUPPORT_WIFI_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_BEACON_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_BT_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_HP_AON_PD + bool + default y + +config SOC_PM_SUPPORT_MAC_BB_PD + bool + default y + +config SOC_PM_SUPPORT_RTC_PERIPH_PD + bool + default y + +config SOC_PM_SUPPORT_PMU_MODEM_STATE + bool + default n + +config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY + bool + default y + +config SOC_PM_MODEM_RETENTION_BY_REGDMA + bool + default n + +config SOC_PM_RETENTION_HAS_CLOCK_BUG + bool + default y + +config SOC_PM_PAU_LINK_NUM + int + default 4 + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_RCC_IS_INDEPENDENT + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL + bool + default y + +config SOC_TEMPERATURE_SENSOR_INTR_SUPPORT + bool + default y + +config SOC_WIFI_HW_TSF + bool + default y + +config SOC_WIFI_FTM_SUPPORT + bool + default n + +config SOC_WIFI_GCMP_SUPPORT + bool + default y + +config SOC_WIFI_WAPI_SUPPORT + bool + default y + +config SOC_WIFI_CSI_SUPPORT + bool + default y + +config SOC_WIFI_MESH_SUPPORT + bool + default y + +config SOC_WIFI_HE_SUPPORT + bool + default y + +config SOC_PHY_COMBO_MODULE + bool + default y + +config SOC_CAPS_NO_RESET_BY_ANA_BOD + bool + default y diff --git a/components/soc/esp32c61/include/soc/boot_mode.h b/components/soc/esp32c61/include/soc/boot_mode.h new file mode 100644 index 0000000000..089bb65554 --- /dev/null +++ b/components/soc/esp32c61/include/soc/boot_mode.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32c61/include/soc/cache_struct.h b/components/soc/esp32c61/include/soc/cache_struct.h index 37179a0e03..f98620a26b 100644 --- a/components/soc/esp32c61/include/soc/cache_struct.h +++ b/components/soc/esp32c61/include/soc/cache_struct.h @@ -5750,7 +5750,7 @@ typedef struct { volatile cache_date_reg_t date; } cache_dev_t; -extern cache_dev_t CACHE_CFG; +extern cache_dev_t CACHE; #ifndef __cplusplus _Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure"); diff --git a/components/soc/esp32c61/include/soc/clic_reg.h b/components/soc/esp32c61/include/soc/clic_reg.h new file mode 100644 index 0000000000..d7a51c598c --- /dev/null +++ b/components/soc/esp32c61/include/soc/clic_reg.h @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define NLBITS 3 +#define CLIC_EXT_INTR_NUM_OFFSET 16 + +#define DR_REG_CLIC_BASE (0x20800000) +#define DR_REG_CLIC_CTRL_BASE (0x20801000) + +#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0) +/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NMBITS 0x00000003 +#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V) << (CLIC_INT_CONFIG_NMBITS_S)) +#define CLIC_INT_CONFIG_NMBITS_V 0x3 +#define CLIC_INT_CONFIG_NMBITS_S 5 +/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NLBITS 0x0000000F +#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V) << (CCLIC_INT_CONFIG_NLBITS_S)) +#define CLIC_INT_CONFIG_NLBITS_V 0xF +#define CLIC_INT_CONFIG_NLBITS_S 1 +/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NVBITS (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_M (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_V 0x1 +#define CLIC_INT_CONFIG_NVBITS_S 0 + +#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4) +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_CTLBITS 0x0000000F +#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V) << (CLIC_INT_INFO_CTLBITS_S)) +#define CLIC_INT_INFO_CTLBITS_V 0xF +#define CLIC_INT_INFO_CTLBITS_S 21 +/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_VERSION 0x000000FF +#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V) << (CLIC_INT_INFO_VERSION_S)) +#define CLIC_INT_INFO_VERSION_V 0xFF +#define CLIC_INT_INFO_VERSION_S 13 +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_NUM_INT 0x00001FFF +#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V) << (CLIC_INT_INFO_NUM_INT_S)) +#define CLIC_INT_INFO_NUM_INT_V 0x1FFF +#define CLIC_INT_INFO_NUM_INT_S 0 + +#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8) +/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_CPU_INT_THRESH 0x000000FF +#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V) << (CLIC_CPU_INT_THRESH_S)) +#define CLIC_CPU_INT_THRESH_V 0xFF +#define CLIC_CPU_INT_THRESH_S 24 + +#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4) +/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_CTL 0x000000FF +#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V) << (CLIC_INT_CTL_S)) +#define CLIC_INT_CTL_V 0xFF +#define CLIC_INT_CTL_S 24 +/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_MODE 0x00000003 +#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V) << (CLIC_INT_ATTR_MODE_S)) +#define CLIC_INT_ATTR_MODE_V 0x3 +#define CLIC_INT_ATTR_MODE_S 22 +/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_TRIG 0x00000003 +#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V) << (CLIC_INT_ATTR_TRIG_S)) +#define CLIC_INT_ATTR_TRIG_V 0x3 +#define CLIC_INT_ATTR_TRIG_S 17 +/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_SHV (BIT(16)) +#define CLIC_INT_ATTR_SHV_M (BIT(16)) +#define CLIC_INT_ATTR_SHV_V 0x1 +#define CLIC_INT_ATTR_SHV_S 16 +/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IE (BIT(8)) +#define CLIC_INT_IE_M (BIT(8)) +#define CLIC_INT_IE_V 0x1 +#define CLIC_INT_IE_S 8 +/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IP (BIT(0)) +#define CLIC_INT_IP_M (BIT(0)) +#define CLIC_INT_IP_V 0x1 +#define CLIC_INT_IP_S 0 + +// each of following registers are 8bits +#define BYTE_CLIC_INT_IP_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4) +/* BYTE_CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define BYTE_CLIC_INT_IP (BIT(0)) +#define BYTE_CLIC_INT_IP_M (BIT(0)) +#define BYTE_CLIC_INT_IP_V 0x1 +#define BYTE_CLIC_INT_IP_S 0 + +#define BYTE_CLIC_INT_IE_REG(i) (DR_REG_CLIC_CTRL_BASE + 1 + (i)*4) +/* BYTE_CLIC_INT_IE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define BYTE_CLIC_INT_IE (BIT(0)) +#define BYTE_CLIC_INT_IE_M (BIT(0)) +#define BYTE_CLIC_INT_IE_V 0x1 +#define BYTE_CLIC_INT_IE_S 0 + +#define BYTE_CLIC_INT_ATTR_REG(i) (DR_REG_CLIC_CTRL_BASE + 2 + (i)*4) +/* BYTE_CLIC_INT_ATTR_SHV : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: 1 means hardware vector interrupt.*/ +#define BYTE_CLIC_INT_ATTR_SHV (BIT(0)) +#define BYTE_CLIC_INT_ATTR_SHV_M (BIT(0)) +#define BYTE_CLIC_INT_ATTR_SHV_V 0x1 +#define BYTE_CLIC_INT_ATTR_SHV_S 0 +/* BYTE_CLIC_INT_ATTR_TRIG: R/W ; bitpos:[2:1] ;default: 2'd0 ; */ +/*description: + [X0] -> level trigger + [01] -> rising edge trigger + [11] -> falling edge trigger */ +#define BYTE_CLIC_INT_ATTR_TRIG 0x00000003 +#define BYTE_CLIC_INT_ATTR_TRIG_M ((BYTE_CLIC_INT_ATTR_TRIG_V) << (BYTE_CLIC_INT_ATTR_TRIG_S)) +#define BYTE_CLIC_INT_ATTR_TRIG_V 0x3 +#define BYTE_CLIC_INT_ATTR_TRIG_S 1 +/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:6] ;default: 2'd0 ; */ +/*description: privilege level for interrupt, fixed to 2'b11 */ +#define BYTE_CLIC_INT_ATTR_MODE 0x00000003 +#define BYTE_CLIC_INT_ATTR_MODE_M ((BYTE_CLIC_INT_ATTR_MODE_V) << (BYTE_CLIC_INT_ATTR_MODE_S)) +#define BYTE_CLIC_INT_ATTR_MODE_V 0x3 +#define BYTE_CLIC_INT_ATTR_MODE_S 6 + +#define BYTE_CLIC_INT_CTL_REG(i) (DR_REG_CLIC_CTRL_BASE + 3 + (i)*4) +/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:5] ;default: 3'd0 ; */ +/*description: interrupt pririty */ +#define BYTE_CLIC_INT_CTL 0x00000007 +#define BYTE_CLIC_INT_CTL_M ((BYTE_CLIC_INT_CTL_V) << (BYTE_CLIC_INT_CTL_S)) +#define BYTE_CLIC_INT_CTL_V 0x7 +#define BYTE_CLIC_INT_CTL_S 5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/clint_reg.h b/components/soc/esp32c61/include/soc/clint_reg.h new file mode 100644 index 0000000000..e24677730d --- /dev/null +++ b/components/soc/esp32c61/include/soc/clint_reg.h @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/*CLINT MINT*/ +#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0) +/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_SIP BIT(0) +#define CLINT_CPU_MINT_SIP_M BIT(0) +#define CLINT_CPU_MINT_SIP_V 1 +#define CLINT_CPU_MINT_SIP_S 0 + +#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000) +/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) +#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_S 0 + +#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004) +/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) +#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_S 0 + +#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010) +/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_MINT_SAMPLING_MODE 0x00000003 +#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) +#define CLINT_MINT_SAMPLING_MODE_V 0x3 +#define CLINT_MINT_SAMPLING_MODE_S 4 +/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_MINT_COUNTER_OVERFLOW_S 3 +/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_EN (BIT(0)) +#define CLINT_MINT_COUNTER_EN_M (BIT(0)) +#define CLINT_MINT_COUNTER_EN_V 0x1 +#define CLINT_MINT_COUNTER_EN_S 0 + +#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8) +/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) +#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_S 0 + +#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC) +/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) +#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h new file mode 100644 index 0000000000..df78d1d907 --- /dev/null +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -0,0 +1,507 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +// TODO: [ESP32C61] IDF-9249, This file comes from verification code +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32C61 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 40MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ + SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +/** + * @brief Possible main XTAL frequency options on the target + * @note Enum values equal to the frequency value in MHz + * @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for + * the supported ones. + */ +typedef enum { + SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */ +} soc_xtal_freq_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ + // For LP peripherals + SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ + + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { + GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { + TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ +} soc_periph_tg_clk_src_legacy_t; + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of RMT + */ +#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of RMT clock source + */ +typedef enum { + RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_rmt_clk_src_t; + +/** + * @brief Type of RMT clock source, reserved for the legacy RMT driver + */ +typedef enum { + RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */ + RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ +} soc_periph_rmt_clk_src_legacy_t; + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Temperature Sensor + */ +#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of Temp Sensor clock source + */ +typedef enum { + TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +} soc_periph_temperature_sensor_clk_src_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of UART + */ +#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { + UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ +} soc_periph_uart_clk_src_legacy_t; + +/** + * @brief Array initializer for all supported clock sources of LP_UART + */ +#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} + +/** + * @brief Type of LP_UART clock source + */ +typedef enum { + LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ + LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ + LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ +} soc_periph_lp_uart_clk_src_t; + +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { + MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { + MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_capture_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Carrier + */ +#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM carrier clock source + */ +typedef enum { + MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_carrier_clk_src_t; + +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} + +/** + * @brief I2S clock source enum + */ +typedef enum { + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ + I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ +} soc_periph_i2s_clk_src_t; + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2C + */ +#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of I2C clock source. + */ +typedef enum { + I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ +} soc_periph_i2c_clk_src_t; + +///////////////////////////////////////////////LP_I2C/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LP_I2C + */ +#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} + +/** + * @brief Type of LP_I2C clock source. + */ +typedef enum { + LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */ + LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */ + LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */ +} soc_periph_lp_i2c_clk_src_t; + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SDM + */ +#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Sigma Delta Modulator clock source + */ +typedef enum { + SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_sdm_clk_src_t; + +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Glitch Filter + */ +#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Glitch filter clock source + */ + +typedef enum { + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + +//////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of TWAI + */ +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} + +/** + * @brief TWAI clock source + */ +typedef enum { + TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +} soc_periph_twai_clk_src_t; + +//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of ADC digital controller + */ +#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief ADC digital controller clock source + */ +typedef enum { + ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ +} soc_periph_adc_digi_clk_src_t; + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LEDC + */ +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of LEDC clock source, reserved for the legacy LEDC driver + */ +typedef enum { + LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + + LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ +} soc_periph_ledc_clk_src_legacy_t; + +//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of PARLIO + */ +#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} + +/** + * @brief PARLIO clock source + */ +typedef enum { + PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ + PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */ + PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ +} soc_periph_parlio_clk_src_t; + +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { + CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ + CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ + CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */ + CLKOUT_SIG_CPU = 16, /*!< CPU clock */ + CLKOUT_SIG_AHB = 17, /*!< AHB clock */ + CLKOUT_SIG_APB = 18, /*!< APB clock */ + CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ + CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ + CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ + CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/dport_access.h b/components/soc/esp32c61/include/soc/dport_access.h new file mode 100644 index 0000000000..85bdb9e6b8 --- /dev/null +++ b/components/soc/esp32c61/include/soc/dport_access.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _DPORT_ACCESS_H_ +#define _DPORT_ACCESS_H_ + +#include +#include "soc.h" +#include "uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif + +#endif /* _DPORT_ACCESS_H_ */ diff --git a/components/soc/esp32c61/include/soc/efuse_defs.h b/components/soc/esp32c61/include/soc/efuse_defs.h new file mode 100644 index 0000000000..48cc4ce65d --- /dev/null +++ b/components/soc/esp32c61/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/efuse_reg.h b/components/soc/esp32c61/include/soc/efuse_reg.h index 850733bbd9..b154df3092 100644 --- a/components/soc/esp32c61/include/soc/efuse_reg.h +++ b/components/soc/esp32c61/include/soc/efuse_reg.h @@ -14,7 +14,7 @@ extern "C" { /** EFUSE_PGM_DATA0_REG register * Represents pgm_data0 */ -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE0_BASE + 0x0) /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; * Configures the 0th 32-bit data to be programmed. */ @@ -26,7 +26,7 @@ extern "C" { /** EFUSE_PGM_DATA1_REG register * Represents pgm_data1 */ -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE0_BASE + 0x4) /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; * Configures the 1th 32-bit data to be programmed. */ @@ -38,7 +38,7 @@ extern "C" { /** EFUSE_PGM_DATA2_REG register * Represents pgm_data2 */ -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE0_BASE + 0x8) /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; * Configures the 2th 32-bit data to be programmed. */ @@ -50,7 +50,7 @@ extern "C" { /** EFUSE_PGM_DATA3_REG register * Represents pgm_data3 */ -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc) /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; * Configures the 3th 32-bit data to be programmed. */ @@ -62,7 +62,7 @@ extern "C" { /** EFUSE_PGM_DATA4_REG register * Represents pgm_data4 */ -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10) /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; * Configures the 4th 32-bit data to be programmed. */ @@ -74,7 +74,7 @@ extern "C" { /** EFUSE_PGM_DATA5_REG register * Represents pgm_data5 */ -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE0_BASE + 0x14) /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; * Configures the 5th 32-bit data to be programmed. */ @@ -86,7 +86,7 @@ extern "C" { /** EFUSE_PGM_DATA6_REG register * Represents pgm_data6 */ -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE0_BASE + 0x18) /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; * Configures the 6th 32-bit data to be programmed. */ @@ -98,7 +98,7 @@ extern "C" { /** EFUSE_PGM_DATA7_REG register * Represents pgm_data7 */ -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE0_BASE + 0x1c) /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; * Configures the 7th 32-bit data to be programmed. */ @@ -110,7 +110,7 @@ extern "C" { /** EFUSE_PGM_CHECK_VALUE0_REG register * Represents pgm_check_value0 */ -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE0_BASE + 0x20) /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; * Configures the 0th RS code to be programmed. */ @@ -122,7 +122,7 @@ extern "C" { /** EFUSE_PGM_CHECK_VALUE1_REG register * Represents pgm_check_value1 */ -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE0_BASE + 0x24) /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; * Configures the 1th RS code to be programmed. */ @@ -134,7 +134,7 @@ extern "C" { /** EFUSE_PGM_CHECK_VALUE2_REG register * Represents pgm_check_value2 */ -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE0_BASE + 0x28) /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; * Configures the 2th RS code to be programmed. */ @@ -146,7 +146,7 @@ extern "C" { /** EFUSE_RD_WR_DIS0_REG register * Represents rd_wr_dis */ -#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c) +#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE0_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or * enabled.\\ 1: Disabled\\ 0: Enabled\\ @@ -159,7 +159,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA0_REG register * Represents rd_repeat_data */ -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE0_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or * enabled.\\ 1: disabled\\ 0: enabled\\ @@ -308,7 +308,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA1_REG register * Represents rd_repeat_data */ -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE0_BASE + 0x34) /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [3:0]; default: 0; * Represents the purpose of Key0. */ @@ -386,7 +386,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA2_REG register * Represents rd_repeat_data */ -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE0_BASE + 0x38) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ */ @@ -506,7 +506,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA3_REG register * Represents rd_repeat_data */ -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE0_BASE + 0x3c) /** EFUSE_RD_REPEAT_DATA3 : RO; bitpos: [31:0]; default: 0; * Reserved. */ @@ -518,7 +518,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data */ -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE0_BASE + 0x40) /** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [31:0]; default: 0; * Reserved. */ @@ -530,7 +530,7 @@ extern "C" { /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) +#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE0_BASE + 0x44) /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; * Represents MAC address. Low 32-bit. */ @@ -542,7 +542,7 @@ extern "C" { /** EFUSE_RD_MAC_SYS1_REG register * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) +#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE0_BASE + 0x48) /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; * Represents MAC address. High 16-bit. */ @@ -561,7 +561,7 @@ extern "C" { /** EFUSE_RD_MAC_SYS2_REG register * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) +#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE0_BASE + 0x4c) /** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; * Reserved. */ @@ -580,7 +580,7 @@ extern "C" { /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) +#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE0_BASE + 0x50) /** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; * Reserved. */ @@ -599,7 +599,7 @@ extern "C" { /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) +#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE0_BASE + 0x54) /** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; * Represents the first 14-bit of zeroth part of system data. */ @@ -611,7 +611,7 @@ extern "C" { /** EFUSE_RD_MAC_SYS5_REG register * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) +#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE0_BASE + 0x58) /** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; * Represents the second 32-bit of zeroth part of system data. */ @@ -623,7 +623,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA0_REG register * Represents rd_sys_part1_data0 */ -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE0_BASE + 0x5c) /** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -635,7 +635,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA1_REG register * Represents rd_sys_part1_data1 */ -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE0_BASE + 0x60) /** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -647,7 +647,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA2_REG register * Represents rd_sys_part1_data2 */ -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE0_BASE + 0x64) /** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -659,7 +659,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA3_REG register * Represents rd_sys_part1_data3 */ -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE0_BASE + 0x68) /** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -671,7 +671,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA4_REG register * Represents rd_sys_part1_data4 */ -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE0_BASE + 0x6c) /** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -683,7 +683,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 */ -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE0_BASE + 0x70) /** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -695,7 +695,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA6_REG register * Represents rd_sys_part1_data6 */ -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE0_BASE + 0x74) /** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -707,7 +707,7 @@ extern "C" { /** EFUSE_RD_SYS_PART1_DATA7_REG register * Represents rd_sys_part1_data7 */ -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE0_BASE + 0x78) /** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ @@ -719,7 +719,7 @@ extern "C" { /** EFUSE_RD_USR_DATA0_REG register * Represents rd_usr_data0 */ -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE0_BASE + 0x7c) /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -731,7 +731,7 @@ extern "C" { /** EFUSE_RD_USR_DATA1_REG register * Represents rd_usr_data1 */ -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE0_BASE + 0x80) /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -743,7 +743,7 @@ extern "C" { /** EFUSE_RD_USR_DATA2_REG register * Represents rd_usr_data2 */ -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE0_BASE + 0x84) /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -755,7 +755,7 @@ extern "C" { /** EFUSE_RD_USR_DATA3_REG register * Represents rd_usr_data3 */ -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE0_BASE + 0x88) /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -767,7 +767,7 @@ extern "C" { /** EFUSE_RD_USR_DATA4_REG register * Represents rd_usr_data4 */ -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE0_BASE + 0x8c) /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -779,7 +779,7 @@ extern "C" { /** EFUSE_RD_USR_DATA5_REG register * Represents rd_usr_data5 */ -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE0_BASE + 0x90) /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -791,7 +791,7 @@ extern "C" { /** EFUSE_RD_USR_DATA6_REG register * Represents rd_usr_data6 */ -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE0_BASE + 0x94) /** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -803,7 +803,7 @@ extern "C" { /** EFUSE_RD_USR_DATA7_REG register * Represents rd_usr_data7 */ -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE0_BASE + 0x98) /** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ @@ -815,7 +815,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA0_REG register * Represents rd_key0_data0 */ -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE0_BASE + 0x9c) /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -827,7 +827,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA1_REG register * Represents rd_key0_data1 */ -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE0_BASE + 0xa0) /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -839,7 +839,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA2_REG register * Represents rd_key0_data2 */ -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE0_BASE + 0xa4) /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -851,7 +851,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA3_REG register * Represents rd_key0_data3 */ -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE0_BASE + 0xa8) /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -863,7 +863,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA4_REG register * Represents rd_key0_data4 */ -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE0_BASE + 0xac) /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -875,7 +875,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA5_REG register * Represents rd_key0_data5 */ -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE0_BASE + 0xb0) /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -887,7 +887,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA6_REG register * Represents rd_key0_data6 */ -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE0_BASE + 0xb4) /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -899,7 +899,7 @@ extern "C" { /** EFUSE_RD_KEY0_DATA7_REG register * Represents rd_key0_data7 */ -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE0_BASE + 0xb8) /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ @@ -911,7 +911,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA0_REG register * Represents rd_key1_data0 */ -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE0_BASE + 0xbc) /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -923,7 +923,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA1_REG register * Represents rd_key1_data1 */ -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE0_BASE + 0xc0) /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -935,7 +935,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA2_REG register * Represents rd_key1_data2 */ -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE0_BASE + 0xc4) /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -947,7 +947,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA3_REG register * Represents rd_key1_data3 */ -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc8) /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -959,7 +959,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA4_REG register * Represents rd_key1_data4 */ -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE0_BASE + 0xcc) /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -971,7 +971,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA5_REG register * Represents rd_key1_data5 */ -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE0_BASE + 0xd0) /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -983,7 +983,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA6_REG register * Represents rd_key1_data6 */ -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE0_BASE + 0xd4) /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -995,7 +995,7 @@ extern "C" { /** EFUSE_RD_KEY1_DATA7_REG register * Represents rd_key1_data7 */ -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE0_BASE + 0xd8) /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ @@ -1007,7 +1007,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA0_REG register * Represents rd_key2_data0 */ -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE0_BASE + 0xdc) /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1019,7 +1019,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA1_REG register * Represents rd_key2_data1 */ -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE0_BASE + 0xe0) /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1031,7 +1031,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA2_REG register * Represents rd_key2_data2 */ -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE0_BASE + 0xe4) /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1043,7 +1043,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA3_REG register * Represents rd_key2_data3 */ -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE0_BASE + 0xe8) /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1055,7 +1055,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA4_REG register * Represents rd_key2_data4 */ -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE0_BASE + 0xec) /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1067,7 +1067,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA5_REG register * Represents rd_key2_data5 */ -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE0_BASE + 0xf0) /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1079,7 +1079,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA6_REG register * Represents rd_key2_data6 */ -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE0_BASE + 0xf4) /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1091,7 +1091,7 @@ extern "C" { /** EFUSE_RD_KEY2_DATA7_REG register * Represents rd_key2_data7 */ -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE0_BASE + 0xf8) /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ @@ -1103,7 +1103,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA0_REG register * Represents rd_key3_data0 */ -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE0_BASE + 0xfc) /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1115,7 +1115,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA1_REG register * Represents rd_key3_data1 */ -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE0_BASE + 0x100) /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1127,7 +1127,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA2_REG register * Represents rd_key3_data2 */ -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE0_BASE + 0x104) /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1139,7 +1139,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA3_REG register * Represents rd_key3_data3 */ -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE0_BASE + 0x108) /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1151,7 +1151,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA4_REG register * Represents rd_key3_data4 */ -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10c) /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1163,7 +1163,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA5_REG register * Represents rd_key3_data5 */ -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE0_BASE + 0x110) /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1175,7 +1175,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA6_REG register * Represents rd_key3_data6 */ -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE0_BASE + 0x114) /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1187,7 +1187,7 @@ extern "C" { /** EFUSE_RD_KEY3_DATA7_REG register * Represents rd_key3_data7 */ -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE0_BASE + 0x118) /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ @@ -1199,7 +1199,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA0_REG register * Represents rd_key4_data0 */ -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE0_BASE + 0x11c) /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1211,7 +1211,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA1_REG register * Represents rd_key4_data1 */ -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE0_BASE + 0x120) /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1223,7 +1223,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA2_REG register * Represents rd_key4_data2 */ -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE0_BASE + 0x124) /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1235,7 +1235,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA3_REG register * Represents rd_key4_data3 */ -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE0_BASE + 0x128) /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1247,7 +1247,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA4_REG register * Represents rd_key4_data4 */ -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE0_BASE + 0x12c) /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1259,7 +1259,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA5_REG register * Represents rd_key4_data5 */ -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE0_BASE + 0x130) /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1271,7 +1271,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA6_REG register * Represents rd_key4_data6 */ -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE0_BASE + 0x134) /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1283,7 +1283,7 @@ extern "C" { /** EFUSE_RD_KEY4_DATA7_REG register * Represents rd_key4_data7 */ -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE0_BASE + 0x138) /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ @@ -1295,7 +1295,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA0_REG register * Represents rd_key5_data0 */ -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE0_BASE + 0x13c) /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1307,7 +1307,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA1_REG register * Represents rd_key5_data1 */ -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE0_BASE + 0x140) /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1319,7 +1319,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA2_REG register * Represents rd_key5_data2 */ -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE0_BASE + 0x144) /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1331,7 +1331,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA3_REG register * Represents rd_key5_data3 */ -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE0_BASE + 0x148) /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1343,7 +1343,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA4_REG register * Represents rd_key5_data4 */ -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE0_BASE + 0x14c) /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1355,7 +1355,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA5_REG register * Represents rd_key5_data5 */ -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE0_BASE + 0x150) /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1367,7 +1367,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA6_REG register * Represents rd_key5_data6 */ -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE0_BASE + 0x154) /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1379,7 +1379,7 @@ extern "C" { /** EFUSE_RD_KEY5_DATA7_REG register * Represents rd_key5_data7 */ -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE0_BASE + 0x158) /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ @@ -1391,7 +1391,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA0_REG register * Represents rd_sys_part2_data0 */ -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE0_BASE + 0x15c) /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1403,7 +1403,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA1_REG register * Represents rd_sys_part2_data1 */ -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE0_BASE + 0x160) /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1415,7 +1415,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA2_REG register * Represents rd_sys_part2_data2 */ -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE0_BASE + 0x164) /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1427,7 +1427,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA3_REG register * Represents rd_sys_part2_data3 */ -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE0_BASE + 0x168) /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1439,7 +1439,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA4_REG register * Represents rd_sys_part2_data4 */ -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE0_BASE + 0x16c) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1451,7 +1451,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA5_REG register * Represents rd_sys_part2_data5 */ -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE0_BASE + 0x170) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1463,7 +1463,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA6_REG register * Represents rd_sys_part2_data6 */ -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE0_BASE + 0x174) /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1475,7 +1475,7 @@ extern "C" { /** EFUSE_RD_SYS_PART2_DATA7_REG register * Represents rd_sys_part2_data7 */ -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE0_BASE + 0x178) /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ @@ -1487,7 +1487,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA_ERR0_REG register * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE0_BASE + 0x17c) /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; * Represents the programming error of EFUSE_RD_DIS */ @@ -1618,7 +1618,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA_ERR1_REG register * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE0_BASE + 0x180) /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [3:0]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ @@ -1693,7 +1693,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA_ERR2_REG register * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE0_BASE + 0x184) /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ @@ -1803,7 +1803,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA_ERR3_REG register * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE0_BASE + 0x188) /** EFUSE_RD_REPEAT_DATA_ERR3 : RO; bitpos: [31:0]; default: 0; * Reserved. */ @@ -1815,7 +1815,7 @@ extern "C" { /** EFUSE_RD_REPEAT_DATA_ERR4_REG register * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE0_BASE + 0x18c) /** EFUSE_RD_REPEAT_DATA_ERR4 : RO; bitpos: [31:0]; default: 0; * Reserved. */ @@ -1827,7 +1827,7 @@ extern "C" { /** EFUSE_RD_RS_DATA_ERR0_REG register * Represents rd_rs_data_err */ -#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) +#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE0_BASE + 0x190) /** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; * Represents the error number of registers.\\The value of this signal means the * number of error bytes in rd_mac_sys @@ -1968,7 +1968,7 @@ extern "C" { /** EFUSE_RD_RS_DATA_ERR1_REG register * Represents rd_rs_data_err */ -#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) +#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE0_BASE + 0x194) /** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; * Represents the error number of registers.\\The value of this signal means the * number of error bytes in rd_key5_data @@ -2007,7 +2007,7 @@ extern "C" { /** EFUSE_DATE_REG register * eFuse version register. */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) +#define EFUSE_DATE_REG (DR_REG_EFUSE0_BASE + 0x198) /** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37753088; * Stores eFuse version. */ @@ -2019,7 +2019,7 @@ extern "C" { /** EFUSE_CLK_REG register * eFuse clcok configuration register. */ -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +#define EFUSE_CLK_REG (DR_REG_EFUSE0_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; * Set this bit to force eFuse SRAM into power-saving mode. */ @@ -2052,7 +2052,7 @@ extern "C" { /** EFUSE_CONF_REG register * eFuse operation mode configuraiton register */ -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +#define EFUSE_CONF_REG (DR_REG_EFUSE0_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; * 0x5A5A: programming operation command 0x5AA5: read operation command. */ @@ -2071,7 +2071,7 @@ extern "C" { /** EFUSE_STATUS_REG register * eFuse status register. */ -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +#define EFUSE_STATUS_REG (DR_REG_EFUSE0_BASE + 0x1d0) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; * Indicates the state of the eFuse state machine. */ @@ -2139,7 +2139,7 @@ extern "C" { /** EFUSE_CMD_REG register * eFuse command register. */ -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +#define EFUSE_CMD_REG (DR_REG_EFUSE0_BASE + 0x1d4) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; * Set this bit to send read command. */ @@ -2166,7 +2166,7 @@ extern "C" { /** EFUSE_INT_RAW_REG register * eFuse raw interrupt register. */ -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE0_BASE + 0x1d8) /** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; * The raw bit signal for read_done interrupt. */ @@ -2185,7 +2185,7 @@ extern "C" { /** EFUSE_INT_ST_REG register * eFuse interrupt status register. */ -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +#define EFUSE_INT_ST_REG (DR_REG_EFUSE0_BASE + 0x1dc) /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; * The status signal for read_done interrupt. */ @@ -2204,7 +2204,7 @@ extern "C" { /** EFUSE_INT_ENA_REG register * eFuse interrupt enable register. */ -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE0_BASE + 0x1e0) /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; * The enable signal for read_done interrupt. */ @@ -2223,7 +2223,7 @@ extern "C" { /** EFUSE_INT_CLR_REG register * eFuse interrupt clear register. */ -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE0_BASE + 0x1e4) /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; * The clear signal for read_done interrupt. */ @@ -2242,7 +2242,7 @@ extern "C" { /** EFUSE_DAC_CONF_REG register * Controls the eFuse programming voltage. */ -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE0_BASE + 0x1e8) /** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; * Controls the division factor of the rising clock of the programming voltage. */ @@ -2275,7 +2275,7 @@ extern "C" { /** EFUSE_RD_TIM_CONF_REG register * Configures read timing parameters. */ -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE0_BASE + 0x1ec) /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; * Configures the read hold time. */ @@ -2308,7 +2308,7 @@ extern "C" { /** EFUSE_WR_TIM_CONF1_REG register * Configurarion register 1 of eFuse programming timing parameters. */ -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE0_BASE + 0x1f0) /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; * Configures the programming setup time. */ @@ -2334,7 +2334,7 @@ extern "C" { /** EFUSE_WR_TIM_CONF2_REG register * Configurarion register 2 of eFuse programming timing parameters. */ -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE0_BASE + 0x1f4) /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; * Configures the power outage time for VDDQ. */ @@ -2354,7 +2354,7 @@ extern "C" { * Configurarion register0 of eFuse programming time parameters and rs bypass * operation. */ -#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE0_BASE + 0x1f8) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; * Set this bit to bypass reed solomon correction step. */ @@ -2387,7 +2387,7 @@ extern "C" { /** EFUSE_APB2OTP_WR_DIS_REG register * eFuse apb2otp block0 data register1. */ -#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x500) +#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE0_BASE + 0x500) /** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; * Otp block0 write disable data. */ @@ -2399,7 +2399,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register * eFuse apb2otp block0 data register2. */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x504) +#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE0_BASE + 0x504) /** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup1 word1 data. */ @@ -2411,7 +2411,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register * eFuse apb2otp block0 data register3. */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x508) +#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE0_BASE + 0x508) /** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup1 word2 data. */ @@ -2423,7 +2423,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register * eFuse apb2otp block0 data register4. */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x50c) +#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE0_BASE + 0x50c) /** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup1 word3 data. */ @@ -2435,7 +2435,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register * eFuse apb2otp block0 data register5. */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x510) +#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE0_BASE + 0x510) /** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup1 word4 data. */ @@ -2447,7 +2447,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register * eFuse apb2otp block0 data register6. */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x514) +#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE0_BASE + 0x514) /** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup1 word5 data. */ @@ -2459,7 +2459,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register * eFuse apb2otp block0 data register7. */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x518) +#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE0_BASE + 0x518) /** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup2 word1 data. */ @@ -2471,7 +2471,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register * eFuse apb2otp block0 data register8. */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x51c) +#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE0_BASE + 0x51c) /** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup2 word2 data. */ @@ -2483,7 +2483,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register * eFuse apb2otp block0 data register9. */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x520) +#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE0_BASE + 0x520) /** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup2 word3 data. */ @@ -2495,7 +2495,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register * eFuse apb2otp block0 data register10. */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x524) +#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE0_BASE + 0x524) /** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup2 word4 data. */ @@ -2507,7 +2507,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register * eFuse apb2otp block0 data register11. */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x528) +#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE0_BASE + 0x528) /** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup2 word5 data. */ @@ -2519,7 +2519,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register * eFuse apb2otp block0 data register12. */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x52c) +#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE0_BASE + 0x52c) /** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup3 word1 data. */ @@ -2531,7 +2531,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register * eFuse apb2otp block0 data register13. */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x530) +#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE0_BASE + 0x530) /** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup3 word2 data. */ @@ -2543,7 +2543,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register * eFuse apb2otp block0 data register14. */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x534) +#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE0_BASE + 0x534) /** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup3 word3 data. */ @@ -2555,7 +2555,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register * eFuse apb2otp block0 data register15. */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x538) +#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE0_BASE + 0x538) /** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup3 word4 data. */ @@ -2567,7 +2567,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register * eFuse apb2otp block0 data register16. */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x53c) +#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE0_BASE + 0x53c) /** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup3 word5 data. */ @@ -2579,7 +2579,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register * eFuse apb2otp block0 data register17. */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x540) +#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE0_BASE + 0x540) /** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup4 word1 data. */ @@ -2591,7 +2591,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register * eFuse apb2otp block0 data register18. */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x544) +#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE0_BASE + 0x544) /** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup4 word2 data. */ @@ -2603,7 +2603,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register * eFuse apb2otp block0 data register19. */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x548) +#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE0_BASE + 0x548) /** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup4 word3 data. */ @@ -2615,7 +2615,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register * eFuse apb2otp block0 data register20. */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x54c) +#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE0_BASE + 0x54c) /** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup4 word4 data. */ @@ -2627,7 +2627,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register * eFuse apb2otp block0 data register21. */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x550) +#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE0_BASE + 0x550) /** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; * Otp block0 backup4 word5 data. */ @@ -2639,7 +2639,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W1_REG register * eFuse apb2otp block1 data register1. */ -#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x554) +#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE0_BASE + 0x554) /** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; * Otp block1 word1 data. */ @@ -2651,7 +2651,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W2_REG register * eFuse apb2otp block1 data register2. */ -#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x558) +#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE0_BASE + 0x558) /** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; * Otp block1 word2 data. */ @@ -2663,7 +2663,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W3_REG register * eFuse apb2otp block1 data register3. */ -#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x55c) +#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE0_BASE + 0x55c) /** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; * Otp block1 word3 data. */ @@ -2675,7 +2675,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W4_REG register * eFuse apb2otp block1 data register4. */ -#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x560) +#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE0_BASE + 0x560) /** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; * Otp block1 word4 data. */ @@ -2687,7 +2687,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W5_REG register * eFuse apb2otp block1 data register5. */ -#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x564) +#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE0_BASE + 0x564) /** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; * Otp block1 word5 data. */ @@ -2699,7 +2699,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W6_REG register * eFuse apb2otp block1 data register6. */ -#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x568) +#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE0_BASE + 0x568) /** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; * Otp block1 word6 data. */ @@ -2711,7 +2711,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W7_REG register * eFuse apb2otp block1 data register7. */ -#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x56c) +#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE0_BASE + 0x56c) /** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; * Otp block1 word7 data. */ @@ -2723,7 +2723,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W8_REG register * eFuse apb2otp block1 data register8. */ -#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x570) +#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE0_BASE + 0x570) /** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; * Otp block1 word8 data. */ @@ -2735,7 +2735,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK1_W9_REG register * eFuse apb2otp block1 data register9. */ -#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x574) +#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE0_BASE + 0x574) /** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; * Otp block1 word9 data. */ @@ -2747,7 +2747,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W1_REG register * eFuse apb2otp block2 data register1. */ -#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x578) +#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE0_BASE + 0x578) /** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; * Otp block2 word1 data. */ @@ -2759,7 +2759,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W2_REG register * eFuse apb2otp block2 data register2. */ -#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x57c) +#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE0_BASE + 0x57c) /** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; * Otp block2 word2 data. */ @@ -2771,7 +2771,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W3_REG register * eFuse apb2otp block2 data register3. */ -#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x580) +#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE0_BASE + 0x580) /** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; * Otp block2 word3 data. */ @@ -2783,7 +2783,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W4_REG register * eFuse apb2otp block2 data register4. */ -#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x584) +#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE0_BASE + 0x584) /** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; * Otp block2 word4 data. */ @@ -2795,7 +2795,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W5_REG register * eFuse apb2otp block2 data register5. */ -#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x588) +#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE0_BASE + 0x588) /** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; * Otp block2 word5 data. */ @@ -2807,7 +2807,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W6_REG register * eFuse apb2otp block2 data register6. */ -#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x58c) +#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE0_BASE + 0x58c) /** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; * Otp block2 word6 data. */ @@ -2819,7 +2819,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W7_REG register * eFuse apb2otp block2 data register7. */ -#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x590) +#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE0_BASE + 0x590) /** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; * Otp block2 word7 data. */ @@ -2831,7 +2831,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W8_REG register * eFuse apb2otp block2 data register8. */ -#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x594) +#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE0_BASE + 0x594) /** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; * Otp block2 word8 data. */ @@ -2843,7 +2843,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W9_REG register * eFuse apb2otp block2 data register9. */ -#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x598) +#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE0_BASE + 0x598) /** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; * Otp block2 word9 data. */ @@ -2855,7 +2855,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W10_REG register * eFuse apb2otp block2 data register10. */ -#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x59c) +#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE0_BASE + 0x59c) /** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; * Otp block2 word10 data. */ @@ -2867,7 +2867,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK2_W11_REG register * eFuse apb2otp block2 data register11. */ -#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x5a0) +#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE0_BASE + 0x5a0) /** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; * Otp block2 word11 data. */ @@ -2879,7 +2879,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W1_REG register * eFuse apb2otp block3 data register1. */ -#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x5a4) +#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE0_BASE + 0x5a4) /** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; * Otp block3 word1 data. */ @@ -2891,7 +2891,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W2_REG register * eFuse apb2otp block3 data register2. */ -#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x5a8) +#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE0_BASE + 0x5a8) /** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; * Otp block3 word2 data. */ @@ -2903,7 +2903,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W3_REG register * eFuse apb2otp block3 data register3. */ -#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x5ac) +#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE0_BASE + 0x5ac) /** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; * Otp block3 word3 data. */ @@ -2915,7 +2915,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W4_REG register * eFuse apb2otp block3 data register4. */ -#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x5b0) +#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE0_BASE + 0x5b0) /** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; * Otp block3 word4 data. */ @@ -2927,7 +2927,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W5_REG register * eFuse apb2otp block3 data register5. */ -#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x5b4) +#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE0_BASE + 0x5b4) /** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; * Otp block3 word5 data. */ @@ -2939,7 +2939,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W6_REG register * eFuse apb2otp block3 data register6. */ -#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x5b8) +#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE0_BASE + 0x5b8) /** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; * Otp block3 word6 data. */ @@ -2951,7 +2951,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W7_REG register * eFuse apb2otp block3 data register7. */ -#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x5bc) +#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE0_BASE + 0x5bc) /** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; * Otp block3 word7 data. */ @@ -2963,7 +2963,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W8_REG register * eFuse apb2otp block3 data register8. */ -#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x5c0) +#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE0_BASE + 0x5c0) /** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; * Otp block3 word8 data. */ @@ -2975,7 +2975,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W9_REG register * eFuse apb2otp block3 data register9. */ -#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x5c4) +#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE0_BASE + 0x5c4) /** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; * Otp block3 word9 data. */ @@ -2987,7 +2987,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W10_REG register * eFuse apb2otp block3 data register10. */ -#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x5c8) +#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE0_BASE + 0x5c8) /** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; * Otp block3 word10 data. */ @@ -2999,7 +2999,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK3_W11_REG register * eFuse apb2otp block3 data register11. */ -#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x5cc) +#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE0_BASE + 0x5cc) /** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; * Otp block3 word11 data. */ @@ -3011,7 +3011,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W1_REG register * eFuse apb2otp BLOCK7 data register1. */ -#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x5d0) +#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE0_BASE + 0x5d0) /** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; * Otp block4 word1 data. */ @@ -3023,7 +3023,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W2_REG register * eFuse apb2otp block4 data register2. */ -#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x5d4) +#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE0_BASE + 0x5d4) /** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; * Otp block4 word2 data. */ @@ -3035,7 +3035,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W3_REG register * eFuse apb2otp block4 data register3. */ -#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x5d8) +#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE0_BASE + 0x5d8) /** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; * Otp block4 word3 data. */ @@ -3047,7 +3047,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W4_REG register * eFuse apb2otp block4 data register4. */ -#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x5dc) +#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE0_BASE + 0x5dc) /** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; * Otp block4 word4 data. */ @@ -3059,7 +3059,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W5_REG register * eFuse apb2otp block4 data register5. */ -#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x5e0) +#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE0_BASE + 0x5e0) /** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; * Otp block4 word5 data. */ @@ -3071,7 +3071,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W6_REG register * eFuse apb2otp block4 data register6. */ -#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x5e4) +#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE0_BASE + 0x5e4) /** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; * Otp block4 word6 data. */ @@ -3083,7 +3083,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W7_REG register * eFuse apb2otp block4 data register7. */ -#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x5e8) +#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE0_BASE + 0x5e8) /** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; * Otp block4 word7 data. */ @@ -3095,7 +3095,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W8_REG register * eFuse apb2otp block4 data register8. */ -#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x5ec) +#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE0_BASE + 0x5ec) /** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; * Otp block4 word8 data. */ @@ -3107,7 +3107,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W9_REG register * eFuse apb2otp block4 data register9. */ -#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x5f0) +#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE0_BASE + 0x5f0) /** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; * Otp block4 word9 data. */ @@ -3119,7 +3119,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W10_REG register * eFuse apb2otp block4 data registe10. */ -#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x5f4) +#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE0_BASE + 0x5f4) /** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; * Otp block4 word10 data. */ @@ -3131,7 +3131,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK4_W11_REG register * eFuse apb2otp block4 data register11. */ -#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x5f8) +#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE0_BASE + 0x5f8) /** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; * Otp block4 word11 data. */ @@ -3143,7 +3143,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W1_REG register * eFuse apb2otp block5 data register1. */ -#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x5fc) +#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE0_BASE + 0x5fc) /** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; * Otp block5 word1 data. */ @@ -3155,7 +3155,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W2_REG register * eFuse apb2otp block5 data register2. */ -#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x600) +#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE0_BASE + 0x600) /** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; * Otp block5 word2 data. */ @@ -3167,7 +3167,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W3_REG register * eFuse apb2otp block5 data register3. */ -#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x604) +#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE0_BASE + 0x604) /** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; * Otp block5 word3 data. */ @@ -3179,7 +3179,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W4_REG register * eFuse apb2otp block5 data register4. */ -#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x608) +#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE0_BASE + 0x608) /** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; * Otp block5 word4 data. */ @@ -3191,7 +3191,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W5_REG register * eFuse apb2otp block5 data register5. */ -#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x60c) +#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE0_BASE + 0x60c) /** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; * Otp block5 word5 data. */ @@ -3203,7 +3203,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W6_REG register * eFuse apb2otp block5 data register6. */ -#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x610) +#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE0_BASE + 0x610) /** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; * Otp block5 word6 data. */ @@ -3215,7 +3215,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W7_REG register * eFuse apb2otp block5 data register7. */ -#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x614) +#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE0_BASE + 0x614) /** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; * Otp block5 word7 data. */ @@ -3227,7 +3227,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W8_REG register * eFuse apb2otp block5 data register8. */ -#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x618) +#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE0_BASE + 0x618) /** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; * Otp block5 word8 data. */ @@ -3239,7 +3239,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W9_REG register * eFuse apb2otp block5 data register9. */ -#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x61c) +#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE0_BASE + 0x61c) /** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; * Otp block5 word9 data. */ @@ -3251,7 +3251,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W10_REG register * eFuse apb2otp block5 data register10. */ -#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x620) +#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE0_BASE + 0x620) /** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; * Otp block5 word10 data. */ @@ -3263,7 +3263,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK5_W11_REG register * eFuse apb2otp block5 data register11. */ -#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x624) +#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE0_BASE + 0x624) /** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; * Otp block5 word11 data. */ @@ -3275,7 +3275,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W1_REG register * eFuse apb2otp block6 data register1. */ -#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x628) +#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE0_BASE + 0x628) /** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; * Otp block6 word1 data. */ @@ -3287,7 +3287,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W2_REG register * eFuse apb2otp block6 data register2. */ -#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x62c) +#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE0_BASE + 0x62c) /** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; * Otp block6 word2 data. */ @@ -3299,7 +3299,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W3_REG register * eFuse apb2otp block6 data register3. */ -#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x630) +#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE0_BASE + 0x630) /** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; * Otp block6 word3 data. */ @@ -3311,7 +3311,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W4_REG register * eFuse apb2otp block6 data register4. */ -#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x634) +#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE0_BASE + 0x634) /** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; * Otp block6 word4 data. */ @@ -3323,7 +3323,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W5_REG register * eFuse apb2otp block6 data register5. */ -#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x638) +#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE0_BASE + 0x638) /** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; * Otp block6 word5 data. */ @@ -3335,7 +3335,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W6_REG register * eFuse apb2otp block6 data register6. */ -#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x63c) +#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE0_BASE + 0x63c) /** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; * Otp block6 word6 data. */ @@ -3347,7 +3347,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W7_REG register * eFuse apb2otp block6 data register7. */ -#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x640) +#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE0_BASE + 0x640) /** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; * Otp block6 word7 data. */ @@ -3359,7 +3359,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W8_REG register * eFuse apb2otp block6 data register8. */ -#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x644) +#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE0_BASE + 0x644) /** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; * Otp block6 word8 data. */ @@ -3371,7 +3371,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W9_REG register * eFuse apb2otp block6 data register9. */ -#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x648) +#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE0_BASE + 0x648) /** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; * Otp block6 word9 data. */ @@ -3383,7 +3383,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W10_REG register * eFuse apb2otp block6 data register10. */ -#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x64c) +#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE0_BASE + 0x64c) /** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; * Otp block6 word10 data. */ @@ -3395,7 +3395,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK6_W11_REG register * eFuse apb2otp block6 data register11. */ -#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x650) +#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE0_BASE + 0x650) /** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; * Otp block6 word11 data. */ @@ -3407,7 +3407,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W1_REG register * eFuse apb2otp block7 data register1. */ -#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x654) +#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE0_BASE + 0x654) /** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; * Otp block7 word1 data. */ @@ -3419,7 +3419,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W2_REG register * eFuse apb2otp block7 data register2. */ -#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x658) +#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE0_BASE + 0x658) /** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; * Otp block7 word2 data. */ @@ -3431,7 +3431,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W3_REG register * eFuse apb2otp block7 data register3. */ -#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x65c) +#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE0_BASE + 0x65c) /** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; * Otp block7 word3 data. */ @@ -3443,7 +3443,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W4_REG register * eFuse apb2otp block7 data register4. */ -#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x660) +#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE0_BASE + 0x660) /** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; * Otp block7 word4 data. */ @@ -3455,7 +3455,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W5_REG register * eFuse apb2otp block7 data register5. */ -#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x664) +#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE0_BASE + 0x664) /** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; * Otp block7 word5 data. */ @@ -3467,7 +3467,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W6_REG register * eFuse apb2otp block7 data register6. */ -#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x668) +#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE0_BASE + 0x668) /** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; * Otp block7 word6 data. */ @@ -3479,7 +3479,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W7_REG register * eFuse apb2otp block7 data register7. */ -#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x66c) +#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE0_BASE + 0x66c) /** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; * Otp block7 word7 data. */ @@ -3491,7 +3491,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W8_REG register * eFuse apb2otp block7 data register8. */ -#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x670) +#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE0_BASE + 0x670) /** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; * Otp block7 word8 data. */ @@ -3503,7 +3503,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W9_REG register * eFuse apb2otp block7 data register9. */ -#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x674) +#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE0_BASE + 0x674) /** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; * Otp block7 word9 data. */ @@ -3515,7 +3515,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W10_REG register * eFuse apb2otp block7 data register10. */ -#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x678) +#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE0_BASE + 0x678) /** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; * Otp block7 word10 data. */ @@ -3527,7 +3527,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK7_W11_REG register * eFuse apb2otp block7 data register11. */ -#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x67c) +#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE0_BASE + 0x67c) /** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; * Otp block7 word11 data. */ @@ -3539,7 +3539,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W1_REG register * eFuse apb2otp block8 data register1. */ -#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x680) +#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE0_BASE + 0x680) /** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; * Otp block8 word1 data. */ @@ -3551,7 +3551,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W2_REG register * eFuse apb2otp block8 data register2. */ -#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x684) +#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE0_BASE + 0x684) /** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; * Otp block8 word2 data. */ @@ -3563,7 +3563,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W3_REG register * eFuse apb2otp block8 data register3. */ -#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x688) +#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE0_BASE + 0x688) /** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; * Otp block8 word3 data. */ @@ -3575,7 +3575,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W4_REG register * eFuse apb2otp block8 data register4. */ -#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x68c) +#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE0_BASE + 0x68c) /** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; * Otp block8 word4 data. */ @@ -3587,7 +3587,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W5_REG register * eFuse apb2otp block8 data register5. */ -#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x690) +#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE0_BASE + 0x690) /** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; * Otp block8 word5 data. */ @@ -3599,7 +3599,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W6_REG register * eFuse apb2otp block8 data register6. */ -#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x694) +#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE0_BASE + 0x694) /** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; * Otp block8 word6 data. */ @@ -3611,7 +3611,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W7_REG register * eFuse apb2otp block8 data register7. */ -#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x698) +#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE0_BASE + 0x698) /** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; * Otp block8 word7 data. */ @@ -3623,7 +3623,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W8_REG register * eFuse apb2otp block8 data register8. */ -#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x69c) +#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE0_BASE + 0x69c) /** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; * Otp block8 word8 data. */ @@ -3635,7 +3635,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W9_REG register * eFuse apb2otp block8 data register9. */ -#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x6a0) +#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE0_BASE + 0x6a0) /** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; * Otp block8 word9 data. */ @@ -3647,7 +3647,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W10_REG register * eFuse apb2otp block8 data register10. */ -#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x6a4) +#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE0_BASE + 0x6a4) /** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; * Otp block8 word10 data. */ @@ -3659,7 +3659,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK8_W11_REG register * eFuse apb2otp block8 data register11. */ -#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x6a8) +#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE0_BASE + 0x6a8) /** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; * Otp block8 word11 data. */ @@ -3671,7 +3671,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W1_REG register * eFuse apb2otp block9 data register1. */ -#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x6ac) +#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE0_BASE + 0x6ac) /** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; * Otp block9 word1 data. */ @@ -3683,7 +3683,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W2_REG register * eFuse apb2otp block9 data register2. */ -#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x6b0) +#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE0_BASE + 0x6b0) /** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; * Otp block9 word2 data. */ @@ -3695,7 +3695,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W3_REG register * eFuse apb2otp block9 data register3. */ -#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x6b4) +#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE0_BASE + 0x6b4) /** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; * Otp block9 word3 data. */ @@ -3707,7 +3707,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W4_REG register * eFuse apb2otp block9 data register4. */ -#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x6b8) +#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE0_BASE + 0x6b8) /** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; * Otp block9 word4 data. */ @@ -3719,7 +3719,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W5_REG register * eFuse apb2otp block9 data register5. */ -#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x6bc) +#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE0_BASE + 0x6bc) /** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; * Otp block9 word5 data. */ @@ -3731,7 +3731,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W6_REG register * eFuse apb2otp block9 data register6. */ -#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x6c0) +#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE0_BASE + 0x6c0) /** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; * Otp block9 word6 data. */ @@ -3743,7 +3743,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W7_REG register * eFuse apb2otp block9 data register7. */ -#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x6c4) +#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE0_BASE + 0x6c4) /** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; * Otp block9 word7 data. */ @@ -3755,7 +3755,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W8_REG register * eFuse apb2otp block9 data register8. */ -#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x6c8) +#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE0_BASE + 0x6c8) /** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; * Otp block9 word8 data. */ @@ -3767,7 +3767,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W9_REG register * eFuse apb2otp block9 data register9. */ -#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x6cc) +#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE0_BASE + 0x6cc) /** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; * Otp block9 word9 data. */ @@ -3779,7 +3779,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W10_REG register * eFuse apb2otp block9 data register10. */ -#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x6d0) +#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE0_BASE + 0x6d0) /** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; * Otp block9 word10 data. */ @@ -3791,7 +3791,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK9_W11_REG register * eFuse apb2otp block9 data register11. */ -#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x6d4) +#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE0_BASE + 0x6d4) /** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; * Otp block9 word11 data. */ @@ -3803,7 +3803,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W1_REG register * eFuse apb2otp block10 data register1. */ -#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x6d8) +#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE0_BASE + 0x6d8) /** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; * Otp block10 word1 data. */ @@ -3815,7 +3815,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W2_REG register * eFuse apb2otp block10 data register2. */ -#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x6dc) +#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE0_BASE + 0x6dc) /** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; * Otp block10 word2 data. */ @@ -3827,7 +3827,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W3_REG register * eFuse apb2otp block10 data register3. */ -#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x6e0) +#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE0_BASE + 0x6e0) /** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; * Otp block10 word3 data. */ @@ -3839,7 +3839,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W4_REG register * eFuse apb2otp block10 data register4. */ -#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x6e4) +#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE0_BASE + 0x6e4) /** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; * Otp block10 word4 data. */ @@ -3851,7 +3851,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W5_REG register * eFuse apb2otp block10 data register5. */ -#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x6e8) +#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE0_BASE + 0x6e8) /** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; * Otp block10 word5 data. */ @@ -3863,7 +3863,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W6_REG register * eFuse apb2otp block10 data register6. */ -#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x6ec) +#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE0_BASE + 0x6ec) /** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; * Otp block10 word6 data. */ @@ -3875,7 +3875,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W7_REG register * eFuse apb2otp block10 data register7. */ -#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x6f0) +#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE0_BASE + 0x6f0) /** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; * Otp block10 word7 data. */ @@ -3887,7 +3887,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W8_REG register * eFuse apb2otp block10 data register8. */ -#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x6f4) +#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE0_BASE + 0x6f4) /** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; * Otp block10 word8 data. */ @@ -3899,7 +3899,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W9_REG register * eFuse apb2otp block10 data register9. */ -#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x6f8) +#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE0_BASE + 0x6f8) /** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; * Otp block10 word9 data. */ @@ -3911,7 +3911,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W10_REG register * eFuse apb2otp block10 data register10. */ -#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x6fc) +#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE0_BASE + 0x6fc) /** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0; * Otp block10 word10 data. */ @@ -3923,7 +3923,7 @@ extern "C" { /** EFUSE_APB2OTP_BLK10_W11_REG register * eFuse apb2otp block10 data register11. */ -#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0x700) +#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE0_BASE + 0x700) /** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; * Otp block10 word11 data. */ @@ -3935,7 +3935,7 @@ extern "C" { /** EFUSE_APB2OTP_EN_REG register * eFuse apb2otp enable configuration register. */ -#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0x708) +#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE0_BASE + 0x708) /** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0; * Apb2otp mode enable signal. */ diff --git a/components/soc/esp32c61/include/soc/efuse_struct.h b/components/soc/esp32c61/include/soc/efuse_struct.h index 77da6e32ce..a03db5bcf2 100644 --- a/components/soc/esp32c61/include/soc/efuse_struct.h +++ b/components/soc/esp32c61/include/soc/efuse_struct.h @@ -3356,8 +3356,8 @@ typedef struct { volatile efuse_apb2otp_en_reg_t apb2otp_en; } efuse_dev_t; -extern efuse_dev_t EFUSE_AND_OTP_DEBUG0; -extern efuse_dev_t EFUSE_AND_OTP_DEBUG1; +extern efuse_dev_t EFUSE0; +extern efuse_dev_t EFUSE1; #ifndef __cplusplus _Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure"); diff --git a/components/soc/esp32c61/include/soc/ext_mem_defs.h b/components/soc/esp32c61/include/soc/ext_mem_defs.h new file mode 100644 index 0000000000..7a90cc93b5 --- /dev/null +++ b/components/soc/esp32c61/include/soc/ext_mem_defs.h @@ -0,0 +1,153 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + + +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) + +#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range +#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range + +#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW +#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH + +#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW +#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH + +#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr) +#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr) +#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr) +#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr) + +#define SOC_MMU_ACCESS_FLASH 0 +#define SOC_MMU_ACCESS_SPIRAM BIT(9) +#define SOC_MMU_VALID BIT(10) +#define SOC_MMU_SENSITIVE BIT(11) +#define SOC_MMU_INVALID_MASK BIT(10) +#define SOC_MMU_INVALID 0 + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define SOC_MMU_VALID_VAL_MASK 0x3ff +/** + * Max MMU available paddr page num. + * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define SOC_MMU_MAX_PADDR_PAGE_NUM 512 +//MMU entry num +#define SOC_MMU_ENTRY_NUM 512 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & SOC_MMU_VADDR_MASK + */ +#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) + +#define SOC_MMU_DBUS_VADDR_BASE 0x42000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x42000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +#if (SOC_MMU_PAGE_SIZE == 0x10000) +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x7F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x8000) +/** + * - 32KB MMU page size: the last 0x7FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x3F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x4000) +/** + * - 16KB MMU page size: the last 0x3FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x1F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF +#endif //SOC_MMU_PAGE_SIZE + +/** + * - If high linear address isn't 0, this means MMU can recognize these addresses + * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. + * Under this condition, we use the max linear space. + */ +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +/** + * I/D share the MMU linear address range + */ +#ifndef __cplusplus +_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); +#endif + + +/** + * ROM flash mmap driver needs below definitions + */ +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define ICACHE_MMU_SIZE 0x200 +#define DCACHE_MMU_SIZE 0x200 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x200 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_num.h b/components/soc/esp32c61/include/soc/gpio_num.h new file mode 100644 index 0000000000..4b574a3bfb --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_num.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//TODO: [ESP32C61] IDF-9316, check pins attribute +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO number + */ +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_MAX, +} gpio_num_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_pins.h b/components/soc/esp32c61/include/soc/gpio_pins.h new file mode 100644 index 0000000000..607e691514 --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_pins.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_sig_map.h b/components/soc/esp32c61/include/soc/gpio_sig_map.h index a2bc325aed..10eb7cec7a 100644 --- a/components/soc/esp32c61/include/soc/gpio_sig_map.h +++ b/components/soc/esp32c61/include/soc/gpio_sig_map.h @@ -6,6 +6,7 @@ #pragma once +// version date 2310090 #define EXT_ADC_START_IDX 0 #define LEDC_LS_SIG_OUT0_IDX 0 #define LEDC_LS_SIG_OUT1_IDX 1 @@ -175,4 +176,5 @@ #define MODEM_DIAG29_IDX 158 #define MODEM_DIAG30_IDX 159 #define MODEM_DIAG31_IDX 160 -// version date 2310090 + +#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h new file mode 100644 index 0000000000..8e80288ead --- /dev/null +++ b/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h @@ -0,0 +1,222 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" + +//TODO: [ESP32C61] IDF-9276, inherit from c6 + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_V 0x1 +#define I2C_ANA_MST_I2C0_BUSY_S 25 +/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_S 0 + +#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_V 0x1 +#define I2C_ANA_MST_I2C1_BUSY_S 25 +/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_S 0 + +#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_STATUS 0x000000FF +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_V 0xFF +#define I2C_ANA_MST_I2C0_STATUS_S 24 +/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C0_CONF_S 0 + +#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) +/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_STATUS 0x000000FF +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_V 0xFF +#define I2C_ANA_MST_I2C1_STATUS_S 24 +/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C1_CONF_S 0 + +#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF +#define I2C_ANA_MST_BURST_CTRL_S 0 + +#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 +/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) +#define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 +/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) +#define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 +/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_DONE (BIT(0)) +#define I2C_ANA_MST_BURST_DONE_M (BIT(0)) +#define I2C_ANA_MST_BURST_DONE_V 0x1 +#define I2C_ANA_MST_BURST_DONE_S 0 + +#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS0 0x000000FF +#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S)) +#define I2C_ANA_MST_ANA_STATUS0_V 0xFF +#define I2C_ANA_MST_ANA_STATUS0_S 24 +/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) +#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF0_S 0 + +#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) +/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS1 0x000000FF +#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) +#define I2C_ANA_MST_ANA_STATUS1_V 0xFF +#define I2C_ANA_MST_ANA_STATUS1_S 24 +/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) +#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF1_S 0 + +#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS2 0x000000FF +#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S)) +#define I2C_ANA_MST_ANA_STATUS2_V 0xFF +#define I2C_ANA_MST_ANA_STATUS2_S 24 +/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S)) +#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF2_S 0 + +#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 +/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 +/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) +/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_V 0x1 +#define I2C_ANA_MST_ARBITER_DIS_S 11 +/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_NOUSE 0xFFFFFFFF +#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF +#define I2C_ANA_MST_NOUSE_S 0 + +#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_CLK_EN (BIT(28)) +#define I2C_ANA_MST_CLK_EN_M (BIT(28)) +#define I2C_ANA_MST_CLK_EN_V 0x1 +#define I2C_ANA_MST_CLK_EN_S 28 +/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/*description: .*/ +#define I2C_ANA_MST_DATE 0x0FFFFFFF +#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_V 0xFFFFFFF +#define I2C_ANA_MST_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/interrupt_reg.h b/components/soc/esp32c61/include/soc/interrupt_reg.h new file mode 100644 index 0000000000..6fe29fee6a --- /dev/null +++ b/components/soc/esp32c61/include/soc/interrupt_reg.h @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc_caps.h" +#include "soc/clic_reg.h" + +/** + * ESP32C61 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y) + */ + +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG) + +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG + +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE diff --git a/components/soc/esp32c61/include/soc/interrupts.h b/components/soc/esp32c61/include/soc/interrupts.h index 05ad352b2d..a77cd4ddef 100644 --- a/components/soc/esp32c61/include/soc/interrupts.h +++ b/components/soc/esp32c61/include/soc/interrupts.h @@ -35,15 +35,15 @@ typedef enum { ETS_LP_WDT_INTR_SOURCE, ETS_LP_PERI_TIMEOUT_INTR_SOURCE, ETS_LP_APM_M0_INTR_SOURCE, - ETS_CPU_INTR_FROM_CPU_0_SOURCE, - ETS_CPU_INTR_FROM_CPU_1_SOURCE, - ETS_CPU_INTR_FROM_CPU_2_SOURCE, - ETS_CPU_INTR_FROM_CPU_3_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, + ETS_FROM_CPU_INTR1_SOURCE, + ETS_FROM_CPU_INTR2_SOURCE, + ETS_FROM_CPU_INTR3_SOURCE, ETS_ASSIST_DEBUG_INTR_SOURCE, ETS_TRACE_INTR_SOURCE, ETS_CACHE_INTR_SOURCE, ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, - ETS_GPIO_INTERRUPT_PRO_SOURCE, + ETS_GPIO_INTR_SOURCE, ETS_GPIO_INTERRUPT_EXT_SOURCE, ETS_PAU_INTR_SOURCE, ETS_HP_PERI_TIMEOUT_INTR_SOURCE, @@ -62,10 +62,10 @@ typedef enum { ETS_I2C_EXT0_INTR_SOURCE, ETS_TG0_T0_INTR_SOURCE, ETS_TG0_T1_INTR_SOURCE, - ETS_TG0_WDT_INTR_SOURCE, + ETS_TG0_WDT_LEVEL_INTR_SOURCE, ETS_TG1_T0_INTR_SOURCE, ETS_TG1_T1_INTR_SOURCE, - ETS_TG1_WDT_INTR_SOURCE, + ETS_TG1_WDT_LEVEL_INTR_SOURCE, ETS_SYSTIMER_TARGET0_INTR_SOURCE, ETS_SYSTIMER_TARGET1_INTR_SOURCE, ETS_SYSTIMER_TARGET2_INTR_SOURCE, diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/include/soc/io_mux_reg.h index 9adf6ef7c8..17b2c01feb 100644 --- a/components/soc/esp32c61/include/soc/io_mux_reg.h +++ b/components/soc/esp32c61/include/soc/io_mux_reg.h @@ -67,6 +67,22 @@ extern "C" { #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) #define MCU_SEL_V 0x7 #define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) #define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) #define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) @@ -76,6 +92,8 @@ extern "C" { #define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) #define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P #define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N @@ -124,7 +142,6 @@ extern "C" { #define MAX_GPIO_NUM 34 #define HIGH_IO_HOLD_BIT_SHIFT 32 - #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE #define PIN_CTRL (REG_IO_MUX_BASE +0x00) #define PAD_POWER_SEL BIT(15) @@ -137,6 +154,20 @@ extern "C" { #define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) #define PAD_POWER_SWITCH_DELAY_S 12 +//TODO: [ESP32C61] IDF-9316, copy from verify +#define IO_MUX_CLK_OUT3 0x0000000F +#define IO_MUX_CLK_OUT3_M ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S)) +#define IO_MUX_CLK_OUT3_V 0xF +#define IO_MUX_CLK_OUT3_S 8 +#define IO_MUX_CLK_OUT2 0x0000000F +#define IO_MUX_CLK_OUT2_M ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S)) +#define IO_MUX_CLK_OUT2_V 0xF +#define IO_MUX_CLK_OUT2_S 4 +#define IO_MUX_CLK_OUT1 0x0000000F +#define IO_MUX_CLK_OUT1_M ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S)) +#define IO_MUX_CLK_OUT1_V 0xF +#define IO_MUX_CLK_OUT1_S 0 + #define CLK_OUT3 IO_MUX_CLK_OUT3 #define CLK_OUT3_V IO_MUX_CLK_OUT3_V #define CLK_OUT3_S IO_MUX_CLK_OUT3_S diff --git a/components/soc/esp32c61/include/soc/lp_ana_reg.h b/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_ana_reg.h rename to components/soc/esp32c61/include/soc/lp_analog_peri_reg.h diff --git a/components/soc/esp32c61/include/soc/lp_ana_struct.h b/components/soc/esp32c61/include/soc/lp_analog_peri_struct.h similarity index 100% rename from components/soc/esp32c61/include/soc/lp_ana_struct.h rename to components/soc/esp32c61/include/soc/lp_analog_peri_struct.h diff --git a/components/soc/esp32c61/include/soc/pcr_struct.h b/components/soc/esp32c61/include/soc/pcr_struct.h index 78d68658ca..87776e7631 100644 --- a/components/soc/esp32c61/include/soc/pcr_struct.h +++ b/components/soc/esp32c61/include/soc/pcr_struct.h @@ -1628,7 +1628,7 @@ typedef union { * 3: RC_SLOW_CLK\\ * 4: RC_FAST_CLK\\ */ - uint32_t 32k_sel:3; + uint32_t clk_32k_sel:3; uint32_t reserved_3:5; /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; * When PCR_32K_SEL set as 4, This field PCR_FOSC_TICK_NUM is used to set the divider diff --git a/components/soc/esp32c61/include/soc/periph_defs.h b/components/soc/esp32c61/include/soc/periph_defs.h new file mode 100644 index 0000000000..2950d1cb4c --- /dev/null +++ b/components/soc/esp32c61/include/soc/periph_defs.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/interrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + /* HP peripherals */ + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_SPI2_MODULE, //SPI2 + PERIPH_RNG_MODULE, + PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_ETM_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_TEMPSENSOR_MODULE, + PERIPH_REGDMA_MODULE, + PERIPH_ASSIST_DEBUG_MODULE, + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_IEEE802154_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, + PERIPH_ANA_I2C_MASTER_MODULE, + PERIPH_MODEM_ETM_MODULE, + PERIPH_MODEM_ADC_COMMON_FE_MODULE, + PERIPH_MODULE_MAX + /* !!! Don't append soc modules here !!! */ +} periph_module_t; + +#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pmu_struct.h b/components/soc/esp32c61/include/soc/pmu_struct.h index 3ea8cd5102..2ca2ee6801 100644 --- a/components/soc/esp32c61/include/soc/pmu_struct.h +++ b/components/soc/esp32c61/include/soc/pmu_struct.h @@ -6,2894 +6,750 @@ #pragma once #include +#include #ifdef __cplusplus extern "C" { #endif -/** Group: configure_register */ -/** Type of hp_active_dig_power register - * need_des - */ +#include "soc.h" +#include "soc/pmu_reg.h" + +// TODO: [ESP32C61] This file comes from verification branch typedef union { struct { - uint32_t reserved_0:21; - /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_active_vdd_spi_pd_en:1; - /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_hp_mem_dslp:1; - /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_mem_pd_en:4; - /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_wifi_pd_en:1; - /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_peri_pd_en:1; - /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_cpu_pd_en:1; - /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_aon_pd_en:1; - /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_pd_top_pd_en:1; + uint32_t reserved0 : 21; + uint32_t vdd_spi_pd_en: 1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t reserved1 : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; }; uint32_t val; -} pmu_hp_active_dig_power_reg_t; +} pmu_hp_dig_power_reg_t; -/** Type of hp_active_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_func_en:32; + uint32_t reserved0: 30; + uint32_t code : 2; }; uint32_t val; -} pmu_hp_active_icg_hp_func_reg_t; +} pmu_hp_icg_modem_reg_t; -/** Type of hp_active_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_apb_en:32; + uint32_t reserved0 : 24; + uint32_t uart_wakeup_en : 1; + uint32_t lp_pad_hold_all: 1; + uint32_t hp_pad_hold_all: 1; + uint32_t dig_pad_slp_sel: 1; + uint32_t dig_pause_wdt : 1; + uint32_t dig_cpu_stall : 1; + uint32_t reserved1 : 2; }; uint32_t val; -} pmu_hp_active_icg_hp_apb_reg_t; +} pmu_hp_sys_cntl_reg_t; -/** Type of hp_active_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_icg_modem_code:2; + uint32_t reserved0 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved1 : 1; }; uint32_t val; -} pmu_hp_active_icg_modem_reg_t; +} pmu_hp_clk_power_reg_t; -/** Type of hp_active_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_active_uart_wakeup_en:1; - /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_lp_pad_hold_all:1; - /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_pad_hold_all:1; - /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pad_slp_sel:1; - /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pause_wdt:1; - /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_dig_cpu_stall:1; - uint32_t reserved_30:2; + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_active_hp_sys_cntl_reg_t; +} pmu_hp_bias_reg_t; -/** Type of hp_active_hp_ck_power register - * need_des - */ typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_iso_en:1; - /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_retention:1; - /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bb_i2c:1; - /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll_i2c:1; - /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll:1; - uint32_t reserved_31:1; + struct { /* HP: Active State */ + uint32_t reserved0 : 4; + uint32_t hp_sleep2active_backup_modem_clk_code: 2; + uint32_t hp_modem2active_backup_modem_clk_code: 2; + uint32_t reserved1 : 2; + uint32_t hp_active_retention_mode : 1; + uint32_t hp_sleep2active_retention_en : 1; + uint32_t hp_modem2active_retention_en : 1; + uint32_t reserved2 : 1; + uint32_t hp_sleep2active_backup_clk_sel : 2; + uint32_t hp_modem2active_backup_clk_sel : 2; + uint32_t reserved3 : 2; + uint32_t hp_sleep2active_backup_mode : 3; + uint32_t hp_modem2active_backup_mode : 3; + uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_en : 1; + uint32_t hp_modem2active_backup_en : 1; + uint32_t reserved5 : 1; + }; + struct { /* HP: Modem State */ + uint32_t reserved6 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code : 2; + uint32_t reserved7 : 4; + uint32_t hp_modem_retention_mode : 1; + uint32_t hp_sleep2modem_retention_en : 1; + uint32_t reserved8 : 2; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved9 : 4; + uint32_t hp_sleep2modem_backup_mode : 3; + uint32_t reserved10 : 6; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved11 : 2; + }; + struct { /* HP: Sleep State */ + uint32_t reserved12 : 6; + uint32_t hp_modem2sleep_backup_modem_clk_code : 2; + uint32_t hp_active2sleep_backup_modem_clk_code: 2; + uint32_t hp_sleep_retention_mode : 1; + uint32_t reserved13 : 1; + uint32_t hp_modem2sleep_retention_en : 1; + uint32_t hp_active2sleep_retention_en : 1; + uint32_t reserved14 : 2; + uint32_t hp_modem2sleep_backup_clk_sel : 2; + uint32_t hp_active2sleep_backup_clk_sel : 2; + uint32_t reserved15 : 3; + uint32_t hp_modem2sleep_backup_mode : 3; + uint32_t hp_active2sleep_backup_mode : 3; + uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_en : 1; + uint32_t hp_active2sleep_backup_en : 1; }; uint32_t val; -} pmu_hp_active_hp_ck_power_reg_t; +} pmu_hp_backup_reg_t; -/** Type of hp_active_bias register - * need_des - */ typedef union { struct { - uint32_t reserved_0:25; - /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bias:1; - /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_active_dbg_atten:4; - /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cur:1; - /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_bias_sleep:1; + uint32_t reserved0 : 26; + uint32_t dig_sysclk_nodiv: 1; + uint32_t icg_sysclk_en : 1; + uint32_t sysclk_slp_sel : 1; + uint32_t icg_slp_sel : 1; + uint32_t dig_sysclk_sel : 2; }; uint32_t val; -} pmu_hp_active_bias_reg_t; +} pmu_hp_sysclk_reg_t; -/** Type of hp_active_backup register - * need_des - */ typedef union { struct { - uint32_t reserved_0:4; - /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_modem_clk_code:2; - /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_modem_clk_code:2; - uint32_t reserved_8:2; - /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_active_retention_mode:1; - /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_retention_en:1; - /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hp_modem2active_retention_en:1; - uint32_t reserved_13:1; - /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_clk_sel:2; - /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_clk_sel:2; - uint32_t reserved_18:2; - /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_mode:3; - /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_mode:3; - uint32_t reserved_26:3; - /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_en:1; - /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_en:1; - uint32_t reserved_31:1; + uint32_t reserved0 : 4; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias: 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_active_backup_reg_t; +} pmu_hp_regulator0_reg_t; -/** Type of hp_active_backup_clk register - * need_des - */ typedef union { struct { - /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_active_backup_icg_func_en:32; + uint32_t reserved0: 8; + uint32_t drv_b : 24; }; uint32_t val; -} pmu_hp_active_backup_clk_reg_t; +} pmu_hp_regulator1_reg_t; -/** Type of hp_active_sysclk register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_no_div:1; - /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_icg_sys_clock_en:1; - /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_sys_clk_slp_sel:1; - /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_icg_slp_sel:1; - /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_sel:2; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_active_sysclk_reg_t; +} pmu_hp_xtal_reg_t; -/** Type of hp_active_hp_regulator0 register - * need_des - */ +typedef struct pmu_hp_hw_regmap_t{ + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; +} pmu_hp_hw_regmap_t; + +/** */ typedef union { struct { - uint32_t reserved_0:3; - /** hp_active_hp_regulator_slp_connect_en : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_connect_en:1; - /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; - * need_des - */ - uint32_t lp_dbias_vol:5; - /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; - * need_des - */ - uint32_t hp_dbias_vol:5; - /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; - * need_des - */ - uint32_t dig_regulator0_dbias_sel:1; - /** dig_dbias_init : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dig_dbias_init:1; - /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_xpd:1; - /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_xpd:1; - /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_xpd:1; - /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_dbias:4; - /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_dbias:4; - /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_active_hp_regulator_dbias:5; + uint32_t reserved0: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_active_hp_regulator0_reg_t; +} pmu_lp_regulator0_reg_t; -/** Type of hp_active_hp_regulator1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:8; - /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_active_hp_regulator_drv_b:24; + uint32_t reserved0: 28; + uint32_t drv_b : 4; }; uint32_t val; -} pmu_hp_active_hp_regulator1_reg_t; +} pmu_lp_regulator1_reg_t; -/** Type of hp_active_xtal register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtal:1; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_active_xtal_reg_t; +} pmu_lp_xtal_reg_t; -/** Type of hp_modem_dig_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:21; - /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_modem_vdd_spi_pd_en:1; - /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_mem_dslp:1; - /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_mem_pd_en:4; - /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_wifi_pd_en:1; - /** hp_modem_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_peri_pd_en:1; - /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_cpu_pd_en:1; - /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_aon_pd_en:1; - /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_top_pd_en:1; + uint32_t reserved0 : 30; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en: 1; }; uint32_t val; -} pmu_hp_modem_dig_power_reg_t; +} pmu_lp_dig_power_reg_t; -/** Type of hp_modem_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_modem_dig_icg_func_en:32; + uint32_t reserved0 : 28; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; }; uint32_t val; -} pmu_hp_modem_icg_hp_func_reg_t; +} pmu_lp_clk_power_reg_t; -/** Type of hp_modem_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_modem_dig_icg_apb_en:32; + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_modem_icg_hp_apb_reg_t; +} pmu_lp_bias_reg_t; + +typedef struct pmu_lp_hw_regmap_t{ + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +} pmu_lp_hw_regmap_t; + -/** Type of hp_modem_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_icg_modem_code:2; + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t reserved0 : 18; + uint32_t tie_high_global_bbpll_icg: 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; }; uint32_t val; -} pmu_hp_modem_icg_modem_reg_t; +} pmu_imm_hp_clk_power_reg_t; -/** Type of hp_modem_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_modem_uart_wakeup_en:1; - /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_modem_lp_pad_hold_all:1; - /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_pad_hold_all:1; - /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_pad_slp_sel:1; - /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_pause_wdt:1; - /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_modem_hp_sys_cntl_reg_t; - -/** Type of hp_modem_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_i2c_iso_en:1; - /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_i2c_retention:1; - /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bb_i2c:1; - /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bbpll_i2c:1; - /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_modem_hp_ck_power_reg_t; - -/** Type of hp_modem_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bias:1; - /** hp_modem_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_modem_dbg_atten:4; - /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_cur:1; - /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_modem_bias_reg_t; - -/** Type of hp_modem_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_modem_clk_code:2; - uint32_t reserved_6:4; - /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_modem_retention_mode:1; - /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_retention_en:1; - uint32_t reserved_12:2; - /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_clk_sel:2; - uint32_t reserved_16:4; - /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_mode:3; - uint32_t reserved_23:6; - /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_modem_backup_reg_t; - -/** Type of hp_modem_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_modem_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_modem_backup_clk_reg_t; - -/** Type of hp_modem_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_sys_clk_no_div:1; - /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_icg_sys_clock_en:1; - /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_sys_clk_slp_sel:1; - /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_icg_slp_sel:1; - /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_modem_sysclk_reg_t; - -/** Type of hp_modem_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:15; - /** hp_modem_hp_regulator_slp_connect_en : R/W; bitpos: [15]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_connect_en:1; - /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; - /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; - /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_xpd:1; - /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; - /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; - /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_modem_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_modem_hp_regulator0_reg_t; - -/** Type of hp_modem_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_modem_hp_regulator1_reg_t; - -/** Type of hp_modem_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_modem_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_modem_xtal_reg_t; - -/** Type of hp_sleep_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_spi_pd_en:1; - /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_mem_dslp:1; - /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_mem_pd_en:4; - /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_wifi_pd_en:1; - /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_peri_pd_en:1; - /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_cpu_pd_en:1; - /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_aon_pd_en:1; - /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_dig_power_reg_t; - -/** Type of hp_sleep_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_func_reg_t; - -/** Type of hp_sleep_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_apb_reg_t; - -/** Type of hp_sleep_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_sleep_icg_modem_reg_t; - -/** Type of hp_sleep_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_sleep_uart_wakeup_en:1; - /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_hold_all:1; - /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_pad_hold_all:1; - /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pad_slp_sel:1; - /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pause_wdt:1; - /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_sleep_hp_sys_cntl_reg_t; - -/** Type of hp_sleep_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_iso_en:1; - /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_retention:1; - /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bb_i2c:1; - /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll_i2c:1; - /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_sleep_hp_ck_power_reg_t; - -/** Type of hp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bias:1; - /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dbg_atten:4; - /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cur:1; - /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_sleep_bias_reg_t; - -/** Type of hp_sleep_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_modem_clk_code:2; - /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_modem_clk_code:2; - /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_sleep_retention_mode:1; - uint32_t reserved_11:1; - /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_retention_en:1; - /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_retention_en:1; - uint32_t reserved_14:2; - /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_clk_sel:2; - /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_clk_sel:2; - uint32_t reserved_20:3; - /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_mode:3; - /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_mode:3; - uint32_t reserved_29:1; - /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_en:1; - /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_en:1; - }; - uint32_t val; -} pmu_hp_sleep_backup_reg_t; - -/** Type of hp_sleep_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_backup_clk_reg_t; - -/** Type of hp_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_no_div:1; - /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_sys_clock_en:1; - /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_sys_clk_slp_sel:1; - /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_slp_sel:1; - /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_sleep_sysclk_reg_t; - -/** Type of hp_sleep_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:15; - /** hp_sleep_hp_regulator_slp_connect_en : R/W; bitpos: [15]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_connect_en:1; - /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; - /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; - /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_xpd:1; - /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; - /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; - /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_sleep_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator0_reg_t; - -/** Type of hp_sleep_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator1_reg_t; - -/** Type of hp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_sleep_xtal_reg_t; - -/** Type of hp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_xpd:1; - /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_xpd:1; - /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_dbias:4; - /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator0_reg_t; - -/** Type of hp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator1_reg_t; - -/** Type of hp_sleep_lp_dcdc_reserve register - * need_des - */ -typedef union { - struct { - /** hp_sleep_lp_dcdc_reserve : WT; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_dcdc_reserve:32; - }; - uint32_t val; -} pmu_hp_sleep_lp_dcdc_reserve_reg_t; - -/** Type of hp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_mem_dslp:1; - /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_dig_power_reg_t; - -/** Type of hp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_xtal32k:1; - /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_rc32k:1; - /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_fosc_clk:1; - /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_lp_bias_reserve register - * need_des - */ -typedef union { - struct { - /** lp_sleep_lp_bias_reserve : WT; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_bias_reserve:32; - }; - uint32_t val; -} pmu_lp_sleep_lp_bias_reserve_reg_t; - -/** Type of lp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_xpd:1; - /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_xpd:1; - /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_dbias:4; - /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t lp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator0_reg_t; - -/** Type of lp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator1_reg_t; - -/** Type of lp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_lp_sleep_xtal_reg_t; - -/** Type of lp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_mem_dslp:1; - /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_dig_power_reg_t; - -/** Type of lp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_xtal32k:1; - /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_rc32k:1; - /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_fosc_clk:1; - /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_bias:1; - /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t lp_sleep_dbg_atten:4; - /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_cur:1; - /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_lp_sleep_bias_reg_t; - -/** Type of imm_hp_ck_power register - * need_des - */ -typedef union { - struct { - /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t tie_low_global_bbpll_icg:1; - /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtal_icg:1; - /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_retention:1; - /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bb_i2c:1; - /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll_i2c:1; - /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll:1; - /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtal:1; - uint32_t reserved_7:18; - /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t tie_high_global_bbpll_icg:1; - /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtal_icg:1; - /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_retention:1; - /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bb_i2c:1; - /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll_i2c:1; - /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll:1; - /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_xtal:1; - }; - uint32_t val; -} pmu_imm_hp_ck_power_reg_t; - -/** Type of imm_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t update_dig_icg_switch:1; - /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_icg_slp_sel:1; - /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_icg_slp_sel:1; - /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_sys_clk_sel:1; + uint32_t reserved0 : 28; + uint32_t update_dig_icg_switch: 1; + uint32_t tie_low_icg_slp_sel : 1; + uint32_t tie_high_icg_slp_sel : 1; + uint32_t update_dig_sysclk_sel: 1; }; uint32_t val; } pmu_imm_sleep_sysclk_reg_t; -/** Type of imm_hp_func_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_func_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_func_en: 1; }; uint32_t val; } pmu_imm_hp_func_icg_reg_t; -/** Type of imm_hp_apb_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_apb_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_apb_en: 1; }; uint32_t val; } pmu_imm_hp_apb_icg_reg_t; -/** Type of imm_modem_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_modem_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_modem_en: 1; }; uint32_t val; } pmu_imm_modem_icg_reg_t; -/** Type of imm_lp_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_low_lp_rootclk_sel:1; - /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_lp_rootclk_sel:1; + uint32_t reserved0 : 30; + uint32_t tie_low_lp_rootclk_sel : 1; + uint32_t tie_high_lp_rootclk_sel: 1; }; uint32_t val; } pmu_imm_lp_icg_reg_t; -/** Type of imm_pad_hold_all register - * need_des - */ typedef union { struct { - uint32_t reserved_0:28; - /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_lp_pad_hold_all:1; - /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_lp_pad_hold_all:1; - /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_hp_pad_hold_all:1; - /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_hp_pad_hold_all:1; + uint32_t reserved0 : 28; + uint32_t tie_high_lp_pad_hold_all: 1; + uint32_t tie_low_lp_pad_hold_all : 1; + uint32_t tie_high_hp_pad_hold_all: 1; + uint32_t tie_low_hp_pad_hold_all : 1; }; uint32_t val; } pmu_imm_pad_hold_all_reg_t; -/** Type of imm_i2c_iso register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_iso_en:1; - /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_iso_en:1; + uint32_t reserved0 : 30; + uint32_t tie_high_i2c_iso_en: 1; + uint32_t tie_low_i2c_iso_en : 1; }; uint32_t val; -} pmu_imm_i2c_iso_reg_t; +} pmu_imm_i2c_isolate_reg_t; + +typedef struct pmu_imm_hw_regmap_t{ + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; +} pmu_imm_hw_regmap_t; -/** Type of power_wait_timer0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:5; - /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_hp_powerdown_timer:9; - /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_hp_powerup_timer:9; - /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_hp_pd_wait_timer:9; + uint32_t reserved0 : 5; + uint32_t powerdown_timer: 9; + uint32_t powerup_timer : 9; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer0_reg_t; -/** Type of power_wait_timer1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:9; - /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; - * need_des - */ - uint32_t dg_lp_powerdown_timer:7; - /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; - * need_des - */ - uint32_t dg_lp_powerup_timer:7; - /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_lp_pd_wait_timer:9; + uint32_t reserved0 : 9; + uint32_t powerdown_timer: 7; + uint32_t powerup_timer : 7; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer1_reg_t; -/** Type of power_wait_timer2 register - * need_des - */ typedef union { struct { - /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; - * need_des - */ - uint32_t dg_lp_iso_wait_timer:8; - /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; - * need_des - */ - uint32_t dg_lp_rst_wait_timer:8; - /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; - * need_des - */ - uint32_t dg_hp_iso_wait_timer:8; - /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; - * need_des - */ - uint32_t dg_hp_rst_wait_timer:8; + uint32_t force_reset : 1; + uint32_t force_iso : 1; + uint32_t force_pu : 1; + uint32_t force_no_reset: 1; + uint32_t force_no_iso : 1; + uint32_t force_pd : 1; + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ }; uint32_t val; -} pmu_power_wait_timer2_reg_t; +} pmu_power_domain_cntl_reg_t; -/** Type of power_pd_top_cntl register - * need_des - */ typedef union { struct { - /** force_top_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_top_reset:1; - /** force_top_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_top_iso:1; - /** force_top_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_top_pu:1; - /** force_top_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_top_no_reset:1; - /** force_top_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_top_no_iso:1; - /** force_top_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_top_pd:1; - /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_top_mask:5; - uint32_t reserved_11:16; - /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_top_pd_mask:5; + uint32_t force_hp_mem_iso : 4; + uint32_t force_hp_mem_pd : 4; + uint32_t reserved0 : 16; + uint32_t force_hp_mem_no_iso: 4; + uint32_t force_hp_mem_pu : 4; }; uint32_t val; -} pmu_power_pd_top_cntl_reg_t; +} pmu_power_memory_cntl_reg_t; -/** Type of power_pd_hpaon_cntl register - * need_des - */ typedef union { struct { - /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_aon_reset:1; - /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_aon_iso:1; - /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_aon_pu:1; - /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_reset:1; - /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_iso:1; - /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_aon_pd:1; - /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_mask:5; - uint32_t reserved_11:16; - /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_pd_mask:5; + uint32_t mem2_pd_mask: 5; + uint32_t mem1_pd_mask: 5; + uint32_t mem0_pd_mask: 5; + uint32_t reserved0 : 2; + uint32_t mem2_mask : 5; + uint32_t mem1_mask : 5; + uint32_t mem0_mask : 5; }; uint32_t val; -} pmu_power_pd_hpaon_cntl_reg_t; +} pmu_power_memory_mask_reg_t; -/** Type of power_pd_hpcpu_cntl register - * need_des - */ typedef union { struct { - /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_reset:1; - /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_iso:1; - /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_pu:1; - /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_reset:1; - /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_iso:1; - /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_pd:1; - /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_mask:5; - uint32_t reserved_11:16; - /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpcpu_cntl_reg_t; - -/** Type of power_pd_hpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_peri_reset:1; - /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_peri_iso:1; - /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_peri_pu:1; - /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_reset:1; - /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_iso:1; - /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_peri_pd:1; - /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_mask:5; - uint32_t reserved_11:16; - /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpperi_cntl_reg_t; - -/** Type of power_pd_hpwifi_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_reset:1; - /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_iso:1; - /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_pu:1; - /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_reset:1; - /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_iso:1; - /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_pd:1; - /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_mask:5; - uint32_t reserved_11:16; - /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpwifi_cntl_reg_t; - -/** Type of power_pd_lpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_lp_peri_reset:1; - /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_lp_peri_iso:1; - /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_lp_peri_pu:1; - /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_reset:1; - /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_iso:1; - /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_lp_peri_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_lpperi_cntl_reg_t; - -/** Type of power_pd_mem_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; - * need_des - */ - uint32_t force_hp_mem_iso:4; - /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; - * need_des - */ - uint32_t force_hp_mem_pd:4; - uint32_t reserved_8:16; - /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; - * need_des - */ - uint32_t force_hp_mem_no_iso:4; - /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; - * need_des - */ - uint32_t force_hp_mem_pu:4; - }; - uint32_t val; -} pmu_power_pd_mem_cntl_reg_t; - -/** Type of power_pd_mem_mask register - * need_des - */ -typedef union { - struct { - /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_pd_mask:5; - /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_pd_mask:5; - /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_pd_mask:5; - uint32_t reserved_15:2; - /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_mask:5; - /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_mask:5; - /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_mask:5; - }; - uint32_t val; -} pmu_power_pd_mem_mask_reg_t; - -/** Type of power_hp_pad register - * need_des - */ -typedef union { - struct { - /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_pad_no_iso_all:1; - /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_pad_iso_all:1; - uint32_t reserved_2:30; + uint32_t force_hp_pad_no_iso_all: 1; + uint32_t force_hp_pad_iso_all : 1; + uint32_t reserved0 : 30; }; uint32_t val; } pmu_power_hp_pad_reg_t; -/** Type of power_vdd_spi_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:18; - /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; - * need_des - */ - uint32_t vdd_spi_pwr_wait:11; - /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; - * need_des - */ - uint32_t vdd_spi_pwr_sw:2; - /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t vdd_spi_pwr_sel_sw:1; + uint32_t reserved0 : 18; + uint32_t pwr_wait : 11; + uint32_t pwr_sw : 2; + uint32_t pwr_sel_sw: 1; }; uint32_t val; } pmu_power_vdd_spi_cntl_reg_t; -/** Type of power_ck_wait_cntl register - * need_des - */ typedef union { struct { - /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; - * need_des - */ - uint32_t wait_xtl_stable:16; - /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; - * need_des - */ - uint32_t wait_pll_stable:16; + uint32_t wait_xtal_stable: 16; + uint32_t wait_pll_stable : 16; }; uint32_t val; -} pmu_power_ck_wait_cntl_reg_t; +} pmu_power_clk_wait_cntl_reg_t; + +typedef struct pmu_power_hw_regmap_t{ + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_domain_cntl_reg_t hp_pd[5]; + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_vdd_spi_cntl_reg_t vdd_spi; + pmu_power_clk_wait_cntl_reg_t clk_wait; +} pmu_power_hw_regmap_t; -/** Type of slp_wakeup_cntl0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t sleep_req:1; + uint32_t reserved0: 31; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_slp_wakeup_cntl0_reg_t; -/** Type of slp_wakeup_cntl1 register - * need_des - */ typedef union { struct { - /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t sleep_reject_ena:31; - /** slp_reject_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_en:1; + uint32_t sleep_reject_ena: 31; + uint32_t slp_reject_en : 1; }; uint32_t val; } pmu_slp_wakeup_cntl1_reg_t; -/** Type of slp_wakeup_cntl2 register - * need_des - */ typedef union { struct { - /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_ena:32; - }; - uint32_t val; -} pmu_slp_wakeup_cntl2_reg_t; - -/** Type of slp_wakeup_cntl3 register - * need_des - */ -typedef union { - struct { - /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t lp_min_slp_val:8; - /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; - * need_des - */ - uint32_t hp_min_slp_val:8; - /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sleep_prt_sel:2; - uint32_t reserved_18:14; + uint32_t lp_min_slp_val: 8; + uint32_t hp_min_slp_val: 8; + uint32_t sleep_prt_sel : 2; + uint32_t reserved0 : 14; }; uint32_t val; } pmu_slp_wakeup_cntl3_reg_t; -/** Type of slp_wakeup_cntl4 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_cause_clr:1; + uint32_t reserved0 : 31; + uint32_t slp_reject_cause_clr: 1; }; uint32_t val; } pmu_slp_wakeup_cntl4_reg_t; -/** Type of slp_wakeup_cntl5 register - * need_des - */ typedef union { struct { - /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t modem_wait_target:20; - uint32_t reserved_20:4; - /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; - * need_des - */ - uint32_t lp_ana_wait_target:8; + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 4; + uint32_t lp_ana_wait_target: 8; }; uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; -/** Type of slp_wakeup_cntl6 register - * need_des - */ typedef union { struct { - /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t soc_wakeup_wait:20; - uint32_t reserved_20:10; - /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t soc_wakeup_wait_cfg:2; + uint32_t soc_wakeup_wait : 20; + uint32_t reserved0 : 10; + uint32_t soc_wakeup_wait_cfg: 2; }; uint32_t val; } pmu_slp_wakeup_cntl6_reg_t; -/** Type of slp_wakeup_cntl7 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:16; - /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; - * need_des - */ - uint32_t ana_wait_target:16; + uint32_t reserved0 : 16; + uint32_t ana_wait_target: 16; }; uint32_t val; } pmu_slp_wakeup_cntl7_reg_t; -/** Type of slp_wakeup_status0 register - * need_des - */ +typedef struct pmu_wakeup_hw_regmap_t{ + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + uint32_t status0; + uint32_t status1; +} pmu_wakeup_hw_regmap_t; + typedef union { struct { - /** wakeup_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_cause:32; + uint32_t i2c_por_wait_target: 8; + uint32_t reserved0 : 24; }; uint32_t val; -} pmu_slp_wakeup_status0_reg_t; +} pmu_hp_clk_poweron_reg_t; -/** Type of slp_wakeup_status1 register - * need_des - */ typedef union { struct { - /** reject_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t reject_cause:32; + uint32_t modify_icg_cntl_wait: 8; + uint32_t switch_icg_cntl_wait: 8; + uint32_t reserved0 : 16; }; uint32_t val; -} pmu_slp_wakeup_status1_reg_t; +} pmu_hp_clk_cntl_reg_t; -/** Type of hp_ck_poweron register - * need_des - */ typedef union { struct { - /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; - * need_des - */ - uint32_t i2c_por_wait_target:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} pmu_hp_ck_poweron_reg_t; - -/** Type of hp_ck_cntl register - * need_des - */ -typedef union { - struct { - /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; - * need_des - */ - uint32_t modify_icg_cntl_wait:8; - /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; - * need_des - */ - uint32_t switch_icg_cntl_wait:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} pmu_hp_ck_cntl_reg_t; - -/** Type of por_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** por_done : RO; bitpos: [31]; default: 1; - * need_des - */ - uint32_t por_done:1; + uint32_t reserved0: 31; + uint32_t por_done : 1; }; uint32_t val; } pmu_por_status_reg_t; -/** Type of rf_pwc register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** xpd_tc5g_i2c : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t xpd_tc5g_i2c:1; - /** xpd_rx5g_i2c : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t xpd_rx5g_i2c:1; - /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t perif_i2c_rstb:1; - /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t xpd_perif_i2c:1; - /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t xpd_txrf_i2c:1; - /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t xpd_rfrx_pbus:1; - /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xpd_ckgen_i2c:1; - /** xpd_pll_i2c : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t xpd_pll_i2c:1; + uint32_t reserved0 : 26; + uint32_t perif_i2c_rstb: 1; + uint32_t xpd_perif_i2c : 1; + uint32_t xpd_txrf_i2c : 1; + uint32_t xpd_rfrx_pbus : 1; + uint32_t xpd_ckgen_i2c : 1; + uint32_t xpd_pll_i2c : 1; }; uint32_t val; } pmu_rf_pwc_reg_t; -/** Type of backup_cfg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t backup_sys_clk_no_div:1; + uint32_t reserved0 : 31; + uint32_t backup_sysclk_nodiv: 1; }; uint32_t val; } pmu_backup_cfg_reg_t; -/** Type of int_raw register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_raw:1; - /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_raw:1; - /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_raw:1; - /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_raw:1; - /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_raw:1; + uint32_t reserved0 : 27; + uint32_t lp_cpu_exc: 1; + uint32_t sdio_idle : 1; + uint32_t sw : 1; + uint32_t reject : 1; + uint32_t wakeup : 1; }; uint32_t val; -} pmu_int_raw_reg_t; +} pmu_hp_intr_reg_t; + +typedef struct pmu_hp_ext_hw_regmap_t{ + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; +} pmu_hp_ext_hw_regmap_t; -/** Type of hp_int_st register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_st:1; - /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_st:1; - /** sw_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_st:1; - /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_st:1; - /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_st:1; + uint32_t reserved0 : 20; + uint32_t lp_cpu_wakeup : 1; + uint32_t modem_switch_active_end : 1; + uint32_t sleep_switch_active_end : 1; + uint32_t sleep_switch_modem_end : 1; + uint32_t modem_switch_sleep_end : 1; + uint32_t active_swtich_sleep_end : 1; + uint32_t modem_switch_active_start: 1; + uint32_t sleep_switch_active_start: 1; + uint32_t sleep_switch_modem_start : 1; + uint32_t modem_switch_sleep_start : 1; + uint32_t active_switch_sleep_start: 1; + uint32_t sw_trigger : 1; }; uint32_t val; -} pmu_hp_int_st_reg_t; +} pmu_lp_intr_reg_t; -/** Type of hp_int_ena register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_ena:1; - /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_ena:1; - /** sw_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_ena:1; - /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_ena:1; - /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_ena:1; - }; - uint32_t val; -} pmu_hp_int_ena_reg_t; - -/** Type of hp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_clr:1; - /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_clr:1; - /** sw_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_clr:1; - /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_clr:1; - /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_clr:1; - }; - uint32_t val; -} pmu_hp_int_clr_reg_t; - -/** Type of lp_int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_raw:1; - /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_raw:1; - /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_raw:1; - /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_raw:1; - /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_raw:1; - /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_raw:1; - /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_raw:1; - /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_raw:1; - /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_raw:1; - /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_raw:1; - /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_raw:1; - /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_raw:1; - }; - uint32_t val; -} pmu_lp_int_raw_reg_t; - -/** Type of lp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_st:1; - /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_st:1; - /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_st:1; - /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_st:1; - /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_st:1; - /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_st:1; - /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_st:1; - /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_st:1; - /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_st:1; - /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_st:1; - /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_st:1; - /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_st:1; - }; - uint32_t val; -} pmu_lp_int_st_reg_t; - -/** Type of lp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_ena:1; - /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_ena:1; - /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_ena:1; - /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_ena:1; - /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_ena:1; - /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_ena:1; - /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_ena:1; - /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_ena:1; - /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_ena:1; - /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_ena:1; - /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_ena:1; - /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_ena:1; - }; - uint32_t val; -} pmu_lp_int_ena_reg_t; - -/** Type of lp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_clr:1; - /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_clr:1; - /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_clr:1; - /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_clr:1; - /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_clr:1; - /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_clr:1; - /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_clr:1; - /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_clr:1; - /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_clr:1; - /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_clr:1; - /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_clr:1; - /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_clr:1; - }; - uint32_t val; -} pmu_lp_int_clr_reg_t; - -/** Type of lp_cpu_pwr0 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_cpu_waiti_rdy:1; - /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_cpu_stall_rdy:1; - uint32_t reserved_2:16; - /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; - * need_des - */ - uint32_t lp_cpu_force_stall:1; - /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_waiti_flag_en:1; - /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; - * need_des - */ - uint32_t lp_cpu_slp_stall_flag_en:1; - /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_cpu_slp_stall_wait:8; - /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_stall_en:1; - /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_reset_en:1; - /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_bypass_intr_en:1; + uint32_t waiti_rdy : 1; + uint32_t stall_rdy : 1; + uint32_t reserved0 : 16; + uint32_t force_stall : 1; + uint32_t slp_waiti_flag_en : 1; + uint32_t slp_stall_flag_en : 1; + uint32_t slp_stall_wait : 8; + uint32_t slp_stall_en : 1; + uint32_t slp_reset_en : 1; + uint32_t slp_bypass_intr_en: 1; }; uint32_t val; } pmu_lp_cpu_pwr0_reg_t; -/** Type of lp_cpu_pwr1 register - * need_des - */ typedef union { struct { - /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_en:16; - uint32_t reserved_16:15; - /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_req:1; + uint32_t wakeup_en: 16; + uint32_t reserved0: 15; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_lp_cpu_pwr1_reg_t; -/** Type of hp_lp_cpu_comm register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_trigger_hp : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_trigger_hp:1; - /** hp_trigger_lp : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_trigger_lp:1; - }; - uint32_t val; -} pmu_hp_lp_cpu_comm_reg_t; +typedef struct pmu_lp_ext_hw_regmap_t{ + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; +} pmu_lp_ext_hw_regmap_t; -/** Type of hp_regulator_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dig_regulator_en_cal:1; - }; - uint32_t val; -} pmu_hp_regulator_cfg_reg_t; +typedef struct pmu_dev_t{ + volatile pmu_hp_hw_regmap_t hp_sys[3]; + volatile pmu_lp_hw_regmap_t lp_sys[2]; + volatile pmu_imm_hw_regmap_t imm; + volatile pmu_power_hw_regmap_t power; + volatile pmu_wakeup_hw_regmap_t wakeup; + volatile pmu_hp_ext_hw_regmap_t hp_ext; + volatile pmu_lp_ext_hw_regmap_t lp_ext; -/** Type of main_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** main_last_st_state : RO; bitpos: [17:11]; default: 1; - * need_des - */ - uint32_t main_last_st_state:7; - /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; - * need_des - */ - uint32_t main_tar_st_state:7; - /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; - * need_des - */ - uint32_t main_cur_st_state:7; - }; - uint32_t val; -} pmu_main_state_reg_t; + union { + struct { + uint32_t reserved0 : 30; + volatile uint32_t lp_trigger_hp: 1; + volatile uint32_t hp_trigger_lp: 1; + }; + volatile uint32_t val; + } hp_lp_cpu_comm; -/** Type of pwr_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** backup_st_state : RO; bitpos: [17:13]; default: 1; - * need_des - */ - uint32_t backup_st_state:5; - /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t lp_pwr_st_state:5; - /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; - * need_des - */ - uint32_t hp_pwr_st_state:9; - }; - uint32_t val; -} pmu_pwr_state_reg_t; + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t dig_regulator_en_cal: 1; + }; + volatile uint32_t val; + } hp_regulator_cfg; -/** Type of date register - * need_des - */ -typedef union { - struct { - /** pmu_date : R/W; bitpos: [30:0]; default: 36770128; - * need_des - */ - uint32_t pmu_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} pmu_date_reg_t; + union { + struct { + uint32_t reserved0 : 11; + volatile uint32_t last_st : 7; + volatile uint32_t target_st : 7; + volatile uint32_t current_st: 7; + }; + volatile uint32_t val; + } main_state; + union { + struct { + uint32_t reserved0: 13; + volatile uint32_t backup_st: 5; + volatile uint32_t lp_pwr_st: 5; + volatile uint32_t hp_pwr_st: 9; + }; + volatile uint32_t val; + } pwr_state; -/** Group: status_register */ -/** Type of clk_state0 register - * need_des - */ -typedef union { - struct { - /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t stable_xpd_bbpll_state:1; - /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; - * need_des - */ - uint32_t stable_xpd_xtal_state:1; - uint32_t reserved_2:13; - /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; - * need_des - */ - uint32_t sys_clk_slp_sel_state:1; - /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sys_clk_sel_state:2; - /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; - * need_des - */ - uint32_t sys_clk_no_div_state:1; - /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; - * need_des - */ - uint32_t icg_sys_clk_en_state:1; - /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t icg_modem_switch_state:1; - /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; - * need_des - */ - uint32_t icg_modem_code_state:2; - /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t icg_slp_sel_state:1; - /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t icg_global_xtal_state:1; - /** icg_global_pll_state : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t icg_global_pll_state:1; - /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_i2c_iso_en_state:1; - /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_i2c_retention_state:1; - /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t ana_xpd_bb_i2c_state:1; - /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_i2c_state:1; - /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_state:1; - /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t ana_xpd_xtal_state:1; - }; - uint32_t val; -} pmu_clk_state0_reg_t; + union { + struct { + volatile uint32_t stable_xpd_bbpll : 1; + volatile uint32_t stable_xpd_xtal : 1; + volatile uint32_t reserved0 : 13; + volatile uint32_t sysclk_slp_sel : 1; + volatile uint32_t sysclk_sel : 2; + volatile uint32_t sysclk_nodiv : 1; + volatile uint32_t icg_sysclk_en : 1; + volatile uint32_t icg_modem_switch : 1; + volatile uint32_t icg_modem_code : 2; + volatile uint32_t icg_slp_sel : 1; + volatile uint32_t icg_global_xtal : 1; + volatile uint32_t icg_global_pll : 1; + volatile uint32_t ana_i2c_iso_en : 1; + volatile uint32_t ana_i2c_retention: 1; + volatile uint32_t ana_xpd_bb_i2c : 1; + volatile uint32_t ana_xpd_bbpll_i2c: 1; + volatile uint32_t ana_xpd_bbpll : 1; + volatile uint32_t ana_xpd_xtal : 1; + }; + volatile uint32_t val; + } clk_state0; -/** Type of clk_state1 register - * need_des - */ -typedef union { - struct { - /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_func_en_state:32; - }; - uint32_t val; -} pmu_clk_state1_reg_t; + volatile uint32_t clk_state1; + volatile uint32_t clk_state2; -/** Type of clk_state2 register - * need_des - */ -typedef union { - struct { - /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_apb_en_state:32; - }; - uint32_t val; -} pmu_clk_state2_reg_t; + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t stable_vdd_spi_pwr_drv: 1; + }; + volatile uint32_t val; + } vdd_spi_status; -/** Type of vdd_spi_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t stable_vdd_spi_pwr_drv:1; - }; - uint32_t val; -} pmu_vdd_spi_status_reg_t; + uint32_t reserved[150]; - -typedef struct { - volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; - volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; - volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; - volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; - volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; - volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; - volatile pmu_hp_active_bias_reg_t hp_active_bias; - volatile pmu_hp_active_backup_reg_t hp_active_backup; - volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; - volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; - volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; - volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; - volatile pmu_hp_active_xtal_reg_t hp_active_xtal; - volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; - volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; - volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; - volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; - volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; - volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; - volatile pmu_hp_modem_bias_reg_t hp_modem_bias; - volatile pmu_hp_modem_backup_reg_t hp_modem_backup; - volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; - volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; - volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; - volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; - volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; - volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; - volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; - volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; - volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; - volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; - volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; - volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; - volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; - volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; - volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; - volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; - volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; - volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; - volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; - volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; - volatile pmu_hp_sleep_lp_dcdc_reserve_reg_t hp_sleep_lp_dcdc_reserve; - volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; - volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; - volatile pmu_lp_sleep_lp_bias_reserve_reg_t lp_sleep_lp_bias_reserve; - volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; - volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; - volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; - volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; - volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; - volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; - volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; - volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; - volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; - volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; - volatile pmu_imm_modem_icg_reg_t imm_modem_icg; - volatile pmu_imm_lp_icg_reg_t imm_lp_icg; - volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; - volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; - volatile pmu_power_wait_timer0_reg_t power_wait_timer0; - volatile pmu_power_wait_timer1_reg_t power_wait_timer1; - volatile pmu_power_wait_timer2_reg_t power_wait_timer2; - volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; - volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; - volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; - volatile pmu_power_pd_hpperi_cntl_reg_t power_pd_hpperi_cntl; - volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; - volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; - volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; - volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; - volatile pmu_power_hp_pad_reg_t power_hp_pad; - volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; - volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; - volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; - volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; - volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; - volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; - volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; - volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; - volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; - volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; - volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; - volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; - volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; - volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; - volatile pmu_por_status_reg_t por_status; - volatile pmu_rf_pwc_reg_t rf_pwc; - volatile pmu_backup_cfg_reg_t backup_cfg; - volatile pmu_int_raw_reg_t int_raw; - volatile pmu_hp_int_st_reg_t hp_int_st; - volatile pmu_hp_int_ena_reg_t hp_int_ena; - volatile pmu_hp_int_clr_reg_t hp_int_clr; - volatile pmu_lp_int_raw_reg_t lp_int_raw; - volatile pmu_lp_int_st_reg_t lp_int_st; - volatile pmu_lp_int_ena_reg_t lp_int_ena; - volatile pmu_lp_int_clr_reg_t lp_int_clr; - volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; - volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; - volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; - volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile pmu_main_state_reg_t main_state; - volatile pmu_pwr_state_reg_t pwr_state; - volatile pmu_clk_state0_reg_t clk_state0; - volatile pmu_clk_state1_reg_t clk_state1; - volatile pmu_clk_state2_reg_t clk_state2; - volatile pmu_vdd_spi_status_reg_t vdd_spi_status; - volatile pmu_date_reg_t date; + union { + struct { + volatile uint32_t pmu_date: 31; + volatile uint32_t clk_en : 1; + }; + volatile uint32_t val; + } date; } pmu_dev_t; extern pmu_dev_t PMU; #ifndef __cplusplus -_Static_assert(sizeof(pmu_dev_t) == 0x1ac, "Invalid size of pmu_dev_t structure"); +// _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); + +// _Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); + #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 4747578d47..161bcdaba3 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -6,55 +6,56 @@ #pragma once -#define DR_REG_UART0_BASE 0x60000000 -#define DR_REG_UART1_BASE 0x60001000 -#define DR_REG_MSPI0_BASE 0x60002000 -#define DR_REG_MSPI1_BASE 0x60003000 -#define DR_REG_I2C_BASE 0x60004000 -#define DR_REG_UART2_BASE 0x60006000 -#define DR_REG_LEDC_BASE 0x60007000 -#define DR_REG_TIMG0_BASE 0x60008000 -#define DR_REG_TIMG1_BASE 0x60009000 -#define DR_REG_SYSTIMER_BASE 0x6000A000 -#define DR_REG_I2S_BASE 0x6000C000 -#define DR_REG_SARADC_BASE 0x6000E000 -#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 -#define DR_REG_SOC_ETM_BASE 0x60013000 -#define DR_REG_PVT_MONITOR_BASE 0x60019000 -#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 -#define DR_REG_AHB_GDMA_BASE 0x60080000 -#define DR_REG_GPSPI_BASE 0x60081000 -#define DR_REG_SHA_BASE 0x60089000 -#define DR_REG_ECC_BASE 0x6008B000 -#define DR_REG_ECDSA_BASE 0x6008E000 -#define DR_REG_IO_MUX_BASE 0x60090000 -#define DR_REG_GPIO_BASE 0x60091000 -#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000 -#define DR_REG_PAU_BASE 0x60093000 -#define DR_REG_HP_SYSTEM_REG_BASE 0x60095000 -#define DR_REG_PCR_REG_BASE 0x60096000 -#define DR_REG_TEE_REG_BASE 0x60098000 -#define DR_REG_HP_APM_REG_BASE 0x60099000 -#define DR_REG_MISC_BASE 0x6009F000 -#define DR_REG_MODEM0_BASE 0x600A0000 -#define DR_REG_MODEM1_BASE 0x600AC000 -#define DR_REG_MODEM_PWR0_BASE 0x600AD000 -#define DR_REG_MODEM_PWR1_BASE 0x600AF000 -#define DR_REG_PMU_BASE 0x600B0000 -#define DR_REG_LP_CLKRST_BASE 0x600B0400 -#define DR_REG_LP_TIMER_BASE 0x600B0C00 -#define DR_REG_LP_AON_BASE 0x600B1000 -#define DR_REG_LP_WDT_BASE 0x600B1C00 -#define DR_REG_LPPERI_BASE 0x600B2800 -#define DR_REG_LP_ANA_REG_BASE 0x600B2C00 -#define DR_REG_LP_TEE_BASE 0x600B3400 -#define DR_REG_LP_APM_BASE 0x600B3800 -#define DR_REG_LP_IO_MUX_BASE 0x600B4000 -#define DR_REG_LP_GPIO_BASE 0x600B4400 -#define DR_REG_EFUSE_AND_OTP_DEBUG0_BASE 0x600B4800 -#define DR_REG_EFUSE_AND_OTP_DEBUG1_BASE 0x600B4C00 -#define DR_REG_TRACE_BASE 0x600C0000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 -#define DR_REG_INTPRI_REG_BASE 0x600C5000 -#define DR_REG_CACHE_CFG_BASE 0x600C8000 +#define DR_REG_UART0_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_MSPI0_BASE 0x60002000 +#define DR_REG_MSPI1_BASE 0x60003000 +#define DR_REG_I2C_BASE 0x60004000 +#define DR_REG_UART2_BASE 0x60006000 +#define DR_REG_LEDC_BASE 0x60007000 +#define DR_REG_TIMG0_BASE 0x60008000 +#define DR_REG_TIMG1_BASE 0x60009000 +#define DR_REG_SYSTIMER_BASE 0x6000A000 +#define DR_REG_I2S_BASE 0x6000C000 +#define DR_REG_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_PVT_MONITOR_BASE 0x60019000 +#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 +#define DR_REG_AHB_GDMA_BASE 0x60080000 +#define DR_REG_GPSPI_BASE 0x60081000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_ECC_BASE 0x6008B000 +#define DR_REG_ECDSA_BASE 0x6008E000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_REG_BASE 0x60098000 +#define DR_REG_HP_APM_REG_BASE 0x60099000 +#define DR_REG_MISC_BASE 0x6009F000 +#define DR_REG_MODEM0_BASE 0x600A0000 +#define DR_REG_MODEM1_BASE 0x600AC000 +#define DR_REG_MODEM_PWR0_BASE 0x600AD000 +#define DR_REG_MODEM_PWR1_BASE 0x600AF000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 //TODO: [ESP32C61] IDF-9276, from verify +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANA_BASE 0x600B2C00 +#define DR_REG_LP_TEE_BASE 0x600B3400 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_LP_IO_MUX_BASE 0x600B4000 +#define DR_REG_LP_GPIO_BASE 0x600B4400 +#define DR_REG_EFUSE0_BASE 0x600B4800 +#define DR_REG_EFUSE1_BASE 0x600B4C00 +#define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 +#define DR_REG_INTPRI_BASE 0x600C5000 +#define DR_REG_CACHE_BASE 0x600C8000 diff --git a/components/soc/esp32c61/include/soc/regi2c_bbpll.h b/components/soc/esp32c61/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..236c3fed39 --- /dev/null +++ b/components/soc/esp32c61/include/soc/regi2c_bbpll.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 diff --git a/components/soc/esp32c61/include/soc/regi2c_bias.h b/components/soc/esp32c61/include/soc/regi2c_bias.h new file mode 100644 index 0000000000..49572123be --- /dev/null +++ b/components/soc/esp32c61/include/soc/regi2c_bias.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * bootloader_hardware_init function in bootloader_esp32c6.c. + */ + +#define I2C_BIAS 0X6A +#define I2C_BIAS_HOSTID 0 + +#define I2C_BIAS_DREG_1P1_PVT 1 +#define I2C_BIAS_DREG_1P1_PVT_MSB 3 +#define I2C_BIAS_DREG_1P1_PVT_LSB 0 diff --git a/components/soc/esp32c61/include/soc/regi2c_defs.h b/components/soc/esp32c61/include/soc/regi2c_defs.h new file mode 100644 index 0000000000..9de6bd6385 --- /dev/null +++ b/components/soc/esp32c61/include/soc/regi2c_defs.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +#define I2C_MST_ANA_CONF0_REG 0x600AF818 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) + + +#define ANA_CONFIG_REG 0x600AF81C +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + + +#define ANA_CONFIG2_REG 0x600AF820 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32c61/include/soc/regi2c_dig_reg.h b/components/soc/esp32c61/include/soc/regi2c_dig_reg.h new file mode 100644 index 0000000000..9e2bd628ca --- /dev/null +++ b/components/soc/esp32c61/include/soc/regi2c_dig_reg.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_dig_reg.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DIG_REG 0x6D +#define I2C_DIG_REG_HOSTID 0 + +#define I2C_DIG_REG_EXT_RTC_DREG 4 +#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_RTC_DREG 4 +#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_RTC_DREG 5 +#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG 6 +#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_DIG_DREG 6 +#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_DIG_DREG 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_OR_EN_CONT_CAL 9 +#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7 +#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7 + +#define I2C_DIG_REG_XPD_RTC_REG 13 +#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 +#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 + +#define I2C_DIG_REG_XPD_DIG_REG 13 +#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 +#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 + +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32c61/include/soc/regi2c_lp_bias.h b/components/soc/esp32c61/include/soc/regi2c_lp_bias.h new file mode 100644 index 0000000000..ed1340625b --- /dev/null +++ b/components/soc/esp32c61/include/soc/regi2c_lp_bias.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_lp_bias.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of low power dbais, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_init function in rtc_init.c. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 0 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 + +#define I2C_ULP_IR_FORCE_XPD_CK 0 +#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 +#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 + +#define I2C_ULP_IR_FORCE_XPD_IPH 0 +#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4 +#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4 + +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6 + +#define I2C_ULP_O_DONE_FLAG 3 +#define I2C_ULP_O_DONE_FLAG_MSB 0 +#define I2C_ULP_O_DONE_FLAG_LSB 0 + +#define I2C_ULP_BG_O_DONE_FLAG 3 +#define I2C_ULP_BG_O_DONE_FLAG_MSB 3 +#define I2C_ULP_BG_O_DONE_FLAG_LSB 3 + +#define I2C_ULP_OCODE 4 +#define I2C_ULP_OCODE_MSB 7 +#define I2C_ULP_OCODE_LSB 0 + +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 6 +#define I2C_ULP_IR_FORCE_CODE_LSB 6 + +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 diff --git a/components/soc/esp32c61/include/soc/reset_reasons.h b/components/soc/esp32c61/include/soc/reset_reasons.h new file mode 100644 index 0000000000..074d599720 --- /dev/null +++ b/components/soc/esp32c61/include/soc/reset_reasons.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system) + RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core (hp system) + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system) + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system) + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system) + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system) + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system) + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system) + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/retention_periph_defs.h b/components/soc/esp32c61/include/soc/retention_periph_defs.h new file mode 100644 index 0000000000..8c4440f10e --- /dev/null +++ b/components/soc/esp32c61/include/soc/retention_periph_defs.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum periph_retention_module_bitmap { + /* clock module, which includes system and modem */ + SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = BIT(1), + SLEEP_RETENTION_MODULE_CLOCK_MODEM = BIT(2), + + /* modem module, which includes WiFi, BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_WIFI_MAC = BIT(10), + SLEEP_RETENTION_MODULE_WIFI_BB = BIT(11), + SLEEP_RETENTION_MODULE_BLE_MAC = BIT(12), + SLEEP_RETENTION_MODULE_BT_BB = BIT(13), + SLEEP_RETENTION_MODULE_802154_MAC = BIT(14), + + /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, + * TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */ + SLEEP_RETENTION_MODULE_INTR_MATRIX = BIT(16), + SLEEP_RETENTION_MODULE_HP_SYSTEM = BIT(17), + SLEEP_RETENTION_MODULE_TEE_APM = BIT(18), + SLEEP_RETENTION_MODULE_UART0 = BIT(19), + SLEEP_RETENTION_MODULE_TG0 = BIT(20), + SLEEP_RETENTION_MODULE_IOMUX = BIT(21), + SLEEP_RETENTION_MODULE_SPIMEM = BIT(22), + SLEEP_RETENTION_MODULE_SYSTIMER = BIT(23), + SLEEP_RETENTION_MODULE_GDMA_CH0 = BIT(24), + SLEEP_RETENTION_MODULE_GDMA_CH1 = BIT(25), + SLEEP_RETENTION_MODULE_GDMA_CH2 = BIT(26), + SLEEP_RETENTION_MODULE_I2C0 = BIT(27), + SLEEP_RETENTION_MODULE_ALL = (uint32_t)-1 +} periph_retention_module_bitmap_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h new file mode 100644 index 0000000000..d3421c5978 --- /dev/null +++ b/components/soc/esp32c61/include/soc/soc.h @@ -0,0 +1,240 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 +#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 +#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61 + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define APB_CLK_FREQ ( 40*1000000 ) +#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +#define XTAL_CLK_FREQ (40*1000000) +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x44000000 +#define SOC_EXTRAM_DATA_LOW 0x42000000 +#define SOC_EXTRAM_DATA_HIGH 0x44000000 +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x4004AC00 +#define SOC_DROM_MASK_LOW 0x4004AC00 +#define SOC_DROM_MASK_HIGH 0x40070000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40850000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40850000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C61 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50004000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50004000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50004000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40850000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40850000 + +#define MAP_DRAM_TO_IRAM(addr) (addr) +#define MAP_IRAM_TO_DRAM(addr) (addr) + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40850000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40850000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40850000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40850000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4084c9f0 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h new file mode 100644 index 0000000000..505474d50d --- /dev/null +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -0,0 +1,572 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32C61] IDF-9321 +#define SOC_UART_SUPPORTED 1 //TODO: [ESP32C61] IDF-9320 +// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 +// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 +// #define SOC_GPTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9306 +// #define SOC_BT_SUPPORTED 1 +// #define SOC_IEEE802154_SUPPORTED 1 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 //TODO: [ESP32C61] IDF-9315 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9319 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322 +// #define SOC_WIFI_SUPPORTED 1 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 +// #define SOC_ULP_SUPPORTED 1 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32C61] IDF-9282 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274 +// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313 +// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9335 +// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32C61] IDF-9299, IDF-9300, IDF-9301 +// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9291 +// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9296, IDF-9297 +#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9307, IDF-9308 +// #define SOC_SUPPORT_COEXISTENCE 1 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9234 +// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9323 +// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32C61] IDF-9325 +// #define SOC_ECC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9235 +#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9232 +// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9233 +// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32C61] IDF-9254 +// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9230 +// #define SOC_PMU_SUPPORTED 1 +// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9244 +// #define SOC_LP_AON_SUPPORTED 1 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 +// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32C61] IDF-9249 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9270 +// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9257 +#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32C61] IDF-9314 +// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236 +// #define SOC_MODEM_CLOCK_SUPPORTED 1 +// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9276 + +// #define SOC_PCNT_SUPPORTED 0 //TODO: [ESP32C61] IDF-9332 +// #define SOC_MCPWM_SUPPORTED 0 //TODO: [ESP32C61] IDF-9338 +// #define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336 +// #define SOC_ETM_SUPPORTED 0 +// #define SOC_PARLIO_SUPPORTED 0 //TODO: [ESP32C61] IDF-9333, 9334 +// #define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331 +// #define SOC_RMT_SUPPORTED 0 //TODO: [ESP32C61] IDF-9343 +// #define SOC_AES_SUPPORTED 0 //TODO: [ESP32C61] IDF-9328 +// #define SOC_SDIO_SLAVE_SUPPORTED 0 +// #define SOC_PAU_SUPPORTED 0 +// #define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337 +// #define SOC_ULP_LP_UART_SUPPORTED 0 //TODO: [ESP32C61] IDF-9329, IDF-9341 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_40M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +#define SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +#define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +#define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (1U) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +#define SOC_ADC_MAX_CHANNEL_NUM (7) +#define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +#define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +#define SOC_ADC_SHARED_POWER 1 + +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_PLIC_SUPPORTED 0 //riscv platform-level interrupt controller +#define SOC_INT_CLIC_SUPPORTED 1 +#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting +#define SOC_BRANCH_PREDICTOR_SUPPORTED 1 + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes + +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +//TODO: [ESP32C61] IDF-9325 (Copy from esp32c6, need check) +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule + +/*-------------------------- ETM CAPS --------------------------------------*/ +#define SOC_ETM_GROUPS 1U // Number of ETM groups +#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C61 has 1 GPIO peripheral +#define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 31 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: [ESP32C61] IDF-9340 + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9340 +#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +#define SOC_GPIO_ETM_TASKS_PER_GROUP 8 + +// Target has the full LP IO subsystem +// On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C61 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) //TODO:reopen + +#define SOC_GPIO_VALID_GPIO_MASK ((1U< SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) //TODO: [ESP32C61] IDF-9255 +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +#define SOC_SPI_MEM_SUPPORT_WRAP (1) + +#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +#define SOC_TIMER_SUPPORT_ETM (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +#define SOC_MWDT_SUPPORT_XTAL (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_CONTROLLER_NUM 2 +#define SOC_TWAI_CLK_SUPPORT_XTAL 1 +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 32768 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + + +/*-------------------------- eFuse CAPS----------------------------*/ +#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +#define SOC_EFUSE_DIS_PAD_JTAG 1 +#define SOC_EFUSE_DIS_USB_JTAG 1 +#define SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define SOC_EFUSE_SOFT_DIS_JTAG 1 +#define SOC_EFUSE_DIS_ICACHE 1 +#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block + +/*-------------------------- Secure Boot CAPS----------------------------*/ +#define SOC_SECURE_BOOT_V2_RSA 0 +#define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C61 has 3 UARTs (2 HP UART, and 1 LP UART) +#define SOC_UART_NUM (3) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_LP_NUM (1U) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +// TODO: IDF-5351 (Copy from esp32c3, need check) +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +#define SOC_PM_SUPPORT_BEACON_WAKEUP (1) +#define SOC_PM_SUPPORT_BT_WAKEUP (1) +#define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! -#include "soc/soc.h" +// TODO: [ESP32C61] IDF-9314, This file comes from verification code #ifdef __cplusplus extern "C" { #endif +#include "soc.h" -/** SPI_MEM_CMD_REG register - * SPI0 FSM status register - */ -#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0) -/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; - * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , - * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent - * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - */ -#define SPI_MEM_MST_ST 0x0000000FU -#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) -#define SPI_MEM_MST_ST_V 0x0000000FU -#define SPI_MEM_MST_ST_S 0 -/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; - * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, - * 2: send command state, 3: send address state, 4: wait state, 5: read data state, - * 6:write data state, 7: done state, 8: read data end state. - */ -#define SPI_MEM_SLV_ST 0x0000000FU -#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) -#define SPI_MEM_SLV_ST_V 0x0000000FU -#define SPI_MEM_SLV_ST_S 4 -/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T +he bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the bit is set. The +bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when the bit is set. The + bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b +e cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered when the bit is + set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will be triggered when t +he bit is set. The bit will be cleared once the operation done.1: enable 0: disa +ble..*/ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera +tion will be triggered when the bit is set. The bit will be cleared once the op +eration done .1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit +is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit + is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T +he bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered when the bit is set +. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat +e or high performance mode and obtains the devices ID. The bit will be cleared o +nce the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operat +ion done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 +/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat +ion will be triggered when the bit is set. The bit will be cleared once the oper +ation done.1: enable 0: disable..*/ #define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) -#define SPI_MEM_USR_V 0x00000001U +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 #define SPI_MEM_USR_S 18 +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: In user mode, it is set to indicate that program/erase operation will be trigger +ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o +peration done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 +/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta +te, 2: send command state, 3: send address state, 4: wait state, 5: read data st +ate, 6:write data state, 7: done state, 8: read data end state..*/ +#define SPI_MEM_SLV_ST 0x0000000F +#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) +#define SPI_MEM_SLV_ST_V 0xF +#define SPI_MEM_SLV_ST_S 4 +/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT +, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se +nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/ +#define SPI_MEM_MST_ST 0x0000000F +#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) +#define SPI_MEM_MST_ST_V 0xF +#define SPI_MEM_MST_ST_S 0 -/** SPI_MEM_CTRL_REG register - * SPI0 control register. - */ -#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8) -/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_DQS is output by the MSPI controller. - */ -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 -/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_IO[7:0] is output by the MSPI controller. - */ -#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 -/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; - * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the first half part of dummy phase. It is used to - * mask invalid SPI_DQS in the half part of dummy phase. - */ -#define SPI_MEM_FDUMMY_RIN (BIT(2)) -#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) -#define SPI_MEM_FDUMMY_RIN_V 0x00000001U -#define SPI_MEM_FDUMMY_RIN_S 2 -/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; - * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the second half part of dummy phase. It is used to - * pre-drive flash. - */ -#define SPI_MEM_FDUMMY_WOUT (BIT(3)) -#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) -#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_FDUMMY_WOUT_S 3 -/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; - * Apply 8 signals during write-data phase 1:enable 0: disable - */ -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) -#define SPI_MEM_FDOUT_OCT_V 0x00000001U -#define SPI_MEM_FDOUT_OCT_S 4 -/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; - * Apply 8 signals during read-data phase 1:enable 0: disable - */ -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) -#define SPI_MEM_FDIN_OCT_V 0x00000001U -#define SPI_MEM_FDIN_OCT_S 5 -/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; - * Apply 8 signals during address phase 1:enable 0: disable - */ -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) -#define SPI_MEM_FADDR_OCT_V 0x00000001U -#define SPI_MEM_FADDR_OCT_S 6 -/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable - */ -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) -#define SPI_MEM_FCMD_QUAD_V 0x00000001U -#define SPI_MEM_FCMD_QUAD_S 8 -/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable - */ -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) -#define SPI_MEM_FCMD_OCT_V 0x00000001U -#define SPI_MEM_FCMD_OCT_S 9 -/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - */ -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) -#define SPI_MEM_FASTRD_MODE_V 0x00000001U -#define SPI_MEM_FASTRD_MODE_S 13 -/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - */ -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) -#define SPI_MEM_FREAD_DUAL_V 0x00000001U -#define SPI_MEM_FREAD_DUAL_S 14 -/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low - */ -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) -#define SPI_MEM_Q_POL_V 0x00000001U -#define SPI_MEM_Q_POL_S 18 -/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low - */ -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) -#define SPI_MEM_D_POL_V 0x00000001U -#define SPI_MEM_D_POL_S 19 -/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - */ -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) -#define SPI_MEM_FREAD_QUAD_V 0x00000001U -#define SPI_MEM_FREAD_QUAD_S 20 -/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. - */ -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) -#define SPI_MEM_WP_REG_V 0x00000001U -#define SPI_MEM_WP_REG_S 21 -/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; - * In the read operations address phase and read-data phase apply 2 signals. 1: enable - * 0: disable. - */ -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) -#define SPI_MEM_FREAD_DIO_V 0x00000001U -#define SPI_MEM_FREAD_DIO_S 23 -/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; - * In the read operations address phase and read-data phase apply 4 signals. 1: enable - * 0: disable. - */ -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) -#define SPI_MEM_FREAD_QIO_V 0x00000001U -#define SPI_MEM_FREAD_QIO_S 24 -/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always - * 1. 0: Others. - */ -#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) -#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are - * always 1. 0: Others. - */ +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory +address, the bit24-bit31 are the byte length of a transfer..*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a +lways 1. 0: Others..*/ #define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) -#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 #define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway +s 1. 0: Others..*/ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is set. 1: enable 0: d +isable..*/ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with +spi_mem_flash_res bit. 1: enable 0: disable..*/ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO +UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 +/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +e.*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 +/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +e low..*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 +/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 8 signals during address phase 1:enable 0: disable.*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 +/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 +/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 +/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] +is output by the MSPI controller in the second half part of dummy phase. It is u +sed to pre-drive flash..*/ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_V 0x1 +#define SPI_MEM_FDUMMY_WOUT_S 3 +/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i +s output by the MSPI controller in the first half part of dummy phase. It is use +d to mask invalid SPI_DQS in the half part of dummy phase..*/ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_V 0x1 +#define SPI_MEM_FDUMMY_RIN_S 2 +/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 -/** SPI_MEM_CTRL1_REG register - * SPI0 control1 register. - */ -#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc) -/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. - */ -#define SPI_MEM_CLK_MODE 0x00000003U -#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) -#define SPI_MEM_CLK_MODE_V 0x00000003U -#define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; - * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply - * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) -#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) -#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; - * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) -#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) -#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) -#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_AXI_RDATA_BACK_FAST_S 23 -/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; - * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. - */ -#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) -#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) -#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U -#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; - * Set this bit to enable AXI Read Splice-transfer. - */ -#define SPI_MEM_AR_SPLICE_EN (BIT(25)) -#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) -#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AR_SPLICE_EN_S 25 -/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable AXI Write Splice-transfer. - */ -#define SPI_MEM_AW_SPLICE_EN (BIT(26)) -#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) -#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AW_SPLICE_EN_S 26 -/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be - * accessed at the same time. - */ -#define SPI_MEM_RAM0_EN (BIT(27)) -#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) -#define SPI_MEM_RAM0_EN_V 0x00000001U -#define SPI_MEM_RAM0_EN_S 27 -/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; - * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the - * same time. - */ -#define SPI_MEM_DUAL_RAM_EN (BIT(28)) -#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) -#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U -#define SPI_MEM_DUAL_RAM_EN_S 28 -/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; - * Set this bit to write data faster, do not wait write data has been stored in - * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored - * in tx_bus_fifo_l2. - */ -#define SPI_MEM_FAST_WRITE_EN (BIT(29)) -#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) -#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U -#define SPI_MEM_FAST_WRITE_EN_S 29 -/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; - * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - * receive signals from AXI. Set this bit to reset these FIFO. - */ -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) -#define SPI_MEM_RXFIFO_RST_V 0x00000001U -#define SPI_MEM_RXFIFO_RST_S 30 -/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; - * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - * send signals to AXI. Set this bit to reset these FIFO. - */ +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) +/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + send signals to AXI. Set this bit to reset these FIFO..*/ #define SPI_MEM_TXFIFO_RST (BIT(31)) -#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) -#define SPI_MEM_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_TXFIFO_RST_M (BIT(31)) +#define SPI_MEM_TXFIFO_RST_V 0x1 #define SPI_MEM_TXFIFO_RST_S 31 +/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + receive signals from AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 +/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to write data faster, do not wait write data has been stored in tx_ +bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored +in tx_bus_fifo_l2..*/ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_V 0x1 +#define SPI_MEM_FAST_WRITE_EN_S 29 +/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at +the same time..*/ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_V 0x1 +#define SPI_MEM_DUAL_RAM_EN_S 28 +/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac +cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi +ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac +cessed at the same time..*/ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (BIT(27)) +#define SPI_MEM_RAM0_EN_V 0x1 +#define SPI_MEM_RAM0_EN_S 27 +/* SPI_MEM_AW_SPLICE_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Write Splice-transfer..*/ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_V 0x1 +#define SPI_MEM_AW_SPLICE_EN_S 26 +/* SPI_MEM_AR_SPLICE_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Read Splice-transfer..*/ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_V 0x1 +#define SPI_MEM_AR_SPLICE_EN_S 25 +/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + when there is a ECC error in AXI read data. The ECC error information is record +ed in SPI_MEM_ECC_ERR_ADDR_REG..*/ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x1 +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/* SPI_MEM_AXI_RDATA_BACK_FAST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R +eply AXI read data to AXI bus when all the read data is available..*/ +#define SPI_MEM_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_AXI_RDATA_BACK_FAST_M (BIT(23)) +#define SPI_MEM_AXI_RDATA_BACK_FAST_V 0x1 +#define SPI_MEM_AXI_RDATA_BACK_FAST_S 23 +/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M (BIT(22)) +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S 22 +/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl +y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M (BIT(21)) +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S 21 +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ +/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5 +12) SPI_CLK cycles..*/ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is alwasy on..*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 -/** SPI_MEM_CTRL2_REG register - * SPI0 control2 register. - */ -#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10) -/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; - * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. - */ -#define SPI_MEM_CS_SETUP_TIME 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) -#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_S 0 -/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; - * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. - */ -#define SPI_MEM_CS_HOLD_TIME 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) -#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_S 5 -/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. - */ -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; - * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when - * accesses flash. - */ -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses flash. - */ -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 -/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI - * transfers when one transfer will cross flash or EXT_RAM page corner, valid no - * matter whether there is an ECC region or not. - */ -#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) -#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) -#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_MEM_SPLIT_TRANS_EN_S 24 -/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI - * core clock cycles. - */ -#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) -#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_S 25 -/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; - * The spi0_mst_st and spi0_slv_st will be reset. - */ +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The spi0_mst_st and spi0_slv_st will be reset..*/ #define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) -#define SPI_MEM_SYNC_RESET_V 0x00000001U +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 #define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core + clock cycles..*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans +fers when one transfer will cross flash or EXT_RAM page corner, valid no matter +whether there is an ECC region or not..*/ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses flash..*/ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w +hen accesses flash..*/ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + mode when accessed flash..*/ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ +/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi +th SPI_MEM_CS_HOLD bit..*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ +/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME +M_CS_SETUP bit..*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 -/** SPI_MEM_CLOCK_REG register - * SPI clock division control register. - */ -#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14) -/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. - */ -#define SPI_MEM_CLKCNT_L 0x000000FFU -#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) -#define SPI_MEM_CLKCNT_L_V 0x000000FFU -#define SPI_MEM_CLKCNT_L_S 0 -/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). - */ -#define SPI_MEM_CLKCNT_H 0x000000FFU -#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) -#define SPI_MEM_CLKCNT_H_V 0x000000FFU -#define SPI_MEM_CLKCNT_H_S 8 -/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) - */ -#define SPI_MEM_CLKCNT_N 0x000000FFU -#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) -#define SPI_MEM_CLKCNT_N_V 0x000000FFU -#define SPI_MEM_CLKCNT_N_S 16 -/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - * clock. - */ +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + clock..*/ #define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 #define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 -/** SPI_MEM_USER_REG register - * SPI0 user register. - */ -#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18) -/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) -#define SPI_MEM_CS_HOLD_V 0x00000001U -#define SPI_MEM_CS_HOLD_S 6 -/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - */ -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) -#define SPI_MEM_CS_SETUP_V 0x00000001U -#define SPI_MEM_CS_SETUP_S 7 -/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - */ -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) -#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U -#define SPI_MEM_CK_OUT_EDGE_S 9 -/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. - */ -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U -#define SPI_MEM_USR_DUMMY_IDLE_S 26 -/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. - */ +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation..*/ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation..*/ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation..*/ #define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) -#define SPI_MEM_USR_DUMMY_V 0x00000001U +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 #define SPI_MEM_USR_DUMMY_S 29 +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation..*/ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation..*/ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable..*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. +1: enable 0: disable..*/ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1 +: enable 0: disable..*/ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals..*/ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals..*/ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals.*/ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals.*/ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 -/** SPI_MEM_USER1_REG register - * SPI0 user1 register. - */ -#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c) -/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). - */ -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; - * SPI0 USR_CMD read or write data byte length -1 - */ -#define SPI_MEM_USR_DBYTELEN 0x0000003FU -#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) -#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU -#define SPI_MEM_USR_DBYTELEN_S 6 -/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). - */ -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F #define SPI_MEM_USR_ADDR_BITLEN_S 26 +/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[11:6] ;default: 6'd1 ; */ +/*description: SPI0 USR_CMD read or write data byte length -1.*/ +#define SPI_MEM_USR_DBYTELEN 0x0000003F +#define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S)) +#define SPI_MEM_USR_DBYTELEN_V 0x3F +#define SPI_MEM_USR_DBYTELEN_S 6 +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ +/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy +cle_num-1)..*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USER2_REG register - * SPI0 user2 register. - */ -#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20) -/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; - * The value of command. - */ -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) -#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_S 0 -/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1) - */ -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF #define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command..*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 -/** SPI_MEM_RD_STATUS_REG register - * SPI0 read control register. - */ -#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_BASE + 0x2c) -/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - */ -#define SPI_MEM_WB_MODE 0x000000FFU -#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) -#define SPI_MEM_WB_MODE_V 0x000000FFU -#define SPI_MEM_WB_MODE_S 16 -/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; - * Mode bits length for flash fast read mode. - */ -#define SPI_MEM_WB_MODE_BITLEN 0x00000007U -#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) -#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U -#define SPI_MEM_WB_MODE_BITLEN_S 24 -/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; - * Mode bits is valid while this bit is enable. 1: enable 0: disable. - */ +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) +/* SPI_MEM_WB_MODE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Mode bits is valid while this bit is enable. 1: enable 0: disable..*/ #define SPI_MEM_WB_MODE_EN (BIT(27)) -#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) -#define SPI_MEM_WB_MODE_EN_V 0x00000001U +#define SPI_MEM_WB_MODE_EN_M (BIT(27)) +#define SPI_MEM_WB_MODE_EN_V 0x1 #define SPI_MEM_WB_MODE_EN_S 27 +/* SPI_MEM_WB_MODE_BITLEN : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: Mode bits length for flash fast read mode..*/ +#define SPI_MEM_WB_MODE_BITLEN 0x00000007 +#define SPI_MEM_WB_MODE_BITLEN_M ((SPI_MEM_WB_MODE_BITLEN_V)<<(SPI_MEM_WB_MODE_BITLEN_S)) +#define SPI_MEM_WB_MODE_BITLEN_V 0x7 +#define SPI_MEM_WB_MODE_BITLEN_S 24 +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b +it..*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/ +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 -/** SPI_MEM_MISC_REG register - * SPI0 misc register - */ -#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34) -/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; - * For SPI0, flash is connected to SUBPINs. - */ -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) -#define SPI_MEM_FSUB_PIN_V 0x00000001U -#define SPI_MEM_FSUB_PIN_S 7 -/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; - * For SPI0, sram is connected to SUBPINs. - */ -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) -#define SPI_MEM_SSUB_PIN_V 0x00000001U -#define SPI_MEM_SSUB_PIN_S 8 -/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; - * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - */ -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) -#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U -#define SPI_MEM_CK_IDLE_EDGE_S 9 -/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; - * SPI_CS line keep low when the bit is set. - */ +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: SPI_CS line keep low when the bit is set..*/ #define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 #define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0, sram is connected to SUBPINs..*/ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 +/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0, flash is connected to SUBPINs..*/ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 -/** SPI_MEM_CACHE_FCTRL_REG register - * SPI0 bit mode control register. - */ -#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c) -/** SPI_MEM_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; - * For SPI0, AXI master access enable, 1: enable, 0:disable. - */ -#define SPI_MEM_AXI_REQ_EN (BIT(0)) -#define SPI_MEM_AXI_REQ_EN_M (SPI_MEM_AXI_REQ_EN_V << SPI_MEM_AXI_REQ_EN_S) -#define SPI_MEM_AXI_REQ_EN_V 0x00000001U -#define SPI_MEM_AXI_REQ_EN_S 0 -/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; - * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - */ -#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x00000001U -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 -/** SPI_MEM_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; - * For SPI0, cache read flash for user define command, 1: enable, 0:disable. - */ -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (SPI_MEM_CACHE_FLASH_USR_CMD_V << SPI_MEM_CACHE_FLASH_USR_CMD_S) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x00000001U -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 -/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; - * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - */ -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) -#define SPI_MEM_FDIN_DUAL_V 0x00000001U -#define SPI_MEM_FDIN_DUAL_S 3 -/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; - * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - */ -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) -#define SPI_MEM_FDOUT_DUAL_V 0x00000001U -#define SPI_MEM_FDOUT_DUAL_S 4 -/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_dio. - */ -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) -#define SPI_MEM_FADDR_DUAL_V 0x00000001U -#define SPI_MEM_FADDR_DUAL_S 5 -/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; - * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - */ -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) -#define SPI_MEM_FDIN_QUAD_V 0x00000001U -#define SPI_MEM_FDIN_QUAD_S 6 -/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; - * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - */ -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) -#define SPI_MEM_FDOUT_QUAD_V 0x00000001U -#define SPI_MEM_FDOUT_QUAD_S 7 -/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; - * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_qio. - */ +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: For SPI1, the value of crc32..*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) +/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV +_ERR will be replied to BRESP/RRESP..*/ +#define SPI_MEM_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_CLOSE_AXI_INF_EN_M (BIT(31)) +#define SPI_MEM_CLOSE_AXI_INF_EN_V 0x1 +#define SPI_MEM_CLOSE_AXI_INF_EN_S 31 +/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: Set this bit to check AXI read/write the same address region..*/ +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30)) +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V 0x1 +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S 30 +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_qio..*/ #define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) -#define SPI_MEM_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 #define SPI_MEM_FADDR_QUAD_S 8 -/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; - * Set this bit to check AXI read/write the same address region. - */ -#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U -#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 -/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; - * Set this bit to close AXI read/write transfer to MSPI, which means that only - * SLV_ERR will be replied to BRESP/RRESP. - */ -#define SPI_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) -#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U -#define SPI_CLOSE_AXI_INF_EN_S 31 +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th +e same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_dio..*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the +same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/ +#define SPI_MEM_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_M (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_V 0x1 +#define SPI_MEM_AXI_REQ_EN_S 0 -/** SPI_MEM_CACHE_SCTRL_REG register - * SPI0 external RAM control register - */ -#define SPI_MEM_CACHE_SCTRL_REG (DR_REG_SPI_BASE + 0x40) -/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; - * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: - * enable, 0:disable. - */ -#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 -/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; - * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - */ -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) -#define SPI_MEM_USR_SRAM_DIO_V 0x00000001U -#define SPI_MEM_USR_SRAM_DIO_S 1 -/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; - * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - */ -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) -#define SPI_MEM_USR_SRAM_QIO_V 0x00000001U -#define SPI_MEM_USR_SRAM_QIO_S 2 -/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write - * operations. - */ -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 -/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - * operations. - */ -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 -/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; - * For SPI0, In the external RAM mode cache read external RAM for user define command. - */ -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 -/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. - * The register value shall be (bit_num-1). - */ -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 -/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; - * For SPI0, In the external RAM mode, it is the length in bits of address phase. The - * register value shall be (bit_num-1). - */ -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 -/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; - * For SPI0, In the external RAM mode cache write sram for user define command - */ -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 -/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; - * reserved - */ -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) -#define SPI_MEM_SRAM_OCT_V 0x00000001U -#define SPI_MEM_SRAM_OCT_S 21 -/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. - * The register value shall be (bit_num-1). - */ -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_SRAM_WDUMMY_CYCLELEN_S) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas +e. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 +/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T +he register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase +. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma +nd..*/ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + operations..*/ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ +e operations..*/ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 +/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 +/* SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en +able, 0:disable..*/ +#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 -/** SPI_MEM_SRAM_CMD_REG register - * SPI0 external RAM mode control register - */ -#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44) -/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - */ -#define SPI_MEM_SCLK_MODE 0x00000003U -#define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) -#define SPI_MEM_SCLK_MODE_V 0x00000003U -#define SPI_MEM_SCLK_MODE_S 0 -/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; - * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_fastrd_mode bit. - */ -#define SPI_MEM_SWB_MODE 0x000000FFU -#define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) -#define SPI_MEM_SWB_MODE_V 0x000000FFU -#define SPI_MEM_SWB_MODE_S 2 -/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; - * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_dio. - */ -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) -#define SPI_MEM_SDIN_DUAL_V 0x00000001U -#define SPI_MEM_SDIN_DUAL_S 10 -/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; - * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_dio. - */ -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) -#define SPI_MEM_SDOUT_DUAL_V 0x00000001U -#define SPI_MEM_SDOUT_DUAL_S 11 -/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; - * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_dio. - */ -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) -#define SPI_MEM_SADDR_DUAL_V 0x00000001U -#define SPI_MEM_SADDR_DUAL_S 12 -/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; - * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - */ -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) -#define SPI_MEM_SDIN_QUAD_V 0x00000001U -#define SPI_MEM_SDIN_QUAD_S 14 -/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; - * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_qio. - */ -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) -#define SPI_MEM_SDOUT_QUAD_V 0x00000001U -#define SPI_MEM_SDOUT_QUAD_S 15 -/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_qio. - */ -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) -#define SPI_MEM_SADDR_QUAD_V 0x00000001U -#define SPI_MEM_SADDR_QUAD_S 16 -/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; - * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - */ -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) -#define SPI_MEM_SCMD_QUAD_V 0x00000001U -#define SPI_MEM_SCMD_QUAD_S 17 -/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; - * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - */ -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) -#define SPI_MEM_SDIN_OCT_V 0x00000001U -#define SPI_MEM_SDIN_OCT_S 18 -/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; - * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - */ -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) -#define SPI_MEM_SDOUT_OCT_V 0x00000001U -#define SPI_MEM_SDOUT_OCT_S 19 -/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - */ -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) -#define SPI_MEM_SADDR_OCT_V 0x00000001U -#define SPI_MEM_SADDR_OCT_S 20 -/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; - * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - */ -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (SPI_MEM_SCMD_OCT_V << SPI_MEM_SCMD_OCT_S) -#define SPI_MEM_SCMD_OCT_V 0x00000001U -#define SPI_MEM_SCMD_OCT_S 21 -/** SPI_MEM_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; - * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - */ -#define SPI_MEM_SDUMMY_RIN (BIT(22)) -#define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) -#define SPI_MEM_SDUMMY_RIN_V 0x00000001U -#define SPI_MEM_SDUMMY_RIN_S 22 -/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; - * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - */ -#define SPI_MEM_SDUMMY_WOUT (BIT(23)) -#define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) -#define SPI_MEM_SDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_SDUMMY_WOUT_S 23 -/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_DQS is output by the MSPI controller. - */ -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_IO[7:0] is output by the MSPI controller. - */ -#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/** SPI_MEM_SDIN_HEX : HRO; bitpos: [26]; default: 0; - * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - */ -#define SPI_MEM_SDIN_HEX (BIT(26)) -#define SPI_MEM_SDIN_HEX_M (SPI_MEM_SDIN_HEX_V << SPI_MEM_SDIN_HEX_S) -#define SPI_MEM_SDIN_HEX_V 0x00000001U -#define SPI_MEM_SDIN_HEX_S 26 -/** SPI_MEM_SDOUT_HEX : HRO; bitpos: [27]; default: 0; - * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - */ +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) +/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0 +] are always 1. 0: Others..*/ +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar +e always 1. 0: Others..*/ +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_SDOUT_HEX : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/ #define SPI_MEM_SDOUT_HEX (BIT(27)) -#define SPI_MEM_SDOUT_HEX_M (SPI_MEM_SDOUT_HEX_V << SPI_MEM_SDOUT_HEX_S) -#define SPI_MEM_SDOUT_HEX_V 0x00000001U +#define SPI_MEM_SDOUT_HEX_M (BIT(27)) +#define SPI_MEM_SDOUT_HEX_V 0x1 #define SPI_MEM_SDOUT_HEX_S 27 -/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are - * always 1. 0: Others. - */ -#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] - * are always 1. 0: Others. - */ -#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_SDIN_HEX : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDIN_HEX (BIT(26)) +#define SPI_MEM_SDIN_HEX_M (BIT(26)) +#define SPI_MEM_SDIN_HEX_V 0x1 +#define SPI_MEM_SDIN_HEX_S 26 +/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25)) +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24)) +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/* SPI_MEM_SDUMMY_WOUT : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM, +the signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_M (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_V 0x1 +#define SPI_MEM_SDUMMY_WOUT_S 23 +/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t +he signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_M (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_V 0x1 +#define SPI_MEM_SDUMMY_RIN_S 22 +/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 +/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 +/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 +/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 +/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 +/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 +/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 +/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 +/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 +/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 +/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 +/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ +/*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd +_mode bit..*/ +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 +/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is always on..*/ +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 -/** SPI_MEM_SRAM_DRD_CMD_REG register - * SPI0 external RAM DDR read command control register - */ -#define SPI_MEM_SRAM_DRD_CMD_REG (DR_REG_SPI_BASE + 0x48) -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the read command value of command phase - * for sram. - */ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the length in bits of command phase for - * sram. The register value shall be (bit_num-1). - */ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for + sram. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the read command value of command phase + for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -/** SPI_MEM_SRAM_DWR_CMD_REG register - * SPI0 external RAM DDR write command control register - */ -#define SPI_MEM_SRAM_DWR_CMD_REG (DR_REG_SPI_BASE + 0x4c) -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the write command value of command phase - * for sram. - */ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the in bits of command phase for sram. - * The register value shall be (bit_num-1). - */ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram. + The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the write command value of command phas +e for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -/** SPI_MEM_SRAM_CLK_REG register - * SPI0 external RAM clock control register - */ -#define SPI_MEM_SRAM_CLK_REG (DR_REG_SPI_BASE + 0x50) -/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. - */ -#define SPI_MEM_SCLKCNT_L 0x000000FFU -#define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) -#define SPI_MEM_SCLKCNT_L_V 0x000000FFU -#define SPI_MEM_SCLKCNT_L_S 0 -/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). - */ -#define SPI_MEM_SCLKCNT_H 0x000000FFU -#define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) -#define SPI_MEM_SCLKCNT_H_V 0x000000FFU -#define SPI_MEM_SCLKCNT_H_S 8 -/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) - */ -#define SPI_MEM_SCLKCNT_N 0x000000FFU -#define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) -#define SPI_MEM_SCLKCNT_N_V 0x000000FFU -#define SPI_MEM_SCLKCNT_N_S 16 -/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk - * is divided from system clock. - */ +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) +/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c +lk is divided from system clock..*/ #define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 #define SPI_MEM_SCLK_EQU_SYSCLK_S 31 +/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c +lk frequency is system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 +/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 +/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 -/** SPI_MEM_FSM_REG register - * SPI0 FSM status register - */ -#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; - * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - */ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU -#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU -#define SPI_MEM_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [12]; default: 0; - * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. - */ -#define SPI_MEM_FLASH_LOCK_EN (BIT(12)) -#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) -#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U -#define SPI_MEM_FLASH_LOCK_EN_S 12 -/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [13]; default: 0; - * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. - */ +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) +/* SPI_MEM_SRAM_LOCK_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable..*/ #define SPI_MEM_SRAM_LOCK_EN (BIT(13)) -#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) -#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U +#define SPI_MEM_SRAM_LOCK_EN_M (BIT(13)) +#define SPI_MEM_SRAM_LOCK_EN_V 0x1 #define SPI_MEM_SRAM_LOCK_EN_S 13 +/* SPI_MEM_FLASH_LOCK_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable..*/ +#define SPI_MEM_FLASH_LOCK_EN (BIT(12)) +#define SPI_MEM_FLASH_LOCK_EN_M (BIT(12)) +#define SPI_MEM_FLASH_LOCK_EN_V 0x1 +#define SPI_MEM_FLASH_LOCK_EN_S 12 +/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ +/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001F +#define SPI_MEM_LOCK_DELAY_TIME_M ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S)) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x1F +#define SPI_MEM_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_INT_ENA_REG register - * SPI0 interrupt enable register - */ -#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0) -/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) -#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 -/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) -#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ENA_S 5 -/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) -#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: The command value to wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_CMD 0x0000FFFF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFFFF +#define SPI_MEM_WAITI_CMD_S 16 +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: The dummy cycle length when wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is + 8..*/ +#define SPI_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_M (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_V 0x1 +#define SPI_MEM_WAITI_CMD_2B_S 9 +/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI +_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when +SPI_MEM_WAITI_ADDR_EN is cleared..*/ +#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S)) +#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 +/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out ad +dress in RDSR or read SUS command transfer..*/ +#define SPI_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_M (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_V 0x1 +#define SPI_MEM_WAITI_ADDR_EN_S 2 +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The dummy phase enable when wait flash idle (RDSR).*/ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 +/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto +Suspend/Resume are not supported..*/ +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) +/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ +/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, + it will be treated as check pass..*/ +#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F +#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) +#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F +#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 +/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu +s of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PES_END_EN (BIT(24)) +#define SPI_MEM_PES_END_EN_M (BIT(24)) +#define SPI_MEM_PES_END_EN_V 0x1 +#define SPI_MEM_PES_END_EN_S 24 +/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status + of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PER_END_EN (BIT(23)) +#define SPI_MEM_PER_END_EN_M (BIT(23)) +#define SPI_MEM_PER_END_EN_V 0x1 +#define SPI_MEM_PER_END_EN_S 23 +/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte w +hen check flash SUS/SUS1/SUS2 status bit.*/ +#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_M (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_V 0x1 +#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ +/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is +status_in[15:0](only status_in[7:0] is valid when only one byte of data is read +out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS +2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/ +#define SPI_MEM_PESR_END_MSK 0x0000FFFF +#define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) +#define SPI_MEM_PESR_END_MSK_V 0xFFFF +#define SPI_MEM_PESR_END_MSK_S 6 +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable Auto-suspending function..*/ +#define SPI_MEM_FLASH_PES_EN (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 5 +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a +pplication should send PER after PES is done..*/ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase suspend command is sent. 0: SPI1 does not wait after program erase + suspend command is sent..*/ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase resume command is sent. 0: SPI1 does not wait after program erase +resume command is sent..*/ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program erase suspend bit, program erase suspend operation will be triggered whe +n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +isable..*/ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 +/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: program erase resume bit, program erase suspend operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: di +sable..*/ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) +/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS +/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash +..*/ +#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF +#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) +#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF +#define SPI_MEM_WAIT_PESR_COMMAND_S 16 +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */ +/*description: Program/Erase suspend command..*/ +#define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PES_COMMAND_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */ +/*description: Program/Erase resume command..*/ +#define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PER_COMMAND_S 16 +/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng +th of Program/Erase Suspend/Resume command is 8..*/ +#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1 +#define SPI_MEM_FLASH_PESR_CMD_2B_S 15 +/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/ +#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_V 0x1 +#define SPI_MEM_SPI0_LOCK_EN_S 7 +/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ +#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_128_S 6 +/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ +#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_128_S 5 +/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com +mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles +after DP command is sent..*/ +#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_128_S 4 +/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after RES command is sent..*/ +#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_128_S 3 +/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after HPM command is sent..*/ +#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_128_S 2 +/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/ +#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 +#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status of flash suspend, only used in SPI1..*/ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xAC) +/* SPI_MEM_WAITI_IDLE_DELAY_TIME_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable..*/ +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN (BIT(10)) +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_M (BIT(10)) +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V 0x1 +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S 10 +/* SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE..*/ +#define SPI_MEM_WAITI_IDLE_DELAY_TIME 0x000003FF +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_M ((SPI_MEM_WAITI_IDLE_DELAY_TIME_V)<<(SPI_MEM_WAITI_IDLE_DELAY_TIME_S)) +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_V 0x3FF +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) +/* SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/ #define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x1 #define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 +/* SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x1 +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 +/* SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x1 +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 +/* SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x1 +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 +/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ENA_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_V 0x1 +#define SPI_MEM_WPE_END_INT_ENA_S 2 +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 -/** SPI_MEM_INT_CLR_REG register - * SPI0 interrupt clear register - */ -#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4) -/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) -#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 -/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) -#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_CLR_S 5 -/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) -#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) +/* SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/ #define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x1 #define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 +/* SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/ +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x1 +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 +/* SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x1 +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 +/* SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x1 +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 +/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_CLR_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_V 0x1 +#define SPI_MEM_WPE_END_INT_CLR_S 2 +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 -/** SPI_MEM_INT_RAW_REG register - * SPI0 interrupt raw register - */ -#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8) -/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: - * Others - */ -#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) -#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 -/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. - */ -#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) -#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. - */ -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_RAW_S 5 -/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. - */ -#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) -#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read - * address is invalid by compared to MMU configuration. 0: Others. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - * address is invalid by compared to MMU configuration. 0: Others. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS1 is overflow. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS is overflow. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. - */ +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) +/* SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO + is underflow..*/ #define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x1 #define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 +/* SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO + is underflow..*/ +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x1 +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 +/* SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF +O connected to SPI_DQS is overflow..*/ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x1 +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 +/* SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF +O connected to SPI_DQS1 is overflow..*/ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x1 +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 +/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that +chip is loosing power and RTC module sends out brown out close flash request to +SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + and MSPI returns to idle state. 0: Others..*/ +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_RAW_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr +ite flash request is received. 0: Others..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read +address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access +is rejected. 0: Others..*/ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s +et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error + times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM +. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t +his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq +ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP +I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times +of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E +RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare +d, this bit will not be triggered..*/ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st +is changed from non idle state to idle state. 0: Others..*/ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st +is changed from non idle state to idle state. It means that SPI_CS raises high. +0: Others.*/ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C +E is sent and flash is already idle. 0: Others..*/ +#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_V 0x1 +#define SPI_MEM_WPE_END_INT_RAW_S 2 +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com +mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com +mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 -/** SPI_MEM_INT_ST_REG register - * SPI0 interrupt status register - */ -#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc) -/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) -#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ST_S 3 -/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) -#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ST_S 4 -/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ST_S 5 -/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) -#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ST_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) +/* SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/ #define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x1 #define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 +/* SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x1 +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 +/* SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x1 +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 +/* SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x1 +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 +/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ST_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_V 0x1 +#define SPI_MEM_WPE_END_INT_ST_S 2 +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 -/** SPI_MEM_DDR_REG register - * SPI0 flash DDR mode control register - */ -#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4) -/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ -#define SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) -#define SPI_FMEM_DDR_EN_V 0x00000001U -#define SPI_FMEM_DDR_EN_S 0 -/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ -#define SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) -#define SPI_FMEM_VAR_DUMMY_V 0x00000001U -#define SPI_FMEM_VAR_DUMMY_S 1 -/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ -#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) -#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ -#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) -#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ -#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) -#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_FMEM_DDR_CMD_DIS_S 4 -/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the panda device. - */ -#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) -#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_S 5 -/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to flash. - */ -#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) -#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_TX_DDR_MSK_EN_S 12 -/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to flash. - */ -#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) -#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_RX_DDR_MSK_EN_S 13 -/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ -#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) -#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ -#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) -#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ -#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) -#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_EN_S 24 -/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ -#define SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) -#define SPI_FMEM_DQS_CA_IN_V 0x00000001U -#define SPI_FMEM_DQS_CA_IN_S 26 -/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ -#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to flash. . - */ -#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) -#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_INV_S 28 -/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ -#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) -#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ -#define SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) -#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_FMEM_HYPERBUS_CA_S 30 +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) +/* SPI_MEM_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ +#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_FMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} +..*/ +#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ +#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_FMEM_DQS_CA_IN_S 26 +/* SPI_MEM_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to flash..*/ +#define SPI_MEM_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to flash..*/ +#define SPI_MEM_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the panda device..*/ +#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_FMEM_OUTMINBYTELEN_M ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_FMEM_VAR_DUMMY_S 1 +/* SPI_MEM_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_FMEM_DDR_EN_S 0 -/** SPI_SMEM_DDR_REG register - * SPI0 external RAM DDR mode control register - */ -#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8) -/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ -#define SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) -#define SPI_SMEM_DDR_EN_V 0x00000001U -#define SPI_SMEM_DDR_EN_S 0 -/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ -#define SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) -#define SPI_SMEM_VAR_DUMMY_V 0x00000001U -#define SPI_SMEM_VAR_DUMMY_S 1 -/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ -#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) -#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_RDAT_SWP_S 2 -/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ -#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) -#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_WDAT_SWP_S 3 -/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ -#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) -#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_SMEM_DDR_CMD_DIS_S 4 -/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the DDR psram. - */ -#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) -#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_S 5 -/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to external RAM. - */ -#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) -#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_TX_DDR_MSK_EN_S 12 -/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to external RAM. - */ -#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) -#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_RX_DDR_MSK_EN_S 13 -/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ -#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) -#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_S 14 -/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ -#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) -#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_SMEM_DDR_DQS_LOOP_S 21 -/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ -#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) -#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_EN_S 24 -/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ -#define SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) -#define SPI_SMEM_DQS_CA_IN_V 0x00000001U -#define SPI_SMEM_DQS_CA_IN_S 26 -/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ -#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to external RAM. . - */ -#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) -#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_INV_S 28 -/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], - * 1'b0}. - */ -#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) -#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_SMEM_OCTA_RAM_ADDR_S 29 -/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ -#define SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) -#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_SMEM_HYPERBUS_CA_S 30 +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD8) +/* SPI_MEM_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 +]}..*/ +#define SPI_MEM_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] +, 1'b0}..*/ +#define SPI_MEM_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ +#define SPI_MEM_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to external RAM..*/ +#define SPI_MEM_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to external RAM..*/ +#define SPI_MEM_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the DDR psram..*/ +#define SPI_MEM_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SMEM_DDR_EN_S 0 -/** SPI_FMEM_PMS0_ATTR_REG register - * MSPI flash PMS section 0 attribute register - */ -#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100) -/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) -#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_RD_ATTR_S 0 -/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) -#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_WR_ATTR_S 1 -/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and - * SPI_FMEM_PMS0_SIZE_REG. - */ -#define SPI_FMEM_PMS0_ECC (BIT(2)) -#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) -#define SPI_FMEM_PMS0_ECC_V 0x00000001U -#define SPI_FMEM_PMS0_ECC_S 2 +#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS0_ECC_S 2 +/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS0_RD_ATTR_S 0 -/** SPI_FMEM_PMS1_ATTR_REG register - * MSPI flash PMS section 1 attribute register - */ -#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104) -/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) -#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_RD_ATTR_S 0 -/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) -#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_WR_ATTR_S 1 -/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and - * SPI_FMEM_PMS1_SIZE_REG. - */ -#define SPI_FMEM_PMS1_ECC (BIT(2)) -#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) -#define SPI_FMEM_PMS1_ECC_V 0x00000001U -#define SPI_FMEM_PMS1_ECC_S 2 +#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS1_ECC_S 2 +/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS1_RD_ATTR_S 0 -/** SPI_FMEM_PMS2_ATTR_REG register - * MSPI flash PMS section 2 attribute register - */ -#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108) -/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) -#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_RD_ATTR_S 0 -/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) -#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_WR_ATTR_S 1 -/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and - * SPI_FMEM_PMS2_SIZE_REG. - */ -#define SPI_FMEM_PMS2_ECC (BIT(2)) -#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) -#define SPI_FMEM_PMS2_ECC_V 0x00000001U -#define SPI_FMEM_PMS2_ECC_S 2 +#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS2_ECC_S 2 +/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS2_RD_ATTR_S 0 -/** SPI_FMEM_PMS3_ATTR_REG register - * MSPI flash PMS section 3 attribute register - */ -#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c) -/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) -#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_RD_ATTR_S 0 -/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) -#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_WR_ATTR_S 1 -/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and - * SPI_FMEM_PMS3_SIZE_REG. - */ -#define SPI_FMEM_PMS3_ECC (BIT(2)) -#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) -#define SPI_FMEM_PMS3_ECC_V 0x00000001U -#define SPI_FMEM_PMS3_ECC_S 2 +#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) +/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS3_ECC_S 2 +/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS3_RD_ATTR_S 0 -/** SPI_FMEM_PMS0_ADDR_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110) -/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 0 start address value - */ -#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) -#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_S 0 +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) +/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h0 ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_FMEM_PMS0_ADDR_S 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS0_ADDR_S_M ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS0_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS0_ADDR_S_S 0 -/** SPI_FMEM_PMS1_ADDR_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114) -/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 1 start address value - */ -#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) -#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_S 0 +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) +/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h0ffffff ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_FMEM_PMS1_ADDR_S 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS1_ADDR_S_M ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS1_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS1_ADDR_S_S 0 -/** SPI_FMEM_PMS2_ADDR_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118) -/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 2 start address value - */ -#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) -#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_S 0 +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) +/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h1ffffff ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_FMEM_PMS2_ADDR_S 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS2_ADDR_S_M ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS2_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS2_ADDR_S_S 0 -/** SPI_FMEM_PMS3_ADDR_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c) -/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 3 start address value - */ -#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) -#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_S 0 +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) +/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h2ffffff ; */ +/*description: SPI1 flash PMS section $n start address value.*/ +#define SPI_MEM_FMEM_PMS3_ADDR_S 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS3_ADDR_S_M ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS3_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_FMEM_PMS3_ADDR_S_S 0 -/** SPI_FMEM_PMS0_SIZE_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120) -/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, - * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) - */ -#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) -#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS0_SIZE_S 0 +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS0_SIZE 0x0001FFFF +#define SPI_MEM_FMEM_PMS0_SIZE_M ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S)) +#define SPI_MEM_FMEM_PMS0_SIZE_V 0x1FFFF +#define SPI_MEM_FMEM_PMS0_SIZE_S 0 -/** SPI_FMEM_PMS1_SIZE_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124) -/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, - * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) - */ -#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) -#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS1_SIZE_S 0 +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) +/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS1_SIZE 0x0001FFFF +#define SPI_MEM_FMEM_PMS1_SIZE_M ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S)) +#define SPI_MEM_FMEM_PMS1_SIZE_V 0x1FFFF +#define SPI_MEM_FMEM_PMS1_SIZE_S 0 -/** SPI_FMEM_PMS2_SIZE_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128) -/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, - * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) - */ -#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) -#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS2_SIZE_S 0 +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) +/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS2_SIZE 0x0001FFFF +#define SPI_MEM_FMEM_PMS2_SIZE_M ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S)) +#define SPI_MEM_FMEM_PMS2_SIZE_V 0x1FFFF +#define SPI_MEM_FMEM_PMS2_SIZE_S 0 -/** SPI_FMEM_PMS3_SIZE_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c) -/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, - * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) - */ -#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) -#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS3_SIZE_S 0 +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12C) +/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS3_SIZE 0x0001FFFF +#define SPI_MEM_FMEM_PMS3_SIZE_M ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S)) +#define SPI_MEM_FMEM_PMS3_SIZE_V 0x1FFFF +#define SPI_MEM_FMEM_PMS3_SIZE_S 0 -/** SPI_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130) -/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) -#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_RD_ATTR_S 0 -/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) -#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_WR_ATTR_S 1 -/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and - * SPI_SMEM_PMS0_SIZE_REG. - */ -#define SPI_SMEM_PMS0_ECC (BIT(2)) -#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) -#define SPI_SMEM_PMS0_ECC_V 0x00000001U -#define SPI_SMEM_PMS0_ECC_S 2 +#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) +/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS0_ECC_S 2 +/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS0_RD_ATTR_S 0 -/** SPI_SMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134) -/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) -#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_RD_ATTR_S 0 -/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) -#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_WR_ATTR_S 1 -/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and - * SPI_SMEM_PMS1_SIZE_REG. - */ -#define SPI_SMEM_PMS1_ECC (BIT(2)) -#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) -#define SPI_SMEM_PMS1_ECC_V 0x00000001U -#define SPI_SMEM_PMS1_ECC_S 2 +#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) +/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS1_ECC_S 2 +/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS1_RD_ATTR_S 0 -/** SPI_SMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138) -/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) -#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_RD_ATTR_S 0 -/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) -#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_WR_ATTR_S 1 -/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and - * SPI_SMEM_PMS2_SIZE_REG. - */ -#define SPI_SMEM_PMS2_ECC (BIT(2)) -#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) -#define SPI_SMEM_PMS2_ECC_V 0x00000001U -#define SPI_SMEM_PMS2_ECC_S 2 +#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) +/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS2_ECC_S 2 +/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS2_RD_ATTR_S 0 -/** SPI_SMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c) -/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) -#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_RD_ATTR_S 0 -/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) -#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_WR_ATTR_S 1 -/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and - * SPI_SMEM_PMS3_SIZE_REG. - */ -#define SPI_SMEM_PMS3_ECC (BIT(2)) -#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) -#define SPI_SMEM_PMS3_ECC_V 0x00000001U -#define SPI_SMEM_PMS3_ECC_S 2 +#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13C) +/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS3_ECC_S 2 +/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS3_RD_ATTR_S 0 -/** SPI_SMEM_PMS0_ADDR_REG register - * SPI1 external RAM PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140) -/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 0 start address value - */ -#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) -#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_S 0 +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) +/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h0 ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SMEM_PMS0_ADDR_S 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS0_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS0_ADDR_S_S 0 -/** SPI_SMEM_PMS1_ADDR_REG register - * SPI1 external RAM PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144) -/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 1 start address value - */ -#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) -#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_S 0 +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) +/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h0ffffff ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SMEM_PMS1_ADDR_S 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS1_ADDR_S_M ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS1_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS1_ADDR_S_S 0 -/** SPI_SMEM_PMS2_ADDR_REG register - * SPI1 external RAM PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148) -/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 2 start address value - */ -#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) -#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_S 0 +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) +/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h1ffffff ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SMEM_PMS2_ADDR_S 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS2_ADDR_S_M ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS2_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS2_ADDR_S_S 0 -/** SPI_SMEM_PMS3_ADDR_REG register - * SPI1 external RAM PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c) -/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 3 start address value - */ -#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) -#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_S 0 +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14C) +/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[28:0] ;default: 29'h2ffffff ; */ +/*description: SPI1 external RAM PMS section $n start address value.*/ +#define SPI_MEM_SMEM_PMS3_ADDR_S 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS3_ADDR_S_V 0x1FFFFFFF +#define SPI_MEM_SMEM_PMS3_ADDR_S_S 0 -/** SPI_SMEM_PMS0_SIZE_REG register - * SPI1 external RAM PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150) -/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, - * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) - */ -#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) -#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS0_SIZE_S 0 +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) +/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS0_SIZE 0x0001FFFF +#define SPI_MEM_SMEM_PMS0_SIZE_M ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S)) +#define SPI_MEM_SMEM_PMS0_SIZE_V 0x1FFFF +#define SPI_MEM_SMEM_PMS0_SIZE_S 0 -/** SPI_SMEM_PMS1_SIZE_REG register - * SPI1 external RAM PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154) -/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, - * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) - */ -#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) -#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS1_SIZE_S 0 +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) +/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS1_SIZE 0x0001FFFF +#define SPI_MEM_SMEM_PMS1_SIZE_M ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S)) +#define SPI_MEM_SMEM_PMS1_SIZE_V 0x1FFFF +#define SPI_MEM_SMEM_PMS1_SIZE_S 0 -/** SPI_SMEM_PMS2_SIZE_REG register - * SPI1 external RAM PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158) -/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, - * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) - */ -#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) -#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS2_SIZE_S 0 +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) +/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS2_SIZE 0x0001FFFF +#define SPI_MEM_SMEM_PMS2_SIZE_M ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S)) +#define SPI_MEM_SMEM_PMS2_SIZE_V 0x1FFFF +#define SPI_MEM_SMEM_PMS2_SIZE_S 0 -/** SPI_SMEM_PMS3_SIZE_REG register - * SPI1 external RAM PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c) -/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, - * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) - */ -#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) -#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS3_SIZE_S 0 +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15C) +/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[16:0] ;default: 17'h1000 ; */ +/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS3_SIZE 0x0001FFFF +#define SPI_MEM_SMEM_PMS3_SIZE_M ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S)) +#define SPI_MEM_SMEM_PMS3_SIZE_V 0x1FFFF +#define SPI_MEM_SMEM_PMS3_SIZE_S 0 -/** SPI_MEM_PMS_REJECT_REG register - * SPI1 access reject register - */ -#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x160) -/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI0/1 transfer permission control function. - */ -#define SPI_MEM_PM_EN (BIT(27)) -#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) -#define SPI_MEM_PM_EN_V 0x00000001U -#define SPI_MEM_PM_EN_S 27 -/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; - * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_LD (BIT(28)) -#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) -#define SPI_MEM_PMS_LD_V 0x00000001U -#define SPI_MEM_PMS_LD_S 28 -/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; - * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_ST (BIT(29)) -#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) -#define SPI_MEM_PMS_ST_V 0x00000001U -#define SPI_MEM_PMS_ST_S 29 -/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; - * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) -#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) -#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U -#define SPI_MEM_PMS_MULTI_HIT_S 30 -/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; - * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ +#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x160) +/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ #define SPI_MEM_PMS_IVD (BIT(31)) -#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) -#define SPI_MEM_PMS_IVD_V 0x00000001U +#define SPI_MEM_PMS_IVD_M (BIT(31)) +#define SPI_MEM_PMS_IVD_V 0x1 #define SPI_MEM_PMS_IVD_S 31 +/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It + is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_V 0x1 +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (BIT(29)) +#define SPI_MEM_PMS_ST_V 0x1 +#define SPI_MEM_PMS_ST_S 29 +/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI +_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (BIT(28)) +#define SPI_MEM_PMS_LD_V 0x1 +#define SPI_MEM_PMS_LD_S 28 +/* SPI_MEM_PM_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0/1 transfer permission control function..*/ +#define SPI_MEM_PM_EN (BIT(27)) +#define SPI_MEM_PM_EN_M (BIT(27)) +#define SPI_MEM_PM_EN_V 0x1 +#define SPI_MEM_PM_EN_S 27 -/** SPI_MEM_PMS_REJECT_ADDR_REG register - * SPI1 access reject addr register - */ -#define SPI_MEM_PMS_REJECT_ADDR_REG (DR_REG_SPI_BASE + 0x164) -/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU -#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) -#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[28:0] ;default: 29'h0 ; */ +/*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_REJECT_ADDR 0x1FFFFFFF +#define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S)) +#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFF #define SPI_MEM_REJECT_ADDR_S 0 -/** SPI_MEM_ECC_CTRL_REG register - * MSPI ECC control register - */ -#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168) -/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; - * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ -#define SPI_MEM_ECC_ERR_CNT 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) -#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) -#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - */ -#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) -#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_FMEM_ECC_ERR_INT_EN_S 17 -/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; - * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: - * 1024 bytes. 3: 2048 bytes. - */ -#define SPI_FMEM_PAGE_SIZE 0x00000003U -#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) -#define SPI_FMEM_PAGE_SIZE_V 0x00000003U -#define SPI_FMEM_PAGE_SIZE_S 18 -/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit - * should be 0. Otherwise, this bit should be 1. - */ -#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) -#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) -#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_FMEM_ECC_ADDR_EN_S 21 -/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; - * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - */ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) -#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) -#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U -#define SPI_MEM_USR_ECC_ADDR_EN_S 22 -/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - */ -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; - * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to - * byte 0 bit 0 to byte 15 bit 7) - */ -#define SPI_MEM_ECC_ERR_BITS 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) -#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) +/* SPI_MEM_ECC_ERR_BITS : R/SS/WTC ;bitpos:[31:25] ;default: 7'd0 ; */ +/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding + to byte 0 bit 0 to byte 15 bit 7).*/ +#define SPI_MEM_ECC_ERR_BITS 0x0000007F +#define SPI_MEM_ECC_ERR_BITS_M ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S)) +#define SPI_MEM_ECC_ERR_BITS_V 0x7F #define SPI_MEM_ECC_ERR_BITS_S 25 +/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd +ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD +R record the first ECC error information..*/ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1 +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/* SPI_MEM_USR_ECC_ADDR_EN : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(22)) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_USR_ECC_ADDR_EN_S 22 +/* SPI_MEM_FMEM_ECC_ADDR_EN : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of flash. If there is no ECC region in flash, th +is bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_FMEM_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_FMEM_ECC_ADDR_EN_M (BIT(21)) +#define SPI_MEM_FMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_FMEM_ECC_ADDR_EN_S 21 +/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: +1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_FMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_FMEM_PAGE_SIZE_M ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S)) +#define SPI_MEM_FMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_FMEM_PAGE_SIZE_S 18 +/* SPI_MEM_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas +h..*/ +#define SPI_MEM_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S 17 +/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : R/W ;bitpos:[16:11] ;default: 6'd10 ; */ +/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr +upt..*/ +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM 0x0000003F +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S)) +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V 0x3F +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S 11 +/* SPI_MEM_ECC_ERR_CNT : R/SS/WTC ;bitpos:[10:5] ;default: 6'd0 ; */ +/*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_CNT 0x0000003F +#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) +#define SPI_MEM_ECC_ERR_CNT_V 0x3F +#define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_MEM_ECC_ERR_ADDR_REG register - * MSPI ECC error address register - */ -#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c) -/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ -#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) -#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16C) +/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[28:0] ;default: 29'h0 ; */ +/*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFF +#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) +#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFF #define SPI_MEM_ECC_ERR_ADDR_S 0 -/** SPI_MEM_AXI_ERR_ADDR_REG register - * SPI0 AXI request error address. - */ -#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170) -/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - */ -#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) -#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) +/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[28:0] ;default: 29'h0 ; */ +/*description: This bits show the first AXI write/read invalid error or AXI write flash error a +ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS +H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ +#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFF +#define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) +#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFF #define SPI_MEM_AXI_ERR_ADDR_S 0 -/** SPI_SMEM_ECC_CTRL_REG register - * MSPI ECC control register - */ -#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174) -/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to - * external RAM. - */ -#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) -#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; - * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. - * 2: 1024 bytes. 3: 2048 bytes. - */ -#define SPI_SMEM_PAGE_SIZE 0x00000003U -#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) -#define SPI_SMEM_PAGE_SIZE_V 0x00000003U -#define SPI_SMEM_PAGE_SIZE_S 18 -/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of external RAM. If there is no ECC region in external - * RAM, this bit should be 0. Otherwise, this bit should be 1. - */ -#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) -#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_SMEM_ECC_ADDR_EN_S 20 +#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) +/* SPI_MEM_SMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of external RAM. If there is no ECC region in ex +ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_SMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_SMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_SMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd2 ; */ +/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt +es. 2: 1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_SMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_SMEM_PAGE_SIZE_M ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S)) +#define SPI_MEM_SMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_SMEM_PAGE_SIZE_S 18 +/* SPI_MEM_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte +rnal RAM..*/ +#define SPI_MEM_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_AXI_ADDR_CTRL_REG register - * SPI0 AXI address control register - */ -#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178) -/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; - * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - * and SPI0 transfers are done. 0: Others. - */ +#define SPI_MEM_SPI_SMEM_AXI_ADDR_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x178) +/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO +and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31)) +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1 +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 +/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_WBLEN_AFIFO_REMPTY_M (BIT(30)) +#define SPI_MEM_WBLEN_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_WBLEN_AFIFO_REMPTY_S 30 +/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */ +/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_WDATA_AFIFO_REMPTY_M (BIT(29)) +#define SPI_MEM_WDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_WDATA_AFIFO_REMPTY_S 29 +/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */ +/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_RADDR_AFIFO_REMPTY_M (BIT(28)) +#define SPI_MEM_RADDR_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_RADDR_AFIFO_REMPTY_S 28 +/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_RDATA_AFIFO_REMPTY_M (BIT(27)) +#define SPI_MEM_RDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_RDATA_AFIFO_REMPTY_S 27 +/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + and SPI0 transfers are done. 0: Others..*/ #define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) -#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) -#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 #define SPI_MEM_ALL_FIFO_EMPTY_S 26 -/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; - * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ -#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) -#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) -#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_RDATA_AFIFO_REMPTY_S 27 -/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; - * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ -#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) -#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) -#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U -#define SPI_RADDR_AFIFO_REMPTY_S 28 -/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; - * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ -#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) -#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) -#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_WDATA_AFIFO_REMPTY_S 29 -/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; - * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ -#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) -#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) -#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U -#define SPI_WBLEN_AFIFO_REMPTY_S 30 -/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; - * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and - * RDATA_AFIFO are empty and spi0_mst_st is IDLE. - */ -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 -/** SPI_MEM_AXI_ERR_RESP_EN_REG register - * SPI0 AXI error response enable register - */ -#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c) -/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) -#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) -#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 -/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 -/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; - * Set this bit to enable AXI response function for axi flash err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 -/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 -/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; - * Set this bit to enable AXI response function for mmu sens in err axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 -/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; - * Set this bit to enable AXI response function for axi wstrb err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 -/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 -/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) -#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) -#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 -/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 -/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; - * Set this bit to enable AXI response function for mmu sensitive err in axi read - * trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 -/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi read trans. - */ +#define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x17C) +/* SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for axi size err in axi read trans +..*/ #define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (BIT(11)) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x1 #define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 +/* SPI_MEM_AR_RESP_EN_MMU_SENS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu sensitive err in axi read +trans..*/ +#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (BIT(10)) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x1 +#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 +/* SPI_MEM_AR_RESP_EN_MMU_ECC : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu ecc err in axi read trans..*/ +#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (BIT(9)) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x1 +#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 +/* SPI_MEM_AR_RESP_EN_MMU_GID : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu gid err in axi read trans..*/ +#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_AR_RESP_EN_MMU_GID_M (BIT(8)) +#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x1 +#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 +/* SPI_MEM_AR_RESP_EN_MMU_VLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu valid err in axi read tran +s..*/ +#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (BIT(7)) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x1 +#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 +/* SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for axi wstrb err in axi write tra +ns..*/ +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (BIT(6)) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x1 +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 +/* SPI_MEM_AW_RESP_EN_MMU_SENS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu sens in err axi write tran +s..*/ +#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (BIT(5)) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x1 +#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 +/* SPI_MEM_AW_RESP_EN_MMU_ECC : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu ecc err in axi write trans +..*/ +#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (BIT(4)) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x1 +#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 +/* SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for axi flash err in axi write tra +ns..*/ +#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (BIT(3)) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x1 +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 +/* SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for axi size err in axi write tran +s..*/ +#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (BIT(2)) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x1 +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 +/* SPI_MEM_AW_RESP_EN_MMU_GID : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu gid err in axi write trans +..*/ +#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_AW_RESP_EN_MMU_GID_M (BIT(1)) +#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x1 +#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 +/* SPI_MEM_AW_RESP_EN_MMU_VLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI response function for mmu valid err in axi write tra +ns..*/ +#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (BIT(0)) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x1 +#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_TIMING_CALI_REG register - * SPI0 flash timing calibration register - */ -#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180) -/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable timing adjust clock for all reading operations. - */ -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) -#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_MEM_TIMING_CLK_ENA_S 0 -/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; - * The bit is used to enable timing auto-calibration for all reading operations. - */ -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) -#define SPI_MEM_TIMING_CALI_V 0x00000001U -#define SPI_MEM_TIMING_CALI_S 1 -/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; - * add extra dummy spi clock cycle length for spi clock calibration. - */ -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * flash. - */ -#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) -#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_MEM_DLL_TIMING_CALI_S 5 -/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; - * Set this bit to update delay mode, delay num and extra dummy in MSPI. - */ +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/ #define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) -#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) -#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x1 #define SPI_MEM_TIMING_CALI_UPDATE_S 6 +/* SPI_MEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f +lash..*/ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable timing auto-calibration for all reading operations..*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable timing adjust clock for all reading operations..*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 -/** SPI_MEM_DIN_MODE_REG register - * MSPI flash input timing delay mode control register - */ -#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184) -/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN0_MODE 0x00000007U -#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) -#define SPI_MEM_DIN0_MODE_V 0x00000007U -#define SPI_MEM_DIN0_MODE_S 0 -/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN1_MODE 0x00000007U -#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) -#define SPI_MEM_DIN1_MODE_V 0x00000007U -#define SPI_MEM_DIN1_MODE_S 3 -/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN2_MODE 0x00000007U -#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) -#define SPI_MEM_DIN2_MODE_V 0x00000007U -#define SPI_MEM_DIN2_MODE_S 6 -/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN3_MODE 0x00000007U -#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) -#define SPI_MEM_DIN3_MODE_V 0x00000007U -#define SPI_MEM_DIN3_MODE_S 9 -/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN4_MODE 0x00000007U -#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) -#define SPI_MEM_DIN4_MODE_V 0x00000007U -#define SPI_MEM_DIN4_MODE_S 12 -/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN5_MODE 0x00000007U -#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) -#define SPI_MEM_DIN5_MODE_V 0x00000007U -#define SPI_MEM_DIN5_MODE_S 15 -/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN6_MODE 0x00000007U -#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) -#define SPI_MEM_DIN6_MODE_V 0x00000007U -#define SPI_MEM_DIN6_MODE_S 18 -/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN7_MODE 0x00000007U -#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) -#define SPI_MEM_DIN7_MODE_V 0x00000007U -#define SPI_MEM_DIN7_MODE_S 21 -/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DINS_MODE 0x00000007U -#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) -#define SPI_MEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 #define SPI_MEM_DINS_MODE_S 24 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 -/** SPI_MEM_DIN_NUM_REG register - * MSPI flash input timing delay number control register - */ -#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188) -/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN0_NUM 0x00000003U -#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) -#define SPI_MEM_DIN0_NUM_V 0x00000003U -#define SPI_MEM_DIN0_NUM_S 0 -/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN1_NUM 0x00000003U -#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) -#define SPI_MEM_DIN1_NUM_V 0x00000003U -#define SPI_MEM_DIN1_NUM_S 2 -/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN2_NUM 0x00000003U -#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) -#define SPI_MEM_DIN2_NUM_V 0x00000003U -#define SPI_MEM_DIN2_NUM_S 4 -/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN3_NUM 0x00000003U -#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) -#define SPI_MEM_DIN3_NUM_V 0x00000003U -#define SPI_MEM_DIN3_NUM_S 6 -/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN4_NUM 0x00000003U -#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) -#define SPI_MEM_DIN4_NUM_V 0x00000003U -#define SPI_MEM_DIN4_NUM_S 8 -/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN5_NUM 0x00000003U -#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) -#define SPI_MEM_DIN5_NUM_V 0x00000003U -#define SPI_MEM_DIN5_NUM_S 10 -/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN6_NUM 0x00000003U -#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) -#define SPI_MEM_DIN6_NUM_V 0x00000003U -#define SPI_MEM_DIN6_NUM_S 12 -/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN7_NUM 0x00000003U -#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) -#define SPI_MEM_DIN7_NUM_V 0x00000003U -#define SPI_MEM_DIN7_NUM_S 14 -/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DINS_NUM 0x00000003U -#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) -#define SPI_MEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 #define SPI_MEM_DINS_NUM_S 16 +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 -/** SPI_MEM_DOUT_MODE_REG register - * MSPI flash output timing adjustment control register - */ -#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c) -/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) -#define SPI_MEM_DOUT0_MODE_V 0x00000001U -#define SPI_MEM_DOUT0_MODE_S 0 -/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) -#define SPI_MEM_DOUT1_MODE_V 0x00000001U -#define SPI_MEM_DOUT1_MODE_S 1 -/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) -#define SPI_MEM_DOUT2_MODE_V 0x00000001U -#define SPI_MEM_DOUT2_MODE_S 2 -/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) -#define SPI_MEM_DOUT3_MODE_V 0x00000001U -#define SPI_MEM_DOUT3_MODE_S 3 -/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) -#define SPI_MEM_DOUT4_MODE_V 0x00000001U -#define SPI_MEM_DOUT4_MODE_S 4 -/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) -#define SPI_MEM_DOUT5_MODE_V 0x00000001U -#define SPI_MEM_DOUT5_MODE_S 5 -/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) -#define SPI_MEM_DOUT6_MODE_V 0x00000001U -#define SPI_MEM_DOUT6_MODE_S 6 -/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) -#define SPI_MEM_DOUT7_MODE_V 0x00000001U -#define SPI_MEM_DOUT7_MODE_S 7 -/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C) +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ #define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) -#define SPI_MEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 #define SPI_MEM_DOUTS_MODE_S 8 +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 -/** SPI_SMEM_TIMING_CALI_REG register - * MSPI external RAM timing calibration register - */ -#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190) -/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; - * For sram, the bit is used to enable timing adjust clock for all reading operations. - */ -#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) -#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; - * For sram, the bit is used to enable timing auto-calibration for all reading - * operations. - */ -#define SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) -#define SPI_SMEM_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_TIMING_CALI_S 1 -/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; - * For sram, add extra dummy spi clock cycle length for spi clock calibration. - */ -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * EXT_RAM. - */ -#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) -#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_DLL_TIMING_CALI_S 5 -/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS0_270_SEL 0x00000003U -#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) -#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U -#define SPI_SMEM_DQS0_270_SEL_S 7 -/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS0_90_SEL 0x00000003U -#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) -#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U -#define SPI_SMEM_DQS0_90_SEL_S 9 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) +/* SPI_MEM_SMEM_DQS0_90_SEL : R/W ;bitpos:[10:9] ;default: 2'd1 ; */ +/*description: Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0 +ns, 2'd2: 1.5ns 2'd3: 2.0ns..*/ +#define SPI_MEM_SMEM_DQS0_90_SEL 0x00000003 +#define SPI_MEM_SMEM_DQS0_90_SEL_M ((SPI_MEM_SMEM_DQS0_90_SEL_V)<<(SPI_MEM_SMEM_DQS0_90_SEL_S)) +#define SPI_MEM_SMEM_DQS0_90_SEL_V 0x3 +#define SPI_MEM_SMEM_DQS0_90_SEL_S 9 +/* SPI_MEM_SMEM_DQS0_270_SEL : R/W ;bitpos:[8:7] ;default: 2'd1 ; */ +/*description: Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust +. 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns..*/ +#define SPI_MEM_SMEM_DQS0_270_SEL 0x00000003 +#define SPI_MEM_SMEM_DQS0_270_SEL_M ((SPI_MEM_SMEM_DQS0_270_SEL_V)<<(SPI_MEM_SMEM_DQS0_270_SEL_S)) +#define SPI_MEM_SMEM_DQS0_270_SEL_V 0x3 +#define SPI_MEM_SMEM_DQS0_270_SEL_S 7 +/* SPI_MEM_SMEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E +XT_RAM..*/ +#define SPI_MEM_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_SMEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_SMEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_SMEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper +ations..*/ +#define SPI_MEM_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SMEM_TIMING_CALI_S 1 +/* SPI_MEM_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio +ns..*/ +#define SPI_MEM_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_DIN_MODE_REG register - * MSPI external RAM input timing delay mode control register - */ -#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194) -/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN0_MODE 0x00000007U -#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) -#define SPI_SMEM_DIN0_MODE_V 0x00000007U -#define SPI_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN1_MODE 0x00000007U -#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) -#define SPI_SMEM_DIN1_MODE_V 0x00000007U -#define SPI_SMEM_DIN1_MODE_S 3 -/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN2_MODE 0x00000007U -#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) -#define SPI_SMEM_DIN2_MODE_V 0x00000007U -#define SPI_SMEM_DIN2_MODE_S 6 -/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN3_MODE 0x00000007U -#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) -#define SPI_SMEM_DIN3_MODE_V 0x00000007U -#define SPI_SMEM_DIN3_MODE_S 9 -/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN4_MODE 0x00000007U -#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) -#define SPI_SMEM_DIN4_MODE_V 0x00000007U -#define SPI_SMEM_DIN4_MODE_S 12 -/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN5_MODE 0x00000007U -#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) -#define SPI_SMEM_DIN5_MODE_V 0x00000007U -#define SPI_SMEM_DIN5_MODE_S 15 -/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN6_MODE 0x00000007U -#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) -#define SPI_SMEM_DIN6_MODE_V 0x00000007U -#define SPI_SMEM_DIN6_MODE_S 18 -/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN7_MODE 0x00000007U -#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) -#define SPI_SMEM_DIN7_MODE_V 0x00000007U -#define SPI_SMEM_DIN7_MODE_S 21 -/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DINS_MODE 0x00000007U -#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) -#define SPI_SMEM_DINS_MODE_V 0x00000007U -#define SPI_SMEM_DINS_MODE_S 24 +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) +/* SPI_MEM_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SMEM_DINS_MODE_M ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S)) +#define SPI_MEM_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SMEM_DINS_MODE_S 24 +/* SPI_MEM_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN7_MODE_M ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN7_MODE_S 21 +/* SPI_MEM_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN6_MODE_M ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN6_MODE_S 18 +/* SPI_MEM_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN5_MODE_M ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN5_MODE_S 15 +/* SPI_MEM_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN4_MODE_M ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN4_MODE_S 12 +/* SPI_MEM_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN3_MODE_M ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN3_MODE_S 9 +/* SPI_MEM_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN2_MODE_M ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN2_MODE_S 6 +/* SPI_MEM_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN1_MODE_M ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN1_MODE_S 3 +/* SPI_MEM_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN0_MODE_M ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN_NUM_REG register - * MSPI external RAM input timing delay number control register - */ -#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198) -/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN0_NUM 0x00000003U -#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) -#define SPI_SMEM_DIN0_NUM_V 0x00000003U -#define SPI_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN1_NUM 0x00000003U -#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) -#define SPI_SMEM_DIN1_NUM_V 0x00000003U -#define SPI_SMEM_DIN1_NUM_S 2 -/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN2_NUM 0x00000003U -#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) -#define SPI_SMEM_DIN2_NUM_V 0x00000003U -#define SPI_SMEM_DIN2_NUM_S 4 -/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN3_NUM 0x00000003U -#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) -#define SPI_SMEM_DIN3_NUM_V 0x00000003U -#define SPI_SMEM_DIN3_NUM_S 6 -/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN4_NUM 0x00000003U -#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) -#define SPI_SMEM_DIN4_NUM_V 0x00000003U -#define SPI_SMEM_DIN4_NUM_S 8 -/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN5_NUM 0x00000003U -#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) -#define SPI_SMEM_DIN5_NUM_V 0x00000003U -#define SPI_SMEM_DIN5_NUM_S 10 -/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN6_NUM 0x00000003U -#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) -#define SPI_SMEM_DIN6_NUM_V 0x00000003U -#define SPI_SMEM_DIN6_NUM_S 12 -/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN7_NUM 0x00000003U -#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) -#define SPI_SMEM_DIN7_NUM_V 0x00000003U -#define SPI_SMEM_DIN7_NUM_S 14 -/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DINS_NUM 0x00000003U -#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) -#define SPI_SMEM_DINS_NUM_V 0x00000003U -#define SPI_SMEM_DINS_NUM_S 16 +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) +/* SPI_MEM_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SMEM_DINS_NUM_M ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S)) +#define SPI_MEM_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SMEM_DINS_NUM_S 16 +/* SPI_MEM_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN7_NUM_M ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN7_NUM_S 14 +/* SPI_MEM_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN6_NUM_M ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN6_NUM_S 12 +/* SPI_MEM_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN5_NUM_M ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN5_NUM_S 10 +/* SPI_MEM_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN4_NUM_M ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN4_NUM_S 8 +/* SPI_MEM_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN3_NUM_M ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN3_NUM_S 6 +/* SPI_MEM_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN2_NUM_M ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN2_NUM_S 4 +/* SPI_MEM_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN1_NUM_M ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN1_NUM_S 2 +/* SPI_MEM_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN0_NUM_M ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DOUT_MODE_REG register - * MSPI external RAM output timing adjustment control register - */ -#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c) -/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) -#define SPI_SMEM_DOUT0_MODE_V 0x00000001U -#define SPI_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) -#define SPI_SMEM_DOUT1_MODE_V 0x00000001U -#define SPI_SMEM_DOUT1_MODE_S 1 -/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) -#define SPI_SMEM_DOUT2_MODE_V 0x00000001U -#define SPI_SMEM_DOUT2_MODE_S 2 -/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) -#define SPI_SMEM_DOUT3_MODE_V 0x00000001U -#define SPI_SMEM_DOUT3_MODE_S 3 -/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) -#define SPI_SMEM_DOUT4_MODE_V 0x00000001U -#define SPI_SMEM_DOUT4_MODE_S 4 -/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) -#define SPI_SMEM_DOUT5_MODE_V 0x00000001U -#define SPI_SMEM_DOUT5_MODE_S 5 -/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) -#define SPI_SMEM_DOUT6_MODE_V 0x00000001U -#define SPI_SMEM_DOUT6_MODE_S 6 -/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) -#define SPI_SMEM_DOUT7_MODE_V 0x00000001U -#define SPI_SMEM_DOUT7_MODE_S 7 -/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) -#define SPI_SMEM_DOUTS_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_MODE_S 8 +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19C) +/* SPI_MEM_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUTS_MODE_S 8 +/* SPI_MEM_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT7_MODE_S 7 +/* SPI_MEM_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT6_MODE_S 6 +/* SPI_MEM_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT5_MODE_S 5 +/* SPI_MEM_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT4_MODE_S 4 +/* SPI_MEM_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT3_MODE_S 3 +/* SPI_MEM_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT2_MODE_S 2 +/* SPI_MEM_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT1_MODE_S 1 +/* SPI_MEM_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_AC_REG register - * MSPI external RAM ECC and SPI CS timing control register - */ -#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0) -/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; - * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: - * disable. - */ -#define SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) -#define SPI_SMEM_CS_SETUP_V 0x00000001U -#define SPI_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; - * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ -#define SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) -#define SPI_SMEM_CS_HOLD_V 0x00000001U -#define SPI_SMEM_CS_HOLD_S 1 -/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; - * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. - */ -#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) -#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_S 2 -/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; - * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. - */ -#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) -#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_S 7 -/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. - */ -#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) -#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; - * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when - * accesses external RAM. - */ -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses external RAM. - */ -#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. - */ -#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) -#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_S 25 -/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; - * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter - * whether there is an ECC region or not. - */ -#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) -#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) -#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_SMEM_SPLIT_TRANS_EN_S 31 +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0) +/* SPI_MEM_SMEM_SPLIT_TRANS_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt +er whether there is an ECC region or not..*/ +#define SPI_MEM_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M (BIT(31)) +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S 31 +/* SPI_MEM_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M +SPI core clock cycles..*/ +#define SPI_MEM_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SMEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses external RAM..*/ +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S 16 +/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh +en accesses external RAM..*/ +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c +ycles in ECC mode when accessed external RAM..*/ +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S 12 +/* SPI_MEM_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */ +/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a +re combined with spi_mem_cs_hold bit..*/ +#define SPI_MEM_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SMEM_CS_HOLD_TIME_S 7 +/* SPI_MEM_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */ +/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s +pi_mem_cs_setup bit..*/ +#define SPI_MEM_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SMEM_CS_SETUP_TIME_S 2 +/* SPI_MEM_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab +le..*/ +#define SPI_MEM_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SMEM_CS_HOLD_S 1 +/* SPI_MEM_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d +isable..*/ +#define SPI_MEM_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_DIN_HEX_MODE_REG register - * MSPI 16x external RAM input timing delay mode control register - */ -#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1a4) -/** SPI_SMEM_DIN08_MODE : HRO; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN08_MODE 0x00000007U -#define SPI_SMEM_DIN08_MODE_M (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S) -#define SPI_SMEM_DIN08_MODE_V 0x00000007U -#define SPI_SMEM_DIN08_MODE_S 0 -/** SPI_SMEM_DIN09_MODE : HRO; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN09_MODE 0x00000007U -#define SPI_SMEM_DIN09_MODE_M (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S) -#define SPI_SMEM_DIN09_MODE_V 0x00000007U -#define SPI_SMEM_DIN09_MODE_S 3 -/** SPI_SMEM_DIN10_MODE : HRO; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN10_MODE 0x00000007U -#define SPI_SMEM_DIN10_MODE_M (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S) -#define SPI_SMEM_DIN10_MODE_V 0x00000007U -#define SPI_SMEM_DIN10_MODE_S 6 -/** SPI_SMEM_DIN11_MODE : HRO; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN11_MODE 0x00000007U -#define SPI_SMEM_DIN11_MODE_M (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S) -#define SPI_SMEM_DIN11_MODE_V 0x00000007U -#define SPI_SMEM_DIN11_MODE_S 9 -/** SPI_SMEM_DIN12_MODE : HRO; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN12_MODE 0x00000007U -#define SPI_SMEM_DIN12_MODE_M (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S) -#define SPI_SMEM_DIN12_MODE_V 0x00000007U -#define SPI_SMEM_DIN12_MODE_S 12 -/** SPI_SMEM_DIN13_MODE : HRO; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN13_MODE 0x00000007U -#define SPI_SMEM_DIN13_MODE_M (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S) -#define SPI_SMEM_DIN13_MODE_V 0x00000007U -#define SPI_SMEM_DIN13_MODE_S 15 -/** SPI_SMEM_DIN14_MODE : HRO; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN14_MODE 0x00000007U -#define SPI_SMEM_DIN14_MODE_M (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S) -#define SPI_SMEM_DIN14_MODE_V 0x00000007U -#define SPI_SMEM_DIN14_MODE_S 18 -/** SPI_SMEM_DIN15_MODE : HRO; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN15_MODE 0x00000007U -#define SPI_SMEM_DIN15_MODE_M (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S) -#define SPI_SMEM_DIN15_MODE_V 0x00000007U -#define SPI_SMEM_DIN15_MODE_S 21 -/** SPI_SMEM_DINS_HEX_MODE : HRO; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DINS_HEX_MODE 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_M (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S) -#define SPI_SMEM_DINS_HEX_MODE_V 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_S 24 +#define SPI_MEM_SPI_SMEM_DIN_HEX_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A4) +/* SPI_MEM_SMEM_DINS_HEX_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DINS_HEX_MODE 0x00000007 +#define SPI_MEM_SMEM_DINS_HEX_MODE_M ((SPI_MEM_SMEM_DINS_HEX_MODE_V)<<(SPI_MEM_SMEM_DINS_HEX_MODE_S)) +#define SPI_MEM_SMEM_DINS_HEX_MODE_V 0x7 +#define SPI_MEM_SMEM_DINS_HEX_MODE_S 24 +/* SPI_MEM_SMEM_DIN15_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN15_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN15_MODE_M ((SPI_MEM_SMEM_DIN15_MODE_V)<<(SPI_MEM_SMEM_DIN15_MODE_S)) +#define SPI_MEM_SMEM_DIN15_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN15_MODE_S 21 +/* SPI_MEM_SMEM_DIN14_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN14_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN14_MODE_M ((SPI_MEM_SMEM_DIN14_MODE_V)<<(SPI_MEM_SMEM_DIN14_MODE_S)) +#define SPI_MEM_SMEM_DIN14_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN14_MODE_S 18 +/* SPI_MEM_SMEM_DIN13_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN13_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN13_MODE_M ((SPI_MEM_SMEM_DIN13_MODE_V)<<(SPI_MEM_SMEM_DIN13_MODE_S)) +#define SPI_MEM_SMEM_DIN13_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN13_MODE_S 15 +/* SPI_MEM_SMEM_DIN12_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN12_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN12_MODE_M ((SPI_MEM_SMEM_DIN12_MODE_V)<<(SPI_MEM_SMEM_DIN12_MODE_S)) +#define SPI_MEM_SMEM_DIN12_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN12_MODE_S 12 +/* SPI_MEM_SMEM_DIN11_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN11_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN11_MODE_M ((SPI_MEM_SMEM_DIN11_MODE_V)<<(SPI_MEM_SMEM_DIN11_MODE_S)) +#define SPI_MEM_SMEM_DIN11_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN11_MODE_S 9 +/* SPI_MEM_SMEM_DIN10_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN10_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN10_MODE_M ((SPI_MEM_SMEM_DIN10_MODE_V)<<(SPI_MEM_SMEM_DIN10_MODE_S)) +#define SPI_MEM_SMEM_DIN10_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN10_MODE_S 6 +/* SPI_MEM_SMEM_DIN09_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN09_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN09_MODE_M ((SPI_MEM_SMEM_DIN09_MODE_V)<<(SPI_MEM_SMEM_DIN09_MODE_S)) +#define SPI_MEM_SMEM_DIN09_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN09_MODE_S 3 +/* SPI_MEM_SMEM_DIN08_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN08_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN08_MODE_M ((SPI_MEM_SMEM_DIN08_MODE_V)<<(SPI_MEM_SMEM_DIN08_MODE_S)) +#define SPI_MEM_SMEM_DIN08_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN08_MODE_S 0 -/** SPI_SMEM_DIN_HEX_NUM_REG register - * MSPI 16x external RAM input timing delay number control register - */ -#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_SPI_BASE + 0x1a8) -/** SPI_SMEM_DIN08_NUM : HRO; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN08_NUM 0x00000003U -#define SPI_SMEM_DIN08_NUM_M (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S) -#define SPI_SMEM_DIN08_NUM_V 0x00000003U -#define SPI_SMEM_DIN08_NUM_S 0 -/** SPI_SMEM_DIN09_NUM : HRO; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN09_NUM 0x00000003U -#define SPI_SMEM_DIN09_NUM_M (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S) -#define SPI_SMEM_DIN09_NUM_V 0x00000003U -#define SPI_SMEM_DIN09_NUM_S 2 -/** SPI_SMEM_DIN10_NUM : HRO; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN10_NUM 0x00000003U -#define SPI_SMEM_DIN10_NUM_M (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S) -#define SPI_SMEM_DIN10_NUM_V 0x00000003U -#define SPI_SMEM_DIN10_NUM_S 4 -/** SPI_SMEM_DIN11_NUM : HRO; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN11_NUM 0x00000003U -#define SPI_SMEM_DIN11_NUM_M (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S) -#define SPI_SMEM_DIN11_NUM_V 0x00000003U -#define SPI_SMEM_DIN11_NUM_S 6 -/** SPI_SMEM_DIN12_NUM : HRO; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN12_NUM 0x00000003U -#define SPI_SMEM_DIN12_NUM_M (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S) -#define SPI_SMEM_DIN12_NUM_V 0x00000003U -#define SPI_SMEM_DIN12_NUM_S 8 -/** SPI_SMEM_DIN13_NUM : HRO; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN13_NUM 0x00000003U -#define SPI_SMEM_DIN13_NUM_M (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S) -#define SPI_SMEM_DIN13_NUM_V 0x00000003U -#define SPI_SMEM_DIN13_NUM_S 10 -/** SPI_SMEM_DIN14_NUM : HRO; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN14_NUM 0x00000003U -#define SPI_SMEM_DIN14_NUM_M (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S) -#define SPI_SMEM_DIN14_NUM_V 0x00000003U -#define SPI_SMEM_DIN14_NUM_S 12 -/** SPI_SMEM_DIN15_NUM : HRO; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN15_NUM 0x00000003U -#define SPI_SMEM_DIN15_NUM_M (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S) -#define SPI_SMEM_DIN15_NUM_V 0x00000003U -#define SPI_SMEM_DIN15_NUM_S 14 -/** SPI_SMEM_DINS_HEX_NUM : HRO; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DINS_HEX_NUM 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_M (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S) -#define SPI_SMEM_DINS_HEX_NUM_V 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_S 16 +#define SPI_MEM_SPI_SMEM_DIN_HEX_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A8) +/* SPI_MEM_SMEM_DINS_HEX_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DINS_HEX_NUM 0x00000003 +#define SPI_MEM_SMEM_DINS_HEX_NUM_M ((SPI_MEM_SMEM_DINS_HEX_NUM_V)<<(SPI_MEM_SMEM_DINS_HEX_NUM_S)) +#define SPI_MEM_SMEM_DINS_HEX_NUM_V 0x3 +#define SPI_MEM_SMEM_DINS_HEX_NUM_S 16 +/* SPI_MEM_SMEM_DIN15_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN15_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN15_NUM_M ((SPI_MEM_SMEM_DIN15_NUM_V)<<(SPI_MEM_SMEM_DIN15_NUM_S)) +#define SPI_MEM_SMEM_DIN15_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN15_NUM_S 14 +/* SPI_MEM_SMEM_DIN14_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN14_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN14_NUM_M ((SPI_MEM_SMEM_DIN14_NUM_V)<<(SPI_MEM_SMEM_DIN14_NUM_S)) +#define SPI_MEM_SMEM_DIN14_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN14_NUM_S 12 +/* SPI_MEM_SMEM_DIN13_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN13_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN13_NUM_M ((SPI_MEM_SMEM_DIN13_NUM_V)<<(SPI_MEM_SMEM_DIN13_NUM_S)) +#define SPI_MEM_SMEM_DIN13_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN13_NUM_S 10 +/* SPI_MEM_SMEM_DIN12_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN12_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN12_NUM_M ((SPI_MEM_SMEM_DIN12_NUM_V)<<(SPI_MEM_SMEM_DIN12_NUM_S)) +#define SPI_MEM_SMEM_DIN12_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN12_NUM_S 8 +/* SPI_MEM_SMEM_DIN11_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN11_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN11_NUM_M ((SPI_MEM_SMEM_DIN11_NUM_V)<<(SPI_MEM_SMEM_DIN11_NUM_S)) +#define SPI_MEM_SMEM_DIN11_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN11_NUM_S 6 +/* SPI_MEM_SMEM_DIN10_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN10_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN10_NUM_M ((SPI_MEM_SMEM_DIN10_NUM_V)<<(SPI_MEM_SMEM_DIN10_NUM_S)) +#define SPI_MEM_SMEM_DIN10_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN10_NUM_S 4 +/* SPI_MEM_SMEM_DIN09_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN09_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN09_NUM_M ((SPI_MEM_SMEM_DIN09_NUM_V)<<(SPI_MEM_SMEM_DIN09_NUM_S)) +#define SPI_MEM_SMEM_DIN09_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN09_NUM_S 2 +/* SPI_MEM_SMEM_DIN08_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN08_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN08_NUM_M ((SPI_MEM_SMEM_DIN08_NUM_V)<<(SPI_MEM_SMEM_DIN08_NUM_S)) +#define SPI_MEM_SMEM_DIN08_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN08_NUM_S 0 -/** SPI_SMEM_DOUT_HEX_MODE_REG register - * MSPI 16x external RAM output timing adjustment control register - */ -#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1ac) -/** SPI_SMEM_DOUT08_MODE : HRO; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT08_MODE (BIT(0)) -#define SPI_SMEM_DOUT08_MODE_M (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S) -#define SPI_SMEM_DOUT08_MODE_V 0x00000001U -#define SPI_SMEM_DOUT08_MODE_S 0 -/** SPI_SMEM_DOUT09_MODE : HRO; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT09_MODE (BIT(1)) -#define SPI_SMEM_DOUT09_MODE_M (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S) -#define SPI_SMEM_DOUT09_MODE_V 0x00000001U -#define SPI_SMEM_DOUT09_MODE_S 1 -/** SPI_SMEM_DOUT10_MODE : HRO; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT10_MODE (BIT(2)) -#define SPI_SMEM_DOUT10_MODE_M (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S) -#define SPI_SMEM_DOUT10_MODE_V 0x00000001U -#define SPI_SMEM_DOUT10_MODE_S 2 -/** SPI_SMEM_DOUT11_MODE : HRO; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT11_MODE (BIT(3)) -#define SPI_SMEM_DOUT11_MODE_M (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S) -#define SPI_SMEM_DOUT11_MODE_V 0x00000001U -#define SPI_SMEM_DOUT11_MODE_S 3 -/** SPI_SMEM_DOUT12_MODE : HRO; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT12_MODE (BIT(4)) -#define SPI_SMEM_DOUT12_MODE_M (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S) -#define SPI_SMEM_DOUT12_MODE_V 0x00000001U -#define SPI_SMEM_DOUT12_MODE_S 4 -/** SPI_SMEM_DOUT13_MODE : HRO; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT13_MODE (BIT(5)) -#define SPI_SMEM_DOUT13_MODE_M (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S) -#define SPI_SMEM_DOUT13_MODE_V 0x00000001U -#define SPI_SMEM_DOUT13_MODE_S 5 -/** SPI_SMEM_DOUT14_MODE : HRO; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT14_MODE (BIT(6)) -#define SPI_SMEM_DOUT14_MODE_M (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S) -#define SPI_SMEM_DOUT14_MODE_V 0x00000001U -#define SPI_SMEM_DOUT14_MODE_S 6 -/** SPI_SMEM_DOUT15_MODE : HRO; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT15_MODE (BIT(7)) -#define SPI_SMEM_DOUT15_MODE_M (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S) -#define SPI_SMEM_DOUT15_MODE_V 0x00000001U -#define SPI_SMEM_DOUT15_MODE_S 7 -/** SPI_SMEM_DOUTS_HEX_MODE : HRO; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_HEX_MODE_M (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S) -#define SPI_SMEM_DOUTS_HEX_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_HEX_MODE_S 8 +#define SPI_MEM_SPI_SMEM_DOUT_HEX_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x1AC) +/* SPI_MEM_SMEM_DOUTS_HEX_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUTS_HEX_MODE (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_HEX_MODE_M (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_HEX_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUTS_HEX_MODE_S 8 +/* SPI_MEM_SMEM_DOUT15_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT15_MODE (BIT(7)) +#define SPI_MEM_SMEM_DOUT15_MODE_M (BIT(7)) +#define SPI_MEM_SMEM_DOUT15_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT15_MODE_S 7 +/* SPI_MEM_SMEM_DOUT14_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT14_MODE (BIT(6)) +#define SPI_MEM_SMEM_DOUT14_MODE_M (BIT(6)) +#define SPI_MEM_SMEM_DOUT14_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT14_MODE_S 6 +/* SPI_MEM_SMEM_DOUT13_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT13_MODE (BIT(5)) +#define SPI_MEM_SMEM_DOUT13_MODE_M (BIT(5)) +#define SPI_MEM_SMEM_DOUT13_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT13_MODE_S 5 +/* SPI_MEM_SMEM_DOUT12_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT12_MODE (BIT(4)) +#define SPI_MEM_SMEM_DOUT12_MODE_M (BIT(4)) +#define SPI_MEM_SMEM_DOUT12_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT12_MODE_S 4 +/* SPI_MEM_SMEM_DOUT11_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT11_MODE (BIT(3)) +#define SPI_MEM_SMEM_DOUT11_MODE_M (BIT(3)) +#define SPI_MEM_SMEM_DOUT11_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT11_MODE_S 3 +/* SPI_MEM_SMEM_DOUT10_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT10_MODE (BIT(2)) +#define SPI_MEM_SMEM_DOUT10_MODE_M (BIT(2)) +#define SPI_MEM_SMEM_DOUT10_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT10_MODE_S 2 +/* SPI_MEM_SMEM_DOUT09_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT09_MODE (BIT(1)) +#define SPI_MEM_SMEM_DOUT09_MODE_M (BIT(1)) +#define SPI_MEM_SMEM_DOUT09_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT09_MODE_S 1 +/* SPI_MEM_SMEM_DOUT08_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT08_MODE (BIT(0)) +#define SPI_MEM_SMEM_DOUT08_MODE_M (BIT(0)) +#define SPI_MEM_SMEM_DOUT08_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT08_MODE_S 0 -/** SPI_MEM_CLOCK_GATE_REG register - * SPI0 clock gate register - */ -#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200) -/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Register clock gate enable signal. 1: Enable. 0: Disable. - */ -#define SPI_CLK_EN (BIT(0)) -#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) -#define SPI_CLK_EN_V 0x00000001U -#define SPI_CLK_EN_S 0 +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 -/** SPI_MEM_NAND_FLASH_EN_REG register - * NAND FLASH control register - */ -#define SPI_MEM_NAND_FLASH_EN_REG (DR_REG_SPI_BASE + 0x204) -/** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; - * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: - * Disable NAND FLASH, Enable NOR FLASH. - */ -#define SPI_MEM_NAND_FLASH_EN (BIT(0)) -#define SPI_MEM_NAND_FLASH_EN_M (SPI_MEM_NAND_FLASH_EN_V << SPI_MEM_NAND_FLASH_EN_S) -#define SPI_MEM_NAND_FLASH_EN_V 0x00000001U -#define SPI_MEM_NAND_FLASH_EN_S 0 -/** SPI_MEM_NAND_FLASH_SEQ_HD_INDEX : HRO; bitpos: [15:1]; default: 32767; - * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st - * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. - */ -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX 0x00007FFFU -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_M (SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V << SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S) -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V 0x00007FFFU -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S 1 -/** SPI_MEM_NAND_FLASH_SEQ_USR_TRIG : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG (BIT(16)) -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_M (SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V << SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S) -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S 16 -/** SPI_MEM_NAND_FLASH_LUT_EN : HRO; bitpos: [17]; default: 0; - * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_LUT_EN (BIT(17)) -#define SPI_MEM_NAND_FLASH_LUT_EN_M (SPI_MEM_NAND_FLASH_LUT_EN_V << SPI_MEM_NAND_FLASH_LUT_EN_S) -#define SPI_MEM_NAND_FLASH_LUT_EN_V 0x00000001U -#define SPI_MEM_NAND_FLASH_LUT_EN_S 17 -/** SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO; bitpos: [18]; default: 0; - * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and to - * excute page excute. 1: write end 0: write in a page size. - */ +#define SPI_MEM_NAND_FLASH_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x204) +/* SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and + to excute page excute. 1: write end 0: write in a page size..*/ #define SPI_MEM_NAND_FLASH_SEQ_USR_WEND (BIT(18)) -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M (SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V << SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S) -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M (BIT(18)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V 0x1 #define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S 18 +/* SPI_MEM_NAND_FLASH_LUT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable..*/ +#define SPI_MEM_NAND_FLASH_LUT_EN (BIT(17)) +#define SPI_MEM_NAND_FLASH_LUT_EN_M (BIT(17)) +#define SPI_MEM_NAND_FLASH_LUT_EN_V 0x1 +#define SPI_MEM_NAND_FLASH_LUT_EN_S 17 +/* SPI_MEM_NAND_FLASH_SEQ_USR_TRIG : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_T +RIG is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disabl +e..*/ +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG (BIT(16)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_M (BIT(16)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V 0x1 +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S 16 +/* SPI_MEM_NAND_FLASH_SEQ_HD_INDEX : HRO ;bitpos:[15:1] ;default: 15'h7fff ; */ +/*description: NAND FLASH spi seq head index configure register. Every 5 bits represent the 1s +t index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr..*/ +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX 0x00007FFF +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_M ((SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V)<<(SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S)) +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V 0x7FFF +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S 1 +/* SPI_MEM_NAND_FLASH_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: D +isable NAND FLASH, Enable NOR FLASH..*/ +#define SPI_MEM_NAND_FLASH_EN (BIT(0)) +#define SPI_MEM_NAND_FLASH_EN_M (BIT(0)) +#define SPI_MEM_NAND_FLASH_EN_V 0x1 +#define SPI_MEM_NAND_FLASH_EN_S 0 -/** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG (DR_REG_SPI_BASE + 0x208) -/** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR0_M (SPI_MEM_NAND_FLASH_SR_ADDR0_V << SPI_MEM_NAND_FLASH_SR_ADDR0_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR0_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR0_S 0 -/** SPI_MEM_NAND_FLASH_SR_ADDR1 : HRO; bitpos: [15:8]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR1 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR1_M (SPI_MEM_NAND_FLASH_SR_ADDR1_V << SPI_MEM_NAND_FLASH_SR_ADDR1_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR1_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR1_S 8 -/** SPI_MEM_NAND_FLASH_SR_ADDR2 : HRO; bitpos: [23:16]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR2 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR2_M (SPI_MEM_NAND_FLASH_SR_ADDR2_V << SPI_MEM_NAND_FLASH_SR_ADDR2_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR2_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR2_S 16 -/** SPI_MEM_NAND_FLASH_SR_ADDR3 : HRO; bitpos: [31:24]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR3 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR3_M (SPI_MEM_NAND_FLASH_SR_ADDR3_V << SPI_MEM_NAND_FLASH_SR_ADDR3_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR3_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG(i) (REG_SPI_MEM_BASE(i) + 0x208) +/* SPI_MEM_NAND_FLASH_SR_ADDR3 : HRO ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: configure state register address for SPI SEQ need. If OIP is in address C0H , us +er could configure C0H into this register.*/ +#define SPI_MEM_NAND_FLASH_SR_ADDR3 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_ADDR3_M ((SPI_MEM_NAND_FLASH_SR_ADDR3_V)<<(SPI_MEM_NAND_FLASH_SR_ADDR3_S)) +#define SPI_MEM_NAND_FLASH_SR_ADDR3_V 0xFF #define SPI_MEM_NAND_FLASH_SR_ADDR3_S 24 +/* SPI_MEM_NAND_FLASH_SR_ADDR2 : HRO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: configure state register address for SPI SEQ need. If OIP is in address C0H , us +er could configure C0H into this register.*/ +#define SPI_MEM_NAND_FLASH_SR_ADDR2 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_ADDR2_M ((SPI_MEM_NAND_FLASH_SR_ADDR2_V)<<(SPI_MEM_NAND_FLASH_SR_ADDR2_S)) +#define SPI_MEM_NAND_FLASH_SR_ADDR2_V 0xFF +#define SPI_MEM_NAND_FLASH_SR_ADDR2_S 16 +/* SPI_MEM_NAND_FLASH_SR_ADDR1 : HRO ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: configure state register address for SPI SEQ need. If OIP is in address C0H , us +er could configure C0H into this register.*/ +#define SPI_MEM_NAND_FLASH_SR_ADDR1 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_ADDR1_M ((SPI_MEM_NAND_FLASH_SR_ADDR1_V)<<(SPI_MEM_NAND_FLASH_SR_ADDR1_S)) +#define SPI_MEM_NAND_FLASH_SR_ADDR1_V 0xFF +#define SPI_MEM_NAND_FLASH_SR_ADDR1_S 8 +/* SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: configure state register address for SPI SEQ need. If OIP is in address C0H , us +er could configure C0H into this register.*/ +#define SPI_MEM_NAND_FLASH_SR_ADDR0 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_ADDR0_M ((SPI_MEM_NAND_FLASH_SR_ADDR0_V)<<(SPI_MEM_NAND_FLASH_SR_ADDR0_S)) +#define SPI_MEM_NAND_FLASH_SR_ADDR0_V 0xFF +#define SPI_MEM_NAND_FLASH_SR_ADDR0_S 0 -/** SPI_MEM_NAND_FLASH_SR_DIN0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SR_DIN0_REG (DR_REG_SPI_BASE + 0x20c) -/** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN0 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN0_M (SPI_MEM_NAND_FLASH_SR_DIN0_V << SPI_MEM_NAND_FLASH_SR_DIN0_S) -#define SPI_MEM_NAND_FLASH_SR_DIN0_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN0_S 0 -/** SPI_MEM_NAND_FLASH_SR_DIN1 : RO; bitpos: [15:8]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN1 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN1_M (SPI_MEM_NAND_FLASH_SR_DIN1_V << SPI_MEM_NAND_FLASH_SR_DIN1_S) -#define SPI_MEM_NAND_FLASH_SR_DIN1_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN1_S 8 -/** SPI_MEM_NAND_FLASH_SR_DIN2 : RO; bitpos: [23:16]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN2 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN2_M (SPI_MEM_NAND_FLASH_SR_DIN2_V << SPI_MEM_NAND_FLASH_SR_DIN2_S) -#define SPI_MEM_NAND_FLASH_SR_DIN2_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN2_S 16 -/** SPI_MEM_NAND_FLASH_SR_DIN3 : RO; bitpos: [31:24]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN3 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN3_M (SPI_MEM_NAND_FLASH_SR_DIN3_V << SPI_MEM_NAND_FLASH_SR_DIN3_S) -#define SPI_MEM_NAND_FLASH_SR_DIN3_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN0_REG(i) (REG_SPI_MEM_BASE(i) + 0x20C) +/* SPI_MEM_NAND_FLASH_SR_DIN3 : RO ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLA +SH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG..*/ +#define SPI_MEM_NAND_FLASH_SR_DIN3 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_DIN3_M ((SPI_MEM_NAND_FLASH_SR_DIN3_V)<<(SPI_MEM_NAND_FLASH_SR_DIN3_S)) +#define SPI_MEM_NAND_FLASH_SR_DIN3_V 0xFF #define SPI_MEM_NAND_FLASH_SR_DIN3_S 24 +/* SPI_MEM_NAND_FLASH_SR_DIN2 : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLA +SH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG..*/ +#define SPI_MEM_NAND_FLASH_SR_DIN2 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_DIN2_M ((SPI_MEM_NAND_FLASH_SR_DIN2_V)<<(SPI_MEM_NAND_FLASH_SR_DIN2_S)) +#define SPI_MEM_NAND_FLASH_SR_DIN2_V 0xFF +#define SPI_MEM_NAND_FLASH_SR_DIN2_S 16 +/* SPI_MEM_NAND_FLASH_SR_DIN1 : RO ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLA +SH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG..*/ +#define SPI_MEM_NAND_FLASH_SR_DIN1 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_DIN1_M ((SPI_MEM_NAND_FLASH_SR_DIN1_V)<<(SPI_MEM_NAND_FLASH_SR_DIN1_S)) +#define SPI_MEM_NAND_FLASH_SR_DIN1_V 0xFF +#define SPI_MEM_NAND_FLASH_SR_DIN1_S 8 +/* SPI_MEM_NAND_FLASH_SR_DIN0 : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLA +SH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG..*/ +#define SPI_MEM_NAND_FLASH_SR_DIN0 0x000000FF +#define SPI_MEM_NAND_FLASH_SR_DIN0_M ((SPI_MEM_NAND_FLASH_SR_DIN0_V)<<(SPI_MEM_NAND_FLASH_SR_DIN0_S)) +#define SPI_MEM_NAND_FLASH_SR_DIN0_V 0xFF +#define SPI_MEM_NAND_FLASH_SR_DIN0_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG (DR_REG_SPI_BASE + 0x210) -/** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA0_M (SPI_MEM_NAND_FLASH_CFG_DATA0_V << SPI_MEM_NAND_FLASH_CFG_DATA0_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA0_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA0_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA1 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA1_M (SPI_MEM_NAND_FLASH_CFG_DATA1_V << SPI_MEM_NAND_FLASH_CFG_DATA1_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA1_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG(i) (REG_SPI_MEM_BASE(i) + 0x210) +/* SPI_MEM_NAND_FLASH_CFG_DATA1 : HRO ;bitpos:[31:16] ;default: 16'b0 ; */ +/*description: configure data for SPI SEQ din/dout need. The data could be use to configure NAN +D FLASH or compare read data.*/ +#define SPI_MEM_NAND_FLASH_CFG_DATA1 0x0000FFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA1_M ((SPI_MEM_NAND_FLASH_CFG_DATA1_V)<<(SPI_MEM_NAND_FLASH_CFG_DATA1_S)) +#define SPI_MEM_NAND_FLASH_CFG_DATA1_V 0xFFFF #define SPI_MEM_NAND_FLASH_CFG_DATA1_S 16 +/* SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: configure data for SPI SEQ din/dout need. The data could be use to configure NAN +D FLASH or compare read data.*/ +#define SPI_MEM_NAND_FLASH_CFG_DATA0 0x0000FFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA0_M ((SPI_MEM_NAND_FLASH_CFG_DATA0_V)<<(SPI_MEM_NAND_FLASH_CFG_DATA0_S)) +#define SPI_MEM_NAND_FLASH_CFG_DATA0_V 0xFFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA0_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG (DR_REG_SPI_BASE + 0x214) -/** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA2_M (SPI_MEM_NAND_FLASH_CFG_DATA2_V << SPI_MEM_NAND_FLASH_CFG_DATA2_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA2_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA2_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA3 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA3 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA3_M (SPI_MEM_NAND_FLASH_CFG_DATA3_V << SPI_MEM_NAND_FLASH_CFG_DATA3_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA3_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG(i) (REG_SPI_MEM_BASE(i) + 0x214) +/* SPI_MEM_NAND_FLASH_CFG_DATA3 : HRO ;bitpos:[31:16] ;default: 16'b0 ; */ +/*description: configure data for SPI SEQ din/dout need. The data could be use to configure NAN +D FLASH or compare read data.*/ +#define SPI_MEM_NAND_FLASH_CFG_DATA3 0x0000FFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA3_M ((SPI_MEM_NAND_FLASH_CFG_DATA3_V)<<(SPI_MEM_NAND_FLASH_CFG_DATA3_S)) +#define SPI_MEM_NAND_FLASH_CFG_DATA3_V 0xFFFF #define SPI_MEM_NAND_FLASH_CFG_DATA3_S 16 +/* SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: configure data for SPI SEQ din/dout need. The data could be use to configure NAN +D FLASH or compare read data.*/ +#define SPI_MEM_NAND_FLASH_CFG_DATA2 0x0000FFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA2_M ((SPI_MEM_NAND_FLASH_CFG_DATA2_V)<<(SPI_MEM_NAND_FLASH_CFG_DATA2_S)) +#define SPI_MEM_NAND_FLASH_CFG_DATA2_V 0xFFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA2_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG (DR_REG_SPI_BASE + 0x218) -/** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA4 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA4_M (SPI_MEM_NAND_FLASH_CFG_DATA4_V << SPI_MEM_NAND_FLASH_CFG_DATA4_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA4_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA4_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA5 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA5 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA5_M (SPI_MEM_NAND_FLASH_CFG_DATA5_V << SPI_MEM_NAND_FLASH_CFG_DATA5_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA5_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG(i) (REG_SPI_MEM_BASE(i) + 0x218) +/* SPI_MEM_NAND_FLASH_CFG_DATA5 : HRO ;bitpos:[31:16] ;default: 16'b0 ; */ +/*description: configure data for SPI SEQ din/dout need. The data could be use to configure NAN +D FLASH or compare read data.*/ +#define SPI_MEM_NAND_FLASH_CFG_DATA5 0x0000FFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA5_M ((SPI_MEM_NAND_FLASH_CFG_DATA5_V)<<(SPI_MEM_NAND_FLASH_CFG_DATA5_S)) +#define SPI_MEM_NAND_FLASH_CFG_DATA5_V 0xFFFF #define SPI_MEM_NAND_FLASH_CFG_DATA5_S 16 +/* SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: configure data for SPI SEQ din/dout need. The data could be use to configure NAN +D FLASH or compare read data.*/ +#define SPI_MEM_NAND_FLASH_CFG_DATA4 0x0000FFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA4_M ((SPI_MEM_NAND_FLASH_CFG_DATA4_V)<<(SPI_MEM_NAND_FLASH_CFG_DATA4_S)) +#define SPI_MEM_NAND_FLASH_CFG_DATA4_V 0xFFFF +#define SPI_MEM_NAND_FLASH_CFG_DATA4_S 0 -/** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register - * MSPI NAND FLASH CMD LUT control register - */ -#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG (DR_REG_SPI_BASE + 0x240) -/** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; - * MSPI NAND FLASH config cmd value at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_M (SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V << SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S) -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S 0 -/** SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 : HRO; bitpos: [19:16]; default: 0; - * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; - * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. - */ -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_M (SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V << SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S) -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S 16 -/** SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 : HRO; bitpos: [23:20]; default: 0; - * MSPI NAND FLASH config cmd length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_M (SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V << SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S 20 -/** SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 : HRO; bitpos: [27:24]; default: 0; - * MSPI NAND FLASH config address length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_M (SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V << SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S 24 -/** SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 : HRO; bitpos: [29:28]; default: 0; - * MSPI NAND FLASH config data length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 0x00000003U -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_M (SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V << SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V 0x00000003U -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S 28 -/** SPI_MEM_NAND_FLASH_LUT_BUS_EN0 : HRO; bitpos: [30]; default: 0; - * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode - * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's - * field. The number of CMD LUT entries can be defined by the user, but cannot exceed - * 16 ) - */ +#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG(i) (REG_SPI_MEM_BASE(i) + 0x240) +/* SPI_MEM_NAND_FLASH_LUT_BUS_EN0 : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: MSPI NAND FLASH config spi_bus_en at cmd lut address $n,SPI could use DUAL/QUAD +mode while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.( +Note these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT$n_ +REG's field. The number of CMD LUT entries can be defined by the user, but canno +t exceed 16 ).*/ #define SPI_MEM_NAND_FLASH_LUT_BUS_EN0 (BIT(30)) -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_M (SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V << SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S) -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_M (BIT(30)) +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V 0x1 #define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S 30 +/* SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 : HRO ;bitpos:[29:28] ;default: 2'b0 ; */ +/*description: MSPI NAND FLASH config data length at cmd lut address $n..*/ +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 0x00000003 +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_M ((SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V)<<(SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S)) +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V 0x3 +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S 28 +/* SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 : HRO ;bitpos:[27:24] ;default: 4'b0 ; */ +/*description: MSPI NAND FLASH config address length at cmd lut address $n..*/ +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 0x0000000F +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_M ((SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V)<<(SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S)) +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V 0xF +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S 24 +/* SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 : HRO ;bitpos:[23:20] ;default: 4'b0 ; */ +/*description: MSPI NAND FLASH config cmd length at cmd lut address $n..*/ +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 0x0000000F +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_M ((SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V)<<(SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S)) +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V 0xF +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S 20 +/* SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 : HRO ;bitpos:[19:16] ;default: 4'b0 ; */ +/*description: MSPI NAND FLASH config sfsm_st_en at cmd lut address $n.[3]-ADDR period enable; +[2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period..*/ +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 0x0000000F +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_M ((SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V)<<(SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S)) +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V 0xF +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S 16 +/* SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: MSPI NAND FLASH config cmd value at cmd lut address $n..*/ +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 0x0000FFFF +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_M ((SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V)<<(SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S)) +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V 0xFFFF +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S 0 -/** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG (DR_REG_SPI_BASE + 0x280) -/** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; - * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for - * sequence. 0: Not the last index. - */ -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 (BIT(0)) -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_M (SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V << SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S) -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S 0 -/** SPI_MEM_NAND_FLASH_SR_CHK_EN0 : HRO; bitpos: [1]; default: 0; - * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0 (BIT(1)) -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_M (SPI_MEM_NAND_FLASH_SR_CHK_EN0_V << SPI_MEM_NAND_FLASH_SR_CHK_EN0_S) -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_S 1 -/** SPI_MEM_NAND_FLASH_DIN_INDEX0 : HRO; bitpos: [5:2]; default: 0; - * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_CFG_DATA - */ -#define SPI_MEM_NAND_FLASH_DIN_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_M (SPI_MEM_NAND_FLASH_DIN_INDEX0_V << SPI_MEM_NAND_FLASH_DIN_INDEX0_S) -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_S 2 -/** SPI_MEM_NAND_FLASH_ADDR_INDEX0 : HRO; bitpos: [9:6]; default: 0; - * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_SR_ADDR - */ -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_M (SPI_MEM_NAND_FLASH_ADDR_INDEX0_V << SPI_MEM_NAND_FLASH_ADDR_INDEX0_S) -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_S 6 -/** SPI_MEM_NAND_FLASH_REQ_OR_CFG0 : HRO; bitpos: [10]; default: 0; - * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI - * SEQ configuration. - */ -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0 (BIT(10)) -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_M (SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V << SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S) -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S 10 -/** SPI_MEM_NAND_FLASH_CMD_INDEX0 : HRO; bitpos: [14:11]; default: 0; - * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in - * CMD LUT.(Note these registers are described to indicate the - * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined - * by the user, but cannot exceed 16 ) - */ -#define SPI_MEM_NAND_FLASH_CMD_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_M (SPI_MEM_NAND_FLASH_CMD_INDEX0_V << SPI_MEM_NAND_FLASH_CMD_INDEX0_S) -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG(i) (REG_SPI_MEM_BASE(i) + 0x280) +/* SPI_MEM_NAND_FLASH_CMD_INDEX0 : HRO ;bitpos:[14:11] ;default: 4'b0 ; */ +/*description: MSPI NAND FLASH config spi_cmd_index at spi seq index $n. Use to find SPI comman +d in CMD LUT.(Note these registers are described to indicate the SPI_MEM_NAND_FL +ASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined by the user +, but cannot exceed 16 ).*/ +#define SPI_MEM_NAND_FLASH_CMD_INDEX0 0x0000000F +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_M ((SPI_MEM_NAND_FLASH_CMD_INDEX0_V)<<(SPI_MEM_NAND_FLASH_CMD_INDEX0_S)) +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_V 0xF #define SPI_MEM_NAND_FLASH_CMD_INDEX0_S 11 +/* SPI_MEM_NAND_FLASH_REQ_OR_CFG0 : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: MSPI NAND FLASH config reg_or_cfg at spi seq index $n. 1: AXI/APB request 0: SP +I SEQ configuration..*/ +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0 (BIT(10)) +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_M (BIT(10)) +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V 0x1 +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S 10 +/* SPI_MEM_NAND_FLASH_ADDR_INDEX0 : HRO ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: MSPI NAND FLASH config addr_index at spi seq index $n. Use with SPI_MEM_NAND_FL +ASH_SR_ADDR.*/ +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0 0x0000000F +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_M ((SPI_MEM_NAND_FLASH_ADDR_INDEX0_V)<<(SPI_MEM_NAND_FLASH_ADDR_INDEX0_S)) +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_V 0xF +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_S 6 +/* SPI_MEM_NAND_FLASH_DIN_INDEX0 : HRO ;bitpos:[5:2] ;default: 4'b0 ; */ +/*description: MSPI NAND FLASH config din_index at spi seq index $n. Use with SPI_MEM_NAND_FLA +SH_CFG_DATA.*/ +#define SPI_MEM_NAND_FLASH_DIN_INDEX0 0x0000000F +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_M ((SPI_MEM_NAND_FLASH_DIN_INDEX0_V)<<(SPI_MEM_NAND_FLASH_DIN_INDEX0_S)) +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_V 0xF +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_S 2 +/* SPI_MEM_NAND_FLASH_SR_CHK_EN0 : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: MSPI NAND FLASH config sr_chk_en at spi seq index $n. 1: enable 0: disable..*/ +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0 (BIT(1)) +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_M (BIT(1)) +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_V 0x1 +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_S 1 +/* SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: MSPI NAND FLASH config seq_tail_flg at spi seq index $n.1: The last index for se +quence. 0: Not the last index..*/ +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 (BIT(0)) +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_M (BIT(0)) +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V 0x1 +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S 0 -/** SPI_MEM_XTS_PLAIN_BASE_REG register - * The base address of the memory that stores plaintext in Manual Encryption - */ -#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300) -/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; - * This field is only used to generate include file in c case. This field is useless. - * Please do not use this field. - */ -#define SPI_XTS_PLAIN 0xFFFFFFFFU -#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) -#define SPI_XTS_PLAIN_V 0xFFFFFFFFU -#define SPI_XTS_PLAIN_S 0 +#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* SPI_MEM_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define SPI_MEM_XTS_PLAIN 0xFFFFFFFF +#define SPI_MEM_XTS_PLAIN_M ((SPI_MEM_XTS_PLAIN_V)<<(SPI_MEM_XTS_PLAIN_S)) +#define SPI_MEM_XTS_PLAIN_V 0xFFFFFFFF +#define SPI_MEM_XTS_PLAIN_S 0 -/** SPI_MEM_XTS_LINESIZE_REG register - * Manual Encryption Line-Size register - */ -#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340) -/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; - * This bits stores the line-size parameter which will be used in manual encryption - * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: - * 32-bytes, 2: 64-bytes, 3:reserved. - */ -#define SPI_XTS_LINESIZE 0x00000003U -#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) -#define SPI_XTS_LINESIZE_V 0x00000003U -#define SPI_XTS_LINESIZE_S 0 +#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* SPI_MEM_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define SPI_MEM_XTS_LINESIZE 0x00000003 +#define SPI_MEM_XTS_LINESIZE_M ((SPI_MEM_XTS_LINESIZE_V)<<(SPI_MEM_XTS_LINESIZE_S)) +#define SPI_MEM_XTS_LINESIZE_V 0x3 +#define SPI_MEM_XTS_LINESIZE_S 0 -/** SPI_MEM_XTS_DESTINATION_REG register - * Manual Encryption destination register - */ -#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344) -/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; - * This bit stores the destination parameter which will be used in manual encryption - * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - */ -#define SPI_XTS_DESTINATION (BIT(0)) -#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) -#define SPI_XTS_DESTINATION_V 0x00000001U -#define SPI_XTS_DESTINATION_S 0 +#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* SPI_MEM_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryptio +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define SPI_MEM_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_XTS_DESTINATION_M (BIT(0)) +#define SPI_MEM_XTS_DESTINATION_V 0x1 +#define SPI_MEM_XTS_DESTINATION_S 0 -/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348) -/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; - * This bits stores the physical-address parameter which will be used in manual - * encryption calculation. This value should aligned with byte number decided by - * line-size parameter. - */ -#define SPI_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) -#define SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_S 0 +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* SPI_MEM_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS 0x3FFFFFFF +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_XTS_PHYSICAL_ADDRESS_S)) +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFF +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_S 0 -/** SPI_MEM_XTS_TRIGGER_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c) -/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; - * Set this bit to trigger the process of manual encryption calculation. This action - * should only be asserted when manual encryption status is 0. After this action, - * manual encryption status becomes 1. After calculation is done, manual encryption - * status becomes 2. - */ -#define SPI_XTS_TRIGGER (BIT(0)) -#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) -#define SPI_XTS_TRIGGER_V 0x00000001U -#define SPI_XTS_TRIGGER_S 0 +#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* SPI_MEM_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryptio +n status becomes 2..*/ +#define SPI_MEM_XTS_TRIGGER (BIT(0)) +#define SPI_MEM_XTS_TRIGGER_M (BIT(0)) +#define SPI_MEM_XTS_TRIGGER_V 0x1 +#define SPI_MEM_XTS_TRIGGER_S 0 -/** SPI_MEM_XTS_RELEASE_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350) -/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; - * Set this bit to release encrypted result to mspi. This action should only be - * asserted when manual encryption status is 2. After this action, manual encryption - * status will become 3. - */ -#define SPI_XTS_RELEASE (BIT(0)) -#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) -#define SPI_XTS_RELEASE_V 0x00000001U -#define SPI_XTS_RELEASE_S 0 +#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* SPI_MEM_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define SPI_MEM_XTS_RELEASE (BIT(0)) +#define SPI_MEM_XTS_RELEASE_M (BIT(0)) +#define SPI_MEM_XTS_RELEASE_V 0x1 +#define SPI_MEM_XTS_RELEASE_S 0 -/** SPI_MEM_XTS_DESTROY_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354) -/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; - * Set this bit to destroy encrypted result. This action should be asserted only when - * manual encryption status is 3. After this action, manual encryption status will - * become 0. - */ -#define SPI_XTS_DESTROY (BIT(0)) -#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) -#define SPI_XTS_DESTROY_V 0x00000001U -#define SPI_XTS_DESTROY_S 0 +#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* SPI_MEM_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define SPI_MEM_XTS_DESTROY (BIT(0)) +#define SPI_MEM_XTS_DESTROY_M (BIT(0)) +#define SPI_MEM_XTS_DESTROY_V 0x1 +#define SPI_MEM_XTS_DESTROY_S 0 -/** SPI_MEM_XTS_STATE_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358) -/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; - * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - * calculation, 2: encryption calculation is done but the encrypted result is - * invisible to mspi, 3: the encrypted result is visible to mspi. - */ -#define SPI_XTS_STATE 0x00000003U -#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) -#define SPI_XTS_STATE_V 0x00000003U -#define SPI_XTS_STATE_S 0 +#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* SPI_MEM_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define SPI_MEM_XTS_STATE 0x00000003 +#define SPI_MEM_XTS_STATE_M ((SPI_MEM_XTS_STATE_V)<<(SPI_MEM_XTS_STATE_S)) +#define SPI_MEM_XTS_STATE_V 0x3 +#define SPI_MEM_XTS_STATE_S 0 -/** SPI_MEM_XTS_DATE_REG register - * Manual Encryption version register - */ -#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c) -/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; - * This bits stores the last modified-time of manual encryption feature. - */ -#define SPI_XTS_DATE 0x3FFFFFFFU -#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) -#define SPI_XTS_DATE_V 0x3FFFFFFFU -#define SPI_XTS_DATE_S 0 +#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* SPI_MEM_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20210907 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define SPI_MEM_XTS_DATE 0x3FFFFFFF +#define SPI_MEM_XTS_DATE_M ((SPI_MEM_XTS_DATE_V)<<(SPI_MEM_XTS_DATE_S)) +#define SPI_MEM_XTS_DATE_V 0x3FFFFFFF +#define SPI_MEM_XTS_DATE_S 0 -/** SPI_MEM_MMU_ITEM_CONTENT_REG register - * MSPI-MMU item content register - */ -#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c) -/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; - * MSPI-MMU item content - */ -#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) -#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_S 0 +#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C) +/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: MSPI-MMU item content.*/ +#define SPI_MEM_MMU_ITEM_CONTENT 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_CONTENT_M ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S)) +#define SPI_MEM_MMU_ITEM_CONTENT_V 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_CONTENT_S 0 -/** SPI_MEM_MMU_ITEM_INDEX_REG register - * MSPI-MMU item index register - */ -#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380) -/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; - * MSPI-MMU item index - */ -#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) -#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_S 0 +#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) +/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: MSPI-MMU item index.*/ +#define SPI_MEM_MMU_ITEM_INDEX 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_INDEX_M ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S)) +#define SPI_MEM_MMU_ITEM_INDEX_V 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_INDEX_S 0 -/** SPI_MEM_MMU_POWER_CTRL_REG register - * MSPI MMU power control register - */ -#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384) -/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; - * Set this bit to enable mmu-memory clock force on - */ -#define SPI_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) -#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U -#define SPI_MMU_MEM_FORCE_ON_S 0 -/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 1; - * Set this bit to force mmu-memory powerdown - */ -#define SPI_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) -#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PD_S 1 -/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Set this bit to force mmu-memory powerup, in this case, the power should also be - * controlled by rtc. - */ -#define SPI_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) -#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PU_S 2 -/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; - * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 - */ -#define SPI_MMU_PAGE_SIZE 0x00000003U -#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) -#define SPI_MMU_PAGE_SIZE_V 0x00000003U -#define SPI_MMU_PAGE_SIZE_S 3 -/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; - * MMU PSRAM aux control register - */ -#define SPI_MEM_AUX_CTRL 0x00003FFFU -#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) -#define SPI_MEM_AUX_CTRL_V 0x00003FFFU -#define SPI_MEM_AUX_CTRL_S 16 -/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; - * ECO register enable bit - */ -#define SPI_MEM_RDN_ENA (BIT(30)) -#define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) -#define SPI_MEM_RDN_ENA_V 0x00000001U -#define SPI_MEM_RDN_ENA_S 30 -/** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; - * MSPI module clock domain and AXI clock domain ECO register result register - */ +#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) +/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/ #define SPI_MEM_RDN_RESULT (BIT(31)) -#define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) -#define SPI_MEM_RDN_RESULT_V 0x00000001U +#define SPI_MEM_RDN_RESULT_M (BIT(31)) +#define SPI_MEM_RDN_RESULT_V 0x1 #define SPI_MEM_RDN_RESULT_S 31 +/* SPI_MEM_RDN_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: ECO register enable bit.*/ +#define SPI_MEM_RDN_ENA (BIT(30)) +#define SPI_MEM_RDN_ENA_M (BIT(30)) +#define SPI_MEM_RDN_ENA_V 0x1 +#define SPI_MEM_RDN_ENA_S 30 +/* SPI_MEM_AUX_CTRL : R/W ;bitpos:[29:16] ;default: 14'h1320 ; */ +/*description: MMU PSRAM aux control register.*/ +#define SPI_MEM_AUX_CTRL 0x00003FFF +#define SPI_MEM_AUX_CTRL_M ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S)) +#define SPI_MEM_AUX_CTRL_V 0x3FFF +#define SPI_MEM_AUX_CTRL_S 16 +/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/ +#define SPI_MEM_MMU_PAGE_SIZE 0x00000003 +#define SPI_MEM_MMU_PAGE_SIZE_M ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S)) +#define SPI_MEM_MMU_PAGE_SIZE_V 0x3 +#define SPI_MEM_MMU_PAGE_SIZE_S 3 +/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be + controlled by rtc..*/ +#define SPI_MEM_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_MMU_MEM_FORCE_PU_M (BIT(2)) +#define SPI_MEM_MMU_MEM_FORCE_PU_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_PU_S 2 +/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit to force mmu-memory powerdown.*/ +#define SPI_MEM_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_MMU_MEM_FORCE_PD_M (BIT(1)) +#define SPI_MEM_MMU_MEM_FORCE_PD_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_PD_S 1 +/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable mmu-memory clock force on.*/ +#define SPI_MEM_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_MMU_MEM_FORCE_ON_M (BIT(0)) +#define SPI_MEM_MMU_MEM_FORCE_ON_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_ON_S 0 -/** SPI_MEM_DPA_CTRL_REG register - * SPI memory cryption DPA register - */ -#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388) -/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: - * The bigger the number is, the more secure the cryption is. (Note that the - * performance of cryption will decrease together with this number increasing) - */ -#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) -#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_S 0 -/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the - * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that - * using key 1. - */ -#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) -#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U -#define SPI_CRYPT_CALC_D_DPA_EN_S 3 -/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - */ -#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) -#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U -#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 +#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* SPI_MEM_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_S 4 +/* SPI_MEM_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define SPI_MEM_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_V 0x1 +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_S 3 +/* SPI_MEM_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define SPI_MEM_CRYPT_SECURITY_LEVEL 0x00000007 +#define SPI_MEM_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_CRYPT_SECURITY_LEVEL_S)) +#define SPI_MEM_CRYPT_SECURITY_LEVEL_V 0x7 +#define SPI_MEM_CRYPT_SECURITY_LEVEL_S 0 -/** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register - * SPI memory cryption PSEUDO register - */ -#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_SPI_BASE + 0x38c) -/** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; - * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo - * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. - * 2'b11: crypto with pseudo. - */ -#define SPI_MEM_MODE_PSEUDO 0x00000003U -#define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) -#define SPI_MEM_MODE_PSEUDO_V 0x00000003U -#define SPI_MEM_MODE_PSEUDO_S 0 -/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; - * xts aes peseudo function base round that must be peformed. - */ -#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U -#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) -#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U -#define SPI_MEM_PSEUDO_RNG_CNT_S 2 -/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; - * xts aes peseudo function base round that must be peformed. - */ -#define SPI_MEM_PSEUDO_BASE 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) -#define SPI_MEM_PSEUDO_BASE_V 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_S 5 -/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; - * xts aes peseudo function increment round that will be peformed randomly between 0 & - * 2**(inc+1). - */ -#define SPI_MEM_PSEUDO_INC 0x00000003U -#define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) -#define SPI_MEM_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(i) (REG_SPI_MEM_BASE(i) + 0x38C) +/* SPI_MEM_PSEUDO_INC : R/W ;bitpos:[10:9] ;default: 2'd2 ; */ +/*description: xts aes peseudo function increment round that will be peformed randomly between +0 & 2**(inc+1)..*/ +#define SPI_MEM_PSEUDO_INC 0x00000003 +#define SPI_MEM_PSEUDO_INC_M ((SPI_MEM_PSEUDO_INC_V)<<(SPI_MEM_PSEUDO_INC_S)) +#define SPI_MEM_PSEUDO_INC_V 0x3 #define SPI_MEM_PSEUDO_INC_S 9 +/* SPI_MEM_PSEUDO_BASE : R/W ;bitpos:[8:5] ;default: 4'd2 ; */ +/*description: xts aes peseudo function base round that must be peformed..*/ +#define SPI_MEM_PSEUDO_BASE 0x0000000F +#define SPI_MEM_PSEUDO_BASE_M ((SPI_MEM_PSEUDO_BASE_V)<<(SPI_MEM_PSEUDO_BASE_S)) +#define SPI_MEM_PSEUDO_BASE_V 0xF +#define SPI_MEM_PSEUDO_BASE_S 5 +/* SPI_MEM_PSEUDO_RNG_CNT : R/W ;bitpos:[4:2] ;default: 3'd7 ; */ +/*description: xts aes peseudo function base round that must be peformed..*/ +#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007 +#define SPI_MEM_PSEUDO_RNG_CNT_M ((SPI_MEM_PSEUDO_RNG_CNT_V)<<(SPI_MEM_PSEUDO_RNG_CNT_S)) +#define SPI_MEM_PSEUDO_RNG_CNT_V 0x7 +#define SPI_MEM_PSEUDO_RNG_CNT_S 2 +/* SPI_MEM_MODE_PSEUDO : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ +/*description: Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + and state D without pseudo. 2'b10: state T with pseudo and state D with few pse +udo. 2'b11: crypto with pseudo..*/ +#define SPI_MEM_MODE_PSEUDO 0x00000003 +#define SPI_MEM_MODE_PSEUDO_M ((SPI_MEM_MODE_PSEUDO_V)<<(SPI_MEM_MODE_PSEUDO_S)) +#define SPI_MEM_MODE_PSEUDO_V 0x3 +#define SPI_MEM_MODE_PSEUDO_S 0 -/** SPI_MEM_REGISTERRND_ECO_HIGH_REG register - * MSPI ECO high register - */ -#define SPI_MEM_REGISTERRND_ECO_HIGH_REG (DR_REG_SPI_BASE + 0x3f0) -/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; - * ECO high register - */ -#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_HIGH_M (SPI_MEM_REGISTERRND_ECO_HIGH_V << SPI_MEM_REGISTERRND_ECO_HIGH_S) -#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0) +/* SPI_MEM_REGISTERRND_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO high register.*/ +#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S)) +#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF #define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 -/** SPI_MEM_REGISTERRND_ECO_LOW_REG register - * MSPI ECO low register - */ -#define SPI_MEM_REGISTERRND_ECO_LOW_REG (DR_REG_SPI_BASE + 0x3f4) -/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; - * ECO low register - */ -#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_LOW_M (SPI_MEM_REGISTERRND_ECO_LOW_V << SPI_MEM_REGISTERRND_ECO_LOW_S) -#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F4) +/* SPI_MEM_REGISTERRND_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO low register.*/ +#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_M ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S)) +#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF #define SPI_MEM_REGISTERRND_ECO_LOW_S 0 -/** SPI_MEM_DATE_REG register - * SPI0 version control register - */ -#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37753200; - * SPI0 register version. - */ -#define SPI_MEM_DATE 0x0FFFFFFFU -#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) -#define SPI_MEM_DATE_V 0x0FFFFFFFU +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2401170 ; */ +/*description: SPI0 register version..*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF #define SPI_MEM_DATE_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c61/include/soc/spi_mem_struct.h b/components/soc/esp32c61/include/soc/spi_mem_struct.h index 43766b272a..28698a7dfb 100644 --- a/components/soc/esp32c61/include/soc/spi_mem_struct.h +++ b/components/soc/esp32c61/include/soc/spi_mem_struct.h @@ -5,2918 +5,1253 @@ */ #pragma once -#include #ifdef __cplusplus extern "C" { #endif - -/** Group: Status and state control register */ -/** Type of mem_cmd register - * SPI0 FSM status register - */ -typedef union { - struct { - /** mem_mst_st : RO; bitpos: [3:0]; default: 0; - * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , - * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent - * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - */ - uint32_t mem_mst_st:4; - /** mem_slv_st : RO; bitpos: [7:4]; default: 0; - * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, - * 2: send command state, 3: send address state, 4: wait state, 5: read data state, - * 6:write data state, 7: done state, 8: read data end state. - */ - uint32_t mem_slv_st:4; - uint32_t reserved_8:10; - /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - uint32_t mem_usr:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} spi_mem_cmd_reg_t; - -/** Type of mem_axi_err_addr register - * SPI0 AXI request error address. - */ -typedef union { - struct { - /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - */ - uint32_t mem_axi_err_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_axi_err_addr_reg_t; - - -/** Group: Flash Control and configuration registers */ -/** Type of mem_ctrl register - * SPI0 control register. - */ -typedef union { - struct { - /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_DQS is output by the MSPI controller. - */ - uint32_t mem_wdummy_dqs_always_out:1; - /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_IO[7:0] is output by the MSPI controller. - */ - uint32_t mem_wdummy_always_out:1; - /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; - * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the first half part of dummy phase. It is used to - * mask invalid SPI_DQS in the half part of dummy phase. - */ - uint32_t mem_fdummy_rin:1; - /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; - * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the second half part of dummy phase. It is used to - * pre-drive flash. - */ - uint32_t mem_fdummy_wout:1; - /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; - * Apply 8 signals during write-data phase 1:enable 0: disable - */ - uint32_t mem_fdout_oct:1; - /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; - * Apply 8 signals during read-data phase 1:enable 0: disable - */ - uint32_t mem_fdin_oct:1; - /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; - * Apply 8 signals during address phase 1:enable 0: disable - */ - uint32_t mem_faddr_oct:1; - uint32_t reserved_7:1; - /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable - */ - uint32_t mem_fcmd_quad:1; - /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable - */ - uint32_t mem_fcmd_oct:1; - uint32_t reserved_10:3; - /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - */ - uint32_t mem_fastrd_mode:1; - /** mem_fread_dual : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - */ - uint32_t mem_fread_dual:1; - uint32_t reserved_15:3; - /** mem_q_pol : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low - */ - uint32_t mem_q_pol:1; - /** mem_d_pol : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low - */ - uint32_t mem_d_pol:1; - /** mem_fread_quad : R/W; bitpos: [20]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - */ - uint32_t mem_fread_quad:1; - /** mem_wp_reg : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. - */ - uint32_t mem_wp_reg:1; - uint32_t reserved_22:1; - /** mem_fread_dio : R/W; bitpos: [23]; default: 0; - * In the read operations address phase and read-data phase apply 2 signals. 1: enable - * 0: disable. - */ - uint32_t mem_fread_dio:1; - /** mem_fread_qio : R/W; bitpos: [24]; default: 0; - * In the read operations address phase and read-data phase apply 4 signals. 1: enable - * 0: disable. - */ - uint32_t mem_fread_qio:1; - uint32_t reserved_25:5; - /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; - * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always - * 1. 0: Others. - */ - uint32_t mem_dqs_ie_always_on:1; - /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; - * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are - * always 1. 0: Others. - */ - uint32_t mem_data_ie_always_on:1; - }; - uint32_t val; -} spi_mem_ctrl_reg_t; - -/** Type of mem_ctrl1 register - * SPI0 control1 register. - */ -typedef union { - struct { - /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is alwasy on. - */ - uint32_t mem_clk_mode:2; - uint32_t reserved_2:19; - /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; - * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply - * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - */ - uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; - * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - */ - uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; - /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; - * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. - */ - uint32_t mem_rresp_ecc_err_en:1; - /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; - * Set this bit to enable AXI Read Splice-transfer. - */ - uint32_t mem_ar_splice_en:1; - /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; - * Set this bit to enable AXI Write Splice-transfer. - */ - uint32_t mem_aw_splice_en:1; - /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be - * accessed at the same time. - */ - uint32_t mem_ram0_en:1; - /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; - * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the - * same time. - */ - uint32_t mem_dual_ram_en:1; - /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; - * Set this bit to write data faster, do not wait write data has been stored in - * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored - * in tx_bus_fifo_l2. - */ - uint32_t mem_fast_write_en:1; - /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; - * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - * receive signals from AXI. Set this bit to reset these FIFO. - */ - uint32_t mem_rxfifo_rst:1; - /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; - * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - * send signals to AXI. Set this bit to reset these FIFO. - */ - uint32_t mem_txfifo_rst:1; - }; - uint32_t val; -} spi_mem_ctrl1_reg_t; - -/** Type of mem_ctrl2 register - * SPI0 control2 register. - */ -typedef union { - struct { - /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; - * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. - */ - uint32_t mem_cs_setup_time:5; - /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; - * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. - */ - uint32_t mem_cs_hold_time:5; - /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. - */ - uint32_t mem_ecc_cs_hold_time:3; - /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; - * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when - * accesses flash. - */ - uint32_t mem_ecc_skip_page_corner:1; - /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses flash. - */ - uint32_t mem_ecc_16to18_byte_en:1; - uint32_t reserved_15:9; - /** mem_split_trans_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI - * transfers when one transfer will cross flash or EXT_RAM page corner, valid no - * matter whether there is an ECC region or not. - */ - uint32_t mem_split_trans_en:1; - /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI - * core clock cycles. - */ - uint32_t mem_cs_hold_delay:6; - /** mem_sync_reset : WT; bitpos: [31]; default: 0; - * The spi0_mst_st and spi0_slv_st will be reset. - */ - uint32_t mem_sync_reset:1; - }; - uint32_t val; -} spi_mem_ctrl2_reg_t; - -/** Type of mem_misc register - * SPI0 misc register - */ -typedef union { - struct { - uint32_t reserved_0:7; - /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; - * For SPI0, flash is connected to SUBPINs. - */ - uint32_t mem_fsub_pin:1; - /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; - * For SPI0, sram is connected to SUBPINs. - */ - uint32_t mem_ssub_pin:1; - /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; - * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - */ - uint32_t mem_ck_idle_edge:1; - /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; - * SPI_CS line keep low when the bit is set. - */ - uint32_t mem_cs_keep_active:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_mem_misc_reg_t; - -/** Type of mem_cache_fctrl register - * SPI0 bit mode control register. - */ -typedef union { - struct { - /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; - * For SPI0, AXI master access enable, 1: enable, 0:disable. - */ - uint32_t mem_axi_req_en:1; - /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; - * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - */ - uint32_t mem_cache_usr_addr_4byte:1; - /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; - * For SPI0, cache read flash for user define command, 1: enable, 0:disable. - */ - uint32_t mem_cache_flash_usr_cmd:1; - /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; - * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - */ - uint32_t mem_fdin_dual:1; - /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; - * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - */ - uint32_t mem_fdout_dual:1; - /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; - * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_dio. - */ - uint32_t mem_faddr_dual:1; - /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; - * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - */ - uint32_t mem_fdin_quad:1; - /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; - * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - */ - uint32_t mem_fdout_quad:1; - /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; - * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_qio. - */ - uint32_t mem_faddr_quad:1; - uint32_t reserved_9:21; - /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; - * Set this bit to check AXI read/write the same address region. - */ - uint32_t same_aw_ar_addr_chk_en:1; - /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; - * Set this bit to close AXI read/write transfer to MSPI, which means that only - * SLV_ERR will be replied to BRESP/RRESP. - */ - uint32_t close_axi_inf_en:1; - }; - uint32_t val; -} spi_mem_cache_fctrl_reg_t; - -/** Type of mem_ddr register - * SPI0 flash DDR mode control register - */ -typedef union { - struct { - /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ - uint32_t fmem_ddr_en:1; - /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ - uint32_t fmem_var_dummy:1; - /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ - uint32_t fmem_ddr_rdat_swp:1; - /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ - uint32_t fmem_ddr_wdat_swp:1; - /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ - uint32_t fmem_ddr_cmd_dis:1; - /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the panda device. - */ - uint32_t fmem_outminbytelen:7; - /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to flash. - */ - uint32_t fmem_tx_ddr_msk_en:1; - /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to flash. - */ - uint32_t fmem_rx_ddr_msk_en:1; - /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ - uint32_t fmem_usr_ddr_dqs_thd:7; - /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ - uint32_t fmem_ddr_dqs_loop:1; - uint32_t reserved_22:2; - /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ - uint32_t fmem_clk_diff_en:1; - uint32_t reserved_25:1; - /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ - uint32_t fmem_dqs_ca_in:1; - /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ - uint32_t fmem_hyperbus_dummy_2x:1; - /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to flash. . - */ - uint32_t fmem_clk_diff_inv:1; - /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ - uint32_t fmem_octa_ram_addr:1; - /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ - uint32_t fmem_hyperbus_ca:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_mem_ddr_reg_t; - - -/** Group: Clock control and configuration registers */ -/** Type of mem_clock register - * SPI clock division control register. - */ -typedef union { - struct { - /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. - */ - uint32_t mem_clkcnt_l:8; - /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). - */ - uint32_t mem_clkcnt_h:8; - /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) - */ - uint32_t mem_clkcnt_n:8; - uint32_t reserved_24:7; - /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - * clock. - */ - uint32_t mem_clk_equ_sysclk:1; - }; - uint32_t val; -} spi_mem_clock_reg_t; - -/** Type of mem_sram_clk register - * SPI0 external RAM clock control register - */ -typedef union { - struct { - /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. - */ - uint32_t mem_sclkcnt_l:8; - /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). - */ - uint32_t mem_sclkcnt_h:8; - /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) - */ - uint32_t mem_sclkcnt_n:8; - uint32_t reserved_24:7; - /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk - * is divided from system clock. - */ - uint32_t mem_sclk_equ_sysclk:1; - }; - uint32_t val; -} spi_mem_sram_clk_reg_t; - -/** Type of mem_clock_gate register - * SPI0 clock gate register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Register clock gate enable signal. 1: Enable. 0: Disable. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_clock_gate_reg_t; - - -/** Group: Flash User-defined control registers */ -/** Type of mem_user register - * SPI0 user register. - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** mem_cs_hold : R/W; bitpos: [6]; default: 0; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ - uint32_t mem_cs_hold:1; - /** mem_cs_setup : R/W; bitpos: [7]; default: 0; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - */ - uint32_t mem_cs_setup:1; - uint32_t reserved_8:1; - /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - */ - uint32_t mem_ck_out_edge:1; - uint32_t reserved_10:16; - /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. - */ - uint32_t mem_usr_dummy_idle:1; - uint32_t reserved_27:2; - /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. - */ - uint32_t mem_usr_dummy:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_user_reg_t; - -/** Type of mem_user1 register - * SPI0 user1 register. - */ -typedef union { - struct { - /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). - */ - uint32_t mem_usr_dummy_cyclelen:6; - /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; - * SPI0 USR_CMD read or write data byte length -1 - */ - uint32_t mem_usr_dbytelen:6; - uint32_t reserved_12:14; - /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). - */ - uint32_t mem_usr_addr_bitlen:6; - }; - uint32_t val; -} spi_mem_user1_reg_t; - -/** Type of mem_user2 register - * SPI0 user2 register. - */ -typedef union { - struct { - /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; - * The value of command. - */ - uint32_t mem_usr_command_value:16; - uint32_t reserved_16:12; - /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1) - */ - uint32_t mem_usr_command_bitlen:4; - }; - uint32_t val; -} spi_mem_user2_reg_t; - -/** Type of mem_rd_status register - * SPI0 read control register. - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - */ - uint32_t mem_wb_mode:8; - /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; - * Mode bits length for flash fast read mode. - */ - uint32_t mem_wb_mode_bitlen:3; - /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; - * Mode bits is valid while this bit is enable. 1: enable 0: disable. - */ - uint32_t mem_wb_mode_en:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_rd_status_reg_t; - - -/** Group: External RAM Control and configuration registers */ -/** Type of mem_cache_sctrl register - * SPI0 external RAM control register - */ -typedef union { - struct { - /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; - * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: - * enable, 0:disable. - */ - uint32_t mem_cache_usr_saddr_4byte:1; - /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; - * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - */ - uint32_t mem_usr_sram_dio:1; - /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; - * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - */ - uint32_t mem_usr_sram_qio:1; - /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write - * operations. - */ - uint32_t mem_usr_wr_sram_dummy:1; - /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - * operations. - */ - uint32_t mem_usr_rd_sram_dummy:1; - /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; - * For SPI0, In the external RAM mode cache read external RAM for user define command. - */ - uint32_t mem_cache_sram_usr_rcmd:1; - /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. - * The register value shall be (bit_num-1). - */ - uint32_t mem_sram_rdummy_cyclelen:6; - uint32_t reserved_12:2; - /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; - * For SPI0, In the external RAM mode, it is the length in bits of address phase. The - * register value shall be (bit_num-1). - */ - uint32_t mem_sram_addr_bitlen:6; - /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; - * For SPI0, In the external RAM mode cache write sram for user define command - */ - uint32_t mem_cache_sram_usr_wcmd:1; - /** mem_sram_oct : R/W; bitpos: [21]; default: 0; - * reserved - */ - uint32_t mem_sram_oct:1; - /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. - * The register value shall be (bit_num-1). - */ - uint32_t mem_sram_wdummy_cyclelen:6; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_cache_sctrl_reg_t; - -/** Type of mem_sram_cmd register - * SPI0 external RAM mode control register - */ -typedef union { - struct { - /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - */ - uint32_t mem_sclk_mode:2; - /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; - * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_fastrd_mode bit. - */ - uint32_t mem_swb_mode:8; - /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; - * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_dio. - */ - uint32_t mem_sdin_dual:1; - /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; - * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_dio. - */ - uint32_t mem_sdout_dual:1; - /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; - * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_dio. - */ - uint32_t mem_saddr_dual:1; - uint32_t reserved_13:1; - /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; - * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - */ - uint32_t mem_sdin_quad:1; - /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; - * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_qio. - */ - uint32_t mem_sdout_quad:1; - /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_qio. - */ - uint32_t mem_saddr_quad:1; - /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; - * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - */ - uint32_t mem_scmd_quad:1; - /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; - * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - */ - uint32_t mem_sdin_oct:1; - /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; - * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - */ - uint32_t mem_sdout_oct:1; - /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - */ - uint32_t mem_saddr_oct:1; - /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; - * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - */ - uint32_t mem_scmd_oct:1; - /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; - * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - */ - uint32_t mem_sdummy_rin:1; - /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; - * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - */ - uint32_t mem_sdummy_wout:1; - /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_DQS is output by the MSPI controller. - */ - uint32_t smem_wdummy_dqs_always_out:1; - /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_IO[7:0] is output by the MSPI controller. - */ - uint32_t smem_wdummy_always_out:1; - /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; - * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - */ - uint32_t mem_sdin_hex:1; - /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; - * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - */ - uint32_t mem_sdout_hex:1; - uint32_t reserved_28:2; - /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are - * always 1. 0: Others. - */ - uint32_t smem_dqs_ie_always_on:1; - /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] - * are always 1. 0: Others. - */ - uint32_t smem_data_ie_always_on:1; - }; - uint32_t val; -} spi_mem_sram_cmd_reg_t; - -/** Type of mem_sram_drd_cmd register - * SPI0 external RAM DDR read command control register - */ -typedef union { - struct { - /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the read command value of command phase - * for sram. - */ - uint32_t mem_cache_sram_usr_rd_cmd_value:16; - uint32_t reserved_16:12; - /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the length in bits of command phase for - * sram. The register value shall be (bit_num-1). - */ - uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; - }; - uint32_t val; -} spi_mem_sram_drd_cmd_reg_t; - -/** Type of mem_sram_dwr_cmd register - * SPI0 external RAM DDR write command control register - */ -typedef union { - struct { - /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the write command value of command phase - * for sram. - */ - uint32_t mem_cache_sram_usr_wr_cmd_value:16; - uint32_t reserved_16:12; - /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the in bits of command phase for sram. - * The register value shall be (bit_num-1). - */ - uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; - }; - uint32_t val; -} spi_mem_sram_dwr_cmd_reg_t; - -/** Type of smem_ddr register - * SPI0 external RAM DDR mode control register - */ -typedef union { - struct { - /** smem_ddr_en : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ - uint32_t smem_ddr_en:1; - /** smem_var_dummy : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ - uint32_t smem_var_dummy:1; - /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ - uint32_t smem_ddr_rdat_swp:1; - /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ - uint32_t smem_ddr_wdat_swp:1; - /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ - uint32_t smem_ddr_cmd_dis:1; - /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the DDR psram. - */ - uint32_t smem_outminbytelen:7; - /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to external RAM. - */ - uint32_t smem_tx_ddr_msk_en:1; - /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to external RAM. - */ - uint32_t smem_rx_ddr_msk_en:1; - /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ - uint32_t smem_usr_ddr_dqs_thd:7; - /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ - uint32_t smem_ddr_dqs_loop:1; - uint32_t reserved_22:2; - /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ - uint32_t smem_clk_diff_en:1; - uint32_t reserved_25:1; - /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ - uint32_t smem_dqs_ca_in:1; - /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ - uint32_t smem_hyperbus_dummy_2x:1; - /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to external RAM. . - */ - uint32_t smem_clk_diff_inv:1; - /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], - * 1'b0}. - */ - uint32_t smem_octa_ram_addr:1; - /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ - uint32_t smem_hyperbus_ca:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_smem_ddr_reg_t; - -/** Type of smem_ac register - * MSPI external RAM ECC and SPI CS timing control register - */ -typedef union { - struct { - /** smem_cs_setup : R/W; bitpos: [0]; default: 0; - * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: - * disable. - */ - uint32_t smem_cs_setup:1; - /** smem_cs_hold : R/W; bitpos: [1]; default: 0; - * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ - uint32_t smem_cs_hold:1; - /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; - * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. - */ - uint32_t smem_cs_setup_time:5; - /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; - * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. - */ - uint32_t smem_cs_hold_time:5; - /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. - */ - uint32_t smem_ecc_cs_hold_time:3; - /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; - * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when - * accesses external RAM. - */ - uint32_t smem_ecc_skip_page_corner:1; - /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses external RAM. - */ - uint32_t smem_ecc_16to18_byte_en:1; - uint32_t reserved_17:8; - /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. - */ - uint32_t smem_cs_hold_delay:6; - /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; - * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter - * whether there is an ECC region or not. - */ - uint32_t smem_split_trans_en:1; - }; - uint32_t val; -} spi_smem_ac_reg_t; - - -/** Group: State control register */ -/** Type of mem_fsm register - * SPI0 FSM status register - */ -typedef union { - struct { - uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; - * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - */ - uint32_t mem_lock_delay_time:5; - /** mem_flash_lock_en : R/W; bitpos: [12]; default: 0; - * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. - */ - uint32_t mem_flash_lock_en:1; - /** mem_sram_lock_en : R/W; bitpos: [13]; default: 0; - * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. - */ - uint32_t mem_sram_lock_en:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} spi_mem_fsm_reg_t; - - -/** Group: Interrupt registers */ -/** Type of mem_int_ena register - * SPI0 interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_ena:1; - /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_ena:1; - /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_ena:1; - /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_ena:1; - /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_ena:1; - /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_ena:1; - /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_ena:1; - /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_ena:1; - /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_ena:1; - /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_ena:1; - }; - uint32_t val; -} spi_mem_int_ena_reg_t; - -/** Type of mem_int_clr register - * SPI0 interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_clr:1; - /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_clr:1; - /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_clr:1; - /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_clr:1; - /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_clr:1; - /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_clr:1; - /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_clr:1; - /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_clr:1; - /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_clr:1; - /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_clr:1; - }; - uint32_t val; -} spi_mem_int_clr_reg_t; - -/** Type of mem_int_raw register - * SPI0 interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: - * Others - */ - uint32_t mem_slv_st_end_int_raw:1; - /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. - */ - uint32_t mem_mst_st_end_int_raw:1; - /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. - */ - uint32_t mem_ecc_err_int_raw:1; - /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. - */ - uint32_t mem_pms_reject_int_raw:1; - /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read - * address is invalid by compared to MMU configuration. 0: Others. - */ - uint32_t mem_axi_raddr_err_int_raw:1; - /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. - */ - uint32_t mem_axi_wr_flash_err_int_raw:1; - /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - * address is invalid by compared to MMU configuration. 0: Others. - */ - uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS1 is overflow. - */ - uint32_t mem_dqs0_afifo_ovf_int_raw:1; - /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS is overflow. - */ - uint32_t mem_dqs1_afifo_ovf_int_raw:1; - /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. - */ - uint32_t mem_bus_fifo1_udf_int_raw:1; - /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. - */ - uint32_t mem_bus_fifo0_udf_int_raw:1; - }; - uint32_t val; -} spi_mem_int_raw_reg_t; - -/** Type of mem_int_st register - * SPI0 interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_st:1; - /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_st:1; - /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_st:1; - /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_st:1; - /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_st:1; - /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_st:1; - /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_st:1; - /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_st:1; - /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_st:1; - /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_st:1; - }; - uint32_t val; -} spi_mem_int_st_reg_t; - - -/** Group: PMS control and configuration registers */ -/** Type of fmem_pmsn_attr register - * MSPI flash PMS section n attribute register - */ -typedef union { - struct { - /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. - */ - uint32_t fmem_pmsn_rd_attr:1; - /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. - */ - uint32_t fmem_pmsn_wr_attr:1; - /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and - * SPI_FMEM_PMSn_SIZE_REG. - */ - uint32_t fmem_pmsn_ecc:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_fmem_pmsn_attr_reg_t; - -/** Type of fmem_pmsn_addr register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section n start address value - */ - uint32_t fmem_pmsn_addr_s:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_fmem_pmsn_addr_reg_t; - -/** Type of fmem_pmsn_size register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, - * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) - */ - uint32_t fmem_pmsn_size:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_fmem_pmsn_size_reg_t; - -/** Type of smem_pmsn_attr register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. - */ - uint32_t smem_pmsn_rd_attr:1; - /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. - */ - uint32_t smem_pmsn_wr_attr:1; - /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and - * SPI_SMEM_PMSn_SIZE_REG. - */ - uint32_t smem_pmsn_ecc:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_smem_pmsn_attr_reg_t; - -/** Type of smem_pmsn_addr register - * SPI1 external RAM PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section n start address value - */ - uint32_t smem_pmsn_addr_s:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_smem_pmsn_addr_reg_t; - -/** Type of smem_pmsn_size register - * SPI1 external RAM PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, - * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) - */ - uint32_t smem_pmsn_size:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_smem_pmsn_size_reg_t; - -/** Type of mem_pms_reject register - * SPI1 access reject register - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** mem_pm_en : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI0/1 transfer permission control function. - */ - uint32_t mem_pm_en:1; - /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; - * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_ld:1; - /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; - * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_st:1; - /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; - * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_multi_hit:1; - /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; - * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_ivd:1; - }; - uint32_t val; -} spi_mem_pms_reject_reg_t; - -/** Type of mem_pms_reject_addr register - * SPI1 access reject addr register - */ -typedef union { - struct { - /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_reject_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_pms_reject_addr_reg_t; - - -/** Group: MSPI ECC registers */ -/** Type of mem_ecc_ctrl register - * MSPI ECC control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; - * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - uint32_t mem_ecc_err_cnt:6; - /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t fmem_ecc_err_int_num:6; - /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - */ - uint32_t fmem_ecc_err_int_en:1; - /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; - * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: - * 1024 bytes. 3: 2048 bytes. - */ - uint32_t fmem_page_size:2; - uint32_t reserved_20:1; - /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit - * should be 0. Otherwise, this bit should be 1. - */ - uint32_t fmem_ecc_addr_en:1; - /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; - * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - */ - uint32_t mem_usr_ecc_addr_en:1; - uint32_t reserved_23:1; - /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - */ - uint32_t mem_ecc_continue_record_err_en:1; - /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; - * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to - * byte 0 bit 0 to byte 15 bit 7) - */ - uint32_t mem_ecc_err_bits:7; - }; - uint32_t val; -} spi_mem_ecc_ctrl_reg_t; - -/** Type of mem_ecc_err_addr register - * MSPI ECC error address register - */ -typedef union { - struct { - /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - uint32_t mem_ecc_err_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_ecc_err_addr_reg_t; - -/** Type of smem_ecc_ctrl register - * MSPI ECC control register - */ -typedef union { - struct { - uint32_t reserved_0:17; - /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to - * external RAM. - */ - uint32_t smem_ecc_err_int_en:1; - /** smem_page_size : R/W; bitpos: [19:18]; default: 2; - * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. - * 2: 1024 bytes. 3: 2048 bytes. - */ - uint32_t smem_page_size:2; - /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of external RAM. If there is no ECC region in external - * RAM, this bit should be 0. Otherwise, this bit should be 1. - */ - uint32_t smem_ecc_addr_en:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_smem_ecc_ctrl_reg_t; - - -/** Group: Status and state control registers */ -/** Type of smem_axi_addr_ctrl register - * SPI0 AXI address control register - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; - * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - * and SPI0 transfers are done. 0: Others. - */ - uint32_t mem_all_fifo_empty:1; - /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; - * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ - uint32_t rdata_afifo_rempty:1; - /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; - * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ - uint32_t raddr_afifo_rempty:1; - /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; - * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ - uint32_t wdata_afifo_rempty:1; - /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; - * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ - uint32_t wblen_afifo_rempty:1; - /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; - * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and - * RDATA_AFIFO are empty and spi0_mst_st is IDLE. - */ - uint32_t all_axi_trans_afifo_empty:1; - }; - uint32_t val; -} spi_smem_axi_addr_ctrl_reg_t; - -/** Type of mem_axi_err_resp_en register - * SPI0 AXI error response enable register - */ -typedef union { - struct { - /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_vld:1; - /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_gid:1; - /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_size:1; - /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; - * Set this bit to enable AXI response function for axi flash err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_flash:1; - /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_ecc:1; - /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; - * Set this bit to enable AXI response function for mmu sens in err axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_sens:1; - /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; - * Set this bit to enable AXI response function for axi wstrb err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_wstrb:1; - /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_vld:1; - /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_gid:1; - /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_ecc:1; - /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; - * Set this bit to enable AXI response function for mmu sensitive err in axi read - * trans. - */ - uint32_t mem_ar_resp_en_mmu_sens:1; - /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi read trans. - */ - uint32_t mem_ar_resp_en_axi_size:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} spi_mem_axi_err_resp_en_reg_t; - - -/** Group: Flash timing registers */ -/** Type of mem_timing_cali register - * SPI0 flash timing calibration register - */ -typedef union { - struct { - /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; - * The bit is used to enable timing adjust clock for all reading operations. - */ - uint32_t mem_timing_clk_ena:1; - /** mem_timing_cali : R/W; bitpos: [1]; default: 0; - * The bit is used to enable timing auto-calibration for all reading operations. - */ - uint32_t mem_timing_cali:1; - /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; - * add extra dummy spi clock cycle length for spi clock calibration. - */ - uint32_t mem_extra_dummy_cyclelen:3; - /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * flash. - */ - uint32_t mem_dll_timing_cali:1; - /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; - * Set this bit to update delay mode, delay num and extra dummy in MSPI. - */ - uint32_t mem_timing_cali_update:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} spi_mem_timing_cali_reg_t; - -/** Type of mem_din_mode register - * MSPI flash input timing delay mode control register - */ -typedef union { - struct { - /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din0_mode:3; - /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din1_mode:3; - /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din2_mode:3; - /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din3_mode:3; - /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din4_mode:3; - /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din5_mode:3; - /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din6_mode:3; - /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din7_mode:3; - /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_dins_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_mem_din_mode_reg_t; - -/** Type of mem_din_num register - * MSPI flash input timing delay number control register - */ -typedef union { - struct { - /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din0_num:2; - /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din1_num:2; - /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din2_num:2; - /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din3_num:2; - /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din4_num:2; - /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din5_num:2; - /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din6_num:2; - /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din7_num:2; - /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_dins_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_mem_din_num_reg_t; - -/** Type of mem_dout_mode register - * MSPI flash output timing adjustment control register - */ -typedef union { - struct { - /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout0_mode:1; - /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout1_mode:1; - /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout2_mode:1; - /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout3_mode:1; - /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout4_mode:1; - /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout5_mode:1; - /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout6_mode:1; - /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout7_mode:1; - /** mem_douts_mode : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_douts_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_mem_dout_mode_reg_t; - - -/** Group: External RAM timing registers */ -/** Type of smem_timing_cali register - * MSPI external RAM timing calibration register - */ -typedef union { - struct { - /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; - * For sram, the bit is used to enable timing adjust clock for all reading operations. - */ - uint32_t smem_timing_clk_ena:1; - /** smem_timing_cali : R/W; bitpos: [1]; default: 0; - * For sram, the bit is used to enable timing auto-calibration for all reading - * operations. - */ - uint32_t smem_timing_cali:1; - /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; - * For sram, add extra dummy spi clock cycle length for spi clock calibration. - */ - uint32_t smem_extra_dummy_cyclelen:3; - /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * EXT_RAM. - */ - uint32_t smem_dll_timing_cali:1; - uint32_t reserved_6:1; - /** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs0_270_sel:2; - /** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs0_90_sel:2; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_smem_timing_cali_reg_t; - -/** Type of smem_din_mode register - * MSPI external RAM input timing delay mode control register - */ -typedef union { - struct { - /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din0_mode:3; - /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din1_mode:3; - /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din2_mode:3; - /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din3_mode:3; - /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din4_mode:3; - /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din5_mode:3; - /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din6_mode:3; - /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din7_mode:3; - /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_dins_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_smem_din_mode_reg_t; - -/** Type of smem_din_num register - * MSPI external RAM input timing delay number control register - */ -typedef union { - struct { - /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din0_num:2; - /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din1_num:2; - /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din2_num:2; - /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din3_num:2; - /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din4_num:2; - /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din5_num:2; - /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din6_num:2; - /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din7_num:2; - /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_dins_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_smem_din_num_reg_t; - -/** Type of smem_dout_mode register - * MSPI external RAM output timing adjustment control register - */ -typedef union { - struct { - /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout0_mode:1; - /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout1_mode:1; - /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout2_mode:1; - /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout3_mode:1; - /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout4_mode:1; - /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout5_mode:1; - /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout6_mode:1; - /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout7_mode:1; - /** smem_douts_mode : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_douts_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_smem_dout_mode_reg_t; - -/** Type of smem_din_hex_mode register - * MSPI 16x external RAM input timing delay mode control register - */ -typedef union { - struct { - /** smem_din08_mode : HRO; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din08_mode:3; - /** smem_din09_mode : HRO; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din09_mode:3; - /** smem_din10_mode : HRO; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din10_mode:3; - /** smem_din11_mode : HRO; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din11_mode:3; - /** smem_din12_mode : HRO; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din12_mode:3; - /** smem_din13_mode : HRO; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din13_mode:3; - /** smem_din14_mode : HRO; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din14_mode:3; - /** smem_din15_mode : HRO; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din15_mode:3; - /** smem_dins_hex_mode : HRO; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_dins_hex_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_smem_din_hex_mode_reg_t; - -/** Type of smem_din_hex_num register - * MSPI 16x external RAM input timing delay number control register - */ -typedef union { - struct { - /** smem_din08_num : HRO; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din08_num:2; - /** smem_din09_num : HRO; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din09_num:2; - /** smem_din10_num : HRO; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din10_num:2; - /** smem_din11_num : HRO; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din11_num:2; - /** smem_din12_num : HRO; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din12_num:2; - /** smem_din13_num : HRO; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din13_num:2; - /** smem_din14_num : HRO; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din14_num:2; - /** smem_din15_num : HRO; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din15_num:2; - /** smem_dins_hex_num : HRO; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_dins_hex_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_smem_din_hex_num_reg_t; - -/** Type of smem_dout_hex_mode register - * MSPI 16x external RAM output timing adjustment control register - */ -typedef union { - struct { - /** smem_dout08_mode : HRO; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout08_mode:1; - /** smem_dout09_mode : HRO; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout09_mode:1; - /** smem_dout10_mode : HRO; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout10_mode:1; - /** smem_dout11_mode : HRO; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout11_mode:1; - /** smem_dout12_mode : HRO; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout12_mode:1; - /** smem_dout13_mode : HRO; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout13_mode:1; - /** smem_dout14_mode : HRO; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout14_mode:1; - /** smem_dout15_mode : HRO; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout15_mode:1; - /** smem_douts_hex_mode : HRO; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_douts_hex_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_smem_dout_hex_mode_reg_t; - - -/** Group: NAND FLASH control and status registers */ -/** Type of mem_nand_flash_en register - * NAND FLASH control register - */ -typedef union { - struct { - /** mem_nand_flash_en : HRO; bitpos: [0]; default: 0; - * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: - * Disable NAND FLASH, Enable NOR FLASH. - */ - uint32_t mem_nand_flash_en:1; - /** mem_nand_flash_seq_hd_index : HRO; bitpos: [15:1]; default: 32767; - * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st - * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. - */ - uint32_t mem_nand_flash_seq_hd_index:15; - /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. - */ - uint32_t mem_nand_flash_seq_usr_trig:1; - /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; - * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. - */ - uint32_t mem_nand_flash_lut_en:1; - /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; - * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and to - * excute page excute. 1: write end 0: write in a page size. - */ - uint32_t mem_nand_flash_seq_usr_wend:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} spi_mem_nand_flash_en_reg_t; - -/** Type of mem_nand_flash_sr_addr0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_sr_addr0 : HRO; bitpos: [7:0]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr0:8; - /** mem_nand_flash_sr_addr1 : HRO; bitpos: [15:8]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr1:8; - /** mem_nand_flash_sr_addr2 : HRO; bitpos: [23:16]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr2:8; - /** mem_nand_flash_sr_addr3 : HRO; bitpos: [31:24]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr3:8; - }; - uint32_t val; -} spi_mem_nand_flash_sr_addr0_reg_t; - -/** Type of mem_nand_flash_sr_din0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din0:8; - /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din1:8; - /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din2:8; - /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din3:8; - }; - uint32_t val; -} spi_mem_nand_flash_sr_din0_reg_t; - -/** Type of mem_nand_flash_cfg_data0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data0 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data0:16; - /** mem_nand_flash_cfg_data1 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data1:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data0_reg_t; - -/** Type of mem_nand_flash_cfg_data1 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data2 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data2:16; - /** mem_nand_flash_cfg_data3 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data3:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data1_reg_t; - -/** Type of mem_nand_flash_cfg_data2 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data4 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data4:16; - /** mem_nand_flash_cfg_data5 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data5:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data2_reg_t; - -/** Type of mem_nand_flash_cmd_lut0 register - * MSPI NAND FLASH CMD LUT control register - */ -typedef union { - struct { - /** mem_nand_flash_lut_cmd_value0 : HRO; bitpos: [15:0]; default: 0; - * MSPI NAND FLASH config cmd value at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_cmd_value0:16; - /** mem_nand_flash_lut_sfsm_st_en0 : HRO; bitpos: [19:16]; default: 0; - * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; - * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. - */ - uint32_t mem_nand_flash_lut_sfsm_st_en0:4; - /** mem_nand_flash_lut_cmd_len0 : HRO; bitpos: [23:20]; default: 0; - * MSPI NAND FLASH config cmd length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_cmd_len0:4; - /** mem_nand_flash_lut_addr_len0 : HRO; bitpos: [27:24]; default: 0; - * MSPI NAND FLASH config address length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_addr_len0:4; - /** mem_nand_flash_lut_data_len0 : HRO; bitpos: [29:28]; default: 0; - * MSPI NAND FLASH config data length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_data_len0:2; - /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; - * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode - * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's - * field. The number of CMD LUT entries can be defined by the user, but cannot exceed - * 16 ) - */ - uint32_t mem_nand_flash_lut_bus_en0:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_mem_nand_flash_cmd_lut0_reg_t; - -/** Type of mem_nand_flash_spi_seq0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_seq_tail_flg0 : HRO; bitpos: [0]; default: 0; - * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for - * sequence. 0: Not the last index. - */ - uint32_t mem_nand_flash_seq_tail_flg0:1; - /** mem_nand_flash_sr_chk_en0 : HRO; bitpos: [1]; default: 0; - * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. - */ - uint32_t mem_nand_flash_sr_chk_en0:1; - /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; - * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_CFG_DATA - */ - uint32_t mem_nand_flash_din_index0:4; - /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; - * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_SR_ADDR - */ - uint32_t mem_nand_flash_addr_index0:4; - /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; - * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI - * SEQ configuration. - */ - uint32_t mem_nand_flash_req_or_cfg0:1; - /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; - * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in - * CMD LUT.(Note these registers are described to indicate the - * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined - * by the user, but cannot exceed 16 ) - */ - uint32_t mem_nand_flash_cmd_index0:4; - uint32_t reserved_15:17; - }; - uint32_t val; -} spi_mem_nand_flash_spi_seq0_reg_t; - - -/** Group: Manual Encryption plaintext Memory */ -/** Type of mem_xts_plain_base register - * The base address of the memory that stores plaintext in Manual Encryption - */ -typedef union { - struct { - /** xts_plain : R/W; bitpos: [31:0]; default: 0; - * This field is only used to generate include file in c case. This field is useless. - * Please do not use this field. - */ - uint32_t xts_plain:32; - }; - uint32_t val; -} spi_mem_xts_plain_base_reg_t; - - -/** Group: Manual Encryption configuration registers */ -/** Type of mem_xts_linesize register - * Manual Encryption Line-Size register - */ -typedef union { - struct { - /** xts_linesize : R/W; bitpos: [1:0]; default: 0; - * This bits stores the line-size parameter which will be used in manual encryption - * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: - * 32-bytes, 2: 64-bytes, 3:reserved. - */ - uint32_t xts_linesize:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_xts_linesize_reg_t; - -/** Type of mem_xts_destination register - * Manual Encryption destination register - */ -typedef union { - struct { - /** xts_destination : R/W; bitpos: [0]; default: 0; - * This bit stores the destination parameter which will be used in manual encryption - * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - */ - uint32_t xts_destination:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_destination_reg_t; - -/** Type of mem_xts_physical_address register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; - * This bits stores the physical-address parameter which will be used in manual - * encryption calculation. This value should aligned with byte number decided by - * line-size parameter. - */ - uint32_t xts_physical_address:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_xts_physical_address_reg_t; - - -/** Group: Manual Encryption control and status registers */ -/** Type of mem_xts_trigger register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_trigger : WT; bitpos: [0]; default: 0; - * Set this bit to trigger the process of manual encryption calculation. This action - * should only be asserted when manual encryption status is 0. After this action, - * manual encryption status becomes 1. After calculation is done, manual encryption - * status becomes 2. - */ - uint32_t xts_trigger:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_trigger_reg_t; - -/** Type of mem_xts_release register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_release : WT; bitpos: [0]; default: 0; - * Set this bit to release encrypted result to mspi. This action should only be - * asserted when manual encryption status is 2. After this action, manual encryption - * status will become 3. - */ - uint32_t xts_release:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_release_reg_t; - -/** Type of mem_xts_destroy register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_destroy : WT; bitpos: [0]; default: 0; - * Set this bit to destroy encrypted result. This action should be asserted only when - * manual encryption status is 3. After this action, manual encryption status will - * become 0. - */ - uint32_t xts_destroy:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_destroy_reg_t; - -/** Type of mem_xts_state register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_state : RO; bitpos: [1:0]; default: 0; - * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - * calculation, 2: encryption calculation is done but the encrypted result is - * invisible to mspi, 3: the encrypted result is visible to mspi. - */ - uint32_t xts_state:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_xts_state_reg_t; - - -/** Group: Manual Encryption version control register */ -/** Type of mem_xts_date register - * Manual Encryption version register - */ -typedef union { - struct { - /** xts_date : R/W; bitpos: [29:0]; default: 539035911; - * This bits stores the last modified-time of manual encryption feature. - */ - uint32_t xts_date:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_xts_date_reg_t; - - -/** Group: MMU access registers */ -/** Type of mem_mmu_item_content register - * MSPI-MMU item content register - */ -typedef union { - struct { - /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; - * MSPI-MMU item content - */ - uint32_t mmu_item_content:32; - }; - uint32_t val; -} spi_mem_mmu_item_content_reg_t; - -/** Type of mem_mmu_item_index register - * MSPI-MMU item index register - */ -typedef union { - struct { - /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; - * MSPI-MMU item index - */ - uint32_t mmu_item_index:32; - }; - uint32_t val; -} spi_mem_mmu_item_index_reg_t; - - -/** Group: MMU power control and configuration registers */ -/** Type of mem_mmu_power_ctrl register - * MSPI MMU power control register - */ -typedef union { - struct { - /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; - * Set this bit to enable mmu-memory clock force on - */ - uint32_t mmu_mem_force_on:1; - /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 1; - * Set this bit to force mmu-memory powerdown - */ - uint32_t mmu_mem_force_pd:1; - /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force mmu-memory powerup, in this case, the power should also be - * controlled by rtc. - */ - uint32_t mmu_mem_force_pu:1; - /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; - * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 - */ - uint32_t mmu_page_size:2; - uint32_t reserved_5:11; - /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * MMU PSRAM aux control register - */ - uint32_t mem_aux_ctrl:14; - /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; - * ECO register enable bit - */ - uint32_t mem_rdn_ena:1; - /** mem_rdn_result : RO; bitpos: [31]; default: 0; - * MSPI module clock domain and AXI clock domain ECO register result register - */ - uint32_t mem_rdn_result:1; - }; - uint32_t val; -} spi_mem_mmu_power_ctrl_reg_t; - - -/** Group: External mem cryption DPA registers */ -/** Type of mem_dpa_ctrl register - * SPI memory cryption DPA register - */ -typedef union { - struct { - /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: - * The bigger the number is, the more secure the cryption is. (Note that the - * performance of cryption will decrease together with this number increasing) - */ - uint32_t crypt_security_level:3; - /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the - * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that - * using key 1. - */ - uint32_t crypt_calc_d_dpa_en:1; - /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - */ - uint32_t crypt_dpa_select_register:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} spi_mem_dpa_ctrl_reg_t; - - -/** Group: External mem cryption PSEUDO registers */ -/** Type of mem_xts_pseudo_round_conf register - * SPI memory cryption PSEUDO register - */ -typedef union { - struct { - /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; - * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo - * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. - * 2'b11: crypto with pseudo. - */ - uint32_t mem_mode_pseudo:2; - /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; - * xts aes peseudo function base round that must be peformed. - */ - uint32_t mem_pseudo_rng_cnt:3; - /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; - * xts aes peseudo function base round that must be peformed. - */ - uint32_t mem_pseudo_base:4; - /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; - * xts aes peseudo function increment round that will be peformed randomly between 0 & - * 2**(inc+1). - */ - uint32_t mem_pseudo_inc:2; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_mem_xts_pseudo_round_conf_reg_t; - - -/** Group: ECO registers */ -/** Type of mem_registerrnd_eco_high register - * MSPI ECO high register - */ -typedef union { - struct { - /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; - * ECO high register - */ - uint32_t mem_registerrnd_eco_high:32; - }; - uint32_t val; -} spi_mem_registerrnd_eco_high_reg_t; - -/** Type of mem_registerrnd_eco_low register - * MSPI ECO low register - */ -typedef union { - struct { - /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; - * ECO low register - */ - uint32_t mem_registerrnd_eco_low:32; - }; - uint32_t val; -} spi_mem_registerrnd_eco_low_reg_t; - - -/** Group: Version control register */ -/** Type of mem_date register - * SPI0 version control register - */ -typedef union { - struct { - /** mem_date : R/W; bitpos: [27:0]; default: 37753200; - * SPI0 register version. - */ - uint32_t mem_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_date_reg_t; - - -typedef struct { - volatile spi_mem_cmd_reg_t mem_cmd; - uint32_t reserved_004; - volatile spi_mem_ctrl_reg_t mem_ctrl; - volatile spi_mem_ctrl1_reg_t mem_ctrl1; - volatile spi_mem_ctrl2_reg_t mem_ctrl2; - volatile spi_mem_clock_reg_t mem_clock; - volatile spi_mem_user_reg_t mem_user; - volatile spi_mem_user1_reg_t mem_user1; - volatile spi_mem_user2_reg_t mem_user2; - uint32_t reserved_024[2]; - volatile spi_mem_rd_status_reg_t mem_rd_status; - uint32_t reserved_030; - volatile spi_mem_misc_reg_t mem_misc; - uint32_t reserved_038; - volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; - volatile spi_mem_cache_sctrl_reg_t mem_cache_sctrl; - volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; - volatile spi_mem_sram_drd_cmd_reg_t mem_sram_drd_cmd; - volatile spi_mem_sram_dwr_cmd_reg_t mem_sram_dwr_cmd; - volatile spi_mem_sram_clk_reg_t mem_sram_clk; - volatile spi_mem_fsm_reg_t mem_fsm; - uint32_t reserved_058[26]; - volatile spi_mem_int_ena_reg_t mem_int_ena; - volatile spi_mem_int_clr_reg_t mem_int_clr; - volatile spi_mem_int_raw_reg_t mem_int_raw; - volatile spi_mem_int_st_reg_t mem_int_st; - uint32_t reserved_0d0; - volatile spi_mem_ddr_reg_t mem_ddr; - volatile spi_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; - volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; - volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; - volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; - volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; - volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; - volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; - volatile spi_mem_pms_reject_reg_t mem_pms_reject; - volatile spi_mem_pms_reject_addr_reg_t mem_pms_reject_addr; - volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; - volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; - volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; - volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; - volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; - volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; - volatile spi_mem_timing_cali_reg_t mem_timing_cali; - volatile spi_mem_din_mode_reg_t mem_din_mode; - volatile spi_mem_din_num_reg_t mem_din_num; - volatile spi_mem_dout_mode_reg_t mem_dout_mode; - volatile spi_smem_timing_cali_reg_t smem_timing_cali; - volatile spi_smem_din_mode_reg_t smem_din_mode; - volatile spi_smem_din_num_reg_t smem_din_num; - volatile spi_smem_dout_mode_reg_t smem_dout_mode; - volatile spi_smem_ac_reg_t smem_ac; - volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode; - volatile spi_smem_din_hex_num_reg_t smem_din_hex_num; - volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode; - uint32_t reserved_1b0[20]; - volatile spi_mem_clock_gate_reg_t mem_clock_gate; - volatile spi_mem_nand_flash_en_reg_t mem_nand_flash_en; - volatile spi_mem_nand_flash_sr_addr0_reg_t mem_nand_flash_sr_addr0; - volatile spi_mem_nand_flash_sr_din0_reg_t mem_nand_flash_sr_din0; - volatile spi_mem_nand_flash_cfg_data0_reg_t mem_nand_flash_cfg_data0; - volatile spi_mem_nand_flash_cfg_data1_reg_t mem_nand_flash_cfg_data1; - volatile spi_mem_nand_flash_cfg_data2_reg_t mem_nand_flash_cfg_data2; - uint32_t reserved_21c[9]; - volatile spi_mem_nand_flash_cmd_lut0_reg_t mem_nand_flash_cmd_lut0; - uint32_t reserved_244[15]; - volatile spi_mem_nand_flash_spi_seq0_reg_t mem_nand_flash_spi_seq0; - uint32_t reserved_284[31]; - volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; - uint32_t reserved_304[15]; - volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; - volatile spi_mem_xts_destination_reg_t mem_xts_destination; - volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; - volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; - volatile spi_mem_xts_release_reg_t mem_xts_release; - volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; - volatile spi_mem_xts_state_reg_t mem_xts_state; - volatile spi_mem_xts_date_reg_t mem_xts_date; - uint32_t reserved_360[7]; - volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; - volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; - volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; - volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; - volatile spi_mem_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; - uint32_t reserved_390[24]; - volatile spi_mem_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; - volatile spi_mem_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; +#include "soc.h" + +// TODO: [ESP32C61] IDF-9314, This file comes from verification code +typedef volatile struct spi_mem_dev_s{ + union { + struct { + uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/ + uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/ + uint32_t reserved8 : 9; /*reserved*/ + uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */ + uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + }; + uint32_t val; + } cmd; + uint32_t addr; + union { + struct { + uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t fdummy_rin : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/ + uint32_t fdummy_wout : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/ + uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ + uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ + uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ + uint32_t reserved7 : 1; /*reserved*/ + uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12 : 1; /*reserved*/ + uint32_t fastrd_mode : 1; /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ + uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ + uint32_t reserved16 : 2; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/ + uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */ + uint32_t wrsr_2b : 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */ + uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t reserved25 : 5; /*reserved*/ + uint32_t dqs_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t data_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ + uint32_t reserved2 : 9; /*reserved*/ + uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_axi_rdata_back_fast : 1; /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/ + uint32_t rresp_ecc_err_en : 1; /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/ + uint32_t ar_splice_en : 1; /*Set this bit to enable AXI Read Splice-transfer.*/ + uint32_t aw_splice_en : 1; /*Set this bit to enable AXI Write Splice-transfer.*/ + uint32_t ram0_en : 1; /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t dual_ram_en : 1; /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t fast_write_en : 1; /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.*/ + uint32_t rxfifo_rst : 1; /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO.*/ + uint32_t txfifo_rst : 1; /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/ + uint32_t cs_hold_time : 5; /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/ + uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/ + uint32_t ecc_skip_page_corner : 1; /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ + uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ + uint32_t reserved15 : 9; /*reserved*/ + uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset : 1; /*The spi0_mst_st and spi0_slv_st will be reset.*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. */ + uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */ + uint32_t clk_equ_sysclk : 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reserved8 : 1; /*reserved*/ + uint32_t ck_out_edge : 1; /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t reserved16 : 8; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t usr_dbytelen : 6; /*SPI0 USR_CMD read or write data byte length -1*/ + uint32_t reserved12 : 14; /*reserved*/ + uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value : 16; /*The value of command.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_bit_len : 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + union { + struct { + uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ + uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t wb_mode_bitlen : 3; /*Mode bits length for flash fast read mode.*/ + uint32_t wb_mode_en : 1; /*Mode bits is valid while this bit is enable. 1: enable 0: disable.*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } rd_status; + uint32_t reserved_30; + union { + struct { + uint32_t cs0_dis : 1; /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t reserved0 : 5; /*reserved*/ + uint32_t fsub_pin : 1; /*For SPI0, flash is connected to SUBPINs.*/ + uint32_t ssub_pin : 1; /*For SPI0, sram is connected to SUBPINs.*/ + uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ + uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } misc; + uint32_t tx_crc; + union { + struct { + uint32_t axi_req_en : 1; /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/ + uint32_t usr_addr_4byte : 1; /*For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.*/ + uint32_t flash_usr_cmd : 1; /*For SPI0, cache read flash for user define command, 1: enable, 0:disable.*/ + uint32_t fdin_dual : 1; /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdout_dual : 1; /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t faddr_dual : 1; /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t fdout_quad : 1; /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t reserved9 : 21; /*reserved*/ + uint32_t reg_same_aw_ar_addr_chk_en : 1; /*Set this bit to check AXI read/write the same address region.*/ + uint32_t reg_close_axi_inf_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t usr_saddr_4byte : 1; /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/ + uint32_t usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_wr_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/ + uint32_t sram_usr_rcmd : 1; /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/ + uint32_t sram_rdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved12 : 2; /*reserved*/ + uint32_t sram_addr_bitlen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/ + uint32_t sram_oct : 1; /*reserved*/ + uint32_t sram_wdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ + uint32_t swb_mode : 8; /*Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t sdin_dual : 1; /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t sdout_dual : 1; /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t saddr_dual : 1; /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t reserved13 : 1; /*reserved*/ + uint32_t sdin_quad : 1; /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdout_quad : 1; /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t saddr_quad : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t scmd_quad : 1; /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdin_oct : 1; /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdout_oct : 1; /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */ + uint32_t saddr_oct : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */ + uint32_t scmd_oct : 1; /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdummy_rin : 1; /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t sdummy_wout : 1; /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t reg_smem_wdummy_dqs_always_out: 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t reg_smem_wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t sdin_hex : 1; /*For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. */ + uint32_t sdout_hex : 1; /*For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. */ + uint32_t reserved28 : 2; /*reserved*/ + uint32_t reg_smem_dqs_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t reg_smem_data_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t sram_usr_rd_cmd_value : 16; /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_rd_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t sram_usr_wr_cmd_value : 16; /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_wr_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t sclkcnt_l : 8; /*For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.*/ + uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t sclkcnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*reserved*/ + uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + }; + uint32_t val; + } sram_clk; + union { + struct { + uint32_t reserved0 : 7; /*reserved*/ + uint32_t lock_delay_time : 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/ + uint32_t flash_lock_en : 1; /*The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable.*/ + uint32_t sram_lock_en : 1; /*The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable.*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } fsm; + uint32_t data_buf[16]; + union { + struct { + uint32_t waiti_en : 1; /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/ + uint32_t waiti_dummy : 1; /*The dummy phase enable when wait flash idle (RDSR)*/ + uint32_t waiti_addr_en : 1; /*1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/ + uint32_t waiti_addr_cyclelen : 2; /*When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/ + uint32_t reserved5 : 4; /*reserved*/ + uint32_t waiti_cmd_2b : 1; /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/ + uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/ + uint32_t waiti_cmd : 16; /*The command value to wait flash idle(RDSR).*/ + }; + uint32_t val; + } flash_waiti_ctrl; + union { + struct { + uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_per_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */ + uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */ + uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/ + uint32_t flash_pes_en : 1; /*Set this bit to enable Auto-suspending function.*/ + uint32_t pesr_end_msk : 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ + uint32_t frd_sus_2b : 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ + uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ + uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ + uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/ + }; + uint32_t val; + } flash_sus_ctrl; + union { + struct { + uint32_t flash_pes_command : 16; /*Program/Erase suspend command.*/ + uint32_t wait_pesr_command : 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ + }; + uint32_t val; + } flash_sus_cmd; + union { + struct { + uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/ + uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/ + uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ + uint32_t flash_res_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ + uint32_t flash_dp_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ + uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ + uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ + uint32_t spi0_lock_en : 1; /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/ + uint32_t reserved8 : 7; /*reserved*/ + uint32_t flash_pesr_cmd_2b : 1; /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/ + uint32_t flash_per_command : 16; /*Program/Erase resume command.*/ + }; + uint32_t val; + } sus_status; + uint32_t reserved_a8; + union { + struct { + uint32_t reg_wait_idle_delay_time : 10; /*SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.*/ + uint32_t reg_wait_idle_delay_time_en : 1; /*Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } flash_waiti_ctrl1; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + union { + struct { + uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end_en : 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject_en : 1; /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err_en : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf_en : 1; /*The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ + uint32_t dqs1_afifo_ovf_en : 1; /*The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ + uint32_t bus_fifo1_udf_en : 1; /*The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ + uint32_t bus_fifo0_udf_en : 1; /*The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t per_end : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf : 1; /*The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ + uint32_t dqs1_afifo_ovf : 1; /*The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ + uint32_t bus_fifo1_udf : 1; /*The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ + uint32_t bus_fifo0_udf : 1; /*The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t per_end : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ + uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ + uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ + uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ + uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/ + uint32_t ecc_err : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ + uint32_t pms_reject : 1; /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/ + uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ + uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf : 1; /*The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow.*/ + uint32_t dqs1_afifo_ovf : 1; /*The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow.*/ + uint32_t bus_fifo1_udf : 1; /*The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow.*/ + uint32_t bus_fifo0_udf : 1; /*The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t per_end : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved10 : 17; /*reserved*/ + uint32_t dqs0_afifo_ovf : 1; /*The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ + uint32_t dqs1_afifo_ovf : 1; /*The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ + uint32_t bus_fifo1_udf : 1; /*The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ + uint32_t bus_fifo0_udf : 1; /*The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ + }; + uint32_t val; + } int_st; + uint32_t reserved_d0; + union { + struct { + uint32_t reg_fmem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t reg_fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t reg_fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t reg_fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t reg_fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t reg_fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ + uint32_t reg_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/ + uint32_t reg_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/ + uint32_t reg_fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t reg_fmem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t reg_fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t reg_fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t reg_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t reg_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ + uint32_t reg_fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t reg_fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } ddr; + union { + struct { + uint32_t reg_smem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t reg_smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t reg_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t reg_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t reg_smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t reg_smem_outminbytelen : 7; /*It is the minimum output data length in the DDR psram.*/ + uint32_t reg_smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/ + uint32_t reg_smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/ + uint32_t reg_smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t reg_smem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t reg_smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t reg_smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t reg_smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t reg_smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ + uint32_t reg_smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t reg_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } spi_smem_ddr; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + union { + struct { + uint32_t reg_fmem_pms0_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms0_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms0_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_attr; + union { + struct { + uint32_t reg_fmem_pms1_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms1_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms1_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_attr; + union { + struct { + uint32_t reg_fmem_pms2_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms2_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms2_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_attr; + union { + struct { + uint32_t reg_fmem_pms3_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms3_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms3_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_attr; + union { + struct { + uint32_t reg_fmem_pms0_addr_s : 29; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_addr; + union { + struct { + uint32_t reg_fmem_pms1_addr_s : 29; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_addr; + union { + struct { + uint32_t reg_fmem_pms2_addr_s : 29; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_addr; + union { + struct { + uint32_t reg_fmem_pms3_addr_s : 29; /*SPI1 flash PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_addr; + union { + struct { + uint32_t reg_fmem_pms0_size : 17; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_size; + union { + struct { + uint32_t reg_fmem_pms1_size : 17; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_size; + union { + struct { + uint32_t reg_fmem_pms2_size : 17; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_size; + union { + struct { + uint32_t reg_fmem_pms3_size : 17; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_size; + union { + struct { + uint32_t reg_smem_pms0_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms0_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms0_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_attr; + union { + struct { + uint32_t reg_smem_pms1_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms1_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms1_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_attr; + union { + struct { + uint32_t reg_smem_pms2_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms2_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms2_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_attr; + union { + struct { + uint32_t reg_smem_pms3_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms3_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms3_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_attr; + union { + struct { + uint32_t reg_smem_pms0_addr_s : 29; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_addr; + union { + struct { + uint32_t reg_smem_pms1_addr_s : 29; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_addr; + union { + struct { + uint32_t reg_smem_pms2_addr_s : 29; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_addr; + union { + struct { + uint32_t reg_smem_pms3_addr_s : 29; /*SPI1 external RAM PMS section $n start address value*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_addr; + union { + struct { + uint32_t reg_smem_pms0_size : 17; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_size; + union { + struct { + uint32_t reg_smem_pms1_size : 17; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_size; + union { + struct { + uint32_t reg_smem_pms2_size : 17; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_size; + union { + struct { + uint32_t reg_smem_pms3_size : 17; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved17 : 15; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_size; + union { + struct { + uint32_t reserved0 : 27; /*reserved*/ + uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/ + uint32_t pms_ld : 1; /*1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_st : 1; /*1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_multi_hit : 1; /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_ivd : 1; /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + }; + uint32_t val; + } pms_reject; + union { + struct { + uint32_t reject_addr : 29; /*This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } pms_reject_addr; + union { + struct { + uint32_t reserved0 : 5; /*reserved*/ + uint32_t ecc_err_cnt : 6; /*This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t reg_fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/ + uint32_t reg_fmem_page_size : 2; /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reserved20 : 1; /*reserved*/ + uint32_t reg_fmem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t usr_ecc_addr_en : 1; /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/ + uint32_t reserved23 : 1; /*reserved*/ + uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/ + uint32_t ecc_err_bits : 7; /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/ + }; + uint32_t val; + } ecc_ctrl; + union { + struct { + uint32_t ecc_err_addr : 29; /*This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } ecc_err_addr; + union { + struct { + uint32_t axi_err_addr : 29; /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } axi_err_addr; + union { + struct { + uint32_t reserved0 : 17; /*reserved*/ + uint32_t reg_smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/ + uint32_t reg_smem_page_size : 2; /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reg_smem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } spi_smem_ecc_ctrl; + union { + struct { + uint32_t reserved0 : 26; /*reserved*/ + uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/ + uint32_t reg_rdata_afifo_rempty : 1; /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_raddr_afifo_rempty : 1; /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_wdata_afifo_rempty : 1; /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_wblen_afifo_rempty : 1; /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_all_axi_trans_afifo_empty : 1; /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/ + }; + uint32_t val; + } spi_smem_axi_addr_ctrl; + union { + struct { + uint32_t aw_resp_en_mmu_vld : 1; /*Set this bit to enable AXI response function for mmu valid err in axi write trans. */ + uint32_t aw_resp_en_mmu_gid : 1; /*Set this bit to enable AXI response function for mmu gid err in axi write trans.*/ + uint32_t aw_resp_en_axi_size : 1; /*Set this bit to enable AXI response function for axi size err in axi write trans.*/ + uint32_t aw_resp_en_axi_flash : 1; /*Set this bit to enable AXI response function for axi flash err in axi write trans.*/ + uint32_t aw_resp_en_mmu_ecc : 1; /*Set this bit to enable AXI response function for mmu ecc err in axi write trans.*/ + uint32_t aw_resp_en_mmu_sens : 1; /*Set this bit to enable AXI response function for mmu sens in err axi write trans.*/ + uint32_t aw_resp_en_axi_wstrb : 1; /*Set this bit to enable AXI response function for axi wstrb err in axi write trans.*/ + uint32_t ar_resp_en_mmu_vld : 1; /*Set this bit to enable AXI response function for mmu valid err in axi read trans.*/ + uint32_t ar_resp_en_mmu_gid : 1; /*Set this bit to enable AXI response function for mmu gid err in axi read trans.*/ + uint32_t ar_resp_en_mmu_ecc : 1; /*Set this bit to enable AXI response function for mmu ecc err in axi read trans.*/ + uint32_t ar_resp_en_mmu_sens : 1; /*Set this bit to enable AXI response function for mmu sensitive err in axi read trans.*/ + uint32_t ar_resp_en_axi_size : 1; /*Set this bit to enable AXI response function for axi size err in axi read trans.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } axi_err_resp_en; + union { + struct { + uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/ + uint32_t timing_cali_update : 1; /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/ + uint32_t reserved7 : 25; /*reserved*/ + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } dout_mode; + union { + struct { + uint32_t reg_smem_timing_clk_ena : 1; /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t reg_smem_timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t reg_smem_extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reg_smem_dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/ + uint32_t reserved6 : 1; /*reserved*/ + uint32_t reg_smem_dqs0_270_sel : 2; /*Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. */ + uint32_t reg_smem_dqs0_90_sel : 2; /*Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } spi_smem_timing_cali; + union { + struct { + uint32_t reg_smem_din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_mode; + union { + struct { + uint32_t reg_smem_din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_num; + union { + struct { + uint32_t reg_smem_dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_mode; + union { + struct { + uint32_t reg_smem_cs_setup : 1; /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reg_smem_cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t reg_smem_cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t reg_smem_cs_hold_time : 5; /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t reg_smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/ + uint32_t reg_smem_ecc_skip_page_corner : 1; /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/ + uint32_t reg_smem_ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/ + uint32_t reserved17 : 8; /*reserved*/ + uint32_t reg_smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t reg_smem_split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + }; + uint32_t val; + } spi_smem_ac; + union { + struct { + uint32_t reg_smem_din08_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din09_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din10_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din11_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din12_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din13_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din14_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din15_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_dins_hex_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_hex_mode; + union { + struct { + uint32_t reg_smem_din08_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din09_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din10_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din11_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din12_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din13_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din14_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din15_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_dins_hex_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_hex_num; + union { + struct { + uint32_t reg_smem_dout08_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout09_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout10_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout11_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout12_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout13_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout14_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout15_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_douts_hex_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_hex_mode; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + union { + struct { + uint32_t reg_clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + union { + struct { + uint32_t reg_nand_flash_en : 1; /*NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: Disable NAND FLASH, Enable NOR FLASH.*/ + uint32_t reg_nand_flash_seq_hd_index : 15; /*NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. */ + uint32_t reg_nand_flash_seq_usr_trig : 1; /*NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. */ + uint32_t reg_nand_flash_lut_en : 1; /*NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. */ + uint32_t reg_nand_flash_seq_usr_wend : 1; /*Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and to excute page excute. 1: write end 0: write in a page size.*/ + uint32_t reserved19 : 13; /*reserved*/ + }; + uint32_t val; + } nand_flash_en; + union { + struct { + uint32_t reg_nand_flash_sr_addr0 : 8; /*configure state register address for SPI SEQ need. If OIP is in address C0H , user could configure C0H into this register*/ + uint32_t reg_nand_flash_sr_addr1 : 8; /*configure state register address for SPI SEQ need. If OIP is in address C0H , user could configure C0H into this register*/ + uint32_t reg_nand_flash_sr_addr2 : 8; /*configure state register address for SPI SEQ need. If OIP is in address C0H , user could configure C0H into this register*/ + uint32_t reg_nand_flash_sr_addr3 : 8; /*configure state register address for SPI SEQ need. If OIP is in address C0H , user could configure C0H into this register*/ + }; + uint32_t val; + } nand_flash_sr_addr0; + union { + struct { + uint32_t reg_nand_flash_sr_din0 : 8; /*spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ + uint32_t reg_nand_flash_sr_din1 : 8; /*spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ + uint32_t reg_nand_flash_sr_din2 : 8; /*spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ + uint32_t reg_nand_flash_sr_din3 : 8; /*spi read state register data to this register for SPI SEQ need. SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ + }; + uint32_t val; + } nand_flash_sr_din0; + union { + struct { + uint32_t reg_nand_flash_cfg_data0 : 16; /*configure data for SPI SEQ din/dout need. The data could be use to configure NAND FLASH or compare read data*/ + uint32_t reg_nand_flash_cfg_data1 : 16; /*configure data for SPI SEQ din/dout need. The data could be use to configure NAND FLASH or compare read data*/ + }; + uint32_t val; + } nand_flash_cfg_data0; + union { + struct { + uint32_t reg_nand_flash_cfg_data2 : 16; /*configure data for SPI SEQ din/dout need. The data could be use to configure NAND FLASH or compare read data*/ + uint32_t reg_nand_flash_cfg_data3 : 16; /*configure data for SPI SEQ din/dout need. The data could be use to configure NAND FLASH or compare read data*/ + }; + uint32_t val; + } nand_flash_cfg_data1; + union { + struct { + uint32_t reg_nand_flash_cfg_data4 : 16; /*configure data for SPI SEQ din/dout need. The data could be use to configure NAND FLASH or compare read data*/ + uint32_t reg_nand_flash_cfg_data5 : 16; /*configure data for SPI SEQ din/dout need. The data could be use to configure NAND FLASH or compare read data*/ + }; + uint32_t val; + } nand_flash_cfg_data2; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + union { + struct { + uint32_t reg_nand_flash_cmd_value0 : 16; /*MSPI NAND FLASH config cmd value at cmd lut address $n.*/ + uint32_t reg_nand_flash_sfsm_st_en0 : 4; /*MSPI NAND FLASH config sfsm_st_en at cmd lut address $n.[3]-ADDR period enable; [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period.*/ + uint32_t reg_nand_flash_cmd_len0 : 4; /*MSPI NAND FLASH config cmd length at cmd lut address $n.*/ + uint32_t reg_nand_flash_addr_len0 : 4; /*MSPI NAND FLASH config address length at cmd lut address $n.*/ + uint32_t reg_nand_flash_data_len0 : 2; /*MSPI NAND FLASH config data length at cmd lut address $n.*/ + uint32_t reg_nand_flash_spi_bus_en0 : 1; /*MSPI NAND FLASH config spi_bus_en at cmd lut address $n,SPI could use DUAL/QUAD mode while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT$n_REG's field. The number of CMD LUT entries can be defined by the user, but cannot exceed 16 )*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } nand_flash_cmd_lut0; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + union { + struct { + uint32_t reg_nand_flash_seq_tail_flg0 : 1; /*MSPI NAND FLASH config seq_tail_flg at spi seq index $n.1: The last index for sequence. 0: Not the last index. */ + uint32_t reg_nand_flash_sr_chk_en0 : 1; /*MSPI NAND FLASH config sr_chk_en at spi seq index $n. 1: enable 0: disable. */ + uint32_t reg_nand_flash_din_index0 : 4; /*MSPI NAND FLASH config din_index at spi seq index $n. Use with SPI_MEM_NAND_FLASH_CFG_DATA*/ + uint32_t reg_nand_flash_addr_index0 : 4; /*MSPI NAND FLASH config addr_index at spi seq index $n. Use with SPI_MEM_NAND_FLASH_SR_ADDR*/ + uint32_t reg_nand_flash_req_or_cfg0 : 1; /*MSPI NAND FLASH config reg_or_cfg at spi seq index $n. 1: AXI/APB request 0: SPI SEQ configuration. */ + uint32_t reg_nand_flash_spi_cmd_index0 : 4; /*MSPI NAND FLASH config spi_cmd_index at spi seq index $n. Use to find SPI command in CMD LUT.(Note these registers are described to indicate the SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined by the user, but cannot exceed 16 )*/ + uint32_t reserved15 : 17; /*reserved*/ + }; + uint32_t val; + } nand_flash_spi_seq0; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t xts_plain_base; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + union { + struct { + uint32_t reg_xts_linesize : 2; /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_linesize; + union { + struct { + uint32_t reg_xts_destination : 1; /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destination; + union { + struct { + uint32_t reg_xts_physical_address : 30; /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/ + uint32_t reserved30 : 2; /*reserved*/ + }; + uint32_t val; + } xts_physical_address; + union { + struct { + uint32_t reg_xts_trigger : 1; /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_trigger; + union { + struct { + uint32_t reg_xts_release : 1; /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_release; + union { + struct { + uint32_t reg_xts_destroy : 1; /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destroy; + union { + struct { + uint32_t reg_xts_state : 2; /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_state; + union { + struct { + uint32_t reg_xts_date : 30; /*This bits stores the last modified-time of manual encryption feature.*/ + uint32_t reserved30 : 2; /*reserved*/ + }; + uint32_t val; + } xts_date; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t mmu_item_content; + uint32_t mmu_item_index; + union { + struct { + uint32_t reg_mmu_mem_force_on : 1; /*Set this bit to enable mmu-memory clock force on*/ + uint32_t reg_mmu_mem_force_pd : 1; /*Set this bit to force mmu-memory powerdown*/ + uint32_t reg_mmu_mem_force_pu : 1; /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/ + uint32_t reg_mmu_page_size : 2; /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/ + uint32_t reserved5 : 11; /*reserved*/ + uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/ + uint32_t rdn_ena : 1; /*ECO register enable bit*/ + uint32_t rdn_result : 1; /*MSPI module clock domain and AXI clock domain ECO register result register*/ + }; + uint32_t val; + } mmu_power_ctrl; + union { + struct { + uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ + uint32_t reg_crypt_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ + uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } dpa_ctrl; + union { + struct { + uint32_t reg_mode_pseudo : 2; /*Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. 2'b11: crypto with pseudo.*/ + uint32_t reg_pseudo_rng_cnt : 3; /*xts aes peseudo function base round that must be peformed.*/ + uint32_t reg_pseudo_base : 4; /*xts aes peseudo function base round that must be peformed.*/ + uint32_t reg_pseudo_inc : 2; /*xts aes peseudo function increment round that will be peformed randomly between 0 & 2**(inc+1).*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } xts_pseudo_round_conf; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t spi_memisterrnd_eco_high; + uint32_t spi_memisterrnd_eco_low; uint32_t reserved_3f8; - volatile spi_mem_date_reg_t mem_date; + union { + struct { + uint32_t date : 28; /*SPI0 register version.*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } date; } spi_mem_dev_t; extern spi_mem_dev_t SPIMEM0; extern spi_mem_dev_t SPIMEM1; -#ifndef __cplusplus -_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure"); -#endif - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c61/include/soc/spi_pins.h b/components/soc/esp32c61/include/soc/spi_pins.h new file mode 100644 index 0000000000..270f2ad395 --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi_pins.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_SPI_PINS_H_ +#define _SOC_SPI_PINS_H_ + +#define SPI_FUNC_NUM 0 +#define SPI_IOMUX_PIN_NUM_CS 24 +#define SPI_IOMUX_PIN_NUM_CLK 29 +#define SPI_IOMUX_PIN_NUM_MOSI 30 +#define SPI_IOMUX_PIN_NUM_MISO 25 +#define SPI_IOMUX_PIN_NUM_WP 26 +#define SPI_IOMUX_PIN_NUM_HD 28 + +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 16 + +#endif diff --git a/components/soc/esp32c61/include/soc/spi_struct.h b/components/soc/esp32c61/include/soc/spi_struct.h index f84df62b84..7b84c9d658 100644 --- a/components/soc/esp32c61/include/soc/spi_struct.h +++ b/components/soc/esp32c61/include/soc/spi_struct.h @@ -1084,90 +1084,90 @@ typedef union { */ typedef union { struct { - /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + /** dma_infifo_full_err : R/W; bitpos: [0]; default: 0; * Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - uint32_t dma_infifo_full_err_int_ena:1; - /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0; * Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - uint32_t dma_outfifo_empty_err_int_ena:1; - /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : R/W; bitpos: [2]; default: 0; * Write 1 to enable SPI_SLV_EX_QPI_INT interrupt. */ - uint32_t slv_ex_qpi_int_ena:1; - /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : R/W; bitpos: [3]; default: 0; * Write 1 to enable SPI_SLV_EN_QPI_INT interrupt. */ - uint32_t slv_en_qpi_int_ena:1; - /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t slv_en_qpi:1; + /** slv_cmd7 : R/W; bitpos: [4]; default: 0; * Write 1 to enable SPI_SLV_CMD7_INT interrupt. */ - uint32_t slv_cmd7_int_ena:1; - /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + uint32_t slv_cmd7:1; + /** slv_cmd8 : R/W; bitpos: [5]; default: 0; * Write 1 to enable SPI_SLV_CMD8_INT interrupt. */ - uint32_t slv_cmd8_int_ena:1; - /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + uint32_t slv_cmd8:1; + /** slv_cmd9 : R/W; bitpos: [6]; default: 0; * Write 1 to enable SPI_SLV_CMD9_INT interrupt. */ - uint32_t slv_cmd9_int_ena:1; - /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + uint32_t slv_cmd9:1; + /** slv_cmda : R/W; bitpos: [7]; default: 0; * Write 1 to enable SPI_SLV_CMDA_INT interrupt. */ - uint32_t slv_cmda_int_ena:1; - /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + uint32_t slv_cmda:1; + /** slv_rd_dma_done : R/W; bitpos: [8]; default: 0; * Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt. */ - uint32_t slv_rd_dma_done_int_ena:1; - /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : R/W; bitpos: [9]; default: 0; * Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt. */ - uint32_t slv_wr_dma_done_int_ena:1; - /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : R/W; bitpos: [10]; default: 0; * Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt. */ - uint32_t slv_rd_buf_done_int_ena:1; - /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : R/W; bitpos: [11]; default: 0; * Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt. */ - uint32_t slv_wr_buf_done_int_ena:1; - /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + uint32_t slv_wr_buf_done:1; + /** trans_done : R/W; bitpos: [12]; default: 0; * Write 1 to enable SPI_TRANS_DONE_INT interrupt. */ - uint32_t trans_done_int_ena:1; - /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + uint32_t trans_done:1; + /** dma_seg_trans_done : R/W; bitpos: [13]; default: 0; * Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t dma_seg_trans_done_int_ena:1; - /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : R/W; bitpos: [14]; default: 0; * Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt. */ - uint32_t seg_magic_err_int_ena:1; - /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : R/W; bitpos: [15]; default: 0; * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - uint32_t slv_buf_addr_err_int_ena:1; - /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : R/W; bitpos: [16]; default: 0; * Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt. */ - uint32_t slv_cmd_err_int_ena:1; - /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0; * Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - uint32_t mst_rx_afifo_wfull_err_int_ena:1; - /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0; * Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - uint32_t mst_tx_afifo_rempty_err_int_ena:1; - /** app2_int_ena : R/W; bitpos: [19]; default: 0; + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : R/W; bitpos: [19]; default: 0; * Write 1 to enable SPI_APP2_INT interrupt. */ - uint32_t app2_int_ena:1; - /** app1_int_ena : R/W; bitpos: [20]; default: 0; + uint32_t app2:1; + /** app1 : R/W; bitpos: [20]; default: 0; * Write 1 to enable SPI_APP1_INT interrupt. */ - uint32_t app1_int_ena:1; + uint32_t app1:1; uint32_t reserved_21:11; }; uint32_t val; @@ -1178,90 +1178,90 @@ typedef union { */ typedef union { struct { - /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + /** dma_infifo_full_err : WT; bitpos: [0]; default: 0; * Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - uint32_t dma_infifo_full_err_int_clr:1; - /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0; * Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - uint32_t dma_outfifo_empty_err_int_clr:1; - /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : WT; bitpos: [2]; default: 0; * Write 1 to clear SPI_SLV_EX_QPI_INT interrupt. */ - uint32_t slv_ex_qpi_int_clr:1; - /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : WT; bitpos: [3]; default: 0; * Write 1 to clear SPI_SLV_EN_QPI_INT interrupt. */ - uint32_t slv_en_qpi_int_clr:1; - /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + uint32_t slv_en_qpi:1; + /** slv_cmd7 : WT; bitpos: [4]; default: 0; * Write 1 to clear SPI_SLV_CMD7_INT interrupt. */ - uint32_t slv_cmd7_int_clr:1; - /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + uint32_t slv_cmd7:1; + /** slv_cmd8 : WT; bitpos: [5]; default: 0; * Write 1 to clear SPI_SLV_CMD8_INT interrupt. */ - uint32_t slv_cmd8_int_clr:1; - /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + uint32_t slv_cmd8:1; + /** slv_cmd9 : WT; bitpos: [6]; default: 0; * Write 1 to clear SPI_SLV_CMD9_INT interrupt. */ - uint32_t slv_cmd9_int_clr:1; - /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + uint32_t slv_cmd9:1; + /** slv_cmda : WT; bitpos: [7]; default: 0; * Write 1 to clear SPI_SLV_CMDA_INT interrupt. */ - uint32_t slv_cmda_int_clr:1; - /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + uint32_t slv_cmda:1; + /** slv_rd_dma_done : WT; bitpos: [8]; default: 0; * Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt. */ - uint32_t slv_rd_dma_done_int_clr:1; - /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : WT; bitpos: [9]; default: 0; * Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt. */ - uint32_t slv_wr_dma_done_int_clr:1; - /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : WT; bitpos: [10]; default: 0; * Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt. */ - uint32_t slv_rd_buf_done_int_clr:1; - /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : WT; bitpos: [11]; default: 0; * Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt. */ - uint32_t slv_wr_buf_done_int_clr:1; - /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + uint32_t slv_wr_buf_done:1; + /** trans_done : WT; bitpos: [12]; default: 0; * Write 1 to clear SPI_TRANS_DONE_INT interrupt. */ - uint32_t trans_done_int_clr:1; - /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + uint32_t trans_done:1; + /** dma_seg_trans_done : WT; bitpos: [13]; default: 0; * Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t dma_seg_trans_done_int_clr:1; - /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : WT; bitpos: [14]; default: 0; * Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt. */ - uint32_t seg_magic_err_int_clr:1; - /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : WT; bitpos: [15]; default: 0; * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - uint32_t slv_buf_addr_err_int_clr:1; - /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : WT; bitpos: [16]; default: 0; * Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt. */ - uint32_t slv_cmd_err_int_clr:1; - /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0; * Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - uint32_t mst_rx_afifo_wfull_err_int_clr:1; - /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0; * Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - uint32_t mst_tx_afifo_rempty_err_int_clr:1; - /** app2_int_clr : WT; bitpos: [19]; default: 0; + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : WT; bitpos: [19]; default: 0; * Write 1 to clear SPI_APP2_INT interrupt. */ - uint32_t app2_int_clr:1; - /** app1_int_clr : WT; bitpos: [20]; default: 0; + uint32_t app2:1; + /** app1 : WT; bitpos: [20]; default: 0; * Write 1 to clear SPI_APP1_INT interrupt. */ - uint32_t app1_int_clr:1; + uint32_t app1:1; uint32_t reserved_21:11; }; uint32_t val; @@ -1272,94 +1272,94 @@ typedef union { */ typedef union { struct { - /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + /** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - uint32_t dma_infifo_full_err_int_raw:1; - /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - uint32_t dma_outfifo_empty_err_int_raw:1; - /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt. */ - uint32_t slv_ex_qpi_int_raw:1; - /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt. */ - uint32_t slv_en_qpi_int_raw:1; - /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t slv_en_qpi:1; + /** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt status of SPI_SLV_CMD7_INT interrupt. */ - uint32_t slv_cmd7_int_raw:1; - /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + uint32_t slv_cmd7:1; + /** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt status of SPI_SLV_CMD8_INT interrupt. */ - uint32_t slv_cmd8_int_raw:1; - /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + uint32_t slv_cmd8:1; + /** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt status of SPI_SLV_CMD9_INT interrupt. */ - uint32_t slv_cmd9_int_raw:1; - /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + uint32_t slv_cmd9:1; + /** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt status of SPI_SLV_CMDA_INT interrupt. */ - uint32_t slv_cmda_int_raw:1; - /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + uint32_t slv_cmda:1; + /** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0; * The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt. */ - uint32_t slv_rd_dma_done_int_raw:1; - /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt. */ - uint32_t slv_wr_dma_done_int_raw:1; - /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0; * The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt. */ - uint32_t slv_rd_buf_done_int_raw:1; - /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0; * The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt. */ - uint32_t slv_wr_buf_done_int_raw:1; - /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + uint32_t slv_wr_buf_done:1; + /** trans_done : R/WTC/SS; bitpos: [12]; default: 0; * The raw interrupt status of SPI_TRANS_DONE_INT interrupt. */ - uint32_t trans_done_int_raw:1; - /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + uint32_t trans_done:1; + /** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0; * The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t dma_seg_trans_done_int_raw:1; - /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0; * The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt. */ - uint32_t seg_magic_err_int_raw:1; - /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0; * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is * bigger than 63. 0: Others. */ - uint32_t slv_buf_addr_err_int_raw:1; - /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0; * The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt. */ - uint32_t slv_cmd_err_int_raw:1; - /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0; * The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - uint32_t mst_rx_afifo_wfull_err_int_raw:1; - /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0; * The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - uint32_t mst_tx_afifo_rempty_err_int_raw:1; - /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : R/WTC/SS; bitpos: [19]; default: 0; * The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by * the application. */ - uint32_t app2_int_raw:1; - /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + uint32_t app2:1; + /** app1 : R/WTC/SS; bitpos: [20]; default: 0; * The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by * the application. */ - uint32_t app1_int_raw:1; + uint32_t app1:1; uint32_t reserved_21:11; }; uint32_t val; @@ -1370,90 +1370,90 @@ typedef union { */ typedef union { struct { - /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + /** dma_infifo_full_err : RO; bitpos: [0]; default: 0; * The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - uint32_t dma_infifo_full_err_int_st:1; - /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0; * The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - uint32_t dma_outfifo_empty_err_int_st:1; - /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : RO; bitpos: [2]; default: 0; * The interrupt status of SPI_SLV_EX_QPI_INT interrupt. */ - uint32_t slv_ex_qpi_int_st:1; - /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : RO; bitpos: [3]; default: 0; * The interrupt status of SPI_SLV_EN_QPI_INT interrupt. */ - uint32_t slv_en_qpi_int_st:1; - /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + uint32_t slv_en_qpi:1; + /** slv_cmd7 : RO; bitpos: [4]; default: 0; * The interrupt status of SPI_SLV_CMD7_INT interrupt. */ - uint32_t slv_cmd7_int_st:1; - /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + uint32_t slv_cmd7:1; + /** slv_cmd8 : RO; bitpos: [5]; default: 0; * The interrupt status of SPI_SLV_CMD8_INT interrupt. */ - uint32_t slv_cmd8_int_st:1; - /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + uint32_t slv_cmd8:1; + /** slv_cmd9 : RO; bitpos: [6]; default: 0; * The interrupt status of SPI_SLV_CMD9_INT interrupt. */ - uint32_t slv_cmd9_int_st:1; - /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + uint32_t slv_cmd9:1; + /** slv_cmda : RO; bitpos: [7]; default: 0; * The interrupt status of SPI_SLV_CMDA_INT interrupt. */ - uint32_t slv_cmda_int_st:1; - /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + uint32_t slv_cmda:1; + /** slv_rd_dma_done : RO; bitpos: [8]; default: 0; * The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt. */ - uint32_t slv_rd_dma_done_int_st:1; - /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : RO; bitpos: [9]; default: 0; * The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt. */ - uint32_t slv_wr_dma_done_int_st:1; - /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : RO; bitpos: [10]; default: 0; * The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt. */ - uint32_t slv_rd_buf_done_int_st:1; - /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : RO; bitpos: [11]; default: 0; * The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt. */ - uint32_t slv_wr_buf_done_int_st:1; - /** trans_done_int_st : RO; bitpos: [12]; default: 0; + uint32_t slv_wr_buf_done:1; + /** trans_done : RO; bitpos: [12]; default: 0; * The interrupt status of SPI_TRANS_DONE_INT interrupt. */ - uint32_t trans_done_int_st:1; - /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + uint32_t trans_done:1; + /** dma_seg_trans_done : RO; bitpos: [13]; default: 0; * The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t dma_seg_trans_done_int_st:1; - /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : RO; bitpos: [14]; default: 0; * The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt. */ - uint32_t seg_magic_err_int_st:1; - /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : RO; bitpos: [15]; default: 0; * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - uint32_t slv_buf_addr_err_int_st:1; - /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : RO; bitpos: [16]; default: 0; * The interrupt status of SPI_SLV_CMD_ERR_INT interrupt. */ - uint32_t slv_cmd_err_int_st:1; - /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0; * The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - uint32_t mst_rx_afifo_wfull_err_int_st:1; - /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0; * The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - uint32_t mst_tx_afifo_rempty_err_int_st:1; - /** app2_int_st : RO; bitpos: [19]; default: 0; + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : RO; bitpos: [19]; default: 0; * The interrupt status of SPI_APP2_INT interrupt. */ - uint32_t app2_int_st:1; - /** app1_int_st : RO; bitpos: [20]; default: 0; + uint32_t app2:1; + /** app1 : RO; bitpos: [20]; default: 0; * The interrupt status of SPI_APP1_INT interrupt. */ - uint32_t app1_int_st:1; + uint32_t app1:1; uint32_t reserved_21:11; }; uint32_t val; @@ -1464,90 +1464,90 @@ typedef union { */ typedef union { struct { - /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + /** dma_infifo_full_err : WT; bitpos: [0]; default: 0; * Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - uint32_t dma_infifo_full_err_int_set:1; - /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0; * Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - uint32_t dma_outfifo_empty_err_int_set:1; - /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : WT; bitpos: [2]; default: 0; * Write 1 to set SPI_SLV_EX_QPI_INT interrupt. */ - uint32_t slv_ex_qpi_int_set:1; - /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : WT; bitpos: [3]; default: 0; * Write 1 to set SPI_SLV_EN_QPI_INT interrupt. */ - uint32_t slv_en_qpi_int_set:1; - /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + uint32_t slv_en_qpi:1; + /** slv_cmd7 : WT; bitpos: [4]; default: 0; * Write 1 to set SPI_SLV_CMD7_INT interrupt. */ - uint32_t slv_cmd7_int_set:1; - /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + uint32_t slv_cmd7:1; + /** slv_cmd8 : WT; bitpos: [5]; default: 0; * Write 1 to set SPI_SLV_CMD8_INT interrupt. */ - uint32_t slv_cmd8_int_set:1; - /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + uint32_t slv_cmd8:1; + /** slv_cmd9 : WT; bitpos: [6]; default: 0; * Write 1 to set SPI_SLV_CMD9_INT interrupt. */ - uint32_t slv_cmd9_int_set:1; - /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + uint32_t slv_cmd9:1; + /** slv_cmda : WT; bitpos: [7]; default: 0; * Write 1 to set SPI_SLV_CMDA_INT interrupt. */ - uint32_t slv_cmda_int_set:1; - /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + uint32_t slv_cmda:1; + /** slv_rd_dma_done : WT; bitpos: [8]; default: 0; * Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt. */ - uint32_t slv_rd_dma_done_int_set:1; - /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : WT; bitpos: [9]; default: 0; * Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt. */ - uint32_t slv_wr_dma_done_int_set:1; - /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : WT; bitpos: [10]; default: 0; * Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt. */ - uint32_t slv_rd_buf_done_int_set:1; - /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : WT; bitpos: [11]; default: 0; * Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt. */ - uint32_t slv_wr_buf_done_int_set:1; - /** trans_done_int_set : WT; bitpos: [12]; default: 0; + uint32_t slv_wr_buf_done:1; + /** trans_done : WT; bitpos: [12]; default: 0; * Write 1 to set SPI_TRANS_DONE_INT interrupt. */ - uint32_t trans_done_int_set:1; - /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + uint32_t trans_done:1; + /** dma_seg_trans_done : WT; bitpos: [13]; default: 0; * Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t dma_seg_trans_done_int_set:1; - /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : WT; bitpos: [14]; default: 0; * Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt. */ - uint32_t seg_magic_err_int_set:1; - /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : WT; bitpos: [15]; default: 0; * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - uint32_t slv_buf_addr_err_int_set:1; - /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : WT; bitpos: [16]; default: 0; * Write 1 to set SPI_SLV_CMD_ERR_INT interrupt. */ - uint32_t slv_cmd_err_int_set:1; - /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0; * Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - uint32_t mst_rx_afifo_wfull_err_int_set:1; - /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0; * Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - uint32_t mst_tx_afifo_rempty_err_int_set:1; - /** app2_int_set : WT; bitpos: [19]; default: 0; + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : WT; bitpos: [19]; default: 0; * Write 1 to set SPI_APP2_INT interrupt. */ - uint32_t app2_int_set:1; - /** app1_int_set : WT; bitpos: [20]; default: 0; + uint32_t app2:1; + /** app1 : WT; bitpos: [20]; default: 0; * Write 1 to set SPI_APP1_INT interrupt. */ - uint32_t app1_int_set:1; + uint32_t app1:1; uint32_t reserved_21:11; }; uint32_t val; diff --git a/components/soc/esp32c61/include/soc/system_periph_retention.h b/components/soc/esp32c61/include/soc/system_periph_retention.h new file mode 100644 index 0000000000..33247d0b6e --- /dev/null +++ b/components/soc/esp32c61/include/soc/system_periph_retention.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "soc/regdma.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Provide access to interrupt matrix configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define INT_MTX_RETENTION_LINK_LEN 1 +extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to hp_system configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define HP_SYSTEM_RETENTION_LINK_LEN 1 +extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to TEE_APM configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define TEE_APM_RETENTION_LINK_LEN 2 +extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN]; +#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN 1 +extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to uart configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define UART_RETENTION_LINK_LEN 3 +extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to timer group configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define TIMG_RETENTION_LINK_LEN 8 +extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to IOMUX configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define IOMUX_RETENTION_LINK_LEN 4 +extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to spimem configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define SPIMEM_RETENTION_LINK_LEN 8 +extern const regdma_entries_config_t spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN]; + +/** + * @brief Provide access to systimer configuration registers retention + * context defination. + * + * This is an internal function of the sleep retention driver, and is not + * useful for external use. + */ +#define SYSTIMER_RETENTION_LINK_LEN 19 +extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/system_reg.h b/components/soc/esp32c61/include/soc/system_reg.h new file mode 100644 index 0000000000..4577fecbeb --- /dev/null +++ b/components/soc/esp32c61/include/soc/system_reg.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/hp_system_reg.h" + +#include "intpri_reg.h" +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG +#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32c61/include/soc/sys_timer_reg.h b/components/soc/esp32c61/include/soc/systimer_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/sys_timer_reg.h rename to components/soc/esp32c61/include/soc/systimer_reg.h diff --git a/components/soc/esp32c61/include/soc/sys_timer_struct.h b/components/soc/esp32c61/include/soc/systimer_struct.h similarity index 88% rename from components/soc/esp32c61/include/soc/sys_timer_struct.h rename to components/soc/esp32c61/include/soc/systimer_struct.h index df6721e4a1..af7ed294cd 100644 --- a/components/soc/esp32c61/include/soc/sys_timer_struct.h +++ b/components/soc/esp32c61/include/soc/systimer_struct.h @@ -95,18 +95,18 @@ typedef union { /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0; * Represents UNIT0 value is synchronized and valid. */ - uint32_t timer_unit0_value_valid:1; + uint32_t timer_unit_value_valid:1; /** timer_unit0_update : WT; bitpos: [30]; default: 0; * Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value * to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\ * 0: No effect\\ * 1: Update timer UNIT0 \\ */ - uint32_t timer_unit0_update:1; + uint32_t timer_unit_update:1; uint32_t reserved_31:1; }; uint32_t val; -} systimer_unit0_op_reg_t; +} systimer_unit_op_reg_t; /** Type of unit0_load_hi register * High 20 bits to be loaded to UNIT0 @@ -116,7 +116,7 @@ typedef union { /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0; * Configures the value to be loaded to UNIT0, high 20 bits. */ - uint32_t timer_unit0_load_hi:20; + uint32_t timer_unit_load_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -130,7 +130,7 @@ typedef union { /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0; * Configures the value to be loaded to UNIT0, low 32 bits. */ - uint32_t timer_unit0_load_lo:32; + uint32_t timer_unit_load_lo:32; }; uint32_t val; } systimer_unit0_load_lo_reg_t; @@ -143,7 +143,7 @@ typedef union { /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0; * Represents UNIT0 read value, high 20 bits. */ - uint32_t timer_unit0_value_hi:20; + uint32_t timer_unit_value_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -157,7 +157,7 @@ typedef union { /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0; * Represents UNIT0 read value, low 32 bits. */ - uint32_t timer_unit0_value_lo:32; + uint32_t timer_unit_value_lo:32; }; uint32_t val; } systimer_unit0_value_lo_reg_t; @@ -177,7 +177,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} systimer_unit0_load_reg_t; +} systimer_unit_load_reg_t; /** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */ @@ -204,7 +204,7 @@ typedef union { } systimer_unit1_op_reg_t; /** Type of unit1_load_hi register - * High 20 bits to be loaded to UNIT1 + * High 20 bits to be loaded to UNIT1systimer_unit1_load_reg_t */ typedef union { struct { @@ -284,7 +284,7 @@ typedef union { /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0; * Configures the alarm value to be loaded to COMP0, high 20 bits. */ - uint32_t timer_target0_hi:20; + uint32_t timer_target_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -298,7 +298,7 @@ typedef union { /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0; * Configures the alarm value to be loaded to COMP0, low 32 bits. */ - uint32_t timer_target0_lo:32; + uint32_t timer_target_lo:32; }; uint32_t val; } systimer_target0_lo_reg_t; @@ -308,26 +308,26 @@ typedef union { */ typedef union { struct { - /** target0_period : R/W; bitpos: [25:0]; default: 0; + /** target_period : R/W; bitpos: [25:0]; default: 0; * Configures COMP0 alarm period. */ - uint32_t target0_period:26; + uint32_t target_period:26; uint32_t reserved_26:4; - /** target0_period_mode : R/W; bitpos: [30]; default: 0; + /** target_period_mode : R/W; bitpos: [30]; default: 0; * Selects the two alarm modes for COMP0. \\ * 0: Target mode\\ * 1: Period mode\\ */ - uint32_t target0_period_mode:1; - /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0; + uint32_t target_period_mode:1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; * Chooses the counter value for comparison with COMP0.\\ * 0: Use the count value from UNIT$0\\ * 1: Use the count value from UNIT$1\\ */ - uint32_t target0_timer_unit_sel:1; + uint32_t target_timer_unit_sel:1; }; uint32_t val; -} systimer_target0_conf_reg_t; +} systimer_target_conf_reg_t; /** Type of comp0_load register * COMP0 synchronization register @@ -344,7 +344,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} systimer_comp0_load_reg_t; +} systimer_comp_load_reg_t; /** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */ @@ -585,7 +585,7 @@ typedef union { /** target0_lo_ro : RO; bitpos: [31:0]; default: 0; * Represents the actual target value of COMP0, low 32 bits. */ - uint32_t target0_lo_ro:32; + uint32_t target_lo_ro:32; }; uint32_t val; } systimer_real_target0_lo_reg_t; @@ -598,7 +598,7 @@ typedef union { /** target0_hi_ro : RO; bitpos: [19:0]; default: 0; * Represents the actual target value of COMP0, high 20 bits. */ - uint32_t target0_hi_ro:20; + uint32_t target_hi_ro:20; uint32_t reserved_20:12; }; uint32_t val; @@ -677,43 +677,45 @@ typedef union { uint32_t val; } systimer_date_reg_t; +typedef struct systimer_unit_load_val_reg +{ + systimer_unit0_load_hi_reg_t hi; + systimer_unit0_load_lo_reg_t lo; +} systimer_unit_load_val_reg_t; -typedef struct { +typedef struct systimer_target_val_reg +{ + systimer_target0_hi_reg_t hi; + systimer_target0_lo_reg_t lo; +} systimer_target_val_reg_t; + +typedef struct systimer_unit_value_reg +{ + systimer_unit0_value_hi_reg_t hi; + systimer_unit0_value_lo_reg_t lo; +} systimer_unit_value_reg_t; + +typedef struct systimer_real_target_reg +{ + systimer_real_target0_lo_reg_t lo; + systimer_real_target0_hi_reg_t hi; +} systimer_real_target_reg_t; + + +typedef struct systimer_dev_t{ volatile systimer_conf_reg_t conf; - volatile systimer_unit0_op_reg_t unit0_op; - volatile systimer_unit1_op_reg_t unit1_op; - volatile systimer_unit0_load_hi_reg_t unit0_load_hi; - volatile systimer_unit0_load_lo_reg_t unit0_load_lo; - volatile systimer_unit1_load_hi_reg_t unit1_load_hi; - volatile systimer_unit1_load_lo_reg_t unit1_load_lo; - volatile systimer_target0_hi_reg_t target0_hi; - volatile systimer_target0_lo_reg_t target0_lo; - volatile systimer_target1_hi_reg_t target1_hi; - volatile systimer_target1_lo_reg_t target1_lo; - volatile systimer_target2_hi_reg_t target2_hi; - volatile systimer_target2_lo_reg_t target2_lo; - volatile systimer_target0_conf_reg_t target0_conf; - volatile systimer_target1_conf_reg_t target1_conf; - volatile systimer_target2_conf_reg_t target2_conf; - volatile systimer_unit0_value_hi_reg_t unit0_value_hi; - volatile systimer_unit0_value_lo_reg_t unit0_value_lo; - volatile systimer_unit1_value_hi_reg_t unit1_value_hi; - volatile systimer_unit1_value_lo_reg_t unit1_value_lo; - volatile systimer_comp0_load_reg_t comp0_load; - volatile systimer_comp1_load_reg_t comp1_load; - volatile systimer_comp2_load_reg_t comp2_load; - volatile systimer_unit0_load_reg_t unit0_load; - volatile systimer_unit1_load_reg_t unit1_load; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; volatile systimer_int_ena_reg_t int_ena; volatile systimer_int_raw_reg_t int_raw; volatile systimer_int_clr_reg_t int_clr; volatile systimer_int_st_reg_t int_st; - volatile systimer_real_target0_lo_reg_t real_target0_lo; - volatile systimer_real_target0_hi_reg_t real_target0_hi; - volatile systimer_real_target1_lo_reg_t real_target1_lo; - volatile systimer_real_target1_hi_reg_t real_target1_hi; - volatile systimer_real_target2_lo_reg_t real_target2_lo; - volatile systimer_real_target2_hi_reg_t real_target2_hi; + volatile systimer_real_target_reg_t real_target[3]; uint32_t reserved_08c[28]; volatile systimer_date_reg_t date; } systimer_dev_t; diff --git a/components/soc/esp32c61/include/soc/timer_group_reg.h b/components/soc/esp32c61/include/soc/timer_group_reg.h index 761db43060..332002a62e 100644 --- a/components/soc/esp32c61/include/soc/timer_group_reg.h +++ b/components/soc/esp32c61/include/soc/timer_group_reg.h @@ -14,7 +14,7 @@ extern "C" { /** TIMG_T0CONFIG_REG register * Timer 0 configuration register */ -#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0) +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) /** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source * clock of timer group. @@ -71,7 +71,7 @@ extern "C" { /** TIMG_T0LO_REG register * Timer 0 current value, low 32 bits */ -#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4) +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter * of timer 0 can be read here. @@ -84,7 +84,7 @@ extern "C" { /** TIMG_T0HI_REG register * Timer 0 current value, high 22 bits */ -#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8) +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter * of timer 0 can be read here. @@ -97,7 +97,7 @@ extern "C" { /** TIMG_T0UPDATE_REG register * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG */ -#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc) +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. */ @@ -109,7 +109,7 @@ extern "C" { /** TIMG_T0ALARMLO_REG register * Timer 0 alarm value, low 32 bits */ -#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10) +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; * Timer 0 alarm trigger time-base counter value, low 32 bits. */ @@ -121,7 +121,7 @@ extern "C" { /** TIMG_T0ALARMHI_REG register * Timer 0 alarm value, high bits */ -#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14) +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; * Timer 0 alarm trigger time-base counter value, high 22 bits. */ @@ -133,7 +133,7 @@ extern "C" { /** TIMG_T0LOADLO_REG register * Timer 0 reload value, low 32 bits */ -#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18) +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; * Low 32 bits of the value that a reload will load onto timer 0 time-base * Counter. @@ -146,7 +146,7 @@ extern "C" { /** TIMG_T0LOADHI_REG register * Timer 0 reload value, high 22 bits */ -#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c) +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; * High 22 bits of the value that a reload will load onto timer 0 time-base * counter. @@ -159,7 +159,7 @@ extern "C" { /** TIMG_T0LOAD_REG register * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG */ -#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20) +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; * * Write any value to trigger a timer 0 time-base counter reload. @@ -330,7 +330,7 @@ extern "C" { /** TIMG_WDTCONFIG0_REG register * Watchdog timer configuration register */ -#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48) +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; * WDT reset CPU enable. */ @@ -421,7 +421,7 @@ extern "C" { /** TIMG_WDTCONFIG1_REG register * Watchdog timer prescaler register */ -#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c) +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; * When set, WDT 's clock divider counter will be reset. */ @@ -441,7 +441,7 @@ extern "C" { /** TIMG_WDTCONFIG2_REG register * Watchdog timer stage 0 timeout value */ -#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50) +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; * Stage 0 timeout value, in MWDT clock cycles. */ @@ -453,7 +453,7 @@ extern "C" { /** TIMG_WDTCONFIG3_REG register * Watchdog timer stage 1 timeout value */ -#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54) +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; * Stage 1 timeout value, in MWDT clock cycles. */ @@ -465,7 +465,7 @@ extern "C" { /** TIMG_WDTCONFIG4_REG register * Watchdog timer stage 2 timeout value */ -#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58) +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; * Stage 2 timeout value, in MWDT clock cycles. */ @@ -477,7 +477,7 @@ extern "C" { /** TIMG_WDTCONFIG5_REG register * Watchdog timer stage 3 timeout value */ -#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c) +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; * Stage 3 timeout value, in MWDT clock cycles. */ @@ -489,7 +489,7 @@ extern "C" { /** TIMG_WDTFEED_REG register * Write to feed the watchdog timer */ -#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60) +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; * Write any value to feed the MWDT. (WO) */ @@ -501,7 +501,7 @@ extern "C" { /** TIMG_WDTWPROTECT_REG register * Watchdog write protect register */ -#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64) +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; * If the register contains a different value than its reset value, write * protection is enabled. @@ -514,7 +514,7 @@ extern "C" { /** TIMG_RTCCALICFG_REG register * RTC calibration configure register */ -#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68) +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) /** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; * 0: one-shot frequency calculation,1: periodic frequency calculation, */ @@ -554,7 +554,7 @@ extern "C" { /** TIMG_RTCCALICFG1_REG register * RTC calibration configure1 register */ -#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c) +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) /** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; * indicate periodic frequency calculation is done. */ @@ -574,7 +574,7 @@ extern "C" { /** TIMG_INT_ENA_TIMERS_REG register * Interrupt enable bits */ -#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70) +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the TIMG_T$x_INT interrupt. */ @@ -600,7 +600,7 @@ extern "C" { /** TIMG_INT_RAW_TIMERS_REG register * Raw interrupt status */ -#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74) +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; * The raw interrupt status bit for the TIMG_T$x_INT interrupt. */ @@ -626,7 +626,7 @@ extern "C" { /** TIMG_INT_ST_TIMERS_REG register * Masked interrupt status */ -#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78) +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status bit for the TIMG_T$x_INT interrupt. */ @@ -652,7 +652,7 @@ extern "C" { /** TIMG_INT_CLR_TIMERS_REG register * Interrupt clear bits */ -#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c) +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the TIMG_T$x_INT interrupt. */ @@ -678,7 +678,7 @@ extern "C" { /** TIMG_RTCCALICFG2_REG register * Timer group calibration register */ -#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80) +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) /** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; * RTC calibration timeout indicator */ @@ -705,7 +705,7 @@ extern "C" { /** TIMG_NTIMERS_DATE_REG register * Timer version control register */ -#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8) +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; * Timer version control register */ @@ -717,7 +717,7 @@ extern "C" { /** TIMG_REGCLK_REG register * Timer group clock gate register */ -#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc) +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) /** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; * enable timer's etm task and event */ diff --git a/components/soc/esp32c61/include/soc/timer_group_struct.h b/components/soc/esp32c61/include/soc/timer_group_struct.h index d3edcc9e0e..0f5d68f92a 100644 --- a/components/soc/esp32c61/include/soc/timer_group_struct.h +++ b/components/soc/esp32c61/include/soc/timer_group_struct.h @@ -167,163 +167,6 @@ typedef union { } timg_txload_reg_t; -/** Group: T1 Control and configuration registers */ -/** Type of txconfig register - * Timer x configuration register - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** tx_use_xtal : R/W; bitpos: [9]; default: 0; - * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source - * clock of timer group. - */ - uint32_t tx_use_xtal:1; - /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; - * When set, the alarm is enabled. This bit is automatically cleared once an - * alarm occurs. - */ - uint32_t tx_alarm_en:1; - uint32_t reserved_11:1; - /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; - * When set, Timer x 's clock divider counter will be reset. - */ - uint32_t tx_divcnt_rst:1; - /** tx_divider : R/W; bitpos: [28:13]; default: 1; - * Timer x clock (Tx_clk) prescaler value. - */ - uint32_t tx_divider:16; - /** tx_autoreload : R/W; bitpos: [29]; default: 1; - * When set, timer x auto-reload at alarm is enabled. - */ - uint32_t tx_autoreload:1; - /** tx_increase : R/W; bitpos: [30]; default: 1; - * When set, the timer x time-base counter will increment every clock tick. When - * cleared, the timer x time-base counter will decrement. - */ - uint32_t tx_increase:1; - /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; - * When set, the timer x time-base counter is enabled. - */ - uint32_t tx_en:1; - }; - uint32_t val; -} timg_txconfig_reg_t; - -/** Type of txlo register - * Timer x current value, low 32 bits - */ -typedef union { - struct { - /** tx_lo : RO; bitpos: [31:0]; default: 0; - * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter - * of timer x can be read here. - */ - uint32_t tx_lo:32; - }; - uint32_t val; -} timg_txlo_reg_t; - -/** Type of txhi register - * Timer x current value, high 22 bits - */ -typedef union { - struct { - /** tx_hi : RO; bitpos: [21:0]; default: 0; - * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter - * of timer x can be read here. - */ - uint32_t tx_hi:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} timg_txhi_reg_t; - -/** Type of txupdate register - * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** tx_update : R/W/SC; bitpos: [31]; default: 0; - * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. - */ - uint32_t tx_update:1; - }; - uint32_t val; -} timg_txupdate_reg_t; - -/** Type of txalarmlo register - * Timer x alarm value, low 32 bits - */ -typedef union { - struct { - /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; - * Timer x alarm trigger time-base counter value, low 32 bits. - */ - uint32_t tx_alarm_lo:32; - }; - uint32_t val; -} timg_txalarmlo_reg_t; - -/** Type of txalarmhi register - * Timer x alarm value, high bits - */ -typedef union { - struct { - /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; - * Timer x alarm trigger time-base counter value, high 22 bits. - */ - uint32_t tx_alarm_hi:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} timg_txalarmhi_reg_t; - -/** Type of txloadlo register - * Timer x reload value, low 32 bits - */ -typedef union { - struct { - /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; - * Low 32 bits of the value that a reload will load onto timer x time-base - * Counter. - */ - uint32_t tx_load_lo:32; - }; - uint32_t val; -} timg_txloadlo_reg_t; - -/** Type of txloadhi register - * Timer x reload value, high 22 bits - */ -typedef union { - struct { - /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; - * High 22 bits of the value that a reload will load onto timer x time-base - * counter. - */ - uint32_t tx_load_hi:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} timg_txloadhi_reg_t; - -/** Type of txload register - * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG - */ -typedef union { - struct { - /** tx_load : WT; bitpos: [31:0]; default: 0; - * - * Write any value to trigger a timer x time-base counter reload. - */ - uint32_t tx_load:32; - }; - uint32_t val; -} timg_txload_reg_t; - - /** Group: WDT Control and configuration registers */ /** Type of wdtconfig0 register * Watchdog timer configuration register @@ -706,7 +549,7 @@ typedef struct { } timg_hwtimer_reg_t; -typedef struct { +typedef struct timg_dev_t { volatile timg_hwtimer_reg_t hw_timer[2]; volatile timg_wdtconfig0_reg_t wdtconfig0; volatile timg_wdtconfig1_reg_t wdtconfig1; diff --git a/components/soc/esp32c61/include/soc/uart_channel.h b/components/soc/esp32c61/include/soc/uart_channel.h new file mode 100644 index 0000000000..f62dddf99b --- /dev/null +++ b/components/soc/esp32c61/include/soc/uart_channel.h @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C61. + +#pragma once + +//UART channels +#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16 +#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17 + +#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL +#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL diff --git a/components/soc/esp32c61/include/soc/uart_pins.h b/components/soc/esp32c61/include/soc/uart_pins.h new file mode 100644 index 0000000000..0d1cbd792e --- /dev/null +++ b/components/soc/esp32c61/include/soc/uart_pins.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/io_mux_reg.h" + +/* Specify the number of pins for UART */ +#define SOC_UART_PINS_COUNT (4) + +/* Specify the GPIO pin number for each UART signal in the IOMUX */ +#define U0RXD_GPIO_NUM 10 +#define U0TXD_GPIO_NUM 11 +#define U0RTS_GPIO_NUM (-1) +#define U0CTS_GPIO_NUM (-1) + +#define U1RXD_GPIO_NUM (-1) +#define U1TXD_GPIO_NUM (-1) +#define U1RTS_GPIO_NUM (-1) +#define U1CTS_GPIO_NUM (-1) + +#define LP_U0RXD_GPIO_NUM 4 +#define LP_U0TXD_GPIO_NUM 5 +#define LP_U0RTS_GPIO_NUM 2 +#define LP_U0CTS_GPIO_NUM 3 + +/* The following defines are necessary for reconfiguring the UART + * to use IOMUX, at runtime. */ +#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD) +#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD) +/* No func for the following pins, they shall not be used */ +#define U0RTS_MUX_FUNC (-1) +#define U0CTS_MUX_FUNC (-1) +/* Same goes for UART1 */ +#define U1TXD_MUX_FUNC (-1) +#define U1RXD_MUX_FUNC (-1) +#define U1RTS_MUX_FUNC (-1) +#define U1CTS_MUX_FUNC (-1) + +#define LP_U0TXD_MUX_FUNC (1) +#define LP_U0RXD_MUX_FUNC (1) +#define LP_U0RTS_MUX_FUNC (1) +#define LP_U0CTS_MUX_FUNC (1) diff --git a/components/soc/esp32c61/include/soc/uart_reg.h b/components/soc/esp32c61/include/soc/uart_reg.h index 73577ca963..1560610f0b 100644 --- a/components/soc/esp32c61/include/soc/uart_reg.h +++ b/components/soc/esp32c61/include/soc/uart_reg.h @@ -14,7 +14,7 @@ extern "C" { /** UART_FIFO_REG register * FIFO data register */ -#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0) +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; * Represents the data UART $n read from FIFO.\\ * Measurement unit: byte. @@ -27,7 +27,7 @@ extern "C" { /** UART_INT_RAW_REG register * Raw interrupt status */ -#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4) +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) /** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt status of UART_RXFIFO_FULL_INT. */ @@ -172,7 +172,7 @@ extern "C" { /** UART_INT_ST_REG register * Masked interrupt status */ -#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8) +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) /** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status of UART_RXFIFO_FULL_INT. */ @@ -317,7 +317,7 @@ extern "C" { /** UART_INT_ENA_REG register * Interrupt enable bits */ -#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc) +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) /** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; * Write 1 to enable UART_RXFIFO_FULL_INT. */ @@ -462,7 +462,7 @@ extern "C" { /** UART_INT_CLR_REG register * Interrupt clear bits */ -#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10) +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) /** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; * Write 1 to clear UART_RXFIFO_FULL_INT. */ @@ -607,7 +607,7 @@ extern "C" { /** UART_CLKDIV_SYNC_REG register * Clock divider configuration */ -#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14) +#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) /** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; * Configures the integral part of the divisor for baud rate generation. */ @@ -626,7 +626,7 @@ extern "C" { /** UART_RX_FILT_REG register * RX filter configuration */ -#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18) +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) /** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; * Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's * clock cycle.\\Pulses whose width is lower than this value will be ignored. @@ -648,7 +648,7 @@ extern "C" { /** UART_STATUS_REG register * UART status register */ -#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c) +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) /** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; * Represents the number of valid data bytes in RX FIFO. */ @@ -709,7 +709,7 @@ extern "C" { /** UART_CONF0_SYNC_REG register * Configuration register 0 */ -#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20) +#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) /** UART_PARITY : R/W; bitpos: [0]; default: 0; * Configures the parity check mode.\\ * 0: Even parity\\ @@ -918,7 +918,7 @@ extern "C" { /** UART_CONF1_REG register * Configuration register 1 */ -#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24) +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; * Configures the threshold for RX FIFO being full.\\Measurement unit: byte. */ @@ -991,7 +991,7 @@ extern "C" { /** UART_HWFC_CONF_SYNC_REG register * Hardware flow control configuration */ -#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c) +#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) /** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; * Configures the maximum number of data bytes that can be received during hardware * flow control.\\Measurement unit: byte. @@ -1013,7 +1013,7 @@ extern "C" { /** UART_SLEEP_CONF0_REG register * UART sleep configuration register 0 */ -#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30) +#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) /** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; * Configures wakeup character 1. */ @@ -1046,7 +1046,7 @@ extern "C" { /** UART_SLEEP_CONF1_REG register * UART sleep configuration register 1 */ -#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34) +#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) /** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; * Configures wakeup character 0. */ @@ -1058,7 +1058,7 @@ extern "C" { /** UART_SLEEP_CONF2_REG register * UART sleep configuration register 2 */ -#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38) +#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) /** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; * Configures the number of RXD edge changes to wake up the chip in wakeup mode 0. */ @@ -1104,7 +1104,7 @@ extern "C" { /** UART_SWFC_CONF0_SYNC_REG register * Software flow control character configuration */ -#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c) +#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) /** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; * Configures the XON character for flow control. */ @@ -1188,7 +1188,7 @@ extern "C" { /** UART_SWFC_CONF1_REG register * Software flow control character configuration */ -#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40) +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) /** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; * Configures the threshold for data in RX FIFO to send XON characters in software * flow control.\\Measurement unit: byte. @@ -1209,7 +1209,7 @@ extern "C" { /** UART_TXBRK_CONF_SYNC_REG register * TX break character configuration */ -#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44) +#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) /** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; * Configures the number of NULL characters to be sent after finishing data * transmission.\\Valid only when UART_TXD_BRK is 1. @@ -1222,7 +1222,7 @@ extern "C" { /** UART_IDLE_CONF_SYNC_REG register * Frame end idle time configuration */ -#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48) +#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) /** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; * Configures the threshold to generate a frame end signal when the receiver takes * more time to receive one data byte data.\\Measurement unit: bit time (the time to @@ -1244,7 +1244,7 @@ extern "C" { /** UART_RS485_CONF_SYNC_REG register * RS485 mode configuration */ -#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c) +#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) /** UART_RS485_EN : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable RS485 mode.\\ * 0: Disable\\ @@ -1312,7 +1312,7 @@ extern "C" { /** UART_AT_CMD_PRECNT_SYNC_REG register * Pre-sequence timing configuration */ -#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50) +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) /** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * Configures the idle time before the receiver receives the first * AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit). @@ -1325,7 +1325,7 @@ extern "C" { /** UART_AT_CMD_POSTCNT_SYNC_REG register * Post-sequence timing configuration */ -#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54) +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) /** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * Configures the interval between the last AT_CMD and subsequent data.\\Measurement * unit: bit time (the time to transmit 1 bit). @@ -1338,7 +1338,7 @@ extern "C" { /** UART_AT_CMD_GAPTOUT_SYNC_REG register * Timeout configuration */ -#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58) +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) /** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; * Configures the interval between two AT_CMD characters.\\Measurement unit: bit time * (the time to transmit 1 bit). @@ -1351,7 +1351,7 @@ extern "C" { /** UART_AT_CMD_CHAR_SYNC_REG register * AT escape sequence detection configuration */ -#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c) +#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) /** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; * Configures the AT_CMD character. */ @@ -1370,7 +1370,7 @@ extern "C" { /** UART_MEM_CONF_REG register * UART memory power configuration */ -#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60) +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) /** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; * Set this bit to force power down UART memory. */ @@ -1389,7 +1389,7 @@ extern "C" { /** UART_TOUT_CONF_SYNC_REG register * UART threshold and allocation configuration */ -#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64) +#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable UART receiver's timeout function.\\ * 0: Disable\\ @@ -1418,7 +1418,7 @@ extern "C" { /** UART_MEM_TX_STATUS_REG register * TX FIFO write and read offset address */ -#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68) +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) /** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; * Represents the offset address to write TX FIFO. */ @@ -1437,7 +1437,7 @@ extern "C" { /** UART_MEM_RX_STATUS_REG register * Rx FIFO write and read offset address */ -#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c) +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) /** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; * Represents the offset address to read RX FIFO. */ @@ -1456,7 +1456,7 @@ extern "C" { /** UART_FSM_STATUS_REG register * UART transmit and receive status */ -#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70) +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) /** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; * Represents the status of the receiver. */ @@ -1475,7 +1475,7 @@ extern "C" { /** UART_POSPULSE_REG register * Autobaud high pulse register */ -#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74) +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) /** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * Represents the minimal input clock counter value between two positive edges. It is * used for baud rate detection. @@ -1488,7 +1488,7 @@ extern "C" { /** UART_NEGPULSE_REG register * Autobaud low pulse register */ -#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78) +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) /** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * Represents the minimal input clock counter value between two negative edges. It is * used for baud rate detection. @@ -1501,7 +1501,7 @@ extern "C" { /** UART_LOWPULSE_REG register * Autobaud minimum low pulse duration register */ -#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c) +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) /** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * Represents the minimum duration time of a low-level pulse. It is used for baud rate * detection.\\Measurement unit: APB_CLK clock cycle. @@ -1514,7 +1514,7 @@ extern "C" { /** UART_HIGHPULSE_REG register * Autobaud minimum high pulse duration register */ -#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80) +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * Represents the maximum duration time for a high-level pulse. It is used for baud * rate detection.\\Measurement unit: APB_CLK clock cycle. @@ -1527,7 +1527,7 @@ extern "C" { /** UART_RXD_CNT_REG register * Autobaud edge change count register */ -#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84) +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) /** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; * Represents the number of RXD edge changes. It is used for baud rate detection. */ @@ -1539,7 +1539,7 @@ extern "C" { /** UART_CLK_CONF_REG register * UART core clock configuration */ -#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88) +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) /** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; * Configures whether or not to enable UART TX clock.\\ * 0: Disable\\ @@ -1576,7 +1576,7 @@ extern "C" { /** UART_DATE_REG register * UART version control register */ -#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c) +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) /** UART_DATE : R/W; bitpos: [31:0]; default: 36774432; * Version control register. */ @@ -1588,7 +1588,7 @@ extern "C" { /** UART_AFIFO_STATUS_REG register * UART asynchronous FIFO status */ -#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90) +#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) /** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; * Represents whether or not the APB TX asynchronous FIFO is full.\\ * 0: Not full\\ @@ -1629,7 +1629,7 @@ extern "C" { /** UART_REG_UPDATE_REG register * UART register configuration update */ -#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98) +#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) /** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; * Configures whether or not to synchronize registers.\\ * 0: Not synchronize\\ @@ -1643,7 +1643,7 @@ extern "C" { /** UART_ID_REG register * UART ID register */ -#define UART_ID_REG (DR_REG_UART_BASE + 0x9c) +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) /** UART_ID : R/W; bitpos: [31:0]; default: 1280; * Configures the UART ID. */ diff --git a/components/soc/esp32c61/include/soc/uart_struct.h b/components/soc/esp32c61/include/soc/uart_struct.h index 24f1dd55eb..870b65310c 100644 --- a/components/soc/esp32c61/include/soc/uart_struct.h +++ b/components/soc/esp32c61/include/soc/uart_struct.h @@ -442,7 +442,7 @@ typedef union { /** clkdiv : R/W; bitpos: [11:0]; default: 694; * Configures the integral part of the divisor for baud rate generation. */ - uint32_t clkdiv:12; + uint32_t clkdiv_int:12; uint32_t reserved_12:8; /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; * Configures the fractional part of the divisor for baud rate generation. @@ -1294,7 +1294,7 @@ typedef union { } uart_id_reg_t; -typedef struct { +typedef struct uart_dev_s { volatile uart_fifo_reg_t fifo; volatile uart_int_raw_reg_t int_raw; volatile uart_int_st_reg_t int_st; diff --git a/components/soc/esp32c61/include/soc/wdev_reg.h b/components/soc/esp32c61/include/soc/wdev_reg.h new file mode 100644 index 0000000000..180ec72469 --- /dev/null +++ b/components/soc/esp32c61/include/soc/wdev_reg.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc.h" +#include "soc/lpperi_reg.h" + +/* Hardware random number generator register */ +#define WDEV_RND_REG LPPERI_RNG_DATA_REG diff --git a/components/soc/esp32c61/include/soc/xts_aes_reg.h b/components/soc/esp32c61/include/soc/xts_aes_reg.h new file mode 100644 index 0000000000..55e0e19beb --- /dev/null +++ b/components/soc/esp32c61/include/soc/xts_aes_reg.h @@ -0,0 +1,128 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define XTS_AES_PLAIN 0xFFFFFFFF +#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S)) +#define XTS_AES_PLAIN_V 0xFFFFFFFF +#define XTS_AES_PLAIN_S 0 + +#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define XTS_AES_LINESIZE 0x00000003 +#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S)) +#define XTS_AES_LINESIZE_V 0x3 +#define XTS_AES_LINESIZE_S 0 + +#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryptio +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define XTS_AES_DESTINATION (BIT(0)) +#define XTS_AES_DESTINATION_M (BIT(0)) +#define XTS_AES_DESTINATION_V 0x1 +#define XTS_AES_DESTINATION_S 0 + +#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF +#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S)) +#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF +#define XTS_AES_PHYSICAL_ADDRESS_S 0 + +#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryptio +n status becomes 2..*/ +#define XTS_AES_TRIGGER (BIT(0)) +#define XTS_AES_TRIGGER_M (BIT(0)) +#define XTS_AES_TRIGGER_V 0x1 +#define XTS_AES_TRIGGER_S 0 + +#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define XTS_AES_RELEASE (BIT(0)) +#define XTS_AES_RELEASE_M (BIT(0)) +#define XTS_AES_RELEASE_V 0x1 +#define XTS_AES_RELEASE_S 0 + +#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define XTS_AES_DESTROY (BIT(0)) +#define XTS_AES_DESTROY_M (BIT(0)) +#define XTS_AES_DESTROY_V 0x1 +#define XTS_AES_DESTROY_S 0 + +#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define XTS_AES_STATE 0x00000003 +#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S)) +#define XTS_AES_STATE_V 0x3 +#define XTS_AES_STATE_S 0 + +#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define XTS_AES_DATE 0x3FFFFFFF +#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S)) +#define XTS_AES_DATE_V 0x3FFFFFFF + +#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4 +/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1 +#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3 +/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007 +#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S)) +#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7 +#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld index cd66133d08..c2e855216f 100644 --- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -19,7 +19,7 @@ PROVIDE ( ADC = 0x6000E000 ); PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); PROVIDE ( INTMTX = 0x60010000 ); PROVIDE ( SOC_ETM = 0x60013000 ); -PROVIDE ( PVT = 0x60019000 ); +PROVIDE ( PVT_MONITOR = 0x60019000 ); PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 ); PROVIDE ( GDMA = 0x60080000 ); PROVIDE ( GPSPI2 = 0x60081000 ); @@ -50,9 +50,9 @@ PROVIDE ( LP_TEE = 0x600B3400 ); PROVIDE ( LP_APM = 0x600B3800 ); PROVIDE ( LP_IO_MUX = 0x600B4000 ); PROVIDE ( LP_GPIO = 0x600B4400 ); -PROVIDE ( EFUSE_AND_OTP_DEBUG0= 0x600B4800 ); -PROVIDE ( EFUSE_AND_OTP_DEBUG1= 0x600B4C00 ); +PROVIDE ( EFUSE0 = 0x600B4800 ); +PROVIDE ( EFUSE1 = 0x600B4C00 ); PROVIDE ( TRACE = 0x600C0000 ); PROVIDE ( ASSIST_DEBUG = 0x600C2000 ); PROVIDE ( INTPRI = 0x600C5000 ); -PROVIDE ( CACHE_CFG = 0x600C8000 ); +PROVIDE ( CACHE = 0x600C8000 );