From 79af9d0be07979f133ce557c7cee45aa09c60055 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Fri, 7 Mar 2025 14:33:36 +0530 Subject: [PATCH] fix(hal): use typedef esp_xts_aes_psuedo_rounds_state_t for pseudo rounds mode --- .../include/hal/spi_flash_encrypted_ll.h | 5 ++- .../include/hal/spi_flash_encrypted_ll.h | 5 ++- .../include/hal/spi_flash_encrypted_ll.h | 5 ++- .../include/hal/spi_flash_encrypted_ll.h | 5 ++- .../hal/include/hal/spi_flash_encrypt_hal.h | 28 ++----------- .../hal/include/hal/spi_flash_encrypt_types.h | 39 +++++++++++++++++++ components/hal/spi_flash_encrypt_hal_iram.c | 2 +- 7 files changed, 55 insertions(+), 34 deletions(-) create mode 100644 components/hal/include/hal/spi_flash_encrypt_types.h diff --git a/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h index 4c5ed687af..561d7a0b13 100644 --- a/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h @@ -20,6 +20,7 @@ #include "soc/soc.h" #include "soc/soc_caps.h" #include "hal/assert.h" +#include "hal/spi_flash_encrypt_types.h" #ifdef __cplusplus extern "C" { @@ -155,11 +156,11 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) * @param increment increment number of pseudo rounds, zero if disable * @param key_rng_cnt update frequency of the pseudo-key, zero if disable */ -static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_MODE_PSEUDO, mode); - if (mode) { + if (mode != ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) { REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_BASE, base); REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_INC, increment); REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_RNG_CNT, key_rng_cnt); diff --git a/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h index 3a7f63b56f..0ff5ff2c92 100644 --- a/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h @@ -20,6 +20,7 @@ #include "soc/soc.h" #include "soc/soc_caps.h" #include "hal/assert.h" +#include "hal/spi_flash_encrypt_types.h" #ifdef __cplusplus extern "C" { @@ -155,13 +156,13 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) * @param increment increment number of pseudo rounds, zero if disable * @param key_rng_cnt update frequency of the pseudo-key, zero if disable */ -static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { (void) key_rng_cnt; REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_MODE_PSEUDO, mode); - if (mode) { + if (mode != ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) { REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_BASE, base); REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_INC, increment); } else { diff --git a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h index eefe8b30ab..625f6c8477 100644 --- a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h @@ -20,6 +20,7 @@ #include "soc/soc.h" #include "soc/soc_caps.h" #include "hal/assert.h" +#include "hal/spi_flash_encrypt_types.h" #include "hal/efuse_hal.h" #include "soc/chip_revision.h" @@ -158,11 +159,11 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) * @param increment increment number of pseudo rounds, zero if disable * @param key_rng_cnt update frequency of the pseudo-key, zero if disable */ -static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_MODE_PSEUDO, mode); - if (mode) { + if (mode != ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) { REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_BASE, base); REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_INC, increment); REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_RNG_CNT, key_rng_cnt); diff --git a/components/hal/esp32h21/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32h21/include/hal/spi_flash_encrypted_ll.h index 300dc9b053..37d4b06143 100644 --- a/components/hal/esp32h21/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32h21/include/hal/spi_flash_encrypted_ll.h @@ -20,6 +20,7 @@ #include "soc/soc.h" #include "soc/soc_caps.h" #include "hal/assert.h" +#include "hal/spi_flash_encrypt_types.h" #ifdef __cplusplus extern "C" { @@ -155,11 +156,11 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) * @param increment increment number of pseudo rounds, zero if disable * @param key_rng_cnt update frequency of the pseudo-key, zero if disable */ -static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_MODE_PSEUDO, mode); - if (mode) { + if (mode != ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) { REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_BASE, base); REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_INC, increment); REG_SET_FIELD(SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0), SPI_MEM_PSEUDO_RNG_CNT, key_rng_cnt); diff --git a/components/hal/include/hal/spi_flash_encrypt_hal.h b/components/hal/include/hal/spi_flash_encrypt_hal.h index df0064b44a..993a479425 100644 --- a/components/hal/include/hal/spi_flash_encrypt_hal.h +++ b/components/hal/include/hal/spi_flash_encrypt_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ // The HAL layer for SPI Flash Encryption +#include "hal/spi_flash_encrypt_types.h" #include "hal/spi_flash_encrypted_ll.h" #include "soc/soc_caps.h" @@ -19,29 +20,6 @@ extern "C" { #endif -#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND -/** - * @brief Default pseudo rounds configs of the XTS-AES accelerator - */ -typedef enum { - ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE = 0, - ESP_XTS_AES_PSEUDO_ROUNDS_LOW, - ESP_XTS_AES_PSEUDO_ROUNDS_MEDIUM, - ESP_XTS_AES_PSEUDO_ROUNDS_HIGH, -} esp_xts_aes_psuedo_rounds_state_t; - -/* The total number of pseudo-rounds randomly inserted in an XTS-AES operation are controlled by - * configuring the PSEUDO_MODE, PSEUDO_BASE, PSEUDO_INC parameters. - * Users can also set the frequency of random key updates by configuring the PSEUDO_RNG_CNT. - * Here, we would be using some pre-decided values for these parameters corresponding to the security needed. - * For more information regarding these parameters please refer the TRM. - */ -#define XTS_AES_PSEUDO_ROUNDS_BASE 4 -#define XTS_AES_PSEUDO_ROUNDS_INC 2 -#define XTS_AES_PSEUDO_ROUNDS_RNG_CNT 7 - -#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND */ - /** * @brief Enable the flash encryption */ @@ -90,7 +68,7 @@ bool spi_flash_encryption_hal_check(uint32_t address, uint32_t length); * @param increment increment number of pseudo rounds, zero if disable * @param key_rng_cnt update frequency of the pseudo-key, zero if disable */ -void spi_flash_encryption_hal_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt); +void spi_flash_encryption_hal_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt); #endif /* SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND */ #ifdef __cplusplus diff --git a/components/hal/include/hal/spi_flash_encrypt_types.h b/components/hal/include/hal/spi_flash_encrypt_types.h new file mode 100644 index 0000000000..b0340d610d --- /dev/null +++ b/components/hal/include/hal/spi_flash_encrypt_types.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND +/** + * @brief Default pseudo rounds configs of the XTS-AES accelerator + */ +typedef enum { + ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE = 0, + ESP_XTS_AES_PSEUDO_ROUNDS_LOW, + ESP_XTS_AES_PSEUDO_ROUNDS_MEDIUM, + ESP_XTS_AES_PSEUDO_ROUNDS_HIGH, +} esp_xts_aes_psuedo_rounds_state_t; + +/* The total number of pseudo-rounds randomly inserted in an XTS-AES operation are controlled by + * configuring the PSEUDO_MODE, PSEUDO_BASE, PSEUDO_INC parameters. + * Users can also set the frequency of random key updates by configuring the PSEUDO_RNG_CNT. + * Here, we would be using some pre-decided values for these parameters corresponding to the security needed. + * For more information regarding these parameters please refer the TRM. + */ +#define XTS_AES_PSEUDO_ROUNDS_BASE 4 +#define XTS_AES_PSEUDO_ROUNDS_INC 2 +#define XTS_AES_PSEUDO_ROUNDS_RNG_CNT 7 + +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND */ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/spi_flash_encrypt_hal_iram.c b/components/hal/spi_flash_encrypt_hal_iram.c index 9feb151db5..7af5a981f2 100644 --- a/components/hal/spi_flash_encrypt_hal_iram.c +++ b/components/hal/spi_flash_encrypt_hal_iram.c @@ -52,7 +52,7 @@ bool spi_flash_encryption_hal_check(uint32_t address, uint32_t length) } #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND -void spi_flash_encryption_hal_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +void spi_flash_encryption_hal_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { spi_flash_encrypt_ll_enable_pseudo_rounds(mode, base, increment, key_rng_cnt);