Merge branch 'feature/add_esp32c6_g0_components' into 'master'

ESP32C6: Add G0 components support (hal, soc, riscv, esp_common)

See merge request espressif/esp-idf!19826

components/driver/uart.c

@@ -19,7 +19,6 @@
 #include "hal/gpio_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "soc/uart_periph.h"
-#include "soc/rtc_cntl_reg.h"
 #include "driver/uart.h"
 #include "driver/gpio.h"
 #include "driver/uart_select.h"

components/esp_rom/include/esp32c6/rom/rtc.h

@@ -76,12 +76,12 @@ typedef enum {
 typedef enum {
     NO_MEAN                =  0,
     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
-    RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core*/
+    RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core (hp system)*/
-    DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core*/
+    DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core (hp system)*/
-    TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
+    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core (hp system)*/
-    TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
+    TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
-    RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
+    TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
-    INTRUSION_RESET        = 10,    /**<10, Instrusion tested to reset CPU*/
+    RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core (hp system)*/
     TG0WDT_CPU_RESET       = 11,    /**<11, Time Group0 reset CPU*/
     RTC_SW_CPU_RESET       = 12,    /**<12, Software reset CPU*/
     RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
@@ -89,17 +89,17 @@ typedef enum {
     RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
     TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
     SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
-    GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core (hp system)*/
-    EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
+    USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core (hp system)*/
-    USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core */
+    USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core (hp system)*/
-    USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core */
+    JTAG_RESET             = 24,    /**<24, jtag reset CPU*/
-    POWER_GLITCH_RESET     = 23,    /**<23, power glitch reset digital core and rtc module*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
 _Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
 _Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
 _Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
+_Static_assert((soc_reset_reason_t)SDIO_RESET == RESET_REASON_CORE_SDIO, "SDIO_RESET != RESET_REASON_CORE_SDIO");
 _Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
 _Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
 _Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
@@ -110,11 +110,10 @@ _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BR
 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
 _Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
-_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
 _Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
 _Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
 _Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
-_Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
+_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
 
 typedef enum {
     NO_SLEEP        = 0,

components/hal/CMakeLists.txt

@@ -38,7 +38,6 @@ if(NOT BOOTLOADER_BUILD)
         "spi_flash_hal.c"
         "spi_flash_hal_iram.c"
         "spi_flash_encrypt_hal_iram.c"
-        "sha_hal.c"
         "adc_hal_common.c"
         "adc_oneshot_hal.c")
 
@@ -98,6 +97,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "ecc_hal.c")
     endif()
 
+    if(CONFIG_SOC_SHA_SUPPORTED)
+        list(APPEND srcs "sha_hal.c")
+    endif()
+
     if(${target} STREQUAL "esp32")
         list(APPEND srcs
             "dac_hal.c"
@@ -173,6 +176,20 @@ if(NOT BOOTLOADER_BUILD)
               "esp32c2/brownout_hal.c"
               "esp32c2/rtc_cntl_hal.c")
     endif()
+
+    if(${target} STREQUAL "esp32c6")
+        list(APPEND srcs
+              "spi_flash_hal_gpspi.c"
+              "spi_slave_hd_hal.c"
+              "esp32c6/brownout_hal.c"
+              "esp32c6/rtc_cntl_hal.c")
+
+        # TODO: IDF-5310
+        list(REMOVE_ITEM srcs
+                "adc_oneshot_hal.c"
+                "adc_hal_common.c"
+                )
+    endif()
 endif()
 
 idf_component_register(SRCS ${srcs}

components/hal/cache_hal.c

@@ -24,6 +24,8 @@
 #include "esp32c2/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/cache.h"
 #endif
 
 /*------------------------------------------------------------------------------

components/hal/esp32/include/hal/rtc_io_ll.h

@@ -13,9 +13,7 @@
 #pragma once
 
 #include <stdlib.h>
-#include "soc/rtc_io_periph.h"
+#include "soc/rtc_periph.h"
-#include "soc/rtc_io_struct.h"
-#include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
 #define RTCIO_LL_PIN_FUNC     0

components/hal/esp32c3/include/hal/aes_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #pragma once
 
@@ -224,7 +216,7 @@ static inline void aes_ll_interrupt_enable(bool enable)
  */
 static inline void aes_ll_interrupt_clear(void)
 {
-    REG_WRITE(AES_INT_CLR_REG, 1);
+    REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
 

components/hal/esp32c6/brownout_hal.c

@@ -0,0 +1,26 @@
+
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hal/brownout_hal.h"
+#include "esp_attr.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_brownout.h"
+
+void brownout_hal_config(const brownout_hal_config_t *cfg)
+{
+    // TODO: IDF-5711
+}
+
+void brownout_hal_intr_enable(bool enable)
+{
+    // TODO: IDF-5711
+}
+
+IRAM_ATTR void brownout_hal_intr_clear(void)
+{
+    // TODO: IDF-5711
+}

components/hal/esp32c6/efuse_hal.c

@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include <sys/param.h>
+#include "soc/soc_caps.h"
+#include "hal/assert.h"
+#include "hal/efuse_hal.h"
+#include "hal/efuse_ll.h"
+
+#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
+#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
+
+uint32_t efuse_hal_get_major_chip_version(void)
+{
+    return efuse_ll_get_chip_wafer_version_major();
+}
+
+uint32_t efuse_hal_get_minor_chip_version(void)
+{
+    return efuse_ll_get_chip_wafer_version_minor();
+}
+
+/******************* eFuse control functions *************************/
+
+void efuse_hal_set_timing(uint32_t apb_freq_hz)
+{
+    (void) apb_freq_hz;
+    efuse_ll_set_pwr_off_num(0x190);
+}
+
+void efuse_hal_read(void)
+{
+    efuse_hal_set_timing(0);
+
+    efuse_ll_set_conf_read_op_code();
+    efuse_ll_set_read_cmd();
+
+    while (efuse_ll_get_read_cmd() != 0) { }
+    /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
+    while (efuse_ll_get_read_cmd() != 0) { }
+}
+
+void efuse_hal_clear_program_registers(void)
+{
+    ets_efuse_clear_program_registers();
+}
+
+void efuse_hal_program(uint32_t block)
+{
+    efuse_hal_set_timing(0);
+
+    efuse_ll_set_conf_write_op_code();
+    efuse_ll_set_pgm_cmd(block);
+
+    while (efuse_ll_get_pgm_cmd() != 0) { }
+
+    efuse_hal_clear_program_registers();
+    efuse_hal_read();
+}
+
+void efuse_hal_rs_calculate(const void *data, void *rs_values)
+{
+    ets_efuse_rs_calculate(data, rs_values);
+}
+
+/******************* eFuse control functions *************************/
+
+bool efuse_hal_is_coding_error_in_block(unsigned block)
+{
+    if (block == 0) {
+        for (unsigned i = 0; i < 5; i++) {
+            if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
+                return true;
+            }
+        }
+    } else if (block <= 10) {
+        // The order of error in these regs is different only for the C3 chip.
+        // Fail bit (mask=0x8):
+        // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
+        // EFUSE_RD_RS_ERR1_REG:                                                      BLOCK9, BLOCK8
+        // Error num bits (mask=0x7):
+        // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
+        // EFUSE_RD_RS_ERR1_REG:                                                      BLOCK10, BLOCK9
+        // BLOCK10 is not presented in the error regs.
+        uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
+        uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
+        return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
+    }
+    return false;
+}

components/hal/esp32c6/include/hal/cache_ll.h

@@ -0,0 +1,197 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for Cache register operations
+
+#pragma once
+
+#include "soc/extmem_reg.h"
+#include "soc/ext_mem_defs.h"
+#include "hal/cache_types.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define CACHE_LL_DEFAULT_IBUS_MASK                  CACHE_BUS_IBUS0
+#define CACHE_LL_DEFAULT_DBUS_MASK                  CACHE_BUS_DBUS0
+
+#define CACHE_LL_L1_ACCESS_EVENT_MASK               (0x3f)
+#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC         (1<<5)
+#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT        (1<<4)
+#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC    (1<<3)
+#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT        (1<<2)
+#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC         (1<<1)
+#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC    (1<<0)
+
+#define CACHE_LL_L1_ILG_EVENT_MASK                  (0x23)
+#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT       (1<<5)
+#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT      (1<<1)
+#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT         (1<<0)
+
+
+/**
+ * @brief Get the buses of a particular cache that are mapped to a virtual address range
+ *
+ * External virtual address can only be accessed when the involved cache buses are enabled.
+ * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
+ *
+ * @param cache_id          cache ID (when l1 cache is per core)
+ * @param vaddr_start       virtual address start
+ * @param len               vaddr length
+ */
+#if !BOOTLOADER_BUILD
+__attribute__((always_inline))
+#endif
+static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
+{
+    HAL_ASSERT(cache_id == 0);
+    cache_bus_mask_t mask = 0;
+
+    uint32_t vaddr_end = vaddr_start + len - 1;
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
+        mask |= CACHE_BUS_IBUS0;
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
+        mask |= CACHE_BUS_DBUS0;
+    } else {
+        HAL_ASSERT(0);          //Out of region
+    }
+
+    return mask;
+}
+
+/**
+ * Enable the Cache Buses
+ *
+ * @param cache_id    cache ID (when l1 cache is per core)
+ * @param mask        To know which buses should be enabled
+ */
+#if !BOOTLOADER_BUILD
+__attribute__((always_inline))
+#endif
+static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
+{
+    HAL_ASSERT(cache_id == 0);
+    //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
+    HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
+
+    uint32_t ibus_mask = 0;
+    ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0;
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask);
+
+    uint32_t dbus_mask = 0;
+    dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0;
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask);
+}
+
+/**
+ * Disable the Cache Buses
+ *
+ * @param cache_id    cache ID (when l1 cache is per core)
+ * @param mask        To know which buses should be disabled
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
+{
+    HAL_ASSERT(cache_id == 0);
+    //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
+    HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
+
+    uint32_t ibus_mask = 0;
+    ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0;
+    REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask);
+
+    uint32_t dbus_mask = 0;
+    dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0;
+    REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask);
+}
+
+/*------------------------------------------------------------------------------
+ * Interrupt
+ *----------------------------------------------------------------------------*/
+/**
+ * @brief Enable Cache access error interrupt
+ *
+ * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // TODO: IDF-5656
+    // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask);
+}
+
+/**
+ * @brief Clear Cache access error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // TODO: IDF-5656
+    // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask);
+}
+
+/**
+ * @brief Get Cache access error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param mask        Interrupt mask
+ *
+ * @return            Status mask
+ */
+static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
+{
+    // TODO: IDF-5656
+    // return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask);
+    return 0;
+}
+
+/**
+ * @brief Enable Cache illegal error interrupt
+ *
+ * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // TODO: IDF-5656
+    // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask);
+}
+
+/**
+ * @brief Clear Cache illegal error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // TODO: IDF-5656
+    // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask);
+}
+
+/**
+ * @brief Get Cache illegal error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param mask        Interrupt mask
+ *
+ * @return            Status mask
+ */
+static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask)
+{
+    // TODO: IDF-5656
+    // return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
+    return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/clk_gate_ll.h

@@ -0,0 +1,322 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/periph_defs.h"
+#include "soc/pcr_reg.h"
+#include "soc/dport_access.h"
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
+{ // TODO: IDF-5713
+    switch (periph) {
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_CLK_EN;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_CLK_EN;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_CLK_EN;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_CLK_EN;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_CLK_EN;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C_CLK_EN;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_CLK_EN;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TG0_CLK_EN;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TG1_CLK_EN;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_CLK_EN;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_CLK_EN;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_CLK_EN;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_CLK_EN;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_CLK_EN;
+        case PERIPH_TWAI1_MODULE:
+            return PCR_TWAI1_CLK_EN;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_CLK_EN;
+        case PERIPH_AES_MODULE:
+            return PCR_AES_CLK_EN;
+        case PERIPH_SHA_MODULE:
+            return PCR_SHA_CLK_EN;
+        case PERIPH_RSA_MODULE:
+            return PCR_RSA_CLK_EN;
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_CLK_EN;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_CLK_EN;
+        // case PERIPH_RNG_MODULE:
+        //     return PCR_WIFI_CLK_RNG_EN;
+        // case PERIPH_WIFI_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_EN_M;
+        // case PERIPH_BT_MODULE:
+        //     return PCR_WIFI_CLK_BT_EN_M;
+        // case PERIPH_WIFI_BT_COMMON_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_BT_COMMON_M;
+        // case PERIPH_BT_BASEBAND_MODULE:
+        //     return PCR_BT_BASEBAND_EN;
+        // case PERIPH_BT_LC_MODULE:
+        //     return PCR_BT_LC_EN;
+        default:
+            return 0;
+    }
+}
+
+static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable)
+{ // TODO: IDF-5713
+    (void)enable; // unused
+
+    switch (periph) {
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_RST_EN;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_RST_EN;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_RST_EN;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_RST_EN;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_RST_EN;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C_RST_EN;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_RST_EN;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TG0_RST_EN;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TG1_RST_EN;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_RST_EN;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_RST_EN;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_RST_EN;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_RST_EN;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_RST_EN;
+        case PERIPH_TWAI1_MODULE:
+            return PCR_TWAI1_RST_EN;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_RST_EN;
+        case PERIPH_AES_MODULE:
+        if (enable == true) {
+            // Clear reset on digital signature, otherwise AES unit is held in reset also.
+                return (PCR_AES_RST_EN | PCR_DS_RST_EN);
+        } else {
+                //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
+                return PCR_AES_RST_EN;
+        }
+        case PERIPH_SHA_MODULE:
+        if (enable == true) {
+            // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
+                return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
+        } else {
+            // Don't assert reset on secure boot, otherwise AES is held in reset
+                return PCR_SHA_RST_EN;
+        }
+        case PERIPH_RSA_MODULE:
+        if (enable == true) {
+            /* also clear reset on digital signature, otherwise RSA is held in reset */
+                return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
+        } else {
+            /* don't reset digital signature unit, as this resets AES also */
+                return PCR_RSA_RST_EN;
+        }
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_RST_EN;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_RST_EN;
+        // case PERIPH_RNG_MODULE:
+        //     return PCR_WIFI_CLK_RNG_EN;
+        // case PERIPH_WIFI_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_EN_M;
+        // case PERIPH_BT_MODULE:
+        //     return PCR_WIFI_CLK_BT_EN_M;
+        // case PERIPH_WIFI_BT_COMMON_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_BT_COMMON_M;
+        // case PERIPH_BT_BASEBAND_MODULE:
+        //     return PCR_BT_BASEBAND_EN;
+        // case PERIPH_BT_LC_MODULE:
+        //     return PCR_BT_LC_EN;
+        default:
+            return 0;
+    }
+}
+
+static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
+{ // TODO: IDF-5713
+    switch (periph) {
+    // case PERIPH_RNG_MODULE:
+    // case PERIPH_WIFI_MODULE:
+    // case PERIPH_BT_MODULE:
+    // case PERIPH_WIFI_BT_COMMON_MODULE:
+    // case PERIPH_BT_BASEBAND_MODULE:
+    // case PERIPH_BT_LC_MODULE:
+    //      return SYSTEM_WIFI_CLK_EN_REG;
+
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_CONF_REG;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_CONF_REG;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_CONF_REG;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_CONF_REG;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_CONF_REG;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C_CONF_REG;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_CONF_REG;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TIMERGROUP0_CONF_REG;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TIMERGROUP1_CONF_REG;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_CONF_REG;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_CONF_REG;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_CONF_REG;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_CONF_REG;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_CONF_REG;
+        case PERIPH_TWAI1_MODULE:
+            return PCR_TWAI1_CONF_REG;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_CONF_REG;
+        case PERIPH_AES_MODULE:
+            return PCR_AES_CONF_REG;
+        case PERIPH_SHA_MODULE:
+            return PCR_SHA_CONF_REG;
+        case PERIPH_RSA_MODULE:
+            return PCR_RSA_CONF_REG;
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_CONF_REG;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_CONF_REG;
+    default:
+        return 0;
+    }
+}
+
+static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
+{ // TODO: IDF-5713
+    switch (periph) {
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_CONF_REG;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_CONF_REG;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_CONF_REG;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_CONF_REG;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_CONF_REG;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C_CONF_REG;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_CONF_REG;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TIMERGROUP0_CONF_REG;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TIMERGROUP1_CONF_REG;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_CONF_REG;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_CONF_REG;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_CONF_REG;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_CONF_REG;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_CONF_REG;
+        case PERIPH_TWAI1_MODULE:
+            return PCR_TWAI1_CONF_REG;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_CONF_REG;
+        case PERIPH_AES_MODULE:
+            return PCR_AES_CONF_REG;
+        case PERIPH_SHA_MODULE:
+            return PCR_SHA_CONF_REG;
+        case PERIPH_RSA_MODULE:
+            return PCR_RSA_CONF_REG;
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_CONF_REG;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_CONF_REG;
+    default:
+        return 0;
+    }
+}
+
+static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
+{
+    DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
+}
+
+static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
+{
+    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+}
+
+static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void)
+{
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// TODO: IDF-5679
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void)
+{
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// TODO: IDF-5679
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void periph_ll_reset(periph_module_t periph)
+{
+    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+}
+
+static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
+{
+    return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
+           DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
+}
+
+static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
+{
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); // TODO: IDF-5679
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
+{
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); // TODO: IDF-5679
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/clk_tree_ll.h

@@ -0,0 +1,511 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/rtc.h"
+#include "soc/pcr_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
+#include "hal/assert.h"
+#include "hal/log.h"
+#include "esp32c6/rom/rtc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MHZ                 (1000000)
+
+#define CLK_LL_PLL_80M_FREQ_MHZ    (80)
+#define CLK_LL_PLL_160M_FREQ_MHZ   (160)
+
+#define CLK_LL_PLL_320M_FREQ_MHZ   (320)
+#define CLK_LL_PLL_480M_FREQ_MHZ   (480)
+
+#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
+    .dac = 3, \
+    .dres = 3, \
+    .dgm = 3, \
+    .dbuf = 1, \
+}
+
+/**
+ * @brief XTAL32K_CLK enable modes
+ */
+typedef enum {
+    CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL,       //!< Enable the external 32kHz crystal for XTAL32K_CLK
+    CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL,      //!< Enable the external clock signal for XTAL32K_CLK
+    CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP,     //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */
+} clk_ll_xtal32k_enable_mode_t;
+
+/**
+ * @brief XTAL32K_CLK configuration structure
+ */
+typedef struct {
+    uint32_t dac : 6;
+    uint32_t dres : 3;
+    uint32_t dgm : 3;
+    uint32_t dbuf: 1;
+} clk_ll_xtal32k_config_t;
+
+/**
+ * @brief Power up BBPLL circuit
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Power down BBPLL circuit
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Enable the 32kHz crystal oscillator
+ *
+ * @param mode Used to determine the xtal32k configuration parameters
+ */
+static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Disable the 32kHz crystal oscillator
+ */
+static inline void clk_ll_xtal32k_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the state of the 32kHz crystal clock
+ *
+ * @return True if the 32kHz XTAL is enabled
+ */
+static inline bool clk_ll_xtal32k_is_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Enable the internal oscillator output for RC_FAST_CLK
+ */
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Disable the internal oscillator output for RC_FAST_CLK
+ */
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the state of the internal oscillator for RC_FAST_CLK
+ *
+ * @return True if the oscillator is enabled
+ */
+static inline bool clk_ll_rc_fast_is_enabled(void)
+{
+    // TODO: IDF-5645
+    return 1;
+}
+
+/**
+ * @brief Enable the output from the internal oscillator to be passed into a configurable divider,
+ * which by default divides the input clock frequency by 256. i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256
+ *
+ * Divider values other than 256 may be configured, but this facility is not currently needed,
+ * so is not exposed in the code.
+ * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
+ */
+static inline void clk_ll_rc_fast_d256_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Disable the output from the internal oscillator to be passed into a configurable divider.
+ * i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256
+ *
+ * Disabling this divider could reduce power consumption.
+ */
+static inline void clk_ll_rc_fast_d256_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the state of the divider which is applied to the output from the internal oscillator (RC_FAST_CLK)
+ *
+ * @return True if the divided output is enabled
+ */
+static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+{
+    // TODO: IDF-5645
+    return 1;
+}
+
+/**
+ * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_digi_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_digi_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the state of the digital RC_FAST_CLK
+ *
+ * @return True if the digital RC_FAST_CLK is enabled
+ */
+static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_d256_digi_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_d256_digi_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_xtal32k_digi_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_xtal32k_digi_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the state of the digital XTAL32K_CLK
+ *
+ * @return True if the digital XTAL32K_CLK is enabled
+ */
+static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Get PLL_CLK frequency
+ *
+ * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Set BBPLL frequency from XTAL source (Digital part)
+ *
+ * @param pll_freq_mhz PLL frequency, in MHz
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Set BBPLL frequency from XTAL source (Analog part)
+ *
+ * @param pll_freq_mhz PLL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Select the clock source for CPU_CLK
+ *
+ * @param in_sel One of the clock sources in soc_cpu_clk_src_t
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
+{
+    // TODO: IDF-5645
+    switch (in_sel) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 0);
+        break;
+    case SOC_CPU_CLK_SRC_PLL:
+        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1);
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 2);
+        break;
+    default:
+        // Unsupported CPU_CLK mux input sel
+        abort();
+    }
+}
+
+/**
+ * @brief Get the clock source for CPU_CLK
+ *
+ * @return Currently selected clock source (one of soc_cpu_clk_src_t values)
+ */
+static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
+{
+    // TODO: IDF-5645
+    uint32_t clk_sel = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL);
+    switch (clk_sel) {
+    case 0:
+        return SOC_CPU_CLK_SRC_XTAL;
+    case 1:
+        return SOC_CPU_CLK_SRC_PLL;
+    case 2:
+        return SOC_CPU_CLK_SRC_RC_FAST;
+    default:
+        // Invalid SOC_CLK_SEL value
+        return SOC_CPU_CLK_SRC_INVALID;
+    }
+}
+
+/**
+ * @brief Set CPU frequency from PLL clock
+ *
+ * @param cpu_mhz CPU frequency value, in MHz
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_freq_mhz_from_pll(uint32_t cpu_mhz)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get CPU_CLK frequency from PLL_CLK source
+ *
+ * @return CPU clock frequency, in MHz. Returns 0 if register field value is invalid.
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_freq_mhz_from_pll(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Set CPU_CLK's XTAL/FAST_RC clock source path divider
+ *
+ * @param divider Divider. Usually this divider is set to 1 in bootloader stage. PRE_DIV_CNT = divider - 1.
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
+{
+    // TODO: IDF-5645  not configurable for 761, fixed at 3 for HS, 1 for LS
+}
+
+/**
+ * @brief Get CPU_CLK's XTAL/FAST_RC clock source path divider
+ *
+ * @return Divider. Divider = (PRE_DIV_CNT + 1).
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Select the clock source for RTC_SLOW_CLK
+ *
+ * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
+ */
+static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the clock source for RTC_SLOW_CLK
+ *
+ * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Select the clock source for RTC_FAST_CLK
+ *
+ * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
+ */
+static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get the clock source for RTC_FAST_CLK
+ *
+ * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX.
+ *
+ * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
+ */
+static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Get RC_FAST_CLK divider
+ *
+ * @return Divider. Divider = (CK8M_DIV_SEL + 1).
+ */
+static inline uint32_t clk_ll_rc_fast_get_divider(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Set RC_SLOW_CLK divider
+ *
+ * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
+ */
+static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+{
+    // TODO: IDF-5645
+}
+
+/************************* RTC STORAGE REGISTER STORE/LOAD **************************/
+/**
+ * @brief Store XTAL_CLK frequency in RTC storage register
+ *
+ * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @param xtal_freq_mhz XTAL frequency, in MHz
+ */
+static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Load XTAL_CLK frequency from RTC storage register
+ *
+ * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid.
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Store APB_CLK frequency in RTC storage register
+ *
+ * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @param apb_freq_hz APB frequency, in Hz
+ */
+static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_hz)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Load APB_CLK frequency from RTC storage register
+ *
+ * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @return The stored APB frequency, in Hz
+ */
+static inline uint32_t clk_ll_apb_load_freq_hz(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+/**
+ * @brief Store RTC_SLOW_CLK calibration value in RTC storage register
+ *
+ * Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ *
+ * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
+ */
+static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register
+ *
+ * This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches
+ *
+ * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
+ */
+static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/efuse_hal.h

@@ -0,0 +1,69 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include_next "hal/efuse_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief get chip version
+ */
+uint32_t efuse_hal_get_chip_revision(void);
+
+/**
+ * @brief set eFuse timings
+ *
+ * @param apb_freq_hz APB frequency in Hz
+ */
+void efuse_hal_set_timing(uint32_t apb_freq_hz);
+
+/**
+ * @brief trigger eFuse read operation
+ */
+void efuse_hal_read(void);
+
+/**
+ * @brief clear registers for programming eFuses
+ */
+void efuse_hal_clear_program_registers(void);
+
+/**
+ * @brief burn eFuses written in programming registers (one block at once)
+ *
+ * @param block block number
+ */
+void efuse_hal_program(uint32_t block);
+
+/**
+ * @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
+ *
+ * @param data Pointer to data buffer (length 32 bytes)
+ * @param rs_values Pointer to write encoded data to (length 12 bytes)
+ */
+void efuse_hal_rs_calculate(const void *data, void *rs_values);
+
+/**
+ * @brief Checks coding error in a block
+ *
+ * @param block Index of efuse block
+ *
+ * @return True  - block has an error.
+ *         False - no error.
+ */
+bool efuse_hal_is_coding_error_in_block(unsigned block);
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/efuse_ll.h

@@ -0,0 +1,133 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/efuse_periph.h"
+#include "hal/assert.h"
+#include "esp32c6/rom/efuse.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Always inline these functions even no gcc optimization is applied.
+
+/******************* eFuse fields *************************/
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
+{
+    return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
+{
+    return EFUSE.rd_repeat_data1.wdt_delay_sel;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
+{
+    return EFUSE.rd_mac_spi_sys_0.mac_0;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
+{
+    return EFUSE.rd_mac_spi_sys_1.mac_1;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
+{
+    return EFUSE.rd_repeat_data2.secure_boot_en;
+}
+
+// TODO: IDF-5341
+// __attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(void)
+// {
+//     return EFUSE.rd_repeat_data3.err_rst_enable;
+// }
+
+// use efuse_hal_get_major_chip_version() to get major chip version
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
+{
+    return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
+}
+
+// use efuse_hal_get_minor_chip_version() to get minor chip version
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
+{
+    return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
+{
+    return EFUSE.rd_repeat_data4.disable_wafer_version_major;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
+{
+    return EFUSE.rd_sys_part1_data4.blk_version_major;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
+{
+    return EFUSE.rd_mac_spi_sys_3.blk_version_minor;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
+{
+    return EFUSE.rd_repeat_data4.disable_blk_version_major;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
+{
+    return EFUSE.rd_mac_spi_sys_3.pkg_version;
+}
+
+/******************* eFuse control functions *************************/
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
+{
+    return EFUSE.cmd.read_cmd;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
+{
+    return EFUSE.cmd.pgm_cmd;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
+{
+    EFUSE.cmd.read_cmd = 1;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
+{
+    HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
+    EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
+{
+    EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
+{
+    EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
+{
+    EFUSE.wr_tim_conf2.pwr_off_num = value;
+}
+
+/******************* eFuse control functions *************************/
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/gdma_ll.h

@@ -0,0 +1,468 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stddef.h> /* Required for NULL constant */
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/gdma_struct.h"
+#include "soc/gdma_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
+
+#define GDMA_LL_RX_EVENT_MASK       (0x7F)
+#define GDMA_LL_TX_EVENT_MASK       (0x3F)
+
+#define GDMA_LL_EVENT_TX_FIFO_UDF   (1<<5)
+#define GDMA_LL_EVENT_TX_FIFO_OVF   (1<<4)
+#define GDMA_LL_EVENT_RX_FIFO_UDF   (1<<6)
+#define GDMA_LL_EVENT_RX_FIFO_OVF   (1<<5)
+#define GDMA_LL_EVENT_TX_TOTAL_EOF  (1<<3)
+#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
+#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
+#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
+#define GDMA_LL_EVENT_TX_EOF        (1<<1)
+#define GDMA_LL_EVENT_TX_DONE       (1<<0)
+#define GDMA_LL_EVENT_RX_ERR_EOF    (1<<2)
+#define GDMA_LL_EVENT_RX_SUC_EOF    (1<<1)
+#define GDMA_LL_EVENT_RX_DONE       (1<<0)
+
+///////////////////////////////////// Common /////////////////////////////////////////
+/**
+ * @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default
+ */
+static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.mem_trans_en = enable;
+    if (enable) {
+        // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value
+        dev->channel[channel].in.in_peri_sel.peri_in_sel = 0;
+        dev->channel[channel].out.out_peri_sel.peri_out_sel = 0;
+    }
+}
+
+/**
+ * @brief Enable DMA clock gating
+ */
+static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
+{
+    dev->misc_conf.clk_en = enable;
+}
+
+///////////////////////////////////// RX /////////////////////////////////////////
+/**
+ * @brief Get DMA RX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->in_intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
+}
+
+/**
+ * @brief Enable DMA RX channel interrupt
+ */
+static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->in_intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);
+    } else {
+        dev->in_intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK);
+    }
+}
+
+/**
+ * @brief Clear DMA RX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->in_intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK);
+}
+
+/**
+ * @brief Get DMA RX channel interrupt status register address
+ */
+static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->in_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf1.in_check_owner = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading data, disabled by default
+ */
+static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_data_burst_en = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
+ */
+static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.indscr_burst_en = enable;
+}
+
+/**
+ * @brief Reset DMA RX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_conf0.in_rst = 1;
+    dev->channel[channel].in.in_conf0.in_rst = 0;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in RX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.infifo_cnt;
+}
+
+/**
+ * @brief Pop data from DMA RX FIFO
+ */
+static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_pop.infifo_pop = 1;
+    return dev->channel[channel].in.in_pop.infifo_rdata;
+}
+
+/**
+ * @brief Set the descriptor link base address for RX channel
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->channel[channel].in.in_link.inlink_addr = addr;
+}
+
+/**
+ * @brief Start dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_start = 1;
+}
+
+/**
+ * @brief Stop dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_stop = 1;
+}
+
+/**
+ * @brief Restart a new inlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_restart = 1;
+}
+
+/**
+ * @brief Enable DMA RX to return the address of current descriptor when receives error
+ */
+static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_link.inlink_auto_ret = enable;
+}
+
+/**
+ * @brief Check if DMA RX FSM is in IDLE state
+ */
+static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_link.inlink_park;
+}
+
+/**
+ * @brief Get RX success EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_suc_eof_des_addr.val;
+}
+
+/**
+ * @brief Get RX error EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_err_eof_des_addr.val;
+}
+
+/**
+ * @brief Get current RX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA RX channel
+ */
+static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].in.in_pri.rx_pri = prio;
+}
+
+/**
+ * @brief Connect DMA RX channel to a given peripheral
+ */
+static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
+{
+    dev->channel[channel].in.in_peri_sel.peri_in_sel = periph_id;
+}
+
+///////////////////////////////////// TX /////////////////////////////////////////
+/**
+ * @brief Get DMA TX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->out_intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
+}
+
+/**
+ * @brief Enable DMA TX channel interrupt
+ */
+static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->out_intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK);
+    } else {
+        dev->out_intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK);
+    }
+}
+
+/**
+ * @brief Clear DMA TX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->out_intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK);
+}
+
+/**
+ * @brief Get DMA TX channel interrupt status register address
+ */
+static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->out_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf1.out_check_owner = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst sending data, disabled by default
+ */
+static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_data_burst_en = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst reading descriptor link, disabled by default
+ */
+static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.outdscr_burst_en = enable;
+}
+
+/**
+ * @brief Set TX channel EOF mode
+ */
+static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
+{
+    dev->channel[channel].out.out_conf0.out_eof_mode = mode;
+}
+
+/**
+ * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
+ */
+static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_auto_wrback = enable;
+}
+
+/**
+ * @brief Reset DMA TX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_conf0.out_rst = 1;
+    dev->channel[channel].out.out_conf0.out_rst = 0;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in TX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.outfifo_cnt;
+}
+
+/**
+ * @brief Push data into DMA TX FIFO
+ */
+static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
+{
+    dev->channel[channel].out.out_push.outfifo_wdata = data;
+    dev->channel[channel].out.out_push.outfifo_push = 1;
+}
+
+/**
+ * @brief Set the descriptor link base address for TX channel
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->channel[channel].out.out_link.outlink_addr = addr;
+}
+
+/**
+ * @brief Start dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_start = 1;
+}
+
+/**
+ * @brief Stop dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_stop = 1;
+}
+
+/**
+ * @brief Restart a new outlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_restart = 1;
+}
+
+/**
+ * @brief Check if DMA TX FSM is in IDLE state
+ */
+static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_link.outlink_park;
+}
+
+/**
+ * @brief Get TX EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_eof_des_addr.val;
+}
+
+/**
+ * @brief Get current TX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA TX channel
+ */
+static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].out.out_pri.tx_pri = prio;
+}
+
+/**
+ * @brief Connect DMA TX channel to a given peripheral
+ */
+static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
+{
+    dev->channel[channel].out.out_peri_sel.peri_out_sel = periph_id;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/gpio_ll.h

@@ -0,0 +1,601 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+// The LL layer for ESP32-C6 GPIO register operations
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/gpio_periph.h"
+#include "soc/gpio_struct.h"
+#include "soc/lp_aon_reg.h"
+#include "soc/lp_io_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/usb_serial_jtag_reg.h"
+#include "hal/gpio_types.h"
+#include "hal/assert.h"
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get GPIO hardware instance with giving gpio num
+#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
+
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+/**
+  * @brief Enable pull-up on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+}
+
+/**
+  * @brief Disable pull-up on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+}
+
+/**
+  * @brief Enable pull-down on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+}
+
+/**
+  * @brief Disable pull-down on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
+    // USB DP pin is default to PU enabled
+    // Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
+    // which should be checked is USB_DM_GPIO_NUM instead.
+    // if (gpio_num == USB_DP_GPIO_NUM) {     // TODO: IDF-5321 find out pin number
+    //     SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
+    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
+    // }
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+}
+
+/**
+ * @brief  GPIO set interrupt trigger type
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  intr_type Interrupt type, select from gpio_int_type_t
+ */
+static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
+{
+    hw->pin[gpio_num].int_type = intr_type;
+}
+
+/**
+  * @brief Get GPIO interrupt status
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param core_id interrupt core id
+  * @param status interrupt status
+  */
+__attribute__((always_inline))
+static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
+{
+    (void)core_id;
+    *status = hw->pcpu_int.procpu_int;
+}
+
+/**
+  * @brief Get GPIO interrupt status high
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param core_id interrupt core id
+  * @param status interrupt status high
+  */
+__attribute__((always_inline))
+static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
+{
+    *status = 0; // Less than 32 GPIOs in ESP32-C6
+}
+
+/**
+  * @brief Clear GPIO interrupt status
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param mask interrupt status clear mask
+  */
+__attribute__((always_inline))
+static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
+{
+    hw->status_w1tc.status_w1tc = mask;
+}
+
+/**
+  * @brief Clear GPIO interrupt status high
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param mask interrupt status high clear mask
+  */
+__attribute__((always_inline))
+static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
+{
+    // Less than 32 GPIOs on ESP32-C6 Do nothing.
+}
+
+/**
+ * @brief  Enable GPIO module interrupt signal
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  core_id Interrupt enabled CPU to corresponding ID
+ * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ */
+__attribute__((always_inline))
+static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
+{
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
+    GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+}
+
+/**
+ * @brief  Disable GPIO module interrupt signal
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ */
+__attribute__((always_inline))
+static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
+}
+
+/**
+  * @brief Disable input mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable input mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable output mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
+    // Ensure no other output signal is routed via GPIO matrix to this pin
+    REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
+              SIG_GPIO_OUT_IDX);
+}
+
+/**
+  * @brief Enable output mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
+}
+
+/**
+  * @brief Disable open-drain mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->pin[gpio_num].pad_driver = 0;
+}
+
+/**
+  * @brief Enable open-drain mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->pin[gpio_num].pad_driver = 1;
+}
+
+/**
+ * @brief  GPIO set output level
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  level Output level. 0: low ; 1: high
+ */
+__attribute__((always_inline))
+static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
+{
+    if (level) {
+        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+    } else {
+        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+    }
+}
+
+/**
+ * @brief  GPIO get input level
+ *
+ * @warning If the pad is not configured for input (or input and output) the returned value is always 0.
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ *
+ * @return
+ *     - 0 the GPIO input level is 0
+ *     - 1 the GPIO input level is 1
+ */
+static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    return (hw->in.in_data_next >> gpio_num) & 0x1;
+}
+
+/**
+ * @brief Enable GPIO wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number.
+ */
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->pin[gpio_num].wakeup_enable = 0x1;
+}
+
+/**
+ * @brief Disable GPIO wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    hw->pin[gpio_num].wakeup_enable = 0;
+}
+
+/**
+  * @brief Set GPIO pad drive capability
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Drive capability of the pad
+  */
+static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
+{
+    SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
+}
+
+/**
+  * @brief Get GPIO pad drive capability
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Pointer to accept drive capability of the pad
+  */
+static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
+{
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+}
+
+/**
+  * @brief Enable all digital gpio pad hold function during Deep-sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  */
+static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
+{
+    // ESP32C6 has removed deepsleep and replace with software backup sleep
+    // TODO: IDF-5321
+}
+
+/**
+  * @brief Disable all digital gpio pad hold function during Deep-sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  */
+static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
+{
+    // ESP32C6 has removed deepsleep and replace with software backup sleep
+    // TODO: IDF-5321
+}
+
+/**
+  * @brief Enable gpio pad hold function.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  */
+static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // if (gpio_num <32) {
+    //     SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
+    // } else if (gpio_num <= MAX_PAD_GPIO_NUM) {
+    //     SET_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
+    // }
+}
+
+/**
+  * @brief Disable gpio pad hold function.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  */
+static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // if (gpio_num <32) {
+    //     CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
+    // } else if (gpio_num <= MAX_PAD_GPIO_NUM) {
+    //     CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
+    // }
+}
+
+/**
+  * @brief Set pad input to a peripheral signal through the IOMUX.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number of the pad.
+  * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
+  */
+static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
+{
+    hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
+}
+
+/**
+ * @brief  Select a function for the pin in the IOMUX
+ *
+ * @param  pin_name Pin name to configure
+ * @param  func Function to assign to the pin
+ */
+static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
+{
+    // TODO: IDF-5321
+    // // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
+    // if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
+    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
+    // }
+    // PIN_FUNC_SELECT(pin_name, func);
+}
+
+/**
+  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num gpio_num GPIO number of the pad.
+  * @param func The function number of the peripheral pin to output pin.
+  *        One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
+  * @param oen_inv True if the output enable needs to be inverted, otherwise False.
+  */
+static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
+{
+    hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
+    hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
+    gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
+}
+
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
+{
+    // TODO: IDF-5321
+    // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL);
+    // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_LP_PAD_HOLD_ALL);
+}
+
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_unhold_all(void)
+{
+    // TODO: IDF-5321
+    // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL);
+    // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_LP_PAD_HOLD_ALL);
+}
+
+/**
+  * @brief Enable GPIO pin used for wakeup from sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pin used for wakeup from sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pull-up in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO pull-up in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO pull-down in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pull-down in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO input in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO input in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO output in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO output in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // TODO: IDF-5321
+    // PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+ * @brief Enable GPIO deep-sleep wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number.
+ * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
+ */
+static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
+{
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
+    // TODO: IDF-5321
+    // SET_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE);
+    // REG_SET_FIELD(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE, intr_type);
+}
+
+/**
+ * @brief Disable GPIO deep-sleep wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
+    // TODO: IDF-5321
+    // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE);
+    // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/gpspi_flash_ll.h

@@ -0,0 +1,409 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
+#include "hal/spi_types.h"
+#include "hal/spi_flash_types.h"
+#include <sys/param.h> // For MIN/MAX
+#include <stdbool.h>
+#include <string.h>
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//NOTE: These macros are changed on c3 for build. MODIFY these when bringup flash.
+#define gpspi_flash_ll_get_hw(host_id)  ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) )
+#define gpspi_flash_ll_hw_get_id(dev)   ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 )
+
+typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
+#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ  (80)
+
+/*------------------------------------------------------------------------------
+ * Control
+ *----------------------------------------------------------------------------*/
+/**
+ * Reset peripheral registers before configuration and starting control
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
+{
+    dev->user.val = 0;
+    dev->ctrl.val = 0;
+
+    dev->clk_gate.clk_en = 1;
+    dev->clk_gate.mst_clk_active = 1;
+    dev->clk_gate.mst_clk_sel = 1;
+
+    dev->dma_conf.val = 0;
+    dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
+    dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
+    dev->dma_conf.dma_slv_seg_trans_en = 0;
+}
+
+/**
+ * Check whether the previous operation is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if last command is done, otherwise false.
+ */
+static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
+{
+    return (dev->cmd.usr == 0);
+}
+
+/**
+ * Get the read data from the buffer after ``gpspi_flash_ll_read`` is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer to hold the output data
+ * @param read_len Length to get out of the buffer
+ */
+static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
+{
+    if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
+        // If everything is word-aligned, do a faster memcpy
+        memcpy(buffer, (void *)dev->data_buf, read_len);
+    } else {
+        // Otherwise, slow(er) path copies word by word
+        int copy_len = read_len;
+        for (int i = 0; i < (read_len + 3) / 4; i++) {
+            int word_len = MIN(sizeof(uint32_t), copy_len);
+            uint32_t word = dev->data_buf[i].buf;
+            memcpy(buffer, &word, word_len);
+            buffer = (void *)((intptr_t)buffer + word_len);
+            copy_len -= word_len;
+        }
+    }
+}
+
+/**
+ * Write a word to the data buffer.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param word Data to write at address 0.
+ */
+static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
+{
+    dev->data_buf[0].buf = word;
+}
+
+/**
+ * Set the data to be written in the data buffer.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer holding the data
+ * @param length Length of data in bytes.
+ */
+static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
+{
+    // Load data registers, word at a time
+    int num_words = (length + 3) / 4;
+    for (int i = 0; i < num_words; i++) {
+        uint32_t word = 0;
+        uint32_t word_len = MIN(length, sizeof(word));
+        memcpy(&word, buffer, word_len);
+        dev->data_buf[i].buf = word;
+        length -= word_len;
+        buffer = (void *)((intptr_t)buffer + word_len);
+    }
+}
+
+/**
+ * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
+ * should be configured before this is called.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_user_start(spi_dev_t *dev)
+{
+    dev->cmd.update = 1;
+    while (dev->cmd.update);
+    dev->cmd.usr = 1;
+}
+
+/**
+ * Set HD pin high when flash work at spi mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
+{
+    dev->ctrl.hold_pol = pol_val;
+}
+
+/**
+ * Check whether the host is idle to perform new commands.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if the host is idle, otherwise false
+ */
+static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
+{
+    return dev->cmd.usr == 0;
+}
+
+/**
+ * Set phases for user-defined transaction to read
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
+{
+    typeof (dev->user) user = {
+        .usr_command = 1,
+        .usr_mosi = 0,
+        .usr_miso = 1,
+        .usr_addr = 1,
+    };
+    dev->user = user;
+}
+/*------------------------------------------------------------------------------
+ * Configs
+ *----------------------------------------------------------------------------*/
+/**
+ * Select which pin to use for the flash
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
+ */
+static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
+{
+    dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
+}
+
+/**
+ * Set the read io mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param read_mode I/O mode to use in the following transactions.
+ */
+static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
+{
+    typeof (dev->ctrl) ctrl = dev->ctrl;
+    typeof (dev->user) user = dev->user;
+
+    ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
+    user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
+
+    switch (read_mode) {
+    case SPI_FLASH_FASTRD:
+        //the default option
+    case SPI_FLASH_SLOWRD:
+        break;
+    case SPI_FLASH_QIO:
+        ctrl.fread_quad = 1;
+        ctrl.faddr_quad = 1;
+        user.fwrite_quad = 1;
+        break;
+    case SPI_FLASH_QOUT:
+        ctrl.fread_quad = 1;
+        user.fwrite_quad = 1;
+        break;
+    case SPI_FLASH_DIO:
+        ctrl.fread_dual = 1;
+        ctrl.faddr_dual = 1;
+        user.fwrite_dual = 1;
+        break;
+    case SPI_FLASH_DOUT:
+        ctrl.fread_dual = 1;
+        user.fwrite_dual = 1;
+        break;
+    default:
+        abort();
+    }
+
+    dev->ctrl = ctrl;
+    dev->user = user;
+}
+
+/**
+ * Set clock frequency to work at.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param clock_val pointer to the clock value to set
+ */
+static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val)
+{
+    dev->clock.val = *clock_val;
+}
+
+/**
+ * Set the input length, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of input, in bits.
+ */
+static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_miso = bitlen > 0;
+    if (bitlen) {
+        dev->ms_dlen.ms_data_bitlen = bitlen - 1;
+    }
+}
+
+/**
+ * Set the output length, in bits (not including command, address and dummy
+ * phases)
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of output, in bits.
+ */
+static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_mosi = bitlen > 0;
+    if (bitlen) {
+        dev->ms_dlen.ms_data_bitlen = bitlen - 1;
+    }
+}
+
+/**
+ * Set the command.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param command Command to send
+ * @param bitlen Length of the command
+ */
+static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen)
+{
+    dev->user.usr_command = 1;
+    typeof(dev->user2) user2 = {
+        .usr_command_value = command,
+        .usr_command_bitlen = (bitlen - 1),
+    };
+    dev->user2 = user2;
+}
+
+/**
+ * Get the address length that is set in register, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ */
+static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
+{
+    return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
+}
+
+/**
+ * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of the address, in bits
+ */
+static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
+{
+    dev->user1.usr_addr_bitlen = (bitlen - 1);
+    dev->user.usr_addr = bitlen ? 1 : 0;
+}
+
+/**
+ * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
+{
+    // The blank region should be all ones
+    uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
+    dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
+}
+
+/**
+ * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
+{
+    dev->addr.val = addr;
+}
+
+/**
+ * Set the length of dummy cycles.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param dummy_n Cycles of dummy phases
+ */
+static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
+{
+    dev->user.usr_dummy = dummy_n ? 1 : 0;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
+}
+
+/**
+ * Set D/Q output level during dummy phase
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param out_en whether to enable IO output for dummy phase
+ * @param out_level dummy output level
+ */
+static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev)
+{
+    dev->ctrl.dummy_out = out_en;
+    dev->ctrl.q_pol = out_lev;
+    dev->ctrl.d_pol = out_lev;
+}
+
+/**
+ * Set extra hold time of CS after the clocks.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param hold_n Cycles of clocks before CS is inactive
+ */
+static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
+{
+    dev->user1.cs_hold_time = hold_n - 1;
+    dev->user.cs_hold = (hold_n > 0? 1: 0);
+}
+
+static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
+{
+    dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    dev->user1.cs_setup_time = cs_setup_time - 1;
+}
+
+/**
+ * Calculate spi_flash clock frequency division parameters for register.
+ *
+ * @param clkdiv frequency division factor
+ *
+ * @return Register setting for the given clock division factor.
+ */
+static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
+{
+    uint32_t div_parameter;
+    // See comments of `clock` in `spi_struct.h`
+    if (clkdiv == 1) {
+        div_parameter = (1 << 31);
+    } else {
+        div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
+    }
+    return div_parameter;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/lpwdt_ll.h

@@ -0,0 +1,307 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for Timer Group register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "hal/misc.h"
+#include "hal/wdt_types.h"
+#include "soc/rtc_cntl_periph.h"
+#include "soc/efuse_reg.h"
+#include "esp_attr.h"
+
+#include "esp32c6/rom/ets_sys.h"
+
+// TODO: IDF-5717
+// //Type check wdt_stage_action_t
+// _Static_assert(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+// _Static_assert(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+// _Static_assert(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+// _Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+// _Static_assert(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+// //Type check wdt_reset_sig_length_t
+// _Static_assert(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+// _Static_assert(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+
+/**
+ * @brief Enable the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
+{
+    hw->config0.wdt_en = 1;
+}
+
+/**
+ * @brief Disable the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @note This function does not disable the flashboot mode. Therefore, given that
+ *       the MWDT is disabled using this function, a timeout can still occur
+ *       if the flashboot mode is simultaneously enabled.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
+{
+    hw->config0.wdt_en = 0;
+}
+
+/**
+ * @brief Check if the RWDT is enabled
+ *
+ * @param hw Start address of the peripheral registers.
+ * @return True if RTC WDT is enabled
+ */
+FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
+{
+    return (hw->config0.wdt_en) ? true : false;
+}
+
+/**
+ * @brief Configure a particular stage of the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to configure
+ * @param timeout Number of timer ticks for the stage to timeout (see note).
+ * @param behavior What action to take when the stage times out
+ *
+ * @note The value of of RWDT stage 0 timeout register is special, in
+ *       that an implicit multiplier is applied to that value to produce
+ *       and effective timeout tick value. The multiplier is dependent
+ *       on an EFuse value. Therefore, when configuring stage 0, the valid
+ *       values for the timeout argument are:
+ *       - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
+ *       - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
+ *       - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
+ *       - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
+{
+    switch (stage) {
+    case WDT_STAGE0:
+        hw->config0.wdt_stg0 = behavior;
+        //Account of implicty multiplier applied to stage 0 timeout tick config value
+        hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
+        break;
+    case WDT_STAGE1:
+        hw->config0.wdt_stg1 = behavior;
+        hw->config2.val = timeout_ticks;
+        break;
+    case WDT_STAGE2:
+        hw->config0.wdt_stg2 = behavior;
+        hw->config3.val = timeout_ticks;
+        break;
+    case WDT_STAGE3:
+        hw->config0.wdt_stg3 = behavior;
+        hw->config4.val = timeout_ticks;
+        break;
+    default:
+        abort();
+    }
+}
+
+/**
+ * @brief Disable a particular stage of the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to disable
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
+{
+    switch (stage) {
+    case WDT_STAGE0:
+        hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE1:
+        hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE2:
+        hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE3:
+        hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
+        break;
+    default:
+        abort();
+    }
+}
+
+/**
+ * @brief Set the length of the CPU reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of CPU reset signal
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    hw->config0.wdt_cpu_reset_length = length;
+}
+
+/**
+ * @brief Set the length of the system reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of system reset signal
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    hw->config0.wdt_sys_reset_length = length;
+}
+
+/**
+ * @brief Enable/Disable the RWDT flashboot mode.
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
+ *
+ * @note Flashboot mode is independent and can trigger a WDT timeout event if the
+ *       WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
+ *       on flashboot, and should be disabled by software when flashbooting completes.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
+{
+    hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable CPU0 to be reset, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
+{
+    hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable CPU1 to be reset, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
+{
+    hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable the RWDT pause during sleep functionality
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
+{
+    hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable chip reset on RWDT timeout.
+ *
+ * A chip reset also resets the analog portion of the chip. It will appear as a
+ * POWERON reset rather than an RTC reset.
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
+{
+    hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Set width of chip reset signal
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
+}
+
+/**
+ * @brief Feed the RWDT
+ *
+ * Resets the current timer count and current stage.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
+{
+    hw->feed.rtc_wdt_feed = 1;
+}
+
+/**
+ * @brief Enable write protection of the RWDT registers
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
+{
+    hw->wprotect.val = 0;
+}
+
+/**
+ * @brief Disable write protection of the RWDT registers
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
+{
+    hw->wprotect.val = RTC_CNTL_WDT_WKEY_VALUE;
+}
+
+/**
+ * @brief Enable the RWDT interrupt.
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable RWDT interrupt, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
+{
+    hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Check if the RWDT interrupt has been triggered
+ *
+ * @param hw Start address of the peripheral registers.
+ * @return True if the RWDT interrupt was triggered
+ */
+FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
+{
+    return (hw->int_st.lp_wdt_int_st) ? true : false;
+}
+
+/**
+ * @brief Clear the RWDT interrupt status.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
+{
+    hw->int_clr.lp_wdt_int_clr = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/mmu_ll.h

@@ -0,0 +1,239 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for MMU register operations
+
+#pragma once
+
+#include "soc/spi_mem_reg.h"
+#include "soc/ext_mem_defs.h"
+#include "hal/assert.h"
+#include "hal/mmu_types.h"
+#include "hal/efuse_ll.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief The real MMU page size get from Kconfig.
+ *
+ * @note Only used in this file
+ */
+#define MMU_LL_PAGE_SIZE                   (CONFIG_MMU_PAGE_SIZE)
+
+__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
+{
+    unsigned cnt = efuse_ll_get_flash_crypt_cnt();
+    // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
+    cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
+    return (cnt == 1);
+}
+
+/**
+ * Get MMU page size
+ *
+ * @param mmu_id  MMU ID
+ *
+ * @return MMU page size code
+ */
+__attribute__((always_inline))
+static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
+{
+    (void)mmu_id;
+    uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
+    return  (page_size_code == 0) ? MMU_PAGE_64KB : \
+            (page_size_code == 1) ? MMU_PAGE_32KB : \
+            (page_size_code == 2) ? MMU_PAGE_16KB : \
+            MMU_PAGE_8KB;
+}
+
+/**
+ * Set MMU page size
+ *
+ * @param size  MMU page size
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
+{
+    uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
+                      (size == MMU_PAGE_32KB) ? 1 : \
+                      (size == MMU_PAGE_16KB) ? 2 : \
+                      (size == MMU_PAGE_8KB) ? 3 : 0;
+    REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
+}
+
+/**
+ * Check if the external memory vaddr region is valid
+ *
+ * @param mmu_id      MMU ID
+ * @param vaddr_start start of the virtual address
+ * @param len         length, in bytes
+ *
+ * @return
+ *         True for valid
+ */
+__attribute__((always_inline))
+static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
+{
+    (void)mmu_id;
+    uint32_t vaddr_end = vaddr_start + len;
+    return (ADDRESS_IN_IRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_IRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_DRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE));
+}
+
+/**
+ * To get the MMU table entry id to be mapped
+ *
+ * @param mmu_id  MMU ID
+ * @param vaddr   virtual address to be mapped
+ *
+ * @return
+ *         MMU table entry id
+ */
+__attribute__((always_inline))
+static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
+{
+    (void)mmu_id;
+    mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
+    uint32_t shift_code = 0;
+    switch (page_size) {
+        case MMU_PAGE_64KB:
+            shift_code = 16;
+            break;
+        case MMU_PAGE_32KB:
+            shift_code = 15;
+            break;
+        case MMU_PAGE_16KB:
+            shift_code = 14;
+            break;
+        default:
+            HAL_ASSERT(shift_code);
+    }
+    return ((vaddr & MMU_VADDR_MASK(page_size)) >> shift_code);
+}
+
+/**
+ * Format the paddr to be mappable
+ *
+ * @param mmu_id  MMU ID
+ * @param paddr   physical address to be mapped
+ *
+ * @return
+ *         mmu_val - paddr in MMU table supported format
+ */
+__attribute__((always_inline))
+static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
+{
+    (void)mmu_id;
+    mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
+    uint32_t shift_code = 0;
+    switch (page_size) {
+        case MMU_PAGE_64KB:
+            shift_code = 16;
+            break;
+        case MMU_PAGE_32KB:
+            shift_code = 15;
+            break;
+        case MMU_PAGE_16KB:
+            shift_code = 14;
+            break;
+        default:
+            HAL_ASSERT(shift_code);
+    }
+    return paddr >> shift_code;
+}
+
+/**
+ * Write to the MMU table to map the virtual memory and the physical memory
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ * @param mmu_val  Value to be set into an MMU entry, for physical address
+ * @param target   MMU target physical memory.
+ */
+__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
+{
+    (void)mmu_id;
+    (void)target;
+    uint32_t mmu_raw_value;
+    if (mmu_ll_cache_encryption_enabled()) {
+        mmu_val |= MMU_SENSITIVE;
+    }
+    /* Note: for ESP32-C6, invert invalid bit for compatible with upper-layer software */
+    mmu_raw_value = mmu_val ^ MMU_INVALID_MASK;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
+}
+
+/**
+ * Read the raw value from MMU table
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ * @param mmu_val  Value to be read from MMU table
+ */
+__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    uint32_t mmu_raw_value;
+    uint32_t ret;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
+    if (mmu_ll_cache_encryption_enabled()) {
+        mmu_raw_value &= ~MMU_SENSITIVE;
+    }
+    /* Note: for ESP32-C6, invert invalid bit for compatible with upper-layer software */
+    ret = mmu_raw_value ^ MMU_INVALID_MASK;
+    return ret;
+}
+
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry
+ */
+__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), MMU_INVALID);
+}
+
+/**
+ * Get MMU table entry is invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ * return ture for MMU entry is invalid, false for valid
+ */
+__attribute__((always_inline)) static inline bool mmu_ll_get_entry_is_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    uint32_t mmu_raw_value;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
+    /* Note: for ESP32-C6, the invalid-bit of MMU: 0 for invalid, 1 for valid */
+    return (mmu_raw_value & MMU_INVALID_MASK) ? false : true;
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/mpu_ll.h

@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Copied from C3, and this LL is currently unused for ESP32-C3 */
+
+static inline uint32_t mpu_ll_id_to_addr(unsigned id)
+{
+    abort();
+}
+
+static inline void mpu_ll_set_region_rw(uint32_t addr)
+{
+    abort();
+}
+
+static inline void mpu_ll_set_region_rwx(uint32_t addr)
+{
+    abort();
+}
+
+static inline void mpu_ll_set_region_x(uint32_t addr)
+{
+    abort();
+}
+
+
+static inline void mpu_ll_set_region_illegal(uint32_t addr)
+{
+    abort();
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/mwdt_ll.h

@@ -0,0 +1,253 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for Timer Group register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
+#include "hal/wdt_types.h"
+#include "hal/assert.h"
+#include "esp_attr.h"
+#include "hal/misc.h"
+
+//Type check wdt_stage_action_t
+_Static_assert(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+_Static_assert(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+_Static_assert(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+_Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+//Type check wdt_reset_sig_length_t
+_Static_assert(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+
+/**
+ * @brief Enable the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
+{
+    hw->wdtconfig0.wdt_en = 1;
+}
+
+/**
+ * @brief Disable the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @note This function does not disable the flashboot mode. Therefore, given that
+ *       the MWDT is disabled using this function, a timeout can still occur
+ *       if the flashboot mode is simultaneously enabled.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
+{
+    hw->wdtconfig0.wdt_en = 0;
+}
+
+/**
+ * Check if the MWDT is enabled
+ *
+ * @param hw Start address of the peripheral registers.
+ * @return True if the MWDT is enabled, false otherwise
+ */
+FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
+{
+    return (hw->wdtconfig0.wdt_en) ? true : false;
+}
+
+/**
+ * @brief Configure a particular stage of the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to configure
+ * @param timeout Number of timer ticks for the stage to timeout
+ * @param behavior What action to take when the stage times out
+ */
+FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior)
+{
+    switch (stage) {
+    case WDT_STAGE0:
+        hw->wdtconfig0.wdt_stg0 = behavior;
+        hw->wdtconfig2.wdt_stg0_hold = timeout;
+        break;
+    case WDT_STAGE1:
+        hw->wdtconfig0.wdt_stg1 = behavior;
+        hw->wdtconfig3.wdt_stg1_hold = timeout;
+        break;
+    case WDT_STAGE2:
+        hw->wdtconfig0.wdt_stg2 = behavior;
+        hw->wdtconfig4.wdt_stg2_hold = timeout;
+        break;
+    case WDT_STAGE3:
+        hw->wdtconfig0.wdt_stg3 = behavior;
+        hw->wdtconfig5.wdt_stg3_hold = timeout;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported WDT stage");
+        break;
+    }
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Disable a particular stage of the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to disable
+ */
+FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
+{
+    switch (stage) {
+    case WDT_STAGE0:
+        hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE1:
+        hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE2:
+        hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE3:
+        hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported WDT stage");
+        break;
+    }
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Set the length of the CPU reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of CPU reset signal
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    hw->wdtconfig0.wdt_cpu_reset_length = length;
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Set the length of the system reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of system reset signal
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    hw->wdtconfig0.wdt_sys_reset_length = length;
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Enable/Disable the MWDT flashboot mode.
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode.
+ *
+ * @note Flashboot mode is independent and can trigger a WDT timeout event if the
+ *       WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled
+ *       on flashboot, and should be disabled by software when flashbooting completes.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
+{
+    hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Set the clock prescaler of the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param prescaler Prescaler value between 1 to 65535
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
+{
+    // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
+    // We take care of the "read-modify-write" procedure by ourselves.
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Feed the MWDT
+ *
+ * Resets the current timer count and current stage.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
+{
+    hw->wdtfeed.wdt_feed = 1;
+}
+
+/**
+ * @brief Enable write protection of the MWDT registers
+ *
+ * Locking the MWDT will prevent any of the MWDT's registers from being modified
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
+{
+    hw->wdtwprotect.wdt_wkey = 0;
+}
+
+/**
+ * @brief Disable write protection of the MWDT registers
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
+{
+    hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
+}
+
+/**
+ * @brief Clear the MWDT interrupt status.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
+{
+    hw->int_clr_timers.wdt_int_clr = 1;
+}
+
+/**
+ * @brief Set the interrupt enable bit for the MWDT interrupt.
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param enable Whether to enable the MWDT interrupt
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
+{
+    hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h

@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/regi2c_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Reset (Disable) the I2C internal bus for all regi2c registers
+ */
+static inline void regi2c_ctrl_ll_i2c_reset(void)
+{
+    SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
+}
+
+/**
+ * @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register
+ */
+static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
+{
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M);
+}
+
+/**
+ * @brief Start BBPLL self-calibration
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
+{
+    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+}
+
+/**
+ * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
+ */
+static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
+{
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
+}
+
+/**
+ * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
+ */
+static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
+{
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/rtc_cntl_ll.h

@@ -0,0 +1,70 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/rtc.h"
+#include "soc/lp_aon_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
+{
+    // TODO: IDF-5645
+}
+
+static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void)
+{
+    // TODO: IDF-5645
+}
+
+static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
+{
+    // TODO: IDF-5645
+}
+
+static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr)
+{
+    // TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_enable_cpu_retention_clock(void)
+{
+    // TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_enable_cpu_retention(void)
+{
+    // TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_disable_cpu_retention(void)
+{
+    // TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_reset_system(void)
+{
+    REG_SET_BIT(LP_AON_SYS_CFG_REG, LP_AON_HPSYS_SW_RESET);
+}
+
+static inline void rtc_cntl_ll_reset_cpu(int cpu_no)
+{
+    REG_SET_BIT(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/rwdt_ll.h

@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// The LL layer for RTC(LP) watchdog register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "hal/lpwdt_ll.h"
+
+#define rwdt_ll_enable(hw) \
+        lpwdt_ll_enable(hw)
+
+#define rwdt_ll_disable(hw) \
+        lpwdt_ll_disable(hw)
+
+#define rwdt_ll_check_if_enabled(hw) \
+        lpwdt_ll_check_if_enabled(hw)
+
+#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \
+        lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior)
+
+#define rwdt_ll_disable_stage(hw, stage) \
+        lpwdt_ll_disable_stage(hw, stage)
+
+#define rwdt_ll_set_cpu_reset_length(hw, length) \
+        lpwdt_ll_set_cpu_reset_length(hw, length)
+
+#define rwdt_ll_set_sys_reset_length(hw, length) \
+        lpwdt_ll_set_sys_reset_length(hw, length)
+
+#define rwdt_ll_set_flashboot_en(hw, enable) \
+        lpwdt_ll_set_flashboot_en(hw, enable)
+
+#define rwdt_ll_set_procpu_reset_en(hw, enable) \
+        lpwdt_ll_set_procpu_reset_en(hw, enable)
+
+#define rwdt_ll_set_appcpu_reset_en(hw, enable) \
+        lpwdt_ll_set_appcpu_reset_en(hw, enable)
+
+#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \
+        lpwdt_ll_set_pause_in_sleep_en(hw, enable)
+
+#define rwdt_ll_set_chip_reset_en(hw, enable) \
+        lpwdt_ll_set_chip_reset_en(hw, enable)
+
+#define rwdt_ll_set_chip_reset_width(hw, width) \
+        lpwdt_ll_set_chip_reset_width(hw, width)
+
+#define rwdt_ll_feed(hw) \
+        lpwdt_ll_feed(hw)
+
+#define rwdt_ll_write_protect_enable(hw) \
+        lpwdt_ll_write_protect_enable(hw)
+
+#define rwdt_ll_write_protect_disable(hw) \
+        lpwdt_ll_write_protect_disable(hw)
+
+#define rwdt_ll_set_intr_enable(hw, enable) \
+        lpwdt_ll_set_intr_enable(hw, enable)
+
+#define rwdt_ll_check_intr_status(hw) \
+        lpwdt_ll_check_intr_status(hw)
+
+#define rwdt_ll_clear_intr_status(hw) \
+        lpwdt_ll_clear_intr_status(hw)
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/spi_flash_encrypted_ll.h

@@ -0,0 +1,149 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash Encryption.
+
+#include <stdbool.h>
+#include <string.h>
+#include "soc/hp_system_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// Choose type of chip you want to encrypt manully
+typedef enum
+{
+    FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
+    PSRAM_ENCRYPTION_MANU = 1  ///!< Manually encrypt the psram chip.
+} flash_encrypt_ll_type_t;
+
+/**
+ * Enable the flash encryption function under spi boot mode and download boot mode.
+ */
+static inline void spi_flash_encrypt_ll_enable(void)
+{
+    REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
+                HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
+                HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
+}
+
+/*
+ * Disable the flash encryption mode.
+ */
+static inline void spi_flash_encrypt_ll_disable(void)
+{
+    REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
+                HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
+}
+
+/**
+ * Choose type of chip you want to encrypt manully
+ *
+ * @param type The type of chip to be encrypted
+ *
+ * @note The hardware currently support flash encryption.
+ */
+static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
+{
+    // Our hardware only support flash encryption
+    HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
+    REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type);
+}
+
+/**
+ * Configure the data size of a single encryption.
+ *
+ * @param block_size Size of the desired block.
+ */
+static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
+{
+    // Desired block should not be larger than the block size.
+    REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5);
+}
+
+/**
+ * Save 32-bit piece of plaintext.
+ *
+ * @param address the address of written flash partition.
+ * @param buffer Buffer to store the input data.
+ * @param size Buffer size.
+ *
+ */
+static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
+{
+    uint32_t plaintext_offs = (address % 64);
+    memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
+}
+
+/**
+ * Copy the flash address to XTS_AES physical address
+ *
+ * @param flash_addr flash address to write.
+ */
+static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
+{
+    REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr);
+}
+
+/**
+ * Start flash encryption
+ */
+static inline void spi_flash_encrypt_ll_calculate_start(void)
+{
+    REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1);
+}
+
+/**
+ * Wait for flash encryption termination
+ */
+static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
+{
+    while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) {
+    }
+}
+
+/**
+ * Finish the flash encryption and make encrypted result accessible to SPI.
+ */
+static inline void spi_flash_encrypt_ll_done(void)
+{
+    REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE);
+    while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) {
+    }
+}
+
+/**
+ * Set to destroy encrypted result
+ */
+static inline void spi_flash_encrypt_ll_destroy(void)
+{
+    REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY);
+}
+
+/**
+ * Check if is qualified to encrypt the buffer
+ *
+ * @param address the address of written flash partition.
+ * @param length Buffer size.
+ */
+static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
+{
+    return ((address % length) == 0) ? true : false;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/spi_flash_ll.h

@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash
+
+#pragma once
+
+#include "gpspi_flash_ll.h"
+#include "spimem_flash_ll.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
+                                            : gpspi_flash_ll_calculate_clock_reg(clock_div))
+
+#define spi_flash_ll_get_source_clock_freq_mhz(host_id)  (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
+
+#define spi_flash_ll_get_hw(host_id)  (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
+                                      : gpspi_flash_ll_get_hw(host_id)))
+
+#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \
+                                     if (dev_id < 0) {\
+                                        dev_id = gpspi_flash_ll_hw_get_id(dev);\
+                                     }\
+                                     dev_id; \
+                                    })
+
+
+typedef union  {
+    gpspi_flash_ll_clock_reg_t gpspi;
+    spimem_flash_ll_clock_reg_t spimem;
+} spi_flash_ll_clock_reg_t;
+
+#ifdef GPSPI_BUILD
+#define spi_flash_ll_reset(dev)                              gpspi_flash_ll_reset((spi_dev_t*)dev)
+#define spi_flash_ll_cmd_is_done(dev)                        gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
+#define spi_flash_ll_get_buffer_data(dev, buffer, read_len)  gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len)
+#define spi_flash_ll_set_buffer_data(dev, buffer, len)       gpspi_flash_ll_set_buffer_data((spi_dev_t*)dev, buffer, len)
+#define spi_flash_ll_user_start(dev)                         gpspi_flash_ll_user_start((spi_dev_t*)dev)
+#define spi_flash_ll_host_idle(dev)                          gpspi_flash_ll_host_idle((spi_dev_t*)dev)
+#define spi_flash_ll_read_phase(dev)                         gpspi_flash_ll_read_phase((spi_dev_t*)dev)
+#define spi_flash_ll_set_cs_pin(dev, pin)                    gpspi_flash_ll_set_cs_pin((spi_dev_t*)dev, pin)
+#define spi_flash_ll_set_read_mode(dev, read_mode)           gpspi_flash_ll_set_read_mode((spi_dev_t*)dev, read_mode)
+#define spi_flash_ll_set_clock(dev, clk)                     gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk)
+#define spi_flash_ll_set_miso_bitlen(dev, bitlen)            gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_mosi_bitlen(dev, bitlen)            gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_command(dev, cmd, bitlen)           gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen)
+#define spi_flash_ll_set_addr_bitlen(dev, bitlen)            gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen)
+#define spi_flash_ll_get_addr_bitlen(dev)                    gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev)
+#define spi_flash_ll_set_address(dev, addr)                  gpspi_flash_ll_set_address((spi_dev_t*)dev, addr)
+#define spi_flash_ll_set_usr_address(dev, addr, bitlen)      gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen)
+#define spi_flash_ll_set_dummy(dev, dummy)                   gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy)
+#define spi_flash_ll_set_dummy_out(dev, en, lev)             gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev)
+#define spi_flash_ll_set_hold(dev, hold_n)                   gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
+#define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
+#else
+#define spi_flash_ll_reset(dev)                              spimem_flash_ll_reset((spi_mem_dev_t*)dev)
+#define spi_flash_ll_cmd_is_done(dev)                        spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
+#define spi_flash_ll_erase_chip(dev)                         spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev)
+#define spi_flash_ll_erase_sector(dev)                       spimem_flash_ll_erase_sector((spi_mem_dev_t*)dev)
+#define spi_flash_ll_erase_block(dev)                        spimem_flash_ll_erase_block((spi_mem_dev_t*)dev)
+#define spi_flash_ll_set_write_protect(dev, wp)              spimem_flash_ll_set_write_protect((spi_mem_dev_t*)dev, wp)
+#define spi_flash_ll_get_buffer_data(dev, buffer, read_len)  spimem_flash_ll_get_buffer_data((spi_mem_dev_t*)dev, buffer, read_len)
+#define spi_flash_ll_set_buffer_data(dev, buffer, len)       spimem_flash_ll_set_buffer_data((spi_mem_dev_t*)dev, buffer, len)
+#define spi_flash_ll_program_page(dev, buffer, len)          spimem_flash_ll_program_page((spi_mem_dev_t*)dev, buffer, len)
+#define spi_flash_ll_user_start(dev)                         spimem_flash_ll_user_start((spi_mem_dev_t*)dev)
+#define spi_flash_ll_host_idle(dev)                          spimem_flash_ll_host_idle((spi_mem_dev_t*)dev)
+#define spi_flash_ll_read_phase(dev)                         spimem_flash_ll_read_phase((spi_mem_dev_t*)dev)
+#define spi_flash_ll_set_cs_pin(dev, pin)                    spimem_flash_ll_set_cs_pin((spi_mem_dev_t*)dev, pin)
+#define spi_flash_ll_set_read_mode(dev, read_mode)           spimem_flash_ll_set_read_mode((spi_mem_dev_t*)dev, read_mode)
+#define spi_flash_ll_set_clock(dev, clk)                     spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk)
+#define spi_flash_ll_set_miso_bitlen(dev, bitlen)            spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_mosi_bitlen(dev, bitlen)            spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_command(dev, cmd, bitlen)           spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen)
+#define spi_flash_ll_set_addr_bitlen(dev, bitlen)            spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen)
+#define spi_flash_ll_get_addr_bitlen(dev)                    spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev)
+#define spi_flash_ll_set_address(dev, addr)                  spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr)
+#define spi_flash_ll_set_usr_address(dev, addr, bitlen)      spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen)
+#define spi_flash_ll_set_dummy(dev, dummy)                   spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy)
+#define spi_flash_ll_set_dummy_out(dev, en, lev)             spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
+#define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
+#define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/spimem_flash_ll.h

@@ -0,0 +1,596 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash
+
+#pragma once
+
+#include <stdlib.h>
+#include <sys/param.h> // For MIN/MAX
+#include <stdbool.h>
+#include <string.h>
+
+#include "soc/spi_periph.h"
+#include "soc/spi_mem_struct.h"
+#include "hal/assert.h"
+#include "hal/spi_types.h"
+#include "hal/spi_flash_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define spimem_flash_ll_get_hw(host_id)  (((host_id)==SPI1_HOST ?  &SPIMEM1 : NULL ))
+#define spimem_flash_ll_hw_get_id(dev)   ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1)
+
+typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t;
+
+/*------------------------------------------------------------------------------
+ * Control
+ *----------------------------------------------------------------------------*/
+/**
+ * Reset peripheral registers before configuration and starting control
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
+{
+    dev->user.val = 0;
+    dev->ctrl.val = 0;
+}
+
+/**
+ * Check whether the previous operation is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if last command is done, otherwise false.
+ */
+static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
+{
+    return (dev->cmd.val == 0);
+}
+
+/**
+ * Erase the flash chip.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_erase_chip(spi_mem_dev_t *dev)
+{
+    dev->cmd.flash_ce = 1;
+}
+
+/**
+ * Erase the sector, the address should be set by spimem_flash_ll_set_address.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev)
+{
+    dev->ctrl.val = 0;
+    dev->cmd.flash_se = 1;
+}
+
+/**
+ * Erase the block, the address should be set by spimem_flash_ll_set_address.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev)
+{
+    dev->cmd.flash_be = 1;
+}
+
+/**
+ * Suspend erase/program operation.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev)
+{
+    dev->flash_sus_ctrl.flash_pes = 1;
+}
+
+/**
+ * Resume suspended erase/program operation.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev)
+{
+    dev->flash_sus_ctrl.flash_per = 1;
+}
+
+/**
+ * Initialize auto suspend mode, and esp32c3 doesn't support disable auto-suspend.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param auto_sus Enable/disable Flash Auto-Suspend.
+ */
+static inline void spimem_flash_ll_auto_suspend_init(spi_mem_dev_t *dev, bool auto_sus)
+{
+    dev->flash_sus_ctrl.flash_pes_en = auto_sus;
+}
+
+/**
+ * Initialize auto resume mode
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param auto_res Enable/Disable Flash Auto-Resume.
+ *
+ */
+static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool auto_res)
+{
+    dev->flash_sus_ctrl.pes_per_en = auto_res;
+}
+
+/**
+ * Setup the flash suspend command, may vary from chips to chips.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param sus_cmd Flash suspend command.
+ *
+ */
+static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd);
+}
+
+/**
+ * Setup the flash resume command, may vary from chips to chips.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param res_cmd Flash resume command.
+ *
+ */
+static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sus_status, flash_per_command, res_cmd);
+}
+
+/**
+ * Setup the flash read suspend status command, may vary from chips to chips.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param pesr_cmd Flash read suspend status command.
+ *
+ */
+static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd);
+}
+
+/**
+ * Setup to check SUS/SUS1/SUS2 to ensure the suspend status of flashs.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param sus_check_sus_en 1: enable, 0: disable.
+ *
+ */
+static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en)
+{
+    dev->flash_sus_ctrl.sus_timeout_cnt = 5;
+    dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en;
+}
+
+/**
+ * Setup to check SUS/SUS1/SUS2 to ensure the resume status of flashs.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param sus_check_sus_en 1: enable, 0: disable.
+ *
+ */
+static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en)
+{
+    dev->flash_sus_ctrl.sus_timeout_cnt = 5;
+    dev->flash_sus_ctrl.per_end_en = res_check_sus_en;
+}
+
+/**
+ * Set 8 bit command to read suspend status
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
+{
+    dev->flash_sus_ctrl.frd_sus_2b = 0;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
+}
+
+/**
+ * Initialize auto wait idle mode
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param auto_waiti Enable/disable auto wait-idle function
+ */
+static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05);
+    dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti;
+    dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
+}
+
+/**
+ * Return the suspend status of erase or program operations.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if suspended, otherwise false.
+ */
+static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
+{
+    return dev->sus_status.flash_sus;
+}
+
+/**
+ * Enable/disable write protection for the flash chip.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param wp true to enable the protection, false to disable (write enable).
+ */
+static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp)
+{
+    if (wp) {
+        dev->cmd.flash_wrdi = 1;
+    } else {
+        dev->cmd.flash_wren = 1;
+    }
+}
+
+/**
+ * Get the read data from the buffer after ``spimem_flash_ll_read`` is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer to hold the output data
+ * @param read_len Length to get out of the buffer
+ */
+static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
+{
+    if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
+        // If everything is word-aligned, do a faster memcpy
+        memcpy(buffer, (void *)dev->data_buf, read_len);
+    } else {
+        // Otherwise, slow(er) path copies word by word
+        int copy_len = read_len;
+        for (int i = 0; i < (read_len + 3) / 4; i++) {
+            int word_len = MIN(sizeof(uint32_t), copy_len);
+            uint32_t word = dev->data_buf[i];
+            memcpy(buffer, &word, word_len);
+            buffer = (void *)((intptr_t)buffer + word_len);
+            copy_len -= word_len;
+        }
+    }
+}
+
+/**
+ * Set the data to be written in the data buffer.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer holding the data
+ * @param length Length of data in bytes.
+ */
+static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
+{
+    // Load data registers, word at a time
+    int num_words = (length + 3) / 4;
+    for (int i = 0; i < num_words; i++) {
+        uint32_t word = 0;
+        uint32_t word_len = MIN(length, sizeof(word));
+        memcpy(&word, buffer, word_len);
+        dev->data_buf[i] = word;
+        length -= word_len;
+        buffer = (void *)((intptr_t)buffer + word_len);
+    }
+}
+
+
+/**
+ * Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
+ * this to set the address to program.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer holding the data to program
+ * @param length Length to program.
+ */
+static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
+{
+    dev->user.usr_dummy = 0;
+    spimem_flash_ll_set_buffer_data(dev, buffer, length);
+    dev->cmd.flash_pp = 1;
+}
+
+/**
+ * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
+ * should be configured before this is called.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev)
+{
+    dev->cmd.usr = 1;
+}
+
+/**
+ * Check whether the host is idle to perform new commands.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if the host is idle, otherwise false
+ */
+static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
+{
+    return dev->cmd.mst_st == 0;
+}
+
+/**
+ * Set phases for user-defined transaction to read
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
+{
+    typeof (dev->user) user = {
+        .usr_command = 1,
+        .usr_mosi = 0,
+        .usr_miso = 1,
+        .usr_addr = 1,
+    };
+    dev->user = user;
+}
+/*------------------------------------------------------------------------------
+ * Configs
+ *----------------------------------------------------------------------------*/
+/**
+ * Select which pin to use for the flash
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
+ */
+static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
+{
+    dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
+}
+
+/**
+ * Set the read io mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param read_mode I/O mode to use in the following transactions.
+ */
+static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
+{
+    typeof (dev->ctrl) ctrl = dev->ctrl;
+    ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
+    ctrl.val |= SPI_MEM_FASTRD_MODE_M;
+    switch (read_mode) {
+    case SPI_FLASH_FASTRD:
+        //the default option
+        break;
+    case SPI_FLASH_QIO:
+        ctrl.fread_qio = 1;
+        break;
+    case SPI_FLASH_QOUT:
+        ctrl.fread_quad = 1;
+        break;
+    case SPI_FLASH_DIO:
+        ctrl.fread_dio = 1;
+        break;
+    case SPI_FLASH_DOUT:
+        ctrl.fread_dual = 1;
+        break;
+    case SPI_FLASH_SLOWRD:
+        ctrl.fastrd_mode = 0;
+        break;
+    default:
+        abort();
+    }
+    dev->ctrl = ctrl;
+}
+
+/**
+ * Set clock frequency to work at.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param clock_val pointer to the clock value to set
+ */
+static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll_clock_reg_t *clock_val)
+{
+    dev->clock.val = *clock_val;
+}
+
+/**
+ * Set the input length, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of input, in bits.
+ */
+static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_miso = bitlen > 0;
+    dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0;
+}
+
+/**
+ * Set the output length, in bits (not including command, address and dummy
+ * phases)
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of output, in bits.
+ */
+static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_mosi = bitlen > 0;
+    dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
+}
+
+/**
+ * Set the command.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param command Command to send
+ * @param bitlen Length of the command
+ */
+static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
+{
+    dev->user.usr_command = 1;
+    typeof(dev->user2) user2 = {
+        .usr_command_value = command,
+        .usr_command_bitlen = (bitlen - 1),
+    };
+    dev->user2 = user2;
+}
+
+/**
+ * Get the address length that is set in register, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ */
+static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
+{
+    return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
+}
+
+/**
+ * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of the address, in bits
+ */
+static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
+{
+    dev->user1.usr_addr_bitlen = (bitlen - 1);
+    dev->user.usr_addr = bitlen ? 1 : 0;
+}
+
+/**
+ * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr)
+{
+    dev->addr = addr;
+}
+
+/**
+ * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
+{
+    (void)bitlen;
+    spimem_flash_ll_set_address(dev, addr);
+}
+
+/**
+ * Set the length of dummy cycles.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param dummy_n Cycles of dummy phases
+ */
+static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
+{
+    dev->user.usr_dummy = dummy_n ? 1 : 0;
+    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+}
+
+/**
+ * Set D/Q output level during dummy phase
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param out_en whether to enable IO output for dummy phase
+ * @param out_level dummy output level
+ */
+static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t out_en, uint32_t out_lev)
+{
+    // dev->ctrl.fdummy_out = out_en; // TODO: IDF-5333 removed
+    dev->ctrl.q_pol = out_lev;
+    dev->ctrl.d_pol = out_lev;
+}
+
+/**
+ * Set CS hold time.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param hold_n CS hold time config used by the host.
+ */
+static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
+{
+    dev->ctrl2.cs_hold_time = hold_n - 1;
+    dev->user.cs_hold = (hold_n > 0? 1: 0);
+}
+
+static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
+{
+    dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    dev->ctrl2.cs_setup_time = cs_setup_time - 1;
+}
+
+/**
+ * Get the spi flash source clock frequency. Used for calculating
+ * the divider parameters.
+ *
+ * @param None
+ *
+ * @return the frequency of spi flash clock source.(MHz)
+ */
+static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
+{
+    // TODO: IDF-5333
+    // // TODO: Default is PLL480M, this is hard-coded.
+    // // In the future, we can get the CPU clock source by calling interface.
+    // uint8_t clock_val = 0;
+    // switch (SPIMEM0.core_clk_sel.spi01_clk_sel) {
+    // case 0:
+    //     clock_val = 80;
+    //     break;
+    // case 1:
+    //     clock_val = 120;
+    //     break;
+    // case 2:
+    //     clock_val = 160;
+    //     break;
+    // default:
+    //     abort();
+    // }
+    // return clock_val;
+    return 80;
+}
+
+/**
+ * Calculate spi_flash clock frequency division parameters for register.
+ *
+ * @param clkdiv frequency division factor
+ *
+ * @return Register setting for the given clock division factor.
+ */
+static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
+{
+    uint32_t div_parameter;
+    // See comments of `clock` in `spi_mem_struct.h`
+    if (clkdiv == 1) {
+        div_parameter = (1 << 31);
+    } else {
+        div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
+    }
+    return div_parameter;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/systimer_ll.h

@@ -0,0 +1,159 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/systimer_struct.h"
+#include "hal/assert.h"
+
+#define SYSTIMER_LL_COUNTER_CLOCK       0 // Counter used by esptimer, to generate the system level wall clock
+#define SYSTIMER_LL_COUNTER_OS_TICK     1 // Counter used by RTOS porting layer, to generate the OS tick
+#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 0 // Alarm used by OS tick, dedicated for core 0
+#define SYSTIMER_LL_ALARM_CLOCK         2 // Alarm used by esptimer
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// All these functions get invoked either from ISR or HAL that linked to IRAM.
+// Always inline these functions even no gcc optimization is applied.
+
+/******************* Clock *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
+{
+    dev->conf.clk_en = en;
+}
+
+/******************* Counter *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (30 - counter_id);
+    } else {
+        dev->conf.val &= ~(1 << (30 - counter_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
+{
+    if (can) {
+        dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
+    } else {
+        dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_op[counter_id].timer_unit_update = 1;
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_op[counter_id].timer_unit_value_valid;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
+{
+    dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
+    dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].lo.timer_unit_value_lo;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].hi.timer_unit_value_hi;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_load[counter_id].val = 0x01;
+}
+
+/******************* Alarm *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
+{
+    dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
+    dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
+{
+    dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 0;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 1;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
+{
+    HAL_ASSERT(period < (1 << 26));
+    dev->target_conf[alarm_id].target_period = period;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->target_conf[alarm_id].target_period;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->comp_load[alarm_id].val = 0x01;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (24 - alarm_id);
+    } else {
+        dev->conf.val &= ~(1 << (24 - alarm_id));
+    }
+}
+
+/******************* Interrupt *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->int_ena.val |= 1 << alarm_id;
+    } else {
+        dev->int_ena.val &= ~(1 << alarm_id);
+    }
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->int_st.val & (1 << alarm_id);
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->int_clr.val |= 1 << alarm_id;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/timer_ll.h

@@ -0,0 +1,279 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "hal/timer_types.h"
+#include "soc/timer_group_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get timer group register base address with giving group number
+#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
+
+/**
+ * @brief Set clock source for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param clk_src Clock source
+ */
+static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
+{
+    switch (clk_src) {
+    case GPTIMER_CLK_SRC_APB:
+        hw->hw_timer[timer_num].config.tx_use_xtal = 0;
+        break;
+    case GPTIMER_CLK_SRC_XTAL:
+        hw->hw_timer[timer_num].config.tx_use_xtal = 1;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
+}
+
+/**
+ * @brief Enable alarm event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable alarm
+ *           False: disable alarm
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_alarm_en = en;
+}
+
+/**
+ * @brief Set clock prescale for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param divider Prescale value (0 and 1 are not valid)
+ */
+static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
+{
+    HAL_ASSERT(divider >= 2 && divider <= 65536);
+    if (divider >= 65536) {
+        divider = 0;
+    }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
+    hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
+}
+
+/**
+ * @brief Enable auto-reload mode
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable auto reload mode
+ *           False: disable auto reload mode
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_autoreload = en;
+}
+
+/**
+ * @brief Set count direction
+ *
+ * @param hw Timer peripheral register base address
+ * @param timer_num Timer number in the group
+ * @param direction Count direction
+ */
+static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
+{
+    hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP);
+}
+
+/**
+ * @brief Enable timer, start couting
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable the counter
+ *           False: disable the counter
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_en = en;
+}
+
+/**
+ * @brief Trigger software capture event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ */
+__attribute__((always_inline))
+static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].update.tx_update = 1;
+    // Timer register is in a different clock domain from Timer hardware logic
+    // We need to wait for the update to take effect before fetching the count value
+    while (hw->hw_timer[timer_num].update.tx_update) {
+    }
+}
+
+/**
+ * @brief Get counter value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ *
+ * @return counter value
+ */
+__attribute__((always_inline))
+static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
+}
+
+/**
+ * @brief Set alarm value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param alarm_value When counter reaches alarm value, alarm event will be triggered
+ */
+__attribute__((always_inline))
+static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
+{
+    hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32);
+    hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value;
+}
+
+/**
+ * @brief Set reload value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param reload_val Reload counter value
+ */
+__attribute__((always_inline))
+static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val)
+{
+    hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32);
+    hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val;
+}
+
+/**
+ * @brief Get reload value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @return reload count value
+ */
+static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
+}
+
+/**
+ * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ */
+static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].load.tx_load = 1;
+}
+
+/**
+ * @brief Enable ETM module
+ *
+ * @param hw Timer Group register base address
+ * @param en True: enable ETM module, False: disable ETM module
+ */
+static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en)
+{
+    hw->regclk.etm_en = en;
+}
+
+/**
+ * @brief Enable timer interrupt by mask
+ *
+ * @param hw Timer Group register base address
+ * @param mask Mask of interrupt events
+ * @param en True: enable interrupt
+ *           False: disable interrupt
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
+{
+    if (en) {
+        hw->int_ena_timers.val |= mask;
+    } else {
+        hw->int_ena_timers.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Get interrupt status
+ *
+ * @param hw Timer Group register base address
+ *
+ * @return Interrupt status
+ */
+__attribute__((always_inline))
+static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
+{
+    return hw->int_st_timers.val & 0x01;
+}
+
+/**
+ * @brief Clear interrupt status by mask
+ *
+ * @param hw Timer Group register base address
+ * @param mask Interrupt events mask
+ */
+__attribute__((always_inline))
+static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
+{
+    hw->int_clr_timers.val = mask;
+}
+
+/**
+ * @brief Enable the register clock forever
+ *
+ * @param hw Timer Group register base address
+ * @param en True: Enable the register clock forever
+ *           False: Register clock is enabled only when register operation happens
+ */
+static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
+{
+    hw->regclk.clk_en = en;
+}
+
+/**
+ * @brief Get interrupt status register address
+ *
+ * @param hw Timer Group register base address
+ *
+ * @return Interrupt status register address
+ */
+static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
+{
+    return &hw->int_st_timers;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/usb_phy_ll.h

@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/usb_serial_jtag_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Configures the internal PHY for USB_Serial_JTAG
+ *
+ * @param hw Start address of the USB Serial_JTAG registers
+ */
+static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+{
+    // USB_Serial_JTAG use internal PHY
+    hw->conf0.phy_sel = 0;
+    // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
+    hw->conf0.pad_pull_override = 0;
+    // Enable USB D+ pullup
+    hw->conf0.dp_pullup = 1;
+    // Enable USB pad function
+    hw->conf0.usb_pad_enable = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h

@@ -0,0 +1,164 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer of the USB-serial-jtag controller
+
+#pragma once
+#include "soc/usb_serial_jtag_reg.h"
+#include "soc/usb_serial_jtag_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//The in and out endpoints are this long.
+#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
+
+#define USB_SERIAL_JTAG_LL_INTR_MASK         (0x7ffff) //All interrupt mask
+
+// Define USB_SERIAL_JTAG interrupts
+// Note the hardware has more interrupts, but they're only useful for debugging
+// the hardware.
+typedef enum {
+    USB_SERIAL_JTAG_INTR_SOF                    = (1 << 1),
+    USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT    = (1 << 2),
+    USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY        = (1 << 3),
+    USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1       = (1 << 8),
+    USB_SERIAL_JTAG_INTR_BUS_RESET              = (1 << 9),
+    USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD       = (1 << 10),
+} usb_serial_jtag_ll_intr_t;
+
+/**
+ * @brief  Enable the USB_SERIAL_JTAG interrupt based on the given mask.
+ *
+ * @param  mask The bitmap of the interrupts need to be enabled.
+ *
+ * @return None
+ */
+static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask)
+{
+    USB_SERIAL_JTAG.int_ena.val |= mask;
+}
+
+/**
+ * @brief  Disable the USB_SERIAL_JTAG interrupt based on the given mask.
+ *
+ * @param  mask The bitmap of the interrupts need to be disabled.
+ *
+ * @return None
+ */
+static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
+{
+    USB_SERIAL_JTAG.int_ena.val &= (~mask);
+}
+
+/**
+ * @brief  Get the USB_SERIAL_JTAG interrupt status.
+ *
+ * @return The USB_SERIAL_JTAG interrupt status.
+ */
+static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
+{
+    return USB_SERIAL_JTAG.int_st.val;
+}
+
+/**
+ * @brief  Clear the USB_SERIAL_JTAG interrupt status based on the given mask.
+ *
+ * @param  mask The bitmap of the interrupts need to be cleared.
+ *
+ * @return None
+ */
+static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask)
+{
+    USB_SERIAL_JTAG.int_clr.val = mask;
+}
+
+/**
+ * @brief  Get status of enabled interrupt.
+ *
+ * @return interrupt enable value
+ */
+static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void)
+{
+    return USB_SERIAL_JTAG.int_ena.val;
+}
+
+/**
+ * @brief  Read the bytes from the USB_SERIAL_JTAG rxfifo.
+ *
+ * @param  buf The data buffer.
+ * @param  rd_len The data length needs to be read.
+ *
+ * @return amount of bytes read
+ */
+static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
+{
+    int i;
+    for (i = 0; i < (int)rd_len; i++) {
+        if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
+        buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
+    }
+    return i;
+}
+
+/**
+ * @brief  Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there
+ *         is room in the buffer.
+ *
+ * @param  buf The data buffer.
+ * @param  wr_len The data length needs to be writen.
+ *
+ * @return Amount of bytes actually written. May be less than wr_len.
+ */
+static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len)
+{
+    int i;
+    for (i = 0; i < (int)wr_len; i++) {
+        if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
+        USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
+    }
+    return i;
+}
+
+/**
+ * @brief  Returns 1 if the USB_SERIAL_JTAG rxfifo has data available.
+ *
+ * @return 0 if no data available, 1 if data available
+ */
+static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
+{
+    return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
+}
+
+/**
+ * @brief  Returns 1 if the USB_SERIAL_JTAG txfifo has room.
+ *
+ * @return 0 if no data available, 1 if data available
+ */
+static inline int usb_serial_jtag_ll_txfifo_writable(void)
+{
+    return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free;
+}
+
+/**
+ * @brief  Flushes the TX buffer, that is, make it available for the
+ *         host to pick up.
+ *
+ * @note  When fifo is full (with 64 byte), HW will flush the buffer automatically.
+ *        It won't be executed if there is nothing in the fifo.
+ *
+ * @return na
+ */
+static inline void usb_serial_jtag_ll_txfifo_flush(void)
+{
+    USB_SERIAL_JTAG.ep1_conf.wr_done=1;
+}
+
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/rtc_cntl_hal.c

@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The HAL layer for RTC CNTL (common part)
+
+#include "soc/soc_caps.h"
+#include "soc/lldesc.h"
+#include "hal/dma_types.h"
+#include "hal/rtc_hal.h"
+#include "hal/assert.h"
+#include "esp_attr.h"
+
+#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN  (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
+
+typedef struct rtc_cntl_link_buf_conf {
+    uint32_t cfg[4];    /* 4 word for dma link buffer configuration */
+} rtc_cntl_link_buf_conf_t;
+
+void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
+{
+    HAL_ASSERT(elem != NULL);
+    HAL_ASSERT(buff != NULL);
+    HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
+
+    lldesc_t *plink = (lldesc_t *)elem;
+
+    plink->eof    = next ? 0 : 1;
+    plink->owner  = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
+    plink->size   = size >> 4;  /* in unit of 16 bytes */
+    plink->length = size >> 4;
+    plink->buf    = buff;
+    plink->offset = 0;
+    plink->sosf   = 0;
+    STAILQ_NEXT(plink, qe) = next;
+    return (void *)plink;
+}
+
+#if SOC_PM_SUPPORT_CPU_PD
+
+void rtc_cntl_hal_enable_cpu_retention(void *addr)
+{
+    // TODO: IDF-5718 has removed the retention feature
+}
+
+void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
+{
+    // TODO: IDF-5718 has removed the retention feature
+}
+
+#endif // SOC_PM_SUPPORT_CPU_PD

components/hal/esp32h2/include/hal/aes_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #pragma once
 
@@ -224,7 +216,7 @@ static inline void aes_ll_interrupt_enable(bool enable)
  */
 static inline void aes_ll_interrupt_clear(void)
 {
-    REG_WRITE(AES_INT_CLR_REG, 1);
+    REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
 

components/hal/esp32s2/include/hal/aes_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #pragma once
 
@@ -235,7 +227,7 @@ static inline void aes_ll_interrupt_enable(bool enable)
  */
 static inline void aes_ll_interrupt_clear(void)
 {
-    REG_WRITE(AES_INT_CLR_REG, 1);
+    REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
 /**

components/hal/esp32s2/include/hal/rtc_io_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 /*******************************************************************************
  * NOTICE
@@ -21,10 +13,8 @@
 #pragma once
 
 #include <stdlib.h>
-#include "soc/rtc_io_periph.h"
+#include "soc/rtc_periph.h"
-#include "soc/rtc_io_struct.h"
 #include "soc/sens_struct.h"
-#include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
 #define RTCIO_LL_PIN_FUNC     0

components/hal/esp32s3/include/hal/aes_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #pragma once
 
@@ -224,7 +216,7 @@ static inline void aes_ll_interrupt_enable(bool enable)
  */
 static inline void aes_ll_interrupt_clear(void)
 {
-    REG_WRITE(AES_INT_CLR_REG, 1);
+    REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
 

components/hal/esp32s3/include/hal/rtc_io_ll.h

@@ -13,9 +13,7 @@
 #pragma once
 
 #include <stdlib.h>
-#include "soc/rtc_io_periph.h"
+#include "soc/rtc_periph.h"
-#include "soc/rtc_io_struct.h"
-#include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 #include "soc/io_mux_reg.h"
 #include "soc/usb_serial_jtag_reg.h"

components/hal/include/hal/gpio_types.h

@@ -348,6 +348,43 @@ typedef enum {
     GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
+#elif CONFIG_IDF_TARGET_ESP32C6
+typedef enum {
+    GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
+    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
+    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
+    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output */
+    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
+    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
+    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
+    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
+    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
+    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
+    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
+    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
+    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
+    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
+    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
+    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
+    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
+    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
+    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
+    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
+    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
+    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
+    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+    GPIO_NUM_24 = 24,   /*!< GPIO24, input and output */
+    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
+    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
+    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
+    GPIO_NUM_28 = 28,   /*!< GPIO28, input and output */
+    GPIO_NUM_29 = 29,   /*!< GPIO29, input and output */
+    GPIO_NUM_30 = 30,   /*!< GPIO30, input and output */
+    GPIO_NUM_MAX,
+/** @endcond */
+} gpio_num_t;
 #endif
 
 typedef enum {

components/hal/include/hal/mmu_types.h

@@ -15,6 +15,7 @@ extern "C" {
  * MMU Page size
  */
 typedef enum {
+    MMU_PAGE_8KB = 0x2000,
     MMU_PAGE_16KB = 0x4000,
     MMU_PAGE_32KB = 0x8000,
     MMU_PAGE_64KB = 0x10000,

components/hal/include/hal/rtc_hal.h

@@ -10,7 +10,7 @@
 #include "soc/soc_caps.h"
 #include "hal/gpio_types.h"
 #include "hal/rtc_cntl_ll.h"
-#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 #include "hal/rtc_io_ll.h"
 #endif
 

components/hal/include/hal/rtc_io_hal.h

@@ -17,9 +17,10 @@
 #include <esp_err.h>
 #include "sdkconfig.h"
 
-#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #include "soc/soc_caps.h"
 #include "hal/rtc_io_ll.h"
+#include "hal/rtc_io_types.h"
 #endif
 
 #ifdef __cplusplus

components/hal/include/hal/sha_types.h

@@ -21,6 +21,8 @@
 #include "esp32h2/rom/sha.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/sha.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/sha.h"
 #endif
 
 #ifdef __cplusplus

components/hal/include/hal/wdt_hal.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 /*******************************************************************************
  * NOTICE
@@ -37,7 +29,11 @@ typedef struct {
     wdt_inst_t inst;                /**< Which WDT instance this HAL context is using (i.e. MWDT0, MWDT1, RWDT)*/
     union {
         timg_dev_t *mwdt_dev;       /**< Starting address of the MWDT */
+#if CONFIG_IDF_TARGET_ESP32C6       // TODO: IDF-5653
+        lp_wdt_dev_t *rwdt_dev;     /**< Starting address of the RWDT*/
+#else
         rtc_cntl_dev_t *rwdt_dev;   /**< Starting address of the RWDT*/
+#endif
     };
 } wdt_hal_context_t;
 

components/hal/mmu_hal.c

@@ -26,6 +26,8 @@
 #include "esp32c2/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/cache.h"
 #endif
 
 void mmu_hal_init(void)

components/hal/spi_flash_hal.c

@@ -23,7 +23,7 @@ static const char *TAG = "flash_hal";
 static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg)
 {
     int clk_source = cfg->clock_src_freq;
-    // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz,
+    // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz, // TODO: IDF-5333 (check this)
     // If user passes freq_mhz like 26 or 27, it's allowed to use integer divider 3.
     // However on other chips or on other frequency, we only allow user pass frequency which
     // can be integer divided. If no, the following strategy is round up the division and

components/hal/wdt_hal_iram.c

@@ -24,7 +24,11 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
     }
 #endif
     else {
+#if CONFIG_IDF_TARGET_ESP32C6       // TODO: IDF-5653
+        hal->rwdt_dev = &LP_WDT;
+#else
         hal->rwdt_dev = &RTCCNTL;
+#endif
     }
     hal->inst = wdt_inst;
 
@@ -67,7 +71,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
         mwdt_ll_disable_stage(hal->mwdt_dev, 1);
         mwdt_ll_disable_stage(hal->mwdt_dev, 2);
         mwdt_ll_disable_stage(hal->mwdt_dev, 3);
-#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
         //Enable or disable level interrupt. Edge interrupt is always disabled.
         mwdt_ll_set_edge_intr(hal->mwdt_dev, false);
         mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr);

components/perfmon/CMakeLists.txt

@@ -1,6 +1,7 @@
-idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(arch IDF_TARGET_ARCH)
-if(${target} STREQUAL "esp32c3" OR ${target} STREQUAL "esp32h2" OR ${target} STREQUAL "esp32c2")
+
-        return()
+if(NOT "${arch}" STREQUAL "xtensa")
+    return()
 endif()
 
 set(xtensa_perfmon_srcs "xtensa_perfmon_access.c"

components/riscv/include/riscv/rv_utils.h

@@ -10,7 +10,7 @@
 
 #include "soc/soc_caps.h"
 #include "soc/assist_debug_reg.h"
-#include "soc/interrupt_core0_reg.h"
+#include "soc/interrupt_reg.h"
 #include "esp_attr.h"
 #include "riscv/csr.h"
 #include "riscv/interrupt.h"

components/soc/esp32/rtc_io_periph.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/rtc_io_periph.h"
+#include "soc/rtc_periph.h"
 
 const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     RTCIO_GPIO0_CHANNEL,    //GPIO0

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -183,6 +183,10 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
     bool
     default y
 
+config SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    bool
+    default y
+
 config SOC_GDMA_GROUPS
     int
     default 1
@@ -543,10 +547,6 @@ config SOC_PM_SUPPORT_BT_WAKEUP
     bool
     default y
 
-config SOC_MMU_PAGE_SIZE_CONFIGURABLE
-    bool
-    default y
-
 config SOC_PM_SUPPORT_CPU_PD
     bool
     default n

components/soc/esp32c2/include/soc/io_mux_reg.h

@@ -115,9 +115,6 @@
 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
 #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
 
-#define U0RXD_GPIO_NUM               19
-#define U0TXD_GPIO_NUM               20
-
 #define SPI_HD_GPIO_NUM              12
 #define SPI_WP_GPIO_NUM              13
 #define SPI_CS0_GPIO_NUM             14

components/soc/esp32c2/include/soc/soc_caps.h

@@ -90,6 +90,9 @@
 
 #define SOC_CPU_IDRAM_SPLIT_USING_PMP   1
 
+/*-------------------------- MMU CAPS ----------------------------------------*/
+#define SOC_MMU_PAGE_SIZE_CONFIGURABLE  (1)
+
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_GDMA_GROUPS                 (1U) // Number of GDMA groups
 #define SOC_GDMA_PAIRS_PER_GROUP        (1U) // Number of GDMA pairs in each group
@@ -261,15 +264,9 @@
 
 /*-------------------------- Power Management CAPS ----------------------------*/
 #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
-
 #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
-
-/*-------------------------- MMU CAPS ----------------------------------------*/
-#define SOC_MMU_PAGE_SIZE_CONFIGURABLE  (1)
 #define SOC_PM_SUPPORT_CPU_PD           (0)
-
 #define SOC_PM_SUPPORT_WIFI_PD          (0)
-
 #define SOC_PM_SUPPORT_BT_PD            (0)
 
 /*------------------------------------ WI-FI CAPS ------------------------------------*/

components/soc/esp32c2/include/soc/system_reg.h

@@ -5,7 +5,6 @@
  */
 #pragma once
 
-#include <stdint.h>
 #include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32c3/include/soc/hwcrypto_reg.h

@@ -1,16 +1,9 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
 
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 #ifndef __HWCRYPTO_REG_H__
 #define __HWCRYPTO_REG_H__
 
@@ -113,11 +106,6 @@
 #define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
 #define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
 
-#define AES_INT_CLR_REG         ((DR_REG_AES_BASE) + 0xAC)
-#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
-#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
-#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
-
 /* AES_STATE_REG values */
 #define AES_STATE_IDLE 0
 #define AES_STATE_BUSY 1

components/soc/esp32c6/CMakeLists.txt

@@ -0,0 +1,30 @@
+set(srcs
+    "adc_periph.c"
+    "dedic_gpio_periph.c"
+    "gdma_periph.c"
+    "gpio_periph.c"
+    "sdm_periph.c"
+    "interrupts.c"
+    "spi_periph.c"
+    "ledc_periph.c"
+    "rmt_periph.c"
+    "i2s_periph.c"
+    "i2c_periph.c"
+    "uart_periph.c"
+    "temperature_sensor_periph.c"
+    "timer_periph.c")
+
+# ESP32C6-TODO
+list(REMOVE_ITEM srcs
+        "adc_periph.c"                  # TODO: IDF-5310
+        "dedic_gpio_periph.c"           # TODO: IDF-5331
+        "ledc_periph.c"                 # TODO: IDF-5328
+        "i2s_periph.c"                  # TODO: IDF-5314
+        "i2c_periph.c"                  # TODO: IDF-5326
+        "temperature_sensor_periph.c"   # TODO: IDF-5322
+        )
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+target_include_directories(${COMPONENT_LIB} PUBLIC . include)

components/soc/esp32c6/adc_periph.c

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/adc_periph.h"
+
+/* Store IO number corresponding to the ADC channel number. */
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
+    /* ADC1 */
+    {
+        ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
+    },
+    /* ADC2 */
+    {
+        ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
+    }
+};

components/soc/esp32c6/dedic_gpio_periph.c

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_sig_map.h"
+#include "soc/dedic_gpio_periph.h"
+
+const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
+    .module = -1,
+    .irq = -1,
+    .cores = {
+        [0] = {
+            .in_sig_per_channel = {
+                [0] = CPU_GPIO_IN0_IDX,
+                [1] = CPU_GPIO_IN1_IDX,
+                [2] = CPU_GPIO_IN2_IDX,
+                [3] = CPU_GPIO_IN3_IDX,
+                [4] = CPU_GPIO_IN4_IDX,
+                [5] = CPU_GPIO_IN5_IDX,
+                [6] = CPU_GPIO_IN6_IDX,
+                [7] = CPU_GPIO_IN7_IDX,
+            },
+            .out_sig_per_channel = {
+                [0] = CPU_GPIO_OUT0_IDX,
+                [1] = CPU_GPIO_OUT1_IDX,
+                [2] = CPU_GPIO_OUT2_IDX,
+                [3] = CPU_GPIO_OUT3_IDX,
+                [4] = CPU_GPIO_OUT4_IDX,
+                [5] = CPU_GPIO_OUT5_IDX,
+                [6] = CPU_GPIO_OUT6_IDX,
+                [7] = CPU_GPIO_OUT7_IDX,
+            }
+        },
+    },
+};

components/soc/esp32c6/gdma_periph.c

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gdma_periph.h"
+
+const gdma_signal_conn_t gdma_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_GDMA_MODULE,
+            .pairs = {
+                [0]  = {
+                    .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
+                    .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
+                },
+                [1]  = {
+                    .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
+                    .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
+                },
+                [2]  = {
+                    .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
+                    .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
+                }
+            }
+        }
+    }
+};

components/soc/esp32c6/gpio_periph.c

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_periph.h"
+
+const uint32_t GPIO_PIN_MUX_REG[] = {
+    IO_MUX_GPIO0_REG,
+    IO_MUX_GPIO1_REG,
+    IO_MUX_GPIO2_REG,
+    IO_MUX_GPIO3_REG,
+    IO_MUX_GPIO4_REG,
+    IO_MUX_GPIO5_REG,
+    IO_MUX_GPIO6_REG,
+    IO_MUX_GPIO7_REG,
+    IO_MUX_GPIO8_REG,
+    IO_MUX_GPIO9_REG,
+    IO_MUX_GPIO10_REG,
+    IO_MUX_GPIO11_REG,
+    IO_MUX_GPIO12_REG,
+    IO_MUX_GPIO13_REG,
+    IO_MUX_GPIO14_REG,
+    IO_MUX_GPIO15_REG,
+    IO_MUX_GPIO16_REG,
+    IO_MUX_GPIO17_REG,
+    IO_MUX_GPIO18_REG,
+    IO_MUX_GPIO19_REG,
+    IO_MUX_GPIO20_REG,
+    IO_MUX_GPIO21_REG,
+    IO_MUX_GPIO22_REG,
+    IO_MUX_GPIO23_REG,
+    IO_MUX_GPIO24_REG,
+    IO_MUX_GPIO25_REG,
+    IO_MUX_GPIO26_REG,
+    IO_MUX_GPIO27_REG,
+    IO_MUX_GPIO28_REG,
+    IO_MUX_GPIO29_REG,
+    IO_MUX_GPIO30_REG,
+};
+
+_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
+
+const uint32_t GPIO_HOLD_MASK[] = {
+    BIT(0),          //GPIO0   // LP_AON_GPIO_HOLD0_REG
+    BIT(1),          //GPIO1
+    BIT(2),          //GPIO2
+    BIT(3),          //GPIO3
+    BIT(4),          //GPIO4
+    BIT(5),          //GPIO5
+    BIT(6),          //GPIO6
+    BIT(7),          //GPIO7
+    BIT(8),          //GPIO8
+    BIT(9),          //GPIO9
+    BIT(10),         //GPIO10
+    BIT(11),         //GPIO11
+    BIT(12),         //GPIO12
+    BIT(13),         //GPIO13
+    BIT(14),         //GPIO14
+    BIT(15),         //GPIO15
+    BIT(16),         //GPIO16
+    BIT(17),         //GPIO17
+    BIT(18),         //GPIO18
+    BIT(19),         //GPIO19
+    BIT(20),         //GPIO20
+    BIT(21),         //GPIO21
+    BIT(22),         //GPIO22
+    BIT(23),         //GPIO23
+    BIT(24),         //GPIO24
+    BIT(25),         //GPIO25
+    BIT(26),         //GPIO26
+    BIT(27),         //GPIO27
+    BIT(28),         //GPIO28
+    BIT(29),         //GPIO29
+    BIT(30),         //GPIO30
+};
+
+_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

components/soc/esp32c6/i2c_periph.c

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/i2c_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
+    {
+        .sda_out_sig = I2CEXT0_SDA_OUT_IDX,
+        .sda_in_sig = I2CEXT0_SDA_IN_IDX,
+        .scl_out_sig = I2CEXT0_SCL_OUT_IDX,
+        .scl_in_sig = I2CEXT0_SCL_IN_IDX,
+        .irq = ETS_I2C_EXT0_INTR_SOURCE,
+        .module = PERIPH_I2C0_MODULE,
+    },
+};

components/soc/esp32c6/i2s_periph.c

@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/i2s_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
+    {
+        .mck_out_sig  = I2S_MCLK_OUT_IDX,
+
+        .m_tx_bck_sig = I2SO_BCK_OUT_IDX,
+        .m_rx_bck_sig = I2SI_BCK_OUT_IDX,
+        .m_tx_ws_sig  = I2SO_WS_OUT_IDX,
+        .m_rx_ws_sig  = I2SI_WS_OUT_IDX,
+
+        .s_tx_bck_sig = I2SO_BCK_IN_IDX,
+        .s_rx_bck_sig = I2SI_BCK_IN_IDX,
+        .s_tx_ws_sig  = I2SO_WS_IN_IDX,
+        .s_rx_ws_sig  = I2SI_WS_IN_IDX,
+
+        .data_out_sig = I2SO_SD_OUT_IDX,
+        .data_in_sig  = I2SI_SD_IN_IDX,
+
+        .irq          = -1,
+        .module       = PERIPH_I2S1_MODULE,
+    }
+};

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -0,0 +1,744 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config SOC_GDMA_SUPPORTED
+    bool
+    default y
+
+config SOC_BT_SUPPORTED
+    bool
+    default y
+
+config SOC_ASYNC_MEMCPY_SUPPORTED
+    bool
+    default y
+
+config SOC_USB_SERIAL_JTAG_SUPPORTED
+    bool
+    default y
+
+config SOC_WIFI_SUPPORTED
+    bool
+    default y
+
+config SOC_SUPPORTS_SECURE_DL_MODE
+    bool
+    default y
+
+config SOC_RISCV_COPROC_SUPPORTED
+    bool
+    default y
+
+config SOC_EFUSE_KEY_PURPOSE_FIELD
+    bool
+    default y
+
+config SOC_EFUSE_HAS_EFUSE_RST_BUG
+    bool
+    default y
+
+config SOC_RTC_FAST_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_RTC_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORTED
+    bool
+    default y
+
+config SOC_SUPPORT_COEXISTENCE
+    bool
+    default y
+
+config SOC_FLASH_ENC_SUPPORTED
+    bool
+    default y
+
+config SOC_SECURE_BOOT_SUPPORTED
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
+config SOC_AES_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_AES_GDMA
+    bool
+    default y
+
+config SOC_AES_SUPPORT_AES_128
+    bool
+    default y
+
+config SOC_AES_SUPPORT_AES_256
+    bool
+    default y
+
+config SOC_ADC_DIG_CTRL_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_ARBITER_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_FILTER_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_MONITOR_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_PERIPH_NUM
+    int
+    default 2
+
+config SOC_ADC_MAX_CHANNEL_NUM
+    int
+    default 5
+
+config SOC_ADC_ATTEN_NUM
+    int
+    default 4
+
+config SOC_ADC_DIGI_CONTROLLER_NUM
+    int
+    default 1
+
+config SOC_ADC_PATT_LEN_MAX
+    int
+    default 8
+
+config SOC_ADC_DIGI_MAX_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_FILTER_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_MONITOR_NUM
+    int
+    default 2
+
+config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
+    int
+    default 83333
+
+config SOC_ADC_SAMPLE_FREQ_THRES_LOW
+    int
+    default 611
+
+config SOC_ADC_RTC_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_RTC_MAX_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_CALIBRATION_V1_SUPPORTED
+    bool
+    default n
+
+config SOC_APB_BACKUP_DMA
+    bool
+    default n
+
+config SOC_BROWNOUT_RESET_SUPPORTED
+    bool
+    default y
+
+config SOC_SHARED_IDCACHE_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_CORES_NUM
+    int
+    default 1
+
+config SOC_CPU_INTR_NUM
+    int
+    default 32
+
+config SOC_CPU_HAS_FLEXIBLE_INTC
+    bool
+    default y
+
+config SOC_RV32A_SUPPORTED
+    bool
+    default y
+
+config SOC_INT_PLIC_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_BREAKPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINT_SIZE
+    hex
+    default 0x80000000
+
+config SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    bool
+    default y
+
+config SOC_DS_SIGNATURE_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_DS_KEY_PARAM_MD_IV_LENGTH
+    int
+    default 16
+
+config SOC_DS_KEY_CHECK_MAX_WAIT_US
+    int
+    default 1100
+
+config SOC_GDMA_GROUPS
+    int
+    default 1
+
+config SOC_GDMA_PAIRS_PER_GROUP
+    int
+    default 3
+
+config SOC_GPIO_PORT
+    int
+    default 1
+
+config SOC_GPIO_PIN_COUNT
+    int
+    default 31
+
+config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+    bool
+    default y
+
+config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
+    int
+    default 0
+
+config SOC_GPIO_SUPPORT_SLP_SWITCH
+    bool
+    default y
+
+config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
+    int
+    default 8
+
+config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
+    int
+    default 8
+
+config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+    bool
+    default y
+
+config SOC_I2C_NUM
+    int
+    default 1
+
+config SOC_I2C_FIFO_LEN
+    int
+    default 32
+
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_HW_CLR_BUS
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_RTC
+    bool
+    default y
+
+config SOC_I2S_NUM
+    bool
+    default y
+
+config SOC_I2S_HW_VERSION_2
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PCM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM_TX
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM_CODEC
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_TDM
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_APB_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_XTAL_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_CHANNEL_NUM
+    int
+    default 6
+
+config SOC_LEDC_TIMER_BIT_WIDE_NUM
+    int
+    default 14
+
+config SOC_LEDC_SUPPORT_FADE_STOP
+    bool
+    default y
+
+config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
+    bool
+    default n
+
+config SOC_MPU_MIN_REGION_SIZE
+    hex
+    default 0x20000000
+
+config SOC_MPU_REGIONS_MAX_NUM
+    int
+    default 8
+
+config SOC_MPU_REGION_RO_SUPPORTED
+    bool
+    default n
+
+config SOC_MPU_REGION_WO_SUPPORTED
+    bool
+    default n
+
+config SOC_RMT_GROUPS
+    int
+    default 1
+
+config SOC_RMT_TX_CANDIDATES_PER_GROUP
+    int
+    default 2
+
+config SOC_RMT_RX_CANDIDATES_PER_GROUP
+    int
+    default 2
+
+config SOC_RMT_CHANNELS_PER_GROUP
+    int
+    default 4
+
+config SOC_RMT_MEM_WORDS_PER_CHANNEL
+    int
+    default 48
+
+config SOC_RMT_SUPPORT_RX_PINGPONG
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_RX_DEMODULATION
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_ASYNC_STOP
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_LOOP_COUNT
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_SYNCHRO
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_APB
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_RC_FAST
+    bool
+    default y
+
+config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
+    int
+    default 128
+
+config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
+    int
+    default 108
+
+config SOC_RTCIO_PIN_COUNT
+    int
+    default 0
+
+config SOC_RSA_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_SHA_DMA_MAX_BUFFER_SIZE
+    int
+    default 3968
+
+config SOC_SHA_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_RESUME
+    bool
+    default y
+
+config SOC_SHA_GDMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA1
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA224
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA256
+    bool
+    default y
+
+config SOC_SDM_GROUPS
+    int
+    default 1
+
+config SOC_SDM_CHANNELS_PER_GROUP
+    int
+    default 4
+
+config SOC_SPI_PERIPH_NUM
+    int
+    default 2
+
+config SOC_SPI_MAXIMUM_BUFFER_SIZE
+    int
+    default 64
+
+config SOC_SPI_SUPPORT_DDRCLK
+    bool
+    default y
+
+config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CD_SIG
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_SLAVE_HD_VER2
+    bool
+    default y
+
+config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
+    bool
+    default y
+
+config SOC_MEMSPI_IS_INDEPENDENT
+    bool
+    default y
+
+config SOC_SPI_MAX_PRE_DIVIDER
+    int
+    default 16
+
+config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_IDLE_INTR
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
+    bool
+    default y
+
+config SOC_SPI_MEM_SUPPORT_CHECK_SUS
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_COUNTER_NUM
+    int
+    default 2
+
+config SOC_SYSTIMER_ALARM_NUM
+    int
+    default 3
+
+config SOC_SYSTIMER_BIT_WIDTH_LO
+    int
+    default 32
+
+config SOC_SYSTIMER_BIT_WIDTH_HI
+    int
+    default 20
+
+config SOC_SYSTIMER_FIXED_DIVIDER
+    bool
+    default y
+
+config SOC_SYSTIMER_INT_LEVEL
+    bool
+    default y
+
+config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+    bool
+    default y
+
+config SOC_TIMER_GROUPS
+    int
+    default 2
+
+config SOC_TIMER_GROUP_TIMERS_PER_GROUP
+    int
+    default 1
+
+config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
+    int
+    default 54
+
+config SOC_TIMER_GROUP_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_TIMER_GROUP_SUPPORT_APB
+    bool
+    default y
+
+config SOC_TIMER_GROUP_TOTAL_TIMERS
+    int
+    default 2
+
+config SOC_TWAI_BRP_MIN
+    int
+    default 2
+
+config SOC_TWAI_BRP_MAX
+    int
+    default 16384
+
+config SOC_TWAI_SUPPORTS_RX_STATUS
+    bool
+    default y
+
+config SOC_SECURE_BOOT_V2_RSA
+    bool
+    default y
+
+config SOC_SECURE_BOOT_V2_ECC
+    bool
+    default y
+
+config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
+    int
+    default 3
+
+config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
+    bool
+    default y
+
+config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
+    int
+    default 32
+
+config SOC_FLASH_ENCRYPTION_XTS_AES
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTION_XTS_AES_128
+    bool
+    default y
+
+config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
+    int
+    default 16
+
+config SOC_MEMPROT_MEM_ALIGN_SIZE
+    int
+    default 512
+
+config SOC_UART_NUM
+    int
+    default 2
+
+config SOC_UART_FIFO_LEN
+    int
+    default 128
+
+config SOC_UART_BITRATE_MAX
+    int
+    default 5000000
+
+config SOC_UART_SUPPORT_APB_CLK
+    bool
+    default y
+
+config SOC_UART_SUPPORT_RTC_CLK
+    bool
+    default n
+
+config SOC_UART_SUPPORT_XTAL_CLK
+    bool
+    default y
+
+config SOC_UART_REQUIRE_CORE_RESET
+    bool
+    default y
+
+config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
+    bool
+    default y
+
+config SOC_COEX_HW_PTI
+    bool
+    default y
+
+config SOC_PHY_DIG_REGS_MEM_SIZE
+    int
+    default 21
+
+config SOC_MAC_BB_PD_MEM_SIZE
+    int
+    default 192
+
+config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
+    int
+    default 12
+
+config SOC_PM_SUPPORT_WIFI_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_BT_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_CPU_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_WIFI_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_BT_PD
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_WIFI_HW_TSF
+    bool
+    default y
+
+config SOC_WIFI_FTM_SUPPORT
+    bool
+    default y
+
+config SOC_WIFI_GCMP_SUPPORT
+    bool
+    default y
+
+config SOC_WIFI_WAPI_SUPPORT
+    bool
+    default y
+
+config SOC_WIFI_CSI_SUPPORT
+    bool
+    default y
+
+config SOC_WIFI_MESH_SUPPORT
+    bool
+    default y

components/soc/esp32c6/include/soc/adc_channel.h

@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ADC1_GPIO0_CHANNEL     ADC1_CHANNEL_0
+#define ADC1_CHANNEL_0_GPIO_NUM 0
+
+#define ADC1_GPIO1_CHANNEL     ADC1_CHANNEL_1
+#define ADC1_CHANNEL_1_GPIO_NUM 1
+
+#define ADC1_GPIO2_CHANNEL     ADC1_CHANNEL_2
+#define ADC1_CHANNEL_2_GPIO_NUM 2
+
+#define ADC1_GPIO3_CHANNEL     ADC1_CHANNEL_3
+#define ADC1_CHANNEL_3_GPIO_NUM 3
+
+#define ADC1_GPIO4_CHANNEL     ADC1_CHANNEL_4
+#define ADC1_CHANNEL_4_GPIO_NUM 4
+
+#define ADC2_GPIO5_CHANNEL      ADC2_CHANNEL_0
+#define ADC2_CHANNEL_0_GPIO_NUM 5

components/soc/esp32c6/include/soc/boot_mode.h

@@ -0,0 +1,93 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_BOOT_MODE_H_
+#define _SOC_BOOT_MODE_H_
+
+#include "soc.h"
+
+/*SPI Boot*/
+#define IS_1XXX(v)                              (((v)&0x08)==0x08)
+
+/*Download Boot, SPI(or SDIO_V2)/UART0*/
+#define IS_00XX(v)                              (((v)&0x0c)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
+#define IS_0000(v)                              (((v)&0x0f)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
+#define IS_0001(v)                              (((v)&0x0f)==0x01)
+
+/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
+#define IS_0010(v)                              (((v)&0x0f)==0x02)
+
+/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
+#define IS_0011(v)                              (((v)&0x0f)==0x03)
+
+/*legacy SPI Boot*/
+#define IS_0100(v)                              (((v)&0x0f)==0x04)
+
+/*ATE/ANALOG Mode*/
+#define IS_0101(v)                              (((v)&0x0f)==0x05)
+
+/*SPI(or SDIO_V1) download Mode*/
+#define IS_0110(v)                              (((v)&0x0f)==0x06)
+
+/*Diagnostic Mode+UART0 download Mode*/
+#define IS_0111(v)                              (((v)&0x0f)==0x07)
+
+
+
+#define BOOT_MODE_GET()                         (GPIO_REG_READ(GPIO_STRAP_REG))
+
+/*do not include download mode*/
+#define ETS_IS_UART_BOOT()                      IS_0111(BOOT_MODE_GET())
+
+/*all spi boot including spi/legacy*/
+#define ETS_IS_FLASH_BOOT()                     (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
+
+/*all faster spi boot including spi*/
+#define ETS_IS_FAST_FLASH_BOOT()                IS_1XXX(BOOT_MODE_GET())
+
+#if SUPPORT_SDIO_DOWNLOAD
+
+/*all sdio V2 of failing edge input, failing edge output*/
+#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()           IS_0000(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, raising edge output*/
+#define ETS_IS_SDIO_FEI_REO_V2_BOOT()           IS_0001(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V2_BOOT()           IS_0010(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, raising edge output*/
+#define ETS_IS_SDIO_REI_REO_V2_BOOT()           IS_0011(BOOT_MODE_GET())
+
+/*all sdio V1 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V1_BOOT()           IS_0110(BOOT_MODE_GET())
+
+/*do not include joint download mode*/
+#define ETS_IS_SDIO_BOOT()                      IS_0110(BOOT_MODE_GET())
+#else
+
+/*do not include joint download mode*/
+#define ETS_IS_SPI_DOWNLOAD_BOOT()              IS_0110(BOOT_MODE_GET())
+
+#endif
+
+/*joint download boot*/
+#define ETS_IS_JOINT_DOWNLOAD_BOOT()                  IS_00XX(BOOT_MODE_GET())
+
+/*ATE mode*/
+#define ETS_IS_ATE_BOOT()                       IS_0101(BOOT_MODE_GET())
+
+/*used by  ETS_IS_SDIO_UART_BOOT*/
+#define SEL_NO_BOOT                             0
+#define SEL_SDIO_BOOT                           BIT0
+#define SEL_UART_BOOT                           BIT1
+#define SEL_SPI_SLAVE_BOOT                      BIT2
+
+#endif /* _SOC_BOOT_MODE_H_ */

components/soc/esp32c6/include/soc/clint_reg.h

@@ -5,7 +5,7 @@
  */
 #pragma once
 
-
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -0,0 +1,253 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-5346 Copied from C3, need to update
+/*
+ ************************* ESP32C6 Root Clock Source ****************************
+ * 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
+ *
+ *    This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
+ *    The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock
+ *    frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description).
+ *
+ *    The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
+ *
+ * 2) External 40MHz Crystal Clock: XTAL
+ *
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ *
+ *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
+ *    can be computed in runtime through calibration.
+ *
+ * 4) External 32kHz Crystal Clock (optional): XTAL32K
+ *
+ *    The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
+ *    pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the
+ *    XTAL_32K_P pin.
+ *
+ *    XTAL32K_CLK can also be calibrated to get its exact frequency.
+ */
+
+/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
+#define SOC_CLK_RC_FAST_FREQ_APPROX         17500000                            /*!< Approximate RC_FAST_CLK frequency in Hz */
+#define SOC_CLK_RC_SLOW_FREQ_APPROX         136000                              /*!< Approximate RC_SLOW_CLK frequency in Hz */
+#define SOC_CLK_RC_FAST_D256_FREQ_APPROX    (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */
+#define SOC_CLK_XTAL32K_FREQ_APPROX         32768                               /*!< Approximate XTAL32K_CLK frequency in Hz */
+
+// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
+// {loc}: EXT, INT
+// {type}: XTAL, RC
+// [attr] - optional: [frequency], FAST, SLOW
+/**
+ * @brief Root clock
+ */
+typedef enum {
+    SOC_ROOT_CLK_INT_RC_FAST,          /*!< Internal 17.5MHz RC oscillator */
+    SOC_ROOT_CLK_INT_RC_SLOW,          /*!< Internal 136kHz RC oscillator */
+    SOC_ROOT_CLK_EXT_XTAL,             /*!< External 40MHz crystal */
+    SOC_ROOT_CLK_EXT_XTAL32K,          /*!< External 32kHz crystal/clock signal */
+} soc_root_clk_t;
+
+/**
+ * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_CPU_CLK_SRC_XTAL = 0,              /*!< Select XTAL_CLK as CPU_CLK source */
+    SOC_CPU_CLK_SRC_PLL = 1,               /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */
+    SOC_CPU_CLK_SRC_RC_FAST = 2,           /*!< Select RC_FAST_CLK as CPU_CLK source */
+    SOC_CPU_CLK_SRC_INVALID,               /*!< Invalid CPU_CLK source */
+} soc_cpu_clk_src_t;
+
+/**
+ * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0,      /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1,      /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_INVALID,          /*!< Invalid RTC_SLOW_CLK source */
+} soc_rtc_slow_clk_src_t;
+
+/**
+ * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0,      /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
+    SOC_RTC_FAST_CLK_SRC_RC_FAST = 1,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
+    SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+} soc_rtc_fast_clk_src_t;
+
+// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
+// {[upstream]clock_name}: APB, (BB)PLL, etc.
+// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
+/**
+ * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
+ *
+ * @note enum starts from 1, to save 0 for special purpose
+ */
+typedef enum {
+    // For CPU domain
+    SOC_MOD_CLK_CPU = 1,                       /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
+    // For RTC domain
+    SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
+    SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
+    // For digital domain: peripherals, WIFI, BLE
+    SOC_MOD_CLK_APB,                           /*!< APB_CLK is highly dependent on the CPU_CLK source */
+    SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
+    SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
+    SOC_MOD_CLK_PLL_D2,                        /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */
+    SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
+    SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
+    SOC_MOD_CLK_RC_FAST_D256,                  /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
+    SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
+} soc_module_clk_t;
+
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ *
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
+typedef enum {
+    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,   /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
+} soc_periph_gptimer_clk_src_t;
+
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
+typedef enum {
+    TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB,     /*!< Timer group clock source is APB */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< Timer group clock source is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */
+} soc_periph_tg_clk_src_legacy_t;
+
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of RMT clock source
+ */
+typedef enum {
+    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,         /*!< Select APB as the source clock */
+    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,     /*!< Select APB as the default choice */
+} soc_periph_rmt_clk_src_t;
+
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_APB = SOC_MOD_CLK_APB,     /*!< RMT source clock is APB */
+    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< RMT source clock is XTAL */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
+typedef enum {
+    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
+} soc_periph_temperature_sensor_clk_src_t;
+
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_APB = SOC_MOD_CLK_APB,     /*!< UART source clock is APB CLK */
+    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
+    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< UART source clock is XTAL */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
+} soc_periph_uart_clk_src_legacy_t;
+
+///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of I2S
+ */
+#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
+
+/**
+ * @brief I2S clock source enum
+ */
+typedef enum {
+    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
+    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
+} soc_periph_i2s_clk_src_t;
+
+/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of I2C
+ */
+#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of I2C clock source.
+ */
+typedef enum {
+    I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
+    I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,
+    I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
+} soc_periph_i2c_clk_src_t;
+
+//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of SDM
+ */
+#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
+
+/**
+ * @brief Sigma Delta Modulator clock source
+ */
+typedef enum {
+    SDM_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
+    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
+} soc_periph_sdm_clk_src_t;
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/clkout_channel.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_CLKOUT_CHANNEL_H
+#define _SOC_CLKOUT_CHANNEL_H
+
+// TODO: IDF-5870
+//CLKOUT channels
+#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
+#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
+#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
+#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
+#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
+#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
+
+#endif

components/soc/esp32c6/include/soc/dport_access.h

@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "soc.h"
+#include "uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
+
+#define DPORT_INTERRUPT_DISABLE()
+#define DPORT_INTERRUPT_RESTORE()
+
+/**
+ * @brief Read a sequence of DPORT registers to the buffer.
+ *
+ * @param[out] buff_out  Contains the read data.
+ * @param[in]  address   Initial address for reading registers.
+ * @param[in]  num_words The number of words.
+ */
+void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
+
+// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+// Write value to DPORT register (does not require protecting)
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
+
+#define DPORT_REG_READ(_r)    _DPORT_REG_READ(_r)
+#define DPORT_SEQUENCE_REG_READ(_r)    _DPORT_REG_READ(_r)
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
+#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
+#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
+#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
+#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
+
+#define DPORT_READ_PERI_REG(addr)       _DPORT_READ_PERI_REG(addr)
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DPORT_ACCESS_H_ */

components/soc/esp32c6/include/soc/ext_mem_defs.h

@@ -0,0 +1,115 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _CACHE_MEMORY_H_
+#define _CACHE_MEMORY_H_
+
+#include "esp_bit_defs.h"
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*IRAM0 is connected with Cache IBUS0*/
+#define IRAM0_CACHE_ADDRESS_LOW             0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 128)) // MMU has 256 pages, first 128 for instruction
+#define IRAM0_ADDRESS_LOW                   0x40000000
+#define IRAM0_ADDRESS_HIGH(page_size)       IRAM0_CACHE_ADDRESS_HIGH(page_size)
+
+/*DRAM0 is connected with Cache DBUS0*/
+#define DRAM0_ADDRESS_LOW               0x42000000
+#define DRAM0_ADDRESS_HIGH              0x43000000
+#define DRAM0_CACHE_ADDRESS_LOW         IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE) // ESP32C6-TODO after fixed, also need to remove the sdkconfig.h inclusion
+#define DRAM0_CACHE_ADDRESS_HIGH(page_size)        (IRAM0_CACHE_ADDRESS_HIGH(page_size) + ((page_size) * 128)) // MMU has 256 pages, second 128 for data
+#define DRAM0_CACHE_OPERATION_HIGH(page_size)      DRAM0_CACHE_ADDRESS_HIGH(page_size)
+#define ESP_CACHE_TEMP_ADDR             0x42000000
+
+#define BUS_SIZE(bus_name, page_size)                 (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr, page_size)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size))
+
+#define ADDRESS_IN_IRAM0(vaddr, page_size)            ADDRESS_IN_BUS(IRAM0, vaddr, page_size)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr, page_size)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr, page_size)
+#define ADDRESS_IN_DRAM0(vaddr, page_size)            ADDRESS_IN_BUS(DRAM0, vaddr, page_size)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr, page_size)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr, page_size)
+
+#define BUS_IRAM0_CACHE_SIZE(page_size)              BUS_SIZE(IRAM0_CACHE, page_size)
+#define BUS_DRAM0_CACHE_SIZE(page_size)              BUS_SIZE(DRAM0_CACHE, page_size)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x200
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x200
+
+//TODO, remove these cache function dependencies
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
+#define MMU_MSPI_ACCESS_FLASH           0
+#define MMU_MSPI_VALID                  BIT(9)
+#define MMU_MSPI_INVALID                0
+#define MMU_MSPI_SENSITIVE              BIT(10)
+
+#define MMU_ACCESS_FLASH                MMU_MSPI_ACCESS_FLASH
+#define MMU_ACCESS_SPIRAM               MMU_MSPI_ACCESS_SPIRAM
+#define MMU_VALID                       MMU_MSPI_VALID
+#define MMU_SENSITIVE                   MMU_MSPI_SENSITIVE
+
+// ESP32C6-TODO
+#define MMU_INVALID_MASK                MMU_MSPI_VALID
+#define MMU_INVALID                     MMU_MSPI_INVALID
+
+
+
+#define CACHE_MAX_SYNC_NUM 0x400000
+#define CACHE_MAX_LOCK_NUM 0x8000
+
+#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
+#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
+
+/**
+ * MMU entry valid bit mask for mapping value. For an entry:
+ * valid bit + value bits
+ * valid bit is BIT(9), so value bits are 0x1ff
+ */
+#define MMU_VALID_VAL_MASK 0x1ff
+/**
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 256 * 64KB, means MMU can support 16MB paddr at most
+ */
+#define MMU_MAX_PADDR_PAGE_NUM    256
+//MMU entry num
+#define MMU_ENTRY_NUM   256
+
+/**
+ * This is the mask used for mapping. e.g.:
+ * 0x4200_0000 & MMU_VADDR_MASK
+ */
+#define MMU_VADDR_MASK(page_size)                 ((page_size) * MMU_ENTRY_NUM - 1)
+
+#define CACHE_MEMORY_IBANK0_ADDR        0x40800000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_CACHE_MEMORY_H_ */

components/soc/esp32c6/include/soc/extmem_reg.h

@@ -32,10 +32,10 @@ extern "C" {
 #define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x20)
 /* EXTMEM_DCACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
 /*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
-#define EXTMEM_DCACHE_WRAP    (BIT(4))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND    (BIT(4))
-#define EXTMEM_DCACHE_WRAP_M  (BIT(4))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(4))
-#define EXTMEM_DCACHE_WRAP_V  0x1
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
-#define EXTMEM_DCACHE_WRAP_S  4
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  4
 
 #define EXTMEM_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x24)
 /* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */

components/soc/esp32c6/include/soc/gdma_channel.h

@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
+#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
+#define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
+#define SOC_GDMA_TRIG_PERIPH_UART0   (2)
+#define SOC_GDMA_TRIG_PERIPH_I2S0    (3)
+#define SOC_GDMA_TRIG_PERIPH_AES0    (6)
+#define SOC_GDMA_TRIG_PERIPH_SHA0    (7)
+#define SOC_GDMA_TRIG_PERIPH_ADC0    (8)

components/soc/esp32c6/include/soc/gpio_pins.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x1E)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x1F)
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/hwcrypto_reg.h

@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __HWCRYPTO_REG_H__
+#define __HWCRYPTO_REG_H__
+
+#include "soc/aes_reg.h"
+#include "soc/ds_reg.h"
+#include "soc/hmac_reg.h"
+#include "soc/rsa_reg.h"
+#include "soc/sha_reg.h"
+
+#endif

components/soc/esp32c6/include/soc/interrupt_reg.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/interrupt_matrix_reg.h"
+#include "soc/intpri_reg.h"
+#include "soc/plic_reg.h"
+#include "soc/soc_caps.h"
+
+// ESP32C6 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
+#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG  PLIC_MXINT_CLEAR_REG
+#define INTERRUPT_CORE0_CPU_INT_TYPE_REG   PLIC_MXINT_TYPE_REG
+#define INTC_INT_PRIO_REG(n)               (PLIC_MXINT0_PRI_REG + (n)*4)
+
+#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE

components/soc/esp32c6/include/soc/memprot_defs.h

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "esp32c6/rom/cache.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef union {
+    struct {
+        uint32_t cat0       : 2;
+        uint32_t cat1       : 2;
+        uint32_t cat2       : 2;
+        uint32_t res0       : 8;
+        uint32_t splitaddr  : 8;
+        uint32_t res1       : 10;
+    };
+    uint32_t val;
+} constrain_reg_fields_t;
+
+#ifndef I_D_SRAM_SEGMENT_SIZE
+#define I_D_SRAM_SEGMENT_SIZE       0x20000
+#endif
+
+#define I_D_SPLIT_LINE_SHIFT        0x9
+#define I_D_FAULT_ADDR_SHIFT        0x2
+
+#define DRAM_SRAM_START             0x3FC7C000
+
+//IRAM0
+
+//16kB (ICACHE)
+#define IRAM0_SRAM_LEVEL_0_LOW      SOC_IRAM_LOW //0x40370000
+#define IRAM0_SRAM_LEVEL_0_HIGH     (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
+
+//128kB (LEVEL 1)
+#define IRAM0_SRAM_LEVEL_1_LOW      (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
+#define IRAM0_SRAM_LEVEL_1_HIGH     (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
+
+//128kB (LEVEL 2)
+#define IRAM0_SRAM_LEVEL_2_LOW      (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
+#define IRAM0_SRAM_LEVEL_2_HIGH     (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
+
+//128kB (LEVEL 3)
+#define IRAM0_SRAM_LEVEL_3_LOW      (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
+#define IRAM0_SRAM_LEVEL_3_HIGH     (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
+
+//permission bits
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W  0x2
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F  0x4
+
+//DRAM0
+
+//16kB ICACHE not available from DRAM0
+
+//128kB (LEVEL 1)
+#define DRAM0_SRAM_LEVEL_1_LOW      SOC_DRAM_LOW //0x3FC80000
+#define DRAM0_SRAM_LEVEL_1_HIGH     (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
+
+//128kB (LEVEL 2)
+#define DRAM0_SRAM_LEVEL_2_LOW      (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
+#define DRAM0_SRAM_LEVEL_2_HIGH     (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
+
+//128kB (LEVEL 3)
+#define DRAM0_SRAM_LEVEL_3_LOW      (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
+#define DRAM0_SRAM_LEVEL_3_HIGH     (DRAM0_SRAM_LEVEL_3_LOW  + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W  0x2
+
+//RTC FAST
+
+//permission bits
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R  0x2
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F  0x4
+
+#define AREA_LOW                                                0
+#define AREA_HIGH                                               1
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/mmu.h

@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/ext_mem_defs.h"
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Defined for flash mmap */
+#define SOC_MMU_REGIONS_COUNT                   1
+#define SOC_MMU_PAGES_PER_REGION                256
+#define SOC_MMU_IROM0_PAGES_START               (CACHE_IROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
+#define SOC_MMU_ADDR_MASK                       (MMU_VALID - 1)
+#define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
+#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       FLASH_MMU_TABLE
+#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
+#define SOC_MMU_VADDR0_START_ADDR               (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
+#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/plic_reg.h

@@ -5,12 +5,11 @@
  */
 #pragma once
 
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define DR_REG_PLIC_MX_BASE       ( 0x20001000 )
-#define DR_REG_PLIC_UX_BASE       ( 0x20001400 )
 #define PLIC_MXINT_CONF_REG       ( 0x200013FC )
 #define PLIC_UXINT_CONF_REG       ( 0x200017FC )
 

components/soc/esp32c6/include/soc/reg_base.h

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#define DR_REG_PLIC_MX_BASE                     0x20001000
+#define DR_REG_PLIC_UX_BASE                     0x20001400
 #define DR_REG_CLINT_M_BASE                     0x20001800
 #define DR_REG_CLINT_U_BASE                     0x20001C00
 

components/soc/esp32c6/include/soc/reset_reasons.h

@@ -0,0 +1,56 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+//+-----------------------------------------------Terminology---------------------------------------------+
+//|                                                                                                       |
+//| CPU Reset:    Reset CPU core only, once reset done, CPU will execute from reset vector                |
+//|                                                                                                       |
+//| Core Reset:   Reset the whole digital system except RTC sub-system                                    |
+//|                                                                                                       |
+//| System Reset: Reset the whole digital system, including RTC sub-system                                |
+//|                                                                                                       |
+//| Chip Reset:   Reset the whole chip, including the analog part                                         |
+//|                                                                                                       |
+//+-------------------------------------------------------------------------------------------------------+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// TODO: IDF-5719
+/**
+ * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
+ * @note refer to TRM: <Reset and Clock> chapter
+ */
+typedef enum {
+    RESET_REASON_CHIP_POWER_ON   = 0x01, // Power on reset
+    RESET_REASON_CHIP_BROWN_OUT  = 0x01, // VDD voltage is not stable and resets the chip
+    RESET_REASON_CORE_SW         = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
+    RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
+    RESET_REASON_CORE_SDIO       = 0x06, // SDIO module resets the digital core (hp system)
+    RESET_REASON_CORE_MWDT0      = 0x07, // Main watch dog 0 resets digital core (hp system)
+    RESET_REASON_CORE_MWDT1      = 0x08, // Main watch dog 1 resets digital core (hp system)
+    RESET_REASON_CORE_RTC_WDT    = 0x09, // RTC watch dog resets digital core (hp system)
+    RESET_REASON_CPU0_MWDT0      = 0x0B, // Main watch dog 0 resets CPU 0
+    RESET_REASON_CPU0_SW         = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET
+    RESET_REASON_CPU0_RTC_WDT    = 0x0D, // RTC watch dog resets CPU 0
+    RESET_REASON_SYS_BROWN_OUT   = 0x0F, // VDD voltage is not stable and resets the digital core
+    RESET_REASON_SYS_RTC_WDT     = 0x10, // RTC watch dog resets digital core and rtc module
+    RESET_REASON_CPU0_MWDT1      = 0x11, // Main watch dog 1 resets CPU 0
+    RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
+    RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core (hp system)
+    RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core (hp system)
+    RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core (hp system)
+    RESET_REASON_CPU0_JTAG       = 0x18, // JTAG resets the CPU 0
+} soc_reset_reason_t;
+
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/rtc.h

@@ -0,0 +1,832 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/clk_tree_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock, and sleep functions.
+ *
+ * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ * - rtc_sleep: entry into sleep modes
+ * - rtc_init: initialization
+ */
+
+#define MHZ (1000000)
+
+#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles)  (cycles << 12)
+#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles)  (cycles << 12)
+#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
+
+#define OTHER_BLOCKS_POWERUP        1
+#define OTHER_BLOCKS_WAIT           1
+
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ */
+#define RTC_CNTL_DBIAS_SLP  5 //sleep dig_dbias & rtc_dbias
+#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
+#define RTC_CNTL_DBIAS_0V95 16
+#define RTC_CNTL_DBIAS_1V00 18
+#define RTC_CNTL_DBIAS_1V05 20
+#define RTC_CNTL_DBIAS_1V10 23
+#define RTC_CNTL_DBIAS_1V15 25
+#define RTC_CNTL_DBIAS_1V20 28
+#define RTC_CNTL_DBIAS_1V25 30
+#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
+
+/* Delays for various clock sources to be enabled/switched.
+ * All values are in microseconds.
+ */
+#define SOC_DELAY_RTC_FAST_CLK_SWITCH       3
+#define SOC_DELAY_RTC_SLOW_CLK_SWITCH       300
+#define SOC_DELAY_RC_FAST_ENABLE            50
+#define SOC_DELAY_RC_FAST_DIGI_SWITCH       5
+
+/* Core voltage:
+ * Currently, ESP32C3 never adjust its wake voltage in runtime
+ * Only sets dig/rtc voltage dbias at startup time
+ */
+#define DIG_DBIAS_80M       RTC_CNTL_DBIAS_1V20
+#define DIG_DBIAS_160M      RTC_CNTL_DBIAS_1V20
+#define DIG_DBIAS_XTAL      RTC_CNTL_DBIAS_1V10
+#define DIG_DBIAS_2M        RTC_CNTL_DBIAS_1V00
+
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
+#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
+
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
+
+/* Various delays to be programmed into power control state machines */
+#define RTC_CNTL_XTL_BUF_WAIT_SLP_US            (250)
+#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES        (1)
+#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES           (4)
+#define RTC_CNTL_WAKEUP_DELAY_CYCLES            (5)
+#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES    (1)
+#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES       (1)
+
+/*
+set sleep_init default param
+*/
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT  5
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP  0
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  15
+#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_SLEEP_ON  0
+#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT  1
+#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT  0
+#define RTC_CNTL_PD_CUR_SLEEP_ON  0
+#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
+
+/*
+The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
+storing in efuse (based on ATE 5k ECO3 chips)
+*/
+#define K_RTC_MID_MUL10000 215
+#define K_DIG_MID_MUL10000 213
+#define V_RTC_MID_MUL10000  10800
+#define V_DIG_MID_MUL10000  10860
+
+/**
+ * @brief Possible main XTAL frequency values.
+ *
+ * Enum values should be equal to frequency in MHz.
+ */
+typedef enum {
+    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
+} rtc_xtal_freq_t;
+
+/**
+ * @brief CPU clock configuration structure
+ */
+typedef struct rtc_cpu_freq_config_s {
+    soc_cpu_clk_src_t source;       //!< The clock from which CPU clock is derived
+    uint32_t source_freq_mhz;       //!< Source clock frequency
+    uint32_t div;                   //!< Divider, freq_mhz = source_freq_mhz / div
+    uint32_t freq_mhz;              //!< CPU clock frequency
+} rtc_cpu_freq_config_t;
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
+#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = 0,       //!< Currently selected RTC SLOW_CLK
+    RTC_CAL_8MD256 = 1,        //!< Internal 8 MHz RC oscillator, divided by 256
+    RTC_CAL_32K_XTAL = 2,      //!< External 32 kHz XTAL
+    RTC_CAL_INTERNAL_OSC = 3   //!< Internal 150 kHz oscillator
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    rtc_xtal_freq_t xtal_freq : 8;             //!< Main XTAL frequency
+    uint32_t cpu_freq_mhz : 10;                //!< CPU frequency to set, in MHz
+    soc_rtc_fast_clk_src_t fast_clk_src : 2;   //!< RTC_FAST_CLK clock source to choose
+    soc_rtc_slow_clk_src_t slow_clk_src : 2;   //!< RTC_SLOW_CLK clock source to choose
+    uint32_t clk_rtc_clk_div : 8;
+    uint32_t clk_8m_clk_div : 3;               //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
+    uint32_t slow_clk_dcap : 8;                //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 8;                 //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
+    .cpu_freq_mhz = 80, \
+    .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
+    .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+}
+
+typedef struct {
+    uint16_t wifi_powerup_cycles : 7;
+    uint16_t wifi_wait_cycles : 9;
+    uint16_t bt_powerup_cycles : 7;
+    uint16_t bt_wait_cycles : 9;
+    uint16_t cpu_top_powerup_cycles : 7;
+    uint16_t cpu_top_wait_cycles : 9;
+    uint16_t dg_wrap_powerup_cycles : 7;
+    uint16_t dg_wrap_wait_cycles : 9;
+    uint16_t dg_peri_powerup_cycles : 7;
+    uint16_t dg_peri_wait_cycles : 9;
+} rtc_init_config_t;
+
+#define RTC_INIT_CONFIG_DEFAULT() { \
+    .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .bt_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
+}
+
+void rtc_clk_divider_set(uint32_t div);
+
+void rtc_clk_8m_divider_set(uint32_t div);
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * rtc_clk_init function
+ *
+ * @return XTAL frequency, one of rtc_xtal_freq_t
+ */
+rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
+
+/**
+ * @brief Update XTAL frequency
+ *
+ * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
+ * after startup.
+ *
+ * @param xtal_freq New frequency value
+ */
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
+
+/**
+ * @brief Enable or disable 32 kHz XTAL oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_32k_enable(bool en);
+
+/**
+ * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
+ */
+void rtc_clk_32k_enable_external(void);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled(void);
+
+/**
+ * @brief Enable 32k oscillator, configuring it for fast startup time.
+ * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
+ * must be called one the 32k XTAL oscillator has started up. This function
+ * will initially disable the 32k XTAL oscillator, so it should not be called
+ * when the system is using 32k XTAL as RTC_SLOW_CLK.
+ *
+ * @param cycle Number of 32kHz cycles to bootstrap external crystal.
+ *              If 0, no square wave will be used to bootstrap crystal oscillation.
+ */
+void rtc_clk_32k_bootstrap(uint32_t cycle);
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * Output from 8 MHz internal oscillator is passed into a configurable
+ * divider, which by default divides the input clock frequency by 256.
+ * Output of the divider may be used as RTC_SLOW_CLK source.
+ * Output of the divider is referred to in register descriptions and code as
+ * 8md256 or simply d256. Divider values other than 256 may be configured, but
+ * this facility is not currently needed, so is not exposed in the code.
+ *
+ * When 8MHz/256 divided output is not needed, the divider should be disabled
+ * to reduce power consumption.
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ * @param d256_en true to enable /256 divider
+ */
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled(void);
+
+/**
+ * @brief Get the state of /256 divider which is applied to 8MHz clock
+ * @return true if the divided output is enabled
+ */
+bool rtc_clk_8md256_enabled(void);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
+
+/**
+ * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
+ *
+ * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000
+ * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000
+ *
+ * rtc_clk_cal function can be used to get more precise value by comparing
+ * RTC_SLOW_CLK frequency to the frequency of main XTAL.
+ *
+ * @return RTC_SLOW_CLK frequency, in Hz
+ */
+uint32_t rtc_clk_slow_freq_get_hz(void);
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void);
+
+/**
+ * @brief Get CPU frequency config for a given frequency
+ * @param freq_mhz  Frequency in MHz
+ * @param[out] out_config Output, CPU frequency configuration structure
+ * @return true if frequency can be obtained, false otherwise
+ */
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * This function sets CPU frequency according to the given configuration
+ * structure. It enables PLLs, if necessary.
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Switch CPU frequency (optimized for speed)
+ *
+ * This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
+ * It works faster because it does not disable PLLs when switching from PLL to
+ * XTAL and does not enabled them when switching back. If PLL is not already
+ * enabled when this function is called to switch from XTAL to PLL frequency,
+ * or the PLL which is enabled is the wrong one, this function will fall back
+ * to calling rtc_clk_cpu_freq_set_config.
+ *
+ * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
+ * so it is less safe to use it e.g. from a panic handler (when memory might
+ * be corrupted).
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Get the currently used CPU frequency configuration
+ * @param[out] out_config  Output, CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU clock source to XTAL
+ *
+ * Short form for filling in rtc_cpu_freq_config_t structure and calling
+ * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
+ * Assumes that XTAL frequency has been determined — don't call in startup code.
+ */
+void rtc_clk_cpu_freq_set_xtal(void);
+
+/**
+ * @brief Store new APB frequency value into RTC_APB_FREQ_REG
+ *
+ * This function doesn't change any hardware clocks.
+ *
+ * Functions which perform frequency switching and change APB frequency call
+ * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
+ * (one of RTC general purpose retention registers). This should not normally
+ * be called from application code.
+ *
+ * @param apb_freq  new APB frequency, in Hz
+ */
+void rtc_clk_apb_freq_update(uint32_t apb_freq);
+
+/**
+ * @brief Get the current stored APB frequency.
+ * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get(void);
+
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
+ * @param cal_clk slow clock to be measured
+ * @param slow_clk_cycles number of slow clock cycles to average
+ * @return average ratio between XTAL frequency and slow clock frequency,
+ *         Q13.19 fixed point format, or 0 if calibration has timed out.
+ */
+uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get(void);
+
+uint64_t rtc_light_slp_time_get(void);
+
+uint64_t rtc_deep_slp_time_get(void);
+
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle(void);
+
+/**
+ * @brief Enable the rtc digital 8M clock
+ *
+ * This function is used to enable the digital rtc 8M clock to support peripherals.
+ * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
+ */
+void rtc_dig_clk8m_enable(void);
+
+/**
+ * @brief Disable the rtc digital 8M clock
+ *
+ * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
+ */
+void rtc_dig_clk8m_disable(void);
+
+/**
+ * @brief Get whether the rtc digital 8M clock is enabled
+ */
+bool rtc_dig_8m_enabled(void);
+
+/**
+ * @brief Calculate the real clock value after the clock calibration
+ *
+ * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
+ * @return Frequency of the clock in Hz
+ */
+uint32_t rtc_clk_freq_cal(uint32_t cal_val);
+
+/**
+ * @brief Power down flags for rtc_sleep_pd function
+ */
+typedef struct {
+    uint32_t dig_fpu : 1;    //!< Set to 1 to power UP digital part in sleep
+    uint32_t rtc_fpu : 1;    //!< Set to 1 to power UP RTC memories in sleep
+    uint32_t cpu_fpu : 1;    //!< Set to 1 to power UP digital memories and CPU in sleep
+    uint32_t i2s_fpu : 1;    //!< Set to 1 to power UP I2S in sleep
+    uint32_t bb_fpu : 1;     //!< Set to 1 to power UP WiFi in sleep
+    uint32_t nrx_fpu : 1;    //!< Set to 1 to power UP WiFi in sleep
+    uint32_t fe_fpu : 1;     //!< Set to 1 to power UP WiFi in sleep
+    uint32_t sram_fpu : 1;    //!< Set to 1 to power UP SRAM in sleep
+    uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
+} rtc_sleep_pu_config_t;
+
+/**
+ * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
+ */
+#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
+    .dig_fpu = (val), \
+    .rtc_fpu = (val), \
+    .cpu_fpu = (val), \
+    .i2s_fpu = (val), \
+    .bb_fpu = (val), \
+    .nrx_fpu = (val), \
+    .fe_fpu = (val), \
+    .sram_fpu = (val), \
+    .rom_ram_fpu = (val), \
+}
+
+void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
+
+/**
+ * @brief sleep configuration for rtc_sleep_init function
+ */
+typedef struct {
+    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
+    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
+    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
+    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
+    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
+    uint32_t wifi_pd_en : 1;            //!< power down WiFi
+    uint32_t bt_pd_en : 1;              //!< power down BT
+    uint32_t cpu_pd_en : 1;             //!< power down CPU, but not restart when lightsleep.
+    uint32_t int_8m_pd_en : 1;          //!< Power down Internal 8M oscillator
+    uint32_t dig_peri_pd_en : 1;        //!< power down digital peripherals
+    uint32_t deep_slp : 1;              //!< power down digital domain
+    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
+    uint32_t dig_dbias_wak : 5;         //!< set bias for digital domain, in active mode
+    uint32_t dig_dbias_slp : 5;         //!< set bias for digital domain, in sleep mode
+    uint32_t rtc_dbias_wak : 5;         //!< set bias for RTC domain, in active mode
+    uint32_t rtc_dbias_slp : 5;         //!< set bias for RTC domain, in sleep mode
+    uint32_t dbg_atten_monitor : 4;     //!< voltage parameter, in monitor mode
+    uint32_t bias_sleep_monitor : 1;    //!< circuit control parameter, in monitor mode
+    uint32_t dbg_atten_slp : 4;         //!< voltage parameter, in sleep mode
+    uint32_t bias_sleep_slp : 1;        //!< circuit control parameter, in sleep mode
+    uint32_t pd_cur_monitor : 1;        //!< circuit control parameter, in monitor mode
+    uint32_t pd_cur_slp : 1;            //!< circuit control parameter, in sleep mode
+    uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
+    uint32_t xtal_fpu : 1;              //!< keep main XTAL powered up in sleep
+    uint32_t deep_slp_reject : 1;       //!< enable deep sleep reject
+    uint32_t light_slp_reject : 1;      //!< enable light sleep reject
+} rtc_sleep_config_t;
+
+#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
+#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
+#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
+#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
+#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
+#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
+#define RTC_SLEEP_PD_WIFI               BIT(6)  //!< Power down WIFI
+#define RTC_SLEEP_PD_BT                 BIT(7)  //!< Power down BT
+#define RTC_SLEEP_PD_CPU                BIT(8)  //!< Power down CPU when in lightsleep, but not restart
+#define RTC_SLEEP_PD_DIG_PERIPH         BIT(9)  //!< Power down DIG peripherals
+#define RTC_SLEEP_PD_INT_8M             BIT(10) //!< Power down Internal 8M oscillator
+#define RTC_SLEEP_PD_XTAL               BIT(11) //!< Power down main XTAL
+
+//These flags are not power domains, but will affect some sleep parameters
+#define RTC_SLEEP_DIG_USE_8M            BIT(16)
+#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
+#define RTC_SLEEP_NO_ULTRA_LOW          BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
+
+/**
+ * Default initializer for rtc_sleep_config_t
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use) based on a combination of RTC_SLEEP_PD_x flags.
+ *
+ * @param RTC_SLEEP_PD_x flags combined using bitwise OR
+ */
+void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config);
+
+/**
+ * @brief Prepare the chip to enter sleep mode
+ *
+ * This function configures various power control state machines to handle
+ * entry into light sleep or deep sleep mode, switches APB and CPU clock source
+ * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
+ *
+ * This function does not actually enter sleep mode; this is done using
+ * rtc_sleep_start function. Software may do some other actions between
+ * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
+ * wakeup sources.
+ * @param cfg sleep mode configuration
+ */
+void rtc_sleep_init(rtc_sleep_config_t cfg);
+
+/**
+ * @brief Low level initialize for rtc state machine waiting cycles after waking up
+ *
+ * This function configures the cycles chip need to wait for internal 8MHz
+ * oscillator and external 40MHz crystal. As we configure fixed time for waiting
+ * crystal, we need to pass period to calculate cycles. Now this function only
+ * used in lightsleep mode.
+ *
+ * @param slowclk_period re-calibrated slow clock period
+ */
+void rtc_sleep_low_init(uint32_t slowclk_period);
+
+/**
+ * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
+ * @param t value of RTC counter at which wakeup from sleep will happen;
+ *          only the lower 48 bits are used
+ */
+void rtc_sleep_set_wakeup_time(uint64_t t);
+
+#define RTC_GPIO_TRIG_EN            BIT(2)  //!< GPIO wakeup
+#define RTC_TIMER_TRIG_EN           BIT(3)  //!< Timer wakeup
+#define RTC_WIFI_TRIG_EN            BIT(5)  //!< WIFI wakeup (light sleep only)
+#define RTC_UART0_TRIG_EN           BIT(6)  //!< UART0 wakeup (light sleep only)
+#define RTC_UART1_TRIG_EN           BIT(7)  //!< UART1 wakeup (light sleep only)
+#define RTC_BT_TRIG_EN              BIT(10) //!< BT wakeup (light sleep only)
+#define RTC_XTAL32K_DEAD_TRIG_EN    BIT(12)
+#define RTC_USB_TRIG_EN             BIT(14)
+#define RTC_BROWNOUT_DET_TRIG_EN    BIT(16)
+
+/**
+ * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip
+ */
+#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN         | \
+                               RTC_TIMER_TRIG_EN        | \
+                               RTC_WIFI_TRIG_EN         | \
+                               RTC_UART0_TRIG_EN        | \
+                               RTC_UART1_TRIG_EN        | \
+                               RTC_BT_TRIG_EN           | \
+                               RTC_XTAL32K_DEAD_TRIG_EN | \
+                               RTC_USB_TRIG_EN          | \
+                               RTC_BROWNOUT_DET_TRIG_EN)
+
+/**
+ * @brief Enter deep or light sleep mode
+ *
+ * This function enters the sleep mode previously configured using rtc_sleep_init
+ * function. Before entering sleep, software should configure wake up sources
+ * appropriately (set up GPIO wakeup registers, timer wakeup registers,
+ * and so on).
+ *
+ * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
+ * rejected by hardware (based on reject_opt flags), this function never returns.
+ * When the chip wakes up from deep sleep, CPU is reset and execution starts
+ * from ROM bootloader.
+ *
+ * If light sleep mode was configured using rtc_sleep_init, this function
+ * returns on wakeup, or if sleep is rejected by hardware.
+ *
+ * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
+ *                    combined with OR)
+ * @param reject_opt  bit mask of sleep reject reasons:
+ *                      - RTC_CNTL_GPIO_REJECT_EN
+ *                      - RTC_CNTL_SDIO_REJECT_EN
+ *                    These flags are used to prevent entering sleep when e.g.
+ *                    an external host is communicating via SDIO slave
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
+
+/**
+ * @brief Enter deep sleep mode
+ *
+ * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value
+ * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake
+ * stub is valid to execute (if a wake address is set).
+ *
+ * No RAM is accessed while calculating the CRC and going into deep sleep, which makes
+ * this function safe to use even if the caller's stack is in RTC FAST memory.
+ *
+ * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will
+ * have the same effect and takes less time as CRC calculation is skipped.
+ *
+ * @note This function should only be called after rtc_sleep_init() has been called to
+ * configure the system for deep sleep.
+ *
+ * @param wakeup_opt - same as for rtc_sleep_start
+ * @param reject_opt - same as for rtc_sleep_start
+ *
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
+
+/**
+ * RTC power and clock control initialization settings
+ */
+typedef struct {
+    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
+    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
+    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
+    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
+    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
+    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
+    uint32_t xtal_fpu : 1;
+    uint32_t bbpll_fpu : 1;
+    uint32_t cpu_waiti_clk_gate : 1;
+    uint32_t cali_ocode : 1;        //!< Calibrate Ocode to make bangap voltage more precise.
+} rtc_config_t;
+
+/**
+ * Default initializer of rtc_config_t.
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use).
+ */
+#define RTC_CONFIG_DEFAULT() {\
+    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
+    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
+    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
+    .clkctl_init = 1, \
+    .pwrctl_init = 1, \
+    .rtc_dboost_fpd = 1, \
+    .xtal_fpu = 0, \
+    .bbpll_fpu = 0, \
+    .cpu_waiti_clk_gate = 1, \
+    .cali_ocode = 0\
+}
+
+/**
+ * Initialize RTC clock and power control related functions
+ * @param cfg configuration options as rtc_config_t
+ */
+void rtc_init(rtc_config_t cfg);
+
+/**
+ * Structure describing vddsdio configuration
+ */
+typedef struct {
+    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
+    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
+    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
+    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
+} rtc_vddsdio_config_t;
+
+/**
+ * Get current VDDSDIO configuration
+ * If VDDSDIO configuration is overridden by RTC, get values from RTC
+ * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
+ * Otherwise, use default values and the level of MTDI bootstrapping pin.
+ * @return currently used VDDSDIO configuration
+ */
+rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
+
+/**
+ * Set new VDDSDIO configuration using RTC registers.
+ * If config.force == 1, this overrides configuration done using bootstrapping
+ * pins and EFUSE.
+ *
+ * @param config new VDDSDIO configuration
+ */
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
+
+
+// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
+// **WARNING**: The following are only for backwards compatibility.
+// Please use the declarations in soc/clk_tree_defs.h instead.
+/**
+ * @brief CPU clock source
+ */
+typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
+#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL  //!< XTAL
+#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL    //!< PLL (480M or 320M)
+#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
+#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW         //!< Internal 150 kHz RC oscillator
+#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K    //!< External 32 kHz XTAL
+#define RTC_SLOW_FREQ_8MD256 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 //!< Internal 17.5 MHz RC oscillator, divided by 256
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
+
+/* Alias of frequency related macros */
+#define RTC_FAST_CLK_FREQ_APPROX    SOC_CLK_RC_FAST_FREQ_APPROX
+#define RTC_FAST_CLK_FREQ_8M        SOC_CLK_RC_FAST_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_150K      SOC_CLK_RC_SLOW_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_8MD256    SOC_CLK_RC_FAST_D256_FREQ_APPROX
+#define RTC_SLOW_CLK_FREQ_32K       SOC_CLK_XTAL32K_FREQ_APPROX
+
+/* Alias of deprecated function names */
+#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq)
+#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get()
+#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
+#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/soc.h

@@ -0,0 +1,243 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#include "esp_assert.h"
+#endif
+
+#include "esp_bit_defs.h"
+#include "reg_base.h"
+
+#define PRO_CPU_NUM (0)
+
+#define REG_UHCI_BASE(i)                        (DR_REG_UHCI0_BASE)                      // only one UHCI on C6
+#define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x1000)        // UART0 and UART1
+#define REG_UART_AHB_BASE(i)                    (0x60000000 + (i) * 0x10000)
+#define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C6
+#define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
+#define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
+#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE)                       // only one GPSPI on C6
+#define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE)                    // only one I2C on C6
+#define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE)                      // only one MCPWM on C6
+#define REG_TWAI_BASE(i)                        (DR_REG_TWAI_BASE + (i) * 0x2000)        // TWAI0 and TWAI1
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr)
+
+#ifndef __ASSEMBLER__
+
+//write value to register
+#define REG_WRITE(_r, _v)  do {                                                                                        \
+            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
+        } while(0)
+
+//read value from register
+#define REG_READ(_r) ({                                                                                                \
+            (*(volatile uint32_t *)(_r));                                                                              \
+        })
+
+//get bit or get bits from register
+#define REG_GET_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
+        })
+
+//set bit or set bits to register
+#define REG_SET_BIT(_r, _b)  do {                                                                                      \
+            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b);                                            \
+        } while(0)
+
+//clear bit or clear bits of register
+#define REG_CLR_BIT(_r, _b)  do {                                                                                      \
+            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b));                                         \
+        } while(0)
+
+//set bits of register controlled by mask
+#define REG_SET_BITS(_r, _b, _m) do {                                                                                  \
+            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m));                           \
+        } while(0)
+
+//get field from register, uses field _S & _V to determine mask
+#define REG_GET_FIELD(_r, _f) ({                                                                                       \
+            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
+        })
+
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) do {                                                                                 \
+            REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))));                  \
+        } while(0)
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//read value from register
+#define READ_PERI_REG(addr) ({                                                                                         \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
+        })
+
+//write value to register
+#define WRITE_PERI_REG(addr, val) do {                                                                                 \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
+        } while(0)
+
+//clear bits of register controlled by mask
+#define CLEAR_PERI_REG_MASK(reg, mask)  do {                                                                           \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
+        } while(0)
+
+//set bits of register controlled by mask
+#define SET_PERI_REG_MASK(reg, mask) do {                                                                              \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
+        } while(0)
+
+//get bits of register controlled by mask
+#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            (READ_PERI_REG(reg) & (mask));                                                                             \
+        })
+
+//get bits of register controlled by highest bit and lowest bit
+#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
+            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
+        })
+
+//set bits of register controlled by mask and shift
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do {                                                                \
+            WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) );      \
+        } while(0)
+
+//get field of register
+#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
+            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
+        })
+
+#endif /* !__ASSEMBLER__ */
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#if CONFIG_IDF_ENV_FPGA
+#define  APB_CLK_FREQ                                ( 40*1000000 )
+#else
+#define  APB_CLK_FREQ                                ( 80*1000000 )
+#endif
+#define  REF_CLK_FREQ                                ( 1000000 )
+#define  RTC_CLK_FREQ                                (20*1000000)
+#define  XTAL_CLK_FREQ                               (40*1000000)
+#define  UART_CLK_FREQ                               APB_CLK_FREQ
+#define  WDT_CLK_FREQ                                APB_CLK_FREQ
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
+#define  SPI_CLK_DIV                                 4
+#define  TICKS_PER_US_ROM                            40              // CPU is 80MHz
+#define  GPIO_MATRIX_DELAY_NS                        0
+//}}
+
+/* Overall memory map */
+/* Note: We should not use MACROs similar in cache_memory.h
+ * those are defined during run-time. But the MACROs here
+ * should be defined statically!
+ */
+
+#define SOC_IROM_LOW    0x42000000
+#define SOC_IROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7))
+#define SOC_DROM_LOW    SOC_IROM_HIGH
+#define SOC_DROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
+#define SOC_IROM_MASK_LOW  0x40000000
+#define SOC_IROM_MASK_HIGH 0x4004AC00
+#define SOC_DROM_MASK_LOW  0x4004AC00
+#define SOC_DROM_MASK_HIGH 0x40050000
+#define SOC_IRAM_LOW    0x40800000
+#define SOC_IRAM_HIGH   0x40880000
+#define SOC_DRAM_LOW    0x40800000
+#define SOC_DRAM_HIGH   0x40880000
+#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-C6 only has 16k LP memory
+#define SOC_RTC_IRAM_HIGH 0x50004000
+#define SOC_RTC_DRAM_LOW  0x50000000
+#define SOC_RTC_DRAM_HIGH 0x50004000
+#define SOC_RTC_DATA_LOW  0x50000000
+#define SOC_RTC_DATA_HIGH 0x50004000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW    0x40800000
+#define SOC_DIRAM_IRAM_HIGH   0x40880000
+#define SOC_DIRAM_DRAM_LOW    0x40800000
+#define SOC_DIRAM_DRAM_HIGH   0x40880000
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW  0x40800000
+#define SOC_DMA_HIGH 0x40880000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW     0x40800000
+#define SOC_BYTE_ACCESSIBLE_HIGH    0x40880000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW        0x40800000
+#define SOC_MEM_INTERNAL_HIGH       0x40880000
+#define SOC_MEM_INTERNAL_LOW1       0x40800000
+#define SOC_MEM_INTERNAL_HIGH1      0x40880000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// Debug region, not used by software
+#define SOC_DEBUG_LOW 0x20000000
+#define SOC_DEBUG_HIGH 0x28000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START         0x4087c770
+
+
+//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
+//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
+
+//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
+#define ETS_T1_WDT_INUM                         24
+#define ETS_CACHEERR_INUM                       25
+#define ETS_MEMPROT_ERR_INUM                    26
+//CPU0 Max valid interrupt number
+#define ETS_MAX_INUM                            31
+
+//CPU0 Interrupt number used in ROM, should be cancelled in SDK
+#define ETS_SLC_INUM                            1
+#define ETS_UART0_INUM                          5
+#define ETS_UART1_INUM                          5
+#define ETS_SPI2_INUM                           1
+//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
+#define ETS_GPIO_INUM       4
+
+//Other interrupt number should be managed by the user
+
+//Invalid interrupt for number interrupt matrix
+#define ETS_INVALID_INUM                        0
+
+//Interrupt medium level, used for INT WDT for example
+#define SOC_INTERRUPT_LEVEL_MEDIUM              4

components/soc/esp32c6/include/soc/soc_caps.h

@@ -0,0 +1,405 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The long term plan is to have a single soc_caps.h for each peripheral.
+// During the refactoring and multichip support development process, we
+// seperate these information into periph_caps.h for each peripheral and
+// include them here.
+
+/*
+ * These defines are parsed and imported as kconfig variables via the script
+ * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
+ *
+ * If this file is changed the script will automatically run the script
+ * and generate the kconfig variables as part of the pre-commit hooks.
+ *
+ * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c6/include/soc/'`
+ *
+ * For more information see `tools/gen_soc_caps_kconfig/README.md`
+ *
+*/
+
+#pragma once
+
+/*-------------------------- COMMON CAPS ---------------------------------------*/
+// #define SOC_ADC_SUPPORTED               1 // TODO: IDF-5310
+// #define SOC_DEDICATED_GPIO_SUPPORTED    1 // TODO: IDF-5331
+#define SOC_GDMA_SUPPORTED              1
+// #define SOC_TWAI_SUPPORTED              1 // TODO: IDF-5313
+#define SOC_BT_SUPPORTED                1
+#define SOC_ASYNC_MEMCPY_SUPPORTED      1
+#define SOC_USB_SERIAL_JTAG_SUPPORTED   1
+// #define SOC_TEMP_SENSOR_SUPPORTED       1 // TODO: IDF-5322
+#define SOC_WIFI_SUPPORTED              1
+#define SOC_SUPPORTS_SECURE_DL_MODE     1
+#define SOC_RISCV_COPROC_SUPPORTED      1
+#define SOC_EFUSE_KEY_PURPOSE_FIELD     1
+#define SOC_EFUSE_HAS_EFUSE_RST_BUG     1
+#define SOC_RTC_FAST_MEM_SUPPORTED      1
+#define SOC_RTC_MEM_SUPPORTED           1
+// #define SOC_I2S_SUPPORTED               1 // TODO: IDF-5314
+// #define SOC_RMT_SUPPORTED               1 // TODO: IDF-5320
+// #define SOC_SDM_SUPPORTED               1 // TODO: IDF-5318
+// #define SOC_LEDC_SUPPORTED              1 // TODO: IDF-5328
+// #define SOC_I2C_SUPPORTED               1 // TODO: IDF-5326
+#define SOC_SYSTIMER_SUPPORTED          1
+#define SOC_SUPPORT_COEXISTENCE         1
+// #define SOC_AES_SUPPORTED               1 // TODO: IDF-5356
+// #define SOC_MPI_SUPPORTED               1
+// #define SOC_SHA_SUPPORTED               1 // TODO: IDF-5353
+// #define SOC_HMAC_SUPPORTED              1 // TODO: IDF-5355
+// #define SOC_DIG_SIGN_SUPPORTED          1 // TODO: IDF-5360
+#define SOC_FLASH_ENC_SUPPORTED         1
+#define SOC_SECURE_BOOT_SUPPORTED       1
+// #define SOC_MEMPROT_SUPPORTED           1 // TODO: IDF-5684
+
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_40M            1
+
+// TODO: IDF-5356 (Copy from esp32c3, need check)
+/*-------------------------- AES CAPS -----------------------------------------*/
+#define SOC_AES_SUPPORT_DMA     (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_AES_GDMA            (1)
+
+#define SOC_AES_SUPPORT_AES_128 (1)
+#define SOC_AES_SUPPORT_AES_256 (1)
+
+// TODO: IDF-5310 (Copy from esp32c3, need check)
+/*-------------------------- ADC CAPS -------------------------------*/
+/*!< SAR ADC Module*/
+#define SOC_ADC_DIG_CTRL_SUPPORTED              1
+#define SOC_ADC_ARBITER_SUPPORTED               1
+#define SOC_ADC_FILTER_SUPPORTED                1
+#define SOC_ADC_MONITOR_SUPPORTED               1
+#define SOC_ADC_PERIPH_NUM                      (2)
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         ((PERIPH_NUM==0)? 5 : 1)
+#define SOC_ADC_MAX_CHANNEL_NUM                 (5)
+#define SOC_ADC_ATTEN_NUM                       (4)
+
+/*!< Digital */
+#define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
+#define SOC_ADC_PATT_LEN_MAX                    (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
+#define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
+#define SOC_ADC_DIGI_FILTER_NUM                 (2)
+#define SOC_ADC_DIGI_MONITOR_NUM                (2)
+/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
+#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
+#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+
+/*!< RTC */
+#define SOC_ADC_RTC_MIN_BITWIDTH                (12)
+#define SOC_ADC_RTC_MAX_BITWIDTH                (12)
+
+/*!< Calibration */
+#define SOC_ADC_CALIBRATION_V1_SUPPORTED        (0) /*!< support HW offset calibration version 1*/
+
+// ESP32C6-TODO: Copy from esp32c6, need check
+/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
+#define SOC_APB_BACKUP_DMA              (0)
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+#define SOC_BROWNOUT_RESET_SUPPORTED 1
+
+/*-------------------------- CACHE CAPS --------------------------------------*/
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#define SOC_CPU_CORES_NUM               (1U)
+#define SOC_CPU_INTR_NUM                32
+#define SOC_CPU_HAS_FLEXIBLE_INTC       1
+#define SOC_RV32A_SUPPORTED             1
+#define SOC_INT_PLIC_SUPPORTED          1       //riscv platform-level interrupt controller
+
+#define SOC_CPU_BREAKPOINTS_NUM         4
+#define SOC_CPU_WATCHPOINTS_NUM         4
+#define SOC_CPU_WATCHPOINT_SIZE         0x80000000 // bytes
+
+// TODO: IDF-5339 (Copy from esp32c3, need check)
+/*-------------------------- MMU CAPS ----------------------------------------*/
+#define SOC_MMU_PAGE_SIZE_CONFIGURABLE  (1)
+
+// TODO: IDF-5360 (Copy from esp32c3, need check)
+/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
+/** The maximum length of a Digital Signature in bits. */
+#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
+
+/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
+#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
+
+/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
+    See TRM DS chapter for more details */
+#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
+
+// TODO: IDF-5319 (Copy from esp32c3, need check)
+/*-------------------------- GDMA CAPS -------------------------------------*/
+#define SOC_GDMA_GROUPS                 (1U) // Number of GDMA groups
+#define SOC_GDMA_PAIRS_PER_GROUP        (3)  // Number of GDMA pairs in each group
+
+// TODO: IDF-5321 (Copy from esp32c3, need check)
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+// ESP32-C6 has 1 GPIO peripheral
+#define SOC_GPIO_PORT               (1U)
+#define SOC_GPIO_PIN_COUNT          (31)
+
+// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
+// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
+#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT       (1)
+// Force hold is a new function of ESP32-C6
+#define SOC_GPIO_SUPPORT_FORCE_HOLD         (1)
+// GPIO0~5 on ESP32C6 can support chip deep sleep wakeup
+#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
+
+#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
+
+// Support to configure sleep status
+#define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
+
+// TODO: IDF-5331 (Copy from esp32c3, need check)
+/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
+#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
+#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
+
+// TODO: IDF-5326 (Copy from esp32c3, need check)
+/*-------------------------- I2C CAPS ----------------------------------------*/
+// ESP32-C6 has 1 I2C
+#define SOC_I2C_NUM                 (1U)
+
+#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
+#define SOC_I2C_SUPPORT_SLAVE       (1)
+
+// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+
+#define SOC_I2C_SUPPORT_XTAL        (1)
+#define SOC_I2C_SUPPORT_RTC         (1)
+
+// TODO: IDF-5314 (Copy from esp32c3, need check)
+/*-------------------------- I2S CAPS ----------------------------------------*/
+#define SOC_I2S_NUM                 (1)
+#define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_PCM        (1)
+#define SOC_I2S_SUPPORTS_PDM        (1)
+#define SOC_I2S_SUPPORTS_PDM_TX     (1)
+#define SOC_I2S_SUPPORTS_PDM_CODEC  (1)
+#define SOC_I2S_SUPPORTS_TDM        (1)
+
+// TODO: IDF-5328 (Copy from esp32c3, need check)
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_APB_CLOCK   (1)
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
+#define SOC_LEDC_CHANNEL_NUM         (6)
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
+#define SOC_LEDC_SUPPORT_FADE_STOP   (1)
+
+// TODO: IDF-5684 (Copy from esp32c3, need check)
+/*-------------------------- MPU CAPS ----------------------------------------*/
+#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+#define SOC_MPU_MIN_REGION_SIZE                   0x20000000U
+#define SOC_MPU_REGIONS_MAX_NUM                   8
+#define SOC_MPU_REGION_RO_SUPPORTED               0
+#define SOC_MPU_REGION_WO_SUPPORTED               0
+
+// TODO: IDF-5320 (Copy from esp32c3, need check)
+/*--------------------------- RMT CAPS ---------------------------------------*/
+#define SOC_RMT_GROUPS                        1U /*!< One RMT group */
+#define SOC_RMT_TX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Transmit */
+#define SOC_RMT_RX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Receive */
+#define SOC_RMT_CHANNELS_PER_GROUP            4  /*!< Total 4 channels */
+#define SOC_RMT_MEM_WORDS_PER_CHANNEL         48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
+#define SOC_RMT_SUPPORT_RX_PINGPONG           1  /*!< Support Ping-Pong mode on RX path */
+#define SOC_RMT_SUPPORT_RX_DEMODULATION       1  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
+#define SOC_RMT_SUPPORT_TX_ASYNC_STOP         1  /*!< Support stop transmission asynchronously */
+#define SOC_RMT_SUPPORT_TX_LOOP_COUNT         1  /*!< Support transmit specified number of cycles in loop mode */
+#define SOC_RMT_SUPPORT_TX_SYNCHRO            1  /*!< Support coordinate a group of TX channels to start simultaneously */
+#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY  1  /*!< TX carrier can be modulated to data phase only */
+#define SOC_RMT_SUPPORT_XTAL                  1  /*!< Support set XTAL clock as the RMT clock source */
+#define SOC_RMT_SUPPORT_APB                   1  /*!< Support set APB as the RMT clock source */
+#define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST clock as the RMT clock source */
+
+// TODO: IDF-5348 (Copy from esp32c3, need check)
+/*-------------------------- RTC CAPS --------------------------------------*/
+#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH       (128)
+#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM        (108)
+#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN      (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
+#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE      (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
+
+#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE  (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+/* No dedicated RTCIO subsystem on ESP32-C6. RTC functions are still supported
+ * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
+#define SOC_RTCIO_PIN_COUNT    (0U)
+
+// TODO: IDF-5359 (Copy from esp32c3, need check)
+/*--------------------------- RSA CAPS ---------------------------------------*/
+#define SOC_RSA_MAX_BIT_LEN    (3072)
+
+// TODO: IDF-5353 (Copy from esp32c3, need check)
+/*--------------------------- SHA CAPS ---------------------------------------*/
+
+/* Max amount of bytes in a single DMA operation is 4095,
+   for SHA this means that the biggest safe amount of bytes is
+   31 blocks of 128 bytes = 3968
+*/
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
+
+/* The SHA engine is able to resume hashing from a user */
+#define SOC_SHA_SUPPORT_RESUME          (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_SHA_GDMA             (1)
+
+/* Supported HW algorithms */
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
+
+// TODO: IDF-5318 (Copy from esp32c3, need check)
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
+#define SOC_SDM_GROUPS             1U
+#define SOC_SDM_CHANNELS_PER_GROUP 4
+
+// TODO: IDF-5334 (Copy from esp32c3, need check)
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#define SOC_SPI_PERIPH_NUM          2
+#define SOC_SPI_PERIPH_CS_NUM(i)    6
+
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
+
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)  ({(void)host_id; 1;})
+
+// Peripheral supports output given level during its "dummy phase"
+#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+#define SOC_SPI_MAX_PRE_DIVIDER 16
+
+// TODO: IDF-5333 (Copy from esp32c3, need check)
+/*-------------------------- SPI MEM CAPS ---------------------------------------*/
+#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
+#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
+#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
+#define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
+#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
+#define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
+
+#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
+
+// TODO: IDF-5323 (Copy from esp32c3, need check)
+/*-------------------------- SYSTIMER CAPS ----------------------------------*/
+#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
+#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
+#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
+#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
+#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
+#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
+#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+
+// TODO: IDF-5332 (Copy from esp32c3, need check)
+/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
+#define SOC_TIMER_GROUPS                  (2)
+#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
+#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
+#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
+#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
+
+// TODO: IDF-5313 (Copy from esp32c3, need check)
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+#define SOC_TWAI_BRP_MIN                2
+#define SOC_TWAI_BRP_MAX                16384
+#define SOC_TWAI_SUPPORTS_RX_STATUS     1
+
+// TODO: IDF-5357 (Copy from esp32c3, need check)
+/*-------------------------- Secure Boot CAPS----------------------------*/
+#define SOC_SECURE_BOOT_V2_RSA              1
+#define SOC_SECURE_BOOT_V2_ECC              1
+#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
+#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS   1
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY  1
+
+// TODO: IDF-5358 (Copy from esp32c3, need check)
+/*-------------------------- Flash Encryption CAPS----------------------------*/
+#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (32)
+#define SOC_FLASH_ENCRYPTION_XTS_AES        1
+#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
+
+// TODO: IDF-5684 (Copy from esp32c3, need check)
+/*-------------------------- MEMPROT CAPS ------------------------------------*/
+#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE   16
+#define SOC_MEMPROT_MEM_ALIGN_SIZE          512
+
+// TODO: IDF-5338 (Copy from esp32c3, need check)
+/*-------------------------- UART CAPS ---------------------------------------*/
+// ESP32-C6 has 2 UARTs
+#define SOC_UART_NUM                (2)
+#define SOC_UART_FIFO_LEN           (128)      /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX        (5000000)  /*!< Max bit rate supported by UART */
+
+#define SOC_UART_SUPPORT_APB_CLK    (1)     /*!< Support APB as the clock source */
+#define SOC_UART_SUPPORT_RTC_CLK    (0)     /*!< Support RTC clock as the clock source */ // TODO: IDF-5338
+#define SOC_UART_SUPPORT_XTAL_CLK   (1)     /*!< Support XTAL clock as the clock source */
+// #define SOC_UART_SUPPORT_WAKEUP_INT (1)         /*!< Support UART wakeup interrupt */ // TODO: IDF-5338
+#define SOC_UART_REQUIRE_CORE_RESET (1)
+
+// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
+#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
+
+// TODO: IDF-5679 (Copy from esp32c3, need check)
+/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
+#define SOC_COEX_HW_PTI                 (1)
+
+// TODO: IDF-5680 (Copy from esp32c3, need check)
+/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
+#define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
+#define SOC_MAC_BB_PD_MEM_SIZE          (192*4)
+
+// TODO: IDF-5679 (Copy from esp32c3, need check)
+/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
+#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
+
+// TODO: IDF-5351 (Copy from esp32c3, need check)
+/*-------------------------- Power Management CAPS ----------------------------*/
+#define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
+
+#define SOC_PM_SUPPORT_BT_WAKEUP        (1)
+
+#define SOC_PM_SUPPORT_CPU_PD           (1)
+
+#define SOC_PM_SUPPORT_WIFI_PD          (1)
+
+#define SOC_PM_SUPPORT_BT_PD            (1)
+
+// TODO: IDF-5322 (Copy from esp32c3, need check)
+/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)
+
+// TODO: IDF-5679 (Copy from esp32c3, need check)
+/*------------------------------------ WI-FI CAPS ------------------------------------*/
+#define SOC_WIFI_HW_TSF                 (1)    /*!< Support hardware TSF */
+#define SOC_WIFI_FTM_SUPPORT            (1)    /*!< Support FTM */
+#define SOC_WIFI_GCMP_SUPPORT           (1)    /*!< Support GCMP(GCMP128 and GCMP256) */
+#define SOC_WIFI_WAPI_SUPPORT           (1)    /*!< Support WAPI */
+#define SOC_WIFI_CSI_SUPPORT            (1)    /*!< Support CSI */
+#define SOC_WIFI_MESH_SUPPORT           (1)    /*!< Support WIFI MESH */

components/soc/esp32c6/include/soc/soc_pins.h

@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
+#pragma once
+
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"

components/soc/esp32c6/include/soc/spi_pins.h

@@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_SPI_PINS_H_
+#define _SOC_SPI_PINS_H_
+
+#define SPI_FUNC_NUM            0
+#define SPI_IOMUX_PIN_NUM_HD    12
+#define SPI_IOMUX_PIN_NUM_CS    14
+#define SPI_IOMUX_PIN_NUM_MOSI  16
+#define SPI_IOMUX_PIN_NUM_CLK   15
+#define SPI_IOMUX_PIN_NUM_MISO  17
+#define SPI_IOMUX_PIN_NUM_WP    13
+
+#define SPI2_FUNC_NUM           2
+#define SPI2_IOMUX_PIN_NUM_MISO 2
+#define SPI2_IOMUX_PIN_NUM_HD   4
+#define SPI2_IOMUX_PIN_NUM_WP   5
+#define SPI2_IOMUX_PIN_NUM_CLK  6
+#define SPI2_IOMUX_PIN_NUM_MOSI 7
+#define SPI2_IOMUX_PIN_NUM_CS   10
+
+#endif

components/soc/esp32c6/include/soc/system_reg.h

@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/hp_system_reg.h"
+
+// TODO: IDF-5720
+#include "intpri_reg.h"
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
+#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0

components/soc/esp32c6/include/soc/uart_channel.h

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3.
+
+#ifndef _SOC_UART_CHANNEL_H
+#define _SOC_UART_CHANNEL_H
+
+//UART channels
+#define UART_GPIO21_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  21
+#define UART_GPIO20_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  20
+
+#define UART_TXD_GPIO21_DIRECT_CHANNEL  UART_GPIO21_DIRECT_CHANNEL
+#define UART_RXD_GPIO20_DIRECT_CHANNEL  UART_GPIO20_DIRECT_CHANNEL
+
+#endif

components/soc/esp32c6/include/soc/uart_pins.h

@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/io_mux_reg.h"
+
+/* Specify the number of pins for UART */
+#define SOC_UART_PINS_COUNT  (4)
+
+/* Specify the GPIO pin number for each UART signal in the IOMUX */
+#define U0RXD_GPIO_NUM 17
+#define U0TXD_GPIO_NUM 16
+#define U0RTS_GPIO_NUM (-1)
+#define U0CTS_GPIO_NUM (-1)
+
+#define U1RXD_GPIO_NUM (-1)
+#define U1TXD_GPIO_NUM (-1)
+#define U1RTS_GPIO_NUM (-1)
+#define U1CTS_GPIO_NUM (-1)
+
+/* The following defines are necessary for reconfiguring the UART
+ * to use IOMUX, at runtime. */
+#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
+#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+/* No func for the following pins, they shall not be used */
+#define U0RTS_MUX_FUNC  (-1)
+#define U0CTS_MUX_FUNC  (-1)
+/* Same goes for UART1 */
+#define U1TXD_MUX_FUNC  (-1)
+#define U1RXD_MUX_FUNC  (-1)
+#define U1RTS_MUX_FUNC  (-1)
+#define U1CTS_MUX_FUNC  (-1)

components/soc/esp32c6/include/soc/wdev_reg.h

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc.h"
+#include "soc/lpperi_reg.h"
+
+/* Hardware random number generator register */
+#define WDEV_RND_REG LPPERI_RNG_DATA_REG

components/soc/esp32c6/ledc_periph.c

@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/ledc_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every LEDC peripheral: GPIO signals
+*/
+const ledc_signal_conn_t ledc_periph_signal[1] = {
+	{
+        .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
+	}
+};

components/soc/esp32c6/rmt_periph.c

@@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rmt_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const rmt_signal_conn_t rmt_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_RMT_MODULE,
+            .irq = ETS_RMT_INTR_SOURCE,
+            .channels = {
+                [0] = {
+                    .tx_sig = RMT_SIG_OUT0_IDX,
+                    .rx_sig = -1
+                },
+                [1] = {
+                    .tx_sig = RMT_SIG_OUT1_IDX,
+                    .rx_sig = -1
+                },
+                [2] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_IN0_IDX
+                },
+                [3] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_IN1_IDX
+                },
+            }
+        }
+    }
+};

components/soc/esp32c6/sdm_periph.c

@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/sdm_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
+    .channels = {
+        [0] = {
+            GPIO_SD0_OUT_IDX
+        },
+        [1] = {
+            GPIO_SD1_OUT_IDX
+        },
+        [2] = {
+            GPIO_SD2_OUT_IDX
+        },
+        [3] = {
+            GPIO_SD3_OUT_IDX
+        }
+    }
+};

components/soc/esp32c6/spi_periph.c

@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/spi_periph.h"
+#include "stddef.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    { // TODO: IDF-5333 Need check
+        .spiclk_in = 0,/* SPI clock is not an input signal*/
+        .spics_in = 0,/* SPI cs is not an input signal*/
+        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_MSPI_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI_MODULE,
+        .hw = (spi_dev_t *) &SPIMEM1,
+        .func = SPI_FUNC_NUM,
+    }, { // TODO: IDF-5334 Need check
+        .spiclk_out = FSPICLK_OUT_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
+        .irq = ETS_GSPI2_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI2_MODULE,
+        .hw = &GPSPI2,
+        .func = SPI2_FUNC_NUM,
+    }
+};

components/soc/esp32c6/temperature_sensor_periph.c

@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/temperature_sensor_periph.h"
+
+const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
+    /*Offset   reg_val  min  max  error */
+    {-2,     5,    50,  125,   3},
+    {-1,     7,    20,  100,   2},
+    { 0,    15,   -10,   80,   1},
+    { 1,    11,   -30,   50,   2},
+    { 2,    10,   -40,   20,   3},
+};

components/soc/esp32c6/timer_periph.c

@@ -0,0 +1,24 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/timer_periph.h"
+
+const timer_group_signal_conn_t timer_group_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_TIMG0_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+            }
+        },
+        [1] = {
+            .module = PERIPH_TIMG1_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
+            }
+        }
+    }
+};

components/soc/esp32c6/uart_periph.c

@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/uart_periph.h"
+
+/*
+ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
+   {
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U0TXD_GPIO_NUM,
+                .iomux_func = U0TXD_MUX_FUNC,
+                .input = 0,
+                .signal = U0TXD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U0RXD_GPIO_NUM,
+                .iomux_func = U0RXD_MUX_FUNC,
+                .input = 1,
+                .signal = U0RXD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U0RTS_GPIO_NUM,
+                .iomux_func = U0RTS_MUX_FUNC,
+                .input = 0,
+                .signal = U0RTS_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U0CTS_GPIO_NUM,
+                .iomux_func = U0CTS_MUX_FUNC,
+                .input = 1,
+                .signal = U0CTS_IN_IDX,
+            }
+        },
+        .irq = ETS_UART0_INTR_SOURCE,
+        .module = PERIPH_UART0_MODULE,
+    },
+
+    {
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U1TXD_GPIO_NUM,
+                .iomux_func = U1TXD_MUX_FUNC,
+                .input = 0,
+                .signal = U1TXD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U1RXD_GPIO_NUM,
+                .iomux_func = U1RXD_MUX_FUNC,
+                .input = 1,
+                .signal = U1RXD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U1RTS_GPIO_NUM,
+                .iomux_func = U1RTS_MUX_FUNC,
+                .input = 0,
+                .signal = U1RTS_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U1CTS_GPIO_NUM,
+                .iomux_func = U1CTS_MUX_FUNC,
+                .input = 1,
+                .signal = U1CTS_IN_IDX,
+            },
+        },
+        .irq = ETS_UART1_INTR_SOURCE,
+        .module = PERIPH_UART1_MODULE,
+    },
+};

components/soc/esp32h2/include/soc/hwcrypto_reg.h

@@ -1,16 +1,9 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
 
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 #ifndef __HWCRYPTO_REG_H__
 #define __HWCRYPTO_REG_H__
 
@@ -113,11 +106,6 @@
 #define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
 #define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
 
-#define AES_INT_CLR_REG         ((DR_REG_AES_BASE) + 0xAC)
-#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
-#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
-#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
-
 /* AES_STATE_REG values */
 #define AES_STATE_IDLE 0
 #define AES_STATE_BUSY 1

components/soc/esp32s2/include/soc/hwcrypto_reg.h

@@ -1,16 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
 
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 #ifndef __HWCRYPTO_REG_H__
 #define __HWCRYPTO_REG_H__
 
@@ -102,11 +95,6 @@
 #define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
 #define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
 
-#define AES_INT_CLR_REG         ((DR_REG_AES_BASE) + 0xAC)
-#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
-#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
-#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
-
 /* AES_STATE_REG values */
 #define AES_STATE_IDLE 0
 #define AES_STATE_BUSY 1