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Merge branch 'bugfix/add_mmu_pwr_ctrl_reg_to_retention_link' into 'master'

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bugfix: esp32c6 light sleep minor fixes

Closes WIFI-5353

See merge request espressif/esp-idf!22619
This commit is contained in:
Jiang Jiang Jian
2023-03-08 14:44:51 +08:00
parent fc9538c63d 43bf9fd3ab
commit 7dd7498212
6 changed files with 51 additions and 62 deletions
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28
components/esp_hw_support/modem_clock.c
View File

@@ -48,21 +48,17 @@ typedef struct modem_clock_context {
static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx, bool enable)
{
modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifi_mac_clock(ctx->hal->syscon_dev, enable);
if (enable) {
modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifi_mac_clock(ctx->hal->syscon_dev, enable);
}
}
static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx, bool enable)
{
modem_syscon_ll_enable_wifibb_160x1_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_80x1_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_40x1_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_80x_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_40x_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_80m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_44m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_40m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_wifibb_22m_clock(ctx->hal->syscon_dev, enable);
if (enable) {
modem_syscon_ll_clk_wifibb_configure(ctx->hal->syscon_dev, enable);
}
}
static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, bool enable)
@@ -91,10 +87,12 @@ static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, boo
static void IRAM_ATTR modem_clock_fe_configure(modem_clock_context_t *ctx, bool enable)
{
modem_syscon_ll_enable_fe_apb_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_cal_160m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_160m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_80m_clock(ctx->hal->syscon_dev, enable);
if (enable) {
modem_syscon_ll_enable_fe_apb_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_cal_160m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_160m_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_fe_80m_clock(ctx->hal->syscon_dev, enable);
}
}
static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable)

33
components/esp_hw_support/sleep_clock.c
View File

@@ -48,43 +48,12 @@ esp_err_t sleep_clock_modem_retention_init(void)
{
#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
#define MODEM_WIFI_RETENTION_CLOCK (MODEM_SYSCON_CLK_WIFI_APB_EN | MODEM_SYSCON_CLK_FE_APB_EN)
#define WIFI_MAC_MODEM_STATE_CLK_EN (MODEM_SYSCON_CLK_WIFIMAC_EN | MODEM_SYSCON_CLK_WIFI_APB_EN)
#define WIFI_BB_MODEM_STATE_CLK_EN (MODEM_SYSCON_CLK_WIFIBB_22M_EN | \
MODEM_SYSCON_CLK_WIFIBB_40M_EN | \
MODEM_SYSCON_CLK_WIFIBB_44M_EN | \
MODEM_SYSCON_CLK_WIFIBB_80M_EN | \
MODEM_SYSCON_CLK_WIFIBB_40X_EN | \
MODEM_SYSCON_CLK_WIFIBB_80X_EN | \
MODEM_SYSCON_CLK_WIFIBB_40X1_EN | \
MODEM_SYSCON_CLK_WIFIBB_80X1_EN | \
MODEM_SYSCON_CLK_WIFIBB_160X1_EN)
#define FE_MODEM_STATE_CLK_EN (MODEM_SYSCON_CLK_FE_80M_EN | \
MODEM_SYSCON_CLK_FE_160M_EN | \
MODEM_SYSCON_CLK_FE_CAL_160M_EN | \
MODEM_SYSCON_CLK_FE_APB_EN)
#define WIFI_MODEM_STATE_CLOCK_EN (WIFI_MAC_MODEM_STATE_CLK_EN | WIFI_BB_MODEM_STATE_CLK_EN | FE_MODEM_STATE_CLK_EN)
const static sleep_retention_entries_config_t modem_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0x00), MODEM_SYSCON_CLK_CONF1_REG, 0x0, 0x200, 0, 1), .owner = ENTRY(0) }, /* WiFi MAC clock disable */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0x01), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0x02), MODEM_SYSCON_CLK_CONF1_REG, MODEM_SYSCON_CLK_WIFIMAC_EN,0x200, 1, 0), .owner = ENTRY(0) }, /* WiFi MAC clock enable */
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0x03), MODEM_SYSCON_CLK_CONF1_REG, MODEM_WIFI_RETENTION_CLOCK, 0x10400, 0, 0), .owner = ENTRY(0) }, /* WiFi (MAC, BB and FE) retention clock enable */
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0x04), MODEM_SYSCON_CLK_CONF1_REG, WIFI_MODEM_STATE_CLOCK_EN, 0x1e7ff, 1, 0), .owner = ENTRY(1) }
};
const static sleep_retention_entries_config_t modem_retention_clock[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(0xff), MODEM_SYSCON_CLK_CONF1_REG, 0x0, 0x10400, 0, 0), .owner = ENTRY(0) } /* WiFi (MAC, BB and FE) retention clock disable */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
};
esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_2, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 2 level priority");
err = sleep_retention_entries_create(modem_retention_clock, ARRAY_SIZE(modem_retention_clock), REGDMA_LINK_PRI_7, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, lowest level priority");
ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
return ESP_OK;
}

16
components/esp_hw_support/sleep_retention.c
View File

@@ -182,16 +182,14 @@ static void sleep_retention_entries_stats(void)
#if REGDMA_LINK_DBG
void sleep_retention_entries_show_memories(void)
{
if (&s_retention.lock) {
_lock_acquire_recursive(&s_retention.lock);
if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY && s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
for (int entry = 0; entry < ARRAY_SIZE(s_retention.lists[s_retention.highpri].entries); entry++) {
ESP_LOGW(TAG, "Print sleep retention entries[%d] memories:", entry);
regdma_link_show_memories(s_retention.lists[s_retention.highpri].entries[entry], entry);
}
_lock_acquire_recursive(&s_retention.lock);
if (s_retention.highpri >= SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY && s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
for (int entry = 0; entry < ARRAY_SIZE(s_retention.lists[s_retention.highpri].entries); entry++) {
ESP_LOGW(TAG, "Print sleep retention entries[%d] memories:", entry);
regdma_link_show_memories(s_retention.lists[s_retention.highpri].entries[entry], entry);
}
_lock_release_recursive(&s_retention.lock);
}
_lock_release_recursive(&s_retention.lock);
}
#endif
@@ -343,7 +341,7 @@ void sleep_retention_entries_destroy(int module)
s_retention.lock = NULL;
return;
}
_lock_acquire_recursive(&s_retention.lock);
_lock_release_recursive(&s_retention.lock);
}
static esp_err_t sleep_retention_entries_create_impl(const sleep_retention_entries_config_t retent[], int num, regdma_link_priority_t priority, int module)

8
components/esp_hw_support/sleep_system_peripheral.c
View File

@@ -141,25 +141,25 @@ esp_err_t sleep_sys_periph_spimem_retention_init(void)
#define N_REGS_SPI1_MEM_0() (((SPI_MEM_SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
#define N_REGS_SPI1_MEM_1() (((SPI_MEM_SPI_SMEM_AC_REG(1) - SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(1)) / 4) + 1)
#define N_REGS_SPI1_MEM_2() (1)
#define N_REGS_SPI1_MEM_3() (((SPI_MEM_DATE_REG(1) - SPI_MEM_DPA_CTRL_REG(1)) / 4) + 1)
#define N_REGS_SPI1_MEM_3() (((SPI_MEM_DATE_REG(1) - SPI_MEM_MMU_POWER_CTRL_REG(1)) / 4) + 1)
#define N_REGS_SPI0_MEM_0() (((SPI_MEM_SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_1() (((SPI_MEM_SPI_SMEM_AC_REG(0) - SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_2() (1)
#define N_REGS_SPI0_MEM_3() (((SPI_MEM_DATE_REG(0) - SPI_MEM_DPA_CTRL_REG(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_3() (((SPI_MEM_DATE_REG(0) - SPI_MEM_MMU_POWER_CTRL_REG(0)) / 4) + 1)
const static sleep_retention_entries_config_t spimem_regs_retention[] = {
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1), REG_SPI_MEM_BASE(1), N_REGS_SPI1_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(1), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(1), N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLOCK_GATE_REG(1), N_REGS_SPI1_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI_MEM_DPA_CTRL_REG(1), SPI_MEM_DPA_CTRL_REG(1), N_REGS_SPI1_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI_MEM_MMU_POWER_CTRL_REG(1), SPI_MEM_MMU_POWER_CTRL_REG(1), N_REGS_SPI1_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), REG_SPI_MEM_BASE(0), REG_SPI_MEM_BASE(0), N_REGS_SPI0_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(0), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(0), N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLOCK_GATE_REG(0), N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_DPA_CTRL_REG(0), SPI_MEM_DPA_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_POWER_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
};
esp_err_t err = sleep_retention_entries_create(spimem_regs_retention, ARRAY_SIZE(spimem_regs_retention), SLEEP_RETENTION_PERIPHERALS_PRIORITY_DEFAULT, SLEEP_RETENTION_MODULE_SPIMEM);

4
components/esp_phy/src/phy_init.c
View File

@@ -418,11 +418,13 @@ void esp_mac_bb_pd_mem_deinit(void)
IRAM_ATTR void esp_mac_bb_power_up(void)
{
esp_wifi_bt_power_domain_on();
#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
if (s_mac_bb_pd_mem == NULL) {
return;
}
#endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
esp_wifi_bt_power_domain_on();
#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
if (!s_mac_bb_pu) {
esp_phy_common_clock_enable();
phy_freq_mem_backup(false, s_mac_bb_pd_mem);

24
components/hal/esp32c6/include/hal/modem_syscon_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -253,6 +253,28 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
hw->modem_rst_conf.val = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
{
if(en){
hw->clk_conf1.val = hw->clk_conf1.val | mask;
} else {
hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
}
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
{
/* Configure
clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m
clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1
clk_wifibb_160x1
*/
modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff);
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_22m_clock(modem_syscon_dev_t *hw, bool en)
{