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fix(i2s): return error when mclk_div is smaller than 2

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This commit is contained in:
laokaiyao
2024-12-17 14:41:02 +08:00
parent a47e157731
commit 7fb15156ae
5 changed files with 22 additions and 8 deletions
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8
components/esp_driver_i2s/i2s_pdm.c
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@@ -44,8 +44,8 @@ static esp_err_t i2s_pdm_tx_calculate_clock(i2s_chan_handle_t handle, const i2s_
clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
clk_info->mclk_div = clk_info->sclk / clk_info->mclk; clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
/* Check if the configuration is correct */ /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
/* Set up sampling configuration */ /* Set up sampling configuration */
i2s_ll_tx_set_pdm_fpfs(handle->controller->hal.dev, pdm_tx_clk->up_sample_fp, pdm_tx_clk->up_sample_fs); i2s_ll_tx_set_pdm_fpfs(handle->controller->hal.dev, pdm_tx_clk->up_sample_fp, pdm_tx_clk->up_sample_fs);
i2s_ll_tx_set_pdm_over_sample_ratio(handle->controller->hal.dev, over_sample_ratio); i2s_ll_tx_set_pdm_over_sample_ratio(handle->controller->hal.dev, over_sample_ratio);
@@ -337,8 +337,8 @@ static esp_err_t i2s_pdm_rx_calculate_clock(i2s_chan_handle_t handle, const i2s_
clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
clk_info->mclk_div = clk_info->sclk / clk_info->mclk; clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
/* Check if the configuration is correct */ /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
/* Set down-sampling configuration */ /* Set down-sampling configuration */
i2s_ll_rx_set_pdm_dsr(handle->controller->hal.dev, pdm_rx_clk->dn_sample_mode); i2s_ll_rx_set_pdm_dsr(handle->controller->hal.dev, pdm_rx_clk->dn_sample_mode);
return ESP_OK; return ESP_OK;

6
components/esp_driver_i2s/i2s_std.c
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@@ -51,13 +51,15 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std
#if SOC_I2S_HW_VERSION_2 #if SOC_I2S_HW_VERSION_2
clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ?
clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
float min_mclk_div = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? 0.99 : 1.99;
#else #else
clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
float min_mclk_div = 1.99;
#endif #endif
clk_info->mclk_div = clk_info->sclk / clk_info->mclk; clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
/* Check if the configuration is correct */ /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large for the current clock source"); ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > min_mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate or mclk_multiple is too large for the current clock source");
return ESP_OK; return ESP_OK;
} }

5
components/esp_driver_i2s/i2s_tdm.c
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@@ -61,10 +61,11 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm
} }
clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ?
clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
float min_mclk_div = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? 0.99 : 1.99;
clk_info->mclk_div = clk_info->sclk / clk_info->mclk; clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
/* Check if the configuration is correct */ /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large for the current clock source"); ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > min_mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate or mclk_multiple is too large for the current clock source");
return ESP_OK; return ESP_OK;
} }

4
components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
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@@ -879,7 +879,11 @@ TEST_CASE("I2S_package_lost_test", "[i2s]")
TEST_ESP_OK(i2s_channel_register_event_callback(rx_handle, &cbs, &count)); TEST_ESP_OK(i2s_channel_register_event_callback(rx_handle, &cbs, &count));
uint32_t test_freq[] = {16000, 32000, 48000, 64000, 96000, 128000, 144000}; uint32_t test_freq[] = {16000, 32000, 48000, 64000, 96000, 128000, 144000};
#if CONFIG_IDF_TARGET_ESP32P4
uint32_t test_num = 4;
#else
uint32_t test_num = sizeof(test_freq) / sizeof(uint32_t); uint32_t test_num = sizeof(test_freq) / sizeof(uint32_t);
#endif // CONFIG_IDF_TARGET_ESP32P4
uint8_t *data = (uint8_t *)calloc(TEST_RECV_BUF_LEN, sizeof(uint8_t)); uint8_t *data = (uint8_t *)calloc(TEST_RECV_BUF_LEN, sizeof(uint8_t));
size_t bytes_read = 0; size_t bytes_read = 0;
int i; int i;

7
components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
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@@ -339,6 +339,13 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external)
std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL; std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL;
std_cfg.clk_cfg.ext_clk_freq_hz = 22579200; std_cfg.clk_cfg.ext_clk_freq_hz = 22579200;
} }
#if CONFIG_IDF_TARGET_ESP32P4
else {
// Use APLL instead.
// Because the default clock source is not sufficient for 22.58M MCLK
std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_APLL;
}
#endif
TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg)); TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg)); TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));