diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 33161ac474..b73a13d777 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -39,10 +39,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_BLUEDROID_SUPPORTED - bool - default y - config SOC_CLASSIC_BT_SUPPORTED bool default y diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 38cbe76484..0002dd016a 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -69,7 +69,6 @@ #define SOC_MCPWM_SUPPORTED 1 #define SOC_SDMMC_HOST_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_BLUEDROID_SUPPORTED 1 #define SOC_CLASSIC_BT_SUPPORTED 1 #define SOC_PCNT_SUPPORTED 1 #define SOC_WIFI_SUPPORTED 1 diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index b64541ba5a..fbe6a60578 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -21,7 +21,11 @@ config SOC_GDMA_SUPPORTED config SOC_BT_SUPPORTED bool - default n + default y + +config SOC_ESP_NIMBLE_CONTROLLER + bool + default y config SOC_WIFI_SUPPORTED bool diff --git a/components/soc/esp32c2/include/soc/modem_clkrst_reg.h b/components/soc/esp32c2/include/soc/modem_clkrst_reg.h new file mode 100644 index 0000000000..172de0b263 --- /dev/null +++ b/components/soc/esp32c2/include/soc/modem_clkrst_reg.h @@ -0,0 +1,126 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MODEM_CLKRST_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x0) +/* MODEM_CLKRST_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_CLK_EN (BIT(0)) +#define MODEM_CLKRST_CLK_EN_M (BIT(0)) +#define MODEM_CLKRST_CLK_EN_V 0x1 +#define MODEM_CLKRST_CLK_EN_S 0 + +#define MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x4) +/* MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h0 ; */ +/*description: .*/ +#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM 0x000000FF +#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_M ((MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_V)<<(MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S)) +#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_V 0xFF +#define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S 4 +/* MODEM_CLKRST_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_M (BIT(3)) +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_V 0x1 +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S 3 +/* MODEM_CLKRST_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL_M (BIT(2)) +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL_V 0x1 +#define MODEM_CLKRST_LP_TIMER_SEL_XTAL_S 2 +/* MODEM_CLKRST_LP_TIMER_SEL_8M : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_LP_TIMER_SEL_8M (BIT(1)) +#define MODEM_CLKRST_LP_TIMER_SEL_8M_M (BIT(1)) +#define MODEM_CLKRST_LP_TIMER_SEL_8M_V 0x1 +#define MODEM_CLKRST_LP_TIMER_SEL_8M_S 1 +/* MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW (BIT(0)) +#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_M (BIT(0)) +#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_V 0x1 +#define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S 0 + +#define MODEM_CLKRST_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x8) +/* MODEM_CLKRST_COEX_LPCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h0 ; */ +/*description: .*/ +#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM 0x000000FF +#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_M ((MODEM_CLKRST_COEX_LPCLK_DIV_NUM_V)<<(MODEM_CLKRST_COEX_LPCLK_DIV_NUM_S)) +#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_V 0xFF +#define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_S 4 +/* MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K (BIT(3)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_M (BIT(3)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_V 0x1 +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_S 3 +/* MODEM_CLKRST_COEX_LPCLK_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL (BIT(2)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_M (BIT(2)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_V 0x1 +#define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_S 2 +/* MODEM_CLKRST_COEX_LPCLK_SEL_8M : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_COEX_LPCLK_SEL_8M (BIT(1)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_8M_M (BIT(1)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_8M_V 0x1 +#define MODEM_CLKRST_COEX_LPCLK_SEL_8M_S 1 +/* MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW (BIT(0)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_M (BIT(0)) +#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_V 0x1 +#define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_S 0 + +#define MODEM_CLKRST_BLE_TIMER_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0xC) +/* MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE (BIT(1)) +#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_M (BIT(1)) +#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_V 0x1 +#define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_S 1 +/* MODEM_CLKRST_BLETIMER_USE_XTAL : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_CLKRST_BLETIMER_USE_XTAL (BIT(0)) +#define MODEM_CLKRST_BLETIMER_USE_XTAL_M (BIT(0)) +#define MODEM_CLKRST_BLETIMER_USE_XTAL_V 0x1 +#define MODEM_CLKRST_BLETIMER_USE_XTAL_S 0 + +#define MODEM_CLKRST_ETM_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x10) +/* MODEM_CLKRST_ETM_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_ETM_CLK_ACTIVE (BIT(1)) +#define MODEM_CLKRST_ETM_CLK_ACTIVE_M (BIT(1)) +#define MODEM_CLKRST_ETM_CLK_ACTIVE_V 0x1 +#define MODEM_CLKRST_ETM_CLK_ACTIVE_S 1 +/* MODEM_CLKRST_ETM_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_CLKRST_ETM_CLK_SEL (BIT(0)) +#define MODEM_CLKRST_ETM_CLK_SEL_M (BIT(0)) +#define MODEM_CLKRST_ETM_CLK_SEL_V 0x1 +#define MODEM_CLKRST_ETM_CLK_SEL_S 0 + +#define MODEM_CLKRST_DATE_REG (DR_REG_MODEM_CLKRST_BASE + 0xC) +/* MODEM_CLKRST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2107270 ; */ +/*description: .*/ +#define MODEM_CLKRST_DATE 0x0FFFFFFF +#define MODEM_CLKRST_DATE_M ((MODEM_CLKRST_DATE_V)<<(MODEM_CLKRST_DATE_S)) +#define MODEM_CLKRST_DATE_V 0xFFFFFFF +#define MODEM_CLKRST_DATE_S 0 + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c2/include/soc/periph_defs.h b/components/soc/esp32c2/include/soc/periph_defs.h index 97ffbefdc7..ad812d4eb1 100644 --- a/components/soc/esp32c2/include/soc/periph_defs.h +++ b/components/soc/esp32c2/include/soc/periph_defs.h @@ -32,6 +32,7 @@ typedef enum { PERIPH_GDMA_MODULE, PERIPH_SYSTIMER_MODULE, PERIPH_SARADC_MODULE, + PERIPH_MODEM_RPA_MODULE, PERIPH_MODULE_MAX } periph_module_t; diff --git a/components/soc/esp32c2/include/soc/reg_base.h b/components/soc/esp32c2/include/soc/reg_base.h index 77973a6cca..bdfe3f8039 100644 --- a/components/soc/esp32c2/include/soc/reg_base.h +++ b/components/soc/esp32c2/include/soc/reg_base.h @@ -40,5 +40,6 @@ #define DR_REG_BLE_TIMER_BASE 0x6004B800 #define DR_REG_BLE_SEC_BASE 0x6004C000 #define DR_REG_COEX_BIT_BASE 0x6004C400 +#define DR_REG_MODEM_CLKRST_BASE 0x6004d800 #define DR_REG_I2C_MST_BASE 0x6004E800 #define DR_REG_AES_XTS_BASE 0x600CC000 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index ab6a666564..55780a0dfb 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -29,7 +29,8 @@ #define SOC_ADC_SUPPORTED 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 -#define SOC_BT_SUPPORTED 0 // Enable during bringup, IDF-4357 +#define SOC_BT_SUPPORTED 1 +#define SOC_ESP_NIMBLE_CONTROLLER 1 #define SOC_WIFI_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 diff --git a/components/soc/esp32c2/include/soc/syscon_reg.h b/components/soc/esp32c2/include/soc/syscon_reg.h index bdbade2d89..9c4f8b5e61 100644 --- a/components/soc/esp32c2/include/soc/syscon_reg.h +++ b/components/soc/esp32c2/include/soc/syscon_reg.h @@ -209,6 +209,7 @@ extern "C" { #define BLE_REG_REST_BIT BIT(11) #define BLE_PWR_REG_REST_BIT BIT(12) #define BLE_BB_REG_REST_BIT BIT(13) +#define BLE_RPA_REST_BIT BIT(27) #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 74c34aae1d..4ebedf8127 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -27,10 +27,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_BLUEDROID_SUPPORTED - bool - default y - config SOC_ASYNC_MEMCPY_SUPPORTED bool default y diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 41e79af81e..e6c9e9ddeb 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -31,7 +31,6 @@ #define SOC_GDMA_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_BLUEDROID_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 0d0ea68d3b..6ed1c9e699 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -27,10 +27,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_BLUEDROID_SUPPORTED - bool - default y - config SOC_ESP_NIMBLE_CONTROLLER bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index fc4d2a4d09..18bc3bfbd3 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -39,7 +39,6 @@ #define SOC_GDMA_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_BLUEDROID_SUPPORTED 1 #define SOC_ESP_NIMBLE_CONTROLLER 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 443c3da2f5..7a60bfd6c6 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -115,10 +115,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_BLUEDROID_SUPPORTED - bool - default y - config SOC_USB_OTG_SUPPORTED bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index bf0a452094..8f5c5119d3 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -38,7 +38,6 @@ #define SOC_ULP_SUPPORTED 1 #define SOC_RISCV_COPROC_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_BLUEDROID_SUPPORTED 1 #define SOC_USB_OTG_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 #define SOC_CCOMP_TIMER_SUPPORTED 1