diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c
index c1fc22e6b2..4d98082872 100644
--- a/components/esp_system/port/soc/esp32p4/clk.c
+++ b/components/esp_system/port/soc/esp32p4/clk.c
@@ -54,6 +54,7 @@
 #include "hal/usb_serial_jtag_ll.h"
 #include "hal/usb_utmi_ll.h"
 #include "hal/wdt_hal.h"
+#include "hal/bitscrambler_ll.h"
 
 #include "esp_private/esp_modem_clock.h"
 #include "esp_private/esp_sleep_internal.h"
@@ -253,9 +254,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         _pau_ll_enable_bus_clock(false);
         _parlio_ll_enable_bus_clock(0, false);
         _etm_ll_enable_bus_clock(0, false);
-        REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN);
-        REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN);
-        REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN);
+        _bitscrambler_ll_set_bus_clock_sys_enable(false);
+        _bitscrambler_ll_set_bus_clock_rx_enable(false);
+        _bitscrambler_ll_set_bus_clock_tx_enable(false);
 
 // Non-Console UART
 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt
index 97011039f1..698bd8adff 100644
--- a/components/hal/CMakeLists.txt
+++ b/components/hal/CMakeLists.txt
@@ -30,11 +30,6 @@ if(CONFIG_SOC_KEY_MANAGER_SUPPORTED)
     list(APPEND srcs "huk_hal.c")
 endif()
 
-if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED)
-    list(APPEND srcs "${target}/bitscrambler_periph.c")
-endif()
-
-
 if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
     if(CONFIG_SOC_MMU_PERIPH_NUM)
         list(APPEND srcs "mmu_hal.c")
diff --git a/components/hal/esp32p4/bitscrambler_periph.c b/components/hal/esp32p4/bitscrambler_periph.c
deleted file mode 100644
index 5dd3c9900b..0000000000
--- a/components/hal/esp32p4/bitscrambler_periph.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "hal/bitscrambler_hal.h"
-
-const bitscrambler_regs_t bitscramblers_reg[2]={
-	{ //BITSCRAMBLER_DIR_TX
-		.inst_cfg0=&BITSCRAMBLER.tx_inst_cfg0,
-		.inst_cfg1=&BITSCRAMBLER.tx_inst_cfg1,
-		.lut_cfg0=&BITSCRAMBLER.tx_lut_cfg0,
-		.lut_cfg1=&BITSCRAMBLER.tx_lut_cfg1,
-		.trailing_bits=&BITSCRAMBLER.tx_tailing_bits,
-		.ctrl=&BITSCRAMBLER.tx_ctrl,
-		.state=&BITSCRAMBLER.tx_state,
-	},
-	{ //BITSCRAMBLER_DIR_RX
-	  //Note that this assumes the RX and TX registers are exactly the same. If there's
-	  //ever a chip where this is not the case, we need to rework this.
-		.inst_cfg0=(bitscrambler_tx_inst_cfg0_reg_t*)&BITSCRAMBLER.rx_inst_cfg0,
-		.inst_cfg1=(bitscrambler_tx_inst_cfg1_reg_t*)&BITSCRAMBLER.rx_inst_cfg1,
-		.lut_cfg0=(bitscrambler_tx_lut_cfg0_reg_t*)&BITSCRAMBLER.rx_lut_cfg0,
-		.lut_cfg1=(bitscrambler_tx_lut_cfg1_reg_t*)&BITSCRAMBLER.rx_lut_cfg1,
-		.trailing_bits=(bitscrambler_tx_tailing_bits_reg_t*)&BITSCRAMBLER.rx_tailing_bits,
-		.ctrl=(bitscrambler_tx_ctrl_reg_t*)&BITSCRAMBLER.rx_ctrl,
-		.state=(bitscrambler_tx_state_reg_t*)&BITSCRAMBLER.rx_state,
-	}
-};
diff --git a/components/hal/esp32p4/include/hal/bitscrambler_ll.h b/components/hal/esp32p4/include/hal/bitscrambler_ll.h
index e43bd2b3ae..33c6276c9e 100644
--- a/components/hal/esp32p4/include/hal/bitscrambler_ll.h
+++ b/components/hal/esp32p4/include/hal/bitscrambler_ll.h
@@ -12,11 +12,8 @@
 #include <stdbool.h>
 #include "soc/bitscrambler_struct.h"
 #include "hal/bitscrambler_types.h"
-#include "hal/bitscrambler_hal.h"
-#include "hal/misc.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/hp_system_struct.h"
-#include "hal/hal_utils.h"
 #include "hal/misc.h"
 
 #ifdef __cplusplus
@@ -25,20 +22,12 @@ extern "C" {
 
 #define BITSCRAMBLER_LL_GET_HW(num)      (((num) == 0) ? (&BITSCRAMBLER) : NULL)
 
-//Note: Most of the register operations refer tx_something fields. Because they
-//are done to bitscramblers_reg[dir] members and rx register fields are the
-//same, this code works for RX as well.
-
-//Note: This code entirely ignores the 'hw' argument, which is fine, as for now
-//we only have one BitScrambler peripheral. If we have a chip that has more, we
-//need to do something to use hw to select one of multiple bitscramblers_reg
-//versions.
-
 /**
  * @brief Select peripheral BitScrambler is attached to
  *
  * @param hw BitScrambler hardware instance address.
  * @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
+ * @param peri Peripheral to select, should pick the value from soc/bitscrambler_peri_select.h
  */
 static inline void bitscrambler_ll_select_peripheral(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int peri)
 {
@@ -57,7 +46,7 @@ static inline void bitscrambler_ll_select_peripheral(bitscrambler_dev_t *hw, bit
  */
 static inline void bitscrambler_ll_enable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
 {
-    bitscramblers_reg[dir].ctrl->tx_ena=1;
+    hw->ctrl[dir].ena = 1;
 }
 
 /**
@@ -68,7 +57,7 @@ static inline void bitscrambler_ll_enable(bitscrambler_dev_t *hw, bitscrambler_d
  */
 static inline void bitscrambler_ll_disable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
 {
-    bitscramblers_reg[dir].ctrl->tx_ena=0;
+    hw->ctrl[dir].ena = 0;
 }
 
 
@@ -83,9 +72,9 @@ static inline void bitscrambler_ll_disable(bitscrambler_dev_t *hw, bitscrambler_
  */
 static inline void bitscrambler_ll_instmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx, uint32_t data)
 {
-    bitscramblers_reg[dir].inst_cfg0->tx_inst_idx=inst_idx;
-    bitscramblers_reg[dir].inst_cfg0->tx_inst_pos=word_idx;
-    bitscramblers_reg[dir].inst_cfg1->tx_inst=data;
+    hw->inst_cfg[dir].cfg0.inst_idx = inst_idx;
+    hw->inst_cfg[dir].cfg0.inst_pos = word_idx;
+    hw->inst_cfg[dir].cfg1.inst = data;
 }
 
 /**
@@ -100,9 +89,9 @@ static inline void bitscrambler_ll_instmem_write(bitscrambler_dev_t *hw, bitscra
  */
 static inline uint32_t bitscrambler_ll_instmem_read(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx)
 {
-    bitscramblers_reg[dir].inst_cfg0->tx_inst_idx=inst_idx;
-    bitscramblers_reg[dir].inst_cfg0->tx_inst_pos=word_idx;
-    return bitscramblers_reg[dir].inst_cfg1->tx_inst;
+    hw->inst_cfg[dir].cfg0.inst_idx = inst_idx;
+    hw->inst_cfg[dir].cfg0.inst_pos = word_idx;
+    return hw->inst_cfg[dir].cfg1.inst;
 }
 
 /**
@@ -113,9 +102,10 @@ static inline uint32_t bitscrambler_ll_instmem_read(bitscrambler_dev_t *hw, bits
  * @param word_idx Word within the LUT to write to
  * @param data Data to write
  */
-static inline void bitscrambler_ll_lutmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int word_idx, uint32_t data) {
-    bitscramblers_reg[dir].lut_cfg0->tx_lut_idx=word_idx;
-    bitscramblers_reg[dir].lut_cfg1->tx_lut=data;
+static inline void bitscrambler_ll_lutmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int word_idx, uint32_t data)
+{
+    hw->lut_cfg[dir].cfg0.lut_idx = word_idx;
+    hw->lut_cfg[dir].cfg1.lut = data;
 }
 
 /**
@@ -127,7 +117,7 @@ static inline void bitscrambler_ll_lutmem_write(bitscrambler_dev_t *hw, bitscram
  */
 static inline void bitscrambler_ll_set_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_lut_width_t width)
 {
-    bitscramblers_reg[dir].lut_cfg0->tx_lut_mode=width;
+    hw->lut_cfg[dir].cfg0.lut_mode = width;
 }
 
 /**
@@ -138,7 +128,7 @@ static inline void bitscrambler_ll_set_lut_width(bitscrambler_dev_t *hw, bitscra
  */
 static inline int bitscrambler_ll_get_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
 {
-    return bitscramblers_reg[dir].lut_cfg0->tx_lut_mode;
+    return hw->lut_cfg[dir].cfg0.lut_mode;
 }
 
 /**
@@ -150,7 +140,7 @@ static inline int bitscrambler_ll_get_lut_width(bitscrambler_dev_t *hw, bitscram
  */
 static inline void bitscrambler_ll_enable_loopback(bitscrambler_dev_t *hw, bool en)
 {
-    hw->sys.loop_mode=en?1:0;
+    hw->sys.loop_mode = en ? 1 : 0;
 }
 
 /**
@@ -162,7 +152,7 @@ static inline void bitscrambler_ll_enable_loopback(bitscrambler_dev_t *hw, bool
  */
 static inline void bitscrambler_ll_set_cond_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_cond_mode_t mode)
 {
-    bitscramblers_reg[dir].ctrl->tx_cond_mode=mode;
+    hw->ctrl[dir].cond_mode = mode;
 }
 
 /**
@@ -174,7 +164,7 @@ static inline void bitscrambler_ll_set_cond_mode(bitscrambler_dev_t *hw, bitscra
  */
 static inline void bitscrambler_ll_set_prefetch_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_prefetch_mode_t mode)
 {
-    bitscramblers_reg[dir].ctrl->tx_fetch_mode=mode;
+    hw->ctrl[dir].fetch_mode = mode;
 }
 
 /**
@@ -186,7 +176,7 @@ static inline void bitscrambler_ll_set_prefetch_mode(bitscrambler_dev_t *hw, bit
  */
 static inline void bitscrambler_ll_set_eof_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_eof_mode_t mode)
 {
-    bitscramblers_reg[dir].ctrl->tx_eof_mode=mode;
+    hw->ctrl[dir].eof_mode = mode;
 }
 
 /**
@@ -198,7 +188,7 @@ static inline void bitscrambler_ll_set_eof_mode(bitscrambler_dev_t *hw, bitscram
  */
 static inline void bitscrambler_ll_set_dummy_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_dummy_mode_t mode)
 {
-    bitscramblers_reg[dir].ctrl->tx_rd_dummy=mode;
+    hw->ctrl[dir].rd_dummy = mode;
 }
 
 /**
@@ -210,7 +200,7 @@ static inline void bitscrambler_ll_set_dummy_mode(bitscrambler_dev_t *hw, bitscr
  */
 static inline void bitscrambler_ll_set_halt_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_halt_mode_t mode)
 {
-    bitscramblers_reg[dir].ctrl->tx_halt_mode=mode;
+    hw->ctrl[dir].halt_mode = mode;
 }
 
 /**
@@ -222,7 +212,7 @@ static inline void bitscrambler_ll_set_halt_mode(bitscrambler_dev_t *hw, bitscra
  */
 static inline void bitscrambler_ll_set_tailing_bits(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int bitcount)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD((*bitscramblers_reg[dir].trailing_bits), tx_tailing_bits, bitcount);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tailing_bits[dir], tailing_bits, bitcount);
 }
 
 /**
@@ -233,8 +223,8 @@ static inline void bitscrambler_ll_set_tailing_bits(bitscrambler_dev_t *hw, bits
  */
 static inline void bitscrambler_ll_reset_fifo(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
 {
-    bitscramblers_reg[dir].ctrl->tx_fifo_rst=1;
-    bitscramblers_reg[dir].ctrl->tx_fifo_rst=0;
+    hw->ctrl[dir].fifo_rst = 1;
+    hw->ctrl[dir].fifo_rst = 0;
 }
 
 /**
@@ -245,8 +235,8 @@ static inline void bitscrambler_ll_reset_fifo(bitscrambler_dev_t *hw, bitscrambl
  */
 static inline void bitscrambler_ll_clear_eof_trace(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
 {
-    bitscramblers_reg[dir].state->tx_eof_trace_clr=1;
-    bitscramblers_reg[dir].state->tx_eof_trace_clr=0;
+    hw->state[dir].eof_trace_clr = 1;
+    hw->state[dir].eof_trace_clr = 0;
 }
 
 /**
@@ -258,8 +248,8 @@ static inline void bitscrambler_ll_clear_eof_trace(bitscrambler_dev_t *hw, bitsc
  */
 static inline void bitscrambler_ll_set_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_set_state_t state)
 {
-    bitscramblers_reg[dir].ctrl->tx_pause=(state==BITSCRAMBLER_SET_STATE_PAUSE)?1:0;
-    bitscramblers_reg[dir].ctrl->tx_halt=(state==BITSCRAMBLER_SET_STATE_HALT)?1:0;
+    hw->ctrl[dir].pause = (state == BITSCRAMBLER_SET_STATE_PAUSE) ? 1 : 0;
+    hw->ctrl[dir].halt = (state == BITSCRAMBLER_SET_STATE_HALT) ? 1 : 0;
 }
 
 /**
@@ -272,10 +262,18 @@ static inline void bitscrambler_ll_set_state(bitscrambler_dev_t *hw, bitscramble
  */
 static inline bitscrambler_state_t bitscrambler_ll_current_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
 {
-    if (bitscramblers_reg[dir].state->tx_in_idle) return BITSCRAMBLER_STATE_IDLE;
-    if (bitscramblers_reg[dir].state->tx_in_run) return BITSCRAMBLER_STATE_RUN;
-    if (bitscramblers_reg[dir].state->tx_in_wait) return BITSCRAMBLER_STATE_WAIT;
-    if (bitscramblers_reg[dir].state->tx_in_pause) return BITSCRAMBLER_STATE_PAUSED;
+    if (hw->state[dir].in_idle) {
+        return BITSCRAMBLER_STATE_IDLE;
+    }
+    if (hw->state[dir].in_run) {
+        return BITSCRAMBLER_STATE_RUN;
+    }
+    if (hw->state[dir].in_wait) {
+        return BITSCRAMBLER_STATE_WAIT;
+    }
+    if (hw->state[dir].in_pause) {
+        return BITSCRAMBLER_STATE_PAUSED;
+    }
     return BITSCRAMBLER_STATE_UNKNOWN;
 }
 
diff --git a/components/hal/include/hal/bitscrambler_hal.h b/components/hal/include/hal/bitscrambler_hal.h
index 1d96d61287..d0459ee550 100644
--- a/components/hal/include/hal/bitscrambler_hal.h
+++ b/components/hal/include/hal/bitscrambler_hal.h
@@ -6,35 +6,10 @@
 
 #pragma once
 
-#include "sdkconfig.h"
-
-#if CONFIG_SOC_BITSCRAMBLER_SUPPORTED
-#include "soc/bitscrambler_struct.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-
-/*
- * @brief The TX and RX BitScramblers have registers that work in the same way, but that are
- * in different locations. This struct defines those registers; if we address the TX and
- * RX bitscramblers through this we can mostly use the same code for both.
- */
-typedef struct {
-	volatile bitscrambler_tx_inst_cfg0_reg_t *inst_cfg0;
-	volatile bitscrambler_tx_inst_cfg1_reg_t *inst_cfg1;
-	volatile bitscrambler_tx_lut_cfg0_reg_t *lut_cfg0;
-	volatile bitscrambler_tx_lut_cfg1_reg_t *lut_cfg1;
-	volatile bitscrambler_tx_tailing_bits_reg_t *trailing_bits;
-	volatile bitscrambler_tx_ctrl_reg_t *ctrl;
-	volatile bitscrambler_tx_state_reg_t *state;
-} bitscrambler_regs_t;
-
-extern const bitscrambler_regs_t bitscramblers_reg[2];
-
 #ifdef __cplusplus
 }
 #endif
-
-#endif
diff --git a/components/hal/include/hal/bitscrambler_types.h b/components/hal/include/hal/bitscrambler_types.h
index f726859eb3..25f0f8421b 100644
--- a/components/hal/include/hal/bitscrambler_types.h
+++ b/components/hal/include/hal/bitscrambler_types.h
@@ -19,85 +19,75 @@ typedef enum {
 } bitscrambler_direction_t;
 
 /**
- * @brief BitScrambler LUT width
+ * @brief BitScrambler LUT (look up table) width
  */
 typedef enum {
-    BITSCRAMBLER_LUT_WIDTH_8BIT = 0,
-    BITSCRAMBLER_LUT_WIDTH_16BIT = 1,
-    BITSCRAMBLER_LUT_WIDTH_32BIT = 2
+    BITSCRAMBLER_LUT_WIDTH_8BIT = 0,  /*!< 8-bit LUT */
+    BITSCRAMBLER_LUT_WIDTH_16BIT = 1, /*!< 16-bit LUT */
+    BITSCRAMBLER_LUT_WIDTH_32BIT = 2, /*!< 32-bit LUT */
 } bitscrambler_lut_width_t;
 
 
 /**
- * @brief BitScrambler loopback select
+ * @brief EOF signal generating mode of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_LOOP_DISABLE = 0,
-    BITSCRAMBLER_LOOP_ENABLE = 1
-} bitscrambler_loop_mode_t;
-
-
-/**
- * @brief EOF mode of bitscrambler
- */
-typedef enum {
-    BITSCRAMBLER_EOF_MODE_READ = 0,
-    BITSCRAMBLER_EOF_MODE_WRITE = 1
+    BITSCRAMBLER_EOF_MODE_READ = 0,  /*!< EOF is counted by reading the source FIFO */
+    BITSCRAMBLER_EOF_MODE_WRITE = 1, /*!< EOF is counted by writing the destination FIFO */
 } bitscrambler_eof_mode_t;
 
 /**
  * @brief Condition mode of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_COND_MODE_LESSTHAN = 0,
-    BITSCRAMBLER_COND_MODE_NOTEQUAL = 1
+    BITSCRAMBLER_COND_MODE_LESSTHAN = 0, /*!< Use "<=" to generate the condition */
+    BITSCRAMBLER_COND_MODE_NOTEQUAL = 1, /*!< Use "!=" to generate the condition */
 } bitscrambler_cond_mode_t;
 
 /**
- * @brief Condition mode of bitscrambler
+ * @brief Prefetch mode of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_PREFETCH_ENABLED = 0,
-    BITSCRAMBLER_PREFETCH_DISABLED = 1
+    BITSCRAMBLER_PREFETCH_ENABLED = 0,  /*!< Hardware prefetch is enabled */
+    BITSCRAMBLER_PREFETCH_DISABLED = 1, /*!< Hardware prefetch is disabled, but the bitscrambler instructions can still do the prefetch */
 } bitscrambler_prefetch_mode_t;
 
 /**
- * @brief Condition mode of bitscrambler
+ * @brief Halt mode of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_HALT_WAIT_WRITES = 0,
-    BITSCRAMBLER_HALT_IGNORE_WRITES = 1
+    BITSCRAMBLER_HALT_WAIT_WRITES = 0,   /*!< Wait data write back */
+    BITSCRAMBLER_HALT_IGNORE_WRITES = 1, /*!< Ignore write data back */
 } bitscrambler_halt_mode_t;
 
 /**
- * @brief Condition mode of bitscrambler
+ * @brief Dummy mode of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_DUMMY_MODE_HALT = 0,
-    BITSCRAMBLER_DUMMY_MODE_DUMMY = 1
+    BITSCRAMBLER_DUMMY_MODE_HALT = 0,  /*!< Halt and wait the read data */
+    BITSCRAMBLER_DUMMY_MODE_DUMMY = 1, /*!< Ignore the read data */
 } bitscrambler_dummy_mode_t;
 
 /**
- * @brief Condition mode of bitscrambler
+ * @brief Commands to set the state of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_SET_STATE_RUN,
-    BITSCRAMBLER_SET_STATE_HALT,
-    BITSCRAMBLER_SET_STATE_PAUSE
+    BITSCRAMBLER_SET_STATE_RUN,   /*!< Run */
+    BITSCRAMBLER_SET_STATE_HALT,  /*!< Halt */
+    BITSCRAMBLER_SET_STATE_PAUSE, /*!< Pause */
 } bitscrambler_set_state_t;
 
 /**
  * @brief Status of bitscrambler
  */
 typedef enum {
-    BITSCRAMBLER_STATE_IDLE,
-    BITSCRAMBLER_STATE_RUN,
-    BITSCRAMBLER_STATE_WAIT,
-    BITSCRAMBLER_STATE_PAUSED,
+    BITSCRAMBLER_STATE_IDLE,   /*!< Idle (halt) */
+    BITSCRAMBLER_STATE_RUN,    /*!< Running */
+    BITSCRAMBLER_STATE_WAIT,   /*!< Waiting data write back */
+    BITSCRAMBLER_STATE_PAUSED, /*!< Paused */
     BITSCRAMBLER_STATE_UNKNOWN /*!< Invalid, should never be returned */
 } bitscrambler_state_t;
 
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32p4/register/soc/bitscrambler_struct.h b/components/soc/esp32p4/register/soc/bitscrambler_struct.h
index ef0b5f23ac..aeb4fee033 100644
--- a/components/soc/esp32p4/register/soc/bitscrambler_struct.h
+++ b/components/soc/esp32p4/register/soc/bitscrambler_struct.h
@@ -405,22 +405,197 @@ typedef union {
     uint32_t val;
 } bitscrambler_version_reg_t;
 
+///////////////////// TX and RX registers are exactly the same //////////////////////////////////
+// The following registers are used for both TX and RX, so we can use the same struct for both //
+/////////////////////////////////////////////////////////////////////////////////////////////////
+
+/** Type of inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t inst_idx:3;
+        /** inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_inst_cfg0_reg_t;
+
+/** Type of inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction, Read this bits to get instruction.
+         */
+        uint32_t inst:32;
+    };
+    uint32_t val;
+} bitscrambler_inst_cfg1_reg_t;
+
+/** Type of lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on lut_mode
+         */
+        uint32_t lut_idx:11;
+        /** lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_lut_cfg0_reg_t;
+
+/** Type of lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT, Read this bits to get LUT
+         */
+        uint32_t lut:32;
+    };
+    uint32_t val;
+} bitscrambler_lut_cfg1_reg_t;
+
+/** Type of tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tailing_bits_reg_t;
+
+/** Type of ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t ena:1;
+        /** pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t pause:1;
+        /** halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t halt:1;
+        /** eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t eof_mode:1;
+        /** cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t cond_mode:1;
+        /** fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t fetch_mode:1;
+        /** halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t halt_mode:1;
+        /** rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rd_dummy:1;
+        /** fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_ctrl_reg_t;
+
+/** Group: Status registers */
+/** Type of state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t in_idle:1;
+        /** in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t in_run:1;
+        /** in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t in_wait:1;
+        /** in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t in_pause:1;
+        /** fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t eof_get_cnt:14;
+        /** eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t eof_overload:1;
+        /** eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_eof_overload and
+         *  reg_bitscrambler_eof_get_cnt registers
+         */
+        uint32_t eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_state_reg_t;
 
 typedef struct {
-    volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
-    volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
-    volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
-    volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
-    volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
-    volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
-    volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
-    volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
-    volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
-    volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
-    volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
-    volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
-    volatile bitscrambler_tx_state_reg_t tx_state;
-    volatile bitscrambler_rx_state_reg_t rx_state;
+    volatile struct {
+        bitscrambler_inst_cfg0_reg_t cfg0;
+        bitscrambler_inst_cfg1_reg_t cfg1;
+    } inst_cfg[2];
+    volatile struct {
+        bitscrambler_lut_cfg0_reg_t cfg0;
+        bitscrambler_lut_cfg1_reg_t cfg1;
+    } lut_cfg[2];
+    volatile bitscrambler_tailing_bits_reg_t tailing_bits[2];
+    volatile bitscrambler_ctrl_reg_t ctrl[2];
+    volatile bitscrambler_state_reg_t state[2];
     uint32_t reserved_038[48];
     volatile bitscrambler_sys_reg_t sys;
     volatile bitscrambler_version_reg_t version;