From 626fb5d426a6ea16bb59b508cfe6bffecf7ea9df Mon Sep 17 00:00:00 2001
From: jiangguangming <jiangguangming@espressif.com>
Date: Mon, 26 Dec 2022 16:51:31 +0800
Subject: [PATCH 1/3] esp_rom: update H4/H2/C2/C6 rom rtc.h

---
 components/esp_rom/include/esp32c2/rom/rtc.h | 31 -----------
 components/esp_rom/include/esp32c6/rom/rtc.h | 53 ++++++++-----------
 components/esp_rom/include/esp32h2/rom/rtc.h | 53 ++++++++-----------
 components/esp_rom/include/esp32h4/rom/rtc.h | 55 ++++++++------------
 4 files changed, 63 insertions(+), 129 deletions(-)

diff --git a/components/esp_rom/include/esp32c2/rom/rtc.h b/components/esp_rom/include/esp32c2/rom/rtc.h
index 910792a29a..fb7008c251 100644
--- a/components/esp_rom/include/esp32c2/rom/rtc.h
+++ b/components/esp_rom/include/esp32c2/rom/rtc.h
@@ -161,17 +161,6 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
-/**
-  * @brief Get CRC for Fast RTC Memory.
-  *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
-  *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
-  *
-  * @return uint32_t : CRC32 result
-  */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
-
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
   * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
@@ -190,26 +179,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *
diff --git a/components/esp_rom/include/esp32c6/rom/rtc.h b/components/esp_rom/include/esp32c6/rom/rtc.h
index e5e5a44553..844f010147 100644
--- a/components/esp_rom/include/esp32c6/rom/rtc.h
+++ b/components/esp_rom/include/esp32c6/rom/rtc.h
@@ -4,10 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ROM_RTC_H_
-#define _ROM_RTC_H_
-
-#include "ets_sys.h"
+#pragma once
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -67,7 +64,6 @@ extern "C" {
 
 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 
-
 typedef enum {
     AWAKE = 0,             //<CPU ON
     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
@@ -172,16 +168,31 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
+typedef void (* esp_rom_wake_func_t)(void);
+
 /**
-  * @brief Get CRC for Fast RTC Memory.
+  * @brief Read stored RTC wake function address
   *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
   *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  * @param  None
   *
-  * @return uint32_t : CRC32 result
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
   */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
+/**
+  * @brief Store new RTC wake function address
+  *
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
+  *
+  * @param entry_addr Address of function. If NULL, length is ignored and all registers are cleared to 0.
+  * @param length of function in RTC fast memory. cannot be larger than RTC Fast memory size.
+  *
+  * @return None
+  */
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
 
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
@@ -201,26 +212,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(LP_AON_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *
@@ -252,5 +243,3 @@ void software_reset_cpu(int cpu_no);
 #ifdef __cplusplus
 }
 #endif
-
-#endif /* _ROM_RTC_H_ */
diff --git a/components/esp_rom/include/esp32h2/rom/rtc.h b/components/esp_rom/include/esp32h2/rom/rtc.h
index 5ab500420a..4bfa6b7533 100644
--- a/components/esp_rom/include/esp32h2/rom/rtc.h
+++ b/components/esp_rom/include/esp32h2/rom/rtc.h
@@ -4,10 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ROM_RTC_H_
-#define _ROM_RTC_H_
-
-#include "ets_sys.h"
+#pragma once
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -67,7 +64,6 @@ extern "C" {
 
 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 
-
 typedef enum {
     AWAKE = 0,             //<CPU ON
     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
@@ -173,16 +169,31 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
+typedef void (* esp_rom_wake_func_t)(void);
+
 /**
-  * @brief Get CRC for Fast RTC Memory.
+  * @brief Read stored RTC wake function address
   *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
   *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  * @param  None
   *
-  * @return uint32_t : CRC32 result
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
   */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
+/**
+  * @brief Store new RTC wake function address
+  *
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
+  *
+  * @param entry_addr Address of function. If NULL, length is ignored and all registers are cleared to 0.
+  * @param length of function in RTC fast memory. cannot be larger than RTC Fast memory size.
+  *
+  * @return None
+  */
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
 
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
@@ -202,26 +213,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(LP_AON_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *
@@ -253,5 +244,3 @@ void software_reset_cpu(int cpu_no);
 #ifdef __cplusplus
 }
 #endif
-
-#endif /* _ROM_RTC_H_ */
diff --git a/components/esp_rom/include/esp32h4/rom/rtc.h b/components/esp_rom/include/esp32h4/rom/rtc.h
index 2629fd9a6d..8499f1b052 100644
--- a/components/esp_rom/include/esp32h4/rom/rtc.h
+++ b/components/esp_rom/include/esp32h4/rom/rtc.h
@@ -4,16 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ROM_RTC_H_
-#define _ROM_RTC_H_
-
-#include "ets_sys.h"
+#pragma once
 
 #include <stdbool.h>
 #include <stdint.h>
 #include "esp_assert.h"
-
-#include "soc/soc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/reset_reasons.h"
 
@@ -67,7 +62,6 @@ extern "C" {
 
 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 
-
 typedef enum {
     AWAKE = 0,             //<CPU ON
     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
@@ -175,16 +169,31 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
+typedef void (* esp_rom_wake_func_t)(void);
+
 /**
-  * @brief Get CRC for Fast RTC Memory.
+  * @brief Read stored RTC wake function address
   *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
   *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  * @param  None
   *
-  * @return uint32_t : CRC32 result
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
   */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
+/**
+  * @brief Store new RTC wake function address
+  *
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
+  *
+  * @param entry_addr Address of function. If NULL, length is ignored and all registers are cleared to 0.
+  * @param length of function in RTC fast memory. cannot be larger than RTC Fast memory size.
+  *
+  * @return None
+  */
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
 
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
@@ -204,26 +213,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *
@@ -255,5 +244,3 @@ void software_reset_cpu(int cpu_no);
 #ifdef __cplusplus
 }
 #endif
-
-#endif /* _ROM_RTC_H_ */

From 42144a7e4571bb4329b0447874b2a63a800f7196 Mon Sep 17 00:00:00 2001
From: jiangguangming <jiangguangming@espressif.com>
Date: Mon, 26 Dec 2022 16:58:47 +0800
Subject: [PATCH 2/3] soc: H4/H2/C6 support
 SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY

---
 components/soc/esp32c6/include/soc/Kconfig.soc_caps.in | 4 ++++
 components/soc/esp32c6/include/soc/soc_caps.h          | 2 ++
 components/soc/esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++++
 components/soc/esp32h2/include/soc/soc_caps.h          | 2 ++
 components/soc/esp32h4/include/soc/Kconfig.soc_caps.in | 4 ++++
 components/soc/esp32h4/include/soc/soc_caps.h          | 2 ++
 components/soc/esp32s3/include/soc/Kconfig.soc_caps.in | 8 ++++----
 components/soc/esp32s3/include/soc/soc_caps.h          | 2 +-
 8 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 085a860374..042dde1a75 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -927,6 +927,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
+    bool
+    default y
+
 config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
     default y
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 4b78381fb4..8365b2bbe7 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -427,6 +427,8 @@
 #define SOC_PM_SUPPORT_RC32K_PD         (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 
+#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
+
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
 #define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index e4df424186..f2da2b1da7 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -755,6 +755,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index 40c064e800..b11d36576d 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -409,6 +409,8 @@
 #define SOC_PM_SUPPORT_BT_PD            (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 
+#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
+
 // TODO: IDF-6229 (Copy from esp32c6, need check)
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index efec18599b..d75ccacf85 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -771,6 +771,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index 1a745d54b0..ee6e50553b 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -367,6 +367,8 @@
 #define SOC_PM_SUPPORT_BT_PD            (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 
+#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)
diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
index 7a108d03ca..2a0312203e 100644
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@@ -959,10 +959,6 @@ config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
     bool
     default y
 
-config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
-    bool
-    default y
-
 config SOC_PM_SUPPORT_CPU_PD
     bool
     default y
@@ -979,6 +975,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
+    bool
+    default y
+
 config SOC_CLK_RC_FAST_D256_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index 0ae868a7f5..305d57f4e0 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -399,13 +399,13 @@
 #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
 #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
 #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP    (1)     /*!<Supports waking up from touch pad trigger */
-#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1)
 
 #define SOC_PM_SUPPORT_CPU_PD           (1)
 #define SOC_PM_SUPPORT_TAGMEM_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 
+#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
 /*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */
 #define SOC_CLK_RC_FAST_D256_SUPPORTED            (1)

From fe2984a52dd7a86188d37eea919df80f867ff023 Mon Sep 17 00:00:00 2001
From: jiangguangming <jiangguangming@espressif.com>
Date: Mon, 26 Dec 2022 18:00:51 +0800
Subject: [PATCH 3/3] esp_hw_support: support riscv call

---
 components/esp_hw_support/sleep_modes.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 067ef09a91..465965e267 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -222,9 +222,15 @@ static void __attribute__((section(".rtc.entry.text"))) esp_wake_stub_entry(void
 {
 #define _SYM2STR(s) # s
 #define SYM2STR(s)  _SYM2STR(s)
+
+#ifdef __riscv
+    __asm__ __volatile__ ("call " SYM2STR(esp_wake_stub_start) "\n");
+#else
     // call4 has a larger effective addressing range (-524284 to 524288 bytes),
     // which is sufficient for instruction addressing in RTC fast memory.
     __asm__ __volatile__ ("call4 " SYM2STR(esp_wake_stub_start) "\n");
+#endif
+
 }
 #endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY