From 5fef81609a1aa5b0e3439bd1a9fb663c96c2f967 Mon Sep 17 00:00:00 2001 From: wanlei Date: Fri, 1 Mar 2024 11:32:50 +0800 Subject: [PATCH] feat(esp32c61): add soc peripheral header files (1/2) --- .../soc/esp32c61/include/soc/apb_saradc_reg.h | 884 +++ .../esp32c61/include/soc/apb_saradc_struct.h | 757 ++ .../soc/esp32c61/include/soc/cache_reg.h | 6166 +++++++++++++++++ .../soc/esp32c61/include/soc/cache_struct.h | 5761 +++++++++++++++ .../soc/esp32c61/include/soc/efuse_reg.h | 3949 +++++++++++ .../soc/esp32c61/include/soc/efuse_struct.h | 3368 +++++++++ .../soc/esp32c61/include/soc/gdma_reg.h | 2371 +++++++ .../soc/esp32c61/include/soc/gdma_struct.h | 1281 ++++ .../soc/esp32c61/include/soc/gpio_ext_reg.h | 964 +++ .../esp32c61/include/soc/gpio_ext_struct.h | 693 ++ .../soc/esp32c61/include/soc/gpio_reg.h | 5688 +++++++++++++++ .../soc/esp32c61/include/soc/gpio_sig_map.h | 178 + .../soc/esp32c61/include/soc/gpio_struct.h | 1259 ++++ .../soc/esp32c61/include/soc/hp_system_reg.h | 441 ++ .../esp32c61/include/soc/hp_system_struct.h | 489 ++ components/soc/esp32c61/include/soc/i2c_reg.h | 1518 ++++ .../soc/esp32c61/include/soc/i2c_struct.h | 1115 +++ components/soc/esp32c61/include/soc/i2s_reg.h | 1275 ++++ .../soc/esp32c61/include/soc/i2s_struct.h | 1010 +++ .../include/soc/interrupt_matrix_reg.h | 814 +++ .../include/soc/interrupt_matrix_struct.h | 1023 +++ .../soc/esp32c61/include/soc/interrupts.h | 88 + .../soc/esp32c61/include/soc/intpri_reg.h | 131 + .../soc/esp32c61/include/soc/intpri_struct.h | 127 + .../soc/esp32c61/include/soc/io_mux_reg.h | 275 + .../soc/esp32c61/include/soc/io_mux_struct.h | 145 + .../soc/esp32c61/include/soc/ledc_reg.h | 2370 +++++++ .../soc/esp32c61/include/soc/ledc_struct.h | 1063 +++ .../esp32c61/include/soc/mem_monitor_reg.h | 345 + .../esp32c61/include/soc/mem_monitor_struct.h | 368 + components/soc/esp32c61/include/soc/pcr_reg.h | 2245 ++++++ .../soc/esp32c61/include/soc/pcr_struct.h | 2052 ++++++ .../esp32c61/include/soc/pmu_icg_mapping.h | 67 + .../soc/esp32c61/include/soc/reg_base.h | 60 + .../soc/esp32c61/include/soc/soc_etm_reg.h | 6146 ++++++++++++++++ .../soc/esp32c61/include/soc/soc_etm_source.h | 253 + .../soc/esp32c61/include/soc/soc_etm_struct.h | 3301 +++++++++ .../soc/esp32c61/include/soc/spi1_mem_reg.h | 1514 ++++ .../esp32c61/include/soc/spi1_mem_struct.h | 1282 ++++ .../soc/esp32c61/include/soc/spi_mem_reg.h | 3907 +++++++++++ .../soc/esp32c61/include/soc/spi_mem_struct.h | 2922 ++++++++ components/soc/esp32c61/include/soc/spi_reg.h | 2336 +++++++ .../soc/esp32c61/include/soc/spi_struct.h | 1625 +++++ .../soc/esp32c61/include/soc/sys_timer_reg.h | 680 ++ .../esp32c61/include/soc/sys_timer_struct.h | 729 ++ .../esp32c61/include/soc/timer_group_reg.h | 753 ++ .../esp32c61/include/soc/timer_group_struct.h | 740 ++ .../soc/esp32c61/include/soc/uart_reg.h | 1657 +++++ .../soc/esp32c61/include/soc/uart_struct.h | 1350 ++++ .../include/soc/usb_serial_jtag_reg.h | 1228 ++++ .../include/soc/usb_serial_jtag_struct.h | 980 +++ components/soc/esp32c61/interrupts.c | 72 + .../soc/esp32c61/ld/esp32c61.peripherals.ld | 58 + 53 files changed, 81873 insertions(+) create mode 100644 components/soc/esp32c61/include/soc/apb_saradc_reg.h create mode 100644 components/soc/esp32c61/include/soc/apb_saradc_struct.h create mode 100644 components/soc/esp32c61/include/soc/cache_reg.h create mode 100644 components/soc/esp32c61/include/soc/cache_struct.h create mode 100644 components/soc/esp32c61/include/soc/efuse_reg.h create mode 100644 components/soc/esp32c61/include/soc/efuse_struct.h create mode 100644 components/soc/esp32c61/include/soc/gdma_reg.h create mode 100644 components/soc/esp32c61/include/soc/gdma_struct.h create mode 100644 components/soc/esp32c61/include/soc/gpio_ext_reg.h create mode 100644 components/soc/esp32c61/include/soc/gpio_ext_struct.h create mode 100644 components/soc/esp32c61/include/soc/gpio_reg.h create mode 100644 components/soc/esp32c61/include/soc/gpio_sig_map.h create mode 100644 components/soc/esp32c61/include/soc/gpio_struct.h create mode 100644 components/soc/esp32c61/include/soc/hp_system_reg.h create mode 100644 components/soc/esp32c61/include/soc/hp_system_struct.h create mode 100644 components/soc/esp32c61/include/soc/i2c_reg.h create mode 100644 components/soc/esp32c61/include/soc/i2c_struct.h create mode 100644 components/soc/esp32c61/include/soc/i2s_reg.h create mode 100644 components/soc/esp32c61/include/soc/i2s_struct.h create mode 100644 components/soc/esp32c61/include/soc/interrupt_matrix_reg.h create mode 100644 components/soc/esp32c61/include/soc/interrupt_matrix_struct.h create mode 100644 components/soc/esp32c61/include/soc/interrupts.h create mode 100644 components/soc/esp32c61/include/soc/intpri_reg.h create mode 100644 components/soc/esp32c61/include/soc/intpri_struct.h create mode 100644 components/soc/esp32c61/include/soc/io_mux_reg.h create mode 100644 components/soc/esp32c61/include/soc/io_mux_struct.h create mode 100644 components/soc/esp32c61/include/soc/ledc_reg.h create mode 100644 components/soc/esp32c61/include/soc/ledc_struct.h create mode 100644 components/soc/esp32c61/include/soc/mem_monitor_reg.h create mode 100644 components/soc/esp32c61/include/soc/mem_monitor_struct.h create mode 100644 components/soc/esp32c61/include/soc/pcr_reg.h create mode 100644 components/soc/esp32c61/include/soc/pcr_struct.h create mode 100644 components/soc/esp32c61/include/soc/pmu_icg_mapping.h create mode 100644 components/soc/esp32c61/include/soc/reg_base.h create mode 100644 components/soc/esp32c61/include/soc/soc_etm_reg.h create mode 100644 components/soc/esp32c61/include/soc/soc_etm_source.h create mode 100644 components/soc/esp32c61/include/soc/soc_etm_struct.h create mode 100644 components/soc/esp32c61/include/soc/spi1_mem_reg.h create mode 100644 components/soc/esp32c61/include/soc/spi1_mem_struct.h create mode 100644 components/soc/esp32c61/include/soc/spi_mem_reg.h create mode 100644 components/soc/esp32c61/include/soc/spi_mem_struct.h create mode 100644 components/soc/esp32c61/include/soc/spi_reg.h create mode 100644 components/soc/esp32c61/include/soc/spi_struct.h create mode 100644 components/soc/esp32c61/include/soc/sys_timer_reg.h create mode 100644 components/soc/esp32c61/include/soc/sys_timer_struct.h create mode 100644 components/soc/esp32c61/include/soc/timer_group_reg.h create mode 100644 components/soc/esp32c61/include/soc/timer_group_struct.h create mode 100644 components/soc/esp32c61/include/soc/uart_reg.h create mode 100644 components/soc/esp32c61/include/soc/uart_struct.h create mode 100644 components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h create mode 100644 components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h create mode 100644 components/soc/esp32c61/interrupts.c create mode 100644 components/soc/esp32c61/ld/esp32c61.peripherals.ld diff --git a/components/soc/esp32c61/include/soc/apb_saradc_reg.h b/components/soc/esp32c61/include/soc/apb_saradc_reg.h new file mode 100644 index 0000000000..b855a7cb2a --- /dev/null +++ b/components/soc/esp32c61/include/soc/apb_saradc_reg.h @@ -0,0 +1,884 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SARADC_CTRL_REG register + * digital saradc configure register + */ +#define SARADC_CTRL_REG (DR_REG_SARADC_BASE + 0x0) +/** SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ +#define SARADC_START_FORCE (BIT(0)) +#define SARADC_START_FORCE_M (SARADC_START_FORCE_V << SARADC_START_FORCE_S) +#define SARADC_START_FORCE_V 0x00000001U +#define SARADC_START_FORCE_S 0 +/** SARADC_START : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ +#define SARADC_START (BIT(1)) +#define SARADC_START_M (SARADC_START_V << SARADC_START_S) +#define SARADC_START_V 0x00000001U +#define SARADC_START_S 1 +/** SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ +#define SARADC_SAR_CLK_GATED (BIT(6)) +#define SARADC_SAR_CLK_GATED_M (SARADC_SAR_CLK_GATED_V << SARADC_SAR_CLK_GATED_S) +#define SARADC_SAR_CLK_GATED_V 0x00000001U +#define SARADC_SAR_CLK_GATED_S 6 +/** SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ +#define SARADC_SAR_CLK_DIV 0x000000FFU +#define SARADC_SAR_CLK_DIV_M (SARADC_SAR_CLK_DIV_V << SARADC_SAR_CLK_DIV_S) +#define SARADC_SAR_CLK_DIV_V 0x000000FFU +#define SARADC_SAR_CLK_DIV_S 7 +/** SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ +#define SARADC_SAR_PATT_LEN 0x00000007U +#define SARADC_SAR_PATT_LEN_M (SARADC_SAR_PATT_LEN_V << SARADC_SAR_PATT_LEN_S) +#define SARADC_SAR_PATT_LEN_V 0x00000007U +#define SARADC_SAR_PATT_LEN_S 15 +/** SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ +#define SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define SARADC_SAR_PATT_P_CLEAR_M (SARADC_SAR_PATT_P_CLEAR_V << SARADC_SAR_PATT_P_CLEAR_S) +#define SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define SARADC_SAR_PATT_P_CLEAR_S 23 +/** SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ +#define SARADC_XPD_SAR_FORCE 0x00000003U +#define SARADC_XPD_SAR_FORCE_M (SARADC_XPD_SAR_FORCE_V << SARADC_XPD_SAR_FORCE_S) +#define SARADC_XPD_SAR_FORCE_V 0x00000003U +#define SARADC_XPD_SAR_FORCE_S 27 +/** SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ +#define SARADC_SARADC2_PWDET_DRV (BIT(29)) +#define SARADC_SARADC2_PWDET_DRV_M (SARADC_SARADC2_PWDET_DRV_V << SARADC_SARADC2_PWDET_DRV_S) +#define SARADC_SARADC2_PWDET_DRV_V 0x00000001U +#define SARADC_SARADC2_PWDET_DRV_S 29 +/** SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ +#define SARADC_WAIT_ARB_CYCLE 0x00000003U +#define SARADC_WAIT_ARB_CYCLE_M (SARADC_WAIT_ARB_CYCLE_V << SARADC_WAIT_ARB_CYCLE_S) +#define SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define SARADC_WAIT_ARB_CYCLE_S 30 + +/** SARADC_CTRL2_REG register + * digital saradc configure register + */ +#define SARADC_CTRL2_REG (DR_REG_SARADC_BASE + 0x4) +/** SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ +#define SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define SARADC_MEAS_NUM_LIMIT_M (SARADC_MEAS_NUM_LIMIT_V << SARADC_MEAS_NUM_LIMIT_S) +#define SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define SARADC_MEAS_NUM_LIMIT_S 0 +/** SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ +#define SARADC_MAX_MEAS_NUM 0x000000FFU +#define SARADC_MAX_MEAS_NUM_M (SARADC_MAX_MEAS_NUM_V << SARADC_MAX_MEAS_NUM_S) +#define SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define SARADC_MAX_MEAS_NUM_S 1 +/** SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ +#define SARADC_SAR1_INV (BIT(9)) +#define SARADC_SAR1_INV_M (SARADC_SAR1_INV_V << SARADC_SAR1_INV_S) +#define SARADC_SAR1_INV_V 0x00000001U +#define SARADC_SAR1_INV_S 9 +/** SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ +#define SARADC_SAR2_INV (BIT(10)) +#define SARADC_SAR2_INV_M (SARADC_SAR2_INV_V << SARADC_SAR2_INV_S) +#define SARADC_SAR2_INV_V 0x00000001U +#define SARADC_SAR2_INV_S 10 +/** SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ +#define SARADC_TIMER_TARGET 0x00000FFFU +#define SARADC_TIMER_TARGET_M (SARADC_TIMER_TARGET_V << SARADC_TIMER_TARGET_S) +#define SARADC_TIMER_TARGET_V 0x00000FFFU +#define SARADC_TIMER_TARGET_S 12 +/** SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ +#define SARADC_TIMER_EN (BIT(24)) +#define SARADC_TIMER_EN_M (SARADC_TIMER_EN_V << SARADC_TIMER_EN_S) +#define SARADC_TIMER_EN_V 0x00000001U +#define SARADC_TIMER_EN_S 24 + +/** SARADC_FILTER_CTRL1_REG register + * digital saradc configure register + */ +#define SARADC_FILTER_CTRL1_REG (DR_REG_SARADC_BASE + 0x8) +/** SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ +#define SARADC_FILTER_FACTOR1 0x00000007U +#define SARADC_FILTER_FACTOR1_M (SARADC_FILTER_FACTOR1_V << SARADC_FILTER_FACTOR1_S) +#define SARADC_FILTER_FACTOR1_V 0x00000007U +#define SARADC_FILTER_FACTOR1_S 26 +/** SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ +#define SARADC_FILTER_FACTOR0 0x00000007U +#define SARADC_FILTER_FACTOR0_M (SARADC_FILTER_FACTOR0_V << SARADC_FILTER_FACTOR0_S) +#define SARADC_FILTER_FACTOR0_V 0x00000007U +#define SARADC_FILTER_FACTOR0_S 29 + +/** SARADC_FSM_WAIT_REG register + * digital saradc configure register + */ +#define SARADC_FSM_WAIT_REG (DR_REG_SARADC_BASE + 0xc) +/** SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; + * saradc_xpd_wait + */ +#define SARADC_XPD_WAIT 0x000000FFU +#define SARADC_XPD_WAIT_M (SARADC_XPD_WAIT_V << SARADC_XPD_WAIT_S) +#define SARADC_XPD_WAIT_V 0x000000FFU +#define SARADC_XPD_WAIT_S 0 +/** SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; + * saradc_rstb_wait + */ +#define SARADC_RSTB_WAIT 0x000000FFU +#define SARADC_RSTB_WAIT_M (SARADC_RSTB_WAIT_V << SARADC_RSTB_WAIT_S) +#define SARADC_RSTB_WAIT_V 0x000000FFU +#define SARADC_RSTB_WAIT_S 8 +/** SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; + * saradc_standby_wait + */ +#define SARADC_STANDBY_WAIT 0x000000FFU +#define SARADC_STANDBY_WAIT_M (SARADC_STANDBY_WAIT_V << SARADC_STANDBY_WAIT_S) +#define SARADC_STANDBY_WAIT_V 0x000000FFU +#define SARADC_STANDBY_WAIT_S 16 + +/** SARADC_SAR1_STATUS_REG register + * digital saradc configure register + */ +#define SARADC_SAR1_STATUS_REG (DR_REG_SARADC_BASE + 0x10) +/** SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912; + * saradc1 status about data and channel + */ +#define SARADC_SAR1_STATUS 0xFFFFFFFFU +#define SARADC_SAR1_STATUS_M (SARADC_SAR1_STATUS_V << SARADC_SAR1_STATUS_S) +#define SARADC_SAR1_STATUS_V 0xFFFFFFFFU +#define SARADC_SAR1_STATUS_S 0 + +/** SARADC_SAR2_STATUS_REG register + * digital saradc configure register + */ +#define SARADC_SAR2_STATUS_REG (DR_REG_SARADC_BASE + 0x14) +/** SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912; + * saradc2 status about data and channel + */ +#define SARADC_SAR2_STATUS 0xFFFFFFFFU +#define SARADC_SAR2_STATUS_M (SARADC_SAR2_STATUS_V << SARADC_SAR2_STATUS_S) +#define SARADC_SAR2_STATUS_V 0xFFFFFFFFU +#define SARADC_SAR2_STATUS_S 0 + +/** SARADC_SAR_PATT_TAB1_REG register + * digital saradc configure register + */ +#define SARADC_SAR_PATT_TAB1_REG (DR_REG_SARADC_BASE + 0x18) +/** SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ +#define SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define SARADC_SAR_PATT_TAB1_M (SARADC_SAR_PATT_TAB1_V << SARADC_SAR_PATT_TAB1_S) +#define SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define SARADC_SAR_PATT_TAB1_S 0 + +/** SARADC_SAR_PATT_TAB2_REG register + * digital saradc configure register + */ +#define SARADC_SAR_PATT_TAB2_REG (DR_REG_SARADC_BASE + 0x1c) +/** SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ +#define SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define SARADC_SAR_PATT_TAB2_M (SARADC_SAR_PATT_TAB2_V << SARADC_SAR_PATT_TAB2_S) +#define SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define SARADC_SAR_PATT_TAB2_S 0 + +/** SARADC_ONETIME_SAMPLE_REG register + * digital saradc configure register + */ +#define SARADC_ONETIME_SAMPLE_REG (DR_REG_SARADC_BASE + 0x20) +/** SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ +#define SARADC_ONETIME_ATTEN 0x00000003U +#define SARADC_ONETIME_ATTEN_M (SARADC_ONETIME_ATTEN_V << SARADC_ONETIME_ATTEN_S) +#define SARADC_ONETIME_ATTEN_V 0x00000003U +#define SARADC_ONETIME_ATTEN_S 23 +/** SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ +#define SARADC_ONETIME_CHANNEL 0x0000000FU +#define SARADC_ONETIME_CHANNEL_M (SARADC_ONETIME_CHANNEL_V << SARADC_ONETIME_CHANNEL_S) +#define SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define SARADC_ONETIME_CHANNEL_S 25 +/** SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ +#define SARADC_ONETIME_START (BIT(29)) +#define SARADC_ONETIME_START_M (SARADC_ONETIME_START_V << SARADC_ONETIME_START_S) +#define SARADC_ONETIME_START_V 0x00000001U +#define SARADC_ONETIME_START_S 29 +/** SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ +#define SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define SARADC_SARADC2_ONETIME_SAMPLE_M (SARADC_SARADC2_ONETIME_SAMPLE_V << SARADC_SARADC2_ONETIME_SAMPLE_S) +#define SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define SARADC_SARADC2_ONETIME_SAMPLE_S 30 +/** SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ +#define SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define SARADC_SARADC1_ONETIME_SAMPLE_M (SARADC_SARADC1_ONETIME_SAMPLE_V << SARADC_SARADC1_ONETIME_SAMPLE_S) +#define SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define SARADC_SARADC1_ONETIME_SAMPLE_S 31 + +/** SARADC_ARB_CTRL_REG register + * digital saradc configure register + */ +#define SARADC_ARB_CTRL_REG (DR_REG_SARADC_BASE + 0x24) +/** SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ +#define SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define SARADC_ADC_ARB_APB_FORCE_M (SARADC_ADC_ARB_APB_FORCE_V << SARADC_ADC_ARB_APB_FORCE_S) +#define SARADC_ADC_ARB_APB_FORCE_V 0x00000001U +#define SARADC_ADC_ARB_APB_FORCE_S 2 +/** SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ +#define SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define SARADC_ADC_ARB_RTC_FORCE_M (SARADC_ADC_ARB_RTC_FORCE_V << SARADC_ADC_ARB_RTC_FORCE_S) +#define SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U +#define SARADC_ADC_ARB_RTC_FORCE_S 3 +/** SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ +#define SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define SARADC_ADC_ARB_WIFI_FORCE_M (SARADC_ADC_ARB_WIFI_FORCE_V << SARADC_ADC_ARB_WIFI_FORCE_S) +#define SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U +#define SARADC_ADC_ARB_WIFI_FORCE_S 4 +/** SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ +#define SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define SARADC_ADC_ARB_GRANT_FORCE_M (SARADC_ADC_ARB_GRANT_FORCE_V << SARADC_ADC_ARB_GRANT_FORCE_S) +#define SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U +#define SARADC_ADC_ARB_GRANT_FORCE_S 5 +/** SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ +#define SARADC_ADC_ARB_APB_PRIORITY 0x00000003U +#define SARADC_ADC_ARB_APB_PRIORITY_M (SARADC_ADC_ARB_APB_PRIORITY_V << SARADC_ADC_ARB_APB_PRIORITY_S) +#define SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U +#define SARADC_ADC_ARB_APB_PRIORITY_S 6 +/** SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ +#define SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U +#define SARADC_ADC_ARB_RTC_PRIORITY_M (SARADC_ADC_ARB_RTC_PRIORITY_V << SARADC_ADC_ARB_RTC_PRIORITY_S) +#define SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U +#define SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/** SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ +#define SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U +#define SARADC_ADC_ARB_WIFI_PRIORITY_M (SARADC_ADC_ARB_WIFI_PRIORITY_V << SARADC_ADC_ARB_WIFI_PRIORITY_S) +#define SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U +#define SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/** SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ +#define SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define SARADC_ADC_ARB_FIX_PRIORITY_M (SARADC_ADC_ARB_FIX_PRIORITY_V << SARADC_ADC_ARB_FIX_PRIORITY_S) +#define SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U +#define SARADC_ADC_ARB_FIX_PRIORITY_S 12 + +/** SARADC_FILTER_CTRL0_REG register + * digital saradc configure register + */ +#define SARADC_FILTER_CTRL0_REG (DR_REG_SARADC_BASE + 0x28) +/** SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ +#define SARADC_FILTER_CHANNEL1 0x0000000FU +#define SARADC_FILTER_CHANNEL1_M (SARADC_FILTER_CHANNEL1_V << SARADC_FILTER_CHANNEL1_S) +#define SARADC_FILTER_CHANNEL1_V 0x0000000FU +#define SARADC_FILTER_CHANNEL1_S 18 +/** SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ +#define SARADC_FILTER_CHANNEL0 0x0000000FU +#define SARADC_FILTER_CHANNEL0_M (SARADC_FILTER_CHANNEL0_V << SARADC_FILTER_CHANNEL0_S) +#define SARADC_FILTER_CHANNEL0_V 0x0000000FU +#define SARADC_FILTER_CHANNEL0_S 22 +/** SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ +#define SARADC_FILTER_RESET (BIT(31)) +#define SARADC_FILTER_RESET_M (SARADC_FILTER_RESET_V << SARADC_FILTER_RESET_S) +#define SARADC_FILTER_RESET_V 0x00000001U +#define SARADC_FILTER_RESET_S 31 + +/** SARADC_SAR1DATA_STATUS_REG register + * digital saradc configure register + */ +#define SARADC_SAR1DATA_STATUS_REG (DR_REG_SARADC_BASE + 0x2c) +/** SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ +#define SARADC_APB_SARADC1_DATA 0x0001FFFFU +#define SARADC_APB_SARADC1_DATA_M (SARADC_APB_SARADC1_DATA_V << SARADC_APB_SARADC1_DATA_S) +#define SARADC_APB_SARADC1_DATA_V 0x0001FFFFU +#define SARADC_APB_SARADC1_DATA_S 0 + +/** SARADC_SAR2DATA_STATUS_REG register + * digital saradc configure register + */ +#define SARADC_SAR2DATA_STATUS_REG (DR_REG_SARADC_BASE + 0x30) +/** SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ +#define SARADC_APB_SARADC2_DATA 0x0001FFFFU +#define SARADC_APB_SARADC2_DATA_M (SARADC_APB_SARADC2_DATA_V << SARADC_APB_SARADC2_DATA_S) +#define SARADC_APB_SARADC2_DATA_V 0x0001FFFFU +#define SARADC_APB_SARADC2_DATA_S 0 + +/** SARADC_THRES0_CTRL_REG register + * digital saradc configure register + */ +#define SARADC_THRES0_CTRL_REG (DR_REG_SARADC_BASE + 0x34) +/** SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ +#define SARADC_THRES0_CHANNEL 0x0000000FU +#define SARADC_THRES0_CHANNEL_M (SARADC_THRES0_CHANNEL_V << SARADC_THRES0_CHANNEL_S) +#define SARADC_THRES0_CHANNEL_V 0x0000000FU +#define SARADC_THRES0_CHANNEL_S 0 +/** SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ +#define SARADC_THRES0_HIGH 0x00001FFFU +#define SARADC_THRES0_HIGH_M (SARADC_THRES0_HIGH_V << SARADC_THRES0_HIGH_S) +#define SARADC_THRES0_HIGH_V 0x00001FFFU +#define SARADC_THRES0_HIGH_S 5 +/** SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ +#define SARADC_THRES0_LOW 0x00001FFFU +#define SARADC_THRES0_LOW_M (SARADC_THRES0_LOW_V << SARADC_THRES0_LOW_S) +#define SARADC_THRES0_LOW_V 0x00001FFFU +#define SARADC_THRES0_LOW_S 18 + +/** SARADC_THRES1_CTRL_REG register + * digital saradc configure register + */ +#define SARADC_THRES1_CTRL_REG (DR_REG_SARADC_BASE + 0x38) +/** SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ +#define SARADC_THRES1_CHANNEL 0x0000000FU +#define SARADC_THRES1_CHANNEL_M (SARADC_THRES1_CHANNEL_V << SARADC_THRES1_CHANNEL_S) +#define SARADC_THRES1_CHANNEL_V 0x0000000FU +#define SARADC_THRES1_CHANNEL_S 0 +/** SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ +#define SARADC_THRES1_HIGH 0x00001FFFU +#define SARADC_THRES1_HIGH_M (SARADC_THRES1_HIGH_V << SARADC_THRES1_HIGH_S) +#define SARADC_THRES1_HIGH_V 0x00001FFFU +#define SARADC_THRES1_HIGH_S 5 +/** SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ +#define SARADC_THRES1_LOW 0x00001FFFU +#define SARADC_THRES1_LOW_M (SARADC_THRES1_LOW_V << SARADC_THRES1_LOW_S) +#define SARADC_THRES1_LOW_V 0x00001FFFU +#define SARADC_THRES1_LOW_S 18 + +/** SARADC_THRES_CTRL_REG register + * digital saradc configure register + */ +#define SARADC_THRES_CTRL_REG (DR_REG_SARADC_BASE + 0x3c) +/** SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ +#define SARADC_THRES_ALL_EN (BIT(27)) +#define SARADC_THRES_ALL_EN_M (SARADC_THRES_ALL_EN_V << SARADC_THRES_ALL_EN_S) +#define SARADC_THRES_ALL_EN_V 0x00000001U +#define SARADC_THRES_ALL_EN_S 27 +/** SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ +#define SARADC_THRES1_EN (BIT(30)) +#define SARADC_THRES1_EN_M (SARADC_THRES1_EN_V << SARADC_THRES1_EN_S) +#define SARADC_THRES1_EN_V 0x00000001U +#define SARADC_THRES1_EN_S 30 +/** SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ +#define SARADC_THRES0_EN (BIT(31)) +#define SARADC_THRES0_EN_M (SARADC_THRES0_EN_V << SARADC_THRES0_EN_S) +#define SARADC_THRES0_EN_V 0x00000001U +#define SARADC_THRES0_EN_S 31 + +/** SARADC_INT_ENA_REG register + * digital saradc int register + */ +#define SARADC_INT_ENA_REG (DR_REG_SARADC_BASE + 0x40) +/** SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ +#define SARADC_TSENS_INT_ENA (BIT(25)) +#define SARADC_TSENS_INT_ENA_M (SARADC_TSENS_INT_ENA_V << SARADC_TSENS_INT_ENA_S) +#define SARADC_TSENS_INT_ENA_V 0x00000001U +#define SARADC_TSENS_INT_ENA_S 25 +/** SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ +#define SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define SARADC_THRES1_LOW_INT_ENA_M (SARADC_THRES1_LOW_INT_ENA_V << SARADC_THRES1_LOW_INT_ENA_S) +#define SARADC_THRES1_LOW_INT_ENA_V 0x00000001U +#define SARADC_THRES1_LOW_INT_ENA_S 26 +/** SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ +#define SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define SARADC_THRES0_LOW_INT_ENA_M (SARADC_THRES0_LOW_INT_ENA_V << SARADC_THRES0_LOW_INT_ENA_S) +#define SARADC_THRES0_LOW_INT_ENA_V 0x00000001U +#define SARADC_THRES0_LOW_INT_ENA_S 27 +/** SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ +#define SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define SARADC_THRES1_HIGH_INT_ENA_M (SARADC_THRES1_HIGH_INT_ENA_V << SARADC_THRES1_HIGH_INT_ENA_S) +#define SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U +#define SARADC_THRES1_HIGH_INT_ENA_S 28 +/** SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ +#define SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define SARADC_THRES0_HIGH_INT_ENA_M (SARADC_THRES0_HIGH_INT_ENA_V << SARADC_THRES0_HIGH_INT_ENA_S) +#define SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U +#define SARADC_THRES0_HIGH_INT_ENA_S 29 +/** SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ +#define SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30)) +#define SARADC_APB_SARADC2_DONE_INT_ENA_M (SARADC_APB_SARADC2_DONE_INT_ENA_V << SARADC_APB_SARADC2_DONE_INT_ENA_S) +#define SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U +#define SARADC_APB_SARADC2_DONE_INT_ENA_S 30 +/** SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ +#define SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31)) +#define SARADC_APB_SARADC1_DONE_INT_ENA_M (SARADC_APB_SARADC1_DONE_INT_ENA_V << SARADC_APB_SARADC1_DONE_INT_ENA_S) +#define SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U +#define SARADC_APB_SARADC1_DONE_INT_ENA_S 31 + +/** SARADC_INT_RAW_REG register + * digital saradc int register + */ +#define SARADC_INT_RAW_REG (DR_REG_SARADC_BASE + 0x44) +/** SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ +#define SARADC_TSENS_INT_RAW (BIT(25)) +#define SARADC_TSENS_INT_RAW_M (SARADC_TSENS_INT_RAW_V << SARADC_TSENS_INT_RAW_S) +#define SARADC_TSENS_INT_RAW_V 0x00000001U +#define SARADC_TSENS_INT_RAW_S 25 +/** SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ +#define SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define SARADC_THRES1_LOW_INT_RAW_M (SARADC_THRES1_LOW_INT_RAW_V << SARADC_THRES1_LOW_INT_RAW_S) +#define SARADC_THRES1_LOW_INT_RAW_V 0x00000001U +#define SARADC_THRES1_LOW_INT_RAW_S 26 +/** SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ +#define SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define SARADC_THRES0_LOW_INT_RAW_M (SARADC_THRES0_LOW_INT_RAW_V << SARADC_THRES0_LOW_INT_RAW_S) +#define SARADC_THRES0_LOW_INT_RAW_V 0x00000001U +#define SARADC_THRES0_LOW_INT_RAW_S 27 +/** SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ +#define SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define SARADC_THRES1_HIGH_INT_RAW_M (SARADC_THRES1_HIGH_INT_RAW_V << SARADC_THRES1_HIGH_INT_RAW_S) +#define SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U +#define SARADC_THRES1_HIGH_INT_RAW_S 28 +/** SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ +#define SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define SARADC_THRES0_HIGH_INT_RAW_M (SARADC_THRES0_HIGH_INT_RAW_V << SARADC_THRES0_HIGH_INT_RAW_S) +#define SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U +#define SARADC_THRES0_HIGH_INT_RAW_S 29 +/** SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ +#define SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30)) +#define SARADC_APB_SARADC2_DONE_INT_RAW_M (SARADC_APB_SARADC2_DONE_INT_RAW_V << SARADC_APB_SARADC2_DONE_INT_RAW_S) +#define SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U +#define SARADC_APB_SARADC2_DONE_INT_RAW_S 30 +/** SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ +#define SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31)) +#define SARADC_APB_SARADC1_DONE_INT_RAW_M (SARADC_APB_SARADC1_DONE_INT_RAW_V << SARADC_APB_SARADC1_DONE_INT_RAW_S) +#define SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U +#define SARADC_APB_SARADC1_DONE_INT_RAW_S 31 + +/** SARADC_INT_ST_REG register + * digital saradc int register + */ +#define SARADC_INT_ST_REG (DR_REG_SARADC_BASE + 0x48) +/** SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ +#define SARADC_TSENS_INT_ST (BIT(25)) +#define SARADC_TSENS_INT_ST_M (SARADC_TSENS_INT_ST_V << SARADC_TSENS_INT_ST_S) +#define SARADC_TSENS_INT_ST_V 0x00000001U +#define SARADC_TSENS_INT_ST_S 25 +/** SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ +#define SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define SARADC_THRES1_LOW_INT_ST_M (SARADC_THRES1_LOW_INT_ST_V << SARADC_THRES1_LOW_INT_ST_S) +#define SARADC_THRES1_LOW_INT_ST_V 0x00000001U +#define SARADC_THRES1_LOW_INT_ST_S 26 +/** SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ +#define SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define SARADC_THRES0_LOW_INT_ST_M (SARADC_THRES0_LOW_INT_ST_V << SARADC_THRES0_LOW_INT_ST_S) +#define SARADC_THRES0_LOW_INT_ST_V 0x00000001U +#define SARADC_THRES0_LOW_INT_ST_S 27 +/** SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ +#define SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define SARADC_THRES1_HIGH_INT_ST_M (SARADC_THRES1_HIGH_INT_ST_V << SARADC_THRES1_HIGH_INT_ST_S) +#define SARADC_THRES1_HIGH_INT_ST_V 0x00000001U +#define SARADC_THRES1_HIGH_INT_ST_S 28 +/** SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ +#define SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define SARADC_THRES0_HIGH_INT_ST_M (SARADC_THRES0_HIGH_INT_ST_V << SARADC_THRES0_HIGH_INT_ST_S) +#define SARADC_THRES0_HIGH_INT_ST_V 0x00000001U +#define SARADC_THRES0_HIGH_INT_ST_S 29 +/** SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ +#define SARADC_APB_SARADC2_DONE_INT_ST (BIT(30)) +#define SARADC_APB_SARADC2_DONE_INT_ST_M (SARADC_APB_SARADC2_DONE_INT_ST_V << SARADC_APB_SARADC2_DONE_INT_ST_S) +#define SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U +#define SARADC_APB_SARADC2_DONE_INT_ST_S 30 +/** SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ +#define SARADC_APB_SARADC1_DONE_INT_ST (BIT(31)) +#define SARADC_APB_SARADC1_DONE_INT_ST_M (SARADC_APB_SARADC1_DONE_INT_ST_V << SARADC_APB_SARADC1_DONE_INT_ST_S) +#define SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U +#define SARADC_APB_SARADC1_DONE_INT_ST_S 31 + +/** SARADC_INT_CLR_REG register + * digital saradc int register + */ +#define SARADC_INT_CLR_REG (DR_REG_SARADC_BASE + 0x4c) +/** SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ +#define SARADC_TSENS_INT_CLR (BIT(25)) +#define SARADC_TSENS_INT_CLR_M (SARADC_TSENS_INT_CLR_V << SARADC_TSENS_INT_CLR_S) +#define SARADC_TSENS_INT_CLR_V 0x00000001U +#define SARADC_TSENS_INT_CLR_S 25 +/** SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ +#define SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define SARADC_THRES1_LOW_INT_CLR_M (SARADC_THRES1_LOW_INT_CLR_V << SARADC_THRES1_LOW_INT_CLR_S) +#define SARADC_THRES1_LOW_INT_CLR_V 0x00000001U +#define SARADC_THRES1_LOW_INT_CLR_S 26 +/** SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ +#define SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define SARADC_THRES0_LOW_INT_CLR_M (SARADC_THRES0_LOW_INT_CLR_V << SARADC_THRES0_LOW_INT_CLR_S) +#define SARADC_THRES0_LOW_INT_CLR_V 0x00000001U +#define SARADC_THRES0_LOW_INT_CLR_S 27 +/** SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ +#define SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define SARADC_THRES1_HIGH_INT_CLR_M (SARADC_THRES1_HIGH_INT_CLR_V << SARADC_THRES1_HIGH_INT_CLR_S) +#define SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U +#define SARADC_THRES1_HIGH_INT_CLR_S 28 +/** SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ +#define SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define SARADC_THRES0_HIGH_INT_CLR_M (SARADC_THRES0_HIGH_INT_CLR_V << SARADC_THRES0_HIGH_INT_CLR_S) +#define SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U +#define SARADC_THRES0_HIGH_INT_CLR_S 29 +/** SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ +#define SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30)) +#define SARADC_APB_SARADC2_DONE_INT_CLR_M (SARADC_APB_SARADC2_DONE_INT_CLR_V << SARADC_APB_SARADC2_DONE_INT_CLR_S) +#define SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U +#define SARADC_APB_SARADC2_DONE_INT_CLR_S 30 +/** SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ +#define SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31)) +#define SARADC_APB_SARADC1_DONE_INT_CLR_M (SARADC_APB_SARADC1_DONE_INT_CLR_V << SARADC_APB_SARADC1_DONE_INT_CLR_S) +#define SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U +#define SARADC_APB_SARADC1_DONE_INT_CLR_S 31 + +/** SARADC_DMA_CONF_REG register + * digital saradc configure register + */ +#define SARADC_DMA_CONF_REG (DR_REG_SARADC_BASE + 0x50) +/** SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ +#define SARADC_APB_ADC_EOF_NUM 0x0000FFFFU +#define SARADC_APB_ADC_EOF_NUM_M (SARADC_APB_ADC_EOF_NUM_V << SARADC_APB_ADC_EOF_NUM_S) +#define SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU +#define SARADC_APB_ADC_EOF_NUM_S 0 +/** SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ +#define SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define SARADC_APB_ADC_RESET_FSM_M (SARADC_APB_ADC_RESET_FSM_V << SARADC_APB_ADC_RESET_FSM_S) +#define SARADC_APB_ADC_RESET_FSM_V 0x00000001U +#define SARADC_APB_ADC_RESET_FSM_S 30 +/** SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ +#define SARADC_APB_ADC_TRANS (BIT(31)) +#define SARADC_APB_ADC_TRANS_M (SARADC_APB_ADC_TRANS_V << SARADC_APB_ADC_TRANS_S) +#define SARADC_APB_ADC_TRANS_V 0x00000001U +#define SARADC_APB_ADC_TRANS_S 31 + +/** SARADC_CLKM_CONF_REG register + * digital saradc configure register + */ +#define SARADC_CLKM_CONF_REG (DR_REG_SARADC_BASE + 0x54) +/** SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ +#define SARADC_CLKM_DIV_NUM 0x000000FFU +#define SARADC_CLKM_DIV_NUM_M (SARADC_CLKM_DIV_NUM_V << SARADC_CLKM_DIV_NUM_S) +#define SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define SARADC_CLKM_DIV_NUM_S 0 +/** SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ +#define SARADC_CLKM_DIV_B 0x0000003FU +#define SARADC_CLKM_DIV_B_M (SARADC_CLKM_DIV_B_V << SARADC_CLKM_DIV_B_S) +#define SARADC_CLKM_DIV_B_V 0x0000003FU +#define SARADC_CLKM_DIV_B_S 8 +/** SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ +#define SARADC_CLKM_DIV_A 0x0000003FU +#define SARADC_CLKM_DIV_A_M (SARADC_CLKM_DIV_A_V << SARADC_CLKM_DIV_A_S) +#define SARADC_CLKM_DIV_A_V 0x0000003FU +#define SARADC_CLKM_DIV_A_S 14 +/** SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; + * reg clk en + */ +#define SARADC_CLK_EN (BIT(20)) +#define SARADC_CLK_EN_M (SARADC_CLK_EN_V << SARADC_CLK_EN_S) +#define SARADC_CLK_EN_V 0x00000001U +#define SARADC_CLK_EN_S 20 +/** SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ +#define SARADC_CLK_SEL 0x00000003U +#define SARADC_CLK_SEL_M (SARADC_CLK_SEL_V << SARADC_CLK_SEL_S) +#define SARADC_CLK_SEL_V 0x00000003U +#define SARADC_CLK_SEL_S 21 + +/** SARADC_APB_TSENS_CTRL_REG register + * digital tsens configure register + */ +#define SARADC_APB_TSENS_CTRL_REG (DR_REG_SARADC_BASE + 0x58) +/** SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ +#define SARADC_TSENS_OUT 0x000000FFU +#define SARADC_TSENS_OUT_M (SARADC_TSENS_OUT_V << SARADC_TSENS_OUT_S) +#define SARADC_TSENS_OUT_V 0x000000FFU +#define SARADC_TSENS_OUT_S 0 +/** SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ +#define SARADC_TSENS_IN_INV (BIT(13)) +#define SARADC_TSENS_IN_INV_M (SARADC_TSENS_IN_INV_V << SARADC_TSENS_IN_INV_S) +#define SARADC_TSENS_IN_INV_V 0x00000001U +#define SARADC_TSENS_IN_INV_S 13 +/** SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ +#define SARADC_TSENS_CLK_DIV 0x000000FFU +#define SARADC_TSENS_CLK_DIV_M (SARADC_TSENS_CLK_DIV_V << SARADC_TSENS_CLK_DIV_S) +#define SARADC_TSENS_CLK_DIV_V 0x000000FFU +#define SARADC_TSENS_CLK_DIV_S 14 +/** SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ +#define SARADC_TSENS_PU (BIT(22)) +#define SARADC_TSENS_PU_M (SARADC_TSENS_PU_V << SARADC_TSENS_PU_S) +#define SARADC_TSENS_PU_V 0x00000001U +#define SARADC_TSENS_PU_S 22 + +/** SARADC_TSENS_CTRL2_REG register + * digital tsens configure register + */ +#define SARADC_TSENS_CTRL2_REG (DR_REG_SARADC_BASE + 0x5c) +/** SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; + * the time that power up tsens need wait + */ +#define SARADC_TSENS_XPD_WAIT 0x00000FFFU +#define SARADC_TSENS_XPD_WAIT_M (SARADC_TSENS_XPD_WAIT_V << SARADC_TSENS_XPD_WAIT_S) +#define SARADC_TSENS_XPD_WAIT_V 0x00000FFFU +#define SARADC_TSENS_XPD_WAIT_S 0 +/** SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0; + * force power up tsens + */ +#define SARADC_TSENS_XPD_FORCE 0x00000003U +#define SARADC_TSENS_XPD_FORCE_M (SARADC_TSENS_XPD_FORCE_V << SARADC_TSENS_XPD_FORCE_S) +#define SARADC_TSENS_XPD_FORCE_V 0x00000003U +#define SARADC_TSENS_XPD_FORCE_S 12 +/** SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1; + * inv tsens clk + */ +#define SARADC_TSENS_CLK_INV (BIT(14)) +#define SARADC_TSENS_CLK_INV_M (SARADC_TSENS_CLK_INV_V << SARADC_TSENS_CLK_INV_S) +#define SARADC_TSENS_CLK_INV_V 0x00000001U +#define SARADC_TSENS_CLK_INV_S 14 +/** SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ +#define SARADC_TSENS_CLK_SEL (BIT(15)) +#define SARADC_TSENS_CLK_SEL_M (SARADC_TSENS_CLK_SEL_V << SARADC_TSENS_CLK_SEL_S) +#define SARADC_TSENS_CLK_SEL_V 0x00000001U +#define SARADC_TSENS_CLK_SEL_S 15 + +/** SARADC_CALI_REG register + * digital saradc configure register + */ +#define SARADC_CALI_REG (DR_REG_SARADC_BASE + 0x60) +/** SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ +#define SARADC_CALI_CFG 0x0001FFFFU +#define SARADC_CALI_CFG_M (SARADC_CALI_CFG_V << SARADC_CALI_CFG_S) +#define SARADC_CALI_CFG_V 0x0001FFFFU +#define SARADC_CALI_CFG_S 0 + +/** APB_TSENS_WAKE_REG register + * digital tsens configure register + */ +#define APB_TSENS_WAKE_REG (DR_REG_SARADC_BASE + 0x64) +/** SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ +#define SARADC_WAKEUP_TH_LOW 0x000000FFU +#define SARADC_WAKEUP_TH_LOW_M (SARADC_WAKEUP_TH_LOW_V << SARADC_WAKEUP_TH_LOW_S) +#define SARADC_WAKEUP_TH_LOW_V 0x000000FFU +#define SARADC_WAKEUP_TH_LOW_S 0 +/** SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ +#define SARADC_WAKEUP_TH_HIGH 0x000000FFU +#define SARADC_WAKEUP_TH_HIGH_M (SARADC_WAKEUP_TH_HIGH_V << SARADC_WAKEUP_TH_HIGH_S) +#define SARADC_WAKEUP_TH_HIGH_V 0x000000FFU +#define SARADC_WAKEUP_TH_HIGH_S 8 +/** SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ +#define SARADC_WAKEUP_OVER_UPPER_TH (BIT(16)) +#define SARADC_WAKEUP_OVER_UPPER_TH_M (SARADC_WAKEUP_OVER_UPPER_TH_V << SARADC_WAKEUP_OVER_UPPER_TH_S) +#define SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define SARADC_WAKEUP_OVER_UPPER_TH_S 16 +/** SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ +#define SARADC_WAKEUP_MODE (BIT(17)) +#define SARADC_WAKEUP_MODE_M (SARADC_WAKEUP_MODE_V << SARADC_WAKEUP_MODE_S) +#define SARADC_WAKEUP_MODE_V 0x00000001U +#define SARADC_WAKEUP_MODE_S 17 +/** SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ +#define SARADC_WAKEUP_EN (BIT(18)) +#define SARADC_WAKEUP_EN_M (SARADC_WAKEUP_EN_V << SARADC_WAKEUP_EN_S) +#define SARADC_WAKEUP_EN_V 0x00000001U +#define SARADC_WAKEUP_EN_S 18 + +/** APB_TSENS_SAMPLE_REG register + * digital tsens configure register + */ +#define APB_TSENS_SAMPLE_REG (DR_REG_SARADC_BASE + 0x68) +/** SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ +#define SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU +#define SARADC_TSENS_SAMPLE_RATE_M (SARADC_TSENS_SAMPLE_RATE_V << SARADC_TSENS_SAMPLE_RATE_S) +#define SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define SARADC_TSENS_SAMPLE_RATE_S 0 +/** SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0; + * HW sample en + */ +#define SARADC_TSENS_SAMPLE_EN (BIT(16)) +#define SARADC_TSENS_SAMPLE_EN_M (SARADC_TSENS_SAMPLE_EN_V << SARADC_TSENS_SAMPLE_EN_S) +#define SARADC_TSENS_SAMPLE_EN_V 0x00000001U +#define SARADC_TSENS_SAMPLE_EN_S 16 + +/** SARADC_CTRL_DATE_REG register + * version + */ +#define SARADC_CTRL_DATE_REG (DR_REG_SARADC_BASE + 0x3fc) +/** SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; + * version + */ +#define SARADC_DATE 0xFFFFFFFFU +#define SARADC_DATE_M (SARADC_DATE_V << SARADC_DATE_S) +#define SARADC_DATE_V 0xFFFFFFFFU +#define SARADC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/apb_saradc_struct.h b/components/soc/esp32c61/include/soc/apb_saradc_struct.h new file mode 100644 index 0000000000..36de5a70de --- /dev/null +++ b/components/soc/esp32c61/include/soc/apb_saradc_struct.h @@ -0,0 +1,757 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Register */ +/** Type of saradc_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_start_force : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ + uint32_t saradc_start_force:1; + /** saradc_start : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ + uint32_t saradc_start:1; + uint32_t reserved_2:4; + /** saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ + uint32_t saradc_sar_clk_gated:1; + /** saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + uint32_t saradc_sar_clk_div:8; + /** saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ + uint32_t saradc_sar_patt_len:3; + uint32_t reserved_18:5; + /** saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + uint32_t saradc_sar_patt_p_clear:1; + uint32_t reserved_24:3; + /** saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ + uint32_t saradc_xpd_sar_force:2; + /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ + uint32_t saradc_saradc2_pwdet_drv:1; + /** saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ + uint32_t saradc_wait_arb_cycle:2; + }; + uint32_t val; +} adc_ctrl_reg_t; + +/** Type of saradc_ctrl2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ + uint32_t saradc_meas_num_limit:1; + /** saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ + uint32_t saradc_max_meas_num:8; + /** saradc_sar1_inv : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ + uint32_t saradc_sar1_inv:1; + /** saradc_sar2_inv : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ + uint32_t saradc_sar2_inv:1; + uint32_t reserved_11:1; + /** saradc_timer_target : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ + uint32_t saradc_timer_target:12; + /** saradc_timer_en : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ + uint32_t saradc_timer_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} adc_ctrl2_reg_t; + +/** Type of saradc_filter_ctrl1 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_adc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ + uint32_t saradc_adc_filter_factor1:3; + /** saradc_adc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ + uint32_t saradc_adc_filter_factor0:3; + }; + uint32_t val; +} adc_filter_ctrl1_reg_t; + +/** Type of saradc_fsm_wait register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8; + * saradc_xpd_wait + */ + uint32_t saradc_xpd_wait:8; + /** saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8; + * saradc_rstb_wait + */ + uint32_t saradc_rstb_wait:8; + /** saradc_standby_wait : R/W; bitpos: [23:16]; default: 255; + * saradc_standby_wait + */ + uint32_t saradc_standby_wait:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} adc_fsm_wait_reg_t; + +/** Type of saradc_sar1_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912; + * saradc1 status about data and channel + */ + uint32_t saradc_sar1_status:32; + }; + uint32_t val; +} adc_sar1_status_reg_t; + +/** Type of saradc_sar2_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912; + * saradc2 status about data and channel + */ + uint32_t saradc_sar2_status:32; + }; + uint32_t val; +} adc_sar2_status_reg_t; + +/** Type of saradc_sar_patt_tab1 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + uint32_t saradc_sar_patt_tab1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} adc_sar_patt_tab1_reg_t; + +/** Type of saradc_sar_patt_tab2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + uint32_t saradc_sar_patt_tab2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} adc_sar_patt_tab2_reg_t; + +/** Type of saradc_onetime_sample register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ + uint32_t saradc_onetime_atten:2; + /** saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ + uint32_t saradc_onetime_channel:4; + /** saradc_onetime_start : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ + uint32_t saradc_onetime_start:1; + /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ + uint32_t saradc_saradc2_onetime_sample:1; + /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ + uint32_t saradc_saradc1_onetime_sample:1; + }; + uint32_t val; +} adc_onetime_sample_reg_t; + +/** Type of saradc_arb_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ + uint32_t saradc_adc_arb_apb_force:1; + /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ + uint32_t saradc_adc_arb_rtc_force:1; + /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ + uint32_t saradc_adc_arb_wifi_force:1; + /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ + uint32_t saradc_adc_arb_grant_force:1; + /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ + uint32_t saradc_adc_arb_apb_priority:2; + /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ + uint32_t saradc_adc_arb_rtc_priority:2; + /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ + uint32_t saradc_adc_arb_wifi_priority:2; + /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ + uint32_t saradc_adc_arb_fix_priority:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} adc_arb_ctrl_reg_t; + +/** Type of saradc_filter_ctrl0 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** saradc_adc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ + uint32_t saradc_adc_filter_channel1:4; + /** saradc_adc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ + uint32_t saradc_adc_filter_channel0:4; + uint32_t reserved_26:5; + /** saradc_adc_filter_reset : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ + uint32_t saradc_adc_filter_reset:1; + }; + uint32_t val; +} adc_filter_ctrl0_reg_t; + +/** Type of saradc_sar1data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_adc1_data : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ + uint32_t saradc_adc1_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} adc_sar1data_status_reg_t; + +/** Type of saradc_sar2data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_adc2_data : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ + uint32_t saradc_adc2_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} adc_sar2data_status_reg_t; + +/** Type of saradc_thres0_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_adc_thres0_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ + uint32_t saradc_adc_thres0_channel:4; + uint32_t reserved_4:1; + /** saradc_adc_thres0_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ + uint32_t saradc_adc_thres0_high:13; + /** saradc_adc_thres0_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ + uint32_t saradc_adc_thres0_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} adc_thres0_ctrl_reg_t; + +/** Type of saradc_thres1_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_adc_thres1_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ + uint32_t saradc_adc_thres1_channel:4; + uint32_t reserved_4:1; + /** saradc_adc_thres1_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ + uint32_t saradc_adc_thres1_high:13; + /** saradc_adc_thres1_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ + uint32_t saradc_adc_thres1_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} adc_thres1_ctrl_reg_t; + +/** Type of saradc_thres_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** saradc_adc_thres_all_en : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ + uint32_t saradc_adc_thres_all_en:1; + uint32_t reserved_28:2; + /** saradc_adc_thres1_en : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ + uint32_t saradc_adc_thres1_en:1; + /** saradc_adc_thres0_en : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ + uint32_t saradc_adc_thres0_en:1; + }; + uint32_t val; +} adc_thres_ctrl_reg_t; + +/** Type of saradc_int_ena register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_adc_tsens_int_ena : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ + uint32_t saradc_adc_tsens_int_ena:1; + /** saradc_adc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ + uint32_t saradc_adc_thres1_low_int_ena:1; + /** saradc_adc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ + uint32_t saradc_adc_thres0_low_int_ena:1; + /** saradc_adc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ + uint32_t saradc_adc_thres1_high_int_ena:1; + /** saradc_adc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ + uint32_t saradc_adc_thres0_high_int_ena:1; + /** saradc_adc2_done_int_ena : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ + uint32_t saradc_adc2_done_int_ena:1; + /** saradc_adc1_done_int_ena : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ + uint32_t saradc_adc1_done_int_ena:1; + }; + uint32_t val; +} adc_int_ena_reg_t; + +/** Type of saradc_int_raw register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_adc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ + uint32_t saradc_adc_tsens_int_raw:1; + /** saradc_adc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ + uint32_t saradc_adc_thres1_low_int_raw:1; + /** saradc_adc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ + uint32_t saradc_adc_thres0_low_int_raw:1; + /** saradc_adc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ + uint32_t saradc_adc_thres1_high_int_raw:1; + /** saradc_adc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ + uint32_t saradc_adc_thres0_high_int_raw:1; + /** saradc_adc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ + uint32_t saradc_adc2_done_int_raw:1; + /** saradc_adc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ + uint32_t saradc_adc1_done_int_raw:1; + }; + uint32_t val; +} adc_int_raw_reg_t; + +/** Type of saradc_int_st register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_adc_tsens_int_st : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ + uint32_t saradc_adc_tsens_int_st:1; + /** saradc_adc_thres1_low_int_st : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ + uint32_t saradc_adc_thres1_low_int_st:1; + /** saradc_adc_thres0_low_int_st : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ + uint32_t saradc_adc_thres0_low_int_st:1; + /** saradc_adc_thres1_high_int_st : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ + uint32_t saradc_adc_thres1_high_int_st:1; + /** saradc_adc_thres0_high_int_st : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ + uint32_t saradc_adc_thres0_high_int_st:1; + /** saradc_adc2_done_int_st : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ + uint32_t saradc_adc2_done_int_st:1; + /** saradc_adc1_done_int_st : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ + uint32_t saradc_adc1_done_int_st:1; + }; + uint32_t val; +} adc_int_st_reg_t; + +/** Type of saradc_int_clr register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_adc_tsens_int_clr : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ + uint32_t saradc_adc_tsens_int_clr:1; + /** saradc_adc_thres1_low_int_clr : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ + uint32_t saradc_adc_thres1_low_int_clr:1; + /** saradc_adc_thres0_low_int_clr : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ + uint32_t saradc_adc_thres0_low_int_clr:1; + /** saradc_adc_thres1_high_int_clr : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ + uint32_t saradc_adc_thres1_high_int_clr:1; + /** saradc_adc_thres0_high_int_clr : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ + uint32_t saradc_adc_thres0_high_int_clr:1; + /** saradc_adc2_done_int_clr : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ + uint32_t saradc_adc2_done_int_clr:1; + /** saradc_adc1_done_int_clr : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ + uint32_t saradc_adc1_done_int_clr:1; + }; + uint32_t val; +} adc_int_clr_reg_t; + +/** Type of saradc_dma_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ + uint32_t saradc_apb_adc_eof_num:16; + uint32_t reserved_16:14; + /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ + uint32_t saradc_apb_adc_reset_fsm:1; + /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ + uint32_t saradc_apb_adc_trans:1; + }; + uint32_t val; +} adc_dma_conf_reg_t; + +/** Type of saradc_clkm_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clk_en : R/W; bitpos: [20]; default: 0; + * reg clk en + */ + uint32_t saradc_clk_en:1; + /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ + uint32_t saradc_clk_sel:2; + uint32_t reserved_23:9; + }; + uint32_t val; +} adc_clkm_conf_reg_t; + +/** Type of saradc_apb_tsens_ctrl register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ + uint32_t saradc_tsens_out:8; + uint32_t reserved_8:5; + /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ + uint32_t saradc_tsens_in_inv:1; + /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ + uint32_t saradc_tsens_clk_div:8; + /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ + uint32_t saradc_tsens_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} adc_apb_tsens_ctrl_reg_t; + +/** Type of saradc_tsens_ctrl2 register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2; + * the time that power up tsens need wait + */ + uint32_t saradc_tsens_xpd_wait:12; + /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0; + * force power up tsens + */ + uint32_t saradc_tsens_xpd_force:2; + /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1; + * inv tsens clk + */ + uint32_t saradc_tsens_clk_inv:1; + /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ + uint32_t saradc_tsens_clk_sel:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} adc_tsens_ctrl2_reg_t; + +/** Type of saradc_cali register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_adc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ + uint32_t saradc_adc_cali_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} adc_cali_reg_t; + +/** Type of tsens_wake register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ + uint32_t saradc_wakeup_th_low:8; + /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ + uint32_t saradc_wakeup_th_high:8; + /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ + uint32_t saradc_wakeup_over_upper_th:1; + /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ + uint32_t saradc_wakeup_mode:1; + /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ + uint32_t saradc_wakeup_en:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} apb_tsens_wake_reg_t; + +/** Type of tsens_sample register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ + uint32_t saradc_tsens_sample_rate:16; + /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0; + * HW sample en + */ + uint32_t saradc_tsens_sample_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_tsens_sample_reg_t; + +/** Type of saradc_ctrl_date register + * version + */ +typedef union { + struct { + /** saradc_date : R/W; bitpos: [31:0]; default: 35676736; + * version + */ + uint32_t saradc_date:32; + }; + uint32_t val; +} adc_ctrl_date_reg_t; + + +typedef struct { + volatile adc_ctrl_reg_t saradc_ctrl; + volatile adc_ctrl2_reg_t saradc_ctrl2; + volatile adc_filter_ctrl1_reg_t saradc_filter_ctrl1; + volatile adc_fsm_wait_reg_t saradc_fsm_wait; + volatile adc_sar1_status_reg_t saradc_sar1_status; + volatile adc_sar2_status_reg_t saradc_sar2_status; + volatile adc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; + volatile adc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; + volatile adc_onetime_sample_reg_t saradc_onetime_sample; + volatile adc_arb_ctrl_reg_t saradc_arb_ctrl; + volatile adc_filter_ctrl0_reg_t saradc_filter_ctrl0; + volatile adc_sar1data_status_reg_t saradc_sar1data_status; + volatile adc_sar2data_status_reg_t saradc_sar2data_status; + volatile adc_thres0_ctrl_reg_t saradc_thres0_ctrl; + volatile adc_thres1_ctrl_reg_t saradc_thres1_ctrl; + volatile adc_thres_ctrl_reg_t saradc_thres_ctrl; + volatile adc_int_ena_reg_t saradc_int_ena; + volatile adc_int_raw_reg_t saradc_int_raw; + volatile adc_int_st_reg_t saradc_int_st; + volatile adc_int_clr_reg_t saradc_int_clr; + volatile adc_dma_conf_reg_t saradc_dma_conf; + volatile adc_clkm_conf_reg_t saradc_clkm_conf; + volatile adc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; + volatile adc_tsens_ctrl2_reg_t saradc_tsens_ctrl2; + volatile adc_cali_reg_t saradc_cali; + volatile apb_tsens_wake_reg_t tsens_wake; + volatile apb_tsens_sample_reg_t tsens_sample; + uint32_t reserved_06c[228]; + volatile adc_ctrl_date_reg_t saradc_ctrl_date; +} adc_dev_t; + +extern adc_dev_t ADC; + +#ifndef __cplusplus +_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/cache_reg.h b/components/soc/esp32c61/include/soc/cache_reg.h new file mode 100644 index 0000000000..98390f8e1a --- /dev/null +++ b/components/soc/esp32c61/include/soc/cache_reg.h @@ -0,0 +1,6166 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CACHE_L1_ICACHE_CTRL_REG register + * L1 instruction Cache(L1-ICache) control register + */ +#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0) +/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + */ +#define CACHE_L1_ICACHE_SHUT_IBUS0 (BIT(0)) +#define CACHE_L1_ICACHE_SHUT_IBUS0_M (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S) +#define CACHE_L1_ICACHE_SHUT_IBUS0_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS0_S 0 +/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + */ +#define CACHE_L1_ICACHE_SHUT_IBUS1 (BIT(1)) +#define CACHE_L1_ICACHE_SHUT_IBUS1_M (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S) +#define CACHE_L1_ICACHE_SHUT_IBUS1_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS1_S 1 +/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE_SHUT_IBUS2 (BIT(2)) +#define CACHE_L1_ICACHE_SHUT_IBUS2_M (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S) +#define CACHE_L1_ICACHE_SHUT_IBUS2_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS2_S 2 +/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE_SHUT_IBUS3 (BIT(3)) +#define CACHE_L1_ICACHE_SHUT_IBUS3_M (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S) +#define CACHE_L1_ICACHE_SHUT_IBUS3_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS3_S 3 +/** CACHE_L1_ICACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE_UNDEF_OP 0x000000FFU +#define CACHE_L1_ICACHE_UNDEF_OP_M (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S) +#define CACHE_L1_ICACHE_UNDEF_OP_V 0x000000FFU +#define CACHE_L1_ICACHE_UNDEF_OP_S 8 + +/** CACHE_L1_CACHE_CTRL_REG register + * L1 data Cache(L1-Cache) control register + */ +#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) +/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) +#define CACHE_L1_CACHE_SHUT_BUS0_M (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S) +#define CACHE_L1_CACHE_SHUT_BUS0_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS0_S 0 +/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) +#define CACHE_L1_CACHE_SHUT_BUS1_M (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S) +#define CACHE_L1_CACHE_SHUT_BUS1_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS1_S 1 +/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS2 (BIT(2)) +#define CACHE_L1_CACHE_SHUT_DBUS2_M (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S) +#define CACHE_L1_CACHE_SHUT_DBUS2_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS2_S 2 +/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS3 (BIT(3)) +#define CACHE_L1_CACHE_SHUT_DBUS3_M (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S) +#define CACHE_L1_CACHE_SHUT_DBUS3_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS3_S 3 +/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_DMA (BIT(4)) +#define CACHE_L1_CACHE_SHUT_DMA_M (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S) +#define CACHE_L1_CACHE_SHUT_DMA_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DMA_S 4 +/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_UNDEF_OP 0x000000FFU +#define CACHE_L1_CACHE_UNDEF_OP_M (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S) +#define CACHE_L1_CACHE_UNDEF_OP_V 0x000000FFU +#define CACHE_L1_CACHE_UNDEF_OP_S 8 + +/** CACHE_L1_BYPASS_CACHE_CONF_REG register + * Bypass Cache configure register + */ +#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8) +/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L1_ICACHE0_EN (BIT(0)) +#define CACHE_BYPASS_L1_ICACHE0_EN_M (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S) +#define CACHE_BYPASS_L1_ICACHE0_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE0_EN_S 0 +/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L1_ICACHE1_EN (BIT(1)) +#define CACHE_BYPASS_L1_ICACHE1_EN_M (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S) +#define CACHE_BYPASS_L1_ICACHE1_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE1_EN_S 1 +/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_BYPASS_L1_ICACHE2_EN (BIT(2)) +#define CACHE_BYPASS_L1_ICACHE2_EN_M (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S) +#define CACHE_BYPASS_L1_ICACHE2_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE2_EN_S 2 +/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_BYPASS_L1_ICACHE3_EN (BIT(3)) +#define CACHE_BYPASS_L1_ICACHE3_EN_M (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S) +#define CACHE_BYPASS_L1_ICACHE3_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE3_EN_S 3 +/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0; + * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L1_DCACHE_EN (BIT(4)) +#define CACHE_BYPASS_L1_DCACHE_EN_M (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S) +#define CACHE_BYPASS_L1_DCACHE_EN_V 0x00000001U +#define CACHE_BYPASS_L1_DCACHE_EN_S 4 + +/** CACHE_L1_CACHE_ATOMIC_CONF_REG register + * L1 Cache atomic feature configure register + */ +#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc) +/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable atomic feature on L1-Cache when multiple cores access + * L1-Cache. 1: disable, 1: enable. + */ +#define CACHE_L1_CACHE_ATOMIC_EN (BIT(0)) +#define CACHE_L1_CACHE_ATOMIC_EN_M (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S) +#define CACHE_L1_CACHE_ATOMIC_EN_V 0x00000001U +#define CACHE_L1_CACHE_ATOMIC_EN_S 0 + +/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register + * L1 instruction Cache CacheSize mode configure register + */ +#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10) +/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_256 (BIT(0)) +#define CACHE_L1_ICACHE_CACHESIZE_256_M (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S) +#define CACHE_L1_ICACHE_CACHESIZE_256_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_256_S 0 +/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_512 (BIT(1)) +#define CACHE_L1_ICACHE_CACHESIZE_512_M (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S) +#define CACHE_L1_ICACHE_CACHESIZE_512_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_512_S 1 +/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_1K (BIT(2)) +#define CACHE_L1_ICACHE_CACHESIZE_1K_M (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S) +#define CACHE_L1_ICACHE_CACHESIZE_1K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_1K_S 2 +/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_2K (BIT(3)) +#define CACHE_L1_ICACHE_CACHESIZE_2K_M (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S) +#define CACHE_L1_ICACHE_CACHESIZE_2K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_2K_S 3 +/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_4K (BIT(4)) +#define CACHE_L1_ICACHE_CACHESIZE_4K_M (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S) +#define CACHE_L1_ICACHE_CACHESIZE_4K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_4K_S 4 +/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_8K (BIT(5)) +#define CACHE_L1_ICACHE_CACHESIZE_8K_M (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S) +#define CACHE_L1_ICACHE_CACHESIZE_8K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_8K_S 5 +/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_16K (BIT(6)) +#define CACHE_L1_ICACHE_CACHESIZE_16K_M (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S) +#define CACHE_L1_ICACHE_CACHESIZE_16K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_16K_S 6 +/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_32K (BIT(7)) +#define CACHE_L1_ICACHE_CACHESIZE_32K_M (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S) +#define CACHE_L1_ICACHE_CACHESIZE_32K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_32K_S 7 +/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_64K (BIT(8)) +#define CACHE_L1_ICACHE_CACHESIZE_64K_M (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S) +#define CACHE_L1_ICACHE_CACHESIZE_64K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_64K_S 8 +/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_128K (BIT(9)) +#define CACHE_L1_ICACHE_CACHESIZE_128K_M (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S) +#define CACHE_L1_ICACHE_CACHESIZE_128K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_128K_S 9 +/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_256K (BIT(10)) +#define CACHE_L1_ICACHE_CACHESIZE_256K_M (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S) +#define CACHE_L1_ICACHE_CACHESIZE_256K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_256K_S 10 +/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_512K (BIT(11)) +#define CACHE_L1_ICACHE_CACHESIZE_512K_M (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S) +#define CACHE_L1_ICACHE_CACHESIZE_512K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_512K_S 11 +/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_1024K (BIT(12)) +#define CACHE_L1_ICACHE_CACHESIZE_1024K_M (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S) +#define CACHE_L1_ICACHE_CACHESIZE_1024K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_1024K_S 12 + +/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register + * L1 instruction Cache BlockSize mode configure register + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14) +/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_8 (BIT(0)) +#define CACHE_L1_ICACHE_BLOCKSIZE_8_M (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_8_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_8_S 0 +/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_16 (BIT(1)) +#define CACHE_L1_ICACHE_BLOCKSIZE_16_M (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_16_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_16_S 1 +/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_32 (BIT(2)) +#define CACHE_L1_ICACHE_BLOCKSIZE_32_M (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_32_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_32_S 2 +/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_64 (BIT(3)) +#define CACHE_L1_ICACHE_BLOCKSIZE_64_M (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_64_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_64_S 3 +/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_128 (BIT(4)) +#define CACHE_L1_ICACHE_BLOCKSIZE_128_M (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_128_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_128_S 4 +/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_256 (BIT(5)) +#define CACHE_L1_ICACHE_BLOCKSIZE_256_M (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_256_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_256_S 5 + +/** CACHE_L1_CACHE_CACHESIZE_CONF_REG register + * L1 data Cache CacheSize mode configure register + */ +#define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18) +/** CACHE_L1_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_256 (BIT(0)) +#define CACHE_L1_CACHE_CACHESIZE_256_M (CACHE_L1_CACHE_CACHESIZE_256_V << CACHE_L1_CACHE_CACHESIZE_256_S) +#define CACHE_L1_CACHE_CACHESIZE_256_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_256_S 0 +/** CACHE_L1_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-DCache as 512 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_512 (BIT(1)) +#define CACHE_L1_CACHE_CACHESIZE_512_M (CACHE_L1_CACHE_CACHESIZE_512_V << CACHE_L1_CACHE_CACHESIZE_512_S) +#define CACHE_L1_CACHE_CACHESIZE_512_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_512_S 1 +/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-DCache as 1k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_1K (BIT(2)) +#define CACHE_L1_CACHE_CACHESIZE_1K_M (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S) +#define CACHE_L1_CACHE_CACHESIZE_1K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_1K_S 2 +/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-DCache as 2k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_2K (BIT(3)) +#define CACHE_L1_CACHE_CACHESIZE_2K_M (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S) +#define CACHE_L1_CACHE_CACHESIZE_2K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_2K_S 3 +/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-DCache as 4k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_4K (BIT(4)) +#define CACHE_L1_CACHE_CACHESIZE_4K_M (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S) +#define CACHE_L1_CACHE_CACHESIZE_4K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_4K_S 4 +/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-DCache as 8k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_8K (BIT(5)) +#define CACHE_L1_CACHE_CACHESIZE_8K_M (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S) +#define CACHE_L1_CACHE_CACHESIZE_8K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_8K_S 5 +/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-DCache as 16k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_16K (BIT(6)) +#define CACHE_L1_CACHE_CACHESIZE_16K_M (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S) +#define CACHE_L1_CACHE_CACHESIZE_16K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_16K_S 6 +/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 1; + * The field is used to configure cachesize of L1-DCache as 32k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_32K (BIT(7)) +#define CACHE_L1_CACHE_CACHESIZE_32K_M (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S) +#define CACHE_L1_CACHE_CACHESIZE_32K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_32K_S 7 +/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-DCache as 64k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_64K (BIT(8)) +#define CACHE_L1_CACHE_CACHESIZE_64K_M (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S) +#define CACHE_L1_CACHE_CACHESIZE_64K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_64K_S 8 +/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-DCache as 128k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_128K (BIT(9)) +#define CACHE_L1_CACHE_CACHESIZE_128K_M (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S) +#define CACHE_L1_CACHE_CACHESIZE_128K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_128K_S 9 +/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-DCache as 256k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_256K (BIT(10)) +#define CACHE_L1_CACHE_CACHESIZE_256K_M (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S) +#define CACHE_L1_CACHE_CACHESIZE_256K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_256K_S 10 +/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-DCache as 512k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_512K (BIT(11)) +#define CACHE_L1_CACHE_CACHESIZE_512K_M (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S) +#define CACHE_L1_CACHE_CACHESIZE_512K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_512K_S 11 +/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-DCache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_1024K (BIT(12)) +#define CACHE_L1_CACHE_CACHESIZE_1024K_M (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S) +#define CACHE_L1_CACHE_CACHESIZE_1024K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_1024K_S 12 + +/** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register + * L1 data Cache BlockSize mode configure register + */ +#define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c) +/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_8 (BIT(0)) +#define CACHE_L1_CACHE_BLOCKSIZE_8_M (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S) +#define CACHE_L1_CACHE_BLOCKSIZE_8_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_8_S 0 +/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_16 (BIT(1)) +#define CACHE_L1_CACHE_BLOCKSIZE_16_M (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S) +#define CACHE_L1_CACHE_BLOCKSIZE_16_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_16_S 1 +/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1; + * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_32 (BIT(2)) +#define CACHE_L1_CACHE_BLOCKSIZE_32_M (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S) +#define CACHE_L1_CACHE_BLOCKSIZE_32_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_32_S 2 +/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_64 (BIT(3)) +#define CACHE_L1_CACHE_BLOCKSIZE_64_M (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S) +#define CACHE_L1_CACHE_BLOCKSIZE_64_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_64_S 3 +/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_128 (BIT(4)) +#define CACHE_L1_CACHE_BLOCKSIZE_128_M (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S) +#define CACHE_L1_CACHE_BLOCKSIZE_128_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_128_S 4 +/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_256 (BIT(5)) +#define CACHE_L1_CACHE_BLOCKSIZE_256_M (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S) +#define CACHE_L1_CACHE_BLOCKSIZE_256_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_256_S 5 + +/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) +/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to enable L1-ICache0 wrap around mode. + */ +#define CACHE_L1_ICACHE0_WRAP (BIT(0)) +#define CACHE_L1_ICACHE0_WRAP_M (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S) +#define CACHE_L1_ICACHE0_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE0_WRAP_S 0 +/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to enable L1-ICache1 wrap around mode. + */ +#define CACHE_L1_ICACHE1_WRAP (BIT(1)) +#define CACHE_L1_ICACHE1_WRAP_M (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S) +#define CACHE_L1_ICACHE1_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE1_WRAP_S 1 +/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_WRAP (BIT(2)) +#define CACHE_L1_ICACHE2_WRAP_M (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S) +#define CACHE_L1_ICACHE2_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE2_WRAP_S 2 +/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_WRAP (BIT(3)) +#define CACHE_L1_ICACHE3_WRAP_M (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S) +#define CACHE_L1_ICACHE3_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE3_WRAP_S 3 +/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ +#define CACHE_L1_CACHE_WRAP (BIT(4)) +#define CACHE_L1_CACHE_WRAP_M (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S) +#define CACHE_L1_CACHE_WRAP_V 0x00000001U +#define CACHE_L1_CACHE_WRAP_S 4 + +/** CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x24) +/** CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to disable early restart of L1-ICache0 + */ +#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS (BIT(0)) +#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S) +#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V 0x00000001U +#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S 0 +/** CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to disable early restart of L1-ICache1 + */ +#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS (BIT(1)) +#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S) +#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V 0x00000001U +#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S 1 +/** CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS (BIT(2)) +#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S) +#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V 0x00000001U +#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S 2 +/** CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS (BIT(3)) +#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S) +#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V 0x00000001U +#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S 3 +/** CACHE_L1_CACHE_MISS_DISABLE_ACCESS : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to disable early restart of L1-DCache + */ +#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS (BIT(4)) +#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_M (CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S) +#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V 0x00000001U +#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S 4 + +/** CACHE_L1_CACHE_FREEZE_CTRL_REG register + * Cache Freeze control register + */ +#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28) +/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by + * software. + */ +#define CACHE_L1_ICACHE0_FREEZE_EN (BIT(0)) +#define CACHE_L1_ICACHE0_FREEZE_EN_M (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S) +#define CACHE_L1_ICACHE0_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_FREEZE_EN_S 0 +/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_ICACHE0_FREEZE_MODE (BIT(1)) +#define CACHE_L1_ICACHE0_FREEZE_MODE_M (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S) +#define CACHE_L1_ICACHE0_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE0_FREEZE_MODE_S 1 +/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE0_FREEZE_DONE (BIT(2)) +#define CACHE_L1_ICACHE0_FREEZE_DONE_M (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S) +#define CACHE_L1_ICACHE0_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE0_FREEZE_DONE_S 2 +/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0; + * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by + * software. + */ +#define CACHE_L1_ICACHE1_FREEZE_EN (BIT(4)) +#define CACHE_L1_ICACHE1_FREEZE_EN_M (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S) +#define CACHE_L1_ICACHE1_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_FREEZE_EN_S 4 +/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_ICACHE1_FREEZE_MODE (BIT(5)) +#define CACHE_L1_ICACHE1_FREEZE_MODE_M (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S) +#define CACHE_L1_ICACHE1_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE1_FREEZE_MODE_S 5 +/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE1_FREEZE_DONE (BIT(6)) +#define CACHE_L1_ICACHE1_FREEZE_DONE_M (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S) +#define CACHE_L1_ICACHE1_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE1_FREEZE_DONE_S 6 +/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FREEZE_EN (BIT(8)) +#define CACHE_L1_ICACHE2_FREEZE_EN_M (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S) +#define CACHE_L1_ICACHE2_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_FREEZE_EN_S 8 +/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FREEZE_MODE (BIT(9)) +#define CACHE_L1_ICACHE2_FREEZE_MODE_M (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S) +#define CACHE_L1_ICACHE2_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE2_FREEZE_MODE_S 9 +/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FREEZE_DONE (BIT(10)) +#define CACHE_L1_ICACHE2_FREEZE_DONE_M (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S) +#define CACHE_L1_ICACHE2_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE2_FREEZE_DONE_S 10 +/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FREEZE_EN (BIT(12)) +#define CACHE_L1_ICACHE3_FREEZE_EN_M (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S) +#define CACHE_L1_ICACHE3_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_FREEZE_EN_S 12 +/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FREEZE_MODE (BIT(13)) +#define CACHE_L1_ICACHE3_FREEZE_MODE_M (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S) +#define CACHE_L1_ICACHE3_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE3_FREEZE_MODE_S 13 +/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FREEZE_DONE (BIT(14)) +#define CACHE_L1_ICACHE3_FREEZE_DONE_M (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S) +#define CACHE_L1_ICACHE3_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE3_FREEZE_DONE_S 14 +/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ +#define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) +#define CACHE_L1_CACHE_FREEZE_EN_M (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S) +#define CACHE_L1_CACHE_FREEZE_EN_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_EN_S 16 +/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) +#define CACHE_L1_CACHE_FREEZE_MODE_M (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S) +#define CACHE_L1_CACHE_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_MODE_S 17 +/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) +#define CACHE_L1_CACHE_FREEZE_DONE_M (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S) +#define CACHE_L1_CACHE_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_DONE_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register + * Cache data memory access configure register + */ +#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x2c) +/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN (BIT(0)) +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S 0 +/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, + * 1: enable. + */ +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN (BIT(1)) +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S 1 +/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 0; + * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN (BIT(4)) +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S 4 +/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 0; + * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, + * 1: enable. + */ +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN (BIT(5)) +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S 5 +/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN (BIT(8)) +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S 8 +/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN (BIT(9)) +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S 9 +/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN (BIT(12)) +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S 12 +/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN (BIT(13)) +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S 13 +/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 0; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 0; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 + +/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register + * Cache tag memory access configure register + */ +#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) +/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN (BIT(0)) +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S 0 +/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN (BIT(1)) +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S 1 +/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 0; + * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN (BIT(4)) +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S 4 +/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 0; + * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN (BIT(5)) +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S 5 +/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN (BIT(8)) +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S 8 +/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN (BIT(9)) +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S 9 +/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN (BIT(12)) +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S 12 +/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN (BIT(13)) +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S 13 +/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 0; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 0; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 + +/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register + * L1 instruction Cache 0 prelock configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x34) +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache0 prelock. + */ +#define CACHE_L1_ICACHE0_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOCK_RGID_M (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE0_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 0 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x38) +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 0 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x3c) +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 0 prelock section size configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x40) +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register + * L1 instruction Cache 1 prelock configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x44) +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache1 prelock. + */ +#define CACHE_L1_ICACHE1_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOCK_RGID_M (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE1_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 1 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x48) +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 1 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x4c) +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 1 prelock section size configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x50) +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register + * L1 instruction Cache 2 prelock configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x54) +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache2 prelock. + */ +#define CACHE_L1_ICACHE2_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOCK_RGID_M (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE2_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 2 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x58) +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 2 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x5c) +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 2 prelock section size configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x60) +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register + * L1 instruction Cache 3 prelock configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x64) +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache3 prelock. + */ +#define CACHE_L1_ICACHE3_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOCK_RGID_M (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE3_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 3 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x68) +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 3 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x6c) +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 3 prelock section size configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x70) +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_CACHE_PRELOCK_CONF_REG register + * L1 Cache prelock configure register + */ +#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x74) +/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ +#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_M (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S) +#define CACHE_L1_CACHE_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 + +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register + * L1 Cache prelock section0 address configure register + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x78) +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register + * L1 Cache prelock section1 address configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) +/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register + * L1 Cache prelock section size configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80) +/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_LOCK_CTRL_REG register + * Lock-class (manual lock) operation control register + */ +#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x84) +/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ +#define CACHE_LOCK_ENA (BIT(0)) +#define CACHE_LOCK_ENA_M (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S) +#define CACHE_LOCK_ENA_V 0x00000001U +#define CACHE_LOCK_ENA_S 0 +/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ +#define CACHE_UNLOCK_ENA (BIT(1)) +#define CACHE_UNLOCK_ENA_M (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S) +#define CACHE_UNLOCK_ENA_V 0x00000001U +#define CACHE_UNLOCK_ENA_S 1 +/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ +#define CACHE_LOCK_DONE (BIT(2)) +#define CACHE_LOCK_DONE_M (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S) +#define CACHE_LOCK_DONE_V 0x00000001U +#define CACHE_LOCK_DONE_S 2 +/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ +#define CACHE_LOCK_RGID 0x0000000FU +#define CACHE_LOCK_RGID_M (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S) +#define CACHE_LOCK_RGID_V 0x0000000FU +#define CACHE_LOCK_RGID_S 3 + +/** CACHE_LOCK_MAP_REG register + * Lock (manual lock) map configure register + */ +#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x88) +/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ +#define CACHE_LOCK_MAP 0x0000003FU +#define CACHE_LOCK_MAP_M (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S) +#define CACHE_LOCK_MAP_V 0x0000003FU +#define CACHE_LOCK_MAP_S 0 + +/** CACHE_LOCK_ADDR_REG register + * Lock (manual lock) address configure register + */ +#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x8c) +/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the lock/unlock operation, + * which should be used together with CACHE_LOCK_SIZE_REG + */ +#define CACHE_LOCK_ADDR 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_M (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S) +#define CACHE_LOCK_ADDR_V 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_S 0 + +/** CACHE_LOCK_SIZE_REG register + * Lock (manual lock) size configure register + */ +#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x90) +/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ +#define CACHE_LOCK_SIZE 0x0000FFFFU +#define CACHE_LOCK_SIZE_M (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S) +#define CACHE_LOCK_SIZE_V 0x0000FFFFU +#define CACHE_LOCK_SIZE_S 0 + +/** CACHE_SYNC_CTRL_REG register + * Sync-class operation control register + */ +#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x94) +/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_INVALIDATE_ENA (BIT(0)) +#define CACHE_INVALIDATE_ENA_M (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S) +#define CACHE_INVALIDATE_ENA_V 0x00000001U +#define CACHE_INVALIDATE_ENA_S 0 +/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ +#define CACHE_CLEAN_ENA (BIT(1)) +#define CACHE_CLEAN_ENA_M (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S) +#define CACHE_CLEAN_ENA_V 0x00000001U +#define CACHE_CLEAN_ENA_S 1 +/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_ENA (BIT(2)) +#define CACHE_WRITEBACK_ENA_M (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S) +#define CACHE_WRITEBACK_ENA_V 0x00000001U +#define CACHE_WRITEBACK_ENA_S 2 +/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define CACHE_WRITEBACK_INVALIDATE_ENA_M (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S) +#define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x00000001U +#define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ +#define CACHE_SYNC_DONE (BIT(4)) +#define CACHE_SYNC_DONE_M (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S) +#define CACHE_SYNC_DONE_V 0x00000001U +#define CACHE_SYNC_DONE_S 4 +/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ +#define CACHE_SYNC_RGID 0x0000000FU +#define CACHE_SYNC_RGID_M (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S) +#define CACHE_SYNC_RGID_V 0x0000000FU +#define CACHE_SYNC_RGID_S 5 + +/** CACHE_SYNC_MAP_REG register + * Sync map configure register + */ +#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x98) +/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ +#define CACHE_SYNC_MAP 0x0000003FU +#define CACHE_SYNC_MAP_M (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S) +#define CACHE_SYNC_MAP_V 0x0000003FU +#define CACHE_SYNC_MAP_S 0 + +/** CACHE_SYNC_ADDR_REG register + * Sync address configure register + */ +#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0x9c) +/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the sync operation, which + * should be used together with CACHE_SYNC_SIZE_REG + */ +#define CACHE_SYNC_ADDR 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_M (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S) +#define CACHE_SYNC_ADDR_V 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_S 0 + +/** CACHE_SYNC_SIZE_REG register + * Sync size configure register + */ +#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa0) +/** CACHE_SYNC_SIZE : R/W; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ +#define CACHE_SYNC_SIZE 0x01FFFFFFU +#define CACHE_SYNC_SIZE_M (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S) +#define CACHE_SYNC_SIZE_V 0x01FFFFFFU +#define CACHE_SYNC_SIZE_S 0 + +/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register + * L1 instruction Cache 0 preload-operation control register + */ +#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa4) +/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache0. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE0_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_PRELOAD_ENA_M (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE0_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE0_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE0_PRELOAD_DONE_M (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE0_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE0_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache0 preload. + */ +#define CACHE_L1_ICACHE0_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOAD_RGID_M (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE0_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register + * L1 instruction Cache 0 preload address configure register + */ +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xa8) +/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache0, which + * should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE0_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register + * L1 instruction Cache 0 preload size configure register + */ +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xac) +/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE0_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register + * L1 instruction Cache 1 preload-operation control register + */ +#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb0) +/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache1. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE1_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE1_PRELOAD_ENA_M (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE1_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE1_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE1_PRELOAD_DONE_M (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE1_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE1_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache1 preload. + */ +#define CACHE_L1_ICACHE1_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOAD_RGID_M (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE1_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register + * L1 instruction Cache 1 preload address configure register + */ +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb4) +/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache1, which + * should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE1_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register + * L1 instruction Cache 1 preload size configure register + */ +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb8) +/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE1_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register + * L1 instruction Cache 2 preload-operation control register + */ +#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xbc) +/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache2. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE2_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE2_PRELOAD_ENA_M (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE2_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE2_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE2_PRELOAD_DONE_M (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE2_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE2_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache2 preload. + */ +#define CACHE_L1_ICACHE2_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOAD_RGID_M (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE2_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register + * L1 instruction Cache 2 preload address configure register + */ +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc0) +/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache2, which + * should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE2_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register + * L1 instruction Cache 2 preload size configure register + */ +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc4) +/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE2_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register + * L1 instruction Cache 3 preload-operation control register + */ +#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc8) +/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache3. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE3_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE3_PRELOAD_ENA_M (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE3_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE3_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE3_PRELOAD_DONE_M (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE3_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE3_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache3 preload. + */ +#define CACHE_L1_ICACHE3_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOAD_RGID_M (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE3_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register + * L1 instruction Cache 3 preload address configure register + */ +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xcc) +/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache3, which + * should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE3_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register + * L1 instruction Cache 3 preload size configure register + */ +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd0) +/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE3_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S 0 + +/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register + * L1 Cache preload-operation control register + */ +#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd4) +/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_PRELOAD_ENA_M (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S) +#define CACHE_L1_CACHE_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ENA_S 0 +/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_PRELOAD_DONE_M (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S) +#define CACHE_L1_CACHE_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_DONE_S 1 +/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_PRELOAD_ORDER_M (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S) +#define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 +/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ +#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_M (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S) +#define CACHE_L1_CACHE_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 + +/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register + * L1 Cache preload address configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8) +/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-Cache, which + * should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_M (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S) +#define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register + * L1 Cache preload size configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc) +/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_M (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S) +#define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 0 autoload-operation control register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe0) +/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache0. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache0 autoload. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 0 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe4) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 0 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xe8) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 0 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xec) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 0 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf0) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 1 autoload-operation control register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf4) +/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache1. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache1 autoload. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 1 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xf8) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 1 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xfc) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 1 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x100) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 1 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x104) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 2 autoload-operation control register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x108) +/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache2. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache2 autoload. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 2 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x10c) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 2 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x110) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 2 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x114) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 2 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x118) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 3 autoload-operation control register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x11c) +/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache3. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache3 autoload. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 3 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x120) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 3 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x124) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 3 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x128) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 3 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x12c) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register + * L1 Cache autoload-operation control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x130) +/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_M (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 +/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_M (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 +/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S 10 +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S 11 +/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l1 cache autoload. + */ +#define CACHE_L1_CACHE_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_CACHE_AUTOLOAD_RGID_M (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S) +#define CACHE_L1_CACHE_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_AUTOLOAD_RGID_S 12 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register + * L1 Cache autoload section 0 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x134) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register + * L1 Cache autoload section 0 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x138) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register + * L1 Cache autoload section 1 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x13c) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register + * L1 Cache autoload section 1 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x140) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register + * L1 Cache autoload section 2 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x144) +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the third section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register + * L1 Cache autoload section 2 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x148) +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register + * L1 Cache autoload section 1 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x14c) +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the fourth section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register + * L1 Cache autoload section 1 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x150) +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V 0x01FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S 0 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register + * Cache Access Counter Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x154) +/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_ENA (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_ENA_M (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S) +#define CACHE_L1_IBUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_ENA_S 0 +/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_ENA (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_ENA_M (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S) +#define CACHE_L1_IBUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_ENA_S 1 +/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_OVF_INT_ENA (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_ENA_M (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S) +#define CACHE_L1_IBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_ENA_S 2 +/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_OVF_INT_ENA (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_ENA_M (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S) +#define CACHE_L1_IBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_ENA_S 3 +/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ENA_M (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S) +#define CACHE_L1_BUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ENA_S 4 +/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ENA_M (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S) +#define CACHE_L1_BUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ENA_S 5 +/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_OVF_INT_ENA (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_ENA_M (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S) +#define CACHE_L1_DBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_ENA_S 6 +/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_OVF_INT_ENA (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_ENA_M (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S) +#define CACHE_L1_DBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_ENA_S 7 + +/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register + * Cache Access Counter Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x158) +/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due + * to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_CLR (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_CLR_M (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S) +#define CACHE_L1_IBUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_CLR_S 0 +/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due + * to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_CLR (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_CLR_M (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S) +#define CACHE_L1_IBUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_CLR_S 1 +/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_OVF_INT_CLR (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_CLR_M (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S) +#define CACHE_L1_IBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_CLR_S 2 +/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_OVF_INT_CLR (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_CLR_M (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S) +#define CACHE_L1_IBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_CLR_S 3 +/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_CLR_M (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S) +#define CACHE_L1_BUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_CLR_S 4 +/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_CLR_M (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S) +#define CACHE_L1_BUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_CLR_S 5 +/** CACHE_L1_DBUS2_OVF_INT_CLR : R/W; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_OVF_INT_CLR (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_CLR_M (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S) +#define CACHE_L1_DBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_CLR_S 6 +/** CACHE_L1_DBUS3_OVF_INT_CLR : R/W; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_OVF_INT_CLR (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_CLR_M (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S) +#define CACHE_L1_DBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_CLR_S 7 + +/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register + * Cache Access Counter Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x15c) +/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 + * due to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_RAW (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_RAW_M (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S) +#define CACHE_L1_IBUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_RAW_S 0 +/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 + * due to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_RAW (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_RAW_M (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S) +#define CACHE_L1_IBUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_RAW_S 1 +/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 + * due to bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_OVF_INT_RAW (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_RAW_M (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S) +#define CACHE_L1_IBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_RAW_S 2 +/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 + * due to bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_OVF_INT_RAW (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_RAW_M (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S) +#define CACHE_L1_IBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_RAW_S 3 +/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_RAW_M (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S) +#define CACHE_L1_BUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_RAW_S 4 +/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_RAW_M (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S) +#define CACHE_L1_BUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_RAW_S 5 +/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_OVF_INT_RAW (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_RAW_M (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S) +#define CACHE_L1_DBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_RAW_S 6 +/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_OVF_INT_RAW (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_RAW_M (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S) +#define CACHE_L1_DBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_RAW_S 7 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register + * Cache Access Counter Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x160) +/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_ST (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_ST_M (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S) +#define CACHE_L1_IBUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_ST_S 0 +/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_ST (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_ST_M (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S) +#define CACHE_L1_IBUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_ST_S 1 +/** CACHE_L1_IBUS2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_OVF_INT_ST (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_ST_M (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S) +#define CACHE_L1_IBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_ST_S 2 +/** CACHE_L1_IBUS3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_OVF_INT_ST (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_ST_M (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S) +#define CACHE_L1_IBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_ST_S 3 +/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ST_M (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S) +#define CACHE_L1_BUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ST_S 4 +/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ST_M (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S) +#define CACHE_L1_BUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ST_S 5 +/** CACHE_L1_DBUS2_OVF_INT_ST : RO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_OVF_INT_ST (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_ST_M (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S) +#define CACHE_L1_DBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_ST_S 6 +/** CACHE_L1_DBUS3_OVF_INT_ST : RO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_OVF_INT_ST (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_ST_M (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S) +#define CACHE_L1_DBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_ST_S 7 + +/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register + * Cache Access Fail Configuration register + */ +#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x164) +/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0; + * The bit is used to configure l1 icache0 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE (BIT(0)) +#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S 0 +/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : HRO; bitpos: [1]; default: 0; + * The bit is used to configure l1 icache1 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE (BIT(1)) +#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S 1 +/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : HRO; bitpos: [2]; default: 0; + * The bit is used to configure l1 icache2 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE (BIT(2)) +#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S 2 +/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : HRO; bitpos: [3]; default: 0; + * The bit is used to configure l1 icache3 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE (BIT(3)) +#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S 3 +/** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0; + * The bit is used to configure l1 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE (BIT(4)) +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register + * Cache Access Fail Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168) +/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_ENA (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FAIL_INT_ENA (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FAIL_INT_ENA (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S 3 +/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ENA_M (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S) +#define CACHE_L1_CACHE_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register + * L1-Cache Access Fail Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c) +/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_CLR : WT; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FAIL_INT_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_CLR : WT; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FAIL_INT_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S 3 +/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_CLR_M (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S) +#define CACHE_L1_CACHE_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register + * Cache Access Fail Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170) +/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache0. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_RAW (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache1. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_RAW (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache2. + */ +#define CACHE_L1_ICACHE2_FAIL_INT_RAW (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache3. + */ +#define CACHE_L1_ICACHE3_FAIL_INT_RAW (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S 3 +/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_RAW_M (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S) +#define CACHE_L1_CACHE_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register + * Cache Access Fail Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174) +/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due + * to cpu accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_ST (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_ST_M (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE0_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_ST_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due + * to cpu accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_ST (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_ST_M (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE1_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_ST_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_ST : RO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FAIL_INT_ST (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_ST_M (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE2_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_ST_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_ST : RO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FAIL_INT_ST (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_ST_M (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE3_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_ST_S 3 +/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ST_M (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S) +#define CACHE_L1_CACHE_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ST_S 4 + +/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register + * Cache Access Counter enable and clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178) +/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable ibus0 counter in L1-ICache0. + */ +#define CACHE_L1_IBUS0_CNT_ENA (BIT(0)) +#define CACHE_L1_IBUS0_CNT_ENA_M (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S) +#define CACHE_L1_IBUS0_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS0_CNT_ENA_S 0 +/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable ibus1 counter in L1-ICache1. + */ +#define CACHE_L1_IBUS1_CNT_ENA (BIT(1)) +#define CACHE_L1_IBUS1_CNT_ENA_M (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S) +#define CACHE_L1_IBUS1_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS1_CNT_ENA_S 1 +/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_CNT_ENA (BIT(2)) +#define CACHE_L1_IBUS2_CNT_ENA_M (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S) +#define CACHE_L1_IBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS2_CNT_ENA_S 2 +/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_CNT_ENA (BIT(3)) +#define CACHE_L1_IBUS3_CNT_ENA_M (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S) +#define CACHE_L1_IBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS3_CNT_ENA_S 3 +/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_ENA (BIT(4)) +#define CACHE_L1_BUS0_CNT_ENA_M (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S) +#define CACHE_L1_BUS0_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_CNT_ENA_S 4 +/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_ENA (BIT(5)) +#define CACHE_L1_BUS1_CNT_ENA_M (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S) +#define CACHE_L1_BUS1_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_CNT_ENA_S 5 +/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_CNT_ENA (BIT(6)) +#define CACHE_L1_DBUS2_CNT_ENA_M (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S) +#define CACHE_L1_DBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L1_DBUS2_CNT_ENA_S 6 +/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_CNT_ENA (BIT(7)) +#define CACHE_L1_DBUS3_CNT_ENA_M (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S) +#define CACHE_L1_DBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L1_DBUS3_CNT_ENA_S 7 +/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0; + * The bit is used to clear ibus0 counter in L1-ICache0. + */ +#define CACHE_L1_IBUS0_CNT_CLR (BIT(16)) +#define CACHE_L1_IBUS0_CNT_CLR_M (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S) +#define CACHE_L1_IBUS0_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS0_CNT_CLR_S 16 +/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0; + * The bit is used to clear ibus1 counter in L1-ICache1. + */ +#define CACHE_L1_IBUS1_CNT_CLR (BIT(17)) +#define CACHE_L1_IBUS1_CNT_CLR_M (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S) +#define CACHE_L1_IBUS1_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS1_CNT_CLR_S 17 +/** CACHE_L1_IBUS2_CNT_CLR : WT; bitpos: [18]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_CNT_CLR (BIT(18)) +#define CACHE_L1_IBUS2_CNT_CLR_M (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S) +#define CACHE_L1_IBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS2_CNT_CLR_S 18 +/** CACHE_L1_IBUS3_CNT_CLR : WT; bitpos: [19]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_CNT_CLR (BIT(19)) +#define CACHE_L1_IBUS3_CNT_CLR_M (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S) +#define CACHE_L1_IBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS3_CNT_CLR_S 19 +/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_CLR (BIT(20)) +#define CACHE_L1_BUS0_CNT_CLR_M (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S) +#define CACHE_L1_BUS0_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_CNT_CLR_S 20 +/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_CLR (BIT(21)) +#define CACHE_L1_BUS1_CNT_CLR_M (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S) +#define CACHE_L1_BUS1_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_CNT_CLR_S 21 +/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_CNT_CLR (BIT(22)) +#define CACHE_L1_DBUS2_CNT_CLR_M (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S) +#define CACHE_L1_DBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L1_DBUS2_CNT_CLR_S 22 +/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_CNT_CLR (BIT(23)) +#define CACHE_L1_DBUS3_CNT_CLR_M (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S) +#define CACHE_L1_DBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L1_DBUS3_CNT_CLR_S 23 + +/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register + * L1-ICache bus0 Hit-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c) +/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_HIT_CNT_M (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S) +#define CACHE_L1_IBUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_HIT_CNT_S 0 + +/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register + * L1-ICache bus0 Miss-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180) +/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_MISS_CNT_M (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S) +#define CACHE_L1_IBUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_MISS_CNT_S 0 + +/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register + * L1-ICache bus0 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184) +/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_CONFLICT_CNT_M (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S) +#define CACHE_L1_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register + * L1-ICache bus0 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x188) +/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ +#define CACHE_L1_IBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S) +#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register + * L1-ICache bus1 Hit-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c) +/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_HIT_CNT_M (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S) +#define CACHE_L1_IBUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_HIT_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register + * L1-ICache bus1 Miss-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190) +/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_MISS_CNT_M (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S) +#define CACHE_L1_IBUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_MISS_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register + * L1-ICache bus1 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194) +/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_CONFLICT_CNT_M (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S) +#define CACHE_L1_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register + * L1-ICache bus1 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x198) +/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ +#define CACHE_L1_IBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S) +#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register + * L1-ICache bus2 Hit-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c) +/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_HIT_CNT_M (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S) +#define CACHE_L1_IBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_HIT_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register + * L1-ICache bus2 Miss-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0) +/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_MISS_CNT_M (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S) +#define CACHE_L1_IBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_MISS_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register + * L1-ICache bus2 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4) +/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_CONFLICT_CNT_M (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S) +#define CACHE_L1_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register + * L1-ICache bus2 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1a8) +/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ +#define CACHE_L1_IBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S) +#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register + * L1-ICache bus3 Hit-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac) +/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_HIT_CNT_M (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S) +#define CACHE_L1_IBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_HIT_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register + * L1-ICache bus3 Miss-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0) +/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_MISS_CNT_M (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S) +#define CACHE_L1_IBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_MISS_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register + * L1-ICache bus3 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4) +/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_CONFLICT_CNT_M (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S) +#define CACHE_L1_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register + * L1-ICache bus3 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1b8) +/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ +#define CACHE_L1_IBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S) +#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register + * L1-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc) +/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_M (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S) +#define CACHE_L1_BUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register + * L1-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0) +/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_M (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S) +#define CACHE_L1_BUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register + * L1-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4) +/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_CONFLICT_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S) +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S 0 + +/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register + * L1-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) +/** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_M (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus0 WB-Access Counter register + */ +#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) +/** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_M (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register + * L1-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d0) +/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_M (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S) +#define CACHE_L1_BUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register + * L1-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d4) +/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_M (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S) +#define CACHE_L1_BUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register + * L1-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d8) +/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_M (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S) +#define CACHE_L1_BUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register + * L1-DCache bus1 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1dc) +/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S) +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus1 WB-Access Counter register + */ +#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e0) +/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus1 accesses L1-Cache. + */ +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S) +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register + * L1-DCache bus2 Hit-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4) +/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_HIT_CNT_M (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S) +#define CACHE_L1_DBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_HIT_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register + * L1-DCache bus2 Miss-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e8) +/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_MISS_CNT_M (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S) +#define CACHE_L1_DBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_MISS_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register + * L1-DCache bus2 Conflict-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec) +/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_CONFLICT_CNT_M (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S) +#define CACHE_L1_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register + * L1-DCache bus2 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f0) +/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus2 accessing L1-Cache. + */ +#define CACHE_L1_DBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S) +#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus2 WB-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f4) +/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus2 accesses L1-Cache. + */ +#define CACHE_L1_DBUS2_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S) +#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register + * L1-DCache bus3 Hit-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1f8) +/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_HIT_CNT_M (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S) +#define CACHE_L1_DBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_HIT_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register + * L1-DCache bus3 Miss-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1fc) +/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_MISS_CNT_M (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S) +#define CACHE_L1_DBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_MISS_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register + * L1-DCache bus3 Conflict-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x200) +/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_CONFLICT_CNT_M (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S) +#define CACHE_L1_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register + * L1-DCache bus3 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x204) +/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus3 accessing L1-Cache. + */ +#define CACHE_L1_DBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S) +#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus3 WB-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x208) +/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ +#define CACHE_L1_DBUS3_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S) +#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c) +/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_M (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S) +#define CACHE_L1_ICACHE0_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_S 0 +/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_M (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S) +#define CACHE_L1_ICACHE0_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210) +/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_M (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S) +#define CACHE_L1_ICACHE0_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214) +/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_M (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S) +#define CACHE_L1_ICACHE1_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_S 0 +/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_M (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S) +#define CACHE_L1_ICACHE1_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218) +/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_M (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S) +#define CACHE_L1_ICACHE1_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c) +/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache2 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE2_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ID_M (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S) +#define CACHE_L1_ICACHE2_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ID_S 0 +/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache2 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE2_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ATTR_M (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S) +#define CACHE_L1_ICACHE2_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220) +/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache2 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE2_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_FAIL_ADDR_M (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S) +#define CACHE_L1_ICACHE2_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x224) +/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache3 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE3_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ID_M (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S) +#define CACHE_L1_ICACHE3_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ID_S 0 +/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache3 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE3_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ATTR_M (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S) +#define CACHE_L1_ICACHE3_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x228) +/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache3 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE3_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_FAIL_ADDR_M (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S) +#define CACHE_L1_ICACHE3_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_FAIL_ADDR_S 0 + +/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register + * L1-Cache Access Fail ID/attribution information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c) +/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ID 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_M (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S) +#define CACHE_L1_CACHE_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_S 0 +/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_M (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S) +#define CACHE_L1_CACHE_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_S 16 + +/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register + * L1-Cache Access Fail Address information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230) +/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_M (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S) +#define CACHE_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_S 0 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register + * L1-Cache Access Fail Interrupt enable register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x234) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 +/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ +#define CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define CACHE_SYNC_DONE_INT_ENA_M (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S) +#define CACHE_SYNC_DONE_INT_ENA_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ENA_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation error. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation error. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 +/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define CACHE_SYNC_ERR_INT_ENA_M (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S) +#define CACHE_SYNC_ERR_INT_ENA_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ENA_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register + * Sync Preload operation Interrupt clear register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x238) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 +/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ +#define CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define CACHE_SYNC_DONE_INT_CLR_M (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S) +#define CACHE_SYNC_DONE_INT_CLR_V 0x00000001U +#define CACHE_SYNC_DONE_INT_CLR_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0; + * The bit is used to clear interrupt of L1-ICache0 preload-operation error. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; + * The bit is used to clear interrupt of L1-ICache1 preload-operation error. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 +/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define CACHE_SYNC_ERR_INT_CLR_M (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S) +#define CACHE_SYNC_ERR_INT_CLR_V 0x00000001U +#define CACHE_SYNC_ERR_INT_CLR_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register + * Sync Preload operation Interrupt raw register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x23c) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is + * done. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is + * done. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 +/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define CACHE_SYNC_DONE_INT_RAW_M (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S) +#define CACHE_SYNC_DONE_INT_RAW_V 0x00000001U +#define CACHE_SYNC_DONE_INT_RAW_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation + * error occurs. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation + * error occurs. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 +/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ +#define CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define CACHE_SYNC_ERR_INT_RAW_M (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S) +#define CACHE_SYNC_ERR_INT_RAW_V 0x00000001U +#define CACHE_SYNC_ERR_INT_RAW_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register + * L1-Cache Access Fail Interrupt status register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x240) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 +/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define CACHE_SYNC_DONE_INT_ST_M (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S) +#define CACHE_SYNC_DONE_INT_ST_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ST_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 +/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define CACHE_SYNC_ERR_INT_ST_M (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S) +#define CACHE_SYNC_ERR_INT_ST_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ST_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register + * Cache Sync/Preload Operation exception register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x244) +/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache0. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S 0 +/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache1. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S 2 +/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S 4 +/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S 6 +/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ +#define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_M (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S) +#define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 +/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ +#define CACHE_SYNC_ERR_CODE 0x00000003U +#define CACHE_SYNC_ERR_CODE_M (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S) +#define CACHE_SYNC_ERR_CODE_V 0x00000003U +#define CACHE_SYNC_ERR_CODE_S 12 + +/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register + * Cache Sync Reset control register + */ +#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x248) +/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0; + * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_ICACHE0_SYNC_RST (BIT(0)) +#define CACHE_L1_ICACHE0_SYNC_RST_M (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S) +#define CACHE_L1_ICACHE0_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE0_SYNC_RST_S 0 +/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0; + * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_ICACHE1_SYNC_RST (BIT(1)) +#define CACHE_L1_ICACHE1_SYNC_RST_M (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S) +#define CACHE_L1_ICACHE1_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE1_SYNC_RST_S 1 +/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_SYNC_RST (BIT(2)) +#define CACHE_L1_ICACHE2_SYNC_RST_M (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S) +#define CACHE_L1_ICACHE2_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE2_SYNC_RST_S 2 +/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_SYNC_RST (BIT(3)) +#define CACHE_L1_ICACHE3_SYNC_RST_M (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S) +#define CACHE_L1_ICACHE3_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE3_SYNC_RST_S 3 +/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_CACHE_SYNC_RST (BIT(4)) +#define CACHE_L1_CACHE_SYNC_RST_M (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S) +#define CACHE_L1_CACHE_SYNC_RST_V 0x00000001U +#define CACHE_L1_CACHE_SYNC_RST_S 4 + +/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register + * Cache Preload Reset control register + */ +#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c) +/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0; + * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_ICACHE0_PLD_RST (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_RST_M (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S) +#define CACHE_L1_ICACHE0_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_RST_S 0 +/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0; + * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_ICACHE1_PLD_RST (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_RST_M (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S) +#define CACHE_L1_ICACHE1_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_RST_S 1 +/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_RST (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_RST_M (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S) +#define CACHE_L1_ICACHE2_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_RST_S 2 +/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_RST (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_RST_M (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S) +#define CACHE_L1_ICACHE3_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_RST_S 3 +/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_CACHE_PLD_RST (BIT(4)) +#define CACHE_L1_CACHE_PLD_RST_M (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S) +#define CACHE_L1_CACHE_PLD_RST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_RST_S 4 + +/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register + * Cache Autoload buffer clear control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x250) +/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, + * autoload will not work in L1-ICache0. This bit should not be active when autoload + * works in L1-ICache0. + */ +#define CACHE_L1_ICACHE0_ALD_BUF_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S 0 +/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, + * autoload will not work in L1-ICache1. This bit should not be active when autoload + * works in L1-ICache1. + */ +#define CACHE_L1_ICACHE1_ALD_BUF_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S 1 +/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_ALD_BUF_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S 2 +/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_ALD_BUF_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S 3 +/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ +#define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) +#define CACHE_L1_CACHE_ALD_BUF_CLR_M (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S) +#define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 + +/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register + * Unallocate request buffer clear registers + */ +#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254) +/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache0 where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE0_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 +/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache1 where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE1_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_UNALLOC_CLR_S 1 +/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_UNALLOC_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_UNALLOC_CLR_M (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE2_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_UNALLOC_CLR_S 2 +/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_UNALLOC_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_UNALLOC_CLR_M (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE3_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 +/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) +#define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) +#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 + +/** CACHE_L1_CACHE_OBJECT_CTRL_REG register + * Cache Tag and Data memory Object control register + */ +#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x258) +/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0; + * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_ICACHE0_TAG_OBJECT (BIT(0)) +#define CACHE_L1_ICACHE0_TAG_OBJECT_M (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S) +#define CACHE_L1_ICACHE0_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_OBJECT_S 0 +/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0; + * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_ICACHE1_TAG_OBJECT (BIT(1)) +#define CACHE_L1_ICACHE1_TAG_OBJECT_M (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S) +#define CACHE_L1_ICACHE1_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_OBJECT_S 1 +/** CACHE_L1_ICACHE2_TAG_OBJECT : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_OBJECT (BIT(2)) +#define CACHE_L1_ICACHE2_TAG_OBJECT_M (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S) +#define CACHE_L1_ICACHE2_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_OBJECT_S 2 +/** CACHE_L1_ICACHE3_TAG_OBJECT : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_OBJECT (BIT(3)) +#define CACHE_L1_ICACHE3_TAG_OBJECT_M (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S) +#define CACHE_L1_ICACHE3_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_OBJECT_S 3 +/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) +#define CACHE_L1_CACHE_TAG_OBJECT_M (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S) +#define CACHE_L1_CACHE_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_TAG_OBJECT_S 4 +/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0; + * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ +#define CACHE_L1_ICACHE0_MEM_OBJECT (BIT(6)) +#define CACHE_L1_ICACHE0_MEM_OBJECT_M (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S) +#define CACHE_L1_ICACHE0_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE0_MEM_OBJECT_S 6 +/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0; + * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ +#define CACHE_L1_ICACHE1_MEM_OBJECT (BIT(7)) +#define CACHE_L1_ICACHE1_MEM_OBJECT_M (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S) +#define CACHE_L1_ICACHE1_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE1_MEM_OBJECT_S 7 +/** CACHE_L1_ICACHE2_MEM_OBJECT : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_MEM_OBJECT (BIT(8)) +#define CACHE_L1_ICACHE2_MEM_OBJECT_M (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S) +#define CACHE_L1_ICACHE2_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE2_MEM_OBJECT_S 8 +/** CACHE_L1_ICACHE3_MEM_OBJECT : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_MEM_OBJECT (BIT(9)) +#define CACHE_L1_ICACHE3_MEM_OBJECT_M (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S) +#define CACHE_L1_ICACHE3_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE3_MEM_OBJECT_S 9 +/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) +#define CACHE_L1_CACHE_MEM_OBJECT_M (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S) +#define CACHE_L1_CACHE_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_MEM_OBJECT_S 10 + +/** CACHE_L1_CACHE_WAY_OBJECT_REG register + * Cache Tag and Data memory way register + */ +#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x25c) +/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ +#define CACHE_L1_CACHE_WAY_OBJECT 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_M (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S) +#define CACHE_L1_CACHE_WAY_OBJECT_V 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_S 0 + +/** CACHE_L1_CACHE_ADDR_REG register + * Cache address register + */ +#define CACHE_L1_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x260) +/** CACHE_L1_CACHE_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the address which will decide where inside the specified tag + * memory object will be accessed. + */ +#define CACHE_L1_CACHE_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_ADDR_M (CACHE_L1_CACHE_ADDR_V << CACHE_L1_CACHE_ADDR_S) +#define CACHE_L1_CACHE_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_ADDR_S 0 + +/** CACHE_L1_CACHE_DEBUG_BUS_REG register + * Cache Tag/data memory content register + */ +#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x264) +/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 612; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ +#define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_M (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S) +#define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_S 0 + +/** CACHE_LEVEL_SPLIT0_REG register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x268) +/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 616; + * Reserved + */ +#define CACHE_LEVEL_SPLIT0 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT0_M (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S) +#define CACHE_LEVEL_SPLIT0_V 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT0_S 0 + +/** CACHE_L2_CACHE_CTRL_REG register + * L2 Cache(L2-Cache) control register + */ +#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x26c) +/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + */ +#define CACHE_L2_CACHE_SHUT_DMA (BIT(4)) +#define CACHE_L2_CACHE_SHUT_DMA_M (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S) +#define CACHE_L2_CACHE_SHUT_DMA_V 0x00000001U +#define CACHE_L2_CACHE_SHUT_DMA_S 4 +/** CACHE_L2_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; + * Reserved + */ +#define CACHE_L2_CACHE_UNDEF_OP 0x000000FFU +#define CACHE_L2_CACHE_UNDEF_OP_M (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S) +#define CACHE_L2_CACHE_UNDEF_OP_V 0x000000FFU +#define CACHE_L2_CACHE_UNDEF_OP_S 8 + +/** CACHE_L2_BYPASS_CACHE_CONF_REG register + * Bypass Cache configure register + */ +#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x270) +/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0; + * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L2_CACHE_EN (BIT(5)) +#define CACHE_BYPASS_L2_CACHE_EN_M (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S) +#define CACHE_BYPASS_L2_CACHE_EN_V 0x00000001U +#define CACHE_BYPASS_L2_CACHE_EN_S 5 + +/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register + * L2 Cache CacheSize mode configure register + */ +#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x274) +/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_256 (BIT(0)) +#define CACHE_L2_CACHE_CACHESIZE_256_M (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S) +#define CACHE_L2_CACHE_CACHESIZE_256_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_256_S 0 +/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_512 (BIT(1)) +#define CACHE_L2_CACHE_CACHESIZE_512_M (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S) +#define CACHE_L2_CACHE_CACHESIZE_512_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_512_S 1 +/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_1K (BIT(2)) +#define CACHE_L2_CACHE_CACHESIZE_1K_M (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S) +#define CACHE_L2_CACHE_CACHESIZE_1K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_1K_S 2 +/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_2K (BIT(3)) +#define CACHE_L2_CACHE_CACHESIZE_2K_M (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S) +#define CACHE_L2_CACHE_CACHESIZE_2K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_2K_S 3 +/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_4K (BIT(4)) +#define CACHE_L2_CACHE_CACHESIZE_4K_M (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S) +#define CACHE_L2_CACHE_CACHESIZE_4K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_4K_S 4 +/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_8K (BIT(5)) +#define CACHE_L2_CACHE_CACHESIZE_8K_M (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S) +#define CACHE_L2_CACHE_CACHESIZE_8K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_8K_S 5 +/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_16K (BIT(6)) +#define CACHE_L2_CACHE_CACHESIZE_16K_M (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S) +#define CACHE_L2_CACHE_CACHESIZE_16K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_16K_S 6 +/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_32K (BIT(7)) +#define CACHE_L2_CACHE_CACHESIZE_32K_M (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S) +#define CACHE_L2_CACHE_CACHESIZE_32K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_32K_S 7 +/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_64K (BIT(8)) +#define CACHE_L2_CACHE_CACHESIZE_64K_M (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S) +#define CACHE_L2_CACHE_CACHESIZE_64K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_64K_S 8 +/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_128K (BIT(9)) +#define CACHE_L2_CACHE_CACHESIZE_128K_M (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S) +#define CACHE_L2_CACHE_CACHESIZE_128K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_128K_S 9 +/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_256K (BIT(10)) +#define CACHE_L2_CACHE_CACHESIZE_256K_M (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S) +#define CACHE_L2_CACHE_CACHESIZE_256K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_256K_S 10 +/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_512K (BIT(11)) +#define CACHE_L2_CACHE_CACHESIZE_512K_M (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S) +#define CACHE_L2_CACHE_CACHESIZE_512K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_512K_S 11 +/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_1024K (BIT(12)) +#define CACHE_L2_CACHE_CACHESIZE_1024K_M (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S) +#define CACHE_L2_CACHE_CACHESIZE_1024K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_1024K_S 12 + +/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register + * L2 Cache BlockSize mode configure register + */ +#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278) +/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_8 (BIT(0)) +#define CACHE_L2_CACHE_BLOCKSIZE_8_M (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S) +#define CACHE_L2_CACHE_BLOCKSIZE_8_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_8_S 0 +/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_16 (BIT(1)) +#define CACHE_L2_CACHE_BLOCKSIZE_16_M (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S) +#define CACHE_L2_CACHE_BLOCKSIZE_16_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_16_S 1 +/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_32 (BIT(2)) +#define CACHE_L2_CACHE_BLOCKSIZE_32_M (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S) +#define CACHE_L2_CACHE_BLOCKSIZE_32_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_32_S 2 +/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_64 (BIT(3)) +#define CACHE_L2_CACHE_BLOCKSIZE_64_M (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S) +#define CACHE_L2_CACHE_BLOCKSIZE_64_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_64_S 3 +/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_128 (BIT(4)) +#define CACHE_L2_CACHE_BLOCKSIZE_128_M (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S) +#define CACHE_L2_CACHE_BLOCKSIZE_128_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_128_S 4 +/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_256 (BIT(5)) +#define CACHE_L2_CACHE_BLOCKSIZE_256_M (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S) +#define CACHE_L2_CACHE_BLOCKSIZE_256_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_256_S 5 + +/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x27c) +/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to enable L2-Cache wrap around mode. + */ +#define CACHE_L2_CACHE_WRAP (BIT(5)) +#define CACHE_L2_CACHE_WRAP_M (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S) +#define CACHE_L2_CACHE_WRAP_V 0x00000001U +#define CACHE_L2_CACHE_WRAP_S 5 + +/** CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x280) +/** CACHE_L2_CACHE_MISS_DISABLE_ACCESS : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to disable early restart of L2-Cache + */ +#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS (BIT(5)) +#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_M (CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S) +#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V 0x00000001U +#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S 5 + +/** CACHE_L2_CACHE_FREEZE_CTRL_REG register + * Cache Freeze control register + */ +#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x284) +/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0; + * The bit is used to enable freeze operation on L2-Cache. It can be cleared by + * software. + */ +#define CACHE_L2_CACHE_FREEZE_EN (BIT(20)) +#define CACHE_L2_CACHE_FREEZE_EN_M (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S) +#define CACHE_L2_CACHE_FREEZE_EN_V 0x00000001U +#define CACHE_L2_CACHE_FREEZE_EN_S 20 +/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0; + * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L2_CACHE_FREEZE_MODE (BIT(21)) +#define CACHE_L2_CACHE_FREEZE_MODE_M (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S) +#define CACHE_L2_CACHE_FREEZE_MODE_V 0x00000001U +#define CACHE_L2_CACHE_FREEZE_MODE_S 21 +/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0; + * The bit is used to indicate whether freeze operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L2_CACHE_FREEZE_DONE (BIT(22)) +#define CACHE_L2_CACHE_FREEZE_DONE_M (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S) +#define CACHE_L2_CACHE_FREEZE_DONE_V 0x00000001U +#define CACHE_L2_CACHE_FREEZE_DONE_S 22 + +/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register + * Cache data memory access configure register + */ +#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x288) +/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_DATA_MEM_RD_EN (BIT(20)) +#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S) +#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S 20 +/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_DATA_MEM_WR_EN (BIT(21)) +#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S) +#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S 21 + +/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register + * Cache tag memory access configure register + */ +#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x28c) +/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_TAG_MEM_RD_EN (BIT(20)) +#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S) +#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S 20 +/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_TAG_MEM_WR_EN (BIT(21)) +#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S) +#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S 21 + +/** CACHE_L2_CACHE_PRELOCK_CONF_REG register + * L2 Cache prelock configure register + */ +#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x290) +/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L2-Cache. + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S) +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S 0 +/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L2-Cache. + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S) +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S 1 +/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l2 cache prelock. + */ +#define CACHE_L2_CACHE_PRELOCK_RGID 0x0000000FU +#define CACHE_L2_CACHE_PRELOCK_RGID_M (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S) +#define CACHE_L2_CACHE_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L2_CACHE_PRELOCK_RGID_S 2 + +/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register + * L2 Cache prelock section0 address configure register + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x294) +/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S) +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register + * L2 Cache prelock section1 address configure register + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x298) +/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S) +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register + * L2 Cache prelock section size configure register + */ +#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x29c) +/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S) +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535; + * Those bits are used to configure the size of the second section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S) +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register + * L2 Cache preload-operation control register + */ +#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0) +/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L2-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L2_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L2_CACHE_PRELOAD_ENA_M (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S) +#define CACHE_L2_CACHE_PRELOAD_ENA_V 0x00000001U +#define CACHE_L2_CACHE_PRELOAD_ENA_S 0 +/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L2_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L2_CACHE_PRELOAD_DONE_M (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S) +#define CACHE_L2_CACHE_PRELOAD_DONE_V 0x00000001U +#define CACHE_L2_CACHE_PRELOAD_DONE_S 1 +/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L2_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L2_CACHE_PRELOAD_ORDER_M (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S) +#define CACHE_L2_CACHE_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L2_CACHE_PRELOAD_ORDER_S 2 +/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l2 cache preload. + */ +#define CACHE_L2_CACHE_PRELOAD_RGID 0x0000000FU +#define CACHE_L2_CACHE_PRELOAD_RGID_M (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S) +#define CACHE_L2_CACHE_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L2_CACHE_PRELOAD_RGID_S 3 + +/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register + * L2 Cache preload address configure register + */ +#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4) +/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L2-Cache, which + * should be used together with L2_CACHE_PRELOAD_SIZE_REG + */ +#define CACHE_L2_CACHE_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOAD_ADDR_M (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S) +#define CACHE_L2_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOAD_ADDR_S 0 + +/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register + * L2 Cache preload size configure register + */ +#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8) +/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + */ +#define CACHE_L2_CACHE_PRELOAD_SIZE 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOAD_SIZE_M (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S) +#define CACHE_L2_CACHE_PRELOAD_SIZE_V 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOAD_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register + * L2 Cache autoload-operation control register + */ +#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2ac) +/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, + * 0: disable. + */ +#define CACHE_L2_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L2_CACHE_AUTOLOAD_ENA_M (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_ENA_S 0 +/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L2_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L2_CACHE_AUTOLOAD_DONE_M (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S) +#define CACHE_L2_CACHE_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_DONE_S 1 +/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L2-Cache. 0: + * ascending. 1: descending. + */ +#define CACHE_L2_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S) +#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S 2 +/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S 10 +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S 11 +/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l2 cache autoload. + */ +#define CACHE_L2_CACHE_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L2_CACHE_AUTOLOAD_RGID_M (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S) +#define CACHE_L2_CACHE_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L2_CACHE_AUTOLOAD_RGID_S 12 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register + * L2 Cache autoload section 0 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b0) +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register + * L2 Cache autoload section 0 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2b4) +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register + * L2 Cache autoload section 1 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8) +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register + * L2 Cache autoload section 1 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc) +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register + * L2 Cache autoload section 2 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0) +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the third section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register + * L2 Cache autoload section 2 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4) +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register + * L2 Cache autoload section 3 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8) +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the fourth section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register + * L2 Cache autoload section 3 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc) +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S 0 + +/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register + * Cache Access Counter Interrupt enable register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d0) +/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_IBUS0_OVF_INT_ENA (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_ENA_M (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S) +#define CACHE_L2_IBUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_ENA_S 8 +/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_IBUS1_OVF_INT_ENA (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_ENA_M (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S) +#define CACHE_L2_IBUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_ENA_S 9 +/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_OVF_INT_ENA (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_ENA_M (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S) +#define CACHE_L2_IBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_ENA_S 10 +/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_OVF_INT_ENA (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_ENA_M (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S) +#define CACHE_L2_IBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_ENA_S 11 +/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_DBUS0_OVF_INT_ENA (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_ENA_M (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S) +#define CACHE_L2_DBUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_ENA_S 12 +/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_DBUS1_OVF_INT_ENA (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_ENA_M (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S) +#define CACHE_L2_DBUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_ENA_S 13 +/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_OVF_INT_ENA (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_ENA_M (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S) +#define CACHE_L2_DBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_ENA_S 14 +/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_OVF_INT_ENA (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_ENA_M (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S) +#define CACHE_L2_DBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_ENA_S 15 + +/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register + * Cache Access Counter Interrupt clear register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d4) +/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ +#define CACHE_L2_IBUS0_OVF_INT_CLR (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_CLR_M (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S) +#define CACHE_L2_IBUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_CLR_S 8 +/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ +#define CACHE_L2_IBUS1_OVF_INT_CLR (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_CLR_M (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S) +#define CACHE_L2_IBUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_CLR_S 9 +/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_OVF_INT_CLR (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_CLR_M (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S) +#define CACHE_L2_IBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_CLR_S 10 +/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_OVF_INT_CLR (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_CLR_M (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S) +#define CACHE_L2_IBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_CLR_S 11 +/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ +#define CACHE_L2_DBUS0_OVF_INT_CLR (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_CLR_M (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S) +#define CACHE_L2_DBUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_CLR_S 12 +/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ +#define CACHE_L2_DBUS1_OVF_INT_CLR (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_CLR_M (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S) +#define CACHE_L2_DBUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_CLR_S 13 +/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_OVF_INT_CLR (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_CLR_M (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S) +#define CACHE_L2_DBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_CLR_S 14 +/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_OVF_INT_CLR (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_CLR_M (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S) +#define CACHE_L2_DBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_CLR_S 15 + +/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register + * Cache Access Counter Interrupt raw register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2d8) +/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-ICache0. + */ +#define CACHE_L2_IBUS0_OVF_INT_RAW (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_RAW_M (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S) +#define CACHE_L2_IBUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_RAW_S 8 +/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-ICache1. + */ +#define CACHE_L2_IBUS1_OVF_INT_RAW (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_RAW_M (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S) +#define CACHE_L2_IBUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_RAW_S 9 +/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-ICache2. + */ +#define CACHE_L2_IBUS2_OVF_INT_RAW (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_RAW_M (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S) +#define CACHE_L2_IBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_RAW_S 10 +/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-ICache3. + */ +#define CACHE_L2_IBUS3_OVF_INT_RAW (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_RAW_M (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S) +#define CACHE_L2_IBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_RAW_S 11 +/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-DCache. + */ +#define CACHE_L2_DBUS0_OVF_INT_RAW (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_RAW_M (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S) +#define CACHE_L2_DBUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_RAW_S 12 +/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-DCache. + */ +#define CACHE_L2_DBUS1_OVF_INT_RAW (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_RAW_M (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S) +#define CACHE_L2_DBUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_RAW_S 13 +/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-DCache. + */ +#define CACHE_L2_DBUS2_OVF_INT_RAW (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_RAW_M (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S) +#define CACHE_L2_DBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_RAW_S 14 +/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-DCache. + */ +#define CACHE_L2_DBUS3_OVF_INT_RAW (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_RAW_M (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S) +#define CACHE_L2_DBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_RAW_S 15 + +/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register + * Cache Access Counter Interrupt status register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2dc) +/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_IBUS0_OVF_INT_ST (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_ST_M (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S) +#define CACHE_L2_IBUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_ST_S 8 +/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_IBUS1_OVF_INT_ST (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_ST_M (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S) +#define CACHE_L2_IBUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_ST_S 9 +/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_OVF_INT_ST (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_ST_M (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S) +#define CACHE_L2_IBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_ST_S 10 +/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_OVF_INT_ST (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_ST_M (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S) +#define CACHE_L2_IBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_ST_S 11 +/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_DBUS0_OVF_INT_ST (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_ST_M (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S) +#define CACHE_L2_DBUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_ST_S 12 +/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_DBUS1_OVF_INT_ST (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_ST_M (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S) +#define CACHE_L2_DBUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_ST_S 13 +/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_OVF_INT_ST (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_ST_M (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S) +#define CACHE_L2_DBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_ST_S 14 +/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_OVF_INT_ST (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_ST_M (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S) +#define CACHE_L2_DBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_ST_S 15 + +/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register + * Cache Access Fail Configuration register + */ +#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e0) +/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0; + * The bit is used to configure l2 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE (BIT(0)) +#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S 0 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register + * Cache Access Fail Interrupt enable register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2e4) +/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to + * l1 cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_ENA (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_ENA_M (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S) +#define CACHE_L2_CACHE_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_ENA_S 5 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register + * L1-Cache Access Fail Interrupt clear register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2e8) +/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 + * cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_CLR (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_CLR_M (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S) +#define CACHE_L2_CACHE_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_CLR_S 5 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register + * Cache Access Fail Interrupt raw register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2ec) +/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_RAW (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_RAW_M (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S) +#define CACHE_L2_CACHE_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_RAW_S 5 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register + * Cache Access Fail Interrupt status register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f0) +/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L2-Cache due + * to l1 cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_ST (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_ST_M (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S) +#define CACHE_L2_CACHE_FAIL_INT_ST_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_ST_S 5 + +/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register + * Cache Access Counter enable and clear register + */ +#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2f4) +/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable ibus0 counter in L2-Cache. + */ +#define CACHE_L2_IBUS0_CNT_ENA (BIT(8)) +#define CACHE_L2_IBUS0_CNT_ENA_M (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S) +#define CACHE_L2_IBUS0_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS0_CNT_ENA_S 8 +/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable ibus1 counter in L2-Cache. + */ +#define CACHE_L2_IBUS1_CNT_ENA (BIT(9)) +#define CACHE_L2_IBUS1_CNT_ENA_M (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S) +#define CACHE_L2_IBUS1_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS1_CNT_ENA_S 9 +/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_CNT_ENA (BIT(10)) +#define CACHE_L2_IBUS2_CNT_ENA_M (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S) +#define CACHE_L2_IBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS2_CNT_ENA_S 10 +/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_CNT_ENA (BIT(11)) +#define CACHE_L2_IBUS3_CNT_ENA_M (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S) +#define CACHE_L2_IBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS3_CNT_ENA_S 11 +/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0; + * The bit is used to enable dbus0 counter in L2-Cache. + */ +#define CACHE_L2_DBUS0_CNT_ENA (BIT(12)) +#define CACHE_L2_DBUS0_CNT_ENA_M (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S) +#define CACHE_L2_DBUS0_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS0_CNT_ENA_S 12 +/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0; + * The bit is used to enable dbus1 counter in L2-Cache. + */ +#define CACHE_L2_DBUS1_CNT_ENA (BIT(13)) +#define CACHE_L2_DBUS1_CNT_ENA_M (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S) +#define CACHE_L2_DBUS1_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS1_CNT_ENA_S 13 +/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_CNT_ENA (BIT(14)) +#define CACHE_L2_DBUS2_CNT_ENA_M (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S) +#define CACHE_L2_DBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS2_CNT_ENA_S 14 +/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_CNT_ENA (BIT(15)) +#define CACHE_L2_DBUS3_CNT_ENA_M (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S) +#define CACHE_L2_DBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS3_CNT_ENA_S 15 +/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0; + * The bit is used to clear ibus0 counter in L2-Cache. + */ +#define CACHE_L2_IBUS0_CNT_CLR (BIT(24)) +#define CACHE_L2_IBUS0_CNT_CLR_M (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S) +#define CACHE_L2_IBUS0_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS0_CNT_CLR_S 24 +/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0; + * The bit is used to clear ibus1 counter in L2-Cache. + */ +#define CACHE_L2_IBUS1_CNT_CLR (BIT(25)) +#define CACHE_L2_IBUS1_CNT_CLR_M (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S) +#define CACHE_L2_IBUS1_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS1_CNT_CLR_S 25 +/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_CNT_CLR (BIT(26)) +#define CACHE_L2_IBUS2_CNT_CLR_M (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S) +#define CACHE_L2_IBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS2_CNT_CLR_S 26 +/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_CNT_CLR (BIT(27)) +#define CACHE_L2_IBUS3_CNT_CLR_M (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S) +#define CACHE_L2_IBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS3_CNT_CLR_S 27 +/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0; + * The bit is used to clear dbus0 counter in L2-Cache. + */ +#define CACHE_L2_DBUS0_CNT_CLR (BIT(28)) +#define CACHE_L2_DBUS0_CNT_CLR_M (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S) +#define CACHE_L2_DBUS0_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS0_CNT_CLR_S 28 +/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0; + * The bit is used to clear dbus1 counter in L2-Cache. + */ +#define CACHE_L2_DBUS1_CNT_CLR (BIT(29)) +#define CACHE_L2_DBUS1_CNT_CLR_M (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S) +#define CACHE_L2_DBUS1_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS1_CNT_CLR_S 29 +/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_CNT_CLR (BIT(30)) +#define CACHE_L2_DBUS2_CNT_CLR_M (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S) +#define CACHE_L2_DBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS2_CNT_CLR_S 30 +/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_CNT_CLR (BIT(31)) +#define CACHE_L2_DBUS3_CNT_CLR_M (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S) +#define CACHE_L2_DBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS3_CNT_CLR_S 31 + +/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register + * L2-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8) +/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_HIT_CNT_M (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S) +#define CACHE_L2_IBUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_HIT_CNT_S 0 + +/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register + * L2-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc) +/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_MISS_CNT_M (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S) +#define CACHE_L2_IBUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_MISS_CNT_S 0 + +/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register + * L2-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300) +/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache0 accesses + * L2-Cache due to bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_CONFLICT_CNT_M (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S) +#define CACHE_L2_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x304) +/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S) +#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register + * L2-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308) +/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_HIT_CNT_M (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S) +#define CACHE_L2_IBUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_HIT_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register + * L2-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c) +/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_MISS_CNT_M (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S) +#define CACHE_L2_IBUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_MISS_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register + * L2-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310) +/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache1 accesses + * L2-Cache due to bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_CONFLICT_CNT_M (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S) +#define CACHE_L2_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus1 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x314) +/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S) +#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register + * L2-Cache bus2 Hit-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318) +/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_HIT_CNT_M (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S) +#define CACHE_L2_IBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_HIT_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register + * L2-Cache bus2 Miss-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c) +/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_MISS_CNT_M (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S) +#define CACHE_L2_IBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_MISS_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register + * L2-Cache bus2 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320) +/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache2 accesses + * L2-Cache due to bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_CONFLICT_CNT_M (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S) +#define CACHE_L2_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus2 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x324) +/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S) +#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register + * L2-Cache bus3 Hit-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328) +/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_HIT_CNT_M (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S) +#define CACHE_L2_IBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_HIT_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register + * L2-Cache bus3 Miss-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c) +/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_MISS_CNT_M (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S) +#define CACHE_L2_IBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_MISS_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register + * L2-Cache bus3 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330) +/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache3 accesses + * L2-Cache due to bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_CONFLICT_CNT_M (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S) +#define CACHE_L2_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus3 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x334) +/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S) +#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register + * L2-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338) +/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_HIT_CNT_M (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S) +#define CACHE_L2_DBUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_HIT_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register + * L2-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c) +/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_MISS_CNT_M (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S) +#define CACHE_L2_DBUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_MISS_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register + * L2-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340) +/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_CONFLICT_CNT_M (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S) +#define CACHE_L2_DBUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x344) +/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S) +#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register + * L2-Cache bus0 WB-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x348) +/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S) +#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register + * L2-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x34c) +/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_HIT_CNT_M (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S) +#define CACHE_L2_DBUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_HIT_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register + * L2-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x350) +/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_MISS_CNT_M (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S) +#define CACHE_L2_DBUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_MISS_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register + * L2-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x354) +/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_CONFLICT_CNT_M (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S) +#define CACHE_L2_DBUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus1 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x358) +/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S) +#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register + * L2-Cache bus1 WB-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x35c) +/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S) +#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register + * L2-Cache bus2 Hit-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x360) +/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_HIT_CNT_M (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S) +#define CACHE_L2_DBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_HIT_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register + * L2-Cache bus2 Miss-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x364) +/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_MISS_CNT_M (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S) +#define CACHE_L2_DBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_MISS_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register + * L2-Cache bus2 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x368) +/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_CONFLICT_CNT_M (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S) +#define CACHE_L2_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus2 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x36c) +/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S) +#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register + * L2-Cache bus2 WB-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x370) +/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S) +#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register + * L2-Cache bus3 Hit-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x374) +/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_HIT_CNT_M (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S) +#define CACHE_L2_DBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_HIT_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register + * L2-Cache bus3 Miss-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x378) +/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_MISS_CNT_M (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S) +#define CACHE_L2_DBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_MISS_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register + * L2-Cache bus3 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x37c) +/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_CONFLICT_CNT_M (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S) +#define CACHE_L2_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register + * L2-Cache bus3 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x380) +/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S) +#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register + * L2-Cache bus3 WB-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x384) +/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S) +#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S 0 + +/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register + * L2-Cache Access Fail ID/attribution information register + */ +#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x388) +/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when L1-Cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_ID 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ID_M (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S) +#define CACHE_L2_CACHE_FAIL_ID_V 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ID_S 0 +/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when L1-Cache accesses L2-Cache + * due to cache accessing L1-Cache. + */ +#define CACHE_L2_CACHE_FAIL_ATTR 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ATTR_M (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S) +#define CACHE_L2_CACHE_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ATTR_S 16 + +/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register + * L2-Cache Access Fail Address information register + */ +#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x38c) +/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when L1-Cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_FAIL_ADDR_M (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S) +#define CACHE_L2_CACHE_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_FAIL_ADDR_S 0 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register + * L1-Cache Access Fail Interrupt enable register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x390) +/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation error. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register + * Sync Preload operation Interrupt clear register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x394) +/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation + * is done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0; + * The bit is used to clear interrupt of L2-Cache preload-operation error. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register + * Sync Preload operation Interrupt raw register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x398) +/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is + * done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error + * occurs. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register + * L1-Cache Access Fail Interrupt status register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x39c) +/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L2-Cache + * preload-operation is done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_ST (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0; + * The bit indicates the status of the interrupt of L2-Cache preload-operation error. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_ST (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register + * Cache Sync/Preload Operation exception register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a0) +/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0; + * The value 2 is Only available which means preload size is error in L2-Cache. + */ +#define CACHE_L2_CACHE_PLD_ERR_CODE 0x00000003U +#define CACHE_L2_CACHE_PLD_ERR_CODE_M (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S) +#define CACHE_L2_CACHE_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L2_CACHE_PLD_ERR_CODE_S 10 + +/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register + * Cache Sync Reset control register + */ +#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a4) +/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0; + * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L2_CACHE_SYNC_RST (BIT(5)) +#define CACHE_L2_CACHE_SYNC_RST_M (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S) +#define CACHE_L2_CACHE_SYNC_RST_V 0x00000001U +#define CACHE_L2_CACHE_SYNC_RST_S 5 + +/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register + * Cache Preload Reset control register + */ +#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a8) +/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0; + * set this bit to reset preload-logic inside L2-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L2_CACHE_PLD_RST (BIT(5)) +#define CACHE_L2_CACHE_PLD_RST_M (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S) +#define CACHE_L2_CACHE_PLD_RST_V 0x00000001U +#define CACHE_L2_CACHE_PLD_RST_S 5 + +/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register + * Cache Autoload buffer clear control register + */ +#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac) +/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0; + * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, + * autoload will not work in L2-Cache. This bit should not be active when autoload + * works in L2-Cache. + */ +#define CACHE_L2_CACHE_ALD_BUF_CLR (BIT(5)) +#define CACHE_L2_CACHE_ALD_BUF_CLR_M (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S) +#define CACHE_L2_CACHE_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L2_CACHE_ALD_BUF_CLR_S 5 + +/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register + * Unallocate request buffer clear registers + */ +#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0) +/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0; + * The bit is used to clear the unallocate request buffer of l2 icache where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) +#define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) +#define CACHE_L2_CACHE_UNALLOC_CLR_V 0x00000001U +#define CACHE_L2_CACHE_UNALLOC_CLR_S 5 + +/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register + * L2 cache access attribute control register + */ +#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4) +/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1; + * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and + * non-cacheable. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_CC (BIT(0)) +#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S 0 +/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1; + * Set this bit to force the request to l2 cache with write-back attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of write-back and + * write-through. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_WB (BIT(1)) +#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S 1 +/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1; + * Set this bit to force the request to l2 cache with write-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * write-miss-allocate and write-miss-no-allocate. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA (BIT(2)) +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S 2 +/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1; + * Set this bit to force the request to l2 cache with read-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * read-miss-allocate and read-miss-no-allocate. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA (BIT(3)) +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S 3 + +/** CACHE_L2_CACHE_OBJECT_CTRL_REG register + * Cache Tag and Data memory Object control register + */ +#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3b8) +/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0; + * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L2_CACHE_TAG_OBJECT (BIT(5)) +#define CACHE_L2_CACHE_TAG_OBJECT_M (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S) +#define CACHE_L2_CACHE_TAG_OBJECT_V 0x00000001U +#define CACHE_L2_CACHE_TAG_OBJECT_S 5 +/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0; + * Set this bit to set L2-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L2_CACHE_MEM_OBJECT (BIT(11)) +#define CACHE_L2_CACHE_MEM_OBJECT_M (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S) +#define CACHE_L2_CACHE_MEM_OBJECT_V 0x00000001U +#define CACHE_L2_CACHE_MEM_OBJECT_S 11 + +/** CACHE_L2_CACHE_WAY_OBJECT_REG register + * Cache Tag and Data memory way register + */ +#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3bc) +/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ +#define CACHE_L2_CACHE_WAY_OBJECT 0x00000007U +#define CACHE_L2_CACHE_WAY_OBJECT_M (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S) +#define CACHE_L2_CACHE_WAY_OBJECT_V 0x00000007U +#define CACHE_L2_CACHE_WAY_OBJECT_S 0 + +/** CACHE_L2_CACHE_ADDR_REG register + * Cache address register + */ +#define CACHE_L2_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x3c0) +/** CACHE_L2_CACHE_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits stores the address which will decide where inside the specified tag + * memory object will be accessed. + */ +#define CACHE_L2_CACHE_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_ADDR_M (CACHE_L2_CACHE_ADDR_V << CACHE_L2_CACHE_ADDR_S) +#define CACHE_L2_CACHE_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_ADDR_S 0 + +/** CACHE_L2_CACHE_DEBUG_BUS_REG register + * Cache Tag/data memory content register + */ +#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3c4) +/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 964; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ +#define CACHE_L2_CACHE_DEBUG_BUS 0xFFFFFFFFU +#define CACHE_L2_CACHE_DEBUG_BUS_M (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S) +#define CACHE_L2_CACHE_DEBUG_BUS_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_DEBUG_BUS_S 0 + +/** CACHE_LEVEL_SPLIT1_REG register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3c8) +/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 968; + * Reserved + */ +#define CACHE_LEVEL_SPLIT1 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT1_M (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S) +#define CACHE_LEVEL_SPLIT1_V 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT1_S 0 + +/** CACHE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3cc) +/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 0; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define CACHE_CLK_EN (BIT(0)) +#define CACHE_CLK_EN_M (CACHE_CLK_EN_V << CACHE_CLK_EN_S) +#define CACHE_CLK_EN_V 0x00000001U +#define CACHE_CLK_EN_S 0 + +/** CACHE_TRACE_ENA_REG register + * Clock gate control register + */ +#define CACHE_TRACE_ENA_REG (DR_REG_CACHE_BASE + 0x3d0) +/** CACHE_L1_CACHE_TRACE_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable L1-Cache trace for the performance counter and fail tracer + */ +#define CACHE_L1_CACHE_TRACE_ENA (BIT(0)) +#define CACHE_L1_CACHE_TRACE_ENA_M (CACHE_L1_CACHE_TRACE_ENA_V << CACHE_L1_CACHE_TRACE_ENA_S) +#define CACHE_L1_CACHE_TRACE_ENA_V 0x00000001U +#define CACHE_L1_CACHE_TRACE_ENA_S 0 +/** CACHE_L2_CACHE_TRACE_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable L2-Cache trace for the performance counter and fail tracer + */ +#define CACHE_L2_CACHE_TRACE_ENA (BIT(1)) +#define CACHE_L2_CACHE_TRACE_ENA_M (CACHE_L2_CACHE_TRACE_ENA_V << CACHE_L2_CACHE_TRACE_ENA_S) +#define CACHE_L2_CACHE_TRACE_ENA_V 0x00000001U +#define CACHE_L2_CACHE_TRACE_ENA_S 1 + +/** CACHE_REDUNDANCY_SIG0_REG register + * Cache redundancy signal 0 register + */ +#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3d4) +/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG0 0xFFFFFFFFU +#define CACHE_REDCY_SIG0_M (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S) +#define CACHE_REDCY_SIG0_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG0_S 0 + +/** CACHE_REDUNDANCY_SIG1_REG register + * Cache redundancy signal 1 register + */ +#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3d8) +/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG1 0xFFFFFFFFU +#define CACHE_REDCY_SIG1_M (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S) +#define CACHE_REDCY_SIG1_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG1_S 0 + +/** CACHE_REDUNDANCY_SIG2_REG register + * Cache redundancy signal 2 register + */ +#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3dc) +/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG2 0xFFFFFFFFU +#define CACHE_REDCY_SIG2_M (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S) +#define CACHE_REDCY_SIG2_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG2_S 0 + +/** CACHE_REDUNDANCY_SIG3_REG register + * Cache redundancy signal 3 register + */ +#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3e0) +/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG3 0xFFFFFFFFU +#define CACHE_REDCY_SIG3_M (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S) +#define CACHE_REDCY_SIG3_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG3_S 0 + +/** CACHE_REDUNDANCY_SIG4_REG register + * Cache redundancy signal 0 register + */ +#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3e4) +/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG4 0x0000000FU +#define CACHE_REDCY_SIG4_M (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S) +#define CACHE_REDCY_SIG4_V 0x0000000FU +#define CACHE_REDCY_SIG4_S 0 + +/** CACHE_DATE_REG register + * Version control register + */ +#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) +/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36774432; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define CACHE_DATE 0x0FFFFFFFU +#define CACHE_DATE_M (CACHE_DATE_V << CACHE_DATE_S) +#define CACHE_DATE_V 0x0FFFFFFFU +#define CACHE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/cache_struct.h b/components/soc/esp32c61/include/soc/cache_struct.h new file mode 100644 index 0000000000..37179a0e03 --- /dev/null +++ b/components/soc/esp32c61/include/soc/cache_struct.h @@ -0,0 +1,5761 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of l1_icache_ctrl register + * L1 instruction Cache(L1-ICache) control register + */ +typedef union { + struct { + /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus0:1; + /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus1:1; + /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus2:1; + /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus3:1; + uint32_t reserved_4:4; + /** l1_icache_undef_op : R/W; bitpos: [15:8]; default: 0; + * Reserved + */ + uint32_t l1_icache_undef_op:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l1_icache_ctrl_reg_t; + +/** Type of l1_cache_ctrl register + * L1 data Cache(L1-Cache) control register + */ +typedef union { + struct { + /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus0:1; + /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus1:1; + /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus2:1; + /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus3:1; + /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_dma:1; + uint32_t reserved_5:3; + /** l1_cache_undef_op : R/W; bitpos: [15:8]; default: 0; + * Reserved + */ + uint32_t l1_cache_undef_op:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l1_cache_ctrl_reg_t; + +/** Type of l2_cache_ctrl register + * L2 Cache(L2-Cache) control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + */ + uint32_t l2_cache_shut_dma:1; + uint32_t reserved_5:3; + /** l2_cache_undef_op : R/W; bitpos: [15:8]; default: 0; + * Reserved + */ + uint32_t l2_cache_undef_op:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_ctrl_reg_t; + + +/** Group: Bypass Cache Control and configuration registers */ +/** Type of l1_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache0_en:1; + /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache1_en:1; + /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache2_en:1; + /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache3_en:1; + /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_dcache_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_bypass_cache_conf_reg_t; + +/** Type of l2_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; + * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l2_cache_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_bypass_cache_conf_reg_t; + + +/** Group: Cache Atomic Control and configuration registers */ +/** Type of l1_cache_atomic_conf register + * L1 Cache atomic feature configure register + */ +typedef union { + struct { + /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable atomic feature on L1-Cache when multiple cores access + * L1-Cache. 1: disable, 1: enable. + */ + uint32_t l1_cache_atomic_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cache_l1_cache_atomic_conf_reg_t; + + +/** Group: Cache Mode Control and configuration registers */ +/** Type of l1_icache_cachesize_conf register + * L1 instruction Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_256:1; + /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_512:1; + /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1k:1; + /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2k:1; + /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4k:1; + /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_8k:1; + /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_16k:1; + /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_32k:1; + /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_64k:1; + /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_128k:1; + /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_256k:1; + /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_512k:1; + /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1024k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l1_icache_cachesize_conf_reg_t; + +/** Type of l1_icache_blocksize_conf register + * L1 instruction Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_8:1; + /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_16:1; + /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_32:1; + /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_64:1; + /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_128:1; + /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache_blocksize_conf_reg_t; + +/** Type of l1_cache_cachesize_conf register + * L1 data Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_cache_cachesize_256 : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_256:1; + /** l1_cache_cachesize_512 : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-DCache as 512 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_512:1; + /** l1_cache_cachesize_1k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-DCache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1k:1; + /** l1_cache_cachesize_2k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-DCache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2k:1; + /** l1_cache_cachesize_4k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-DCache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4k:1; + /** l1_cache_cachesize_8k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-DCache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_8k:1; + /** l1_cache_cachesize_16k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-DCache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_16k:1; + /** l1_cache_cachesize_32k : HRO; bitpos: [7]; default: 1; + * The field is used to configure cachesize of L1-DCache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_32k:1; + /** l1_cache_cachesize_64k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-DCache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_64k:1; + /** l1_cache_cachesize_128k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-DCache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_128k:1; + /** l1_cache_cachesize_256k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-DCache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_256k:1; + /** l1_cache_cachesize_512k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-DCache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_512k:1; + /** l1_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-DCache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1024k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l1_cache_cachesize_conf_reg_t; + +/** Type of l1_cache_blocksize_conf register + * L1 data Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_8:1; + /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_16:1; + /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; + * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_32:1; + /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_64:1; + /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_128:1; + /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_blocksize_conf_reg_t; + +/** Type of l2_cache_cachesize_conf register + * L2 Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_256:1; + /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_512:1; + /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1k:1; + /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2k:1; + /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4k:1; + /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_8k:1; + /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_16k:1; + /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_32k:1; + /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_64k:1; + /** l2_cache_cachesize_128k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_128k:1; + /** l2_cache_cachesize_256k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_256k:1; + /** l2_cache_cachesize_512k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_512k:1; + /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1024k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_cachesize_conf_reg_t; + +/** Type of l2_cache_blocksize_conf register + * L2 Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_8:1; + /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_16:1; + /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_32:1; + /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_64:1; + /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_128:1; + /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_blocksize_conf_reg_t; + + +/** Group: Wrap Mode Control and configuration registers */ +/** Type of l1_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to enable L1-ICache0 wrap around mode. + */ + uint32_t l1_icache0_wrap:1; + /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to enable L1-ICache1 wrap around mode. + */ + uint32_t l1_icache1_wrap:1; + /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_wrap:1; + /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_wrap:1; + /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ + uint32_t l1_cache_wrap:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_wrap_around_ctrl_reg_t; + +/** Type of l2_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to enable L2-Cache wrap around mode. + */ + uint32_t l2_cache_wrap:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_wrap_around_ctrl_reg_t; + + +/** Group: Early Restart Control registers */ +/** Type of l1_cache_miss_access_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + /** l1_icache0_miss_disable_access : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to disable early restart of L1-ICache0 + */ + uint32_t l1_icache0_miss_disable_access:1; + /** l1_icache1_miss_disable_access : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to disable early restart of L1-ICache1 + */ + uint32_t l1_icache1_miss_disable_access:1; + /** l1_icache2_miss_disable_access : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_miss_disable_access:1; + /** l1_icache3_miss_disable_access : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_miss_disable_access:1; + /** l1_cache_miss_disable_access : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to disable early restart of L1-DCache + */ + uint32_t l1_cache_miss_disable_access:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_miss_access_ctrl_reg_t; + +/** Type of l2_cache_miss_access_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_miss_disable_access : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to disable early restart of L2-Cache + */ + uint32_t l2_cache_miss_disable_access:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_miss_access_ctrl_reg_t; + + +/** Group: Cache Freeze Control registers */ +/** Type of l1_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by + * software. + */ + uint32_t l1_icache0_freeze_en:1; + /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache0_freeze_mode:1; + /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_freeze_done:1; + uint32_t reserved_3:1; + /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by + * software. + */ + uint32_t l1_icache1_freeze_en:1; + /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache1_freeze_mode:1; + /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_freeze_done:1; + uint32_t reserved_7:1; + /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_en:1; + /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_mode:1; + /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_done:1; + uint32_t reserved_11:1; + /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_en:1; + /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_mode:1; + /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_done:1; + uint32_t reserved_15:1; + /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ + uint32_t l1_cache_freeze_en:1; + /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_cache_freeze_mode:1; + /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_freeze_done:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_freeze_ctrl_reg_t; + +/** Type of l2_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable freeze operation on L2-Cache. It can be cleared by + * software. + */ + uint32_t l2_cache_freeze_en:1; + /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; + * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l2_cache_freeze_mode:1; + /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; + * The bit is used to indicate whether freeze operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_freeze_done:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} cache_l2_cache_freeze_ctrl_reg_t; + + +/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Type of l1_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_data_mem_rd_en:1; + /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache0_data_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_data_mem_rd_en:1; + /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 0; + * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache1_data_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_data_mem_rd_en:1; + /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_data_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t l1_icache3_data_mem_rd_en:1; + /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_data_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_rd_en:1; + /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 0; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_data_mem_acs_conf_reg_t; + +/** Type of l2_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_rd_en:1; + /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} cache_l2_cache_data_mem_acs_conf_reg_t; + + +/** Group: Cache Tag Memory Access Control and Configuration registers */ +/** Type of l1_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_rd_en:1; + /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_rd_en:1; + /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 0; + * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_mem_rd_en:1; + /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_mem_rd_en:1; + /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_rd_en:1; + /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 0; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_tag_mem_acs_conf_reg_t; + +/** Type of l2_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_rd_en:1; + /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} cache_l2_cache_tag_mem_acs_conf_reg_t; + + +/** Group: Prelock Control and configuration registers */ +/** Type of l1_icache0_prelock_conf register + * L1 instruction Cache 0 prelock configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct0_en:1; + /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct1_en:1; + /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache0 prelock. + */ + uint32_t l1_icache0_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache0_prelock_conf_reg_t; + +/** Type of l1_icache0_prelock_sct0_addr register + * L1 instruction Cache 0 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache0_prelock_sct0_addr_reg_t; + +/** Type of l1_icache0_prelock_sct1_addr register + * L1 instruction Cache 0 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache0_prelock_sct1_addr_reg_t; + +/** Type of l1_icache0_prelock_sct_size register + * L1 instruction Cache 0 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache0_prelock_sct_size_reg_t; + +/** Type of l1_icache1_prelock_conf register + * L1 instruction Cache 1 prelock configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct0_en:1; + /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct1_en:1; + /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache1 prelock. + */ + uint32_t l1_icache1_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache1_prelock_conf_reg_t; + +/** Type of l1_icache1_prelock_sct0_addr register + * L1 instruction Cache 1 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache1_prelock_sct0_addr_reg_t; + +/** Type of l1_icache1_prelock_sct1_addr register + * L1 instruction Cache 1 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache1_prelock_sct1_addr_reg_t; + +/** Type of l1_icache1_prelock_sct_size register + * L1 instruction Cache 1 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache1_prelock_sct_size_reg_t; + +/** Type of l1_icache2_prelock_conf register + * L1 instruction Cache 2 prelock configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct0_en:1; + /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct1_en:1; + /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache2 prelock. + */ + uint32_t l1_icache2_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache2_prelock_conf_reg_t; + +/** Type of l1_icache2_prelock_sct0_addr register + * L1 instruction Cache 2 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache2_prelock_sct0_addr_reg_t; + +/** Type of l1_icache2_prelock_sct1_addr register + * L1 instruction Cache 2 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache2_prelock_sct1_addr_reg_t; + +/** Type of l1_icache2_prelock_sct_size register + * L1 instruction Cache 2 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache2_prelock_sct_size_reg_t; + +/** Type of l1_icache3_prelock_conf register + * L1 instruction Cache 3 prelock configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct0_en:1; + /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct1_en:1; + /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache3 prelock. + */ + uint32_t l1_icache3_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache3_prelock_conf_reg_t; + +/** Type of l1_icache3_prelock_sct0_addr register + * L1 instruction Cache 3 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache3_prelock_sct0_addr_reg_t; + +/** Type of l1_icache3_prelock_sct1_addr register + * L1 instruction Cache 3 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache3_prelock_sct1_addr_reg_t; + +/** Type of l1_icache3_prelock_sct_size register + * L1 instruction Cache 3 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache3_prelock_sct_size_reg_t; + +/** Type of l1_cache_prelock_conf register + * L1 Cache prelock configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct0_en:1; + /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct1_en:1; + /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ + uint32_t l1_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_prelock_conf_reg_t; + +/** Type of l1_cache_prelock_sct0_addr register + * L1 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_prelock_sct0_addr_reg_t; + +/** Type of l1_dcache_prelock_sct1_addr register + * L1 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct1_addr_reg_t; + +/** Type of l1_dcache_prelock_sct_size register + * L1 Cache prelock section size configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_cache_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_cache_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct_size_reg_t; + +/** Type of l2_cache_prelock_conf register + * L2 Cache prelock configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct0_en:1; + /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct1_en:1; + /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l2 cache prelock. + */ + uint32_t l2_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_prelock_conf_reg_t; + +/** Type of l2_cache_prelock_sct0_addr register + * L2 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section of prelock + * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l2_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l2_cache_prelock_sct0_addr_reg_t; + +/** Type of l2_cache_prelock_sct1_addr register + * L2 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section of prelock + * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l2_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l2_cache_prelock_sct1_addr_reg_t; + +/** Type of l2_cache_prelock_sct_size register + * L2 Cache prelock section size configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l2_cache_prelock_sct0_size:16; + /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; + * Those bits are used to configure the size of the second section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l2_cache_prelock_sct1_size:16; + }; + uint32_t val; +} cache_l2_cache_prelock_sct_size_reg_t; + + +/** Group: Lock Control and configuration registers */ +/** Type of lock_ctrl register + * Lock-class (manual lock) operation control register + */ +typedef union { + struct { + /** lock_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ + uint32_t lock_ena:1; + /** unlock_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ + uint32_t unlock_ena:1; + /** lock_done : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ + uint32_t lock_done:1; + /** lock_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ + uint32_t lock_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_lock_ctrl_reg_t; + +/** Type of lock_map register + * Lock (manual lock) map configure register + */ +typedef union { + struct { + /** lock_map : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ + uint32_t lock_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_lock_map_reg_t; + +/** Type of lock_addr register + * Lock (manual lock) address configure register + */ +typedef union { + struct { + /** lock_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the lock/unlock operation, + * which should be used together with CACHE_LOCK_SIZE_REG + */ + uint32_t lock_addr:32; + }; + uint32_t val; +} cache_lock_addr_reg_t; + +/** Type of lock_size register + * Lock (manual lock) size configure register + */ +typedef union { + struct { + /** lock_size : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ + uint32_t lock_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_lock_size_reg_t; + + +/** Group: Sync Control and configuration registers */ +/** Type of sync_ctrl register + * Sync-class operation control register + */ +typedef union { + struct { + /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t invalidate_ena:1; + /** clean_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ + uint32_t clean_ena:1; + /** writeback_ena : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_ena:1; + /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_invalidate_ena:1; + /** sync_done : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ + uint32_t sync_done:1; + /** sync_rgid : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ + uint32_t sync_rgid:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} cache_sync_ctrl_reg_t; + +/** Type of sync_map register + * Sync map configure register + */ +typedef union { + struct { + /** sync_map : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ + uint32_t sync_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_sync_map_reg_t; + +/** Type of sync_addr register + * Sync address configure register + */ +typedef union { + struct { + /** sync_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the sync operation, which + * should be used together with CACHE_SYNC_SIZE_REG + */ + uint32_t sync_addr:32; + }; + uint32_t val; +} cache_sync_addr_reg_t; + +/** Type of sync_size register + * Sync size configure register + */ +typedef union { + struct { + /** sync_size : R/W; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ + uint32_t sync_size:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} cache_sync_size_reg_t; + + +/** Group: Preload Control and configuration registers */ +/** Type of l1_icache0_preload_ctrl register + * L1 instruction Cache 0 preload-operation control register + */ +typedef union { + struct { + /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache0. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache0_preload_ena:1; + /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache0_preload_done:1; + /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache0_preload_order:1; + /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache0 preload. + */ + uint32_t l1_icache0_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache0_preload_ctrl_reg_t; + +/** Type of l1_icache0_preload_addr register + * L1 instruction Cache 0 preload address configure register + */ +typedef union { + struct { + /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache0, which + * should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + */ + uint32_t l1_icache0_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache0_preload_addr_reg_t; + +/** Type of l1_icache0_preload_size register + * L1 instruction Cache 0 preload size configure register + */ +typedef union { + struct { + /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + */ + uint32_t l1_icache0_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache0_preload_size_reg_t; + +/** Type of l1_icache1_preload_ctrl register + * L1 instruction Cache 1 preload-operation control register + */ +typedef union { + struct { + /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache1. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache1_preload_ena:1; + /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache1_preload_done:1; + /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache1_preload_order:1; + /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache1 preload. + */ + uint32_t l1_icache1_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache1_preload_ctrl_reg_t; + +/** Type of l1_icache1_preload_addr register + * L1 instruction Cache 1 preload address configure register + */ +typedef union { + struct { + /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache1, which + * should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + */ + uint32_t l1_icache1_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache1_preload_addr_reg_t; + +/** Type of l1_icache1_preload_size register + * L1 instruction Cache 1 preload size configure register + */ +typedef union { + struct { + /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + */ + uint32_t l1_icache1_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache1_preload_size_reg_t; + +/** Type of l1_icache2_preload_ctrl register + * L1 instruction Cache 2 preload-operation control register + */ +typedef union { + struct { + /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache2. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache2_preload_ena:1; + /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache2_preload_done:1; + /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache2_preload_order:1; + /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache2 preload. + */ + uint32_t l1_icache2_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache2_preload_ctrl_reg_t; + +/** Type of l1_icache2_preload_addr register + * L1 instruction Cache 2 preload address configure register + */ +typedef union { + struct { + /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache2, which + * should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + */ + uint32_t l1_icache2_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache2_preload_addr_reg_t; + +/** Type of l1_icache2_preload_size register + * L1 instruction Cache 2 preload size configure register + */ +typedef union { + struct { + /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + */ + uint32_t l1_icache2_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache2_preload_size_reg_t; + +/** Type of l1_icache3_preload_ctrl register + * L1 instruction Cache 3 preload-operation control register + */ +typedef union { + struct { + /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache3. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache3_preload_ena:1; + /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache3_preload_done:1; + /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache3_preload_order:1; + /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache3 preload. + */ + uint32_t l1_icache3_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache3_preload_ctrl_reg_t; + +/** Type of l1_icache3_preload_addr register + * L1 instruction Cache 3 preload address configure register + */ +typedef union { + struct { + /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-ICache3, which + * should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + */ + uint32_t l1_icache3_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache3_preload_addr_reg_t; + +/** Type of l1_icache3_preload_size register + * L1 instruction Cache 3 preload size configure register + */ +typedef union { + struct { + /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + */ + uint32_t l1_icache3_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache3_preload_size_reg_t; + +/** Type of l1_cache_preload_ctrl register + * L1 Cache preload-operation control register + */ +typedef union { + struct { + /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_cache_preload_ena:1; + /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_cache_preload_done:1; + /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_cache_preload_order:1; + /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ + uint32_t l1_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_cache_preload_ctrl_reg_t; + +/** Type of l1_dcache_preload_addr register + * L1 Cache preload address configure register + */ +typedef union { + struct { + /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L1-Cache, which + * should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l1_cache_preload_addr:32; + }; + uint32_t val; +} cache_l1_dcache_preload_addr_reg_t; + +/** Type of l1_dcache_preload_size register + * L1 Cache preload size configure register + */ +typedef union { + struct { + /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l1_cache_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_dcache_preload_size_reg_t; + +/** Type of l2_cache_preload_ctrl register + * L2 Cache preload-operation control register + */ +typedef union { + struct { + /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L2-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l2_cache_preload_ena:1; + /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l2_cache_preload_done:1; + /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l2_cache_preload_order:1; + /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l2 cache preload. + */ + uint32_t l2_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l2_cache_preload_ctrl_reg_t; + +/** Type of l2_cache_preload_addr register + * L2 Cache preload address configure register + */ +typedef union { + struct { + /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of preload on L2-Cache, which + * should be used together with L2_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l2_cache_preload_addr:32; + }; + uint32_t val; +} cache_l2_cache_preload_addr_reg_t; + +/** Type of l2_cache_preload_size register + * L2 Cache preload size configure register + */ +typedef union { + struct { + /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l2_cache_preload_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_preload_size_reg_t; + + +/** Group: Autoload Control and configuration registers */ +/** Type of l1_icache0_autoload_ctrl register + * L1 instruction Cache 0 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, + * 0: disable. + */ + uint32_t l1_icache0_autoload_ena:1; + /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_autoload_done:1; + /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache0_autoload_order:1; + /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache0. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache0_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct0_ena:1; + /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct1_ena:1; + /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache0 autoload. + */ + uint32_t l1_icache0_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache0_autoload_ctrl_reg_t; + +/** Type of l1_icache0_autoload_sct0_addr register + * L1 instruction Cache 0 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct0_addr_reg_t; + +/** Type of l1_icache0_autoload_sct0_size register + * L1 instruction Cache 0 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct0_size_reg_t; + +/** Type of l1_icache0_autoload_sct1_addr register + * L1 instruction Cache 0 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct1_addr_reg_t; + +/** Type of l1_icache0_autoload_sct1_size register + * L1 instruction Cache 0 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct1_size_reg_t; + +/** Type of l1_icache1_autoload_ctrl register + * L1 instruction Cache 1 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, + * 0: disable. + */ + uint32_t l1_icache1_autoload_ena:1; + /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_autoload_done:1; + /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache1_autoload_order:1; + /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache1. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache1_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct0_ena:1; + /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct1_ena:1; + /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache1 autoload. + */ + uint32_t l1_icache1_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache1_autoload_ctrl_reg_t; + +/** Type of l1_icache1_autoload_sct0_addr register + * L1 instruction Cache 1 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct0_addr_reg_t; + +/** Type of l1_icache1_autoload_sct0_size register + * L1 instruction Cache 1 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct0_size_reg_t; + +/** Type of l1_icache1_autoload_sct1_addr register + * L1 instruction Cache 1 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct1_addr_reg_t; + +/** Type of l1_icache1_autoload_sct1_size register + * L1 instruction Cache 1 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct1_size_reg_t; + +/** Type of l1_icache2_autoload_ctrl register + * L1 instruction Cache 2 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, + * 0: disable. + */ + uint32_t l1_icache2_autoload_ena:1; + /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache2_autoload_done:1; + /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache2_autoload_order:1; + /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache2. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache2_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct0_ena:1; + /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct1_ena:1; + /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache2 autoload. + */ + uint32_t l1_icache2_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache2_autoload_ctrl_reg_t; + +/** Type of l1_icache2_autoload_sct0_addr register + * L1 instruction Cache 2 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct0_addr_reg_t; + +/** Type of l1_icache2_autoload_sct0_size register + * L1 instruction Cache 2 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct0_size_reg_t; + +/** Type of l1_icache2_autoload_sct1_addr register + * L1 instruction Cache 2 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct1_addr_reg_t; + +/** Type of l1_icache2_autoload_sct1_size register + * L1 instruction Cache 2 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct1_size_reg_t; + +/** Type of l1_icache3_autoload_ctrl register + * L1 instruction Cache 3 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, + * 0: disable. + */ + uint32_t l1_icache3_autoload_ena:1; + /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache3_autoload_done:1; + /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache3_autoload_order:1; + /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache3. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache3_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct0_ena:1; + /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct1_ena:1; + /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache3 autoload. + */ + uint32_t l1_icache3_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache3_autoload_ctrl_reg_t; + +/** Type of l1_icache3_autoload_sct0_addr register + * L1 instruction Cache 3 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct0_addr_reg_t; + +/** Type of l1_icache3_autoload_sct0_size register + * L1 instruction Cache 3 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct0_size_reg_t; + +/** Type of l1_icache3_autoload_sct1_addr register + * L1 instruction Cache 3 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache3_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct1_addr_reg_t; + +/** Type of l1_icache3_autoload_sct1_size register + * L1 instruction Cache 3 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Reserved + */ + uint32_t l1_icache3_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_ctrl register + * L1 Cache autoload-operation control register + */ +typedef union { + struct { + /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ + uint32_t l1_cache_autoload_ena:1; + /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_autoload_done:1; + /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l1_cache_autoload_order:1; + /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct0_ena:1; + /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct1_ena:1; + /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct2_ena:1; + /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct3_ena:1; + /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l1 cache autoload. + */ + uint32_t l1_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l1_cache_autoload_ctrl_reg_t; + +/** Type of l1_cache_autoload_sct0_addr register + * L1 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_addr_reg_t; + +/** Type of l1_cache_autoload_sct0_size register + * L1 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_size : R/W; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_size:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_size_reg_t; + +/** Type of l1_cache_autoload_sct1_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_addr_reg_t; + +/** Type of l1_cache_autoload_sct1_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_size : R/W; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_size:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_sct2_addr register + * L1 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the third section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct2_addr_reg_t; + +/** Type of l1_cache_autoload_sct2_size register + * L1 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_size : HRO; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_size:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} cache_l1_cache_autoload_sct2_size_reg_t; + +/** Type of l1_cache_autoload_sct3_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the fourth section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct3_addr_reg_t; + +/** Type of l1_cache_autoload_sct3_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_size : HRO; bitpos: [24:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_size:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} cache_l1_cache_autoload_sct3_size_reg_t; + +/** Type of l2_cache_autoload_ctrl register + * L2 Cache autoload-operation control register + */ +typedef union { + struct { + /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, + * 0: disable. + */ + uint32_t l2_cache_autoload_ena:1; + /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_autoload_done:1; + /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L2-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l2_cache_autoload_order:1; + /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l2_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct0_ena:1; + /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct1_ena:1; + /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct2_ena:1; + /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct3_ena:1; + /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l2 cache autoload. + */ + uint32_t l2_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_autoload_ctrl_reg_t; + +/** Type of l2_cache_autoload_sct0_addr register + * L2 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the first section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct0_addr_reg_t; + +/** Type of l2_cache_autoload_sct0_size register + * L2 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct0_size_reg_t; + +/** Type of l2_cache_autoload_sct1_addr register + * L2 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the second section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct1_addr_reg_t; + +/** Type of l2_cache_autoload_sct1_size register + * L2 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct1_size_reg_t; + +/** Type of l2_cache_autoload_sct2_addr register + * L2 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the third section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct2_addr_reg_t; + +/** Type of l2_cache_autoload_sct2_size register + * L2 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct2_size_reg_t; + +/** Type of l2_cache_autoload_sct3_addr register + * L2 Cache autoload section 3 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start address of the fourth section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct3_addr_reg_t; + +/** Type of l2_cache_autoload_sct3_size register + * L2 Cache autoload section 3 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct3_size_reg_t; + + +/** Group: Interrupt registers */ +/** Type of l1_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_ena:1; + /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_ena:1; + /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_ena:1; + /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_ena:1; + /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_ena:1; + /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_ena:1; + /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_ena:1; + /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_ena_reg_t; + +/** Type of l1_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due + * to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_clr:1; + /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due + * to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_clr:1; + /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_clr:1; + /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_clr:1; + /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_clr:1; + /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_clr:1; + /** l1_dbus2_ovf_int_clr : R/W; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_clr:1; + /** l1_dbus3_ovf_int_clr : R/W; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_clr_reg_t; + +/** Type of l1_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 + * due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_raw:1; + /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 + * due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_raw:1; + /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 + * due to bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_ovf_int_raw:1; + /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 + * due to bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_ovf_int_raw:1; + /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_raw:1; + /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_raw:1; + /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_ovf_int_raw:1; + /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_ovf_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_raw_reg_t; + +/** Type of l1_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_st:1; + /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_st:1; + /** l1_ibus2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_st:1; + /** l1_ibus3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_st:1; + /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_st:1; + /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_st:1; + /** l1_dbus2_ovf_int_st : RO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_st:1; + /** l1_dbus3_ovf_int_st : RO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_st_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_ena:1; + /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_ena:1; + /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_ena:1; + /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_ena:1; + /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_ena_reg_t; + +/** Type of l1_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_clr:1; + /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_clr:1; + /** l1_icache2_fail_int_clr : WT; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_clr:1; + /** l1_icache3_fail_int_clr : WT; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_clr:1; + /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_clr_reg_t; + +/** Type of l1_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache0. + */ + uint32_t l1_icache0_fail_int_raw:1; + /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache1. + */ + uint32_t l1_icache1_fail_int_raw:1; + /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache2. + */ + uint32_t l1_icache2_fail_int_raw:1; + /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache3. + */ + uint32_t l1_icache3_fail_int_raw:1; + /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ + uint32_t l1_cache_fail_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_raw_reg_t; + +/** Type of l1_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache0_fail_int_st:1; + /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache1_fail_int_st:1; + /** l1_icache2_fail_int_st : RO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_st:1; + /** l1_icache3_fail_int_st : RO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_st:1; + /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_st_reg_t; + +/** Type of l1_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache0_pld_done_int_ena:1; + /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache1_pld_done_int_ena:1; + /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_ena:1; + /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_ena:1; + /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_cache_pld_done_int_ena:1; + uint32_t reserved_5:1; + /** sync_done_int_ena : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ + uint32_t sync_done_int_ena:1; + /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_ena:1; + /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_ena:1; + /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_ena:1; + /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_ena:1; + /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_ena:1; + uint32_t reserved_12:1; + /** sync_err_int_ena : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_ena_reg_t; + +/** Type of l1_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_clr:1; + /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_clr:1; + /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_clr:1; + /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_clr:1; + /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ + uint32_t l1_cache_pld_done_int_clr:1; + uint32_t reserved_5:1; + /** sync_done_int_clr : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ + uint32_t sync_done_int_clr:1; + /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; + * The bit is used to clear interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_clr:1; + /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_clr:1; + /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_clr:1; + /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_clr:1; + /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_clr:1; + uint32_t reserved_12:1; + /** sync_err_int_clr : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_clr_reg_t; + +/** Type of l1_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is + * done. + */ + uint32_t l1_icache0_pld_done_int_raw:1; + /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is + * done. + */ + uint32_t l1_icache1_pld_done_int_raw:1; + /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_raw:1; + /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_raw:1; + /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ + uint32_t l1_cache_pld_done_int_raw:1; + uint32_t reserved_5:1; + /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ + uint32_t sync_done_int_raw:1; + /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation + * error occurs. + */ + uint32_t l1_icache0_pld_err_int_raw:1; + /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation + * error occurs. + */ + uint32_t l1_icache1_pld_err_int_raw:1; + /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_raw:1; + /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_raw:1; + /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ + uint32_t l1_cache_pld_err_int_raw:1; + uint32_t reserved_12:1; + /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ + uint32_t sync_err_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_raw_reg_t; + +/** Type of l1_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_st:1; + /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_st:1; + /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_st:1; + /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_st:1; + /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ + uint32_t l1_cache_pld_done_int_st:1; + uint32_t reserved_5:1; + /** sync_done_int_st : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ + uint32_t sync_done_int_st:1; + /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_st:1; + /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_st:1; + /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_st:1; + /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_st:1; + /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_st:1; + uint32_t reserved_12:1; + /** sync_err_int_st : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_st_reg_t; + +/** Type of l2_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_ena:1; + /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_ena:1; + /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_ena:1; + /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_ena:1; + /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_ena:1; + /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_ena:1; + /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_ena:1; + /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_ena_reg_t; + +/** Type of l2_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_clr:1; + /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_clr:1; + /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_clr:1; + /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_clr:1; + /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_clr:1; + /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_clr:1; + /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_clr:1; + /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_clr_reg_t; + +/** Type of l2_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-ICache0. + */ + uint32_t l2_ibus0_ovf_int_raw:1; + /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-ICache1. + */ + uint32_t l2_ibus1_ovf_int_raw:1; + /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-ICache2. + */ + uint32_t l2_ibus2_ovf_int_raw:1; + /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-ICache3. + */ + uint32_t l2_ibus3_ovf_int_raw:1; + /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-DCache. + */ + uint32_t l2_dbus0_ovf_int_raw:1; + /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-DCache. + */ + uint32_t l2_dbus1_ovf_int_raw:1; + /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-DCache. + */ + uint32_t l2_dbus2_ovf_int_raw:1; + /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-DCache. + */ + uint32_t l2_dbus3_ovf_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_raw_reg_t; + +/** Type of l2_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_st:1; + /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_st:1; + /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_st:1; + /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_st:1; + /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_st:1; + /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_st:1; + /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_st:1; + /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_st_reg_t; + +/** Type of l2_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to + * l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_ena_reg_t; + +/** Type of l2_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 + * cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_clr_reg_t; + +/** Type of l2_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L2-Cache. + */ + uint32_t l2_cache_fail_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_raw_reg_t; + +/** Type of l2_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L2-Cache due + * to l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_st_reg_t; + +/** Type of l2_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation done. + */ + uint32_t l2_cache_pld_done_int_ena:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_ena:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_ena_reg_t; + +/** Type of l2_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation + * is done. + */ + uint32_t l2_cache_pld_done_int_clr:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_clr:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_clr_reg_t; + +/** Type of l2_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is + * done. + */ + uint32_t l2_cache_pld_done_int_raw:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error + * occurs. + */ + uint32_t l2_cache_pld_err_int_raw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_raw_reg_t; + +/** Type of l2_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L2-Cache + * preload-operation is done. + */ + uint32_t l2_cache_pld_done_int_st:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the status of the interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_st:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_st_reg_t; + + +/** Group: Cache Access Fail Configuration register */ +/** Type of l1_cache_acs_fail_ctrl register + * Cache Access Fail Configuration register + */ +typedef union { + struct { + /** l1_icache0_acs_fail_check_mode : HRO; bitpos: [0]; default: 0; + * The bit is used to configure l1 icache0 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_icache0_acs_fail_check_mode:1; + /** l1_icache1_acs_fail_check_mode : HRO; bitpos: [1]; default: 0; + * The bit is used to configure l1 icache1 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_icache1_acs_fail_check_mode:1; + /** l1_icache2_acs_fail_check_mode : HRO; bitpos: [2]; default: 0; + * The bit is used to configure l1 icache2 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_icache2_acs_fail_check_mode:1; + /** l1_icache3_acs_fail_check_mode : HRO; bitpos: [3]; default: 0; + * The bit is used to configure l1 icache3 access fail check mode. 0: the access fail + * is not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_icache3_acs_fail_check_mode:1; + /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; + * The bit is used to configure l1 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_cache_acs_fail_check_mode:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_ctrl_reg_t; + +/** Type of l2_cache_acs_fail_ctrl register + * Cache Access Fail Configuration register + */ +typedef union { + struct { + /** l2_cache_acs_fail_check_mode : HRO; bitpos: [0]; default: 0; + * The bit is used to configure l2 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l2_cache_acs_fail_check_mode:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cache_l2_cache_acs_fail_ctrl_reg_t; + + +/** Group: Access Statistics registers */ +/** Type of l1_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_ena:1; + /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_ena:1; + /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_ena:1; + /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_ena:1; + /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_ena:1; + /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_ena:1; + /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_ena:1; + /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_ena:1; + uint32_t reserved_8:8; + /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0; + * The bit is used to clear ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_clr:1; + /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0; + * The bit is used to clear ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_clr:1; + /** l1_ibus2_cnt_clr : WT; bitpos: [18]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_clr:1; + /** l1_ibus3_cnt_clr : WT; bitpos: [19]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_clr:1; + /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_clr:1; + /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_clr:1; + /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_clr:1; + /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_clr:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_ctrl_reg_t; + +/** Type of l1_ibus0_acs_hit_cnt register + * L1-ICache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_hit_cnt_reg_t; + +/** Type of l1_ibus0_acs_miss_cnt register + * L1-ICache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_miss_cnt_reg_t; + +/** Type of l1_ibus0_acs_conflict_cnt register + * L1-ICache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register + * L1-ICache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l1_ibus0_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_ibus1_acs_hit_cnt register + * L1-ICache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_hit_cnt_reg_t; + +/** Type of l1_ibus1_acs_miss_cnt register + * L1-ICache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_miss_cnt_reg_t; + +/** Type of l1_ibus1_acs_conflict_cnt register + * L1-ICache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register + * L1-ICache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l1_ibus1_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_ibus2_acs_hit_cnt register + * L1-ICache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_hit_cnt_reg_t; + +/** Type of l1_ibus2_acs_miss_cnt register + * L1-ICache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_miss_cnt_reg_t; + +/** Type of l1_ibus2_acs_conflict_cnt register + * L1-ICache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register + * L1-ICache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l1_ibus2_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_ibus3_acs_hit_cnt register + * L1-ICache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_hit_cnt_reg_t; + +/** Type of l1_ibus3_acs_miss_cnt register + * L1-ICache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_miss_cnt_reg_t; + +/** Type of l1_ibus3_acs_conflict_cnt register + * L1-ICache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register + * L1-ICache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l1_ibus3_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_bus0_acs_hit_cnt register + * L1-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_hit_cnt_reg_t; + +/** Type of l1_bus0_acs_miss_cnt register + * L1-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_miss_cnt_reg_t; + +/** Type of l1_bus0_acs_conflict_cnt register + * L1-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_conflict_rd_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register + * L1-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register + * L1-DCache bus0 WB-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l1_bus1_acs_hit_cnt register + * L1-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_hit_cnt_reg_t; + +/** Type of l1_bus1_acs_miss_cnt register + * L1-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_miss_cnt_reg_t; + +/** Type of l1_bus1_acs_conflict_cnt register + * L1-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register + * L1-DCache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ + uint32_t l1_dbus1_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register + * L1-DCache bus1 WB-Access Counter register + */ +typedef union { + struct { + /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus1 accesses L1-Cache. + */ + uint32_t l1_dbus1_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l1_dbus2_acs_hit_cnt register + * L1-DCache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_hit_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_hit_cnt_reg_t; + +/** Type of l1_dbus2_acs_miss_cnt register + * L1-DCache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_miss_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_miss_cnt_reg_t; + +/** Type of l1_dbus2_acs_conflict_cnt register + * L1-DCache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register + * L1-DCache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus2 accessing L1-Cache. + */ + uint32_t l1_dbus2_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register + * L1-DCache bus2 WB-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus2 accesses L1-Cache. + */ + uint32_t l1_dbus2_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l1_dbus3_acs_hit_cnt register + * L1-DCache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_hit_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_hit_cnt_reg_t; + +/** Type of l1_dbus3_acs_miss_cnt register + * L1-DCache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_miss_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_miss_cnt_reg_t; + +/** Type of l1_dbus3_acs_conflict_cnt register + * L1-DCache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register + * L1-DCache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus3 accessing L1-Cache. + */ + uint32_t l1_dbus3_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register + * L1-DCache bus3 WB-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ + uint32_t l1_dbus3_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l2_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_ena:1; + /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_ena:1; + /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_ena:1; + /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_ena:1; + /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_ena:1; + /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_ena:1; + /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_ena:1; + /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_ena:1; + uint32_t reserved_16:8; + /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; + * The bit is used to clear ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_clr:1; + /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; + * The bit is used to clear ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_clr:1; + /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_clr:1; + /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_clr:1; + /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; + * The bit is used to clear dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_clr:1; + /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; + * The bit is used to clear dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_clr:1; + /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_clr:1; + /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_clr:1; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_ctrl_reg_t; + +/** Type of l2_ibus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_hit_cnt_reg_t; + +/** Type of l2_ibus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_miss_cnt_reg_t; + +/** Type of l2_ibus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache0 accesses + * L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_ibus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_hit_cnt_reg_t; + +/** Type of l2_ibus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_miss_cnt_reg_t; + +/** Type of l2_ibus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache1 accesses + * L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_ibus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_hit_cnt_reg_t; + +/** Type of l2_ibus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_miss_cnt_reg_t; + +/** Type of l2_ibus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache2 accesses + * L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_ibus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_hit_cnt_reg_t; + +/** Type of l2_ibus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_miss_cnt_reg_t; + +/** Type of l2_ibus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache3 accesses + * L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_dbus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_hit_cnt_reg_t; + +/** Type of l2_dbus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_miss_cnt_reg_t; + +/** Type of l2_dbus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register + * L2-Cache bus0 WB-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l2_dbus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_hit_cnt_reg_t; + +/** Type of l2_dbus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_miss_cnt_reg_t; + +/** Type of l2_dbus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register + * L2-Cache bus1 WB-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l2_dbus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_hit_cnt_reg_t; + +/** Type of l2_dbus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_miss_cnt_reg_t; + +/** Type of l2_dbus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register + * L2-Cache bus2 WB-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l2_dbus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_hit_cnt_reg_t; + +/** Type of l2_dbus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_miss_cnt_reg_t; + +/** Type of l2_dbus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register + * L2-Cache bus3 WB-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when L1-DCache accesses L2-Cache due + * to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t; + + +/** Group: Access Fail Debug registers */ +/** Type of l1_icache0_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_id:16; + /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_id_attr_reg_t; + +/** Type of l1_icache0_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_addr_reg_t; + +/** Type of l1_icache1_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_id:16; + /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_id_attr_reg_t; + +/** Type of l1_icache1_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_addr_reg_t; + +/** Type of l1_icache2_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_id:16; + /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache2_acs_fail_id_attr_reg_t; + +/** Type of l1_icache2_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache2_acs_fail_addr_reg_t; + +/** Type of l1_icache3_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_id:16; + /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache3_acs_fail_id_attr_reg_t; + +/** Type of l1_icache3_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache3_acs_fail_addr_reg_t; + +/** Type of l1_dcache_acs_fail_id_attr register + * L1-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_id:16; + /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_attr:16; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_id_attr_reg_t; + +/** Type of l1_dcache_acs_fail_addr register + * L1-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_addr:32; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_addr_reg_t; + +/** Type of l2_cache_acs_fail_id_attr register + * L2-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_id:16; + /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when L1-Cache accesses L2-Cache + * due to cache accessing L1-Cache. + */ + uint32_t l2_cache_fail_attr:16; + }; + uint32_t val; +} cache_l2_cache_acs_fail_id_attr_reg_t; + +/** Type of l2_cache_acs_fail_addr register + * L2-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_addr:32; + }; + uint32_t val; +} cache_l2_cache_acs_fail_addr_reg_t; + + +/** Group: Operation Exception registers */ +/** Type of l1_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache0. + */ + uint32_t l1_icache0_pld_err_code:2; + /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache1. + */ + uint32_t l1_icache1_pld_err_code:2; + /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_code:2; + /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_code:2; + /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ + uint32_t l1_cache_pld_err_code:2; + uint32_t reserved_10:2; + /** sync_err_code : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ + uint32_t sync_err_code:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_exception_reg_t; + +/** Type of l2_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; + * The value 2 is Only available which means preload size is error in L2-Cache. + */ + uint32_t l2_cache_pld_err_code:2; + uint32_t reserved_12:20; + }; + uint32_t val; +} cache_l2_cache_sync_preload_exception_reg_t; + + +/** Group: Sync Reset control and configuration registers */ +/** Type of l1_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache0_sync_rst:1; + /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache1_sync_rst:1; + /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_sync_rst:1; + /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_sync_rst:1; + /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_cache_sync_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_sync_rst_ctrl_reg_t; + +/** Type of l2_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l2_cache_sync_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_sync_rst_ctrl_reg_t; + + +/** Group: Preload Reset control and configuration registers */ +/** Type of l1_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache0_pld_rst:1; + /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache1_pld_rst:1; + /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_rst:1; + /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_rst:1; + /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_cache_pld_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_preload_rst_ctrl_reg_t; + +/** Type of l2_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset preload-logic inside L2-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l2_cache_pld_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_preload_rst_ctrl_reg_t; + + +/** Group: Autoload buffer clear control and configuration registers */ +/** Type of l1_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, + * autoload will not work in L1-ICache0. This bit should not be active when autoload + * works in L1-ICache0. + */ + uint32_t l1_icache0_ald_buf_clr:1; + /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, + * autoload will not work in L1-ICache1. This bit should not be active when autoload + * works in L1-ICache1. + */ + uint32_t l1_icache1_ald_buf_clr:1; + /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_ald_buf_clr:1; + /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_ald_buf_clr:1; + /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ + uint32_t l1_cache_ald_buf_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_autoload_buf_clr_ctrl_reg_t; + +/** Type of l2_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; + * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, + * autoload will not work in L2-Cache. This bit should not be active when autoload + * works in L2-Cache. + */ + uint32_t l2_cache_ald_buf_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_autoload_buf_clr_ctrl_reg_t; + + +/** Group: Unallocate request buffer clear registers */ +/** Type of l1_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache0 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache0_unalloc_clr:1; + /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache1 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache1_unalloc_clr:1; + /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_unalloc_clr:1; + /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_unalloc_clr:1; + /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_cache_unalloc_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_unallocate_buffer_clear_reg_t; + +/** Type of l2_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear the unallocate request buffer of l2 icache where the + * unallocate request is responsed but not completed. + */ + uint32_t l2_cache_unalloc_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_unallocate_buffer_clear_reg_t; + + +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0; + * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache0_tag_object:1; + /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0; + * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache1_tag_object:1; + /** l1_icache2_tag_object : R/W; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_object:1; + /** l1_icache3_tag_object : R/W; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_object:1; + /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_tag_object:1; + uint32_t reserved_5:1; + /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0; + * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache0_mem_object:1; + /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0; + * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache1_mem_object:1; + /** l1_icache2_mem_object : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_mem_object:1; + /** l1_icache3_mem_object : R/W; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache3_mem_object:1; + /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_mem_object:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} cache_l1_cache_object_ctrl_reg_t; + +/** Type of l1_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l1_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} cache_l1_cache_way_object_reg_t; + +/** Type of l1_cache_addr register + * Cache address register + */ +typedef union { + struct { + /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the address which will decide where inside the specified tag + * memory object will be accessed. + */ + uint32_t l1_cache_addr:32; + }; + uint32_t val; +} cache_l1_cache_addr_reg_t; + +/** Type of l1_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 612; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l1_cache_debug_bus:32; + }; + uint32_t val; +} cache_l1_cache_debug_bus_reg_t; + +/** Type of l2_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; + * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_tag_object:1; + uint32_t reserved_6:5; + /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; + * Set this bit to set L2-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_mem_object:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} cache_l2_cache_object_ctrl_reg_t; + +/** Type of l2_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l2_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} cache_l2_cache_way_object_reg_t; + +/** Type of l2_cache_addr register + * Cache address register + */ +typedef union { + struct { + /** l2_cache_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits stores the address which will decide where inside the specified tag + * memory object will be accessed. + */ + uint32_t l2_cache_addr:32; + }; + uint32_t val; +} cache_l2_cache_addr_reg_t; + +/** Type of l2_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 964; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l2_cache_debug_bus:32; + }; + uint32_t val; +} cache_l2_cache_debug_bus_reg_t; + + +/** Group: Split L1 and L2 registers */ +/** Type of level_split0 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split0 : HRO; bitpos: [31:0]; default: 616; + * Reserved + */ + uint32_t level_split0:32; + }; + uint32_t val; +} cache_level_split0_reg_t; + +/** Type of level_split1 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split1 : HRO; bitpos: [31:0]; default: 968; + * Reserved + */ + uint32_t level_split1:32; + }; + uint32_t val; +} cache_level_split1_reg_t; + + +/** Group: L2 cache access attribute control register */ +/** Type of l2_cache_access_attr_ctrl register + * L2 cache access attribute control register + */ +typedef union { + struct { + /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; + * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and + * non-cacheable. + */ + uint32_t l2_cache_access_force_cc:1; + /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; + * Set this bit to force the request to l2 cache with write-back attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of write-back and + * write-through. + */ + uint32_t l2_cache_access_force_wb:1; + /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; + * Set this bit to force the request to l2 cache with write-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * write-miss-allocate and write-miss-no-allocate. + */ + uint32_t l2_cache_access_force_wma:1; + /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; + * Set this bit to force the request to l2 cache with read-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * read-miss-allocate and read-miss-no-allocate. + */ + uint32_t l2_cache_access_force_rma:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} cache_l2_cache_access_attr_ctrl_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cache_clock_gate_reg_t; + + +/** Group: Cache Trace Control register */ +/** Type of trace_ena register + * Clock gate control register + */ +typedef union { + struct { + /** l1_cache_trace_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable L1-Cache trace for the performance counter and fail tracer + */ + uint32_t l1_cache_trace_ena:1; + /** l2_cache_trace_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable L2-Cache trace for the performance counter and fail tracer + */ + uint32_t l2_cache_trace_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cache_trace_ena_reg_t; + + +/** Group: Redundancy register (Prepare for ECO) */ +/** Type of redundancy_sig0 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig0:32; + }; + uint32_t val; +} cache_redundancy_sig0_reg_t; + +/** Type of redundancy_sig1 register + * Cache redundancy signal 1 register + */ +typedef union { + struct { + /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig1:32; + }; + uint32_t val; +} cache_redundancy_sig1_reg_t; + +/** Type of redundancy_sig2 register + * Cache redundancy signal 2 register + */ +typedef union { + struct { + /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig2:32; + }; + uint32_t val; +} cache_redundancy_sig2_reg_t; + +/** Type of redundancy_sig3 register + * Cache redundancy signal 3 register + */ +typedef union { + struct { + /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig3:32; + }; + uint32_t val; +} cache_redundancy_sig3_reg_t; + +/** Type of redundancy_sig4 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** redcy_sig4 : RO; bitpos: [3:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig4:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} cache_redundancy_sig4_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36774432; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_date_reg_t; + + +typedef struct { + volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl; + volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl; + volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; + volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; + volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; + volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; + volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; + volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; + volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; + volatile cache_l1_cache_miss_access_ctrl_reg_t l1_cache_miss_access_ctrl; + volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; + volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; + volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; + volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; + volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; + volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; + volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; + volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; + volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; + volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; + volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; + volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; + volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; + volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; + volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; + volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; + volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; + volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; + volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; + volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; + volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; + volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; + volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile cache_lock_ctrl_reg_t lock_ctrl; + volatile cache_lock_map_reg_t lock_map; + volatile cache_lock_addr_reg_t lock_addr; + volatile cache_lock_size_reg_t lock_size; + volatile cache_sync_ctrl_reg_t sync_ctrl; + volatile cache_sync_map_reg_t sync_map; + volatile cache_sync_addr_reg_t sync_addr; + volatile cache_sync_size_reg_t sync_size; + volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; + volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; + volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size; + volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; + volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; + volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size; + volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; + volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; + volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size; + volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; + volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; + volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size; + volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; + volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; + volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size; + volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; + volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; + volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; + volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; + volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; + volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; + volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; + volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; + volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; + volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; + volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; + volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; + volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; + volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; + volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; + volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; + volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; + volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; + volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; + volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; + volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; + volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; + volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; + volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; + volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; + volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; + volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; + volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; + volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; + volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; + volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; + volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; + volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; + volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl; + volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; + volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; + volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; + volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; + volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; + volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; + volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; + volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; + volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt; + volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; + volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; + volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; + volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt; + volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; + volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; + volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; + volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt; + volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; + volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; + volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; + volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt; + volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; + volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; + volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; + volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt; + volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; + volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; + volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; + volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt; + volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; + volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; + volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; + volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt; + volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; + volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; + volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; + volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt; + volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; + volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; + volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; + volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; + volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; + volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; + volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; + volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; + volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr; + volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; + volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; + volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; + volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st; + volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception; + volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; + volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; + volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; + volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; + volatile cache_l1_cache_way_object_reg_t l1_cache_way_object; + volatile cache_l1_cache_addr_reg_t l1_cache_addr; + volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus; + volatile cache_level_split0_reg_t level_split0; + volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl; + volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; + volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; + volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; + volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; + volatile cache_l2_cache_miss_access_ctrl_reg_t l2_cache_miss_access_ctrl; + volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; + volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; + volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; + volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; + volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; + volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; + volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; + volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; + volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr; + volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size; + volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; + volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; + volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; + volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; + volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; + volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; + volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; + volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; + volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; + volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; + volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; + volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; + volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; + volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl; + volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; + volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; + volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; + volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; + volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; + volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; + volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; + volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; + volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt; + volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; + volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; + volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; + volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt; + volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; + volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; + volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; + volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt; + volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; + volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; + volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; + volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt; + volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; + volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; + volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; + volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt; + volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt; + volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; + volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; + volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; + volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt; + volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt; + volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; + volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; + volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; + volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt; + volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt; + volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; + volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; + volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; + volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt; + volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt; + volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; + volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; + volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; + volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; + volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; + volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; + volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; + volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; + volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; + volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; + volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; + volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; + volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; + volatile cache_l2_cache_way_object_reg_t l2_cache_way_object; + volatile cache_l2_cache_addr_reg_t l2_cache_addr; + volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus; + volatile cache_level_split1_reg_t level_split1; + volatile cache_clock_gate_reg_t clock_gate; + volatile cache_trace_ena_reg_t trace_ena; + volatile cache_redundancy_sig0_reg_t redundancy_sig0; + volatile cache_redundancy_sig1_reg_t redundancy_sig1; + volatile cache_redundancy_sig2_reg_t redundancy_sig2; + volatile cache_redundancy_sig3_reg_t redundancy_sig3; + volatile cache_redundancy_sig4_reg_t redundancy_sig4; + uint32_t reserved_3e8[5]; + volatile cache_date_reg_t date; +} cache_dev_t; + +extern cache_dev_t CACHE_CFG; + +#ifndef __cplusplus +_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/efuse_reg.h b/components/soc/esp32c61/include/soc/efuse_reg.h new file mode 100644 index 0000000000..850733bbd9 --- /dev/null +++ b/components/soc/esp32c61/include/soc/efuse_reg.h @@ -0,0 +1,3949 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_PGM_DATA0_REG register + * Represents pgm_data0 + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA1_REG register + * Represents pgm_data1 + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 + +/** EFUSE_PGM_DATA2_REG register + * Represents pgm_data2 + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 + +/** EFUSE_PGM_DATA3_REG register + * Represents pgm_data3 + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Represents pgm_data4 + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Represents pgm_data5 + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Represents pgm_data6 + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Represents pgm_data7 + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Represents pgm_check_value0 + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Represents pgm_check_value1 + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1th RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Represents pgm_check_value2 + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2th RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_S 0 + +/** EFUSE_RD_WR_DIS0_REG register + * Represents rd_wr_dis + */ +#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled.\\ 1: Disabled\\ 0: Enabled\\ + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_WR_DIS_S 0 + +/** EFUSE_RD_REPEAT_DATA0_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_ICACHE : RO; bitpos: [7]; default: 0; + * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + */ +#define EFUSE_DIS_ICACHE (BIT(7)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 7 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [8]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: + * disabled\\ 0: enabled\\ + */ +#define EFUSE_DIS_USB_JTAG (BIT(8)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 8 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(9)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 9 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [10]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(10)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 10 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [11]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(11)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 11 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [12]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(12)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 12 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [13]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ + * 0: enabled\\ + */ +#define EFUSE_DIS_PAD_JTAG (BIT(13)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 13 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [14]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode).\\ 1: disabled\\ 0: enabled\\ + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(14)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 14 +/** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 15 +/** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 17 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [19]; default: 0; + * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not + * exchanged\\ + */ +#define EFUSE_USB_EXCHG_PINS (BIT(19)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 19 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [20]; default: 0; + * Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not + * functioned\\ + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(20)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 20 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [22:21]; default: 0; + * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original + * threshold configuration value of STG0 *2 \\1: Original threshold configuration + * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: + * Original threshold configuration value of STG0 *16 \\ + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 21 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [25:23]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of + * 1: enabled\\ Even number of 1: disabled\\ + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 23 +/** EFUSE_SECURE_BOOT_KEY_REVOKE_0 : RO; bitpos: [26]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0 (BIT(26)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_M (EFUSE_SECURE_BOOT_KEY_REVOKE_0_V << EFUSE_SECURE_BOOT_KEY_REVOKE_0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_S 26 +/** EFUSE_SECURE_BOOT_KEY_REVOKE_1 : RO; bitpos: [27]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1 (BIT(27)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_M (EFUSE_SECURE_BOOT_KEY_REVOKE_1_V << EFUSE_SECURE_BOOT_KEY_REVOKE_1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_S 27 +/** EFUSE_SECURE_BOOT_KEY_REVOKE_2 : RO; bitpos: [28]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2 (BIT(28)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_M (EFUSE_SECURE_BOOT_KEY_REVOKE_2_V << EFUSE_SECURE_BOOT_KEY_REVOKE_2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_S 28 + +/** EFUSE_RD_REPEAT_DATA1_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 0 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 4 +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_S 8 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 12 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [19:16]; default: 0; + * Represents the purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 16 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [23:20]; default: 0; + * Represents the purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 20 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [25:24]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ +#define EFUSE_SEC_DPA_LEVEL 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) +#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_S 24 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [26]; default: 0; + * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + */ +#define EFUSE_SECURE_BOOT_EN (BIT(26)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 26 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [27]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: + * enabled.\\ 0: disabled\\ + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(27)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 27 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is programmed value. Otherwise, the waiting time is + * 2 times the programmed value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 + +/** EFUSE_RD_REPEAT_DATA2_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: + * Enable\\ + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. + * Disable\\ 0: Enable\\ + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [3]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ + * 1: Disable\\ 0: Enable\\ + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(3)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 3 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [4]; default: 0; + * Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: + * Disable\\ + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(4)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 4 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [6:5]; default: 0; + * Represents the types of UART printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 5 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [7]; default: 0; + * Represents whether ROM code is forced to send a resume commmand during SPI boot. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(7)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 7 +/** EFUSE_SECURE_VERSION : RO; bitpos: [23:8]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 8 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [24]; default: 0; + * Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is + * enable. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(24)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 24 +/** EFUSE_HYS_EN_PAD : RO; bitpos: [25]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: + * enabled\\ 0:disabled\\ + */ +#define EFUSE_HYS_EN_PAD (BIT(25)) +#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) +#define EFUSE_HYS_EN_PAD_V 0x00000001U +#define EFUSE_HYS_EN_PAD_S 25 +/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [26]; default: 0; + * Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: + * Disable\\ + */ +#define EFUSE_XTS_DPA_CLK_ENABLE (BIT(26)) +#define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_S 26 +/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; + * Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: + * Low\\ 0: Decided by register configuration\\ + */ +#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 +/** EFUSE_DIS_WIFI6 : RO; bitpos: [29]; default: 0; + * Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is + * disable\\ 0: WiFi 6 is enabled.\\ + */ +#define EFUSE_DIS_WIFI6 (BIT(29)) +#define EFUSE_DIS_WIFI6_M (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S) +#define EFUSE_DIS_WIFI6_V 0x00000001U +#define EFUSE_DIS_WIFI6_S 29 +/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [30]; default: 0; + * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. + */ +#define EFUSE_ECDSA_DISABLE_P192 (BIT(30)) +#define EFUSE_ECDSA_DISABLE_P192_M (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S) +#define EFUSE_ECDSA_DISABLE_P192_V 0x00000001U +#define EFUSE_ECDSA_DISABLE_P192_S 30 +/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [31]; default: 0; + * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. + * \\ 0: Disable. + */ +#define EFUSE_ECC_FORCE_CONST_TIME (BIT(31)) +#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) +#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_S 31 + +/** EFUSE_RD_REPEAT_DATA3_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_RD_REPEAT_DATA3 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define EFUSE_RD_REPEAT_DATA3 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA3_M (EFUSE_RD_REPEAT_DATA3_V << EFUSE_RD_REPEAT_DATA3_S) +#define EFUSE_RD_REPEAT_DATA3_V 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA3_S 0 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * Represents rd_repeat_data + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define EFUSE_RD_REPEAT_DATA4 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA4_M (EFUSE_RD_REPEAT_DATA4_V << EFUSE_RD_REPEAT_DATA4_S) +#define EFUSE_RD_REPEAT_DATA4_V 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA4_S 0 + +/** EFUSE_RD_MAC_SYS0_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Represents MAC address. Low 32-bit. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU +#define EFUSE_MAC_0_S 0 + +/** EFUSE_RD_MAC_SYS1_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Represents MAC address. High 16-bit. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Represents the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 + +/** EFUSE_RD_MAC_SYS2_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_0 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_S 0 +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_S 14 + +/** EFUSE_RD_MAC_SYS3_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/** EFUSE_RD_MAC_SYS4_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/** EFUSE_RD_MAC_SYS5_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Represents rd_sys_part1_data0 + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Represents rd_sys_part1_data1 + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Represents rd_sys_part1_data2 + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Represents rd_sys_part1_data3 + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Represents rd_sys_part1_data4 + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Represents rd_sys_part1_data5 + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Represents rd_sys_part1_data6 + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Represents rd_sys_part1_data7 + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/** EFUSE_RD_USR_DATA0_REG register + * Represents rd_usr_data0 + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU +#define EFUSE_USR_DATA0_S 0 + +/** EFUSE_RD_USR_DATA1_REG register + * Represents rd_usr_data1 + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU +#define EFUSE_USR_DATA1_S 0 + +/** EFUSE_RD_USR_DATA2_REG register + * Represents rd_usr_data2 + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU +#define EFUSE_USR_DATA2_S 0 + +/** EFUSE_RD_USR_DATA3_REG register + * Represents rd_usr_data3 + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU +#define EFUSE_USR_DATA3_S 0 + +/** EFUSE_RD_USR_DATA4_REG register + * Represents rd_usr_data4 + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU +#define EFUSE_USR_DATA4_S 0 + +/** EFUSE_RD_USR_DATA5_REG register + * Represents rd_usr_data5 + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU +#define EFUSE_USR_DATA5_S 0 + +/** EFUSE_RD_USR_DATA6_REG register + * Represents rd_usr_data6 + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 + +/** EFUSE_RD_USR_DATA7_REG register + * Represents rd_usr_data7 + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Represents rd_key0_data0 + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_S 0 + +/** EFUSE_RD_KEY0_DATA1_REG register + * Represents rd_key0_data1 + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_S 0 + +/** EFUSE_RD_KEY0_DATA2_REG register + * Represents rd_key0_data2 + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_S 0 + +/** EFUSE_RD_KEY0_DATA3_REG register + * Represents rd_key0_data3 + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_S 0 + +/** EFUSE_RD_KEY0_DATA4_REG register + * Represents rd_key0_data4 + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_S 0 + +/** EFUSE_RD_KEY0_DATA5_REG register + * Represents rd_key0_data5 + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_S 0 + +/** EFUSE_RD_KEY0_DATA6_REG register + * Represents rd_key0_data6 + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_S 0 + +/** EFUSE_RD_KEY0_DATA7_REG register + * Represents rd_key0_data7 + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_S 0 + +/** EFUSE_RD_KEY1_DATA0_REG register + * Represents rd_key1_data0 + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_S 0 + +/** EFUSE_RD_KEY1_DATA1_REG register + * Represents rd_key1_data1 + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_S 0 + +/** EFUSE_RD_KEY1_DATA2_REG register + * Represents rd_key1_data2 + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_S 0 + +/** EFUSE_RD_KEY1_DATA3_REG register + * Represents rd_key1_data3 + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_S 0 + +/** EFUSE_RD_KEY1_DATA4_REG register + * Represents rd_key1_data4 + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_S 0 + +/** EFUSE_RD_KEY1_DATA5_REG register + * Represents rd_key1_data5 + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_S 0 + +/** EFUSE_RD_KEY1_DATA6_REG register + * Represents rd_key1_data6 + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_S 0 + +/** EFUSE_RD_KEY1_DATA7_REG register + * Represents rd_key1_data7 + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_S 0 + +/** EFUSE_RD_KEY2_DATA0_REG register + * Represents rd_key2_data0 + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_S 0 + +/** EFUSE_RD_KEY2_DATA1_REG register + * Represents rd_key2_data1 + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_S 0 + +/** EFUSE_RD_KEY2_DATA2_REG register + * Represents rd_key2_data2 + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_S 0 + +/** EFUSE_RD_KEY2_DATA3_REG register + * Represents rd_key2_data3 + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_S 0 + +/** EFUSE_RD_KEY2_DATA4_REG register + * Represents rd_key2_data4 + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_S 0 + +/** EFUSE_RD_KEY2_DATA5_REG register + * Represents rd_key2_data5 + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_S 0 + +/** EFUSE_RD_KEY2_DATA6_REG register + * Represents rd_key2_data6 + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_S 0 + +/** EFUSE_RD_KEY2_DATA7_REG register + * Represents rd_key2_data7 + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_S 0 + +/** EFUSE_RD_KEY3_DATA0_REG register + * Represents rd_key3_data0 + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_S 0 + +/** EFUSE_RD_KEY3_DATA1_REG register + * Represents rd_key3_data1 + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_S 0 + +/** EFUSE_RD_KEY3_DATA2_REG register + * Represents rd_key3_data2 + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_S 0 + +/** EFUSE_RD_KEY3_DATA3_REG register + * Represents rd_key3_data3 + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_S 0 + +/** EFUSE_RD_KEY3_DATA4_REG register + * Represents rd_key3_data4 + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_S 0 + +/** EFUSE_RD_KEY3_DATA5_REG register + * Represents rd_key3_data5 + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_S 0 + +/** EFUSE_RD_KEY3_DATA6_REG register + * Represents rd_key3_data6 + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_S 0 + +/** EFUSE_RD_KEY3_DATA7_REG register + * Represents rd_key3_data7 + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_S 0 + +/** EFUSE_RD_KEY4_DATA0_REG register + * Represents rd_key4_data0 + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_S 0 + +/** EFUSE_RD_KEY4_DATA1_REG register + * Represents rd_key4_data1 + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_S 0 + +/** EFUSE_RD_KEY4_DATA2_REG register + * Represents rd_key4_data2 + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_S 0 + +/** EFUSE_RD_KEY4_DATA3_REG register + * Represents rd_key4_data3 + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_S 0 + +/** EFUSE_RD_KEY4_DATA4_REG register + * Represents rd_key4_data4 + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_S 0 + +/** EFUSE_RD_KEY4_DATA5_REG register + * Represents rd_key4_data5 + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_S 0 + +/** EFUSE_RD_KEY4_DATA6_REG register + * Represents rd_key4_data6 + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_S 0 + +/** EFUSE_RD_KEY4_DATA7_REG register + * Represents rd_key4_data7 + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_S 0 + +/** EFUSE_RD_KEY5_DATA0_REG register + * Represents rd_key5_data0 + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_S 0 + +/** EFUSE_RD_KEY5_DATA1_REG register + * Represents rd_key5_data1 + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_S 0 + +/** EFUSE_RD_KEY5_DATA2_REG register + * Represents rd_key5_data2 + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_S 0 + +/** EFUSE_RD_KEY5_DATA3_REG register + * Represents rd_key5_data3 + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_S 0 + +/** EFUSE_RD_KEY5_DATA4_REG register + * Represents rd_key5_data4 + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_S 0 + +/** EFUSE_RD_KEY5_DATA5_REG register + * Represents rd_key5_data5 + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_S 0 + +/** EFUSE_RD_KEY5_DATA6_REG register + * Represents rd_key5_data6 + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_S 0 + +/** EFUSE_RD_KEY5_DATA7_REG register + * Represents rd_key5_data7 + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_S 0 + +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Represents rd_sys_part2_data0 + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Represents rd_sys_part2_data1 + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Represents rd_sys_part2_data2 + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Represents rd_sys_part2_data3 + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Represents rd_sys_part2_data4 + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Represents rd_sys_part2_data5 + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Represents rd_sys_part2_data6 + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Represents rd_sys_part2_data7 + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/** EFUSE_RD_REPEAT_DATA_ERR0_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Represents the programming error of EFUSE_RD_DIS + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_DIS_ICACHE + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(7)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 7 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [8]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_JTAG + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(8)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 8 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 9 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(10)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 10 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(11)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 11 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(12)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 12 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_DIS_PAD_JTAG + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(13)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 13 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(14)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 14 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [16:15]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 15 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [18:17]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 17 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_USB_EXCHG_PINS + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(19)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 19 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [20]; default: 0; + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(20)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 20 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 21 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [25:23]; default: 0; + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 23 +/** EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_0 + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR (BIT(26)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_S 26 +/** EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_1 + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR (BIT(27)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_S 27 +/** EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR : RO; bitpos: [28]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_2 + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR (BIT(28)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_S 28 + +/** EFUSE_RD_REPEAT_DATA_ERR1_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_0 + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 0 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [7:4]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_1 + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 4 +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [11:8]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_2 + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 8 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [15:12]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_3 + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 12 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [19:16]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_4 + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 16 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [23:20]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_5 + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 20 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [25:24]; default: 0; + * Represents the programming error of EFUSE_SEC_DPA_LEVEL + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 24 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_EN + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(26)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 26 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(27)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 27 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Represents the programming error of EFUSE_FLASH_TPUW + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/** EFUSE_RD_REPEAT_DATA_ERR2_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(3)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 3 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(4)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 4 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [6:5]; default: 0; + * Represents the programming error of EFUSE_UART_PRINT_CONTROL + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 5 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_FORCE_SEND_RESUME + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(7)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 7 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [23:8]; default: 0; + * Represents the programming error of EFUSE_SECURE_VERSION + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 8 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [24]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(24)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 24 +/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_HYS_EN_PAD + */ +#define EFUSE_HYS_EN_PAD_ERR (BIT(25)) +#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) +#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U +#define EFUSE_HYS_EN_PAD_ERR_S 25 +/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE + */ +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR (BIT(26)) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S 26 +/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + */ +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 27 +/** EFUSE_DIS_WIFI6_ERR : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_DIS_WIFI6 + */ +#define EFUSE_DIS_WIFI6_ERR (BIT(29)) +#define EFUSE_DIS_WIFI6_ERR_M (EFUSE_DIS_WIFI6_ERR_V << EFUSE_DIS_WIFI6_ERR_S) +#define EFUSE_DIS_WIFI6_ERR_V 0x00000001U +#define EFUSE_DIS_WIFI6_ERR_S 29 +/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [30]; default: 0; + * Represents the programming error of EFUSE_ECDSA_DISABLE_P192 + */ +#define EFUSE_ECDSA_DISABLE_P192_ERR (BIT(30)) +#define EFUSE_ECDSA_DISABLE_P192_ERR_M (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S) +#define EFUSE_ECDSA_DISABLE_P192_ERR_V 0x00000001U +#define EFUSE_ECDSA_DISABLE_P192_ERR_S 30 +/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + */ +#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(31)) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 31 + +/** EFUSE_RD_REPEAT_DATA_ERR3_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_RD_REPEAT_DATA_ERR3 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define EFUSE_RD_REPEAT_DATA_ERR3 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA_ERR3_M (EFUSE_RD_REPEAT_DATA_ERR3_V << EFUSE_RD_REPEAT_DATA_ERR3_S) +#define EFUSE_RD_REPEAT_DATA_ERR3_V 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA_ERR3_S 0 + +/** EFUSE_RD_REPEAT_DATA_ERR4_REG register + * Represents rd_repeat_data_err + */ +#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +/** EFUSE_RD_REPEAT_DATA_ERR4 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define EFUSE_RD_REPEAT_DATA_ERR4 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA_ERR4_M (EFUSE_RD_REPEAT_DATA_ERR4_V << EFUSE_RD_REPEAT_DATA_ERR4_S) +#define EFUSE_RD_REPEAT_DATA_ERR4_V 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA_ERR4_S 0 + +/** EFUSE_RD_RS_DATA_ERR0_REG register + * Represents rd_rs_data_err + */ +#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) +#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. + */ +#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) +#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_RD_MAC_SYS_FAIL_S 3 +/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data + */ +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. + */ +#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 +/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data + */ +#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) +#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 +/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) +#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_USR_DATA_FAIL_S 11 +/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data + */ +#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 +/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) +#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) +#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY0_DATA_FAIL_S 15 +/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data + */ +#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 +/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) +#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) +#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY1_DATA_FAIL_S 19 +/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data + */ +#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 +/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) +#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) +#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY2_DATA_FAIL_S 23 +/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data + */ +#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 +/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) +#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) +#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY3_DATA_FAIL_S 27 +/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data + */ +#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 +/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) +#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) +#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY4_DATA_FAIL_S 31 + +/** EFUSE_RD_RS_DATA_ERR1_REG register + * Represents rd_rs_data_err + */ +#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) +/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key5_data + */ +#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 +/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) +#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) +#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY5_DATA_FAIL_S 3 +/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data + */ +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. + */ +#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37753088; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 + +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 + +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U +#define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 + +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U +#define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U +#define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U +#define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U +#define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 + +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU +#define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 + +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU +#define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 + +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 + +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ +#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U +#define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 + +/** EFUSE_APB2OTP_WR_DIS_REG register + * eFuse apb2otp block0 data register1. + */ +#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x500) +/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ +#define EFUSE_APB2OTP_BLOCK0_WR_DIS 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S) +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register + * eFuse apb2otp block0 data register2. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x504) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register + * eFuse apb2otp block0 data register3. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x508) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register + * eFuse apb2otp block0 data register4. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x50c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register + * eFuse apb2otp block0 data register5. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x510) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register + * eFuse apb2otp block0 data register6. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x514) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register + * eFuse apb2otp block0 data register7. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x518) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register + * eFuse apb2otp block0 data register8. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x51c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register + * eFuse apb2otp block0 data register9. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x520) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register + * eFuse apb2otp block0 data register10. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x524) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register + * eFuse apb2otp block0 data register11. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x528) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register + * eFuse apb2otp block0 data register12. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x52c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register + * eFuse apb2otp block0 data register13. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x530) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register + * eFuse apb2otp block0 data register14. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x534) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register + * eFuse apb2otp block0 data register15. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x538) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register + * eFuse apb2otp block0 data register16. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x53c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register + * eFuse apb2otp block0 data register17. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x540) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register + * eFuse apb2otp block0 data register18. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x544) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register + * eFuse apb2otp block0 data register19. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x548) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register + * eFuse apb2otp block0 data register20. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x54c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S 0 + +/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register + * eFuse apb2otp block0 data register21. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x550) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S 0 + +/** EFUSE_APB2OTP_BLK1_W1_REG register + * eFuse apb2otp block1 data register1. + */ +#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x554) +/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W1_M (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S) +#define EFUSE_APB2OTP_BLOCK1_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W1_S 0 + +/** EFUSE_APB2OTP_BLK1_W2_REG register + * eFuse apb2otp block1 data register2. + */ +#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x558) +/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W2_M (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S) +#define EFUSE_APB2OTP_BLOCK1_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W2_S 0 + +/** EFUSE_APB2OTP_BLK1_W3_REG register + * eFuse apb2otp block1 data register3. + */ +#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x55c) +/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W3_M (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S) +#define EFUSE_APB2OTP_BLOCK1_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W3_S 0 + +/** EFUSE_APB2OTP_BLK1_W4_REG register + * eFuse apb2otp block1 data register4. + */ +#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x560) +/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W4_M (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S) +#define EFUSE_APB2OTP_BLOCK1_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W4_S 0 + +/** EFUSE_APB2OTP_BLK1_W5_REG register + * eFuse apb2otp block1 data register5. + */ +#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x564) +/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W5_M (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S) +#define EFUSE_APB2OTP_BLOCK1_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W5_S 0 + +/** EFUSE_APB2OTP_BLK1_W6_REG register + * eFuse apb2otp block1 data register6. + */ +#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x568) +/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W6_M (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S) +#define EFUSE_APB2OTP_BLOCK1_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W6_S 0 + +/** EFUSE_APB2OTP_BLK1_W7_REG register + * eFuse apb2otp block1 data register7. + */ +#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x56c) +/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W7_M (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S) +#define EFUSE_APB2OTP_BLOCK1_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W7_S 0 + +/** EFUSE_APB2OTP_BLK1_W8_REG register + * eFuse apb2otp block1 data register8. + */ +#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x570) +/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W8_M (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S) +#define EFUSE_APB2OTP_BLOCK1_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W8_S 0 + +/** EFUSE_APB2OTP_BLK1_W9_REG register + * eFuse apb2otp block1 data register9. + */ +#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x574) +/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W9_M (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S) +#define EFUSE_APB2OTP_BLOCK1_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W9_S 0 + +/** EFUSE_APB2OTP_BLK2_W1_REG register + * eFuse apb2otp block2 data register1. + */ +#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x578) +/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W1_M (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S) +#define EFUSE_APB2OTP_BLOCK2_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W1_S 0 + +/** EFUSE_APB2OTP_BLK2_W2_REG register + * eFuse apb2otp block2 data register2. + */ +#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x57c) +/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W2_M (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S) +#define EFUSE_APB2OTP_BLOCK2_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W2_S 0 + +/** EFUSE_APB2OTP_BLK2_W3_REG register + * eFuse apb2otp block2 data register3. + */ +#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x580) +/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W3_M (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S) +#define EFUSE_APB2OTP_BLOCK2_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W3_S 0 + +/** EFUSE_APB2OTP_BLK2_W4_REG register + * eFuse apb2otp block2 data register4. + */ +#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x584) +/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W4_M (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S) +#define EFUSE_APB2OTP_BLOCK2_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W4_S 0 + +/** EFUSE_APB2OTP_BLK2_W5_REG register + * eFuse apb2otp block2 data register5. + */ +#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x588) +/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W5_M (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S) +#define EFUSE_APB2OTP_BLOCK2_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W5_S 0 + +/** EFUSE_APB2OTP_BLK2_W6_REG register + * eFuse apb2otp block2 data register6. + */ +#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x58c) +/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W6_M (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S) +#define EFUSE_APB2OTP_BLOCK2_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W6_S 0 + +/** EFUSE_APB2OTP_BLK2_W7_REG register + * eFuse apb2otp block2 data register7. + */ +#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x590) +/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W7_M (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S) +#define EFUSE_APB2OTP_BLOCK2_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W7_S 0 + +/** EFUSE_APB2OTP_BLK2_W8_REG register + * eFuse apb2otp block2 data register8. + */ +#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x594) +/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W8_M (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S) +#define EFUSE_APB2OTP_BLOCK2_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W8_S 0 + +/** EFUSE_APB2OTP_BLK2_W9_REG register + * eFuse apb2otp block2 data register9. + */ +#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x598) +/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W9_M (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S) +#define EFUSE_APB2OTP_BLOCK2_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W9_S 0 + +/** EFUSE_APB2OTP_BLK2_W10_REG register + * eFuse apb2otp block2 data register10. + */ +#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x59c) +/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W10_M (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S) +#define EFUSE_APB2OTP_BLOCK2_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W10_S 0 + +/** EFUSE_APB2OTP_BLK2_W11_REG register + * eFuse apb2otp block2 data register11. + */ +#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x5a0) +/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W11_M (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S) +#define EFUSE_APB2OTP_BLOCK2_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W11_S 0 + +/** EFUSE_APB2OTP_BLK3_W1_REG register + * eFuse apb2otp block3 data register1. + */ +#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x5a4) +/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W1_M (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S) +#define EFUSE_APB2OTP_BLOCK3_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W1_S 0 + +/** EFUSE_APB2OTP_BLK3_W2_REG register + * eFuse apb2otp block3 data register2. + */ +#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x5a8) +/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W2_M (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S) +#define EFUSE_APB2OTP_BLOCK3_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W2_S 0 + +/** EFUSE_APB2OTP_BLK3_W3_REG register + * eFuse apb2otp block3 data register3. + */ +#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x5ac) +/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W3_M (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S) +#define EFUSE_APB2OTP_BLOCK3_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W3_S 0 + +/** EFUSE_APB2OTP_BLK3_W4_REG register + * eFuse apb2otp block3 data register4. + */ +#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x5b0) +/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W4_M (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S) +#define EFUSE_APB2OTP_BLOCK3_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W4_S 0 + +/** EFUSE_APB2OTP_BLK3_W5_REG register + * eFuse apb2otp block3 data register5. + */ +#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x5b4) +/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W5_M (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S) +#define EFUSE_APB2OTP_BLOCK3_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W5_S 0 + +/** EFUSE_APB2OTP_BLK3_W6_REG register + * eFuse apb2otp block3 data register6. + */ +#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x5b8) +/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W6_M (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S) +#define EFUSE_APB2OTP_BLOCK3_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W6_S 0 + +/** EFUSE_APB2OTP_BLK3_W7_REG register + * eFuse apb2otp block3 data register7. + */ +#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x5bc) +/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W7_M (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S) +#define EFUSE_APB2OTP_BLOCK3_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W7_S 0 + +/** EFUSE_APB2OTP_BLK3_W8_REG register + * eFuse apb2otp block3 data register8. + */ +#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x5c0) +/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W8_M (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S) +#define EFUSE_APB2OTP_BLOCK3_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W8_S 0 + +/** EFUSE_APB2OTP_BLK3_W9_REG register + * eFuse apb2otp block3 data register9. + */ +#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x5c4) +/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W9_M (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S) +#define EFUSE_APB2OTP_BLOCK3_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W9_S 0 + +/** EFUSE_APB2OTP_BLK3_W10_REG register + * eFuse apb2otp block3 data register10. + */ +#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x5c8) +/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W10_M (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S) +#define EFUSE_APB2OTP_BLOCK3_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W10_S 0 + +/** EFUSE_APB2OTP_BLK3_W11_REG register + * eFuse apb2otp block3 data register11. + */ +#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x5cc) +/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W11_M (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S) +#define EFUSE_APB2OTP_BLOCK3_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W11_S 0 + +/** EFUSE_APB2OTP_BLK4_W1_REG register + * eFuse apb2otp BLOCK7 data register1. + */ +#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x5d0) +/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W1_M (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S) +#define EFUSE_APB2OTP_BLOCK4_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W1_S 0 + +/** EFUSE_APB2OTP_BLK4_W2_REG register + * eFuse apb2otp block4 data register2. + */ +#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x5d4) +/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W2_M (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S) +#define EFUSE_APB2OTP_BLOCK4_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W2_S 0 + +/** EFUSE_APB2OTP_BLK4_W3_REG register + * eFuse apb2otp block4 data register3. + */ +#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x5d8) +/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W3_M (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S) +#define EFUSE_APB2OTP_BLOCK4_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W3_S 0 + +/** EFUSE_APB2OTP_BLK4_W4_REG register + * eFuse apb2otp block4 data register4. + */ +#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x5dc) +/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W4_M (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S) +#define EFUSE_APB2OTP_BLOCK4_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W4_S 0 + +/** EFUSE_APB2OTP_BLK4_W5_REG register + * eFuse apb2otp block4 data register5. + */ +#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x5e0) +/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W5_M (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S) +#define EFUSE_APB2OTP_BLOCK4_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W5_S 0 + +/** EFUSE_APB2OTP_BLK4_W6_REG register + * eFuse apb2otp block4 data register6. + */ +#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x5e4) +/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W6_M (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S) +#define EFUSE_APB2OTP_BLOCK4_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W6_S 0 + +/** EFUSE_APB2OTP_BLK4_W7_REG register + * eFuse apb2otp block4 data register7. + */ +#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x5e8) +/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W7_M (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S) +#define EFUSE_APB2OTP_BLOCK4_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W7_S 0 + +/** EFUSE_APB2OTP_BLK4_W8_REG register + * eFuse apb2otp block4 data register8. + */ +#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x5ec) +/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W8_M (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S) +#define EFUSE_APB2OTP_BLOCK4_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W8_S 0 + +/** EFUSE_APB2OTP_BLK4_W9_REG register + * eFuse apb2otp block4 data register9. + */ +#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x5f0) +/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W9_M (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S) +#define EFUSE_APB2OTP_BLOCK4_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W9_S 0 + +/** EFUSE_APB2OTP_BLK4_W10_REG register + * eFuse apb2otp block4 data registe10. + */ +#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x5f4) +/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W10_M (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S) +#define EFUSE_APB2OTP_BLOCK4_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W10_S 0 + +/** EFUSE_APB2OTP_BLK4_W11_REG register + * eFuse apb2otp block4 data register11. + */ +#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x5f8) +/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W11_M (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S) +#define EFUSE_APB2OTP_BLOCK4_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W11_S 0 + +/** EFUSE_APB2OTP_BLK5_W1_REG register + * eFuse apb2otp block5 data register1. + */ +#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x5fc) +/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W1_M (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S) +#define EFUSE_APB2OTP_BLOCK5_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W1_S 0 + +/** EFUSE_APB2OTP_BLK5_W2_REG register + * eFuse apb2otp block5 data register2. + */ +#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x600) +/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W2_M (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S) +#define EFUSE_APB2OTP_BLOCK5_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W2_S 0 + +/** EFUSE_APB2OTP_BLK5_W3_REG register + * eFuse apb2otp block5 data register3. + */ +#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x604) +/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W3_M (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S) +#define EFUSE_APB2OTP_BLOCK5_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W3_S 0 + +/** EFUSE_APB2OTP_BLK5_W4_REG register + * eFuse apb2otp block5 data register4. + */ +#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x608) +/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W4_M (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S) +#define EFUSE_APB2OTP_BLOCK5_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W4_S 0 + +/** EFUSE_APB2OTP_BLK5_W5_REG register + * eFuse apb2otp block5 data register5. + */ +#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x60c) +/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W5_M (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S) +#define EFUSE_APB2OTP_BLOCK5_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W5_S 0 + +/** EFUSE_APB2OTP_BLK5_W6_REG register + * eFuse apb2otp block5 data register6. + */ +#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x610) +/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W6_M (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S) +#define EFUSE_APB2OTP_BLOCK5_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W6_S 0 + +/** EFUSE_APB2OTP_BLK5_W7_REG register + * eFuse apb2otp block5 data register7. + */ +#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x614) +/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W7_M (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S) +#define EFUSE_APB2OTP_BLOCK5_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W7_S 0 + +/** EFUSE_APB2OTP_BLK5_W8_REG register + * eFuse apb2otp block5 data register8. + */ +#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x618) +/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W8_M (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S) +#define EFUSE_APB2OTP_BLOCK5_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W8_S 0 + +/** EFUSE_APB2OTP_BLK5_W9_REG register + * eFuse apb2otp block5 data register9. + */ +#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x61c) +/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W9_M (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S) +#define EFUSE_APB2OTP_BLOCK5_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W9_S 0 + +/** EFUSE_APB2OTP_BLK5_W10_REG register + * eFuse apb2otp block5 data register10. + */ +#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x620) +/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W10_M (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S) +#define EFUSE_APB2OTP_BLOCK5_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W10_S 0 + +/** EFUSE_APB2OTP_BLK5_W11_REG register + * eFuse apb2otp block5 data register11. + */ +#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x624) +/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W11_M (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S) +#define EFUSE_APB2OTP_BLOCK5_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W11_S 0 + +/** EFUSE_APB2OTP_BLK6_W1_REG register + * eFuse apb2otp block6 data register1. + */ +#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x628) +/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W1_M (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S) +#define EFUSE_APB2OTP_BLOCK6_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W1_S 0 + +/** EFUSE_APB2OTP_BLK6_W2_REG register + * eFuse apb2otp block6 data register2. + */ +#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x62c) +/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W2_M (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S) +#define EFUSE_APB2OTP_BLOCK6_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W2_S 0 + +/** EFUSE_APB2OTP_BLK6_W3_REG register + * eFuse apb2otp block6 data register3. + */ +#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x630) +/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W3_M (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S) +#define EFUSE_APB2OTP_BLOCK6_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W3_S 0 + +/** EFUSE_APB2OTP_BLK6_W4_REG register + * eFuse apb2otp block6 data register4. + */ +#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x634) +/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W4_M (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S) +#define EFUSE_APB2OTP_BLOCK6_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W4_S 0 + +/** EFUSE_APB2OTP_BLK6_W5_REG register + * eFuse apb2otp block6 data register5. + */ +#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x638) +/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W5_M (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S) +#define EFUSE_APB2OTP_BLOCK6_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W5_S 0 + +/** EFUSE_APB2OTP_BLK6_W6_REG register + * eFuse apb2otp block6 data register6. + */ +#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x63c) +/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W6_M (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S) +#define EFUSE_APB2OTP_BLOCK6_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W6_S 0 + +/** EFUSE_APB2OTP_BLK6_W7_REG register + * eFuse apb2otp block6 data register7. + */ +#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x640) +/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W7_M (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S) +#define EFUSE_APB2OTP_BLOCK6_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W7_S 0 + +/** EFUSE_APB2OTP_BLK6_W8_REG register + * eFuse apb2otp block6 data register8. + */ +#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x644) +/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W8_M (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S) +#define EFUSE_APB2OTP_BLOCK6_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W8_S 0 + +/** EFUSE_APB2OTP_BLK6_W9_REG register + * eFuse apb2otp block6 data register9. + */ +#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x648) +/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W9_M (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S) +#define EFUSE_APB2OTP_BLOCK6_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W9_S 0 + +/** EFUSE_APB2OTP_BLK6_W10_REG register + * eFuse apb2otp block6 data register10. + */ +#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x64c) +/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W10_M (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S) +#define EFUSE_APB2OTP_BLOCK6_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W10_S 0 + +/** EFUSE_APB2OTP_BLK6_W11_REG register + * eFuse apb2otp block6 data register11. + */ +#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x650) +/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W11_M (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S) +#define EFUSE_APB2OTP_BLOCK6_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W11_S 0 + +/** EFUSE_APB2OTP_BLK7_W1_REG register + * eFuse apb2otp block7 data register1. + */ +#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x654) +/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W1_M (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S) +#define EFUSE_APB2OTP_BLOCK7_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W1_S 0 + +/** EFUSE_APB2OTP_BLK7_W2_REG register + * eFuse apb2otp block7 data register2. + */ +#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x658) +/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W2_M (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S) +#define EFUSE_APB2OTP_BLOCK7_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W2_S 0 + +/** EFUSE_APB2OTP_BLK7_W3_REG register + * eFuse apb2otp block7 data register3. + */ +#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x65c) +/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W3_M (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S) +#define EFUSE_APB2OTP_BLOCK7_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W3_S 0 + +/** EFUSE_APB2OTP_BLK7_W4_REG register + * eFuse apb2otp block7 data register4. + */ +#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x660) +/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W4_M (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S) +#define EFUSE_APB2OTP_BLOCK7_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W4_S 0 + +/** EFUSE_APB2OTP_BLK7_W5_REG register + * eFuse apb2otp block7 data register5. + */ +#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x664) +/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W5_M (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S) +#define EFUSE_APB2OTP_BLOCK7_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W5_S 0 + +/** EFUSE_APB2OTP_BLK7_W6_REG register + * eFuse apb2otp block7 data register6. + */ +#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x668) +/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W6_M (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S) +#define EFUSE_APB2OTP_BLOCK7_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W6_S 0 + +/** EFUSE_APB2OTP_BLK7_W7_REG register + * eFuse apb2otp block7 data register7. + */ +#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x66c) +/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W7_M (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S) +#define EFUSE_APB2OTP_BLOCK7_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W7_S 0 + +/** EFUSE_APB2OTP_BLK7_W8_REG register + * eFuse apb2otp block7 data register8. + */ +#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x670) +/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W8_M (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S) +#define EFUSE_APB2OTP_BLOCK7_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W8_S 0 + +/** EFUSE_APB2OTP_BLK7_W9_REG register + * eFuse apb2otp block7 data register9. + */ +#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x674) +/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W9_M (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S) +#define EFUSE_APB2OTP_BLOCK7_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W9_S 0 + +/** EFUSE_APB2OTP_BLK7_W10_REG register + * eFuse apb2otp block7 data register10. + */ +#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x678) +/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W10_M (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S) +#define EFUSE_APB2OTP_BLOCK7_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W10_S 0 + +/** EFUSE_APB2OTP_BLK7_W11_REG register + * eFuse apb2otp block7 data register11. + */ +#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x67c) +/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W11_M (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S) +#define EFUSE_APB2OTP_BLOCK7_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W11_S 0 + +/** EFUSE_APB2OTP_BLK8_W1_REG register + * eFuse apb2otp block8 data register1. + */ +#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x680) +/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W1_M (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S) +#define EFUSE_APB2OTP_BLOCK8_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W1_S 0 + +/** EFUSE_APB2OTP_BLK8_W2_REG register + * eFuse apb2otp block8 data register2. + */ +#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x684) +/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W2_M (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S) +#define EFUSE_APB2OTP_BLOCK8_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W2_S 0 + +/** EFUSE_APB2OTP_BLK8_W3_REG register + * eFuse apb2otp block8 data register3. + */ +#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x688) +/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W3_M (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S) +#define EFUSE_APB2OTP_BLOCK8_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W3_S 0 + +/** EFUSE_APB2OTP_BLK8_W4_REG register + * eFuse apb2otp block8 data register4. + */ +#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x68c) +/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W4_M (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S) +#define EFUSE_APB2OTP_BLOCK8_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W4_S 0 + +/** EFUSE_APB2OTP_BLK8_W5_REG register + * eFuse apb2otp block8 data register5. + */ +#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x690) +/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W5_M (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S) +#define EFUSE_APB2OTP_BLOCK8_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W5_S 0 + +/** EFUSE_APB2OTP_BLK8_W6_REG register + * eFuse apb2otp block8 data register6. + */ +#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x694) +/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W6_M (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S) +#define EFUSE_APB2OTP_BLOCK8_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W6_S 0 + +/** EFUSE_APB2OTP_BLK8_W7_REG register + * eFuse apb2otp block8 data register7. + */ +#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x698) +/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W7_M (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S) +#define EFUSE_APB2OTP_BLOCK8_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W7_S 0 + +/** EFUSE_APB2OTP_BLK8_W8_REG register + * eFuse apb2otp block8 data register8. + */ +#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x69c) +/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W8_M (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S) +#define EFUSE_APB2OTP_BLOCK8_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W8_S 0 + +/** EFUSE_APB2OTP_BLK8_W9_REG register + * eFuse apb2otp block8 data register9. + */ +#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x6a0) +/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W9_M (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S) +#define EFUSE_APB2OTP_BLOCK8_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W9_S 0 + +/** EFUSE_APB2OTP_BLK8_W10_REG register + * eFuse apb2otp block8 data register10. + */ +#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x6a4) +/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W10_M (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S) +#define EFUSE_APB2OTP_BLOCK8_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W10_S 0 + +/** EFUSE_APB2OTP_BLK8_W11_REG register + * eFuse apb2otp block8 data register11. + */ +#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x6a8) +/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W11_M (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S) +#define EFUSE_APB2OTP_BLOCK8_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W11_S 0 + +/** EFUSE_APB2OTP_BLK9_W1_REG register + * eFuse apb2otp block9 data register1. + */ +#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x6ac) +/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W1_M (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S) +#define EFUSE_APB2OTP_BLOCK9_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W1_S 0 + +/** EFUSE_APB2OTP_BLK9_W2_REG register + * eFuse apb2otp block9 data register2. + */ +#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x6b0) +/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W2_M (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S) +#define EFUSE_APB2OTP_BLOCK9_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W2_S 0 + +/** EFUSE_APB2OTP_BLK9_W3_REG register + * eFuse apb2otp block9 data register3. + */ +#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x6b4) +/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W3_M (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S) +#define EFUSE_APB2OTP_BLOCK9_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W3_S 0 + +/** EFUSE_APB2OTP_BLK9_W4_REG register + * eFuse apb2otp block9 data register4. + */ +#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x6b8) +/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W4_M (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S) +#define EFUSE_APB2OTP_BLOCK9_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W4_S 0 + +/** EFUSE_APB2OTP_BLK9_W5_REG register + * eFuse apb2otp block9 data register5. + */ +#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x6bc) +/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W5_M (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S) +#define EFUSE_APB2OTP_BLOCK9_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W5_S 0 + +/** EFUSE_APB2OTP_BLK9_W6_REG register + * eFuse apb2otp block9 data register6. + */ +#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x6c0) +/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W6_M (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S) +#define EFUSE_APB2OTP_BLOCK9_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W6_S 0 + +/** EFUSE_APB2OTP_BLK9_W7_REG register + * eFuse apb2otp block9 data register7. + */ +#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x6c4) +/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W7_M (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S) +#define EFUSE_APB2OTP_BLOCK9_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W7_S 0 + +/** EFUSE_APB2OTP_BLK9_W8_REG register + * eFuse apb2otp block9 data register8. + */ +#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x6c8) +/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W8_M (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S) +#define EFUSE_APB2OTP_BLOCK9_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W8_S 0 + +/** EFUSE_APB2OTP_BLK9_W9_REG register + * eFuse apb2otp block9 data register9. + */ +#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x6cc) +/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W9_M (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S) +#define EFUSE_APB2OTP_BLOCK9_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W9_S 0 + +/** EFUSE_APB2OTP_BLK9_W10_REG register + * eFuse apb2otp block9 data register10. + */ +#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x6d0) +/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W10_M (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S) +#define EFUSE_APB2OTP_BLOCK9_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W10_S 0 + +/** EFUSE_APB2OTP_BLK9_W11_REG register + * eFuse apb2otp block9 data register11. + */ +#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x6d4) +/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W11_M (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S) +#define EFUSE_APB2OTP_BLOCK9_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W11_S 0 + +/** EFUSE_APB2OTP_BLK10_W1_REG register + * eFuse apb2otp block10 data register1. + */ +#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x6d8) +/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W1_M (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S) +#define EFUSE_APB2OTP_BLOCK10_W1_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W1_S 0 + +/** EFUSE_APB2OTP_BLK10_W2_REG register + * eFuse apb2otp block10 data register2. + */ +#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x6dc) +/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W2_M (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S) +#define EFUSE_APB2OTP_BLOCK10_W2_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W2_S 0 + +/** EFUSE_APB2OTP_BLK10_W3_REG register + * eFuse apb2otp block10 data register3. + */ +#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x6e0) +/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W3_M (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S) +#define EFUSE_APB2OTP_BLOCK10_W3_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W3_S 0 + +/** EFUSE_APB2OTP_BLK10_W4_REG register + * eFuse apb2otp block10 data register4. + */ +#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x6e4) +/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W4_M (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S) +#define EFUSE_APB2OTP_BLOCK10_W4_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W4_S 0 + +/** EFUSE_APB2OTP_BLK10_W5_REG register + * eFuse apb2otp block10 data register5. + */ +#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x6e8) +/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W5_M (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S) +#define EFUSE_APB2OTP_BLOCK10_W5_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W5_S 0 + +/** EFUSE_APB2OTP_BLK10_W6_REG register + * eFuse apb2otp block10 data register6. + */ +#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x6ec) +/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W6_M (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S) +#define EFUSE_APB2OTP_BLOCK10_W6_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W6_S 0 + +/** EFUSE_APB2OTP_BLK10_W7_REG register + * eFuse apb2otp block10 data register7. + */ +#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x6f0) +/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W7_M (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S) +#define EFUSE_APB2OTP_BLOCK10_W7_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W7_S 0 + +/** EFUSE_APB2OTP_BLK10_W8_REG register + * eFuse apb2otp block10 data register8. + */ +#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x6f4) +/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W8_M (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S) +#define EFUSE_APB2OTP_BLOCK10_W8_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W8_S 0 + +/** EFUSE_APB2OTP_BLK10_W9_REG register + * eFuse apb2otp block10 data register9. + */ +#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x6f8) +/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W9_M (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S) +#define EFUSE_APB2OTP_BLOCK10_W9_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W9_S 0 + +/** EFUSE_APB2OTP_BLK10_W10_REG register + * eFuse apb2otp block10 data register10. + */ +#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x6fc) +/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W10_M (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S) +#define EFUSE_APB2OTP_BLOCK10_W10_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W10_S 0 + +/** EFUSE_APB2OTP_BLK10_W11_REG register + * eFuse apb2otp block10 data register11. + */ +#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0x700) +/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W11_M (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S) +#define EFUSE_APB2OTP_BLOCK10_W11_V 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W11_S 0 + +/** EFUSE_APB2OTP_EN_REG register + * eFuse apb2otp enable configuration register. + */ +#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0x708) +/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0; + * Apb2otp mode enable signal. + */ +#define EFUSE_APB2OTP_APB2OTP_EN (BIT(0)) +#define EFUSE_APB2OTP_APB2OTP_EN_M (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S) +#define EFUSE_APB2OTP_APB2OTP_EN_V 0x00000001U +#define EFUSE_APB2OTP_APB2OTP_EN_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/efuse_struct.h b/components/soc/esp32c61/include/soc/efuse_struct.h new file mode 100644 index 0000000000..77da6e32ce --- /dev/null +++ b/components/soc/esp32c61/include/soc/efuse_struct.h @@ -0,0 +1,3368 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: buffer0 registers */ +/** Type of pgm_datan register + * Represents pgm_datan + */ +typedef union { + struct { + /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth 32-bit data to be programmed. + */ + uint32_t pgm_data_n:32; + }; + uint32_t val; +} efuse_pgm_datan_reg_t; + + +/** Group: buffer1 registers */ +/** Type of pgm_check_valuen register + * Represents pgm_check_valuen + */ +typedef union { + struct { + /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth RS code to be programmed. + */ + uint32_t pgm_rs_data_n:32; + }; + uint32_t val; +} efuse_pgm_check_valuen_reg_t; + + +/** Group: block0 registers */ +/** Type of rd_wr_dis0 register + * Represents rd_wr_dis + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled.\\ 1: Disabled\\ 0: Enabled\\ + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis0_reg_t; + +/** Type of rd_repeat_data0 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ + */ + uint32_t rd_dis:7; + /** dis_icache : RO; bitpos: [7]; default: 0; + * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [8]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: + * disabled\\ 0: enabled\\ + */ + uint32_t dis_usb_jtag:1; + /** dis_usb_serial_jtag : RO; bitpos: [9]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ + */ + uint32_t dis_usb_serial_jtag:1; + /** dis_force_download : RO; bitpos: [10]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [11]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ + */ + uint32_t spi_download_mspi_dis:1; + /** jtag_sel_enable : RO; bitpos: [12]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + */ + uint32_t jtag_sel_enable:1; + /** dis_pad_jtag : RO; bitpos: [13]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ + * 0: enabled\\ + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [14]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode).\\ 1: disabled\\ 0: enabled\\ + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [16:15]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [18:17]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [19]; default: 0; + * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not + * exchanged\\ + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [20]; default: 0; + * Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not + * functioned\\ + */ + uint32_t vdd_spi_as_gpio:1; + /** wdt_delay_sel : RO; bitpos: [22:21]; default: 0; + * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original + * threshold configuration value of STG0 *2 \\1: Original threshold configuration + * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: + * Original threshold configuration value of STG0 *16 \\ + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [25:23]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of + * 1: enabled\\ Even number of 1: disabled\\ + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke_0 : RO; bitpos: [26]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ + */ + uint32_t secure_boot_key_revoke_0:1; + /** secure_boot_key_revoke_1 : RO; bitpos: [27]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ + */ + uint32_t secure_boot_key_revoke_1:1; + /** secure_boot_key_revoke_2 : RO; bitpos: [28]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ + */ + uint32_t secure_boot_key_revoke_2:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** key_purpose_0 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + /** key_purpose_2 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [19:16]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [23:20]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** sec_dpa_level : RO; bitpos: [25:24]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t sec_dpa_level:2; + /** secure_boot_en : RO; bitpos: [26]; default: 0; + * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [27]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: + * enabled.\\ 0: disabled\\ + */ + uint32_t secure_boot_aggressive_revoke:1; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is programmed value. Otherwise, the waiting time is + * 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: + * Enable\\ + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. + * Disable\\ 0: Enable\\ + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [3]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ + * 1: Disable\\ 0: Enable\\ + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [4]; default: 0; + * Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: + * Disable\\ + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [6:5]; default: 0; + * Represents the types of UART printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [7]; default: 0; + * Represents whether ROM code is forced to send a resume commmand during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [23:8]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [24]; default: 0; + * Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is + * enable. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad : RO; bitpos: [25]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: + * enabled\\ 0:disabled\\ + */ + uint32_t hys_en_pad:1; + /** xts_dpa_clk_enable : RO; bitpos: [26]; default: 0; + * Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: + * Disable\\ + */ + uint32_t xts_dpa_clk_enable:1; + /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; + * Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: + * Low\\ 0: Decided by register configuration\\ + */ + uint32_t xts_dpa_pseudo_level:2; + /** dis_wifi6 : RO; bitpos: [29]; default: 0; + * Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is + * disable\\ 0: WiFi 6 is enabled.\\ + */ + uint32_t dis_wifi6:1; + /** ecdsa_disable_p192 : RO; bitpos: [30]; default: 0; + * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. + */ + uint32_t ecdsa_disable_p192:1; + /** ecc_force_const_time : RO; bitpos: [31]; default: 0; + * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. + * \\ 0: Disable. + */ + uint32_t ecc_force_const_time:1; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** rd_repeat_data3 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rd_repeat_data3:32; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * Represents rd_repeat_data + */ +typedef union { + struct { + /** rd_repeat_data4 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rd_repeat_data4:32; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + + +/** Group: block1 registers */ +/** Type of rd_mac_sys0 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Represents MAC address. Low 32-bit. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys0_reg_t; + +/** Type of rd_mac_sys1 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Represents MAC address. High 16-bit. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Represents the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys1_reg_t; + +/** Type of rd_mac_sys2 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_0:14; + /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_1:18; + }; + uint32_t val; +} efuse_rd_mac_sys2_reg_t; + +/** Type of rd_mac_sys3 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys3_reg_t; + +/** Type of rd_mac_sys4 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys4_reg_t; + +/** Type of rd_mac_sys5 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys5_reg_t; + + +/** Group: block2 registers */ +/** Type of rd_sys_part1_datan register + * Represents rd_sys_part1_datan + */ +typedef union { + struct { + /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_n:32; + }; + uint32_t val; +} efuse_rd_sys_part1_datan_reg_t; + + +/** Group: block3 registers */ +/** Type of rd_usr_datan register + * Represents rd_usr_datan + */ +typedef union { + struct { + /** usr_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_datan:32; + }; + uint32_t val; +} efuse_rd_usr_datan_reg_t; + + +/** Group: block4 registers */ +/** Type of rd_key0_datan register + * Represents rd_key0_datan + */ +typedef union { + struct { + /** key0_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_datan:32; + }; + uint32_t val; +} efuse_rd_key0_datan_reg_t; + + +/** Group: block5 registers */ +/** Type of rd_key1_datan register + * Represents rd_key1_datan + */ +typedef union { + struct { + /** key1_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_datan:32; + }; + uint32_t val; +} efuse_rd_key1_datan_reg_t; + + +/** Group: block6 registers */ +/** Type of rd_key2_datan register + * Represents rd_key2_datan + */ +typedef union { + struct { + /** key2_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_datan:32; + }; + uint32_t val; +} efuse_rd_key2_datan_reg_t; + + +/** Group: block7 registers */ +/** Type of rd_key3_datan register + * Represents rd_key3_datan + */ +typedef union { + struct { + /** key3_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_datan:32; + }; + uint32_t val; +} efuse_rd_key3_datan_reg_t; + + +/** Group: block8 registers */ +/** Type of rd_key4_datan register + * Represents rd_key4_datan + */ +typedef union { + struct { + /** key4_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_datan:32; + }; + uint32_t val; +} efuse_rd_key4_datan_reg_t; + + +/** Group: block9 registers */ +/** Type of rd_key5_datan register + * Represents rd_key5_datan + */ +typedef union { + struct { + /** key5_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_datan:32; + }; + uint32_t val; +} efuse_rd_key5_datan_reg_t; + + +/** Group: block10 registers */ +/** Type of rd_sys_part2_datan register + * Represents rd_sys_part2_datan + */ +typedef union { + struct { + /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_n:32; + }; + uint32_t val; +} efuse_rd_sys_part2_datan_reg_t; + + +/** Group: block0 error report registers */ +/** Type of rd_repeat_data_err0 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Represents the programming error of EFUSE_RD_DIS + */ + uint32_t rd_dis_err:7; + /** dis_icache_err : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_DIS_ICACHE + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [8]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_JTAG + */ + uint32_t dis_usb_jtag_err:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [9]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ + uint32_t dis_usb_serial_jtag_err:1; + /** dis_force_download_err : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + */ + uint32_t spi_download_mspi_dis_err:1; + /** jtag_sel_enable_err : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + */ + uint32_t jtag_sel_enable_err:1; + /** dis_pad_jtag_err : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_DIS_PAD_JTAG + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [16:15]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [18:17]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_USB_EXCHG_PINS + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [20]; default: 0; + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + */ + uint32_t vdd_spi_as_gpio_err:1; + /** wdt_delay_sel_err : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [25:23]; default: 0; + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke_0_err : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_0 + */ + uint32_t secure_boot_key_revoke_0_err:1; + /** secure_boot_key_revoke_1_err : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_1 + */ + uint32_t secure_boot_key_revoke_1_err:1; + /** secure_boot_key_revoke_2_err : RO; bitpos: [28]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_2 + */ + uint32_t secure_boot_key_revoke_2_err:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} efuse_rd_repeat_data_err0_reg_t; + +/** Type of rd_repeat_data_err1 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** key_purpose_0_err : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_0 + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [7:4]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_1 + */ + uint32_t key_purpose_1_err:4; + /** key_purpose_2_err : RO; bitpos: [11:8]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_2 + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [15:12]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_3 + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [19:16]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_4 + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [23:20]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_5 + */ + uint32_t key_purpose_5_err:4; + /** sec_dpa_level_err : RO; bitpos: [25:24]; default: 0; + * Represents the programming error of EFUSE_SEC_DPA_LEVEL + */ + uint32_t sec_dpa_level_err:2; + /** secure_boot_en_err : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_EN + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Represents the programming error of EFUSE_FLASH_TPUW + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_data_err1_reg_t; + +/** Type of rd_repeat_data_err2 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + */ + uint32_t dis_direct_boot_err:1; + /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT + */ + uint32_t dis_usb_serial_jtag_rom_print_err:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [6:5]; default: 0; + * Represents the programming error of EFUSE_UART_PRINT_CONTROL + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_FORCE_SEND_RESUME + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [23:8]; default: 0; + * Represents the programming error of EFUSE_SECURE_VERSION + */ + uint32_t secure_version_err:16; + /** secure_boot_disable_fast_wake_err : RO; bitpos: [24]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + */ + uint32_t secure_boot_disable_fast_wake_err:1; + /** hys_en_pad_err : RO; bitpos: [25]; default: 0; + * Represents the programming error of EFUSE_HYS_EN_PAD + */ + uint32_t hys_en_pad_err:1; + /** xts_dpa_clk_enable_err : RO; bitpos: [26]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE + */ + uint32_t xts_dpa_clk_enable_err:1; + /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + */ + uint32_t xts_dpa_pseudo_level_err:2; + /** dis_wifi6_err : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_DIS_WIFI6 + */ + uint32_t dis_wifi6_err:1; + /** ecdsa_disable_p192_err : RO; bitpos: [30]; default: 0; + * Represents the programming error of EFUSE_ECDSA_DISABLE_P192 + */ + uint32_t ecdsa_disable_p192_err:1; + /** ecc_force_const_time_err : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + */ + uint32_t ecc_force_const_time_err:1; + }; + uint32_t val; +} efuse_rd_repeat_data_err2_reg_t; + +/** Type of rd_repeat_data_err3 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** rd_repeat_data_err3 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rd_repeat_data_err3:32; + }; + uint32_t val; +} efuse_rd_repeat_data_err3_reg_t; + +/** Type of rd_repeat_data_err4 register + * Represents rd_repeat_data_err + */ +typedef union { + struct { + /** rd_repeat_data_err4 : RO; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rd_repeat_data_err4:32; + }; + uint32_t val; +} efuse_rd_repeat_data_err4_reg_t; + + +/** Group: RS block error report registers */ +/** Type of rd_rs_data_err0 register + * Represents rd_rs_data_err + */ +typedef union { + struct { + /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys + */ + uint32_t rd_mac_sys_err_num:3; + /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. + */ + uint32_t rd_mac_sys_fail:1; + /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data + */ + uint32_t rd_sys_part1_data_err_num:3; + /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. + */ + uint32_t rd_sys_part1_data_fail:1; + /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data + */ + uint32_t rd_usr_data_err_num:3; + /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_usr_data_fail:1; + /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data + */ + uint32_t rd_key0_data_err_num:3; + /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_key0_data_fail:1; + /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data + */ + uint32_t rd_key1_data_err_num:3; + /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_key1_data_fail:1; + /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data + */ + uint32_t rd_key2_data_err_num:3; + /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_key2_data_fail:1; + /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data + */ + uint32_t rd_key3_data_err_num:3; + /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_key3_data_fail:1; + /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data + */ + uint32_t rd_key4_data_err_num:3; + /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_key4_data_fail:1; + }; + uint32_t val; +} efuse_rd_rs_data_err0_reg_t; + +/** Type of rd_rs_data_err1 register + * Represents rd_rs_data_err + */ +typedef union { + struct { + /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key5_data + */ + uint32_t rd_key5_data_err_num:3; + /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. + */ + uint32_t rd_key5_data_fail:1; + /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data + */ + uint32_t rd_sys_part2_data_err_num:3; + /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. + */ + uint32_t rd_sys_part2_data_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_data_err1_reg_t; + + +/** Group: EFUSE Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37753088; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +/** Group: EFUSE Clock Registers */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + + +/** Group: EFUSE Configure Registers */ +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ + uint32_t op_code:16; + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + + +/** Group: EFUSE Status Registers */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: EFUSE Command Registers */ +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Write Disable Data */ +/** Type of apb2otp_wr_dis register + * eFuse apb2otp block0 data register1. + */ +typedef union { + struct { + /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ + uint32_t apb2otp_block0_wr_dis:32; + }; + uint32_t val; +} efuse_apb2otp_wr_dis_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */ +/** Type of apb2otp_blk0_backup1_w1 register + * eFuse apb2otp block0 data register2. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ + uint32_t apb2otp_block0_backup1_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */ +/** Type of apb2otp_blk0_backup1_w2 register + * eFuse apb2otp block0 data register3. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ + uint32_t apb2otp_block0_backup1_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */ +/** Type of apb2otp_blk0_backup1_w3 register + * eFuse apb2otp block0 data register4. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ + uint32_t apb2otp_block0_backup1_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */ +/** Type of apb2otp_blk0_backup1_w4 register + * eFuse apb2otp block0 data register5. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ + uint32_t apb2otp_block0_backup1_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */ +/** Type of apb2otp_blk0_backup1_w5 register + * eFuse apb2otp block0 data register6. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ + uint32_t apb2otp_block0_backup1_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */ +/** Type of apb2otp_blk0_backup2_w1 register + * eFuse apb2otp block0 data register7. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ + uint32_t apb2otp_block0_backup2_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */ +/** Type of apb2otp_blk0_backup2_w2 register + * eFuse apb2otp block0 data register8. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ + uint32_t apb2otp_block0_backup2_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */ +/** Type of apb2otp_blk0_backup2_w3 register + * eFuse apb2otp block0 data register9. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ + uint32_t apb2otp_block0_backup2_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */ +/** Type of apb2otp_blk0_backup2_w4 register + * eFuse apb2otp block0 data register10. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ + uint32_t apb2otp_block0_backup2_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */ +/** Type of apb2otp_blk0_backup2_w5 register + * eFuse apb2otp block0 data register11. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ + uint32_t apb2otp_block0_backup2_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */ +/** Type of apb2otp_blk0_backup3_w1 register + * eFuse apb2otp block0 data register12. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ + uint32_t apb2otp_block0_backup3_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */ +/** Type of apb2otp_blk0_backup3_w2 register + * eFuse apb2otp block0 data register13. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ + uint32_t apb2otp_block0_backup3_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */ +/** Type of apb2otp_blk0_backup3_w3 register + * eFuse apb2otp block0 data register14. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ + uint32_t apb2otp_block0_backup3_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */ +/** Type of apb2otp_blk0_backup3_w4 register + * eFuse apb2otp block0 data register15. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ + uint32_t apb2otp_block0_backup3_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */ +/** Type of apb2otp_blk0_backup3_w5 register + * eFuse apb2otp block0 data register16. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ + uint32_t apb2otp_block0_backup3_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */ +/** Type of apb2otp_blk0_backup4_w1 register + * eFuse apb2otp block0 data register17. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ + uint32_t apb2otp_block0_backup4_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */ +/** Type of apb2otp_blk0_backup4_w2 register + * eFuse apb2otp block0 data register18. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ + uint32_t apb2otp_block0_backup4_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */ +/** Type of apb2otp_blk0_backup4_w3 register + * eFuse apb2otp block0 data register19. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ + uint32_t apb2otp_block0_backup4_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */ +/** Type of apb2otp_blk0_backup4_w4 register + * eFuse apb2otp block0 data register20. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ + uint32_t apb2otp_block0_backup4_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */ +/** Type of apb2otp_blk0_backup4_w5 register + * eFuse apb2otp block0 data register21. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ + uint32_t apb2otp_block0_backup4_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word1 Data */ +/** Type of apb2otp_blk1_w1 register + * eFuse apb2otp block1 data register1. + */ +typedef union { + struct { + /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ + uint32_t apb2otp_block1_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word2 Data */ +/** Type of apb2otp_blk1_w2 register + * eFuse apb2otp block1 data register2. + */ +typedef union { + struct { + /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ + uint32_t apb2otp_block1_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word3 Data */ +/** Type of apb2otp_blk1_w3 register + * eFuse apb2otp block1 data register3. + */ +typedef union { + struct { + /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ + uint32_t apb2otp_block1_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word4 Data */ +/** Type of apb2otp_blk1_w4 register + * eFuse apb2otp block1 data register4. + */ +typedef union { + struct { + /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ + uint32_t apb2otp_block1_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word5 Data */ +/** Type of apb2otp_blk1_w5 register + * eFuse apb2otp block1 data register5. + */ +typedef union { + struct { + /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ + uint32_t apb2otp_block1_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word6 Data */ +/** Type of apb2otp_blk1_w6 register + * eFuse apb2otp block1 data register6. + */ +typedef union { + struct { + /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ + uint32_t apb2otp_block1_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word7 Data */ +/** Type of apb2otp_blk1_w7 register + * eFuse apb2otp block1 data register7. + */ +typedef union { + struct { + /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ + uint32_t apb2otp_block1_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word8 Data */ +/** Type of apb2otp_blk1_w8 register + * eFuse apb2otp block1 data register8. + */ +typedef union { + struct { + /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ + uint32_t apb2otp_block1_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word9 Data */ +/** Type of apb2otp_blk1_w9 register + * eFuse apb2otp block1 data register9. + */ +typedef union { + struct { + /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ + uint32_t apb2otp_block1_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word1 Data */ +/** Type of apb2otp_blk2_w1 register + * eFuse apb2otp block2 data register1. + */ +typedef union { + struct { + /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ + uint32_t apb2otp_block2_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word2 Data */ +/** Type of apb2otp_blk2_w2 register + * eFuse apb2otp block2 data register2. + */ +typedef union { + struct { + /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ + uint32_t apb2otp_block2_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word3 Data */ +/** Type of apb2otp_blk2_w3 register + * eFuse apb2otp block2 data register3. + */ +typedef union { + struct { + /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ + uint32_t apb2otp_block2_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word4 Data */ +/** Type of apb2otp_blk2_w4 register + * eFuse apb2otp block2 data register4. + */ +typedef union { + struct { + /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ + uint32_t apb2otp_block2_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word5 Data */ +/** Type of apb2otp_blk2_w5 register + * eFuse apb2otp block2 data register5. + */ +typedef union { + struct { + /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ + uint32_t apb2otp_block2_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word6 Data */ +/** Type of apb2otp_blk2_w6 register + * eFuse apb2otp block2 data register6. + */ +typedef union { + struct { + /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ + uint32_t apb2otp_block2_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word7 Data */ +/** Type of apb2otp_blk2_w7 register + * eFuse apb2otp block2 data register7. + */ +typedef union { + struct { + /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ + uint32_t apb2otp_block2_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word8 Data */ +/** Type of apb2otp_blk2_w8 register + * eFuse apb2otp block2 data register8. + */ +typedef union { + struct { + /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ + uint32_t apb2otp_block2_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word9 Data */ +/** Type of apb2otp_blk2_w9 register + * eFuse apb2otp block2 data register9. + */ +typedef union { + struct { + /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ + uint32_t apb2otp_block2_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word10 Data */ +/** Type of apb2otp_blk2_w10 register + * eFuse apb2otp block2 data register10. + */ +typedef union { + struct { + /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ + uint32_t apb2otp_block2_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word11 Data */ +/** Type of apb2otp_blk2_w11 register + * eFuse apb2otp block2 data register11. + */ +typedef union { + struct { + /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ + uint32_t apb2otp_block2_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w11_reg_t; + +/** Type of apb2otp_blk10_w11 register + * eFuse apb2otp block10 data register11. + */ +typedef union { + struct { + /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t apb2otp_block10_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word1 Data */ +/** Type of apb2otp_blk3_w1 register + * eFuse apb2otp block3 data register1. + */ +typedef union { + struct { + /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ + uint32_t apb2otp_block3_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word2 Data */ +/** Type of apb2otp_blk3_w2 register + * eFuse apb2otp block3 data register2. + */ +typedef union { + struct { + /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ + uint32_t apb2otp_block3_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word3 Data */ +/** Type of apb2otp_blk3_w3 register + * eFuse apb2otp block3 data register3. + */ +typedef union { + struct { + /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ + uint32_t apb2otp_block3_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word4 Data */ +/** Type of apb2otp_blk3_w4 register + * eFuse apb2otp block3 data register4. + */ +typedef union { + struct { + /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ + uint32_t apb2otp_block3_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word5 Data */ +/** Type of apb2otp_blk3_w5 register + * eFuse apb2otp block3 data register5. + */ +typedef union { + struct { + /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ + uint32_t apb2otp_block3_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word6 Data */ +/** Type of apb2otp_blk3_w6 register + * eFuse apb2otp block3 data register6. + */ +typedef union { + struct { + /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ + uint32_t apb2otp_block3_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word7 Data */ +/** Type of apb2otp_blk3_w7 register + * eFuse apb2otp block3 data register7. + */ +typedef union { + struct { + /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ + uint32_t apb2otp_block3_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word8 Data */ +/** Type of apb2otp_blk3_w8 register + * eFuse apb2otp block3 data register8. + */ +typedef union { + struct { + /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ + uint32_t apb2otp_block3_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word9 Data */ +/** Type of apb2otp_blk3_w9 register + * eFuse apb2otp block3 data register9. + */ +typedef union { + struct { + /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ + uint32_t apb2otp_block3_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word10 Data */ +/** Type of apb2otp_blk3_w10 register + * eFuse apb2otp block3 data register10. + */ +typedef union { + struct { + /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ + uint32_t apb2otp_block3_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word11 Data */ +/** Type of apb2otp_blk3_w11 register + * eFuse apb2otp block3 data register11. + */ +typedef union { + struct { + /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ + uint32_t apb2otp_block3_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w11_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */ +/** Type of apb2otp_blk4_w1 register + * eFuse apb2otp BLOCK7 data register1. + */ +typedef union { + struct { + /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ + uint32_t apb2otp_block4_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w1_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */ +/** Type of apb2otp_blk4_w2 register + * eFuse apb2otp block4 data register2. + */ +typedef union { + struct { + /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ + uint32_t apb2otp_block4_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w2_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */ +/** Type of apb2otp_blk4_w3 register + * eFuse apb2otp block4 data register3. + */ +typedef union { + struct { + /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ + uint32_t apb2otp_block4_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w3_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */ +/** Type of apb2otp_blk4_w4 register + * eFuse apb2otp block4 data register4. + */ +typedef union { + struct { + /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ + uint32_t apb2otp_block4_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w4_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */ +/** Type of apb2otp_blk4_w5 register + * eFuse apb2otp block4 data register5. + */ +typedef union { + struct { + /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ + uint32_t apb2otp_block4_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w5_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */ +/** Type of apb2otp_blk4_w6 register + * eFuse apb2otp block4 data register6. + */ +typedef union { + struct { + /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ + uint32_t apb2otp_block4_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w6_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */ +/** Type of apb2otp_blk4_w7 register + * eFuse apb2otp block4 data register7. + */ +typedef union { + struct { + /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ + uint32_t apb2otp_block4_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w7_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */ +/** Type of apb2otp_blk4_w8 register + * eFuse apb2otp block4 data register8. + */ +typedef union { + struct { + /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ + uint32_t apb2otp_block4_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w8_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */ +/** Type of apb2otp_blk4_w9 register + * eFuse apb2otp block4 data register9. + */ +typedef union { + struct { + /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ + uint32_t apb2otp_block4_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w9_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */ +/** Type of apb2otp_blk4_w10 register + * eFuse apb2otp block4 data registe10. + */ +typedef union { + struct { + /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ + uint32_t apb2otp_block4_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w10_reg_t; + + +/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */ +/** Type of apb2otp_blk4_w11 register + * eFuse apb2otp block4 data register11. + */ +typedef union { + struct { + /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ + uint32_t apb2otp_block4_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word1 Data */ +/** Type of apb2otp_blk5_w1 register + * eFuse apb2otp block5 data register1. + */ +typedef union { + struct { + /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ + uint32_t apb2otp_block5_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word2 Data */ +/** Type of apb2otp_blk5_w2 register + * eFuse apb2otp block5 data register2. + */ +typedef union { + struct { + /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ + uint32_t apb2otp_block5_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word3 Data */ +/** Type of apb2otp_blk5_w3 register + * eFuse apb2otp block5 data register3. + */ +typedef union { + struct { + /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ + uint32_t apb2otp_block5_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word4 Data */ +/** Type of apb2otp_blk5_w4 register + * eFuse apb2otp block5 data register4. + */ +typedef union { + struct { + /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ + uint32_t apb2otp_block5_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word5 Data */ +/** Type of apb2otp_blk5_w5 register + * eFuse apb2otp block5 data register5. + */ +typedef union { + struct { + /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ + uint32_t apb2otp_block5_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word6 Data */ +/** Type of apb2otp_blk5_w6 register + * eFuse apb2otp block5 data register6. + */ +typedef union { + struct { + /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ + uint32_t apb2otp_block5_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word7 Data */ +/** Type of apb2otp_blk5_w7 register + * eFuse apb2otp block5 data register7. + */ +typedef union { + struct { + /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ + uint32_t apb2otp_block5_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word8 Data */ +/** Type of apb2otp_blk5_w8 register + * eFuse apb2otp block5 data register8. + */ +typedef union { + struct { + /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ + uint32_t apb2otp_block5_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word9 Data */ +/** Type of apb2otp_blk5_w9 register + * eFuse apb2otp block5 data register9. + */ +typedef union { + struct { + /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ + uint32_t apb2otp_block5_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word10 Data */ +/** Type of apb2otp_blk5_w10 register + * eFuse apb2otp block5 data register10. + */ +typedef union { + struct { + /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ + uint32_t apb2otp_block5_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word11 Data */ +/** Type of apb2otp_blk5_w11 register + * eFuse apb2otp block5 data register11. + */ +typedef union { + struct { + /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ + uint32_t apb2otp_block5_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word1 Data */ +/** Type of apb2otp_blk6_w1 register + * eFuse apb2otp block6 data register1. + */ +typedef union { + struct { + /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ + uint32_t apb2otp_block6_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word2 Data */ +/** Type of apb2otp_blk6_w2 register + * eFuse apb2otp block6 data register2. + */ +typedef union { + struct { + /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ + uint32_t apb2otp_block6_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word3 Data */ +/** Type of apb2otp_blk6_w3 register + * eFuse apb2otp block6 data register3. + */ +typedef union { + struct { + /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ + uint32_t apb2otp_block6_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word4 Data */ +/** Type of apb2otp_blk6_w4 register + * eFuse apb2otp block6 data register4. + */ +typedef union { + struct { + /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ + uint32_t apb2otp_block6_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word5 Data */ +/** Type of apb2otp_blk6_w5 register + * eFuse apb2otp block6 data register5. + */ +typedef union { + struct { + /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ + uint32_t apb2otp_block6_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word6 Data */ +/** Type of apb2otp_blk6_w6 register + * eFuse apb2otp block6 data register6. + */ +typedef union { + struct { + /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ + uint32_t apb2otp_block6_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word7 Data */ +/** Type of apb2otp_blk6_w7 register + * eFuse apb2otp block6 data register7. + */ +typedef union { + struct { + /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ + uint32_t apb2otp_block6_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word8 Data */ +/** Type of apb2otp_blk6_w8 register + * eFuse apb2otp block6 data register8. + */ +typedef union { + struct { + /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ + uint32_t apb2otp_block6_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word9 Data */ +/** Type of apb2otp_blk6_w9 register + * eFuse apb2otp block6 data register9. + */ +typedef union { + struct { + /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ + uint32_t apb2otp_block6_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word10 Data */ +/** Type of apb2otp_blk6_w10 register + * eFuse apb2otp block6 data register10. + */ +typedef union { + struct { + /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ + uint32_t apb2otp_block6_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word11 Data */ +/** Type of apb2otp_blk6_w11 register + * eFuse apb2otp block6 data register11. + */ +typedef union { + struct { + /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ + uint32_t apb2otp_block6_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word1 Data */ +/** Type of apb2otp_blk7_w1 register + * eFuse apb2otp block7 data register1. + */ +typedef union { + struct { + /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ + uint32_t apb2otp_block7_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word2 Data */ +/** Type of apb2otp_blk7_w2 register + * eFuse apb2otp block7 data register2. + */ +typedef union { + struct { + /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ + uint32_t apb2otp_block7_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word3 Data */ +/** Type of apb2otp_blk7_w3 register + * eFuse apb2otp block7 data register3. + */ +typedef union { + struct { + /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ + uint32_t apb2otp_block7_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word4 Data */ +/** Type of apb2otp_blk7_w4 register + * eFuse apb2otp block7 data register4. + */ +typedef union { + struct { + /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ + uint32_t apb2otp_block7_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word5 Data */ +/** Type of apb2otp_blk7_w5 register + * eFuse apb2otp block7 data register5. + */ +typedef union { + struct { + /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ + uint32_t apb2otp_block7_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word6 Data */ +/** Type of apb2otp_blk7_w6 register + * eFuse apb2otp block7 data register6. + */ +typedef union { + struct { + /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ + uint32_t apb2otp_block7_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word7 Data */ +/** Type of apb2otp_blk7_w7 register + * eFuse apb2otp block7 data register7. + */ +typedef union { + struct { + /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ + uint32_t apb2otp_block7_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word8 Data */ +/** Type of apb2otp_blk7_w8 register + * eFuse apb2otp block7 data register8. + */ +typedef union { + struct { + /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ + uint32_t apb2otp_block7_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word9 Data */ +/** Type of apb2otp_blk7_w9 register + * eFuse apb2otp block7 data register9. + */ +typedef union { + struct { + /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ + uint32_t apb2otp_block7_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word10 Data */ +/** Type of apb2otp_blk7_w10 register + * eFuse apb2otp block7 data register10. + */ +typedef union { + struct { + /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ + uint32_t apb2otp_block7_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word11 Data */ +/** Type of apb2otp_blk7_w11 register + * eFuse apb2otp block7 data register11. + */ +typedef union { + struct { + /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ + uint32_t apb2otp_block7_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word1 Data */ +/** Type of apb2otp_blk8_w1 register + * eFuse apb2otp block8 data register1. + */ +typedef union { + struct { + /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ + uint32_t apb2otp_block8_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word2 Data */ +/** Type of apb2otp_blk8_w2 register + * eFuse apb2otp block8 data register2. + */ +typedef union { + struct { + /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ + uint32_t apb2otp_block8_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word3 Data */ +/** Type of apb2otp_blk8_w3 register + * eFuse apb2otp block8 data register3. + */ +typedef union { + struct { + /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ + uint32_t apb2otp_block8_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word4 Data */ +/** Type of apb2otp_blk8_w4 register + * eFuse apb2otp block8 data register4. + */ +typedef union { + struct { + /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ + uint32_t apb2otp_block8_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word5 Data */ +/** Type of apb2otp_blk8_w5 register + * eFuse apb2otp block8 data register5. + */ +typedef union { + struct { + /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ + uint32_t apb2otp_block8_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word6 Data */ +/** Type of apb2otp_blk8_w6 register + * eFuse apb2otp block8 data register6. + */ +typedef union { + struct { + /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ + uint32_t apb2otp_block8_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word7 Data */ +/** Type of apb2otp_blk8_w7 register + * eFuse apb2otp block8 data register7. + */ +typedef union { + struct { + /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ + uint32_t apb2otp_block8_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word8 Data */ +/** Type of apb2otp_blk8_w8 register + * eFuse apb2otp block8 data register8. + */ +typedef union { + struct { + /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ + uint32_t apb2otp_block8_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word9 Data */ +/** Type of apb2otp_blk8_w9 register + * eFuse apb2otp block8 data register9. + */ +typedef union { + struct { + /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ + uint32_t apb2otp_block8_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word10 Data */ +/** Type of apb2otp_blk8_w10 register + * eFuse apb2otp block8 data register10. + */ +typedef union { + struct { + /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ + uint32_t apb2otp_block8_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word11 Data */ +/** Type of apb2otp_blk8_w11 register + * eFuse apb2otp block8 data register11. + */ +typedef union { + struct { + /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ + uint32_t apb2otp_block8_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word1 Data */ +/** Type of apb2otp_blk9_w1 register + * eFuse apb2otp block9 data register1. + */ +typedef union { + struct { + /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ + uint32_t apb2otp_block9_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word2 Data */ +/** Type of apb2otp_blk9_w2 register + * eFuse apb2otp block9 data register2. + */ +typedef union { + struct { + /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ + uint32_t apb2otp_block9_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word3 Data */ +/** Type of apb2otp_blk9_w3 register + * eFuse apb2otp block9 data register3. + */ +typedef union { + struct { + /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ + uint32_t apb2otp_block9_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word4 Data */ +/** Type of apb2otp_blk9_w4 register + * eFuse apb2otp block9 data register4. + */ +typedef union { + struct { + /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ + uint32_t apb2otp_block9_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word5 Data */ +/** Type of apb2otp_blk9_w5 register + * eFuse apb2otp block9 data register5. + */ +typedef union { + struct { + /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ + uint32_t apb2otp_block9_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word6 Data */ +/** Type of apb2otp_blk9_w6 register + * eFuse apb2otp block9 data register6. + */ +typedef union { + struct { + /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ + uint32_t apb2otp_block9_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word7 Data */ +/** Type of apb2otp_blk9_w7 register + * eFuse apb2otp block9 data register7. + */ +typedef union { + struct { + /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ + uint32_t apb2otp_block9_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word8 Data */ +/** Type of apb2otp_blk9_w8 register + * eFuse apb2otp block9 data register8. + */ +typedef union { + struct { + /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ + uint32_t apb2otp_block9_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word9 Data */ +/** Type of apb2otp_blk9_w9 register + * eFuse apb2otp block9 data register9. + */ +typedef union { + struct { + /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ + uint32_t apb2otp_block9_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word10 Data */ +/** Type of apb2otp_blk9_w10 register + * eFuse apb2otp block9 data register10. + */ +typedef union { + struct { + /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ + uint32_t apb2otp_block9_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word11 Data */ +/** Type of apb2otp_blk9_w11 register + * eFuse apb2otp block9 data register11. + */ +typedef union { + struct { + /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ + uint32_t apb2otp_block9_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word1 Data */ +/** Type of apb2otp_blk10_w1 register + * eFuse apb2otp block10 data register1. + */ +typedef union { + struct { + /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ + uint32_t apb2otp_block10_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word2 Data */ +/** Type of apb2otp_blk10_w2 register + * eFuse apb2otp block10 data register2. + */ +typedef union { + struct { + /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ + uint32_t apb2otp_block10_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word3 Data */ +/** Type of apb2otp_blk10_w3 register + * eFuse apb2otp block10 data register3. + */ +typedef union { + struct { + /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ + uint32_t apb2otp_block10_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word4 Data */ +/** Type of apb2otp_blk10_w4 register + * eFuse apb2otp block10 data register4. + */ +typedef union { + struct { + /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ + uint32_t apb2otp_block10_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word5 Data */ +/** Type of apb2otp_blk10_w5 register + * eFuse apb2otp block10 data register5. + */ +typedef union { + struct { + /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ + uint32_t apb2otp_block10_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word6 Data */ +/** Type of apb2otp_blk10_w6 register + * eFuse apb2otp block10 data register6. + */ +typedef union { + struct { + /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ + uint32_t apb2otp_block10_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word7 Data */ +/** Type of apb2otp_blk10_w7 register + * eFuse apb2otp block10 data register7. + */ +typedef union { + struct { + /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ + uint32_t apb2otp_block10_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word8 Data */ +/** Type of apb2otp_blk10_w8 register + * eFuse apb2otp block10 data register8. + */ +typedef union { + struct { + /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ + uint32_t apb2otp_block10_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word9 Data */ +/** Type of apb2otp_blk10_w9 register + * eFuse apb2otp block10 data register9. + */ +typedef union { + struct { + /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ + uint32_t apb2otp_block10_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word10 Data */ +/** Type of apb2otp_blk10_w10 register + * eFuse apb2otp block10 data register10. + */ +typedef union { + struct { + /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ + uint32_t apb2otp_block10_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Function Enable Singal */ +/** Type of apb2otp_en register + * eFuse apb2otp enable configuration register. + */ +typedef union { + struct { + /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0; + * Apb2otp mode enable signal. + */ + uint32_t apb2otp_apb2otp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} efuse_apb2otp_en_reg_t; + + +typedef struct { + volatile efuse_pgm_datan_reg_t pgm_datan[8]; + volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; + volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; + volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; + volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; + volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; + volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; + volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; + volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; + volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; + volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; + volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; + volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; + volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; + volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; + volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; + volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; + volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; + volatile efuse_date_reg_t date; + uint32_t reserved_19c[11]; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + uint32_t reserved_1fc[193]; + volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; + volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; + volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; + volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3; + volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4; + volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5; + volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1; + volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2; + volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3; + volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4; + volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5; + volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1; + volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2; + volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3; + volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4; + volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5; + volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1; + volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2; + volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3; + volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4; + volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5; + volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1; + volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2; + volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3; + volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4; + volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5; + volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6; + volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7; + volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8; + volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9; + volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1; + volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2; + volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3; + volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4; + volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5; + volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6; + volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7; + volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8; + volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9; + volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10; + volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11; + volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1; + volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2; + volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3; + volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4; + volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5; + volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6; + volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7; + volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8; + volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9; + volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10; + volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11; + volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1; + volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2; + volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3; + volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4; + volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5; + volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6; + volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7; + volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8; + volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9; + volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10; + volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11; + volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1; + volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2; + volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3; + volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4; + volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5; + volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6; + volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7; + volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8; + volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9; + volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10; + volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11; + volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1; + volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2; + volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3; + volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4; + volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5; + volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6; + volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7; + volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8; + volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9; + volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10; + volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11; + volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1; + volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2; + volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3; + volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4; + volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5; + volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6; + volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7; + volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8; + volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9; + volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10; + volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11; + volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1; + volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2; + volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3; + volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4; + volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5; + volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6; + volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7; + volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8; + volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9; + volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10; + volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11; + volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1; + volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2; + volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3; + volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4; + volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5; + volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6; + volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7; + volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8; + volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9; + volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10; + volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11; + volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1; + volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2; + volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3; + volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4; + volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5; + volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6; + volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7; + volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8; + volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9; + volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10; + volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; + uint32_t reserved_704; + volatile efuse_apb2otp_en_reg_t apb2otp_en; +} efuse_dev_t; + +extern efuse_dev_t EFUSE_AND_OTP_DEBUG0; +extern efuse_dev_t EFUSE_AND_OTP_DEBUG1; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gdma_reg.h b/components/soc/esp32c61/include/soc/gdma_reg.h new file mode 100644 index 0000000000..1224a96f94 --- /dev/null +++ b/components/soc/esp32c61/include/soc/gdma_reg.h @@ -0,0 +1,2371 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw interrupt status of RX channel 0 + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of GDMA_IN_DONE_CH0_INT. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of GDMA_IN_SUC_EOF_CH0_INT. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of GDMA_IN_ERR_EOF_CH0_INT. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of GDMA_IN_DSCR_ERR_CH0_INT. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of GDMA_IN_DSCR_EMPTY_CH0_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of GDMA_INFIFO_OVF_CH0_INT. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of GDMA_INFIFO_UDF_CH0_INT. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt status of RX channel 0 + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of GDMA_IN_DONE_CH0_INT. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of GDMA_IN_SUC_EOF_CH0_INT. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of GDMA_IN_ERR_EOF_CH0_INT. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of GDMA_IN_DSCR_ERR_CH0_INT. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of GDMA_IN_DSCR_EMPTY_CH0_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of GDMA_INFIFO_OVF_CH0_INT. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of GDMA_INFIFO_UDF_CH0_INT. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of RX channel 0 + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable GDMA_IN_DONE_CH0_INT. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable GDMA_IN_SUC_EOF_CH0_INT. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable GDMA_IN_ERR_EOF_CH0_INT. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable GDMA_IN_DSCR_ERR_CH0_INT. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable GDMA_IN_DSCR_EMPTY_CH0_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable GDMA_INFIFO_OVF_CH0_INT. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable GDMA_INFIFO_UDF_CH0_INT. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of RX channel 0 + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear GDMA_IN_DONE_CH0_INT. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear GDMA_IN_SUC_EOF_CH0_INT. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear GDMA_IN_ERR_EOF_CH0_INT. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear GDMA_IN_DSCR_ERR_CH0_INT. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear GDMA_IN_DSCR_EMPTY_CH0_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear GDMA_INFIFO_OVF_CH0_INT. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear GDMA_INFIFO_UDF_CH0_INT. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw interrupt status of RX channel 0 + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of GDMA_IN_DONE_CH1_INT. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of GDMA_IN_SUC_EOF_CH1_INT. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of GDMA_IN_ERR_EOF_CH1_INT. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of GDMA_IN_DSCR_ERR_CH1_INT. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of GDMA_IN_DSCR_EMPTY_CH1_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of GDMA_INFIFO_OVF_CH1_INT. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of GDMA_INFIFO_UDF_CH1_INT. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt status of RX channel 0 + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of GDMA_IN_DONE_CH1_INT. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of GDMA_IN_SUC_EOF_CH1_INT. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of GDMA_IN_ERR_EOF_CH1_INT. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of GDMA_IN_DSCR_ERR_CH1_INT. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of GDMA_IN_DSCR_EMPTY_CH1_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of GDMA_INFIFO_OVF_CH1_INT. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of GDMA_INFIFO_UDF_CH1_INT. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of RX channel 0 + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable GDMA_IN_DONE_CH1_INT. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable GDMA_IN_SUC_EOF_CH1_INT. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable GDMA_IN_ERR_EOF_CH1_INT. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable GDMA_IN_DSCR_ERR_CH1_INT. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable GDMA_IN_DSCR_EMPTY_CH1_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable GDMA_INFIFO_OVF_CH1_INT. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable GDMA_INFIFO_UDF_CH1_INT. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of RX channel 0 + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear GDMA_IN_DONE_CH1_INT. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear GDMA_IN_SUC_EOF_CH1_INT. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear GDMA_IN_ERR_EOF_CH1_INT. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear GDMA_IN_DSCR_ERR_CH1_INT. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear GDMA_IN_DSCR_EMPTY_CH1_INT. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear GDMA_INFIFO_OVF_CH1_INT. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear GDMA_INFIFO_UDF_CH1_INT. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw interrupt status of TX channel 0 + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of GDMA_OUT_DONE_CH0_INT. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of GDMA_OUT_EOF_CH0_INT. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of GDMA_OUT_DSCR_ERR_CH0_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of GDMA_OUT_TOTAL_EOF_CH0_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of GDMA_OUTFIFO_OVF_CH0_INT. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of GDMA_OUTFIFO_UDF_CH0_INT. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt status of TX channel 0 + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of GDMA_OUT_DONE_CH0_INT. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of GDMA_OUT_EOF_CH0_INT. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of GDMA_OUT_DSCR_ERR_CH0_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of GDMA_OUT_TOTAL_EOF_CH0_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of GDMA_OUTFIFO_OVF_CH0_INT. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of GDMA_OUTFIFO_UDF_CH0_INT. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of TX channel 0 + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable GDMA_OUT_DONE_CH0_INT. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable GDMA_OUT_EOF_CH0_INT. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable GDMA_OUT_DSCR_ERR_CH0_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable GDMA_OUT_TOTAL_EOF_CH0_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable GDMA_OUTFIFO_OVF_CH0_INT. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable GDMA_OUTFIFO_UDF_CH0_INT. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of TX channel 0 + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear GDMA_OUT_DONE_CH0_INT. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear GDMA_OUT_EOF_CH0_INT. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear GDMA_OUT_DSCR_ERR_CH0_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear GDMA_OUT_TOTAL_EOF_CH0_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear GDMA_OUTFIFO_OVF_CH0_INT. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear GDMA_OUTFIFO_UDF_CH0_INT. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw interrupt status of TX channel 0 + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of GDMA_OUT_DONE_CH1_INT. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of GDMA_OUT_EOF_CH1_INT. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of GDMA_OUT_DSCR_ERR_CH1_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of GDMA_OUT_TOTAL_EOF_CH1_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of GDMA_OUTFIFO_OVF_CH1_INT. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of GDMA_OUTFIFO_UDF_CH1_INT. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt status of TX channel 0 + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of GDMA_OUT_DONE_CH1_INT. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of GDMA_OUT_EOF_CH1_INT. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of GDMA_OUT_DSCR_ERR_CH1_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of GDMA_OUT_TOTAL_EOF_CH1_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of GDMA_OUTFIFO_OVF_CH1_INT. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of GDMA_OUTFIFO_UDF_CH1_INT. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of TX channel 0 + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable GDMA_OUT_DONE_CH1_INT. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable GDMA_OUT_EOF_CH1_INT. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable GDMA_OUT_DSCR_ERR_CH1_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable GDMA_OUT_TOTAL_EOF_CH1_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable GDMA_OUTFIFO_OVF_CH1_INT. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable GDMA_OUTFIFO_UDF_CH1_INT. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of TX channel 0 + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear GDMA_OUT_DONE_CH1_INT. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear GDMA_OUT_EOF_CH1_INT. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear GDMA_OUT_DSCR_ERR_CH1_INT. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear GDMA_OUT_TOTAL_EOF_CH1_INT. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear GDMA_OUTFIFO_OVF_CH1_INT. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear GDMA_OUTFIFO_UDF_CH1_INT. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_AHB_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * Miscellaneous register + */ +#define GDMA_MISC_CONF_REG (DR_REG_AHB_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset the internal AHB FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Configures whether or not to disable the fixed-priority channel arbitration.\\0: + * Enable\\1: Disable\\ + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * Configures clock gating.\\0: Support clock only when the application writes + * registers.\\ 1: Always force the clock on for registers.\\ + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_AHB_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 36770448; + * Version control register. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configuration register 0 of RX channel 0 + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable INCR burst transfer for RX channel 0 to read + * descriptors.\\0: Disable\\1: Enable\\ + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: + * Enable\\ + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ETM control for RX channel0.\\0: Disable\\1: + * Enable\\ + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 +/** GDMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ +#define GDMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U +#define GDMA_IN_DATA_BURST_MODE_SEL_CH0_M (GDMA_IN_DATA_BURST_MODE_SEL_CH0_V << GDMA_IN_DATA_BURST_MODE_SEL_CH0_S) +#define GDMA_IN_DATA_BURST_MODE_SEL_CH0_V 0x00000003U +#define GDMA_IN_DATA_BURST_MODE_SEL_CH0_S 6 + +/** GDMA_IN_CONF1_CH0_REG register + * Configuration register 1 of RX channel 0 + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable owner bit check for RX channel 0.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of RX channel 0 + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000007FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000007FU +#define GDMA_INFIFO_CNT_CH0_S 8 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of RX channel 0 + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: + * Pop\\ + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Linked list descriptor configuration and control register of RX channel 0 + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x80) +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; + * Configures whether or not to return to current receive descriptor's address when + * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(0)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 0 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; + * Configures whether or not to stop AHB_DMA's RX channel 0 from receiving data.\\0: + * Invalid. No effect\\1: Stop\\ + */ +#define GDMA_INLINK_STOP_CH0 (BIT(1)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 1 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable AHB_DMA's RX channel 0 for data transfer.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_INLINK_START_CH0 (BIT(2)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 2 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; + * Configures whether or not to restart RX channel 0 for AHB_DMA transfer.\\0: + * Invalid. No effect\\1: Restart\\ + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(3)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 3 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + */ +#define GDMA_INLINK_PARK_CH0 (BIT(4)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 4 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of RX channel 0 + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Receive descriptor address when EOF occurs on RX channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Receive descriptor address when errors occur of RX channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current receive descriptor address of RX channel 0 + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last receive descriptor address of RX channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last receive descriptor address of RX channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of RX channel 0 + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 0.The larger of the value, the higher of the + * priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection register of RX channel 0 + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 0.\\ 0: Dummy\\ 1: SPI2\\ 2: + * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ + * 10: Dummy\\ 11~15: Dummy\\ + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_IN_DONE_DES_ADDR_CH0_REG register + * RX_done Inlink descriptor address of RX channel 0 + */ +#define GDMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xb0) +/** GDMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define GDMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_DONE_DES_ADDR_CH0_M (GDMA_IN_DONE_DES_ADDR_CH0_V << GDMA_IN_DONE_DES_ADDR_CH0_S) +#define GDMA_IN_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_DONE_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configuration register 0 of TX channel 0 + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0: + * Release reset\\1: Reset\\ + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable automatic outlink write-back when all the data + * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated + * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for + * TX channel 0 is generated when data to be transmitted has been popped from FIFO in + * AHB_DMA.\\ + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable INCR burst transfer for TX channel 0 reading + * descriptors.\\0: Disable\\1: Enable\\ + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1: + * Enable\\ + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 +/** GDMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH0_M (GDMA_OUT_DATA_BURST_MODE_SEL_CH0_V << GDMA_OUT_DATA_BURST_MODE_SEL_CH0_S) +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH0_V 0x00000003U +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH0_S 8 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configuration register 1 of TX channel 0 + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable owner bit check for TX channel 0.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of TX channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000007FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000007FU +#define GDMA_OUTFIFO_CNT_CH0_S 8 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of TX channel 0 + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No + * effect\\1: Push\\ + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Linked list descriptor configuration and control register of TX channel 0 + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to stop AHB_DMA's TX channel 0 from transmitting + * data.\\0: Invalid. No effect\\1: Stop\\ + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(0)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 0 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable AHB_DMA's TX channel 0 for data transfer.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_OUTLINK_START_CH0 (BIT(1)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 1 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; + * Configures whether or not to restart TX channel 0 for AHB_DMA transfer.\\0: + * Invalid. No effect\\1: Restart\\ + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(2)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 2 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(3)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 3 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of TX channel 0 + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Transmit descriptor address when EOF occurs on TX channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last transmit descriptor address when EOF occurs on TX channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current transmit descriptor address of TX channel 0 + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last transmit descriptor address of TX channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last transmit descriptor address of TX channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of TX channel 0 + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_AHB_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 0.The larger of the value, the higher of the + * priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection register of TX channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 0.\\ 0: Dummy\\ 1: SPI2\\ 2: + * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ + * 10: Dummy\\ 11~15: Dummy\\ + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_OUT_DONE_DES_ADDR_CH0_REG register + * TX done outlink descriptor address of TX channel 0 + */ +#define GDMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x110) +/** GDMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define GDMA_OUT_DONE_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_DONE_DES_ADDR_CH0_M (GDMA_OUT_DONE_DES_ADDR_CH0_V << GDMA_OUT_DONE_DES_ADDR_CH0_S) +#define GDMA_OUT_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_DONE_DES_ADDR_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configuration register 0 of RX channel 0 + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable INCR burst transfer for RX channel 1 to read + * descriptors.\\0: Disable\\1: Enable\\ + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: + * Enable\\ + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ETM control for RX channel1.\\0: Disable\\1: + * Enable\\ + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 +/** GDMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ +#define GDMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U +#define GDMA_IN_DATA_BURST_MODE_SEL_CH1_M (GDMA_IN_DATA_BURST_MODE_SEL_CH1_V << GDMA_IN_DATA_BURST_MODE_SEL_CH1_S) +#define GDMA_IN_DATA_BURST_MODE_SEL_CH1_V 0x00000003U +#define GDMA_IN_DATA_BURST_MODE_SEL_CH1_S 6 + +/** GDMA_IN_CONF1_CH1_REG register + * Configuration register 1 of RX channel 0 + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable owner bit check for RX channel 1.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of RX channel 0 + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 1. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000007FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000007FU +#define GDMA_INFIFO_CNT_CH1_S 8 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of RX channel 0 + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: + * Pop\\ + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Linked list descriptor configuration and control register of RX channel 0 + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x140) +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; + * Configures whether or not to return to current receive descriptor's address when + * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(0)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 0 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to stop AHB_DMA's RX channel 1 from receiving data.\\0: + * Invalid. No effect\\1: Stop\\ + */ +#define GDMA_INLINK_STOP_CH1 (BIT(1)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 1 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable AHB_DMA's RX channel 1 for data transfer.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_INLINK_START_CH1 (BIT(2)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 2 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; + * Configures whether or not to restart RX channel 1 for AHB_DMA transfer.\\0: + * Invalid. No effect\\1: Restart\\ + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(3)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 3 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + */ +#define GDMA_INLINK_PARK_CH1 (BIT(4)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 4 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of RX channel 0 + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Receive descriptor address when EOF occurs on RX channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Receive descriptor address when errors occur of RX channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current receive descriptor address of RX channel 0 + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last receive descriptor address of RX channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last receive descriptor address of RX channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of RX channel 0 + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 1.The larger of the value, the higher of the + * priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection register of RX channel 0 + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 1.\\ 0: Dummy\\ 1: SPI2\\ 2: + * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ + * 10: Dummy\\ 11~15: Dummy\\ + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_IN_DONE_DES_ADDR_CH1_REG register + * RX_done Inlink descriptor address of RX channel 0 + */ +#define GDMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x170) +/** GDMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define GDMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_DONE_DES_ADDR_CH1_M (GDMA_IN_DONE_DES_ADDR_CH1_V << GDMA_IN_DONE_DES_ADDR_CH1_S) +#define GDMA_IN_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_DONE_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configuration register 0 of TX channel 1 + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.\\0: + * Release reset\\1: Reset\\ + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable automatic outlink write-back when all the data + * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag.\\0: EOF flag for TX channel 1 is generated + * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for + * TX channel 1 is generated when data to be transmitted has been popped from FIFO in + * AHB_DMA.\\ + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable INCR burst transfer for TX channel 1 reading + * descriptors.\\0: Disable\\1: Enable\\ + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ETM control for TX channel 1.\\0: Disable\\1: + * Enable\\ + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 +/** GDMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH1_M (GDMA_OUT_DATA_BURST_MODE_SEL_CH1_V << GDMA_OUT_DATA_BURST_MODE_SEL_CH1_S) +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH1_V 0x00000003U +#define GDMA_OUT_DATA_BURST_MODE_SEL_CH1_S 8 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configuration register 1 of TX channel 0 + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable owner bit check for TX channel 1.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of TX channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 1. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000007FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000007FU +#define GDMA_OUTFIFO_CNT_CH1_S 8 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * Reserved. + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of TX channel 0 + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No + * effect\\1: Push\\ + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Linked list descriptor configuration and control register of TX channel 0 + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; + * Configures whether or not to stop AHB_DMA's TX channel 1 from transmitting + * data.\\0: Invalid. No effect\\1: Stop\\ + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(0)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 0 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable AHB_DMA's TX channel 1 for data transfer.\\0: + * Disable\\1: Enable\\ + */ +#define GDMA_OUTLINK_START_CH1 (BIT(1)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 1 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; + * Configures whether or not to restart TX channel 1 for AHB_DMA transfer.\\0: + * Invalid. No effect\\1: Restart\\ + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(2)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 2 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(3)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 3 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of TX channel 0 + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Transmit descriptor address when EOF occurs on TX channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last transmit descriptor address when EOF occurs on TX channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current transmit descriptor address of TX channel 0 + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last transmit descriptor address of TX channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last transmit descriptor address of TX channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of TX channel 0 + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 1.The larger of the value, the higher of the + * priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection register of TX channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 1.\\ 0: Dummy\\ 1: SPI2\\ 2: + * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ + * 10: Dummy\\ 11~15: Dummy\\ + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_OUT_DONE_DES_ADDR_CH1_REG register + * TX done outlink descriptor address of TX channel 0 + */ +#define GDMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x1d0) +/** GDMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define GDMA_OUT_DONE_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_DONE_DES_ADDR_CH1_M (GDMA_OUT_DONE_DES_ADDR_CH1_V << GDMA_OUT_DONE_DES_ADDR_CH1_S) +#define GDMA_OUT_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_DONE_DES_ADDR_CH1_S 0 + +/** GDMA_TX_CH_ARB_WEIGH_CH0_REG register + * TX channel 0 arbitration weight configuration register + */ +#define GDMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x2dc) +/** GDMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel0 + */ +#define GDMA_TX_CH_ARB_WEIGH_CH0 0x0000000FU +#define GDMA_TX_CH_ARB_WEIGH_CH0_M (GDMA_TX_CH_ARB_WEIGH_CH0_V << GDMA_TX_CH_ARB_WEIGH_CH0_S) +#define GDMA_TX_CH_ARB_WEIGH_CH0_V 0x0000000FU +#define GDMA_TX_CH_ARB_WEIGH_CH0_S 0 + +/** GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG register + * TX channel 0 weight arbitration optimization enable register + */ +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x2e0) +/** GDMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_M (GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_S) +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_V 0x00000001U +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH0_S 0 + +/** GDMA_TX_CH_ARB_WEIGH_CH1_REG register + * TX channel 0 arbitration weight configuration register + */ +#define GDMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x304) +/** GDMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel1 + */ +#define GDMA_TX_CH_ARB_WEIGH_CH1 0x0000000FU +#define GDMA_TX_CH_ARB_WEIGH_CH1_M (GDMA_TX_CH_ARB_WEIGH_CH1_V << GDMA_TX_CH_ARB_WEIGH_CH1_S) +#define GDMA_TX_CH_ARB_WEIGH_CH1_V 0x0000000FU +#define GDMA_TX_CH_ARB_WEIGH_CH1_S 0 + +/** GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG register + * TX channel 0 weight arbitration optimization enable register + */ +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x308) +/** GDMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_M (GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_S) +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_V 0x00000001U +#define GDMA_TX_ARB_WEIGH_OPT_DIR_CH1_S 0 + +/** GDMA_RX_CH_ARB_WEIGH_CH0_REG register + * RX channel 0 arbitration weight configuration register + */ +#define GDMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x354) +/** GDMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel0 + */ +#define GDMA_RX_CH_ARB_WEIGH_CH0 0x0000000FU +#define GDMA_RX_CH_ARB_WEIGH_CH0_M (GDMA_RX_CH_ARB_WEIGH_CH0_V << GDMA_RX_CH_ARB_WEIGH_CH0_S) +#define GDMA_RX_CH_ARB_WEIGH_CH0_V 0x0000000FU +#define GDMA_RX_CH_ARB_WEIGH_CH0_S 0 + +/** GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG register + * RX channel 0 weight arbitration optimization enable register + */ +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x358) +/** GDMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_M (GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_S) +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_V 0x00000001U +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH0_S 0 + +/** GDMA_RX_CH_ARB_WEIGH_CH1_REG register + * RX channel 0 arbitration weight configuration register + */ +#define GDMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x37c) +/** GDMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel1 + */ +#define GDMA_RX_CH_ARB_WEIGH_CH1 0x0000000FU +#define GDMA_RX_CH_ARB_WEIGH_CH1_M (GDMA_RX_CH_ARB_WEIGH_CH1_V << GDMA_RX_CH_ARB_WEIGH_CH1_S) +#define GDMA_RX_CH_ARB_WEIGH_CH1_V 0x0000000FU +#define GDMA_RX_CH_ARB_WEIGH_CH1_S 0 + +/** GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG register + * RX channel 0 weight arbitration optimization enable register + */ +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x380) +/** GDMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_M (GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_S) +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_V 0x00000001U +#define GDMA_RX_ARB_WEIGH_OPT_DIR_CH1_S 0 + +/** GDMA_IN_LINK_ADDR_CH0_REG register + * Link list descriptor address configuration of RX channel 0 + */ +#define GDMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x3ac) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define GDMA_INLINK_ADDR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 + +/** GDMA_IN_LINK_ADDR_CH1_REG register + * Link list descriptor address configuration of RX channel 0 + */ +#define GDMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x3b0) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define GDMA_INLINK_ADDR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 + +/** GDMA_OUT_LINK_ADDR_CH0_REG register + * Link list descriptor address configuration of TX channel 0 + */ +#define GDMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_GDMA_BASE + 0x3b8) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 + +/** GDMA_OUT_LINK_ADDR_CH1_REG register + * Link list descriptor address configuration of TX channel 0 + */ +#define GDMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_GDMA_BASE + 0x3bc) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 + +/** GDMA_INTR_MEM_START_ADDR_REG register + * Accessible address space start address configuration register + */ +#define GDMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_GDMA_BASE + 0x3c4) +/** GDMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configures the start address of accessible address space. + */ +#define GDMA_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU +#define GDMA_ACCESS_INTR_MEM_START_ADDR_M (GDMA_ACCESS_INTR_MEM_START_ADDR_V << GDMA_ACCESS_INTR_MEM_START_ADDR_S) +#define GDMA_ACCESS_INTR_MEM_START_ADDR_V 0xFFFFFFFFU +#define GDMA_ACCESS_INTR_MEM_START_ADDR_S 0 + +/** GDMA_INTR_MEM_END_ADDR_REG register + * Accessible address space end address configuration register + */ +#define GDMA_INTR_MEM_END_ADDR_REG (DR_REG_AHB_GDMA_BASE + 0x3c8) +/** GDMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of accessible address space. + */ +#define GDMA_ACCESS_INTR_MEM_END_ADDR 0xFFFFFFFFU +#define GDMA_ACCESS_INTR_MEM_END_ADDR_M (GDMA_ACCESS_INTR_MEM_END_ADDR_V << GDMA_ACCESS_INTR_MEM_END_ADDR_S) +#define GDMA_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU +#define GDMA_ACCESS_INTR_MEM_END_ADDR_S 0 + +/** GDMA_ARB_TIMEOUT_TX_REG register + * TX arbitration timeout configuration register + */ +#define GDMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_GDMA_BASE + 0x3cc) +/** GDMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. + */ +#define GDMA_ARB_TIMEOUT_TX 0x0000FFFFU +#define GDMA_ARB_TIMEOUT_TX_M (GDMA_ARB_TIMEOUT_TX_V << GDMA_ARB_TIMEOUT_TX_S) +#define GDMA_ARB_TIMEOUT_TX_V 0x0000FFFFU +#define GDMA_ARB_TIMEOUT_TX_S 0 + +/** GDMA_ARB_TIMEOUT_RX_REG register + * RX arbitration timeout configuration register + */ +#define GDMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_GDMA_BASE + 0x3d0) +/** GDMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. + */ +#define GDMA_ARB_TIMEOUT_RX 0x0000FFFFU +#define GDMA_ARB_TIMEOUT_RX_M (GDMA_ARB_TIMEOUT_RX_V << GDMA_ARB_TIMEOUT_RX_S) +#define GDMA_ARB_TIMEOUT_RX_V 0x0000FFFFU +#define GDMA_ARB_TIMEOUT_RX_S 0 + +/** GDMA_WEIGHT_EN_TX_REG register + * TX weight arbitration enable register + */ +#define GDMA_WEIGHT_EN_TX_REG (DR_REG_AHB_GDMA_BASE + 0x3d4) +/** GDMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ + */ +#define GDMA_WEIGHT_EN_TX (BIT(0)) +#define GDMA_WEIGHT_EN_TX_M (GDMA_WEIGHT_EN_TX_V << GDMA_WEIGHT_EN_TX_S) +#define GDMA_WEIGHT_EN_TX_V 0x00000001U +#define GDMA_WEIGHT_EN_TX_S 0 + +/** GDMA_WEIGHT_EN_RX_REG register + * RX weight arbitration enable register + */ +#define GDMA_WEIGHT_EN_RX_REG (DR_REG_AHB_GDMA_BASE + 0x3d8) +/** GDMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ + */ +#define GDMA_WEIGHT_EN_RX (BIT(0)) +#define GDMA_WEIGHT_EN_RX_M (GDMA_WEIGHT_EN_RX_V << GDMA_WEIGHT_EN_RX_S) +#define GDMA_WEIGHT_EN_RX_V 0x00000001U +#define GDMA_WEIGHT_EN_RX_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gdma_struct.h b/components/soc/esp32c61/include/soc/gdma_struct.h new file mode 100644 index 0000000000..a758496aef --- /dev/null +++ b/components/soc/esp32c61/include/soc/gdma_struct.h @@ -0,0 +1,1281 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of in_int_raw_chn register + * Raw interrupt status of RX channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT. + */ + uint32_t in_done_chn_int_raw:1; + /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. + */ + uint32_t in_suc_eof_chn_int_raw:1; + /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. + */ + uint32_t in_err_eof_chn_int_raw:1; + /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. + */ + uint32_t in_dscr_err_chn_int_raw:1; + /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + */ + uint32_t in_dscr_empty_chn_int_raw:1; + /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. + */ + uint32_t infifo_ovf_chn_int_raw:1; + /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. + */ + uint32_t infifo_udf_chn_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt status of RX channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT. + */ + uint32_t in_done_chn_int_st:1; + /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. + */ + uint32_t in_suc_eof_chn_int_st:1; + /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. + */ + uint32_t in_err_eof_chn_int_st:1; + /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. + */ + uint32_t in_dscr_err_chn_int_st:1; + /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + */ + uint32_t in_dscr_empty_chn_int_st:1; + /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. + */ + uint32_t infifo_ovf_chn_int_st:1; + /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. + */ + uint32_t infifo_udf_chn_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of RX channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_IN_DONE_CHn_INT. + */ + uint32_t in_done_chn_int_ena:1; + /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT. + */ + uint32_t in_suc_eof_chn_int_ena:1; + /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT. + */ + uint32_t in_err_eof_chn_int_ena:1; + /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT. + */ + uint32_t in_dscr_err_chn_int_ena:1; + /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + */ + uint32_t in_dscr_empty_chn_int_ena:1; + /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT. + */ + uint32_t infifo_ovf_chn_int_ena:1; + /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT. + */ + uint32_t infifo_udf_chn_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of RX channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_IN_DONE_CHn_INT. + */ + uint32_t in_done_chn_int_clr:1; + /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT. + */ + uint32_t in_suc_eof_chn_int_clr:1; + /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT. + */ + uint32_t in_err_eof_chn_int_clr:1; + /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT. + */ + uint32_t in_dscr_err_chn_int_clr:1; + /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + */ + uint32_t in_dscr_empty_chn_int_clr:1; + /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT. + */ + uint32_t infifo_ovf_chn_int_clr:1; + /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT. + */ + uint32_t infifo_udf_chn_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + +/** Type of out_int_raw_chn register + * Raw interrupt status of TX channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT. + */ + uint32_t out_done_chn_int_raw:1; + /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT. + */ + uint32_t out_eof_chn_int_raw:1; + /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. + */ + uint32_t out_dscr_err_chn_int_raw:1; + /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + */ + uint32_t out_total_eof_chn_int_raw:1; + /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. + */ + uint32_t outfifo_ovf_chn_int_raw:1; + /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. + */ + uint32_t outfifo_udf_chn_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt status of TX channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT. + */ + uint32_t out_done_chn_int_st:1; + /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT. + */ + uint32_t out_eof_chn_int_st:1; + /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. + */ + uint32_t out_dscr_err_chn_int_st:1; + /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + */ + uint32_t out_total_eof_chn_int_st:1; + /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. + */ + uint32_t outfifo_ovf_chn_int_st:1; + /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. + */ + uint32_t outfifo_udf_chn_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of TX channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT. + */ + uint32_t out_done_chn_int_ena:1; + /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT. + */ + uint32_t out_eof_chn_int_ena:1; + /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT. + */ + uint32_t out_dscr_err_chn_int_ena:1; + /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + */ + uint32_t out_total_eof_chn_int_ena:1; + /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT. + */ + uint32_t outfifo_ovf_chn_int_ena:1; + /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT. + */ + uint32_t outfifo_udf_chn_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of TX channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT. + */ + uint32_t out_done_chn_int_clr:1; + /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT. + */ + uint32_t out_eof_chn_int_clr:1; + /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT. + */ + uint32_t out_dscr_err_chn_int_clr:1; + /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + */ + uint32_t out_total_eof_chn_int_clr:1; + /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT. + */ + uint32_t outfifo_ovf_chn_int_clr:1; + /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT. + */ + uint32_t outfifo_udf_chn_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * Miscellaneous register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset the internal AHB FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Configures whether or not to disable the fixed-priority channel arbitration.\\0: + * Enable\\1: Disable\\ + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * Configures clock gating.\\0: Support clock only when the application writes + * registers.\\ 1: Always force the clock on for registers.\\ + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + +/** Type of in_conf0_chn register + * Configuration register 0 of RX channel 0 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable INCR burst transfer for RX channel n to read + * descriptors.\\0: Disable\\1: Enable\\ + */ + uint32_t indscr_burst_en_chn:1; + uint32_t reserved_3:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: + * Enable\\ + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ETM control for RX channeln.\\0: Disable\\1: + * Enable\\ + */ + uint32_t in_etm_en_chn:1; + /** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0; + * Configures max burst size for Rx channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ + uint32_t in_data_burst_mode_sel_chn:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configuration register 1 of RX channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable owner bit check for RX channel n.\\0: + * Disable\\1: Enable\\ + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of RX channel 0 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: + * Pop\\ + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Linked list descriptor configuration and control register of RX channel 0 + */ +typedef union { + struct { + /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; + * Configures whether or not to return to current receive descriptor's address when + * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [1]; default: 0; + * Configures whether or not to stop AHB_DMA's RX channel n from receiving data.\\0: + * Invalid. No effect\\1: Stop\\ + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable AHB_DMA's RX channel n for data transfer.\\0: + * Disable\\1: Enable\\ + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [3]; default: 0; + * Configures whether or not to restart RX channel n for AHB_DMA transfer.\\0: + * Invalid. No effect\\1: Restart\\ + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of out_conf0_ch0 register + * Configuration register 0 of TX channel 0 + */ +typedef union { + struct { + /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0: + * Release reset\\1: Reset\\ + */ + uint32_t out_rst_ch0:1; + /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t out_loop_test_ch0:1; + /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable automatic outlink write-back when all the data + * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + */ + uint32_t out_auto_wrback_ch0:1; + /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated + * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for + * TX channel 0 is generated when data to be transmitted has been popped from FIFO in + * AHB_DMA.\\ + */ + uint32_t out_eof_mode_ch0:1; + /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable INCR burst transfer for TX channel 0 reading + * descriptors.\\0: Disable\\1: Enable\\ + */ + uint32_t outdscr_burst_en_ch0:1; + uint32_t reserved_5:1; + /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1: + * Enable\\ + */ + uint32_t out_etm_en_ch0:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ + uint32_t out_data_burst_mode_sel_ch0:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_conf0_ch0_reg_t; + +/** Type of out_conf1_chn register + * Configuration register 1 of TX channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable owner bit check for TX channel n.\\0: + * Disable\\1: Enable\\ + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of TX channel 0 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No + * effect\\1: Push\\ + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Linked list descriptor configuration and control register of TX channel 0 + */ +typedef union { + struct { + /** outlink_stop_chn : WT; bitpos: [0]; default: 0; + * Configures whether or not to stop AHB_DMA's TX channel n from transmitting + * data.\\0: Invalid. No effect\\1: Stop\\ + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable AHB_DMA's TX channel n for data transfer.\\0: + * Disable\\1: Enable\\ + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [2]; default: 0; + * Configures whether or not to restart TX channel n for AHB_DMA transfer.\\0: + * Invalid. No effect\\1: Restart\\ + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_conf0_chn register + * Configuration register 0 of TX channel 1 + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel n TX FSM and TX FIFO pointer.\\0: + * Release reset\\1: Reset\\ + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable automatic outlink write-back when all the data + * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag.\\0: EOF flag for TX channel n is generated + * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for + * TX channel n is generated when data to be transmitted has been popped from FIFO in + * AHB_DMA.\\ + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable INCR burst transfer for TX channel n reading + * descriptors.\\0: Disable\\1: Enable\\ + */ + uint32_t outdscr_burst_en_chn:1; + uint32_t reserved_5:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ETM control for TX channel n.\\0: Disable\\1: + * Enable\\ + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: + * incr8\\ 2'b11: incr16\\ + */ + uint32_t out_data_burst_mode_sel_chn:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of tx_ch_arb_weigh_chn register + * TX channel 0 arbitration weight configuration register + */ +typedef union { + struct { + /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channeln + */ + uint32_t tx_ch_arb_weigh_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_tx_ch_arb_weigh_chn_reg_t; + +/** Type of tx_arb_weigh_opt_dir_chn register + * TX channel 0 weight arbitration optimization enable register + */ +typedef union { + struct { + /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t tx_arb_weigh_opt_dir_chn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gdma_tx_arb_weigh_opt_dir_chn_reg_t; + +/** Type of rx_ch_arb_weigh_chn register + * RX channel 0 arbitration weight configuration register + */ +typedef union { + struct { + /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channeln + */ + uint32_t rx_ch_arb_weigh_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_rx_ch_arb_weigh_chn_reg_t; + +/** Type of rx_arb_weigh_opt_dir_chn register + * RX channel 0 weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weigh_opt_dir_chn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gdma_rx_arb_weigh_opt_dir_chn_reg_t; + +/** Type of in_link_addr_chn register + * Link list descriptor address configuration of RX channel 0 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ + uint32_t inlink_addr_chn:32; + }; + uint32_t val; +} gdma_in_link_addr_chn_reg_t; + +/** Type of out_link_addr_chn register + * Link list descriptor address configuration of TX channel 0 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ + uint32_t outlink_addr_chn:32; + }; + uint32_t val; +} gdma_out_link_addr_chn_reg_t; + +/** Type of intr_mem_start_addr register + * Accessible address space start address configuration register + */ +typedef union { + struct { + /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Configures the start address of accessible address space. + */ + uint32_t access_intr_mem_start_addr:32; + }; + uint32_t val; +} gdma_intr_mem_start_addr_reg_t; + +/** Type of intr_mem_end_addr register + * Accessible address space end address configuration register + */ +typedef union { + struct { + /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of accessible address space. + */ + uint32_t access_intr_mem_end_addr:32; + }; + uint32_t val; +} gdma_intr_mem_end_addr_reg_t; + +/** Type of arb_timeout_tx register + * TX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_tx:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gdma_arb_timeout_tx_reg_t; + +/** Type of arb_timeout_rx register + * RX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_rx:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gdma_arb_timeout_rx_reg_t; + +/** Type of weight_en_tx register + * TX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en_tx : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ + */ + uint32_t weight_en_tx:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gdma_weight_en_tx_reg_t; + +/** Type of weight_en_rx register + * RX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en_rx : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ + */ + uint32_t weight_en_rx:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gdma_weight_en_rx_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36770448; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Status Registers */ +/** Type of infifo_status_chn register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + */ + uint32_t infifo_empty_chn:1; + uint32_t reserved_2:6; + /** infifo_cnt_chn : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel n. + */ + uint32_t infifo_cnt_chn:7; + uint32_t reserved_15:8; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Receive descriptor address when EOF occurs on RX channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Receive descriptor address when errors occur of RX channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_done_des_addr_chn register + * RX_done Inlink descriptor address of RX channel 0 + */ +typedef union { + struct { + /** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_done_des_addr_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of TX channel 0 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + */ + uint32_t outfifo_empty_chn:1; + uint32_t reserved_2:6; + /** outfifo_cnt_chn : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel n. + */ + uint32_t outfifo_cnt_chn:7; + uint32_t reserved_15:8; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * Reserved. + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * Reserved. + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * Reserved. + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * Reserved. + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Transmit descriptor address when EOF occurs on TX channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last transmit descriptor address when EOF occurs on TX channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_done_des_addr_chn register + * TX done outlink descriptor address of TX channel 0 + */ +typedef union { + struct { + /** out_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ + uint32_t out_done_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_done_des_addr_chn_reg_t; + + +/** Group: Priority Registers */ +/** Type of in_pri_chn register + * Priority register of RX channel 0 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel n.The larger of the value, the higher of the + * priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of TX channel 0 + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel n.The larger of the value, the higher of the + * priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of in_peri_sel_chn register + * Peripheral selection register of RX channel 0 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: + * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ + * 10: Dummy\\ 11~15: Dummy\\ + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection register of TX channel 0 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: + * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ + * 10: Dummy\\ 11~15: Dummy\\ + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +typedef struct { + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; + uint32_t reserved_020[4]; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; + uint32_t reserved_050[4]; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; + volatile gdma_in_pop_chn_reg_t in_pop_ch0; + volatile gdma_in_link_chn_reg_t in_link_ch0; + volatile gdma_in_state_chn_reg_t in_state_ch0; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; + volatile gdma_in_pri_chn_reg_t in_pri_ch0; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; + uint32_t reserved_0a4[3]; + volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0; + uint32_t reserved_0b4[7]; + volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; + volatile gdma_out_push_chn_reg_t out_push_ch0; + volatile gdma_out_link_chn_reg_t out_link_ch0; + volatile gdma_out_state_chn_reg_t out_state_ch0; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; + volatile gdma_out_pri_chn_reg_t out_pri_ch0; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; + uint32_t reserved_104[3]; + volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0; + uint32_t reserved_114[7]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; + volatile gdma_in_pop_chn_reg_t in_pop_ch1; + volatile gdma_in_link_chn_reg_t in_link_ch1; + volatile gdma_in_state_chn_reg_t in_state_ch1; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; + volatile gdma_in_pri_chn_reg_t in_pri_ch1; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; + uint32_t reserved_164[3]; + volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch1; + uint32_t reserved_174[7]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; + volatile gdma_out_push_chn_reg_t out_push_ch1; + volatile gdma_out_link_chn_reg_t out_link_ch1; + volatile gdma_out_state_chn_reg_t out_state_ch1; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; + volatile gdma_out_pri_chn_reg_t out_pri_ch1; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; + uint32_t reserved_1c4[3]; + volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch1; + uint32_t reserved_1d4[66]; + volatile gdma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch0; + volatile gdma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch0; + uint32_t reserved_2e4[8]; + volatile gdma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch1; + volatile gdma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch1; + uint32_t reserved_30c[18]; + volatile gdma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch0; + volatile gdma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch0; + uint32_t reserved_35c[8]; + volatile gdma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch1; + volatile gdma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch1; + uint32_t reserved_384[10]; + volatile gdma_in_link_addr_chn_reg_t in_link_addr_chn[2]; + uint32_t reserved_3b4; + volatile gdma_out_link_addr_chn_reg_t out_link_addr_chn[2]; + uint32_t reserved_3c0; + volatile gdma_intr_mem_start_addr_reg_t intr_mem_start_addr; + volatile gdma_intr_mem_end_addr_reg_t intr_mem_end_addr; + volatile gdma_arb_timeout_tx_reg_t arb_timeout_tx; + volatile gdma_arb_timeout_rx_reg_t arb_timeout_rx; + volatile gdma_weight_en_tx_reg_t weight_en_tx; + volatile gdma_weight_en_rx_reg_t weight_en_rx; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x3dc, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_ext_reg.h b/components/soc/esp32c61/include/soc/gpio_ext_reg.h new file mode 100644 index 0000000000..26effdee28 --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_ext_reg.h @@ -0,0 +1,964 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_EXT_CLOCK_GATE_REG register + * Clock Gating Configure Register + */ +#define GPIO_EXT_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x0) +/** GPIO_EXT_CLK_EN : R/W; bitpos: [0]; default: 0; + * Clock enable bit of configuration registers for sigma delta modulation. + */ +#define GPIO_EXT_CLK_EN (BIT(0)) +#define GPIO_EXT_CLK_EN_M (GPIO_EXT_CLK_EN_V << GPIO_EXT_CLK_EN_S) +#define GPIO_EXT_CLK_EN_V 0x00000001U +#define GPIO_EXT_CLK_EN_S 0 + +/** GPIO_EXT_PAD_COMP_CONFIG_0_REG register + * Configuration register for zero-crossing detection + */ +#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58) +/** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0; + * Configures whether to enable the function of analog PAD voltage comparator.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_XPD_COMP_0 (BIT(0)) +#define GPIO_EXT_XPD_COMP_0_M (GPIO_EXT_XPD_COMP_0_V << GPIO_EXT_XPD_COMP_0_S) +#define GPIO_EXT_XPD_COMP_0_V 0x00000001U +#define GPIO_EXT_XPD_COMP_0_S 0 +/** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0; + * Configures the reference voltage for analog PAD voltage comparater.. \\ + * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be + * used as a regular GPIO\\ + * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + */ +#define GPIO_EXT_MODE_COMP_0 (BIT(1)) +#define GPIO_EXT_MODE_COMP_0_M (GPIO_EXT_MODE_COMP_0_V << GPIO_EXT_MODE_COMP_0_S) +#define GPIO_EXT_MODE_COMP_0_V 0x00000001U +#define GPIO_EXT_MODE_COMP_0_S 1 +/** GPIO_EXT_DREF_COMP_0 : R/W; bitpos: [4:2]; default: 0; + * Configures the internal reference voltage for analog PAD voltage coparator. \\ + * 0: Internal reference voltage is 0 * VDDPST1\\ + * 1: Internal reference voltage is 0.1 * VDDPST1\\ + * ......\\ + * 6: Internal reference voltage is 0.6 * VDDPST1\\ + * 7: Internal reference voltage is 0.7 * VDDPST1\\ + */ +#define GPIO_EXT_DREF_COMP_0 0x00000007U +#define GPIO_EXT_DREF_COMP_0_M (GPIO_EXT_DREF_COMP_0_V << GPIO_EXT_DREF_COMP_0_S) +#define GPIO_EXT_DREF_COMP_0_V 0x00000007U +#define GPIO_EXT_DREF_COMP_0_S 2 + +/** GPIO_EXT_PAD_COMP_FILTER_0_REG register + * Configuration register for interrupt source mask period of zero-crossing detection + */ +#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c) +/** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the period of masking new interrupt source foe analog PAD voltage + * comparator.\\ + * Measurement unit: IO MUX operating clock cycle\\ + */ +#define GPIO_EXT_ZERO_DET_FILTER_CNT_0 0xFFFFFFFFU +#define GPIO_EXT_ZERO_DET_FILTER_CNT_0_M (GPIO_EXT_ZERO_DET_FILTER_CNT_0_V << GPIO_EXT_ZERO_DET_FILTER_CNT_0_S) +#define GPIO_EXT_ZERO_DET_FILTER_CNT_0_V 0xFFFFFFFFU +#define GPIO_EXT_ZERO_DET_FILTER_CNT_0_S 0 + +/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c) +/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH1_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH1_EVENT_SEL_M (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH1_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH1_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH1_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH1_EVENT_EN_M (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S) +#define GPIO_EXT_ETM_CH1_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH1_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120) +/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH2_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH2_EVENT_SEL_M (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH2_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH2_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH2_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH2_EVENT_EN_M (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S) +#define GPIO_EXT_ETM_CH2_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH2_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124) +/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH3_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH3_EVENT_SEL_M (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH3_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH3_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH3_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH3_EVENT_EN_M (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S) +#define GPIO_EXT_ETM_CH3_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH3_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128) +/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH4_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH4_EVENT_SEL_M (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH4_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH4_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH4_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH4_EVENT_EN_M (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S) +#define GPIO_EXT_ETM_CH4_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH4_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c) +/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH5_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH5_EVENT_SEL_M (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH5_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH5_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH5_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH5_EVENT_EN_M (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S) +#define GPIO_EXT_ETM_CH5_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH5_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130) +/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH6_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH6_EVENT_SEL_M (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH6_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH6_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH6_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH6_EVENT_EN_M (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S) +#define GPIO_EXT_ETM_CH6_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH6_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register + * ETM configuration register for channel 0 + */ +#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134) +/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ +#define GPIO_EXT_ETM_CH7_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH7_EVENT_SEL_M (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH7_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH7_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_CH7_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH7_EVENT_EN_M (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S) +#define GPIO_EXT_ETM_CH7_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH7_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_TASK_P0_CFG_REG register + * GPIO selection register 0 for ETM + */ +#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158) +/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO0.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO0 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO0_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO1.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO1 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO1_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO2.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO2 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO2_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO3.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO3 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO3_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO4.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO4 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO4_EN_S 29 + +/** GPIO_EXT_ETM_TASK_P1_CFG_REG register + * GPIO selection register 1 for ETM + */ +#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c) +/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO5.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO5 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO5_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO6.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO6 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO6_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO7.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO7 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO7_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO8.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO8 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO8_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO9.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO9 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO9_EN_S 29 + +/** GPIO_EXT_ETM_TASK_P2_CFG_REG register + * GPIO selection register 2 for ETM + */ +#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160) +/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO10.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO10 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO10_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO11.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO11 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO11_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO12.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO12 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO12_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO13.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO13 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO13_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO14.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO14 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO14_EN_S 29 + +/** GPIO_EXT_ETM_TASK_P3_CFG_REG register + * GPIO selection register 3 for ETM + */ +#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164) +/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO15.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO15 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO15_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO16.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO16 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO16_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO17.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO17 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO17_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO18.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO18 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO18_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO19.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO19 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO19_EN_S 29 + +/** GPIO_EXT_ETM_TASK_P4_CFG_REG register + * GPIO selection register 4 for ETM + */ +#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168) +/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO20.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO20 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO20_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO21.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO21 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO21_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO22.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO22 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO22_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO23.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO23 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO23_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO24.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO24 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ +#define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO24_EN_S 29 + +/** GPIO_EXT_INT_RAW_REG register + * GPIO_EXT interrupt raw register + */ +#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0x1d0) +/** GPIO_EXT_COMP_NEG_0_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt raw + */ +#define GPIO_EXT_COMP_NEG_0_INT_RAW (BIT(0)) +#define GPIO_EXT_COMP_NEG_0_INT_RAW_M (GPIO_EXT_COMP_NEG_0_INT_RAW_V << GPIO_EXT_COMP_NEG_0_INT_RAW_S) +#define GPIO_EXT_COMP_NEG_0_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP_NEG_0_INT_RAW_S 0 +/** GPIO_EXT_COMP_POS_0_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt raw + */ +#define GPIO_EXT_COMP_POS_0_INT_RAW (BIT(1)) +#define GPIO_EXT_COMP_POS_0_INT_RAW_M (GPIO_EXT_COMP_POS_0_INT_RAW_V << GPIO_EXT_COMP_POS_0_INT_RAW_S) +#define GPIO_EXT_COMP_POS_0_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP_POS_0_INT_RAW_S 1 +/** GPIO_EXT_COMP_ALL_0_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt raw + */ +#define GPIO_EXT_COMP_ALL_0_INT_RAW (BIT(2)) +#define GPIO_EXT_COMP_ALL_0_INT_RAW_M (GPIO_EXT_COMP_ALL_0_INT_RAW_V << GPIO_EXT_COMP_ALL_0_INT_RAW_S) +#define GPIO_EXT_COMP_ALL_0_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP_ALL_0_INT_RAW_S 2 + +/** GPIO_EXT_INT_ST_REG register + * GPIO_EXT interrupt masked register + */ +#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0x1d4) +/** GPIO_EXT_COMP_NEG_0_INT_ST : RO; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt status + */ +#define GPIO_EXT_COMP_NEG_0_INT_ST (BIT(0)) +#define GPIO_EXT_COMP_NEG_0_INT_ST_M (GPIO_EXT_COMP_NEG_0_INT_ST_V << GPIO_EXT_COMP_NEG_0_INT_ST_S) +#define GPIO_EXT_COMP_NEG_0_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP_NEG_0_INT_ST_S 0 +/** GPIO_EXT_COMP_POS_0_INT_ST : RO; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt status + */ +#define GPIO_EXT_COMP_POS_0_INT_ST (BIT(1)) +#define GPIO_EXT_COMP_POS_0_INT_ST_M (GPIO_EXT_COMP_POS_0_INT_ST_V << GPIO_EXT_COMP_POS_0_INT_ST_S) +#define GPIO_EXT_COMP_POS_0_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP_POS_0_INT_ST_S 1 +/** GPIO_EXT_COMP_ALL_0_INT_ST : RO; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt status + */ +#define GPIO_EXT_COMP_ALL_0_INT_ST (BIT(2)) +#define GPIO_EXT_COMP_ALL_0_INT_ST_M (GPIO_EXT_COMP_ALL_0_INT_ST_V << GPIO_EXT_COMP_ALL_0_INT_ST_S) +#define GPIO_EXT_COMP_ALL_0_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP_ALL_0_INT_ST_S 2 + +/** GPIO_EXT_INT_ENA_REG register + * GPIO_EXT interrupt enable register + */ +#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0x1d8) +/** GPIO_EXT_COMP_NEG_0_INT_ENA : R/W; bitpos: [0]; default: 1; + * analog comparator pos edge interrupt enable + */ +#define GPIO_EXT_COMP_NEG_0_INT_ENA (BIT(0)) +#define GPIO_EXT_COMP_NEG_0_INT_ENA_M (GPIO_EXT_COMP_NEG_0_INT_ENA_V << GPIO_EXT_COMP_NEG_0_INT_ENA_S) +#define GPIO_EXT_COMP_NEG_0_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP_NEG_0_INT_ENA_S 0 +/** GPIO_EXT_COMP_POS_0_INT_ENA : R/W; bitpos: [1]; default: 1; + * analog comparator neg edge interrupt enable + */ +#define GPIO_EXT_COMP_POS_0_INT_ENA (BIT(1)) +#define GPIO_EXT_COMP_POS_0_INT_ENA_M (GPIO_EXT_COMP_POS_0_INT_ENA_V << GPIO_EXT_COMP_POS_0_INT_ENA_S) +#define GPIO_EXT_COMP_POS_0_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP_POS_0_INT_ENA_S 1 +/** GPIO_EXT_COMP_ALL_0_INT_ENA : R/W; bitpos: [2]; default: 1; + * analog comparator neg or pos edge interrupt enable + */ +#define GPIO_EXT_COMP_ALL_0_INT_ENA (BIT(2)) +#define GPIO_EXT_COMP_ALL_0_INT_ENA_M (GPIO_EXT_COMP_ALL_0_INT_ENA_V << GPIO_EXT_COMP_ALL_0_INT_ENA_S) +#define GPIO_EXT_COMP_ALL_0_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP_ALL_0_INT_ENA_S 2 + +/** GPIO_EXT_INT_CLR_REG register + * GPIO_EXT interrupt clear register + */ +#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0x1dc) +/** GPIO_EXT_COMP_NEG_0_INT_CLR : WT; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt clear + */ +#define GPIO_EXT_COMP_NEG_0_INT_CLR (BIT(0)) +#define GPIO_EXT_COMP_NEG_0_INT_CLR_M (GPIO_EXT_COMP_NEG_0_INT_CLR_V << GPIO_EXT_COMP_NEG_0_INT_CLR_S) +#define GPIO_EXT_COMP_NEG_0_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP_NEG_0_INT_CLR_S 0 +/** GPIO_EXT_COMP_POS_0_INT_CLR : WT; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt clear + */ +#define GPIO_EXT_COMP_POS_0_INT_CLR (BIT(1)) +#define GPIO_EXT_COMP_POS_0_INT_CLR_M (GPIO_EXT_COMP_POS_0_INT_CLR_V << GPIO_EXT_COMP_POS_0_INT_CLR_S) +#define GPIO_EXT_COMP_POS_0_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP_POS_0_INT_CLR_S 1 +/** GPIO_EXT_COMP_ALL_0_INT_CLR : WT; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt clear + */ +#define GPIO_EXT_COMP_ALL_0_INT_CLR (BIT(2)) +#define GPIO_EXT_COMP_ALL_0_INT_CLR_M (GPIO_EXT_COMP_ALL_0_INT_CLR_V << GPIO_EXT_COMP_ALL_0_INT_CLR_S) +#define GPIO_EXT_COMP_ALL_0_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP_ALL_0_INT_CLR_S 2 + +/** GPIO_EXT_PIN_CTRL_REG register + * Clock Output Configuration Register + */ +#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0) +/** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ +#define GPIO_EXT_CLK_OUT1 0x0000001FU +#define GPIO_EXT_CLK_OUT1_M (GPIO_EXT_CLK_OUT1_V << GPIO_EXT_CLK_OUT1_S) +#define GPIO_EXT_CLK_OUT1_V 0x0000001FU +#define GPIO_EXT_CLK_OUT1_S 0 +/** GPIO_EXT_CLK_OUT2 : R/W; bitpos: [9:5]; default: 0; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ +#define GPIO_EXT_CLK_OUT2 0x0000001FU +#define GPIO_EXT_CLK_OUT2_M (GPIO_EXT_CLK_OUT2_V << GPIO_EXT_CLK_OUT2_S) +#define GPIO_EXT_CLK_OUT2_V 0x0000001FU +#define GPIO_EXT_CLK_OUT2_S 5 +/** GPIO_EXT_CLK_OUT3 : R/W; bitpos: [14:10]; default: 0; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ +#define GPIO_EXT_CLK_OUT3 0x0000001FU +#define GPIO_EXT_CLK_OUT3_M (GPIO_EXT_CLK_OUT3_V << GPIO_EXT_CLK_OUT3_S) +#define GPIO_EXT_CLK_OUT3_V 0x0000001FU +#define GPIO_EXT_CLK_OUT3_S 10 + +/** GPIO_EXT_VERSION_REG register + * Version control register + */ +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc) +/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37753392; + * Version control register. + */ +#define GPIO_EXT_DATE 0x0FFFFFFFU +#define GPIO_EXT_DATE_M (GPIO_EXT_DATE_V << GPIO_EXT_DATE_S) +#define GPIO_EXT_DATE_V 0x0FFFFFFFU +#define GPIO_EXT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_ext_struct.h b/components/soc/esp32c61/include/soc/gpio_ext_struct.h new file mode 100644 index 0000000000..f02a5fec8a --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_ext_struct.h @@ -0,0 +1,693 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Clock gate Register */ +/** Type of clock_gate register + * Clock Gating Configure Register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Clock enable bit of configuration registers for sigma delta modulation. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_ext_clock_gate_reg_t; + + +/** Group: Configure Registers */ +/** Type of pad_comp_config_0 register + * Configuration register for zero-crossing detection + */ +typedef union { + struct { + /** xpd_comp_0 : R/W; bitpos: [0]; default: 0; + * Configures whether to enable the function of analog PAD voltage comparator.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t xpd_comp_0:1; + /** mode_comp_0 : R/W; bitpos: [1]; default: 0; + * Configures the reference voltage for analog PAD voltage comparater.. \\ + * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be + * used as a regular GPIO\\ + * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + */ + uint32_t mode_comp_0:1; + /** dref_comp_0 : R/W; bitpos: [4:2]; default: 0; + * Configures the internal reference voltage for analog PAD voltage coparator. \\ + * 0: Internal reference voltage is 0 * VDDPST1\\ + * 1: Internal reference voltage is 0.1 * VDDPST1\\ + * ......\\ + * 6: Internal reference voltage is 0.6 * VDDPST1\\ + * 7: Internal reference voltage is 0.7 * VDDPST1\\ + */ + uint32_t dref_comp_0:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} gpio_ext_pad_comp_config_0_reg_t; + +/** Type of pad_comp_filter_0 register + * Configuration register for interrupt source mask period of zero-crossing detection + */ +typedef union { + struct { + /** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the period of masking new interrupt source foe analog PAD voltage + * comparator.\\ + * Measurement unit: IO MUX operating clock cycle\\ + */ + uint32_t zero_det_filter_cnt_0:32; + }; + uint32_t val; +} gpio_ext_pad_comp_filter_0_reg_t; + +/** Type of pin_ctrl register + * Clock Output Configuration Register + */ +typedef union { + struct { + /** clk_out1 : R/W; bitpos: [4:0]; default: 0; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ + uint32_t clk_out1:5; + /** clk_out2 : R/W; bitpos: [9:5]; default: 0; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ + uint32_t clk_out2:5; + /** clk_out3 : R/W; bitpos: [14:10]; default: 0; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ + uint32_t clk_out3:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} gpio_ext_pin_ctrl_reg_t; + + +/** Group: ETM Configuration Registers */ +/** Type of etm_event_chn_cfg register + * ETM configuration register for channel 0 + */ +typedef union { + struct { + /** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0; + * Configures to select GPIO for ETM event channel.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * 25 ~ 31: Reserved\\ + */ + uint32_t etm_chn_event_sel:5; + uint32_t reserved_5:2; + /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_chn_event_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_ext_etm_event_chn_cfg_reg_t; + +/** Type of etm_task_p0_cfg register + * GPIO selection register 0 for ETM + */ +typedef union { + struct { + /** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO0.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio0_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO0 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio0_en:1; + /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO1.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio1_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO1 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio1_en:1; + /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO2.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio2_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO2 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio2_en:1; + /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO3.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio3_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO3 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio3_en:1; + /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO4.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio4_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO4 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio4_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p0_cfg_reg_t; + +/** Type of etm_task_p1_cfg register + * GPIO selection register 1 for ETM + */ +typedef union { + struct { + /** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO5.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio5_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO5 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio5_en:1; + /** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO6.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio6_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO6 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio6_en:1; + /** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO7.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio7_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO7 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio7_en:1; + /** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO8.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio8_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO8 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio8_en:1; + /** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO9.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio9_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO9 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio9_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p1_cfg_reg_t; + +/** Type of etm_task_p2_cfg register + * GPIO selection register 2 for ETM + */ +typedef union { + struct { + /** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO10.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio10_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO10 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio10_en:1; + /** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO11.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio11_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO11 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio11_en:1; + /** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO12.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio12_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO12 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio12_en:1; + /** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO13.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio13_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO13 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio13_en:1; + /** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO14.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio14_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO14 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio14_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p2_cfg_reg_t; + +/** Type of etm_task_p3_cfg register + * GPIO selection register 3 for ETM + */ +typedef union { + struct { + /** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO15.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio15_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO15 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio15_en:1; + /** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO16.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio16_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO16 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio16_en:1; + /** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO17.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio17_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO17 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio17_en:1; + /** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO18.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio18_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO18 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio18_en:1; + /** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO19.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio19_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO19 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio19_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p3_cfg_reg_t; + +/** Type of etm_task_p4_cfg register + * GPIO selection register 4 for ETM + */ +typedef union { + struct { + /** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0; + * Configures to select an ETM task channel for GPIO20.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio20_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable GPIO20 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio20_en:1; + /** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0; + * Configures to select an ETM task channel for GPIO21.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio21_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable GPIO21 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio21_en:1; + /** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0; + * Configures to select an ETM task channel for GPIO22.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio22_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable GPIO22 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio22_en:1; + /** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0; + * Configures to select an ETM task channel for GPIO23.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio23_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable GPIO23 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio23_en:1; + /** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0; + * Configures to select an ETM task channel for GPIO24.\\ + * 0: Select channel 0\\ + * 1: Select channel 1\\ + * ......\\ + * 7: Select channel 7\\ + */ + uint32_t etm_task_gpio24_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable GPIO24 to response ETM task.\\ + * 0: Not enable\\ + * 1: Enable\\ + */ + uint32_t etm_task_gpio24_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p4_cfg_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * GPIO_EXT interrupt raw register + */ +typedef union { + struct { + /** comp_neg_0_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt raw + */ + uint32_t comp_neg_0_int_raw:1; + /** comp_pos_0_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt raw + */ + uint32_t comp_pos_0_int_raw:1; + /** comp_all_0_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt raw + */ + uint32_t comp_all_0_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_raw_reg_t; + +/** Type of int_st register + * GPIO_EXT interrupt masked register + */ +typedef union { + struct { + /** comp_neg_0_int_st : RO; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt status + */ + uint32_t comp_neg_0_int_st:1; + /** comp_pos_0_int_st : RO; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt status + */ + uint32_t comp_pos_0_int_st:1; + /** comp_all_0_int_st : RO; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt status + */ + uint32_t comp_all_0_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_st_reg_t; + +/** Type of int_ena register + * GPIO_EXT interrupt enable register + */ +typedef union { + struct { + /** comp_neg_0_int_ena : R/W; bitpos: [0]; default: 1; + * analog comparator pos edge interrupt enable + */ + uint32_t comp_neg_0_int_ena:1; + /** comp_pos_0_int_ena : R/W; bitpos: [1]; default: 1; + * analog comparator neg edge interrupt enable + */ + uint32_t comp_pos_0_int_ena:1; + /** comp_all_0_int_ena : R/W; bitpos: [2]; default: 1; + * analog comparator neg or pos edge interrupt enable + */ + uint32_t comp_all_0_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_ena_reg_t; + +/** Type of int_clr register + * GPIO_EXT interrupt clear register + */ +typedef union { + struct { + /** comp_neg_0_int_clr : WT; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt clear + */ + uint32_t comp_neg_0_int_clr:1; + /** comp_pos_0_int_clr : WT; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt clear + */ + uint32_t comp_pos_0_int_clr:1; + /** comp_all_0_int_clr : WT; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt clear + */ + uint32_t comp_all_0_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37753392; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_version_reg_t; + + +typedef struct { + volatile gpio_ext_clock_gate_reg_t clock_gate; + uint32_t reserved_004[21]; + volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0; + volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0; + uint32_t reserved_060[46]; + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_138[8]; + volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg; + volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg; + volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg; + volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg; + volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg; + uint32_t reserved_16c[25]; + volatile gpio_ext_int_raw_reg_t int_raw; + volatile gpio_ext_int_st_reg_t int_st; + volatile gpio_ext_int_ena_reg_t int_ena; + volatile gpio_ext_int_clr_reg_t int_clr; + volatile gpio_ext_pin_ctrl_reg_t pin_ctrl; + uint32_t reserved_1e4[6]; + volatile gpio_ext_version_reg_t version; +} gpio_ext_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_reg.h b/components/soc/esp32c61/include/soc/gpio_reg.h new file mode 100644 index 0000000000..15e4093f27 --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_reg.h @@ -0,0 +1,5688 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_STRAP_REG register + * Strapping pin register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * Represents the values of GPIO strapping pins. + * + * - bit0 ~ bit1: invalid + * - bit2: GPIO8 + * - bit3: GPIO9 + * - bit4: GPIO7 + * - bit5 ~ bit15: invalid + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU +#define GPIO_STRAPPING_S 0 + +/** GPIO_OUT_REG register + * GPIO output register + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [28:0]; default: 0; + * Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\ + * 0: Low level\\ + * 1: High level\\ + * The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24 + * respectively. Bit25 ~ bit31 are invalid.\\ + */ +#define GPIO_OUT_DATA_ORIG 0x1FFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0x1FFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 + +/** GPIO_OUT_W1TS_REG register + * GPIO output set register + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ + * GPIO24.\\ + * 0: Not set\\ + * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set GPIO_OUT_REG. \\ + */ +#define GPIO_OUT_W1TS 0x1FFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0x1FFFFFFFU +#define GPIO_OUT_W1TS_S 0 + +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ + * GPIO24 output.\\ + * 0: Not clear\\ + * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear GPIO_OUT_REG. \\ + */ +#define GPIO_OUT_W1TC 0x1FFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0x1FFFFFFFU +#define GPIO_OUT_W1TC_S 0 + +/** GPIO_ENABLE_REG register + * GPIO output enable register + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34) +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [28:0]; default: 0; + * Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\ + * 0: Not enable\\ + * 1: Enable\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + */ +#define GPIO_ENABLE_DATA 0x1FFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0x1FFFFFFFU +#define GPIO_ENABLE_DATA_S 0 + +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_ENABLE_W1TS : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to set the output enable register GPIO_ENABLE_REG of + * GPIO0 ~ GPIO24.\\ + * 0: Not set\\ + * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ + */ +#define GPIO_ENABLE_W1TS 0x1FFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0x1FFFFFFFU +#define GPIO_ENABLE_W1TS_S 0 + +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_ENABLE_W1TC : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of + * GPIO0 ~ GPIO24. \\ + * 0: Not clear\\ + * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ + */ +#define GPIO_ENABLE_W1TC 0x1FFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0x1FFFFFFFU +#define GPIO_ENABLE_W1TC_S 0 + +/** GPIO_IN_REG register + * GPIO input register + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [28:0]; default: 0; + * Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input + * value:\\ + * 0: Low level\\ + * 1: High level\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + */ +#define GPIO_IN_DATA_NEXT 0x1FFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0x1FFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 + +/** GPIO_STATUS_REG register + * GPIO interrupt status register + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [28:0]; default: 0; + * The interrupt status of GPIO0 ~ GPIO24, can be configured by the software. + * + * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. + * - Each bit represents the status of its corresponding GPIO: + * + * - 0: Represents the GPIO does not generate the interrupt configured by + * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, + * or this bit is configured to 1 by the software. + * + */ +#define GPIO_STATUS_INTERRUPT 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 + +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_STATUS_W1TS : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to set the interrupt status register + * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. + * + * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set GPIO_STATUS_INTERRUPT. + */ +#define GPIO_STATUS_W1TS 0x1FFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0x1FFFFFFFU +#define GPIO_STATUS_W1TS_S 0 + +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_STATUS_W1TC : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to clear the interrupt status register + * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. + * + * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear GPIO_STATUS_INTERRUPT. + */ +#define GPIO_STATUS_W1TC 0x1FFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0x1FFFFFFFU +#define GPIO_STATUS_W1TC_S 0 + +/** GPIO_PROCPU_INT_REG register + * CPU interrupt status register + */ +#define GPIO_PROCPU_INT_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PROCPU_INT : RO; bitpos: [28:0]; default: 0; + * Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\ + * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the + * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the CPU interrupt is enabled.\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). \\ + */ +#define GPIO_PROCPU_INT 0x1FFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0x1FFFFFFFU +#define GPIO_PROCPU_INT_S 0 + +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [28:0]; default: 0; + * Represents the interrupt source signal of GPIO0 ~ GPIO24.\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each + * bit represents:\\ + * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt.\\ + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** GPIO_PIN0_REG register + * GPIO0 configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 + +/** GPIO_PIN1_REG register + * GPIO1 configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 + +/** GPIO_PIN2_REG register + * GPIO2 configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 + +/** GPIO_PIN3_REG register + * GPIO3 configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 + +/** GPIO_PIN4_REG register + * GPIO4 configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 + +/** GPIO_PIN5_REG register + * GPIO5 configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 + +/** GPIO_PIN6_REG register + * GPIO6 configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 + +/** GPIO_PIN7_REG register + * GPIO7 configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 + +/** GPIO_PIN8_REG register + * GPIO8 configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 + +/** GPIO_PIN9_REG register + * GPIO9 configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 + +/** GPIO_PIN10_REG register + * GPIO10 configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xec) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 + +/** GPIO_PIN11_REG register + * GPIO11 configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xf0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 + +/** GPIO_PIN12_REG register + * GPIO12 configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xf4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 + +/** GPIO_PIN13_REG register + * GPIO13 configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xf8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 + +/** GPIO_PIN14_REG register + * GPIO14 configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xfc) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 + +/** GPIO_PIN15_REG register + * GPIO15 configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x100) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 + +/** GPIO_PIN16_REG register + * GPIO16 configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x104) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 + +/** GPIO_PIN17_REG register + * GPIO17 configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x108) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 + +/** GPIO_PIN18_REG register + * GPIO18 configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x10c) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 + +/** GPIO_PIN19_REG register + * GPIO19 configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x110) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 + +/** GPIO_PIN20_REG register + * GPIO20 configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x114) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 + +/** GPIO_PIN21_REG register + * GPIO21 configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x118) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 + +/** GPIO_PIN22_REG register + * GPIO22 configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 + +/** GPIO_PIN23_REG register + * GPIO23 configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 + +/** GPIO_PIN24_REG register + * GPIO24 configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 + +/** GPIO_PIN25_REG register + * GPIO25 configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x128) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO26 configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x12c) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO27 configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x130) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO28 configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x134) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * Configuration register for input signal 0 + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 7 + +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * Configuration register for input signal 6 + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 6.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 7 + +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * Configuration register for input signal 7 + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 7.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 7 + +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * Configuration register for input signal 8 + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 8.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 7 + +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * Configuration register for input signal 9 + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 9.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 7 + +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * Configuration register for input signal 10 + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 10.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 7 + +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * Configuration register for input signal 11 + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 11.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 7 + +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * Configuration register for input signal 12 + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 12.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 7 + +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * Configuration register for input signal 13 + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 13.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 7 + +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * Configuration register for input signal 14 + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 14.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 7 + +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * Configuration register for input signal 15 + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 15.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 7 + +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * Configuration register for input signal 16 + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 16.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 7 + +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * Configuration register for input signal 17 + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 17.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 7 + +/** GPIO_FUNC27_IN_SEL_CFG_REG register + * Configuration register for input signal 27 + */ +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 27.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC27_IN_SEL 0x0000003FU +#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) +#define GPIO_FUNC27_IN_SEL_V 0x0000003FU +#define GPIO_FUNC27_IN_SEL_S 0 +/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) +#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_IN_INV_SEL_S 6 +/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) +#define GPIO_SIG27_IN_SEL_V 0x00000001U +#define GPIO_SIG27_IN_SEL_S 7 + +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * Configuration register for input signal 28 + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 28.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 7 + +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * Configuration register for input signal 29 + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 29.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 7 + +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * Configuration register for input signal 30 + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 30.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 7 + +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * Configuration register for input signal 31 + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 31.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 7 + +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * Configuration register for input signal 32 + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 32.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 7 + +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * Configuration register for input signal 33 + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 33.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 7 + +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * Configuration register for input signal 34 + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 34.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 7 + +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * Configuration register for input signal 35 + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 35.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 7 + +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * Configuration register for input signal 41 + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 41.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 7 + +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * Configuration register for input signal 42 + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 42.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 7 + +/** GPIO_FUNC43_IN_SEL_CFG_REG register + * Configuration register for input signal 43 + */ +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) +/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 43.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC43_IN_SEL 0x0000003FU +#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) +#define GPIO_FUNC43_IN_SEL_V 0x0000003FU +#define GPIO_FUNC43_IN_SEL_S 0 +/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) +#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC43_IN_INV_SEL_S 6 +/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) +#define GPIO_SIG43_IN_SEL_V 0x00000001U +#define GPIO_SIG43_IN_SEL_S 7 + +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * Configuration register for input signal 46 + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 46.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 7 + +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * Configuration register for input signal 47 + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 47.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 7 + +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * Configuration register for input signal 64 + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 64.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 7 + +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * Configuration register for input signal 65 + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 65.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 7 + +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * Configuration register for input signal 66 + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 66.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 7 + +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * Configuration register for input signal 67 + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 67.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 7 + +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * Configuration register for input signal 68 + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 68.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 7 + +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * Configuration register for input signal 69 + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 69.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 7 + +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * Configuration register for input signal 72 + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 72.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 7 + +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * Configuration register for input signal 73 + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 73.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 7 + +/** GPIO_FUNC74_IN_SEL_CFG_REG register + * Configuration register for input signal 74 + */ +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) +/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 74.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC74_IN_SEL 0x0000003FU +#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) +#define GPIO_FUNC74_IN_SEL_V 0x0000003FU +#define GPIO_FUNC74_IN_SEL_S 0 +/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) +#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC74_IN_INV_SEL_S 6 +/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) +#define GPIO_SIG74_IN_SEL_V 0x00000001U +#define GPIO_SIG74_IN_SEL_S 7 + +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * Configuration register for input signal 82 + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 82.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 7 + +/** GPIO_FUNC83_IN_SEL_CFG_REG register + * Configuration register for input signal 83 + */ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 83.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC83_IN_SEL 0x0000003FU +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000003FU +#define GPIO_FUNC83_IN_SEL_S 0 +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001U +#define GPIO_SIG83_IN_SEL_S 7 + +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * Configuration register for input signal 97 + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 97.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 7 + +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * Configuration register for input signal 98 + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 98.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 7 + +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * Configuration register for input signal 99 + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 99.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 7 + +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * Configuration register for input signal 100 + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 100.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 7 + +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * Configuration register for input signal 118 + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 118.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 7 + +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * Configuration register for input signal 119 + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 119.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 7 + +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * Configuration register for input signal 120 + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 120.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 7 + +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * Configuration register for input signal 121 + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 121.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ +#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 7 + +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * Configuration register for GPIO0 output + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac4) +/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO0.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC0_OUT_SEL 0x000001FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 9 +/** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC0_OE_SEL (BIT(10)) +#define GPIO_FUNC0_OE_SEL_M (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S) +#define GPIO_FUNC0_OE_SEL_V 0x00000001U +#define GPIO_FUNC0_OE_SEL_S 10 +/** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC0_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OE_INV_SEL_M (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S) +#define GPIO_FUNC0_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OE_INV_SEL_S 11 + +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * Configuration register for GPIO1 output + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac8) +/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO1.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC1_OUT_SEL 0x000001FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 9 +/** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC1_OE_SEL (BIT(10)) +#define GPIO_FUNC1_OE_SEL_M (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S) +#define GPIO_FUNC1_OE_SEL_V 0x00000001U +#define GPIO_FUNC1_OE_SEL_S 10 +/** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC1_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OE_INV_SEL_M (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S) +#define GPIO_FUNC1_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OE_INV_SEL_S 11 + +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * Configuration register for GPIO2 output + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xacc) +/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO2.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC2_OUT_SEL 0x000001FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 9 +/** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC2_OE_SEL (BIT(10)) +#define GPIO_FUNC2_OE_SEL_M (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S) +#define GPIO_FUNC2_OE_SEL_V 0x00000001U +#define GPIO_FUNC2_OE_SEL_S 10 +/** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC2_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OE_INV_SEL_M (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S) +#define GPIO_FUNC2_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OE_INV_SEL_S 11 + +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * Configuration register for GPIO3 output + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad0) +/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO3.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC3_OUT_SEL 0x000001FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 9 +/** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC3_OE_SEL (BIT(10)) +#define GPIO_FUNC3_OE_SEL_M (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S) +#define GPIO_FUNC3_OE_SEL_V 0x00000001U +#define GPIO_FUNC3_OE_SEL_S 10 +/** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC3_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OE_INV_SEL_M (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S) +#define GPIO_FUNC3_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OE_INV_SEL_S 11 + +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * Configuration register for GPIO4 output + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) +/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO4.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC4_OUT_SEL 0x000001FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 9 +/** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC4_OE_SEL (BIT(10)) +#define GPIO_FUNC4_OE_SEL_M (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S) +#define GPIO_FUNC4_OE_SEL_V 0x00000001U +#define GPIO_FUNC4_OE_SEL_S 10 +/** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC4_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OE_INV_SEL_M (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S) +#define GPIO_FUNC4_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OE_INV_SEL_S 11 + +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * Configuration register for GPIO5 output + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) +/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO5.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC5_OUT_SEL 0x000001FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 9 +/** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC5_OE_SEL (BIT(10)) +#define GPIO_FUNC5_OE_SEL_M (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S) +#define GPIO_FUNC5_OE_SEL_V 0x00000001U +#define GPIO_FUNC5_OE_SEL_S 10 +/** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC5_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OE_INV_SEL_M (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S) +#define GPIO_FUNC5_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OE_INV_SEL_S 11 + +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * Configuration register for GPIO6 output + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) +/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO6.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC6_OUT_SEL 0x000001FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 9 +/** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC6_OE_SEL (BIT(10)) +#define GPIO_FUNC6_OE_SEL_M (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S) +#define GPIO_FUNC6_OE_SEL_V 0x00000001U +#define GPIO_FUNC6_OE_SEL_S 10 +/** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC6_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OE_INV_SEL_M (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S) +#define GPIO_FUNC6_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OE_INV_SEL_S 11 + +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * Configuration register for GPIO7 output + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) +/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO7.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC7_OUT_SEL 0x000001FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 9 +/** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC7_OE_SEL (BIT(10)) +#define GPIO_FUNC7_OE_SEL_M (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S) +#define GPIO_FUNC7_OE_SEL_V 0x00000001U +#define GPIO_FUNC7_OE_SEL_S 10 +/** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC7_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OE_INV_SEL_M (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S) +#define GPIO_FUNC7_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OE_INV_SEL_S 11 + +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * Configuration register for GPIO8 output + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) +/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO8.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC8_OUT_SEL 0x000001FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 9 +/** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC8_OE_SEL (BIT(10)) +#define GPIO_FUNC8_OE_SEL_M (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S) +#define GPIO_FUNC8_OE_SEL_V 0x00000001U +#define GPIO_FUNC8_OE_SEL_S 10 +/** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC8_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OE_INV_SEL_M (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S) +#define GPIO_FUNC8_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OE_INV_SEL_S 11 + +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * Configuration register for GPIO9 output + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) +/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO9.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC9_OUT_SEL 0x000001FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 9 +/** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC9_OE_SEL (BIT(10)) +#define GPIO_FUNC9_OE_SEL_M (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S) +#define GPIO_FUNC9_OE_SEL_V 0x00000001U +#define GPIO_FUNC9_OE_SEL_S 10 +/** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC9_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OE_INV_SEL_M (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S) +#define GPIO_FUNC9_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OE_INV_SEL_S 11 + +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * Configuration register for GPIO10 output + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) +/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO10.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC10_OUT_SEL 0x000001FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 9 +/** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC10_OE_SEL (BIT(10)) +#define GPIO_FUNC10_OE_SEL_M (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S) +#define GPIO_FUNC10_OE_SEL_V 0x00000001U +#define GPIO_FUNC10_OE_SEL_S 10 +/** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC10_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OE_INV_SEL_M (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S) +#define GPIO_FUNC10_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OE_INV_SEL_S 11 + +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * Configuration register for GPIO11 output + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) +/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO11.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC11_OUT_SEL 0x000001FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 9 +/** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC11_OE_SEL (BIT(10)) +#define GPIO_FUNC11_OE_SEL_M (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S) +#define GPIO_FUNC11_OE_SEL_V 0x00000001U +#define GPIO_FUNC11_OE_SEL_S 10 +/** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC11_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OE_INV_SEL_M (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S) +#define GPIO_FUNC11_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OE_INV_SEL_S 11 + +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * Configuration register for GPIO12 output + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) +/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO12.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC12_OUT_SEL 0x000001FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 9 +/** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC12_OE_SEL (BIT(10)) +#define GPIO_FUNC12_OE_SEL_M (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S) +#define GPIO_FUNC12_OE_SEL_V 0x00000001U +#define GPIO_FUNC12_OE_SEL_S 10 +/** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC12_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OE_INV_SEL_M (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S) +#define GPIO_FUNC12_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OE_INV_SEL_S 11 + +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * Configuration register for GPIO13 output + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) +/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO13.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC13_OUT_SEL 0x000001FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 9 +/** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC13_OE_SEL (BIT(10)) +#define GPIO_FUNC13_OE_SEL_M (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S) +#define GPIO_FUNC13_OE_SEL_V 0x00000001U +#define GPIO_FUNC13_OE_SEL_S 10 +/** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC13_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OE_INV_SEL_M (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S) +#define GPIO_FUNC13_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OE_INV_SEL_S 11 + +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * Configuration register for GPIO14 output + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) +/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO14.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC14_OUT_SEL 0x000001FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 9 +/** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC14_OE_SEL (BIT(10)) +#define GPIO_FUNC14_OE_SEL_M (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S) +#define GPIO_FUNC14_OE_SEL_V 0x00000001U +#define GPIO_FUNC14_OE_SEL_S 10 +/** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC14_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OE_INV_SEL_M (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S) +#define GPIO_FUNC14_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OE_INV_SEL_S 11 + +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * Configuration register for GPIO15 output + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) +/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO15.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC15_OUT_SEL 0x000001FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 9 +/** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC15_OE_SEL (BIT(10)) +#define GPIO_FUNC15_OE_SEL_M (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S) +#define GPIO_FUNC15_OE_SEL_V 0x00000001U +#define GPIO_FUNC15_OE_SEL_S 10 +/** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC15_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OE_INV_SEL_M (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S) +#define GPIO_FUNC15_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OE_INV_SEL_S 11 + +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * Configuration register for GPIO16 output + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) +/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO16.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC16_OUT_SEL 0x000001FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 9 +/** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC16_OE_SEL (BIT(10)) +#define GPIO_FUNC16_OE_SEL_M (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S) +#define GPIO_FUNC16_OE_SEL_V 0x00000001U +#define GPIO_FUNC16_OE_SEL_S 10 +/** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC16_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OE_INV_SEL_M (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S) +#define GPIO_FUNC16_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OE_INV_SEL_S 11 + +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * Configuration register for GPIO17 output + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) +/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO17.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC17_OUT_SEL 0x000001FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 9 +/** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC17_OE_SEL (BIT(10)) +#define GPIO_FUNC17_OE_SEL_M (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S) +#define GPIO_FUNC17_OE_SEL_V 0x00000001U +#define GPIO_FUNC17_OE_SEL_S 10 +/** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC17_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OE_INV_SEL_M (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S) +#define GPIO_FUNC17_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OE_INV_SEL_S 11 + +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * Configuration register for GPIO18 output + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) +/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO18.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC18_OUT_SEL 0x000001FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 9 +/** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC18_OE_SEL (BIT(10)) +#define GPIO_FUNC18_OE_SEL_M (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S) +#define GPIO_FUNC18_OE_SEL_V 0x00000001U +#define GPIO_FUNC18_OE_SEL_S 10 +/** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC18_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OE_INV_SEL_M (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S) +#define GPIO_FUNC18_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OE_INV_SEL_S 11 + +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * Configuration register for GPIO19 output + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) +/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO19.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC19_OUT_SEL 0x000001FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 9 +/** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC19_OE_SEL (BIT(10)) +#define GPIO_FUNC19_OE_SEL_M (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S) +#define GPIO_FUNC19_OE_SEL_V 0x00000001U +#define GPIO_FUNC19_OE_SEL_S 10 +/** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC19_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OE_INV_SEL_M (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S) +#define GPIO_FUNC19_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OE_INV_SEL_S 11 + +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * Configuration register for GPIO20 output + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) +/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO20.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC20_OUT_SEL 0x000001FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 9 +/** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC20_OE_SEL (BIT(10)) +#define GPIO_FUNC20_OE_SEL_M (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S) +#define GPIO_FUNC20_OE_SEL_V 0x00000001U +#define GPIO_FUNC20_OE_SEL_S 10 +/** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC20_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OE_INV_SEL_M (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S) +#define GPIO_FUNC20_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OE_INV_SEL_S 11 + +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * Configuration register for GPIO21 output + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) +/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO21.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC21_OUT_SEL 0x000001FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 9 +/** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC21_OE_SEL (BIT(10)) +#define GPIO_FUNC21_OE_SEL_M (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S) +#define GPIO_FUNC21_OE_SEL_V 0x00000001U +#define GPIO_FUNC21_OE_SEL_S 10 +/** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC21_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OE_INV_SEL_M (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S) +#define GPIO_FUNC21_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OE_INV_SEL_S 11 + +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * Configuration register for GPIO22 output + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) +/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO22.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC22_OUT_SEL 0x000001FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 9 +/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC22_OE_SEL (BIT(10)) +#define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S) +#define GPIO_FUNC22_OE_SEL_V 0x00000001U +#define GPIO_FUNC22_OE_SEL_S 10 +/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC22_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S) +#define GPIO_FUNC22_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OE_INV_SEL_S 11 + +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * Configuration register for GPIO23 output + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) +/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO23.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC23_OUT_SEL 0x000001FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 9 +/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC23_OE_SEL (BIT(10)) +#define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S) +#define GPIO_FUNC23_OE_SEL_V 0x00000001U +#define GPIO_FUNC23_OE_SEL_S 10 +/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC23_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S) +#define GPIO_FUNC23_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OE_INV_SEL_S 11 + +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * Configuration register for GPIO24 output + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) +/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO24.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC24_OUT_SEL 0x000001FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 9 +/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC24_OE_SEL (BIT(10)) +#define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S) +#define GPIO_FUNC24_OE_SEL_V 0x00000001U +#define GPIO_FUNC24_OE_SEL_S 10 +/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC24_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S) +#define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OE_INV_SEL_S 11 + +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * Configuration register for GPIO$n output + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC25_OUT_SEL 0x000001FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 9 +/** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC25_OE_SEL (BIT(10)) +#define GPIO_FUNC25_OE_SEL_M (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S) +#define GPIO_FUNC25_OE_SEL_V 0x00000001U +#define GPIO_FUNC25_OE_SEL_S 10 +/** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC25_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OE_INV_SEL_M (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S) +#define GPIO_FUNC25_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OE_INV_SEL_S 11 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * Configuration register for GPIO$n output + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC26_OUT_SEL 0x000001FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 9 +/** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC26_OE_SEL (BIT(10)) +#define GPIO_FUNC26_OE_SEL_M (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S) +#define GPIO_FUNC26_OE_SEL_V 0x00000001U +#define GPIO_FUNC26_OE_SEL_S 10 +/** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC26_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OE_INV_SEL_M (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S) +#define GPIO_FUNC26_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OE_INV_SEL_S 11 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * Configuration register for GPIO$n output + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC27_OUT_SEL 0x000001FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 9 +/** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC27_OE_SEL (BIT(10)) +#define GPIO_FUNC27_OE_SEL_M (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S) +#define GPIO_FUNC27_OE_SEL_V 0x00000001U +#define GPIO_FUNC27_OE_SEL_S 10 +/** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC27_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OE_INV_SEL_M (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S) +#define GPIO_FUNC27_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OE_INV_SEL_S 11 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * Configuration register for GPIO$n output + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ +#define GPIO_FUNC28_OUT_SEL 0x000001FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 9 +/** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ +#define GPIO_FUNC28_OE_SEL (BIT(10)) +#define GPIO_FUNC28_OE_SEL_M (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S) +#define GPIO_FUNC28_OE_SEL_V 0x00000001U +#define GPIO_FUNC28_OE_SEL_S 10 +/** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define GPIO_FUNC28_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OE_INV_SEL_M (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S) +#define GPIO_FUNC28_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OE_INV_SEL_S 11 + +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable clock gate.\\ + * 0: Not enable\\ + * 1: Enable, the clock is free running. \\ + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_DATE_REG register + * GPIO version register + */ +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc) +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37753392; + * Version control register. \\ + */ +#define GPIO_DATE 0x0FFFFFFFU +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFFU +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_sig_map.h b/components/soc/esp32c61/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..a2bc325aed --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_sig_map.h @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define CPU_TESTBUS0_IDX 19 +#define CPU_TESTBUS1_IDX 20 +#define CPU_TESTBUS2_IDX 21 +#define CPU_TESTBUS3_IDX 22 +#define CPU_TESTBUS4_IDX 23 +#define CPU_TESTBUS5_IDX 24 +#define CPU_TESTBUS6_IDX 25 +#define CPU_TESTBUS7_IDX 26 +#define CPU_GPIO_IN0_IDX 27 +#define CPU_GPIO_OUT0_IDX 27 +#define CPU_GPIO_IN1_IDX 28 +#define CPU_GPIO_OUT1_IDX 28 +#define CPU_GPIO_IN2_IDX 29 +#define CPU_GPIO_OUT2_IDX 29 +#define CPU_GPIO_IN3_IDX 30 +#define CPU_GPIO_OUT3_IDX 30 +#define CPU_GPIO_IN4_IDX 31 +#define CPU_GPIO_OUT4_IDX 31 +#define CPU_GPIO_IN5_IDX 32 +#define CPU_GPIO_OUT5_IDX 32 +#define CPU_GPIO_IN6_IDX 33 +#define CPU_GPIO_OUT6_IDX 33 +#define CPU_GPIO_IN7_IDX 34 +#define CPU_GPIO_OUT7_IDX 34 +#define USB_JTAG_TDO_IDX 35 +#define USB_JTAG_TRST_IDX 35 +#define USB_JTAG_SRST_IDX 36 +#define USB_JTAG_TCK_IDX 37 +#define USB_JTAG_TMS_IDX 38 +#define USB_JTAG_TDI_IDX 39 +#define CPU_USB_JTAG_TDO_IDX 40 +#define USB_EXTPHY_VP_IDX 41 +#define USB_EXTPHY_OEN_IDX 41 +#define USB_EXTPHY_VM_IDX 42 +#define USB_EXTPHY_SPEED_IDX 42 +#define USB_EXTPHY_RCV_IDX 43 +#define USB_EXTPHY_VPO_IDX 43 +#define USB_EXTPHY_VMO_IDX 44 +#define USB_EXTPHY_SUSPND_IDX 45 +#define I2CEXT0_SCL_IN_IDX 46 +#define I2CEXT0_SCL_OUT_IDX 46 +#define I2CEXT0_SDA_IN_IDX 47 +#define I2CEXT0_SDA_OUT_IDX 47 +#define ANT_SEL0_IDX 48 +#define ANT_SEL1_IDX 49 +#define ANT_SEL2_IDX 50 +#define ANT_SEL3_IDX 51 +#define ANT_SEL4_IDX 52 +#define ANT_SEL5_IDX 53 +#define ANT_SEL6_IDX 54 +#define ANT_SEL7_IDX 55 +#define ANT_SEL8_IDX 56 +#define ANT_SEL9_IDX 57 +#define ANT_SEL10_IDX 58 +#define ANT_SEL11_IDX 59 +#define ANT_SEL12_IDX 60 +#define ANT_SEL13_IDX 61 +#define ANT_SEL14_IDX 62 +#define ANT_SEL15_IDX 63 +#define FSPICLK_IN_IDX 64 +#define FSPICLK_OUT_IDX 64 +#define FSPIQ_IN_IDX 65 +#define FSPIQ_OUT_IDX 65 +#define FSPID_IN_IDX 66 +#define FSPID_OUT_IDX 66 +#define FSPIHD_IN_IDX 67 +#define FSPIHD_OUT_IDX 67 +#define FSPIWP_IN_IDX 68 +#define FSPIWP_OUT_IDX 68 +#define FSPICS0_IN_IDX 69 +#define FSPICS0_OUT_IDX 69 +#define U2RXD_IN_IDX 72 +#define U2TXD_OUT_IDX 72 +#define U2CTS_IN_IDX 73 +#define U2RTS_OUT_IDX 73 +#define U2DSR_IN_IDX 74 +#define U2DTR_OUT_IDX 74 +#define EXTERN_PRIORITY_I_IDX 82 +#define EXTERN_PRIORITY_O_IDX 82 +#define EXTERN_ACTIVE_I_IDX 83 +#define EXTERN_ACTIVE_O_IDX 83 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define FSPICS1_OUT_IDX 102 +#define FSPICS2_OUT_IDX 103 +#define FSPICS3_OUT_IDX 104 +#define FSPICS4_OUT_IDX 105 +#define FSPICS5_OUT_IDX 106 +#define GPIO_EVENT_MATRIX_IN0_IDX 118 +#define GPIO_TASK_MATRIX_OUT0_IDX 118 +#define GPIO_EVENT_MATRIX_IN1_IDX 119 +#define GPIO_TASK_MATRIX_OUT1_IDX 119 +#define GPIO_EVENT_MATRIX_IN2_IDX 120 +#define GPIO_TASK_MATRIX_OUT2_IDX 120 +#define GPIO_EVENT_MATRIX_IN3_IDX 121 +#define GPIO_TASK_MATRIX_OUT3_IDX 121 +#define CLK_OUT_OUT1_IDX 126 +#define CLK_OUT_OUT2_IDX 127 +#define CLK_OUT_OUT3_IDX 128 +#define MODEM_DIAG0_IDX 129 +#define MODEM_DIAG1_IDX 130 +#define MODEM_DIAG2_IDX 131 +#define MODEM_DIAG3_IDX 132 +#define MODEM_DIAG4_IDX 133 +#define MODEM_DIAG5_IDX 134 +#define MODEM_DIAG6_IDX 135 +#define MODEM_DIAG7_IDX 136 +#define MODEM_DIAG8_IDX 137 +#define MODEM_DIAG9_IDX 138 +#define MODEM_DIAG10_IDX 139 +#define MODEM_DIAG11_IDX 140 +#define MODEM_DIAG12_IDX 141 +#define MODEM_DIAG13_IDX 142 +#define MODEM_DIAG14_IDX 143 +#define MODEM_DIAG15_IDX 144 +#define MODEM_DIAG16_IDX 145 +#define MODEM_DIAG17_IDX 146 +#define MODEM_DIAG18_IDX 147 +#define MODEM_DIAG19_IDX 148 +#define MODEM_DIAG20_IDX 149 +#define MODEM_DIAG21_IDX 150 +#define MODEM_DIAG22_IDX 151 +#define MODEM_DIAG23_IDX 152 +#define MODEM_DIAG24_IDX 153 +#define MODEM_DIAG25_IDX 154 +#define MODEM_DIAG26_IDX 155 +#define MODEM_DIAG27_IDX 156 +#define MODEM_DIAG28_IDX 157 +#define MODEM_DIAG29_IDX 158 +#define MODEM_DIAG30_IDX 159 +#define MODEM_DIAG31_IDX 160 +// version date 2310090 diff --git a/components/soc/esp32c61/include/soc/gpio_struct.h b/components/soc/esp32c61/include/soc/gpio_struct.h new file mode 100644 index 0000000000..18bb9e7566 --- /dev/null +++ b/components/soc/esp32c61/include/soc/gpio_struct.h @@ -0,0 +1,1259 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of strap register + * Strapping pin register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * Represents the values of GPIO strapping pins. + * + * - bit0 ~ bit1: invalid + * - bit2: GPIO8 + * - bit3: GPIO9 + * - bit4: GPIO7 + * - bit5 ~ bit15: invalid + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of out register + * GPIO output register + */ +typedef union { + struct { + /** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0; + * Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\ + * 0: Low level\\ + * 1: High level\\ + * The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24 + * respectively. Bit25 ~ bit31 are invalid.\\ + */ + uint32_t out_data_orig:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ + * GPIO24.\\ + * 0: Not set\\ + * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set GPIO_OUT_REG. \\ + */ + uint32_t out_w1ts:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ + * GPIO24 output.\\ + * 0: Not clear\\ + * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear GPIO_OUT_REG. \\ + */ + uint32_t out_w1tc:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of enable register + * GPIO output enable register + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [28:0]; default: 0; + * Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\ + * 0: Not enable\\ + * 1: Enable\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + */ + uint32_t enable_data:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to set the output enable register GPIO_ENABLE_REG of + * GPIO0 ~ GPIO24.\\ + * 0: Not set\\ + * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ + */ + uint32_t enable_w1ts:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of + * GPIO0 ~ GPIO24. \\ + * 0: Not clear\\ + * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ + */ + uint32_t enable_w1tc:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of in register + * GPIO input register + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [28:0]; default: 0; + * Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input + * value:\\ + * 0: Low level\\ + * 1: High level\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + */ + uint32_t in_data_next:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_in_reg_t; + + +/** Group: Interrupt Status Registers */ +/** Type of status register + * GPIO interrupt status register + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0; + * The interrupt status of GPIO0 ~ GPIO24, can be configured by the software. + * + * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. + * - Each bit represents the status of its corresponding GPIO: + * + * - 0: Represents the GPIO does not generate the interrupt configured by + * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, + * or this bit is configured to 1 by the software. + * + */ + uint32_t status_interrupt:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to set the interrupt status register + * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. + * + * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set GPIO_STATUS_INTERRUPT. + */ + uint32_t status_w1ts:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [28:0]; default: 0; + * Configures whether or not to clear the interrupt status register + * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. + * + * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear GPIO_STATUS_INTERRUPT. + */ + uint32_t status_w1tc:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of procpu_int register + * CPU interrupt status register + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [28:0]; default: 0; + * Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\ + * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the + * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the CPU interrupt is enabled.\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). \\ + */ + uint32_t procpu_int:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_procpu_int_reg_t; + +/** Type of status_next register + * GPIO interrupt source register + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [28:0]; default: 0; + * Represents the interrupt source signal of GPIO0 ~ GPIO24.\\ + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each + * bit represents:\\ + * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt.\\ + */ + uint32_t status_interrupt_next:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} gpio_status_next_reg_t; + + +/** Group: Pin Configuration Registers */ +/** Type of pinn register + * GPIOn configuration register + */ +typedef union { + struct { + /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pinn_sync2_bypass:2; + /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ + uint32_t pinn_pad_driver:1; + /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pinn_sync1_bypass:2; + uint32_t reserved_5:2; + /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ + uint32_t pinn_int_type:3; + /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ + uint32_t pinn_wakeup_enable:1; + uint32_t reserved_11:2; + /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ + uint32_t pinn_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pinn_reg_t; + +/** Type of pin25 register + * GPIO25 configuration register + */ +typedef union { + struct { + /** pin25_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin25_sync2_bypass:2; + /** pin25_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ + uint32_t pin25_pad_driver:1; + /** pin25_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin25_sync1_bypass:2; + uint32_t reserved_5:2; + /** pin25_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ + uint32_t pin25_int_type:3; + /** pin25_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ + uint32_t pin25_wakeup_enable:1; + uint32_t reserved_11:2; + /** pin25_int_ena : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ + uint32_t pin25_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin25_reg_t; + +/** Type of pin26 register + * GPIO26 configuration register + */ +typedef union { + struct { + /** pin26_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin26_sync2_bypass:2; + /** pin26_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ + uint32_t pin26_pad_driver:1; + /** pin26_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin26_sync1_bypass:2; + uint32_t reserved_5:2; + /** pin26_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ + uint32_t pin26_int_type:3; + /** pin26_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ + uint32_t pin26_wakeup_enable:1; + uint32_t reserved_11:2; + /** pin26_int_ena : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ + uint32_t pin26_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin26_reg_t; + +/** Type of pin27 register + * GPIO27 configuration register + */ +typedef union { + struct { + /** pin27_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin27_sync2_bypass:2; + /** pin27_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ + uint32_t pin27_pad_driver:1; + /** pin27_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin27_sync1_bypass:2; + uint32_t reserved_5:2; + /** pin27_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ + uint32_t pin27_int_type:3; + /** pin27_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ + uint32_t pin27_wakeup_enable:1; + uint32_t reserved_11:2; + /** pin27_int_ena : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ + uint32_t pin27_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin27_reg_t; + +/** Type of pin28 register + * GPIO28 configuration register + */ +typedef union { + struct { + /** pin28_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin28_sync2_bypass:2; + /** pin28_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ + uint32_t pin28_pad_driver:1; + /** pin28_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize GPIO input data on either edge of IO MUX + * operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pin28_sync1_bypass:2; + uint32_t reserved_5:2; + /** pin28_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures GPIO interrupt type.\\ + * 0: GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ + uint32_t pin28_int_type:3; + /** pin28_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ + uint32_t pin28_wakeup_enable:1; + uint32_t reserved_11:2; + /** pin28_int_ena : R/W; bitpos: [17:13]; default: 0; + * Configures whether or not to enable CPU interrupt. + * + * - bit13: Configures whether or not to enable CPU interrupt:\\ + * 0: Disable\\ + * 1: Enable\\ + * - bit14 ~ bit17: invalid + */ + uint32_t pin28_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin28_reg_t; + + +/** Group: Input Configuration Registers */ +/** Type of func0_in_sel_cfg register + * Configuration register for input signal 0 + */ +typedef union { + struct { + /** func0_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t func0_in_sel:6; + /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func0_in_inv_sel:1; + /** sig0_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sig0_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func0_in_sel_cfg_reg_t; + +/** Type of funcb_in_sel_cfg register + * Configuration register for input signal b + */ +typedef union { + struct { + /** funcb_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal b.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funcb_in_sel:6; + /** funcb_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcb_in_inv_sel:1; + /** sigb_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigb_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funcb_in_sel_cfg_reg_t; + +/** Type of funcc_in_sel_cfg register + * Configuration register for input signal c + */ +typedef union { + struct { + /** funcc_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal c.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funcc_in_sel:6; + /** funcc_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcc_in_inv_sel:1; + /** sigc_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigc_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funcc_in_sel_cfg_reg_t; + +/** Type of funcd_in_sel_cfg register + * Configuration register for input signal d + */ +typedef union { + struct { + /** funcd_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal d.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funcd_in_sel:6; + /** funcd_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcd_in_inv_sel:1; + /** sigd_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigd_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funcd_in_sel_cfg_reg_t; + +/** Type of funce_in_sel_cfg register + * Configuration register for input signal e + */ +typedef union { + struct { + /** funce_in_sel : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal e.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funce_in_sel:6; + /** funce_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funce_in_inv_sel:1; + /** sige_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sige_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funce_in_sel_cfg_reg_t; + +/** Type of funcf_in_sel_cfg register + * Configuration register for input signal f + */ +typedef union { + struct { + /** funcf_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal f.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funcf_in_sel:6; + /** funcf_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcf_in_inv_sel:1; + /** sigf_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigf_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funcf_in_sel_cfg_reg_t; + +/** Type of funcg_in_sel_cfg register + * Configuration register for input signal g + */ +typedef union { + struct { + /** funcg_in_sel : R/W; bitpos: [5:0]; default: 32; + * Configures to select a pin from the 25 GPIO pins to connect the input signal g.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funcg_in_sel:6; + /** funcg_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcg_in_inv_sel:1; + /** sigg_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigg_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funcg_in_sel_cfg_reg_t; + +/** Type of funch_in_sel_cfg register + * Configuration register for input signal h + */ +typedef union { + struct { + /** funch_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal h.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funch_in_sel:6; + /** funch_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funch_in_inv_sel:1; + /** sigh_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigh_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funch_in_sel_cfg_reg_t; + +/** Type of funci_in_sel_cfg register + * Configuration register for input signal i + */ +typedef union { + struct { + /** funci_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal i.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funci_in_sel:6; + /** funci_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funci_in_inv_sel:1; + /** sigi_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigi_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funci_in_sel_cfg_reg_t; + +/** Type of funcj_in_sel_cfg register + * Configuration register for input signal j + */ +typedef union { + struct { + /** funcj_in_sel : R/W; bitpos: [5:0]; default: 48; + * Configures to select a pin from the 25 GPIO pins to connect the input signal j.\\ + * 0: Select GPIO0\\ + * 1: Select GPIO1\\ + * ......\\ + * 23: Select GPIO23\\ + * 24: Select GPIO24\\ + * Or\\ + * 0x20: A constantly high input\\ + * 0x30: A constantly low input\\ + */ + uint32_t funcj_in_sel:6; + /** funcj_in_inv_sel : R/W; bitpos: [6]; default: 0; + * Configures whether or not to invert the input value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcj_in_inv_sel:1; + /** sigj_in_sel : R/W; bitpos: [7]; default: 0; + * Configures whether or not to route signals via GPIO matrix.\\ + * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in + * IO MUX.\\ + * 1: Route signals via GPIO matrix.\\ + */ + uint32_t sigj_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_funcj_in_sel_cfg_reg_t; + + +/** Group: Output Configuration Registers */ +/** Type of funcn_out_sel_cfg register + * Configuration register for GPIOn output + */ +typedef union { + struct { + /** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIOn.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and + * output enable. + * + * For the detailed signal list, see Table link. + * " + */ + uint32_t funcn_out_sel:9; + /** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcn_out_inv_sel:1; + /** funcn_oe_sel : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\ + */ + uint32_t funcn_oe_sel:1; + /** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcn_oe_inv_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} gpio_funcn_out_sel_cfg_reg_t; + +/** Type of func25_out_sel_cfg register + * Configuration register for GPIO$n output + */ +typedef union { + struct { + /** func25_out_sel : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ + uint32_t func25_out_sel:9; + /** func25_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func25_out_inv_sel:1; + /** func25_oe_sel : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ + uint32_t func25_oe_sel:1; + /** func25_oe_inv_sel : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func25_oe_inv_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} gpio_func25_out_sel_cfg_reg_t; + +/** Type of func26_out_sel_cfg register + * Configuration register for GPIO$n output + */ +typedef union { + struct { + /** func26_out_sel : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ + uint32_t func26_out_sel:9; + /** func26_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func26_out_inv_sel:1; + /** func26_oe_sel : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ + uint32_t func26_oe_sel:1; + /** func26_oe_inv_sel : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func26_oe_inv_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} gpio_func26_out_sel_cfg_reg_t; + +/** Type of func27_out_sel_cfg register + * Configuration register for GPIO$n output + */ +typedef union { + struct { + /** func27_out_sel : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ + uint32_t func27_out_sel:9; + /** func27_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func27_out_inv_sel:1; + /** func27_oe_sel : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ + uint32_t func27_oe_sel:1; + /** func27_oe_inv_sel : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func27_oe_inv_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} gpio_func27_out_sel_cfg_reg_t; + +/** Type of func28_out_sel_cfg register + * Configuration register for GPIO$n output + */ +typedef union { + struct { + /** func28_out_sel : R/W/SC; bitpos: [8:0]; default: 256; + * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be + * output from GPIO$n.\\ + * 0: Select signal 0\\ + * 1: Select signal 1\\ + * ......\\ + * 254: Select signal 254\\ + * 255: Select signal 255\\ + * Or\\ + * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value + * and output enable. + * + * For the detailed signal list, see Table link. + * " + */ + uint32_t func28_out_sel:9; + /** func28_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func28_out_inv_sel:1; + /** func28_oe_sel : R/W; bitpos: [10]; default: 0; + * Configures to select the source of output enable signal.\\ + * 0: Use output enable signal from peripheral.\\ + * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ + */ + uint32_t func28_oe_sel:1; + /** func28_oe_inv_sel : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t func28_oe_inv_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} gpio_func28_out_sel_cfg_reg_t; + + +/** Group: Clock Gate Register */ +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable clock gate.\\ + * 0: Not enable\\ + * 1: Enable, the clock is free running. \\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * GPIO version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37753392; + * Version control register. \\ + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_date_reg_t; + + +typedef struct { + volatile gpio_strap_reg_t strap; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + uint32_t reserved_010[9]; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + uint32_t reserved_040[9]; + volatile gpio_in_reg_t in; + uint32_t reserved_068[3]; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + uint32_t reserved_080[9]; + volatile gpio_procpu_int_reg_t procpu_int; + uint32_t reserved_0a8[3]; + volatile gpio_status_next_reg_t status_next; + uint32_t reserved_0b8[3]; + volatile gpio_pinn_reg_t pinn[25]; + volatile gpio_pin25_reg_t pin25; + volatile gpio_pin26_reg_t pin26; + volatile gpio_pin27_reg_t pin27; + volatile gpio_pin28_reg_t pin28; + uint32_t reserved_138[99]; + volatile gpio_func0_in_sel_cfg_reg_t func0_in_sel_cfg; + uint32_t reserved_2c8[5]; + volatile gpio_funcb_in_sel_cfg_reg_t funcb_in_sel_cfg[12]; + uint32_t reserved_30c[9]; + volatile gpio_funcc_in_sel_cfg_reg_t funcc_in_sel_cfg[9]; + uint32_t reserved_354[5]; + volatile gpio_funcd_in_sel_cfg_reg_t funcd_in_sel_cfg[3]; + uint32_t reserved_374[2]; + volatile gpio_funce_in_sel_cfg_reg_t funce_in_sel_cfg[2]; + uint32_t reserved_384[16]; + volatile gpio_funcf_in_sel_cfg_reg_t funcf_in_sel_cfg[6]; + uint32_t reserved_3dc[2]; + volatile gpio_funcg_in_sel_cfg_reg_t funcg_in_sel_cfg[3]; + uint32_t reserved_3f0[7]; + volatile gpio_funch_in_sel_cfg_reg_t funch_in_sel_cfg[2]; + uint32_t reserved_414[13]; + volatile gpio_funci_in_sel_cfg_reg_t funci_in_sel_cfg[4]; + uint32_t reserved_458[17]; + volatile gpio_funcj_in_sel_cfg_reg_t funcj_in_sel_cfg[4]; + uint32_t reserved_4ac[390]; + volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25]; + volatile gpio_func25_out_sel_cfg_reg_t func25_out_sel_cfg; + volatile gpio_func26_out_sel_cfg_reg_t func26_out_sel_cfg; + volatile gpio_func27_out_sel_cfg_reg_t func27_out_sel_cfg; + volatile gpio_func28_out_sel_cfg_reg_t func28_out_sel_cfg; + uint32_t reserved_b38[176]; + volatile gpio_clock_gate_reg_t clock_gate; + volatile gpio_date_reg_t date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/hp_system_reg.h b/components/soc/esp32c61/include/soc/hp_system_reg.h new file mode 100644 index 0000000000..168e95015c --- /dev/null +++ b/components/soc/esp32c61/include/soc/hp_system_reg.h @@ -0,0 +1,441 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * External device encryption/decryption configuration register + */ +#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0) +/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable MSPI XTS auto decryption in download boot + * mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable MSPI XTS manual encryption in download boot + * mode. \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/** HP_SYSTEM_SRAM_USAGE_CONF_REG register + * HP memory usage configuration register + */ +#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4) +/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0; + * reserved + */ +#define HP_SYSTEM_CACHE_USAGE (BIT(0)) +#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S) +#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U +#define HP_SYSTEM_CACHE_USAGE_S 0 +/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [12:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ +#define HP_SYSTEM_SRAM_USAGE 0x0000001FU +#define HP_SYSTEM_SRAM_USAGE_M (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S) +#define HP_SYSTEM_SRAM_USAGE_V 0x0000001FU +#define HP_SYSTEM_SRAM_USAGE_S 8 +/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ +#define HP_SYSTEM_MAC_DUMP_ALLOC (BIT(16)) +#define HP_SYSTEM_MAC_DUMP_ALLOC_M (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S) +#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x00000001U +#define HP_SYSTEM_MAC_DUMP_ALLOC_S 16 + +/** HP_SYSTEM_SEC_DPA_CONF_REG register + * HP anti-DPA security configuration register + */ +#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8) +/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to enable anti-DPA attack. Valid only when + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ + * 0: Disable\\ + * 1-3: Enable. The larger the number, the higher the security level, which represents + * the ability to resist DPA attacks, with increased computational overhead of the + * hardware crypto-accelerators at the same time. \\ + */ +#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U +#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) +#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U +#define HP_SYSTEM_SEC_DPA_LEVEL_S 0 +/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from + * eFuse) to control DPA level. \\ + * 0: Select EFUSE_SEC_DPA_LEVEL\\ + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + */ +#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2)) +#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S) +#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U +#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register + * CPU_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Configures the timeout threshold for bus access for accessing CPU peripheral + * register in the number of clock cycles of the clock domain. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Write 1 to clear timeout interrupt. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Configures whether or not to enable timeout protection for accessing CPU peripheral + * registers.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register + * CPU_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the address information of abnormal access. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register + * CPU_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This + * register will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register + * HP_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18) +/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Configures the timeout threshold for bus access for accessing HP peripheral + * register, corresponding to the number of clock cycles of the clock domain. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear timeout interrupt.\\ + * 0: No effect\\ + * 1: Clear timeout interrupt\\ + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Configures whether or not to enable timeout protection for accessing HP peripheral + * registers.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register + * HP_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c) +/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the address information of abnormal access. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register + * HP_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20) +/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This + * register will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register + * MODEM_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24) +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing modem registers + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register + * MODEM_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28) +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register + * MODEM_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c) +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_ROM_TABLE_LOCK_REG register + * ROM-Table lock register + */ +#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x30) +/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ + * 0: Unlock \\ + * 1: Lock \\ + */ +#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0)) +#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S) +#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U +#define HP_SYSTEM_ROM_TABLE_LOCK_S 0 + +/** HP_SYSTEM_ROM_TABLE_REG register + * ROM-Table register + */ +#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x34) +/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; + * Software ROM-Table register, whose content can be modified only when + * HP_SYSTEM_ROM_TABLE_LOCK is 0. + */ +#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU +#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S) +#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU +#define HP_SYSTEM_ROM_TABLE_S 0 + +/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register + * Core Debug RunStall configurion register + */ +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x38) +/** HP_SYSTEM_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0; + * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: + * not stalled. + */ +#define HP_SYSTEM_CORE_RUNSTALLED (BIT(1)) +#define HP_SYSTEM_CORE_RUNSTALLED_M (HP_SYSTEM_CORE_RUNSTALLED_V << HP_SYSTEM_CORE_RUNSTALLED_S) +#define HP_SYSTEM_CORE_RUNSTALLED_V 0x00000001U +#define HP_SYSTEM_CORE_RUNSTALLED_S 1 + +/** HP_SYSTEM_SPROM_CTRL_REG register + * reserved + */ +#define HP_SYSTEM_SPROM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x3c) +/** HP_SYSTEM_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; + * reserved + */ +#define HP_SYSTEM_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_M (HP_SYSTEM_SPROM_MEM_AUX_CTRL_V << HP_SYSTEM_SPROM_MEM_AUX_CTRL_S) +#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_S 0 + +/** HP_SYSTEM_SPRAM_CTRL_REG register + * reserved + */ +#define HP_SYSTEM_SPRAM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x40) +/** HP_SYSTEM_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ +#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_M (HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V << HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S) +#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S 0 + +/** HP_SYSTEM_SPRF_CTRL_REG register + * reserved + */ +#define HP_SYSTEM_SPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x44) +/** HP_SYSTEM_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ +#define HP_SYSTEM_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SPRF_MEM_AUX_CTRL_S) +#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_S 0 + +/** HP_SYSTEM_SDPRF_CTRL_REG register + * reserved + */ +#define HP_SYSTEM_SDPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x48) +/** HP_SYSTEM_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S) +#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S 0 + +/** HP_SYSTEM_RND_ECO_REG register + * redcy eco register. + */ +#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x4c) +/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_ENA (BIT(0)) +#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S) +#define HP_SYSTEM_REDCY_ENA_V 0x00000001U +#define HP_SYSTEM_REDCY_ENA_S 0 +/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_RESULT (BIT(1)) +#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S) +#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U +#define HP_SYSTEM_REDCY_RESULT_S 1 + +/** HP_SYSTEM_RND_ECO_LOW_REG register + * redcy eco low register. + */ +#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x50) +/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S) +#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_LOW_S 0 + +/** HP_SYSTEM_RND_ECO_HIGH_REG register + * redcy eco high register. + */ +#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x54) +/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S) +#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_HIGH_S 0 + +/** HP_SYSTEM_DEBUG_REG register + * HP-SYSTEM debug register + */ +#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x58) +/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1; + * Reserved + */ +#define HP_SYSTEM_FPGA_DEBUG (BIT(0)) +#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S) +#define HP_SYSTEM_FPGA_DEBUG_V 0x00000001U +#define HP_SYSTEM_FPGA_DEBUG_S 0 + +/** HP_SYSTEM_CLOCK_GATE_REG register + * HP-SYSTEM clock gating configure register + */ +#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x5c) +/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define HP_SYSTEM_CLK_EN (BIT(0)) +#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S) +#define HP_SYSTEM_CLK_EN_V 0x00000001U +#define HP_SYSTEM_CLK_EN_S 0 + +/** HP_SYSTEM_DATE_REG register + * Date control and version control register + */ +#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) +/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 36769824; + * Version control register. + */ +#define HP_SYSTEM_DATE 0x0FFFFFFFU +#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S) +#define HP_SYSTEM_DATE_V 0x0FFFFFFFU +#define HP_SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/hp_system_struct.h b/components/soc/esp32c61/include/soc/hp_system_struct.h new file mode 100644 index 0000000000..6c786758a9 --- /dev/null +++ b/components/soc/esp32c61/include/soc/hp_system_struct.h @@ -0,0 +1,489 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of external_device_encrypt_decrypt_control register + * External device encryption/decryption configuration register + */ +typedef union { + struct { + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable MSPI XTS auto decryption in download boot + * mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable MSPI XTS manual encryption in download boot + * mode. \\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t enable_download_manual_encrypt:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_system_external_device_encrypt_decrypt_control_reg_t; + +/** Type of sram_usage_conf register + * HP memory usage configuration register + */ +typedef union { + struct { + /** cache_usage : HRO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t cache_usage:1; + uint32_t reserved_1:7; + /** sram_usage : R/W; bitpos: [12:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ + uint32_t sram_usage:5; + uint32_t reserved_13:3; + /** mac_dump_alloc : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ + uint32_t mac_dump_alloc:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hp_system_sram_usage_conf_reg_t; + +/** Type of sec_dpa_conf register + * HP anti-DPA security configuration register + */ +typedef union { + struct { + /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to enable anti-DPA attack. Valid only when + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ + * 0: Disable\\ + * 1-3: Enable. The larger the number, the higher the security level, which represents + * the ability to resist DPA attacks, with increased computational overhead of the + * hardware crypto-accelerators at the same time. \\ + */ + uint32_t sec_dpa_level:2; + /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from + * eFuse) to control DPA level. \\ + * 0: Select EFUSE_SEC_DPA_LEVEL\\ + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + */ + uint32_t sec_dpa_cfg_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} hp_system_sec_dpa_conf_reg_t; + +/** Type of rom_table_lock register + * ROM-Table lock register + */ +typedef union { + struct { + /** rom_table_lock : R/W; bitpos: [0]; default: 0; + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ + * 0: Unlock \\ + * 1: Lock \\ + */ + uint32_t rom_table_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_rom_table_lock_reg_t; + +/** Type of rom_table register + * ROM-Table register + */ +typedef union { + struct { + /** rom_table : R/W; bitpos: [31:0]; default: 0; + * Software ROM-Table register, whose content can be modified only when + * HP_SYSTEM_ROM_TABLE_LOCK is 0. + */ + uint32_t rom_table:32; + }; + uint32_t val; +} hp_system_rom_table_reg_t; + +/** Type of core_debug_runstall_conf register + * Core Debug RunStall configurion register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_runstalled : RO; bitpos: [1]; default: 0; + * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: + * not stalled. + */ + uint32_t core_runstalled:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_core_debug_runstall_conf_reg_t; + +/** Type of sprom_ctrl register + * reserved + */ +typedef union { + struct { + /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + * reserved + */ + uint32_t sprom_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_system_sprom_ctrl_reg_t; + +/** Type of spram_ctrl register + * reserved + */ +typedef union { + struct { + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ + uint32_t spram_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_system_spram_ctrl_reg_t; + +/** Type of sprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ + uint32_t sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_system_sprf_ctrl_reg_t; + +/** Type of sdprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_system_sdprf_ctrl_reg_t; + +/** Type of clock_gate register + * HP-SYSTEM clock gating configure register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_clock_gate_reg_t; + + +/** Group: Timeout Register */ +/** Type of cpu_peri_timeout_conf register + * CPU_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Configures the timeout threshold for bus access for accessing CPU peripheral + * register in the number of clock cycles of the clock domain. + */ + uint32_t cpu_peri_timeout_thres:16; + /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Write 1 to clear timeout interrupt. + */ + uint32_t cpu_peri_timeout_int_clear:1; + /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Configures whether or not to enable timeout protection for accessing CPU peripheral + * registers.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t cpu_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_system_cpu_peri_timeout_conf_reg_t; + +/** Type of cpu_peri_timeout_addr register + * CPU_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Represents the address information of abnormal access. + */ + uint32_t cpu_peri_timeout_addr:32; + }; + uint32_t val; +} hp_system_cpu_peri_timeout_addr_reg_t; + +/** Type of cpu_peri_timeout_uid register + * CPU_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This + * register will be cleared after the interrupt is cleared. + */ + uint32_t cpu_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_system_cpu_peri_timeout_uid_reg_t; + +/** Type of hp_peri_timeout_conf register + * HP_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Configures the timeout threshold for bus access for accessing HP peripheral + * register, corresponding to the number of clock cycles of the clock domain. + */ + uint32_t hp_peri_timeout_thres:16; + /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear timeout interrupt.\\ + * 0: No effect\\ + * 1: Clear timeout interrupt\\ + */ + uint32_t hp_peri_timeout_int_clear:1; + /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Configures whether or not to enable timeout protection for accessing HP peripheral + * registers.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t hp_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_system_hp_peri_timeout_conf_reg_t; + +/** Type of hp_peri_timeout_addr register + * HP_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Represents the address information of abnormal access. + */ + uint32_t hp_peri_timeout_addr:32; + }; + uint32_t val; +} hp_system_hp_peri_timeout_addr_reg_t; + +/** Type of hp_peri_timeout_uid register + * HP_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This + * register will be cleared after the interrupt is cleared. + */ + uint32_t hp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_system_hp_peri_timeout_uid_reg_t; + +/** Type of modem_peri_timeout_conf register + * MODEM_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t modem_peri_timeout_thres:16; + /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t modem_peri_timeout_int_clear:1; + /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing modem registers + */ + uint32_t modem_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_system_modem_peri_timeout_conf_reg_t; + +/** Type of modem_peri_timeout_addr register + * MODEM_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t modem_peri_timeout_addr:32; + }; + uint32_t val; +} hp_system_modem_peri_timeout_addr_reg_t; + +/** Type of modem_peri_timeout_uid register + * MODEM_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t modem_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_system_modem_peri_timeout_uid_reg_t; + + +/** Group: Redcy ECO Registers */ +/** Type of rnd_eco register + * redcy eco register. + */ +typedef union { + struct { + /** redcy_ena : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_ena:1; + /** redcy_result : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_rnd_eco_reg_t; + +/** Type of rnd_eco_low register + * redcy eco low register. + */ +typedef union { + struct { + /** redcy_low : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_low:32; + }; + uint32_t val; +} hp_system_rnd_eco_low_reg_t; + +/** Type of rnd_eco_high register + * redcy eco high register. + */ +typedef union { + struct { + /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ + uint32_t redcy_high:32; + }; + uint32_t val; +} hp_system_rnd_eco_high_reg_t; + + +/** Group: Debug Register */ +/** Type of debug register + * HP-SYSTEM debug register + */ +typedef union { + struct { + /** fpga_debug : R/W; bitpos: [0]; default: 1; + * Reserved + */ + uint32_t fpga_debug:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_debug_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date control and version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36769824; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_system_date_reg_t; + + +typedef struct { + volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; + volatile hp_system_sram_usage_conf_reg_t sram_usage_conf; + volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf; + volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; + volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; + volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; + volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; + volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; + volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; + volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf; + volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr; + volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid; + volatile hp_system_rom_table_lock_reg_t rom_table_lock; + volatile hp_system_rom_table_reg_t rom_table; + volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf; + volatile hp_system_sprom_ctrl_reg_t sprom_ctrl; + volatile hp_system_spram_ctrl_reg_t spram_ctrl; + volatile hp_system_sprf_ctrl_reg_t sprf_ctrl; + volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl; + volatile hp_system_rnd_eco_reg_t rnd_eco; + volatile hp_system_rnd_eco_low_reg_t rnd_eco_low; + volatile hp_system_rnd_eco_high_reg_t rnd_eco_high; + volatile hp_system_debug_reg_t debug; + volatile hp_system_clock_gate_reg_t clock_gate; + uint32_t reserved_060[231]; + volatile hp_system_date_reg_t date; +} hp_system_dev_t; + +extern hp_system_dev_t HP_SYSTEM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/i2c_reg.h b/components/soc/esp32c61/include/soc/i2c_reg.h new file mode 100644 index 0000000000..07e1c4309d --- /dev/null +++ b/components/soc/esp32c61/include/soc/i2c_reg.h @@ -0,0 +1,1518 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock in master mode. \\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define I2C_SCL_LOW_PERIOD_S 0 + +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) +/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * Configures the SDA output mode.\\ + * 0: Open drain output \\ + * 1: Direct output \\ + */ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) +#define I2C_SDA_FORCE_OUT_V 0x00000001U +#define I2C_SDA_FORCE_OUT_S 0 +/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * Configures the SCL output mode.\\ + * 0: Open drain output \\ + * 1: Direct output \\ + */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) +#define I2C_SCL_FORCE_OUT_V 0x00000001U +#define I2C_SCL_FORCE_OUT_S 1 +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA.\\ + * 0: Sample SDA data on the SCL high level \\ + * 1: Sample SDA data on the SCL low level \\ + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold.\\ + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; + * Configures the module as an I2C Master or Slave.\\ + * 0: Slave \\ + * 1: Master \\ + */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) +#define I2C_MS_MODE_V 0x00000001U +#define I2C_MS_MODE_S 4 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Configures whether the slave starts sending the data in txfifo.\\ + * 0: No effect \\ + * 1: Start + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent.\\ + * 0: send data from the most significant bit \\ + * 1: send data from the least significant bit \\ + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data.\\ + * 0: receive data from the most significant bit \\ + * 1: receive data from the least significant bit \\ + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers.\\ + * 0: Support clock only when registers are read or written to by software \\ + * 1: Force clock on for registers \\ + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection.\\ + * 0: No effect \\ + * 1: Enable \\ + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM.\\ + * 0: No effect \\ + * 1: Reset + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization.\\ + * 0: No effect \\ + * 1: Synchronize + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 +/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; + * Configures to enable slave to send data automatically\\ + * 0: Disable\\ + * 1: Enable \\ + */ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\ + * 0: Not check\\ + * 1: Check + */ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; + * Configures to support the 7 bit general call function.\\ + * 0: Not support \\ + * 1: Support \\ + */ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) +#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/** I2C_SR_REG register + * Describe I2C work status + */ +#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode.\\ + * 0: ACK\\ + * 1: NACK. + */ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U +#define I2C_RESP_REC_S 0 +/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * Represents the transfer direction in slave mode.\\ + * 1: Master reads from slave\\ + * 0: Master writes to slave. + */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) +#define I2C_SLAVE_RW_V 0x00000001U +#define I2C_SLAVE_RW_S 1 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line.\\ + * 0: No arbitration lost\\ + * 1: Arbitration lost\\ + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state.\\ + * 1: The I2C bus is busy transferring data\\ + * 0: The I2C bus is in idle state.\\ + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; + * Represents whether the address sent by the master is equal to the address of the + * slave.\\ + * Valid only when the module is configured as an I2C Slave.\\ + * 0: Not equal\\ + * 1: Equal\\ + */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) +#define I2C_SLAVE_ADDRESSED_V 0x00000001U +#define I2C_SLAVE_ADDRESSED_S 5 +/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; + * Represents the number of data bytes received in RAM. + */ +#define I2C_RXFIFO_CNT 0x0000003FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000003FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; + * Represents the cause of SCL clocking stretching in slave mode.\\ + * 0: Stretching SCL low when the master starts to read data.\\ + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\ + * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. + */ +#define I2C_STRETCH_CAUSE 0x00000003U +#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) +#define I2C_STRETCH_CAUSE_V 0x00000003U +#define I2C_STRETCH_CAUSE_S 14 +/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; + * Represents the number of data bytes to be sent. + */ +#define I2C_TXFIFO_CNT 0x0000003FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000003FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine.\\ + * 0: Idle\\ + * 1: Address shift\\ + * 2: ACK address\\ + * 3: Rx data\\ + * 4: Tx data\\ + * 5: Send ACK\\ + * 6: Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL.\\ + * 0: Idle\\ + * 1: Start\\ + * 2: Negative edge\\ + * 3: Low\\ + * 4: Positive edge\\ + * 5: High\\ + * 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 + +/** I2C_TO_REG register + * Setting time out control for receiving data + */ +#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2\^{}(reg_time_out_value).\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU +#define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control.\\ + * 0: No effect \\ + * 1: Enable \\ + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 + +/** I2C_SLAVE_ADDR_REG register + * Local slave address setting + */ +#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) +/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * Configure the slave address of I2C Slave.\\ + */ +#define I2C_SLAVE_ADDR 0x00007FFFU +#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) +#define I2C_SLAVE_ADDR_V 0x00007FFFU +#define I2C_SLAVE_ADDR_S 0 +/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * Configures to enable the slave 10-bit addressing mode in master mode.\\ + * 0: No effect \\ + * 1: Enable \\ + */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) +#define I2C_ADDR_10BIT_EN_V 0x00000001U +#define I2C_ADDR_10BIT_EN_S 31 + +/** I2C_FIFO_ST_REG register + * FIFO status register + */ +#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO. + */ +#define I2C_RXFIFO_RADDR 0x0000001FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000001FU +#define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ +#define I2C_RXFIFO_WADDR 0x0000001FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000001FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ +#define I2C_TXFIFO_RADDR 0x0000001FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000001FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ +#define I2C_TXFIFO_WADDR 0x0000001FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000001FU +#define I2C_TXFIFO_WADDR_S 15 +/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C slave mode. + */ +#define I2C_SLAVE_RW_POINT 0x000000FFU +#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) +#define I2C_SLAVE_RW_POINT_V 0x000000FFU +#define I2C_SLAVE_RW_POINT_S 22 + +/** I2C_FIFO_CONF_REG register + * FIFO configuration register + */ +#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], + * I2C_RXFIFO_WM_INT_RAW bit will be valid. + * \tododone{For CJ, please check this description. I habe doubt about + * reg_reg_fifo_prt_en.CJ: modified} + */ +#define I2C_RXFIFO_WM_THRHD 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0], + * I2C_TXFIFO_WM_INT_RAW bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; + * Configures the slave to enable dual address mode. When this mode is enabled, the + * byte received after the I2C address byte represents the offset address in the I2C + * Slave RAM. \\ + * 0: Disable\\ + * 1: Enable \\ + */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) +#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO.\\ + * 0: No effect \\ + * 1: Reset + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO.\\ + * 0: No effect \\ + * 1: Reset + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\ + * 0: No effect \\ + * 1: Enable \\ + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 + +/** I2C_DATA_REG register + * Rx FIFO read data + */ +#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) +/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU +#define I2C_FIFO_RDATA_S 0 + +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 +/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) +#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 + +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 +/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; + * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) +#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 + +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to enable the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to enable the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * Write 1 to enable I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 +/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; + * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) +#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 + +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 +/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) +#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ST_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 + +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge + */ +#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU +#define I2C_SDA_HOLD_TIME_S 0 + +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge + */ +#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time for sampling SDA.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_S 0 + +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_S 0 + +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edgeof SCL and the + * positive edge of SDA, in I2C module clock cycles. + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU +#define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. \\ + * 0: No effect \\ + * 1: Enable \\ + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. \\ + * 0: No effect \\ + * 1: Enable \\ + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 + +/** I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) +/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_NUM 0x000000FFU +#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) +#define I2C_SCLK_DIV_NUM_V 0x000000FFU +#define I2C_SCLK_DIV_NUM_S 0 +/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_A 0x0000003FU +#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) +#define I2C_SCLK_DIV_A_V 0x0000003FU +#define I2C_SCLK_DIV_A_S 8 +/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_B 0x0000003FU +#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) +#define I2C_SCLK_DIV_B_V 0x0000003FU +#define I2C_SCLK_DIV_B_S 14 +/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) +#define I2C_SCLK_SEL_V 0x00000001U +#define I2C_SCLK_SEL_S 20 +/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) +#define I2C_SCLK_ACTIVE_V 0x00000001U +#define I2C_SCLK_ACTIVE_S 21 + +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. \\ + * It consists of three parts:\\ + * op_code is the command\\ + * 1: WRITE\\ + * 2: STOP\\ + * 3: READ\\ + * 4: END\\ + * 6: RSTART\\ + * Byte_num represents the number of bytes that need to be sent or received.\\ + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure link for more information. + * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU +#define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 + +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1.\\ + * See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU +#define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 + +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU +#define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 + +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU +#define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 + +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU +#define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 + +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU +#define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 + +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU +#define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 + +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU +#define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 + +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 + +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be + * no more than 23.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to I2C_SCL_RST_SLV_NUM[4:0]. + */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U +#define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. \\ + * Valid when I2C_SCL_RST_SLV_EN is 1.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * Configures to power down the I2C output SCL line. \\ + * 0: Not power down.\\ + * 1: Not work and power down.\\ + * Valid only when I2C_SCL_FORCE_OUT is 1. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SDA line. \\ + * 0: Not power down.\\ + * 1: Not work and power down.\\ + * Valid only when I2C_SDA_FORCE_OUT is 1. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 + +/** I2C_SCL_STRETCH_CONF_REG register + * Set SCL stretch of I2C slave + */ +#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) +/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time.\\ + * Measurement unit: i2c_sclk \\ + */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) +#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_S 0 +/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable slave SCL stretch function. The SCL output line will be + * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The + * stretch cause can be seen in I2C_STRETCH_CAUSE.\\ + * 0: Disable \\ + * 1: Enable \\ + */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; + * Configures to clear the I2C slave SCL stretch function.\\ + * 0: No effect \\ + * 1: Clear\\ + */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; + * Configures to enable the function for slave to control ACK level.\\ + * 0: Disable \\ + * 1: Enable \\ + */ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables.\\ + * 0: Low level\\ + * 1: High level \\ + */ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 37752896; + * Version control register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU +#define I2C_DATE_S 0 + +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) +/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 + +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) +/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/i2c_struct.h b/components/soc/esp32c61/include/soc/i2c_struct.h new file mode 100644 index 0000000000..5c16c1e6e5 --- /dev/null +++ b/components/soc/esp32c61/include/soc/i2c_struct.h @@ -0,0 +1,1115 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock in master mode. \\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time for sampling SDA.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edgeof SCL and the + * positive edge of SDA, in I2C module clock cycles. + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be + * no more than 23.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 0; + * Configures the SDA output mode.\\ + * 0: Open drain output \\ + * 1: Direct output \\ + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 0; + * Configures the SCL output mode.\\ + * 0: Open drain output \\ + * 1: Direct output \\ + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA.\\ + * 0: Sample SDA data on the SCL high level \\ + * 1: Sample SDA data on the SCL low level \\ + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold.\\ + */ + uint32_t rx_full_ack_level:1; + /** ms_mode : R/W; bitpos: [4]; default: 0; + * Configures the module as an I2C Master or Slave.\\ + * 0: Slave \\ + * 1: Master \\ + */ + uint32_t ms_mode:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Configures whether the slave starts sending the data in txfifo.\\ + * 0: No effect \\ + * 1: Start + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent.\\ + * 0: send data from the most significant bit \\ + * 1: send data from the least significant bit \\ + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data.\\ + * 0: receive data from the most significant bit \\ + * 1: receive data from the least significant bit \\ + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers.\\ + * 0: Support clock only when registers are read or written to by software \\ + * 1: Force clock on for registers \\ + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection.\\ + * 0: No effect \\ + * 1: Enable \\ + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM.\\ + * 0: No effect \\ + * 1: Reset + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization.\\ + * 0: No effect \\ + * 1: Synchronize + */ + uint32_t conf_upgate:1; + /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; + * Configures to enable slave to send data automatically\\ + * 0: Disable\\ + * 1: Enable \\ + */ + uint32_t slv_tx_auto_start_en:1; + /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\ + * 0: Not check\\ + * 1: Check + */ + uint32_t addr_10bit_rw_check_en:1; + /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; + * Configures to support the 7 bit general call function.\\ + * 0: Not support \\ + * 1: Support \\ + */ + uint32_t addr_broadcasting_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2\^{}(reg_time_out_value).\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control.\\ + * 0: No effect \\ + * 1: Enable \\ + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of slave_addr register + * Local slave address setting + */ +typedef union { + struct { + /** slave_addr : R/W; bitpos: [14:0]; default: 0; + * Configure the slave address of I2C Slave.\\ + */ + uint32_t slave_addr:15; + uint32_t reserved_15:16; + /** addr_10bit_en : R/W; bitpos: [31]; default: 0; + * Configures to enable the slave 10-bit addressing mode in master mode.\\ + * 0: No effect \\ + * 1: Enable \\ + */ + uint32_t addr_10bit_en:1; + }; + uint32_t val; +} i2c_slave_addr_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], + * I2C_RXFIFO_WM_INT_RAW bit will be valid. + * \tododone{For CJ, please check this description. I habe doubt about + * reg_reg_fifo_prt_en.CJ: modified} + */ + uint32_t rxfifo_wm_thrhd:5; + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0], + * I2C_TXFIFO_WM_INT_RAW bit will be valid. + */ + uint32_t txfifo_wm_thrhd:5; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; + * Configures the slave to enable dual address mode. When this mode is enabled, the + * byte received after the I2C address byte represents the offset address in the I2C + * Slave RAM. \\ + * 0: Disable\\ + * 1: Enable \\ + */ + uint32_t fifo_addr_cfg_en:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO.\\ + * 0: No effect \\ + * 1: Reset + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO.\\ + * 0: No effect \\ + * 1: Reset + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\ + * 0: No effect \\ + * 1: Enable \\ + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk \\ + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. \\ + * 0: No effect \\ + * 1: Enable \\ + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. \\ + * 0: No effect \\ + * 1: Enable \\ + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to I2C_SCL_RST_SLV_NUM[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. \\ + * Valid when I2C_SCL_RST_SLV_EN is 1.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * Configures to power down the I2C output SCL line. \\ + * 0: Not power down.\\ + * 1: Not work and power down.\\ + * Valid only when I2C_SCL_FORCE_OUT is 1. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SDA line. \\ + * 0: Not power down.\\ + * 1: Not work and power down.\\ + * Valid only when I2C_SDA_FORCE_OUT is 1. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ +typedef union { + struct { + /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time.\\ + * Measurement unit: i2c_sclk \\ + */ + uint32_t stretch_protect_num:10; + /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; + * Configures to enable slave SCL stretch function. The SCL output line will be + * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The + * stretch cause can be seen in I2C_STRETCH_CAUSE.\\ + * 0: Disable \\ + * 1: Enable \\ + */ + uint32_t slave_scl_stretch_en:1; + /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; + * Configures to clear the I2C slave SCL stretch function.\\ + * 0: No effect \\ + * 1: Clear\\ + */ + uint32_t slave_scl_stretch_clr:1; + /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; + * Configures to enable the function for slave to control ACK level.\\ + * 0: Disable \\ + * 1: Enable \\ + */ + uint32_t slave_byte_ack_ctl_en:1; + /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables.\\ + * 0: Low level\\ + * 1: High level \\ + */ + uint32_t slave_byte_ack_lvl:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} i2c_scl_stretch_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode.\\ + * 0: ACK\\ + * 1: NACK. + */ + uint32_t resp_rec:1; + /** slave_rw : RO; bitpos: [1]; default: 0; + * Represents the transfer direction in slave mode.\\ + * 1: Master reads from slave\\ + * 0: Master writes to slave. + */ + uint32_t slave_rw:1; + uint32_t reserved_2:1; + /** arb_lost : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line.\\ + * 0: No arbitration lost\\ + * 1: Arbitration lost\\ + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state.\\ + * 1: The I2C bus is busy transferring data\\ + * 0: The I2C bus is in idle state.\\ + */ + uint32_t bus_busy:1; + /** slave_addressed : RO; bitpos: [5]; default: 0; + * Represents whether the address sent by the master is equal to the address of the + * slave.\\ + * Valid only when the module is configured as an I2C Slave.\\ + * 0: Not equal\\ + * 1: Equal\\ + */ + uint32_t slave_addressed:1; + uint32_t reserved_6:2; + /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; + * Represents the number of data bytes received in RAM. + */ + uint32_t rxfifo_cnt:6; + /** stretch_cause : RO; bitpos: [15:14]; default: 3; + * Represents the cause of SCL clocking stretching in slave mode.\\ + * 0: Stretching SCL low when the master starts to read data.\\ + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\ + * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. + */ + uint32_t stretch_cause:2; + uint32_t reserved_16:2; + /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; + * Represents the number of data bytes to be sent. + */ + uint32_t txfifo_cnt:6; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine.\\ + * 0: Idle\\ + * 1: Address shift\\ + * 2: ACK address\\ + * 3: Rx data\\ + * 4: Tx data\\ + * 5: Send ACK\\ + * 6: Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL.\\ + * 0: Idle\\ + * 1: Start\\ + * 2: Negative edge\\ + * 3: Low\\ + * 4: Positive edge\\ + * 5: High\\ + * 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO. + */ + uint32_t rxfifo_raddr:5; + /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ + uint32_t rxfifo_waddr:5; + /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ + uint32_t txfifo_raddr:5; + /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ + uint32_t txfifo_waddr:5; + uint32_t reserved_20:2; + /** slave_rw_point : RO; bitpos: [29:22]; default: 0; + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C slave mode. + */ + uint32_t slave_rw_point:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data + */ +typedef union { + struct { + /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_raw:1; + /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_raw:1; + /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_raw:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_clr:1; + /** general_call_int_clr : WT; bitpos: [17]; default: 0; + * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_clr:1; + /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_clr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to enable the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to enable the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * Write 1 to enable I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_ena:1; + /** general_call_int_ena : R/W; bitpos: [17]; default: 0; + * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_ena:1; + /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_ena:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_st:1; + /** general_call_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_st:1; + /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_st:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd register + * I2C command register 0 + */ +typedef union { + struct { + /** command : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. \\ + * It consists of three parts:\\ + * op_code is the command\\ + * 1: WRITE\\ + * 2: STOP\\ + * 3: READ\\ + * 4: END\\ + * 6: RSTART\\ + * Byte_num represents the number of bytes that need to be sent or received.\\ + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure link for more information. + * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + */ + uint32_t command:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode.\\ + * 0: Not done \\ + * 1: Done \\ + */ + uint32_t command_done:1; + }; + uint32_t val; +} i2c_comd_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 37752896; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + volatile i2c_slave_addr_reg_t slave_addr; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + volatile i2c_clk_conf_reg_t clk_conf; + volatile i2c_comd_reg_t comd[8]; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; + uint32_t reserved_088[28]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} i2c_dev_t; + +extern i2c_dev_t I2C; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/i2s_reg.h b/components/soc/esp32c61/include/soc/i2s_reg.h new file mode 100644 index 0000000000..a7f16f4d61 --- /dev/null +++ b/components/soc/esp32c61/include/soc/i2s_reg.h @@ -0,0 +1,1275 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2S_INT_RAW_REG register + * I2S interrupt raw register, valid in level. + */ +#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) +/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S) +#define I2S_RX_DONE_INT_RAW_V 0x00000001U +#define I2S_RX_DONE_INT_RAW_S 0 +/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S) +#define I2S_TX_DONE_INT_RAW_V 0x00000001U +#define I2S_TX_DONE_INT_RAW_S 1 +/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001U +#define I2S_RX_HUNG_INT_RAW_S 2 +/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001U +#define I2S_TX_HUNG_INT_RAW_S 3 + +/** I2S_INT_ST_REG register + * I2S interrupt status register. + */ +#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) +/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S) +#define I2S_RX_DONE_INT_ST_V 0x00000001U +#define I2S_RX_DONE_INT_ST_S 0 +/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S) +#define I2S_TX_DONE_INT_ST_V 0x00000001U +#define I2S_TX_DONE_INT_ST_S 1 +/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001U +#define I2S_RX_HUNG_INT_ST_S 2 +/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001U +#define I2S_TX_HUNG_INT_ST_S 3 + +/** I2S_INT_ENA_REG register + * I2S interrupt enable register. + */ +#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) +/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S) +#define I2S_RX_DONE_INT_ENA_V 0x00000001U +#define I2S_RX_DONE_INT_ENA_S 0 +/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S) +#define I2S_TX_DONE_INT_ENA_V 0x00000001U +#define I2S_TX_DONE_INT_ENA_S 1 +/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001U +#define I2S_RX_HUNG_INT_ENA_S 2 +/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001U +#define I2S_TX_HUNG_INT_ENA_S 3 + +/** I2S_INT_CLR_REG register + * I2S interrupt clear register. + */ +#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) +/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S) +#define I2S_RX_DONE_INT_CLR_V 0x00000001U +#define I2S_RX_DONE_INT_CLR_S 0 +/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S) +#define I2S_TX_DONE_INT_CLR_V 0x00000001U +#define I2S_TX_DONE_INT_CLR_S 1 +/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001U +#define I2S_RX_HUNG_INT_CLR_S 2 +/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001U +#define I2S_TX_HUNG_INT_CLR_S 3 + +/** I2S_RX_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20) +/** I2S_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001U +#define I2S_RX_RESET_S 0 +/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001U +#define I2S_RX_FIFO_RESET_S 1 +/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001U +#define I2S_RX_START_S 2 +/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001U +#define I2S_RX_SLAVE_MOD_S 3 +/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ +#define I2S_RX_STOP_MODE 0x00000003U +#define I2S_RX_STOP_MODE_M (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S) +#define I2S_RX_STOP_MODE_V 0x00000003U +#define I2S_RX_STOP_MODE_S 4 +/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ +#define I2S_RX_MONO (BIT(6)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001U +#define I2S_RX_MONO_S 6 +/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001U +#define I2S_RX_BIG_ENDIAN_S 7 +/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S) +#define I2S_RX_UPDATE_V 0x00000001U +#define I2S_RX_UPDATE_S 8 +/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S) +#define I2S_RX_MONO_FST_VLD_V 0x00000001U +#define I2S_RX_MONO_FST_VLD_S 9 +/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_RX_PCM_CONF 0x00000003U +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000003U +#define I2S_RX_PCM_CONF_S 10 +/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001U +#define I2S_RX_PCM_BYPASS_S 12 +/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ +#define I2S_RX_MSB_SHIFT (BIT(13)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001U +#define I2S_RX_MSB_SHIFT_S 13 +/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S) +#define I2S_RX_LEFT_ALIGN_V 0x00000001U +#define I2S_RX_LEFT_ALIGN_S 15 +/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S) +#define I2S_RX_24_FILL_EN_V 0x00000001U +#define I2S_RX_24_FILL_EN_S 16 +/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S) +#define I2S_RX_WS_IDLE_POL_V 0x00000001U +#define I2S_RX_WS_IDLE_POL_S 17 +/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S) +#define I2S_RX_BIT_ORDER_V 0x00000001U +#define I2S_RX_BIT_ORDER_S 18 +/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S) +#define I2S_RX_TDM_EN_V 0x00000001U +#define I2S_RX_TDM_EN_S 19 +/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S) +#define I2S_RX_PDM_EN_V 0x00000001U +#define I2S_RX_PDM_EN_S 20 +/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ +#define I2S_RX_BCK_DIV_NUM 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_S 21 + +/** I2S_TX_CONF_REG register + * I2S TX configure register + */ +#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24) +/** I2S_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001U +#define I2S_TX_RESET_S 0 +/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001U +#define I2S_TX_FIFO_RESET_S 1 +/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001U +#define I2S_TX_START_S 2 +/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001U +#define I2S_TX_SLAVE_MOD_S 3 +/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ +#define I2S_TX_STOP_EN (BIT(4)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001U +#define I2S_TX_STOP_EN_S 4 +/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ +#define I2S_TX_CHAN_EQUAL (BIT(5)) +#define I2S_TX_CHAN_EQUAL_M (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S) +#define I2S_TX_CHAN_EQUAL_V 0x00000001U +#define I2S_TX_CHAN_EQUAL_S 5 +/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ +#define I2S_TX_MONO (BIT(6)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001U +#define I2S_TX_MONO_S 6 +/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001U +#define I2S_TX_BIG_ENDIAN_S 7 +/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S) +#define I2S_TX_UPDATE_V 0x00000001U +#define I2S_TX_UPDATE_S 8 +/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S) +#define I2S_TX_MONO_FST_VLD_V 0x00000001U +#define I2S_TX_MONO_FST_VLD_S 9 +/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_TX_PCM_CONF 0x00000003U +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000003U +#define I2S_TX_PCM_CONF_S 10 +/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001U +#define I2S_TX_PCM_BYPASS_S 12 +/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ +#define I2S_TX_MSB_SHIFT (BIT(13)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001U +#define I2S_TX_MSB_SHIFT_S 13 +/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ +#define I2S_TX_BCK_NO_DLY (BIT(14)) +#define I2S_TX_BCK_NO_DLY_M (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S) +#define I2S_TX_BCK_NO_DLY_V 0x00000001U +#define I2S_TX_BCK_NO_DLY_S 14 +/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S) +#define I2S_TX_LEFT_ALIGN_V 0x00000001U +#define I2S_TX_LEFT_ALIGN_S 15 +/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S) +#define I2S_TX_24_FILL_EN_V 0x00000001U +#define I2S_TX_24_FILL_EN_S 16 +/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S) +#define I2S_TX_WS_IDLE_POL_V 0x00000001U +#define I2S_TX_WS_IDLE_POL_S 17 +/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S) +#define I2S_TX_BIT_ORDER_V 0x00000001U +#define I2S_TX_BIT_ORDER_S 18 +/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S) +#define I2S_TX_TDM_EN_V 0x00000001U +#define I2S_TX_TDM_EN_S 19 +/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S) +#define I2S_TX_PDM_EN_V 0x00000001U +#define I2S_TX_PDM_EN_S 20 +/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ +#define I2S_TX_BCK_DIV_NUM 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_S 21 +/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ +#define I2S_TX_CHAN_MOD 0x00000007U +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007U +#define I2S_TX_CHAN_MOD_S 27 +/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ +#define I2S_SIG_LOOPBACK (BIT(30)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001U +#define I2S_SIG_LOOPBACK_S 30 + +/** I2S_RX_CONF1_REG register + * I2S RX configure register 1 + */ +#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28) +/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_RX_TDM_WS_WIDTH 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_M (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S) +#define I2S_RX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_S 0 +/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_RX_BITS_MOD 0x0000001FU +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000001FU +#define I2S_RX_BITS_MOD_S 14 +/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ +#define I2S_RX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_M (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_S 19 +/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ +#define I2S_RX_TDM_CHAN_BITS 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_M (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S) +#define I2S_RX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_CONF1_REG register + * I2S TX configure register 1 + */ +#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c) +/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_TX_TDM_WS_WIDTH 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_M (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S) +#define I2S_TX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_S 0 +/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_TX_BITS_MOD 0x0000001FU +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000001FU +#define I2S_TX_BITS_MOD_S 14 +/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ +#define I2S_TX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_M (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_S 19 +/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ +#define I2S_TX_TDM_CHAN_BITS 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_M (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S) +#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_PCM2PDM_CONF_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40) +/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0; + * I2S TX PDM bypass hp filter or not. The option has been removed. + */ +#define I2S_TX_PDM_HP_BYPASS (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_M (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S) +#define I2S_TX_PDM_HP_BYPASS_V 0x00000001U +#define I2S_TX_PDM_HP_BYPASS_S 0 +/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_M (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S) +#define I2S_TX_PDM_SINC_OSR2_V 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_S 1 +/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ +#define I2S_TX_PDM_PRESCALE 0x000000FFU +#define I2S_TX_PDM_PRESCALE_M (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S) +#define I2S_TX_PDM_PRESCALE_V 0x000000FFU +#define I2S_TX_PDM_PRESCALE_S 5 +/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_M (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_M (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_M (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S) +#define I2S_PCM2PDM_CONV_EN_V 0x00000001U +#define I2S_PCM2PDM_CONV_EN_S 25 + +/** I2S_TX_PCM2PDM_CONF1_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44) +/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ +#define I2S_TX_PDM_FP 0x000003FFU +#define I2S_TX_PDM_FP_M (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S) +#define I2S_TX_PDM_FP_V 0x000003FFU +#define I2S_TX_PDM_FP_S 0 +/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ +#define I2S_TX_PDM_FS 0x000003FFU +#define I2S_TX_PDM_FS_M (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S) +#define I2S_TX_PDM_FS_V 0x000003FFU +#define I2S_TX_PDM_FS_S 10 +/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_M (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S) +#define I2S_TX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_M (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S) +#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_S 23 + +/** I2S_RX_PDM2PCM_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48) +/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ +#define I2S_RX_PDM2PCM_EN (BIT(19)) +#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S) +#define I2S_RX_PDM2PCM_EN_V 0x00000001U +#define I2S_RX_PDM2PCM_EN_S 19 +/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U +#define I2S_RX_PDM_SINC_DSR_16_EN_S 20 +/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ +#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S) +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21 +/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ +#define I2S_RX_PDM_HP_BYPASS (BIT(25)) +#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S) +#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U +#define I2S_RX_PDM_HP_BYPASS_S 25 +/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_RX_IIR_HP_MULT12_5 0x00000007U +#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S) +#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_RX_IIR_HP_MULT12_5_S 26 +/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_RX_IIR_HP_MULT12_0 0x00000007U +#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S) +#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_RX_IIR_HP_MULT12_0_S 29 + +/** I2S_RX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50) +/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S) +#define I2S_RX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN8_EN_S 8 +/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S) +#define I2S_RX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN9_EN_S 9 +/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S) +#define I2S_RX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN10_EN_S 10 +/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S) +#define I2S_RX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN11_EN_S 11 +/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S) +#define I2S_RX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN12_EN_S 12 +/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S) +#define I2S_RX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN13_EN_S 13 +/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S) +#define I2S_RX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN14_EN_S 14 +/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S) +#define I2S_RX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN15_EN_S 15 +/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_M (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 + +/** I2S_TX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54) +/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S) +#define I2S_TX_TDM_CHAN0_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN0_EN_S 0 +/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S) +#define I2S_TX_TDM_CHAN1_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN1_EN_S 1 +/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S) +#define I2S_TX_TDM_CHAN2_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN2_EN_S 2 +/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S) +#define I2S_TX_TDM_CHAN3_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN3_EN_S 3 +/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S) +#define I2S_TX_TDM_CHAN4_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN4_EN_S 4 +/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S) +#define I2S_TX_TDM_CHAN5_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN5_EN_S 5 +/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S) +#define I2S_TX_TDM_CHAN6_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN6_EN_S 6 +/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S) +#define I2S_TX_TDM_CHAN7_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN7_EN_S 7 +/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S) +#define I2S_TX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN8_EN_S 8 +/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S) +#define I2S_TX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN9_EN_S 9 +/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S) +#define I2S_TX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN10_EN_S 10 +/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S) +#define I2S_TX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN11_EN_S 11 +/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S) +#define I2S_TX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN12_EN_S 12 +/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S) +#define I2S_TX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN13_EN_S 13 +/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S) +#define I2S_TX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN14_EN_S 14 +/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S) +#define I2S_TX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN15_EN_S 15 +/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_M (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x00000001U +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 + +/** I2S_RX_TIMING_REG register + * I2S RX timing control register + */ +#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58) +/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD_IN_DM 0x00000003U +#define I2S_RX_SD_IN_DM_M (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S) +#define I2S_RX_SD_IN_DM_V 0x00000003U +#define I2S_RX_SD_IN_DM_S 0 +/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD1_IN_DM 0x00000003U +#define I2S_RX_SD1_IN_DM_M (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S) +#define I2S_RX_SD1_IN_DM_V 0x00000003U +#define I2S_RX_SD1_IN_DM_S 4 +/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0; + * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD2_IN_DM 0x00000003U +#define I2S_RX_SD2_IN_DM_M (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S) +#define I2S_RX_SD2_IN_DM_V 0x00000003U +#define I2S_RX_SD2_IN_DM_S 8 +/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0; + * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD3_IN_DM 0x00000003U +#define I2S_RX_SD3_IN_DM_M (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S) +#define I2S_RX_SD3_IN_DM_V 0x00000003U +#define I2S_RX_SD3_IN_DM_S 12 +/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_OUT_DM 0x00000003U +#define I2S_RX_WS_OUT_DM_M (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S) +#define I2S_RX_WS_OUT_DM_V 0x00000003U +#define I2S_RX_WS_OUT_DM_S 16 +/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_OUT_DM 0x00000003U +#define I2S_RX_BCK_OUT_DM_M (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S) +#define I2S_RX_BCK_OUT_DM_V 0x00000003U +#define I2S_RX_BCK_OUT_DM_S 20 +/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_IN_DM 0x00000003U +#define I2S_RX_WS_IN_DM_M (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S) +#define I2S_RX_WS_IN_DM_V 0x00000003U +#define I2S_RX_WS_IN_DM_S 24 +/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_IN_DM 0x00000003U +#define I2S_RX_BCK_IN_DM_M (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S) +#define I2S_RX_BCK_IN_DM_V 0x00000003U +#define I2S_RX_BCK_IN_DM_S 28 + +/** I2S_TX_TIMING_REG register + * I2S TX timing control register + */ +#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c) +/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD_OUT_DM 0x00000003U +#define I2S_TX_SD_OUT_DM_M (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S) +#define I2S_TX_SD_OUT_DM_V 0x00000003U +#define I2S_TX_SD_OUT_DM_S 0 +/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD1_OUT_DM 0x00000003U +#define I2S_TX_SD1_OUT_DM_M (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S) +#define I2S_TX_SD1_OUT_DM_V 0x00000003U +#define I2S_TX_SD1_OUT_DM_S 4 +/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_OUT_DM 0x00000003U +#define I2S_TX_WS_OUT_DM_M (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S) +#define I2S_TX_WS_OUT_DM_V 0x00000003U +#define I2S_TX_WS_OUT_DM_S 16 +/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_OUT_DM 0x00000003U +#define I2S_TX_BCK_OUT_DM_M (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S) +#define I2S_TX_BCK_OUT_DM_V 0x00000003U +#define I2S_TX_BCK_OUT_DM_S 20 +/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_IN_DM 0x00000003U +#define I2S_TX_WS_IN_DM_M (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S) +#define I2S_TX_WS_IN_DM_V 0x00000003U +#define I2S_TX_WS_IN_DM_S 24 +/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_IN_DM 0x00000003U +#define I2S_TX_BCK_IN_DM_M (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S) +#define I2S_TX_BCK_IN_DM_V 0x00000003U +#define I2S_TX_BCK_IN_DM_S 28 + +/** I2S_LC_HUNG_CONF_REG register + * I2S HUNG configure register. + */ +#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60) +/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_S 0 +/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/** I2S_RXEOF_NUM_REG register + * I2S RX data number control register. + */ +#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64) +/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ +#define I2S_RX_EOF_NUM 0x00000FFFU +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0x00000FFFU +#define I2S_RX_EOF_NUM_S 0 + +/** I2S_CONF_SIGLE_DATA_REG register + * I2S signal data register + */ +#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68) +/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ +#define I2S_SINGLE_DATA 0xFFFFFFFFU +#define I2S_SINGLE_DATA_M (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S) +#define I2S_SINGLE_DATA_V 0xFFFFFFFFU +#define I2S_SINGLE_DATA_S 0 + +/** I2S_STATE_REG register + * I2S TX status register + */ +#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c) +/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001U +#define I2S_TX_IDLE_S 0 + +/** I2S_ETM_CONF_REG register + * I2S ETM configure register + */ +#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70) +/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_TX_SEND_WORD_NUM 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_M (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S) +#define I2S_ETM_TX_SEND_WORD_NUM_V 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_S 0 +/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_RX_RECEIVE_WORD_NUM 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_M (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S) +#define I2S_ETM_RX_RECEIVE_WORD_NUM_V 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_S 10 + +/** I2S_FIFO_CNT_REG register + * I2S sync counter register + */ +#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74) +/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0; + * tx fifo counter value. + */ +#define I2S_TX_FIFO_CNT 0x7FFFFFFFU +#define I2S_TX_FIFO_CNT_M (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S) +#define I2S_TX_FIFO_CNT_V 0x7FFFFFFFU +#define I2S_TX_FIFO_CNT_S 0 +/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx fifo counter. + */ +#define I2S_TX_FIFO_CNT_RST (BIT(31)) +#define I2S_TX_FIFO_CNT_RST_M (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S) +#define I2S_TX_FIFO_CNT_RST_V 0x00000001U +#define I2S_TX_FIFO_CNT_RST_S 31 + +/** I2S_BCK_CNT_REG register + * I2S sync counter register + */ +#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78) +/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0; + * tx bck counter value. + */ +#define I2S_TX_BCK_CNT 0x7FFFFFFFU +#define I2S_TX_BCK_CNT_M (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S) +#define I2S_TX_BCK_CNT_V 0x7FFFFFFFU +#define I2S_TX_BCK_CNT_S 0 +/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx bck counter. + */ +#define I2S_TX_BCK_CNT_RST (BIT(31)) +#define I2S_TX_BCK_CNT_RST_M (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S) +#define I2S_TX_BCK_CNT_RST_V 0x00000001U +#define I2S_TX_BCK_CNT_RST_S 31 + +/** I2S_CLK_GATE_REG register + * Clock gate register + */ +#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c) +/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ +#define I2S_CLK_EN (BIT(0)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001U +#define I2S_CLK_EN_S 0 + +/** I2S_DATE_REG register + * Version control register + */ +#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80) +/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024; + * I2S version control register + */ +#define I2S_DATE 0x0FFFFFFFU +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0x0FFFFFFFU +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/i2s_struct.h b/components/soc/esp32c61/include/soc/i2s_struct.h new file mode 100644 index 0000000000..a0ff42939e --- /dev/null +++ b/components/soc/esp32c61/include/soc/i2s_struct.h @@ -0,0 +1,1010 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt registers */ +/** Type of int_raw register + * I2S interrupt raw register, valid in level. + */ +typedef union { + struct { + /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_raw:1; + /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_raw:1; + /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_raw_reg_t; + +/** Type of int_st register + * I2S interrupt status register. + */ +typedef union { + struct { + /** rx_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_st_reg_t; + +/** Type of int_ena register + * I2S interrupt enable register. + */ +typedef union { + struct { + /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_ena_reg_t; + +/** Type of int_clr register + * I2S interrupt clear register. + */ +typedef union { + struct { + /** rx_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of rx_conf register + * I2S RX configure register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ + uint32_t rx_reset:1; + /** rx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ + uint32_t rx_fifo_reset:1; + /** rx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ + uint32_t rx_start:1; + /** rx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ + uint32_t rx_slave_mod:1; + /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ + uint32_t rx_stop_mode:2; + /** rx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ + uint32_t rx_mono:1; + /** rx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ + uint32_t rx_big_endian:1; + /** rx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t rx_update:1; + /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ + uint32_t rx_mono_fst_vld:1; + /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t rx_pcm_conf:2; + /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + uint32_t rx_pcm_bypass:1; + /** rx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ + uint32_t rx_msb_shift:1; + uint32_t reserved_14:1; + /** rx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ + uint32_t rx_left_align:1; + /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ + uint32_t rx_24_fill_en:1; + /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ + uint32_t rx_ws_idle_pol:1; + /** rx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ + uint32_t rx_bit_order:1; + /** rx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ + uint32_t rx_tdm_en:1; + /** rx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ + uint32_t rx_pdm_en:1; + /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + uint32_t rx_bck_div_num:6; + uint32_t reserved_27:5; + }; + uint32_t val; +} i2s_rx_conf_reg_t; + +/** Type of rx_conf1 register + * I2S RX configure register 1 + */ +typedef union { + struct { + /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t rx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t rx_bits_mod:5; + /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ + uint32_t rx_half_sample_bits:8; + /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ + uint32_t rx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_rx_conf1_reg_t; + +/** Type of rx_pdm2pcm_conf register + * I2S RX configure register + */ +typedef union { + struct { + uint32_t reserved_0:19; + /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ + uint32_t rx_pdm2pcm_en:1; + /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ + uint32_t rx_pdm_sinc_dsr_16_en:1; + /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ + uint32_t rx_pdm2pcm_amplify_num:4; + /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ + uint32_t rx_pdm_hp_bypass:1; + /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t rx_iir_hp_mult12_5:3; + /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t rx_iir_hp_mult12_0:3; + }; + uint32_t val; +} i2s_rx_pdm2pcm_conf_reg_t; + +/** Type of rx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan0_en:1; + /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan1_en:1; + /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan2_en:1; + /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan3_en:1; + /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan4_en:1; + /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan5_en:1; + /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan6_en:1; + /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan7_en:1; + /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan8_en:1; + /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan9_en:1; + /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan10_en:1; + /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan11_en:1; + /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan12_en:1; + /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan13_en:1; + /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan14_en:1; + /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan15_en:1; + /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t rx_tdm_tot_chan_num:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_rx_tdm_ctrl_reg_t; + +/** Type of rxeof_num register + * I2S RX data number control register. + */ +typedef union { + struct { + /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ + uint32_t rx_eof_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_rxeof_num_reg_t; + + +/** Group: TX Control and configuration registers */ +/** Type of tx_conf register + * I2S TX configure register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + uint32_t tx_reset:1; + /** tx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ + uint32_t tx_fifo_reset:1; + /** tx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ + uint32_t tx_start:1; + /** tx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ + uint32_t tx_slave_mod:1; + /** tx_stop_en : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ + uint32_t tx_stop_en:1; + /** tx_chan_equal : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ + uint32_t tx_chan_equal:1; + /** tx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + uint32_t tx_mono:1; + /** tx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ + uint32_t tx_big_endian:1; + /** tx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t tx_update:1; + /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ + uint32_t tx_mono_fst_vld:1; + /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t tx_pcm_conf:2; + /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + uint32_t tx_pcm_bypass:1; + /** tx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ + uint32_t tx_msb_shift:1; + /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ + uint32_t tx_bck_no_dly:1; + /** tx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ + uint32_t tx_left_align:1; + /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ + uint32_t tx_24_fill_en:1; + /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ + uint32_t tx_ws_idle_pol:1; + /** tx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ + uint32_t tx_bit_order:1; + /** tx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ + uint32_t tx_tdm_en:1; + /** tx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ + uint32_t tx_pdm_en:1; + /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + uint32_t tx_bck_div_num:6; + /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + uint32_t tx_chan_mod:3; + /** sig_loopback : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ + uint32_t sig_loopback:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2s_tx_conf_reg_t; + +/** Type of tx_conf1 register + * I2S TX configure register 1 + */ +typedef union { + struct { + /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t tx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t tx_bits_mod:5; + /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ + uint32_t tx_half_sample_bits:8; + /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ + uint32_t tx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_tx_conf1_reg_t; + +/** Type of tx_pcm2pdm_conf register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0; + * I2S TX PDM bypass hp filter or not. The option has been removed. + */ + uint32_t tx_pdm_hp_bypass:1; + /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ + uint32_t tx_pdm_sinc_osr2:4; + /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ + uint32_t tx_pdm_prescale:8; + /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_hp_in_shift:2; + /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_lp_in_shift:2; + /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sinc_in_shift:2; + /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sigmadelta_in_shift:2; + /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ + uint32_t tx_pdm_sigmadelta_dither2:1; + /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ + uint32_t tx_pdm_sigmadelta_dither:1; + /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ + uint32_t tx_pdm_dac_2out_en:1; + /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ + uint32_t tx_pdm_dac_mode_en:1; + /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ + uint32_t pcm2pdm_conv_en:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf1 register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ + uint32_t tx_pdm_fp:10; + /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ + uint32_t tx_pdm_fs:10; + /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t tx_iir_hp_mult12_5:3; + /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t tx_iir_hp_mult12_0:3; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf1_reg_t; + +/** Type of tx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan0_en:1; + /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan1_en:1; + /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan2_en:1; + /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan3_en:1; + /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan4_en:1; + /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan5_en:1; + /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan6_en:1; + /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan7_en:1; + /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan8_en:1; + /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan9_en:1; + /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan10_en:1; + /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan11_en:1; + /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan12_en:1; + /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan13_en:1; + /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan14_en:1; + /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan15_en:1; + /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t tx_tdm_tot_chan_num:4; + /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ + uint32_t tx_tdm_skip_msk_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} i2s_tx_tdm_ctrl_reg_t; + + +/** Group: RX clock and timing registers */ +/** Type of rx_timing register + * I2S RX timing control register + */ +typedef union { + struct { + /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd_in_dm:2; + uint32_t reserved_2:2; + /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd1_in_dm:2; + uint32_t reserved_6:2; + /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0; + * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd2_in_dm:2; + uint32_t reserved_10:2; + /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0; + * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd3_in_dm:2; + uint32_t reserved_14:2; + /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_out_dm:2; + uint32_t reserved_18:2; + /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_out_dm:2; + uint32_t reserved_22:2; + /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_in_dm:2; + uint32_t reserved_26:2; + /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_timing_reg_t; + + +/** Group: TX clock and timing registers */ +/** Type of tx_timing register + * I2S TX timing control register + */ +typedef union { + struct { + /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd_out_dm:2; + uint32_t reserved_2:2; + /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd1_out_dm:2; + uint32_t reserved_6:10; + /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_out_dm:2; + uint32_t reserved_18:2; + /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_out_dm:2; + uint32_t reserved_22:2; + /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_in_dm:2; + uint32_t reserved_26:2; + /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_timing_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of lc_hung_conf register + * I2S HUNG configure register. + */ +typedef union { + struct { + /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ + uint32_t lc_fifo_timeout:8; + /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + uint32_t lc_fifo_timeout_shift:3; + /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + uint32_t lc_fifo_timeout_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_lc_hung_conf_reg_t; + +/** Type of conf_sigle_data register + * I2S signal data register + */ +typedef union { + struct { + /** single_data : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ + uint32_t single_data:32; + }; + uint32_t val; +} i2s_conf_sigle_data_reg_t; + + +/** Group: TX status registers */ +/** Type of state register + * I2S TX status register + */ +typedef union { + struct { + /** tx_idle : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ + uint32_t tx_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_state_reg_t; + + +/** Group: ETM registers */ +/** Type of etm_conf register + * I2S ETM configure register + */ +typedef union { + struct { + /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_tx_send_word_num:10; + /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_rx_receive_word_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_etm_conf_reg_t; + + +/** Group: Sync counter registers */ +/** Type of fifo_cnt register + * I2S sync counter register + */ +typedef union { + struct { + /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0; + * tx fifo counter value. + */ + uint32_t tx_fifo_cnt:31; + /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx fifo counter. + */ + uint32_t tx_fifo_cnt_rst:1; + }; + uint32_t val; +} i2s_fifo_cnt_reg_t; + +/** Type of bck_cnt register + * I2S sync counter register + */ +typedef union { + struct { + /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0; + * tx bck counter value. + */ + uint32_t tx_bck_cnt:31; + /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx bck counter. + */ + uint32_t tx_bck_cnt_rst:1; + }; + uint32_t val; +} i2s_bck_cnt_reg_t; + + +/** Group: Clock registers */ +/** Type of clk_gate register + * Clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_clk_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36713024; + * I2S version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile i2s_int_raw_reg_t int_raw; + volatile i2s_int_st_reg_t int_st; + volatile i2s_int_ena_reg_t int_ena; + volatile i2s_int_clr_reg_t int_clr; + uint32_t reserved_01c; + volatile i2s_rx_conf_reg_t rx_conf; + volatile i2s_tx_conf_reg_t tx_conf; + volatile i2s_rx_conf1_reg_t rx_conf1; + volatile i2s_tx_conf1_reg_t tx_conf1; + uint32_t reserved_030[4]; + volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; + volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; + volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf; + uint32_t reserved_04c; + volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; + volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; + volatile i2s_rx_timing_reg_t rx_timing; + volatile i2s_tx_timing_reg_t tx_timing; + volatile i2s_lc_hung_conf_reg_t lc_hung_conf; + volatile i2s_rxeof_num_reg_t rxeof_num; + volatile i2s_conf_sigle_data_reg_t conf_sigle_data; + volatile i2s_state_reg_t state; + volatile i2s_etm_conf_reg_t etm_conf; + volatile i2s_fifo_cnt_reg_t fifo_cnt; + volatile i2s_bck_cnt_reg_t bck_cnt; + volatile i2s_clk_gate_reg_t clk_gate; + volatile i2s_date_reg_t date; +} i2s_dev_t; + +extern i2s_dev_t I2S; + +#ifndef __cplusplus +_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c61/include/soc/interrupt_matrix_reg.h new file mode 100644 index 0000000000..f76f3e6593 --- /dev/null +++ b/components/soc/esp32c61/include/soc/interrupt_matrix_reg.h @@ -0,0 +1,814 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register + * WIFI_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register + * WIFI_MAC_NMI mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register + * WIFI_PWR_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register + * WIFI_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register + * BT_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register + * BT_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register + * BT_BB_NMI mapping register + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register + * LP_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register + * COEX_INTR mapping register + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) +#define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register + * BLE_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register + * BLE_SEC_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register + * I2C_MST_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register + * ZB_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register + * PMU_INTR mapping register + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) +#define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register + * EFUSE_INTR mapping register + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register + * LP_RTC_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register + * LP_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register + * LP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register + * LP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * CPU_INTR_FROM_CPU_1 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * CPU_INTR_FROM_CPU_2 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * CPU_INTR_FROM_CPU_3 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register + * ASSIST_DEBUG_INTR mapping register + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register + * TRACE_INTR mapping register + */ +#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TRACE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S) +#define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register + * CACHE_INTR mapping register + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * GPIO_INTERRUPT_PRO mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register + * GPIO_INTERRUPT_EXT mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0 + +/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register + * PAU_INTR mapping register + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) +#define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register + * HP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register + * MODEM_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register + * HP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register + * HP_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register + * HP_APM_M2_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register + * HP_APM_M3_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register + * MSPI_INTR mapping register + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register + * I2S1_INTR mapping register + */ +#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2S1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S) +#define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register + * UART0_INTR mapping register + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) +#define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register + * UART1_INTR mapping register + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART2_INTR_MAP_REG register + * UART2_INTR mapping register + */ +#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +/** INTERRUPT_CORE0_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART2_INTR_MAP_M (INTERRUPT_CORE0_UART2_INTR_MAP_V << INTERRUPT_CORE0_UART2_INTR_MAP_S) +#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register + * LEDC_INTR mapping register + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_INTR_MAP_REG register + * USB_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register + * I2C_EXT0_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register + * TG0_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register + * TG0_T1_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +/** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register + * TG0_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register + * TG1_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register + * TG1_T1_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +/** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register + * TG1_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register + * SYSTIMER_TARGET0_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register + * SYSTIMER_TARGET1_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register + * SYSTIMER_TARGET2_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register + * APB_ADC_INTR mapping register + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register + * DMA_IN_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register + * DMA_IN_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register + * DMA_OUT_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register + * DMA_OUT_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register + * GPSPI2_INTR mapping register + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register + * SHA_INTR mapping register + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) +#define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register + * ECC_INTR mapping register + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) +#define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register + * ECDSA_INTR mapping register + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_0_REG register + * Status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_M (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S) +#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_1_REG register + * Status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_M (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S) +#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_S 0 + +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 + +/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36774400; + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_M (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c61/include/soc/interrupt_matrix_struct.h new file mode 100644 index 0000000000..2b7d52e189 --- /dev/null +++ b/components/soc/esp32c61/include/soc/interrupt_matrix_struct.h @@ -0,0 +1,1023 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of wifi_mac_intr_map register + * WIFI_MAC_INTR mapping register + */ +typedef union { + struct { + /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_wifi_mac_intr_map_reg_t; + +/** Type of wifi_mac_nmi_map register + * WIFI_MAC_NMI mapping register + */ +typedef union { + struct { + /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_wifi_mac_nmi_map_reg_t; + +/** Type of wifi_pwr_intr_map register + * WIFI_PWR_INTR mapping register + */ +typedef union { + struct { + /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_pwr_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_wifi_pwr_intr_map_reg_t; + +/** Type of wifi_bb_intr_map register + * WIFI_BB_INTR mapping register + */ +typedef union { + struct { + /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_bb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_wifi_bb_intr_map_reg_t; + +/** Type of bt_mac_intr_map register + * BT_MAC_INTR mapping register + */ +typedef union { + struct { + /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_bt_mac_intr_map_reg_t; + +/** Type of bt_bb_intr_map register + * BT_BB_INTR mapping register + */ +typedef union { + struct { + /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_bt_bb_intr_map_reg_t; + +/** Type of bt_bb_nmi_map register + * BT_BB_NMI mapping register + */ +typedef union { + struct { + /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_bt_bb_nmi_map_reg_t; + +/** Type of lp_timer_intr_map register + * LP_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_lp_timer_intr_map_reg_t; + +/** Type of coex_intr_map register + * COEX_INTR mapping register + */ +typedef union { + struct { + /** coex_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t coex_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_coex_intr_map_reg_t; + +/** Type of ble_timer_intr_map register + * BLE_TIMER_INTR mapping register + */ +typedef union { + struct { + /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_ble_timer_intr_map_reg_t; + +/** Type of ble_sec_intr_map register + * BLE_SEC_INTR mapping register + */ +typedef union { + struct { + /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_sec_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_ble_sec_intr_map_reg_t; + +/** Type of i2c_mst_intr_map register + * I2C_MST_INTR mapping register + */ +typedef union { + struct { + /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_mst_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_i2c_mst_intr_map_reg_t; + +/** Type of zb_mac_intr_map register + * ZB_MAC_INTR mapping register + */ +typedef union { + struct { + /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t zb_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_zb_mac_intr_map_reg_t; + +/** Type of pmu_intr_map register + * PMU_INTR mapping register + */ +typedef union { + struct { + /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pmu_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_pmu_intr_map_reg_t; + +/** Type of efuse_intr_map register + * EFUSE_INTR mapping register + */ +typedef union { + struct { + /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t efuse_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_efuse_intr_map_reg_t; + +/** Type of lp_rtc_timer_intr_map register + * LP_RTC_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_rtc_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_lp_rtc_timer_intr_map_reg_t; + +/** Type of lp_wdt_intr_map register + * LP_WDT_INTR mapping register + */ +typedef union { + struct { + /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_lp_wdt_intr_map_reg_t; + +/** Type of lp_peri_timeout_intr_map register + * LP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_lp_peri_timeout_intr_map_reg_t; + +/** Type of lp_apm_m0_intr_map register + * LP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm_m0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_lp_apm_m0_intr_map_reg_t; + +/** Type of cpu_intr_from_cpu_0_map register + * CPU_INTR_FROM_CPU_0 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t; + +/** Type of cpu_intr_from_cpu_1_map register + * CPU_INTR_FROM_CPU_1 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t; + +/** Type of cpu_intr_from_cpu_2_map register + * CPU_INTR_FROM_CPU_2 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t; + +/** Type of cpu_intr_from_cpu_3_map register + * CPU_INTR_FROM_CPU_3 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t; + +/** Type of assist_debug_intr_map register + * ASSIST_DEBUG_INTR mapping register + */ +typedef union { + struct { + /** assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t assist_debug_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_assist_debug_intr_map_reg_t; + +/** Type of trace_intr_map register + * TRACE_INTR mapping register + */ +typedef union { + struct { + /** trace_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t trace_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_trace_intr_map_reg_t; + +/** Type of cache_intr_map register + * CACHE_INTR mapping register + */ +typedef union { + struct { + /** cache_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cache_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_cache_intr_map_reg_t; + +/** Type of cpu_peri_timeout_intr_map register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t; + +/** Type of gpio_interrupt_pro_map register + * GPIO_INTERRUPT_PRO mapping register + */ +typedef union { + struct { + /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_pro_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_gpio_interrupt_pro_map_reg_t; + +/** Type of gpio_interrupt_ext_map register + * GPIO_INTERRUPT_EXT mapping register + */ +typedef union { + struct { + /** gpio_interrupt_ext_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_ext_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_gpio_interrupt_ext_map_reg_t; + +/** Type of pau_intr_map register + * PAU_INTR mapping register + */ +typedef union { + struct { + /** pau_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pau_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_pau_intr_map_reg_t; + +/** Type of hp_peri_timeout_intr_map register + * HP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_hp_peri_timeout_intr_map_reg_t; + +/** Type of modem_peri_timeout_intr_map register + * MODEM_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t modem_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_modem_peri_timeout_intr_map_reg_t; + +/** Type of hp_apm_m0_intr_map register + * HP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m0_intr_map_reg_t; + +/** Type of hp_apm_m1_intr_map register + * HP_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m1_intr_map_reg_t; + +/** Type of hp_apm_m2_intr_map register + * HP_APM_M2_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m2_intr_map_reg_t; + +/** Type of hp_apm_m3_intr_map register + * HP_APM_M3_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m3_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m3_intr_map_reg_t; + +/** Type of mspi_intr_map register + * MSPI_INTR mapping register + */ +typedef union { + struct { + /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t mspi_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_mspi_intr_map_reg_t; + +/** Type of i2s1_intr_map register + * I2S1_INTR mapping register + */ +typedef union { + struct { + /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2s1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_i2s1_intr_map_reg_t; + +/** Type of uart0_intr_map register + * UART0_INTR mapping register + */ +typedef union { + struct { + /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_uart0_intr_map_reg_t; + +/** Type of uart1_intr_map register + * UART1_INTR mapping register + */ +typedef union { + struct { + /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_uart1_intr_map_reg_t; + +/** Type of uart2_intr_map register + * UART2_INTR mapping register + */ +typedef union { + struct { + /** uart2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_uart2_intr_map_reg_t; + +/** Type of ledc_intr_map register + * LEDC_INTR mapping register + */ +typedef union { + struct { + /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ledc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_ledc_intr_map_reg_t; + +/** Type of usb_intr_map register + * USB_INTR mapping register + */ +typedef union { + struct { + /** usb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_usb_intr_map_reg_t; + +/** Type of i2c_ext0_intr_map register + * I2C_EXT0_INTR mapping register + */ +typedef union { + struct { + /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_ext0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_i2c_ext0_intr_map_reg_t; + +/** Type of tg0_t0_intr_map register + * TG0_T0_INTR mapping register + */ +typedef union { + struct { + /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_tg0_t0_intr_map_reg_t; + +/** Type of tg0_t1_intr_map register + * TG0_T1_INTR mapping register + */ +typedef union { + struct { + /** tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_tg0_t1_intr_map_reg_t; + +/** Type of tg0_wdt_intr_map register + * TG0_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_tg0_wdt_intr_map_reg_t; + +/** Type of tg1_t0_intr_map register + * TG1_T0_INTR mapping register + */ +typedef union { + struct { + /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_tg1_t0_intr_map_reg_t; + +/** Type of tg1_t1_intr_map register + * TG1_T1_INTR mapping register + */ +typedef union { + struct { + /** tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_tg1_t1_intr_map_reg_t; + +/** Type of tg1_wdt_intr_map register + * TG1_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_tg1_wdt_intr_map_reg_t; + +/** Type of systimer_target0_intr_map register + * SYSTIMER_TARGET0_INTR mapping register + */ +typedef union { + struct { + /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_systimer_target0_intr_map_reg_t; + +/** Type of systimer_target1_intr_map register + * SYSTIMER_TARGET1_INTR mapping register + */ +typedef union { + struct { + /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_systimer_target1_intr_map_reg_t; + +/** Type of systimer_target2_intr_map register + * SYSTIMER_TARGET2_INTR mapping register + */ +typedef union { + struct { + /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_systimer_target2_intr_map_reg_t; + +/** Type of apb_adc_intr_map register + * APB_ADC_INTR mapping register + */ +typedef union { + struct { + /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t apb_adc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_apb_adc_intr_map_reg_t; + +/** Type of dma_in_ch0_intr_map register + * DMA_IN_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_dma_in_ch0_intr_map_reg_t; + +/** Type of dma_in_ch1_intr_map register + * DMA_IN_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_dma_in_ch1_intr_map_reg_t; + +/** Type of dma_out_ch0_intr_map register + * DMA_OUT_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_dma_out_ch0_intr_map_reg_t; + +/** Type of dma_out_ch1_intr_map register + * DMA_OUT_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_dma_out_ch1_intr_map_reg_t; + +/** Type of gpspi2_intr_map register + * GPSPI2_INTR mapping register + */ +typedef union { + struct { + /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpspi2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_gpspi2_intr_map_reg_t; + +/** Type of sha_intr_map register + * SHA_INTR mapping register + */ +typedef union { + struct { + /** sha_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t sha_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_sha_intr_map_reg_t; + +/** Type of ecc_intr_map register + * ECC_INTR mapping register + */ +typedef union { + struct { + /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_ecc_intr_map_reg_t; + +/** Type of ecdsa_intr_map register + * ECDSA_INTR mapping register + */ +typedef union { + struct { + /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecdsa_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_matrix_ecdsa_intr_map_reg_t; + +/** Type of int_status_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} interrupt_matrix_int_status_0_reg_t; + +/** Type of int_status_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} interrupt_matrix_int_status_1_reg_t; + +/** Type of clock_gate register + * Interrupt clock gating configure register + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_matrix_clock_gate_reg_t; + + +/** Group: Version Register */ +/** Type of interrupt_date register + * Version control register + */ +typedef union { + struct { + /** interrupt_date : R/W; bitpos: [27:0]; default: 36774400; + * Version control register + */ + uint32_t interrupt_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_matrix_interrupt_date_reg_t; + + +typedef struct { + volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map; + volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; + volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; + volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map; + volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map; + volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map; + volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map; + volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map; + volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map; + volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map; + volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map; + volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map; + volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map; + volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map; + volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map; + volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; + volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map; + volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; + volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; + volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; + volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; + volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; + volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; + volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map; + volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map; + volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map; + volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; + volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; + volatile interrupt_matrix_gpio_interrupt_ext_map_reg_t gpio_interrupt_ext_map; + volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map; + volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; + volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; + volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; + volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; + volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; + volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; + volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map; + volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map; + volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map; + volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map; + volatile interrupt_matrix_uart2_intr_map_reg_t uart2_intr_map; + volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map; + volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map; + volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; + volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map; + volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map; + volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; + volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map; + volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map; + volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; + volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map; + volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map; + volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map; + volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map; + volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; + volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; + volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; + volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; + volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map; + volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map; + volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map; + volatile interrupt_matrix_ecdsa_intr_map_reg_t ecdsa_intr_map; + volatile interrupt_matrix_int_status_0_reg_t int_status_0; + volatile interrupt_matrix_int_status_1_reg_t int_status_1; + volatile interrupt_matrix_clock_gate_reg_t clock_gate; + uint32_t reserved_104[446]; + volatile interrupt_matrix_interrupt_date_reg_t interrupt_date; +} interrupt_matrix_dev_t; + +extern interrupt_matrix_dev_t INTMTX; + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/interrupts.h b/components/soc/esp32c61/include/soc/interrupts.h new file mode 100644 index 0000000000..05ad352b2d --- /dev/null +++ b/components/soc/esp32c61/include/soc/interrupts.h @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE, + ETS_WIFI_MAC_NMI_SOURCE, + ETS_WIFI_PWR_INTR_SOURCE, + ETS_WIFI_BB_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_SOURCE, + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MST_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, + ETS_ASSIST_DEBUG_INTR_SOURCE, + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, + ETS_GPIO_INTERRUPT_EXT_SOURCE, + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_UART2_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_USB_INTR_SOURCE, + ETS_I2C_EXT0_INTR_SOURCE, + ETS_TG0_T0_INTR_SOURCE, + ETS_TG0_T1_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, + ETS_TG1_T0_INTR_SOURCE, + ETS_TG1_T1_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_APB_ADC_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, + ETS_DMA_IN_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_GPSPI2_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/intpri_reg.h b/components/soc/esp32c61/include/soc/intpri_reg.h new file mode 100644 index 0000000000..2626322922 --- /dev/null +++ b/components/soc/esp32c61/include/soc/intpri_reg.h @@ -0,0 +1,131 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTPRI_CPU_INTR_FROM_CPU_0_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90) +/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * CPU_INTR_FROM_CPU_0 mapping register. + */ +#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S) +#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_0_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_1_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94) +/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * CPU_INTR_FROM_CPU_1 mapping register. + */ +#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S) +#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_1_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_2_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98) +/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * CPU_INTR_FROM_CPU_2 mapping register. + */ +#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S) +#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_2_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_3_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c) +/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * CPU_INTR_FROM_CPU_3 mapping register. + */ +#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S) +#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_3_S 0 + +/** INTPRI_DATE_REG register + * Version control register + */ +#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0) +/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784; + * Version control register. + */ +#define INTPRI_DATE 0x0FFFFFFFU +#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S) +#define INTPRI_DATE_V 0x0FFFFFFFU +#define INTPRI_DATE_S 0 + +/** INTPRI_CLOCK_GATE_REG register + * register description + */ +#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4) +/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTPRI_CLK_EN (BIT(0)) +#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S) +#define INTPRI_CLK_EN_V 0x00000001U +#define INTPRI_CLK_EN_S 0 + +/** INTPRI_RND_ECO_REG register + * redcy eco register. + */ +#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac) +/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_ENA (BIT(0)) +#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S) +#define INTPRI_REDCY_ENA_V 0x00000001U +#define INTPRI_REDCY_ENA_S 0 +/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_RESULT (BIT(1)) +#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S) +#define INTPRI_REDCY_RESULT_V 0x00000001U +#define INTPRI_REDCY_RESULT_S 1 + +/** INTPRI_RND_ECO_LOW_REG register + * redcy eco low register. + */ +#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0) +/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_LOW 0xFFFFFFFFU +#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S) +#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU +#define INTPRI_REDCY_LOW_S 0 + +/** INTPRI_RND_ECO_HIGH_REG register + * redcy eco high register. + */ +#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc) +/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_HIGH 0xFFFFFFFFU +#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S) +#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU +#define INTPRI_REDCY_HIGH_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/intpri_struct.h b/components/soc/esp32c61/include/soc/intpri_struct.h new file mode 100644 index 0000000000..338fb09a38 --- /dev/null +++ b/components/soc/esp32c61/include/soc/intpri_struct.h @@ -0,0 +1,127 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of cpu_intr_from_cpu_n register + * CPU_INTR_FROM_CPU_0 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_n : R/W; bitpos: [0]; default: 0; + * CPU_INTR_FROM_CPU_n mapping register. + */ + uint32_t cpu_intr_from_cpu_n:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_n_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36712784; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} intpri_date_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_clock_gate_reg_t; + + +/** Group: Redcy ECO Registers */ +/** Type of rnd_eco register + * redcy eco register. + */ +typedef union { + struct { + /** redcy_ena : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_ena:1; + /** redcy_result : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} intpri_rnd_eco_reg_t; + +/** Type of rnd_eco_low register + * redcy eco low register. + */ +typedef union { + struct { + /** redcy_low : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_low:32; + }; + uint32_t val; +} intpri_rnd_eco_low_reg_t; + +/** Type of rnd_eco_high register + * redcy eco high register. + */ +typedef union { + struct { + /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ + uint32_t redcy_high:32; + }; + uint32_t val; +} intpri_rnd_eco_high_reg_t; + + +typedef struct { + uint32_t reserved_000[36]; + volatile intpri_cpu_intr_from_cpu_n_reg_t cpu_intr_from_cpu_n[4]; + volatile intpri_date_reg_t date; + volatile intpri_clock_gate_reg_t clock_gate; + uint32_t reserved_0a8; + volatile intpri_rnd_eco_reg_t rnd_eco; + volatile intpri_rnd_eco_low_reg_t rnd_eco_low; + uint32_t reserved_0b4[210]; + volatile intpri_rnd_eco_high_reg_t rnd_eco_high; +} intpri_dev_t; + +extern intpri_dev_t INTPRI_REG; + +#ifndef __cplusplus +_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/include/soc/io_mux_reg.h new file mode 100644 index 0000000000..9adf6ef7c8 --- /dev/null +++ b/components/soc/esp32c61/include/soc/io_mux_reg.h @@ -0,0 +1,275 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2 +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTMS +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTDI +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTCK +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_MTDO +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7 +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8 +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9 +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0RXD +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0TXD +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12 +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SPICS1 +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SPICS0 +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SPIQ +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SPIWP +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22 +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23 +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24 + +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U0RXD_GPIO_NUM 10 +#define U0TXD_GPIO_NUM 11 + +#define SPI_HD_GPIO_NUM 19 +#define SPI_WP_GPIO_NUM 17 +#define SPI_CS0_GPIO_NUM 15 +#define SPI_CLK_GPIO_NUM 20 +#define SPI_D_GPIO_NUM 21 +#define SPI_Q_GPIO_NUM 16 + +#define MAX_RTC_GPIO_NUM 7 +#define MAX_PAD_GPIO_NUM 30 +#define MAX_GPIO_NUM 34 +#define HIGH_IO_HOLD_BIT_SHIFT 32 + + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 IO_MUX_CLK_OUT3 +#define CLK_OUT3_V IO_MUX_CLK_OUT3_V +#define CLK_OUT3_S IO_MUX_CLK_OUT3_S +#define CLK_OUT3_M IO_MUX_CLK_OUT3_M +#define CLK_OUT2 IO_MUX_CLK_OUT2 +#define CLK_OUT2_V IO_MUX_CLK_OUT2_V +#define CLK_OUT2_S IO_MUX_CLK_OUT2_S +#define CLK_OUT2_M IO_MUX_CLK_OUT2_M +#define CLK_OUT1 IO_MUX_CLK_OUT1 +#define CLK_OUT1_V IO_MUX_CLK_OUT1_V +#define CLK_OUT1_S IO_MUX_CLK_OUT1_S +#define CLK_OUT1_M IO_MUX_CLK_OUT1_M +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0) +#define FUNC_XTAL_32K_P_GPIO0 1 +#define FUNC_XTAL_32K_P_GPIO0_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4) +#define FUNC_XTAL_32K_N_GPIO1 1 +#define FUNC_XTAL_32K_N_GPIO1_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8) +#define FUNC_GPIO2_FSPIQ 2 +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC) +#define FUNC_MTMS_FSPIHD 2 +#define FUNC_MTMS_GPIO3 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10) +#define FUNC_MTDI_FSPIWP 2 +#define FUNC_MTDI_GPIO4 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14) +#define FUNC_MTCK_GPIO5 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18) +#define FUNC_MTDO_FSPICLK 2 +#define FUNC_MTDO_GPIO6 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C) +#define FUNC_GPIO7_FSPID 2 +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO8_FSPICS0 2 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x28) +#define FUNC_U0RXD_GPIO10 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C) +#define FUNC_U0TXD_GPIO11 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x38) +#define FUNC_SPICS1_GPIO14 1 +#define FUNC_SPICS1_SPICS1 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x3C) +#define FUNC_SPICS0_GPIO15 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x40) +#define FUNC_SPIQ_GPIO16 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x44) +#define FUNC_SPIWP_GPIO17 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x48) +#define FUNC_VDD_SPI_GPIO18 1 +#define FUNC_VDD_SPI_GPIO18_0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x4C) +#define FUNC_SPIHD_GPIO19 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x50) +#define FUNC_SPICLK_GPIO20 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x54) +#define FUNC_SPID_GPIO21 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58) +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C) +#define FUNC_GPIO23_GPIO23 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60) +#define FUNC_GPIO24_GPIO24 1 +#define FUNC_GPIO24_GPIO24_0 0 + +/** IO_MUX_DATE_REG register + * Version control register + */ +#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x1fc) +/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36774288; + * Version control register + */ +#define IO_MUX_REG_DATE 0x0FFFFFFFU +#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) +#define IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define IO_MUX_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/io_mux_struct.h b/components/soc/esp32c61/include/soc/io_mux_struct.h new file mode 100644 index 0000000000..66268878fa --- /dev/null +++ b/components/soc/esp32c61/include/soc/io_mux_struct.h @@ -0,0 +1,145 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of gpion register + * IO MUX configuration register for GPIOn + */ +typedef union { + struct { + /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of GPIOn in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_oe:1; + /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for GPIOn.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ + uint32_t gpion_slp_sel:1; + /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_wpd:1; + /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. \\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_wpu:1; + /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of GPIOn during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_ie:1; + /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of GPIOn during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ + uint32_t gpion_mcu_drv:2; + /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of GPIOn.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_fun_wpd:1; + /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of GPIOn.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_fun_wpu:1; + /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of GPIOn.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_fun_ie:1; + /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of GPIOn. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ + uint32_t gpion_fun_drv:2; + /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * Configures to select IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ + uint32_t gpion_mcu_sel:3; + /** gpion_filter_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_filter_en:1; + /** gpion_hys_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * IO_MUX_GPIOn_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_hys_en:1; + /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for GPIOn. \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN\\ + */ + uint32_t gpion_hys_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} io_mux_gpion_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 36774288; + * Version control register + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} io_mux_date_reg_t; + + +typedef struct { + volatile io_mux_gpion_reg_t gpion[25]; + uint32_t reserved_064[102]; + volatile io_mux_date_reg_t date; +} io_mux_dev_t; + +extern io_mux_dev_t IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/ledc_reg.h b/components/soc/esp32c61/include/soc/ledc_reg.h new file mode 100644 index 0000000000..ebc116fdeb --- /dev/null +++ b/components/soc/esp32c61/include/soc/ledc_reg.h @@ -0,0 +1,2370 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 0.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 0 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_OVF_CNT_EN_CH0 fields and duty cycle + * range configuration for channel 0, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt + * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 0. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 0. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 1.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 1 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_OVF_CNT_EN_CH1 fields and duty cycle + * range configuration for channel 1, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt + * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 1. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 1. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 2.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 2 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_OVF_CNT_EN_CH2 fields and duty cycle + * range configuration for channel 2, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt + * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 2. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 2. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 3.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 3 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_OVF_CNT_EN_CH3 fields and duty cycle + * range configuration for channel 3, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt + * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 3. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 3. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 4.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 4 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_OVF_CNT_EN_CH4 fields and duty cycle + * range configuration for channel 4, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt + * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 4. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 4. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 5.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 5 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_OVF_CNT_EN_CH5 fields and duty cycle + * range configuration for channel 5, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt + * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 5. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 5. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration register + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the bit width of the counter in timer 0. Valid values are 1 to 20. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 0.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 0. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 0 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER0 (BIT(25)) +#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) +#define LEDC_TICK_SEL_TIMER0_V 0x00000001U +#define LEDC_TICK_SEL_TIMER0_S 25 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and + * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value register + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration register + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the bit width of the counter in timer 1. Valid values are 1 to 20. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 1.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 1. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 1 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER1 (BIT(25)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001U +#define LEDC_TICK_SEL_TIMER1_S 25 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and + * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value register + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration register + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the bit width of the counter in timer 2. Valid values are 1 to 20. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 2.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 2. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 2 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER2 (BIT(25)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001U +#define LEDC_TICK_SEL_TIMER2_S 25 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and + * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value register + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration register + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the bit width of the counter in timer 3. Valid values are 1 to 20. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 3.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 3. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 3 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER3 (BIT(25)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001U +#define LEDC_TICK_SEL_TIMER3_S 25 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and + * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value register + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Interrupt raw status register + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/** LEDC_INT_ST_REG register + * Interrupt masked status register + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/** LEDC_INT_ENA_REG register + * Interrupt enable register + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/** LEDC_INT_CLR_REG register + * Interrupt clear register + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch0. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch1. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch2. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch3. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch4. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch5. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH0 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH1 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH2 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH3 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH4 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH5 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH0 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH1 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH2 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH3 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH4 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH5 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER0 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER1 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER2 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER3 event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH1 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH2 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH3 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH4 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH5 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_CAP task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_CAP task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_CAP task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_CAP task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH0 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH1 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH2 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH3 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH4 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH5 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH0 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH1 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH2 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH3 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH4 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH5 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_RST task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_RST task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_RST task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_RST task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_PAUSE and LEDC_TASK_TIMER0 + * _RESUME task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_PAUSE and LEDC_TASK_TIMER1 + * _RESUME task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_PAUSE and LEDC_TASK_TIMER2 + * _RESUME task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_PAUSE and LEDC_TASK_TIMER3 + * _RESUME task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH0 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH1 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH2 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH3 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH4 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH5 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH0 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH1 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH2 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH3 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH4 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH5 task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH0 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH1 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH2 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH3 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH4 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH5 task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer0. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer1. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer2. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer3. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 captured count value register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 captured count value register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 captured count value register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 captured count value register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * LEDC global configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 36770336; + * Configures the version. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/ledc_struct.h b/components/soc/esp32c61/include/soc/ledc_struct.h new file mode 100644 index 0000000000..fac6a69b3a --- /dev/null +++ b/components/soc/esp32c61/include/soc/ledc_struct.h @@ -0,0 +1,1063 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel n selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ + uint32_t timer_sel_chn:2; + /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel n.\\0: Signal output + * disable\\1: Signal output enable + */ + uint32_t sig_out_en_chn:1; + /** idle_lv_chn : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel n is inactive. Valid only when + * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + */ + uint32_t idle_lv_chn:1; + /** para_up_chn : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_OVF_CNT_EN_CHn fields and duty cycle + * range configuration for channel n, and will be automatically cleared by + * hardware.\\0: Invalid. No effect\\1: Update + */ + uint32_t para_up_chn:1; + /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt + * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num_chn:10; + /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + */ + uint32_t ovf_cnt_en_chn:1; + /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ + uint32_t ovf_cnt_reset_chn:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel n. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ + uint32_t hpoint_chn:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + +/** Type of chn_duty register + * Initial duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel n. + */ + uint32_t duty_chn:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ + uint32_t duty_start_chn:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of timern_conf register + * Timer n configuration register + */ +typedef union { + struct { + /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; + * Configures the bit width of the counter in timer n. Valid values are 1 to 20. + */ + uint32_t timern_duty_res:5; + /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer n.The least significant eight bits + * represent the fractional part. + */ + uint32_t clk_div_timern:18; + /** timern_pause : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + */ + uint32_t timern_pause:1; + /** timern_rst : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer n. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ + uint32_t timern_rst:1; + /** tick_sel_timern : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer n selected. Unused. + */ + uint32_t tick_sel_timern:1; + /** timern_para_up : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and + * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ + uint32_t timern_para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timern_conf_reg_t; + +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t chn_gamma_entry_num:5; + /** chn_gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Pause + */ + uint32_t chn_gamma_pause:1; + /** chn_gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Resume + */ + uint32_t chn_gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH0 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH1 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH2 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH3 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH4 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the LEDC_EVT_DUTY_CHNG_END_CH5 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + uint32_t reserved_6:2; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH0 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH1 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH2 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH3 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH4 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the LEDC_EVT_OVF_CNT_PLS_CH5 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + uint32_t reserved_14:2; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER0 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER1 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER2 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIME_OVF_TIMER3 event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH1 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH2 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH3 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH4 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH5 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_RES_UPDATE task.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_CAP task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_CAP task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_CAP task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_CAP task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH0 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH1 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH2 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH3 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH4 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable LEDC_TASK_SIG_OUT_DIS_CH5 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + uint32_t reserved_14:2; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH0 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH1 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH2 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH3 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH4 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable LEDC_TASK_OVF_CNT_RST_CH5 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + uint32_t reserved_22:2; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_RST task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_RST task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_RST task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_RST task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER0_PAUSE and LEDC_TASK_TIMER0 + * _RESUME task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER1_PAUSE and LEDC_TASK_TIMER1 + * _RESUME task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER2_PAUSE and LEDC_TASK_TIMER2 + * _RESUME task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable LEDC_TASK_TIMER3_PAUSE and LEDC_TASK_TIMER3 + * _RESUME task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH0 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH1 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH2 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH3 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH4 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESTART_CH5 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + uint32_t reserved_6:2; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH0 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH1 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH2 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH3 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH4 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_PAUSE_CH5 task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + uint32_t reserved_14:2; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH0 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH1 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH2 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH3 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH4 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable LEDC_TASK_GAMMA_RESUME_CH5 task.\\0: + * Disable\\1: Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timern_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timern_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + uint32_t reserved_8:23; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Status Register */ +/** Type of chn_duty_r register + * Current duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn_r : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel n. + */ + uint32_t duty_chn_r:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + +/** Type of timern_value register + * Timer n current counter value register + */ +typedef union { + struct { + /** timern_cnt : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer n. + */ + uint32_t timern_cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_value_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timern_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 36770336; + * Configures the version. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + +typedef struct { + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_rd; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_timern_conf_reg_t conf; + volatile ledc_timern_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[6]; + uint32_t reserved_078[10]; + volatile ledc_timerx_reg_t timer[4]; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[6]; + uint32_t reserved_118[2]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_12c[5]; + volatile ledc_timern_cmp_reg_t timern_cmp[4]; + volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; + uint32_t reserved_160[4]; + volatile ledc_conf_reg_t conf; + volatile ledc_date_reg_t date; +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/mem_monitor_reg.h b/components/soc/esp32c61/include/soc/mem_monitor_reg.h new file mode 100644 index 0000000000..71a6e1890a --- /dev/null +++ b/components/soc/esp32c61/include/soc/mem_monitor_reg.h @@ -0,0 +1,345 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MEM_MONITOR_LOG_SETTING_REG register + * Bus access logging configuration register + */ +#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) +/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0; + * Configures monitoring modes.bit[0]: Configures write monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + * bit[1]: Configures word monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + * bit[2]: Configures halfword monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + * bit[3]: Configures byte monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + */ +#define MEM_MONITOR_LOG_MODE 0x0000000FU +#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) +#define MEM_MONITOR_LOG_MODE_V 0x0000000FU +#define MEM_MONITOR_LOG_MODE_S 0 +/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1; + * Configures the writing mode for recorded data.1: Loop mode\\ + * 0: Non-loop mode\\ + */ +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4)) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4 +/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0; + * Configures whether to enable CPU bus access logging.bit[0]: Configures whether to + * enable HP CPU bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ +#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU +#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S) +#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_CORE_ENA_S 8 +/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0; + * Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether + * to enable DMA_0 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ +#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S) +#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_0_ENA_S 16 +/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0; + * Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether + * to enable DMA_1 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ +#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S) +#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_1_ENA_S 24 + +/** MEM_MONITOR_LOG_SETTING1_REG register + * Bus access logging configuration register + */ +#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4) +/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0; + * Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether + * to enable DMA_2 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ +#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S) +#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_2_ENA_S 0 +/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0; + * Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether + * to enable DMA_3 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ +#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S) +#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_3_ENA_S 8 + +/** MEM_MONITOR_LOG_CHECK_DATA_REG register + * Configures monitored data in Bus access logging + */ +#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8) +/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; + * Configures the data to be monitored during bus accessing. + */ +#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S) +#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_S 0 + +/** MEM_MONITOR_LOG_DATA_MASK_REG register + * Configures masked data in Bus access logging + */ +#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc) +/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; + * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]: + * Configures whether to mask the least significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG.\\ + * 0: Not mask \\ + * 1: Mask\\ + * bit[1]: Configures whether to mask the second least significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ + * 0: Not mask \\ + * 1: Mask\\ + * bit[2]: Configures whether to mask the second most significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ + * 0: Not mask \\ + * 1: Mask\\ + * bit[3]: Configures whether to mask the most significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ + * 0: Not mask \\ + * 1: Mask\\ + */ +#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) +#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_S 0 + +/** MEM_MONITOR_LOG_MIN_REG register + * Configures monitored address space in Bus access logging + */ +#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10) +/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; + * Configures the lower bound address of the monitored address space. + */ +#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S) +#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_S 0 + +/** MEM_MONITOR_LOG_MAX_REG register + * Configures monitored address space in Bus access logging + */ +#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14) +/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of the monitored address space. + */ +#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S) +#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_S 0 + +/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG register + * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + */ +#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_MONITOR_BASE + 0x18) +/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the HP CPU bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ +#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S) +#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0 +/** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0; + * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\ + * 0: Not update\\ + */ +#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31)) +#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S) +#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S 31 + +/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG register + * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + */ +#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) +/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_0 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ +#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S) +#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S 0 +/** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_1 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ +#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S) +#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S 8 +/** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_2 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ +#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S) +#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S 16 +/** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_3 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ +#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S) +#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V 0x000000FFU +#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S 24 + +/** MEM_MONITOR_LOG_MEM_START_REG register + * Configures the starting address of the storage memory for recorded data + */ +#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x20) +/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; + * Configures the starting address of the storage space for recorded data. + */ +#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S) +#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_S 0 + +/** MEM_MONITOR_LOG_MEM_END_REG register + * Configures the end address of the storage memory for recorded data + */ +#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x24) +/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; + * Configures the ending address of the storage space for recorded data. + */ +#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S) +#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_S 0 + +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register + * Represents the address for the next write + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x28) +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next write. + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S) +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 + +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register + * Updates the address for the next write with the starting address for the recorded + * data + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c) +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\ + * 0: Not update (default) \\ + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 + +/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register + * Logging overflow status register + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30) +/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; + * Represents whether data overflows the storage space.0: Not Overflow\\ + * 1: Overflow\\ + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 +/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; + * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not + * clear\\ + * 1: Clear\\ + */ +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 + +/** MEM_MONITOR_CLOCK_GATE_REG register + * Register clock control + */ +#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34) +/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable the register clock gating.0: Disable\\ + * 1: Enable\\ + */ +#define MEM_MONITOR_CLK_EN (BIT(0)) +#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) +#define MEM_MONITOR_CLK_EN_V 0x00000001U +#define MEM_MONITOR_CLK_EN_S 0 + +/** MEM_MONITOR_DATE_REG register + * Version control register + */ +#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc) +/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36733248; + * Version control register. + */ +#define MEM_MONITOR_DATE 0x0FFFFFFFU +#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S) +#define MEM_MONITOR_DATE_V 0x0FFFFFFFU +#define MEM_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/mem_monitor_struct.h b/components/soc/esp32c61/include/soc/mem_monitor_struct.h new file mode 100644 index 0000000000..5b810b2b67 --- /dev/null +++ b/components/soc/esp32c61/include/soc/mem_monitor_struct.h @@ -0,0 +1,368 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of log_setting register + * Bus access logging configuration register + */ +typedef union { + struct { + /** log_mode : R/W; bitpos: [3:0]; default: 0; + * Configures monitoring modes.bit[0]: Configures write monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + * bit[1]: Configures word monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + * bit[2]: Configures halfword monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + * bit[3]: Configures byte monitoring. \\ + * 0: Disable \\ + * 1: Enable\\ + */ + uint32_t log_mode:4; + /** log_mem_loop_enable : R/W; bitpos: [4]; default: 1; + * Configures the writing mode for recorded data.1: Loop mode\\ + * 0: Non-loop mode\\ + */ + uint32_t log_mem_loop_enable:1; + uint32_t reserved_5:3; + /** log_core_ena : R/W; bitpos: [15:8]; default: 0; + * Configures whether to enable CPU bus access logging.bit[0]: Configures whether to + * enable HP CPU bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ + uint32_t log_core_ena:8; + /** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0; + * Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether + * to enable DMA_0 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ + uint32_t log_dma_0_ena:8; + /** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0; + * Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether + * to enable DMA_1 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ + uint32_t log_dma_1_ena:8; + }; + uint32_t val; +} mem_monitor_log_setting_reg_t; + +/** Type of log_setting1 register + * Bus access logging configuration register + */ +typedef union { + struct { + /** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0; + * Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether + * to enable DMA_2 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ + uint32_t log_dma_2_ena:8; + /** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0; + * Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether + * to enable DMA_3 bus access logging. \\ + * 0: Disable \\ + * 1: Enable\\ + * Bit[7:1]: Reserved + */ + uint32_t log_dma_3_ena:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} mem_monitor_log_setting1_reg_t; + +/** Type of log_check_data register + * Configures monitored data in Bus access logging + */ +typedef union { + struct { + /** log_check_data : R/W; bitpos: [31:0]; default: 0; + * Configures the data to be monitored during bus accessing. + */ + uint32_t log_check_data:32; + }; + uint32_t val; +} mem_monitor_log_check_data_reg_t; + +/** Type of log_data_mask register + * Configures masked data in Bus access logging + */ +typedef union { + struct { + /** log_data_mask : R/W; bitpos: [3:0]; default: 0; + * Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]: + * Configures whether to mask the least significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG.\\ + * 0: Not mask \\ + * 1: Mask\\ + * bit[1]: Configures whether to mask the second least significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ + * 0: Not mask \\ + * 1: Mask\\ + * bit[2]: Configures whether to mask the second most significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ + * 0: Not mask \\ + * 1: Mask\\ + * bit[3]: Configures whether to mask the most significant byte of + * MEM_MONITOR_LOG_CHECK_DATA_REG. \\ + * 0: Not mask \\ + * 1: Mask\\ + */ + uint32_t log_data_mask:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} mem_monitor_log_data_mask_reg_t; + +/** Type of log_min register + * Configures monitored address space in Bus access logging + */ +typedef union { + struct { + /** log_min : R/W; bitpos: [31:0]; default: 0; + * Configures the lower bound address of the monitored address space. + */ + uint32_t log_min:32; + }; + uint32_t val; +} mem_monitor_log_min_reg_t; + +/** Type of log_max register + * Configures monitored address space in Bus access logging + */ +typedef union { + struct { + /** log_max : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of the monitored address space. + */ + uint32_t log_max:32; + }; + uint32_t val; +} mem_monitor_log_max_reg_t; + +/** Type of log_mon_addr_update_0 register + * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + */ +typedef union { + struct { + /** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the HP CPU bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ + uint32_t log_mon_addr_core_update:8; + uint32_t reserved_8:23; + /** log_mon_addr_all_update : WT; bitpos: [31]; default: 0; + * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\ + * 0: Not update\\ + */ + uint32_t log_mon_addr_all_update:1; + }; + uint32_t val; +} mem_monitor_log_mon_addr_update_0_reg_t; + +/** Type of log_mon_addr_update_1 register + * Configures the address space of from MEM_MONITOR_LOG_MIN_REG to + * MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master. + */ +typedef union { + struct { + /** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_0 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ + uint32_t log_mon_addr_dma_0_update:8; + /** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_1 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ + uint32_t log_mon_addr_dma_1_update:8; + /** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_2 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ + uint32_t log_mon_addr_dma_2_update:8; + /** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0; + * Configures the monitored address space of the certain master. Bit[0]: Configures + * the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the + * monitored address space of the DMA_3 bus.1: Update\\ + * 0: Not update\\ + * Bit[7:1]: Reserved\\ + */ + uint32_t log_mon_addr_dma_3_update:8; + }; + uint32_t val; +} mem_monitor_log_mon_addr_update_1_reg_t; + +/** Type of log_mem_start register + * Configures the starting address of the storage memory for recorded data + */ +typedef union { + struct { + /** log_mem_start : R/W; bitpos: [31:0]; default: 0; + * Configures the starting address of the storage space for recorded data. + */ + uint32_t log_mem_start:32; + }; + uint32_t val; +} mem_monitor_log_mem_start_reg_t; + +/** Type of log_mem_end register + * Configures the end address of the storage memory for recorded data + */ +typedef union { + struct { + /** log_mem_end : R/W; bitpos: [31:0]; default: 0; + * Configures the ending address of the storage space for recorded data. + */ + uint32_t log_mem_end:32; + }; + uint32_t val; +} mem_monitor_log_mem_end_reg_t; + +/** Type of log_mem_current_addr register + * Represents the address for the next write + */ +typedef union { + struct { + /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next write. + */ + uint32_t log_mem_current_addr:32; + }; + uint32_t val; +} mem_monitor_log_mem_current_addr_reg_t; + +/** Type of log_mem_addr_update register + * Updates the address for the next write with the starting address for the recorded + * data + */ +typedef union { + struct { + /** log_mem_addr_update : WT; bitpos: [0]; default: 0; + * Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\ + * 0: Not update (default) \\ + */ + uint32_t log_mem_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_log_mem_addr_update_reg_t; + +/** Type of log_mem_full_flag register + * Logging overflow status register + */ +typedef union { + struct { + /** log_mem_full_flag : RO; bitpos: [0]; default: 0; + * Represents whether data overflows the storage space.0: Not Overflow\\ + * 1: Overflow\\ + */ + uint32_t log_mem_full_flag:1; + /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; + * Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not + * clear\\ + * 1: Clear\\ + */ + uint32_t clr_log_mem_full_flag:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mem_monitor_log_mem_full_flag_reg_t; + + +/** Group: clk register */ +/** Type of clock_gate register + * Register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether to enable the register clock gating.0: Disable\\ + * 1: Enable\\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_clock_gate_reg_t; + + +/** Group: version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36733248; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mem_monitor_date_reg_t; + + +typedef struct { + volatile mem_monitor_log_setting_reg_t log_setting; + volatile mem_monitor_log_setting1_reg_t log_setting1; + volatile mem_monitor_log_check_data_reg_t log_check_data; + volatile mem_monitor_log_data_mask_reg_t log_data_mask; + volatile mem_monitor_log_min_reg_t log_min; + volatile mem_monitor_log_max_reg_t log_max; + volatile mem_monitor_log_mon_addr_update_0_reg_t log_mon_addr_update_0; + volatile mem_monitor_log_mon_addr_update_1_reg_t log_mon_addr_update_1; + volatile mem_monitor_log_mem_start_reg_t log_mem_start; + volatile mem_monitor_log_mem_end_reg_t log_mem_end; + volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr; + volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update; + volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag; + volatile mem_monitor_clock_gate_reg_t clock_gate; + uint32_t reserved_038[241]; + volatile mem_monitor_date_reg_t date; +} mem_monitor_dev_t; + +extern mem_monitor_dev_t TCM_MEM_MONITOR; + +#ifndef __cplusplus +_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pcr_reg.h b/components/soc/esp32c61/include/soc/pcr_reg.h new file mode 100644 index 0000000000..f7539adeba --- /dev/null +++ b/components/soc/esp32c61/include/soc/pcr_reg.h @@ -0,0 +1,2245 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART0.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART1.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart1 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_UART2_CONF_REG register + * UART2 configuration register + */ +#define PCR_UART2_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_UART2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart2 apb clock + */ +#define PCR_UART2_CLK_EN (BIT(0)) +#define PCR_UART2_CLK_EN_M (PCR_UART2_CLK_EN_V << PCR_UART2_CLK_EN_S) +#define PCR_UART2_CLK_EN_V 0x00000001U +#define PCR_UART2_CLK_EN_S 0 +/** PCR_UART2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart2 module + */ +#define PCR_UART2_RST_EN (BIT(1)) +#define PCR_UART2_RST_EN_M (PCR_UART2_RST_EN_V << PCR_UART2_RST_EN_S) +#define PCR_UART2_RST_EN_V 0x00000001U +#define PCR_UART2_RST_EN_S 1 +/** PCR_UART2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart2 module + */ +#define PCR_UART2_READY (BIT(2)) +#define PCR_UART2_READY_M (PCR_UART2_READY_V << PCR_UART2_READY_S) +#define PCR_UART2_READY_V 0x00000001U +#define PCR_UART2_READY_S 2 + +/** PCR_UART2_SCLK_CONF_REG register + * UART2_SCLK configuration register + */ +#define PCR_UART2_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_UART2_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart2 function clock. + */ +#define PCR_UART2_SCLK_DIV_A 0x0000003FU +#define PCR_UART2_SCLK_DIV_A_M (PCR_UART2_SCLK_DIV_A_V << PCR_UART2_SCLK_DIV_A_S) +#define PCR_UART2_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART2_SCLK_DIV_A_S 0 +/** PCR_UART2_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart2 function clock. + */ +#define PCR_UART2_SCLK_DIV_B 0x0000003FU +#define PCR_UART2_SCLK_DIV_B_M (PCR_UART2_SCLK_DIV_B_V << PCR_UART2_SCLK_DIV_B_S) +#define PCR_UART2_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART2_SCLK_DIV_B_S 6 +/** PCR_UART2_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart2 function clock. + */ +#define PCR_UART2_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART2_SCLK_DIV_NUM_M (PCR_UART2_SCLK_DIV_NUM_V << PCR_UART2_SCLK_DIV_NUM_S) +#define PCR_UART2_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART2_SCLK_DIV_NUM_S 12 +/** PCR_UART2_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART2.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_UART2_SCLK_SEL 0x00000003U +#define PCR_UART2_SCLK_SEL_M (PCR_UART2_SCLK_SEL_V << PCR_UART2_SCLK_SEL_S) +#define PCR_UART2_SCLK_SEL_V 0x00000003U +#define PCR_UART2_SCLK_SEL_S 20 +/** PCR_UART2_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart2 function clock + */ +#define PCR_UART2_SCLK_EN (BIT(22)) +#define PCR_UART2_SCLK_EN_M (PCR_UART2_SCLK_EN_V << PCR_UART2_SCLK_EN_S) +#define PCR_UART2_SCLK_EN_V 0x00000001U +#define PCR_UART2_SCLK_EN_S 22 + +/** PCR_UART2_PD_CTRL_REG register + * UART2 power control register + */ +#define PCR_UART2_PD_CTRL_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_UART2_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART2 memory. + */ +#define PCR_UART2_MEM_FORCE_PU (BIT(1)) +#define PCR_UART2_MEM_FORCE_PU_M (PCR_UART2_MEM_FORCE_PU_V << PCR_UART2_MEM_FORCE_PU_S) +#define PCR_UART2_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART2_MEM_FORCE_PU_S 1 +/** PCR_UART2_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART2 memory. + */ +#define PCR_UART2_MEM_FORCE_PD (BIT(2)) +#define PCR_UART2_MEM_FORCE_PD_M (PCR_UART2_MEM_FORCE_PD_V << PCR_UART2_MEM_FORCE_PD_S) +#define PCR_UART2_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART2_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(3)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 3 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 +/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; + * Configures the clock source for MSPI.\\ + * 0(default): XTAL_CLK\\ + * 1 RC_FAST_CLK\\ + * 2: PLL_F480M_CLK\\ + */ +#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) +#define PCR_MSPI_FUNC_CLK_SEL_V 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_S 8 +/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ +#define PCR_MSPI_FUNC_CLK_EN (BIT(10)) +#define PCR_MSPI_FUNC_CLK_EN_M (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S) +#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U +#define PCR_MSPI_FUNC_CLK_EN_S 10 +/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; + * Set 0 to reset axi_clock domain of mspi module + */ +#define PCR_MSPI_AXI_RST_EN (BIT(11)) +#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) +#define PCR_MSPI_AXI_RST_EN_V 0x00000001U +#define PCR_MSPI_AXI_RST_EN_S 11 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of I2C.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of LEDC.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_LEDC_PD_CTRL_REG register + * LEDC power control register + */ +#define PCR_LEDC_PD_CTRL_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_LEDC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down LEDC memory. + */ +#define PCR_LEDC_MEM_FORCE_PU (BIT(1)) +#define PCR_LEDC_MEM_FORCE_PU_M (PCR_LEDC_MEM_FORCE_PU_V << PCR_LEDC_MEM_FORCE_PU_S) +#define PCR_LEDC_MEM_FORCE_PU_V 0x00000001U +#define PCR_LEDC_MEM_FORCE_PU_S 1 +/** PCR_LEDC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up LEDC memory. + */ +#define PCR_LEDC_MEM_FORCE_PD (BIT(2)) +#define PCR_LEDC_MEM_FORCE_PD_M (PCR_LEDC_MEM_FORCE_PD_V << PCR_LEDC_MEM_FORCE_PD_S) +#define PCR_LEDC_MEM_FORCE_PD_V 0x00000001U +#define PCR_LEDC_MEM_FORCE_PD_S 2 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 0.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 0.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 1.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 1.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of System Timer.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S TX.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F120M_CLK\\ + * 2: PLL_F160M_CLK\\ + * 3: I2S_MCLK_in\\ + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S RX.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F120M_CLK\\ + * 2: PLL_F160M_CLK\\ + * 3: I2S_MCLK_in\\ + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * Configures to select master clock.\\ + * 0 (default): I2S_TX_CLK\\ + * 1: I2S_RX_CLK\\ + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SAR ADC.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of the temperature sensor.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE2_RST_EN : R/W; bitpos: [4]; default: 0; + * Set 1 to reset cpu pvt monitor site + */ +#define PCR_PVT_MONITOR_SITE2_RST_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE2_RST_EN_M (PCR_PVT_MONITOR_SITE2_RST_EN_V << PCR_PVT_MONITOR_SITE2_RST_EN_S) +#define PCR_PVT_MONITOR_SITE2_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_RST_EN_S 4 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(5)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 5 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of PVT MONITER.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F160M_CLK\\ + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ +#define PCR_SPI2_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_M (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S) +#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_S 12 +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SPI2.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F160M_CLK\\ + * 2: RC_FAST_CLK\\ + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of IO MUX.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_TCM_MEM_MONITOR_CONF_REG register + * TCM_MEM_MONITOR configuration register + */ +#define PCR_TCM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_TCM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable tcm_mem_monitor clock + */ +#define PCR_TCM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_TCM_MEM_MONITOR_CLK_EN_M (PCR_TCM_MEM_MONITOR_CLK_EN_V << PCR_TCM_MEM_MONITOR_CLK_EN_S) +#define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) +#define PCR_TCM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_RST_EN_S 1 +/** PCR_TCM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_READY (BIT(2)) +#define PCR_TCM_MEM_MONITOR_READY_M (PCR_TCM_MEM_MONITOR_READY_V << PCR_TCM_MEM_MONITOR_READY_S) +#define PCR_TCM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_READY_S 2 + +/** PCR_PSRAM_MEM_MONITOR_CONF_REG register + * PSRAM_MEM_MONITOR configuration register + */ +#define PCR_PSRAM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_PSRAM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable psram_mem_monitor clock + */ +#define PCR_PSRAM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_M (PCR_PSRAM_MEM_MONITOR_CLK_EN_V << PCR_PSRAM_MEM_MONITOR_CLK_EN_S) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_RST_EN_S 1 +/** PCR_PSRAM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_READY (BIT(2)) +#define PCR_PSRAM_MEM_MONITOR_READY_M (PCR_PSRAM_MEM_MONITOR_READY_V << PCR_PSRAM_MEM_MONITOR_READY_S) +#define PCR_PSRAM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_READY_S 2 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_CACHE_PD_CTRL_REG register + * CACHE power control register + */ +#define PCR_CACHE_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_CACHE_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down CACHE memory. + */ +#define PCR_CACHE_MEM_FORCE_PU (BIT(1)) +#define PCR_CACHE_MEM_FORCE_PU_M (PCR_CACHE_MEM_FORCE_PU_V << PCR_CACHE_MEM_FORCE_PU_S) +#define PCR_CACHE_MEM_FORCE_PU_V 0x00000001U +#define PCR_CACHE_MEM_FORCE_PU_S 1 +/** PCR_CACHE_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up CACHE memory. + */ +#define PCR_CACHE_MEM_FORCE_PD (BIT(2)) +#define PCR_CACHE_MEM_FORCE_PD_M (PCR_CACHE_MEM_FORCE_PD_V << PCR_CACHE_MEM_FORCE_PD_S) +#define PCR_CACHE_MEM_FORCE_PD_V 0x00000001U +#define PCR_CACHE_MEM_FORCE_PD_S 2 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ +#define PCR_MODEM_APB_CLK_EN (BIT(0)) +#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) +#define PCR_MODEM_APB_CLK_EN_V 0x00000001U +#define PCR_MODEM_APB_CLK_EN_S 0 +/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(1)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 1 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field indicates if modem source clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_MODEM_CLK_EN (BIT(2)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures to select the clock source of HP_ROOT_CLK.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F160M_CLK\\ + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 +/** PCR_CPU_DBGMD_CLK_EN : R/W; bitpos: [31]; default: 1; + * This field indicates if cpu debug mode clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_CPU_DBGMD_CLK_EN (BIT(31)) +#define PCR_CPU_DBGMD_CLK_EN_M (PCR_CPU_DBGMD_CLK_EN_V << PCR_CPU_DBGMD_CLK_EN_S) +#define PCR_CPU_DBGMD_CLK_EN_V 0x00000001U +#define PCR_CPU_DBGMD_CLK_EN_S 31 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_CPUPERIOD_SEL 0x00000003U +#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) +#define PCR_CPUPERIOD_SEL_V 0x00000003U +#define PCR_CPUPERIOD_SEL_S 0 +/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_PLL_FREQ_SEL (BIT(2)) +#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) +#define PCR_PLL_FREQ_SEL_V 0x00000001U +#define PCR_PLL_FREQ_SEL_S 2 +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_60M_CLK_EN (BIT(4)) +#define PCR_PLL_60M_CLK_EN_M (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S) +#define PCR_PLL_60M_CLK_EN_V 0x00000001U +#define PCR_PLL_60M_CLK_EN_S 4 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(5)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 5 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(6)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 6 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(7)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 7 +/** PCR_PLL_12M_CLK_EN : HRO; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_12M_CLK_EN (BIT(8)) +#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) +#define PCR_PLL_12M_CLK_EN_V 0x00000001U +#define PCR_PLL_12M_CLK_EN_S 8 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ +#define PCR_CLK_320M_OEN (BIT(6)) +#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) +#define PCR_CLK_320M_OEN_V 0x00000001U +#define PCR_CLK_320M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [9]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(9)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 9 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP.\\ + * 0 (default): RC32K_CLK\\ + * 1: XTAL32K_CLK\\ + * 2: OSC_SLOW_CLK\\ + * 3: RC_SLOW_CLK\\ + * 4: RC_FAST_CLK\\ + */ +#define PCR_32K_SEL 0x00000007U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000007U +#define PCR_32K_SEL_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * When PCR_32K_SEL set as 4, This field PCR_FOSC_TICK_NUM is used to set the divider + * number of fosc. + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [1:0]; default: 3; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000003U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000003U +#define PCR_ROM_FORCE_PU_S 0 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [3:2]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000003U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000003U +#define PCR_ROM_FORCE_PD_S 2 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [5:4]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_S 4 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000001FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000001FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000001FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000001FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [24:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 20 + +/** PCR_SEC_CONF_REG register + * Clock source configuration register for External Memory Encryption and Decryption + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the External Memory Encryption and Decryption + * module.\\ + * 0(default): XTAL_CLK\\ + * 1 RC_FAST_CLK\\ + * 2: PLL_F480M_CLK\\ + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 +/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset sec module + */ +#define PCR_SEC_RST_EN (BIT(2)) +#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) +#define PCR_SEC_RST_EN_V 0x00000001U +#define PCR_SEC_RST_EN_S 2 + +/** PCR_ADC_DAC_INV_PHASE_CONF_REG register + * xxxx + */ +#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0)) +#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S) +#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0 +/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0; + * xxxx + */ +#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1)) +#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S) +#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1 + +/** PCR_BUS_CLK_UPDATE_REG register + * Configuration register for applying updated high-performance system clock sources + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK + * division and HP_ROOT_CLK clock source selection.\\ + * 0: Not update configurations\\ + * 1: Update configurations\\ + * This bit is automatically cleared when configurations have been updated.\\ + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * SAR ADC clock divisor configuration register + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control + * signals.\\ + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control + * signals.\\ + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) +#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 +/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_EN (BIT(8)) +#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) +#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U +#define PCR_PWDET_SAR_CLK_EN_S 8 + +/** PCR_TIMERGROUP_WDT_CONF_REG register + * TIMERGROUP_WDT configuration register + */ +#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_RST_EN (BIT(0)) +#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) +#define PCR_TG0_WDT_RST_EN_V 0x00000001U +#define PCR_TG0_WDT_RST_EN_S 0 +/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_RST_EN (BIT(1)) +#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) +#define PCR_TG1_WDT_RST_EN_V 0x00000001U +#define PCR_TG1_WDT_RST_EN_S 1 + +/** PCR_TIMERGROUP_XTAL_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 xtal clock domain + */ +#define PCR_TG0_XTAL_RST_EN (BIT(0)) +#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) +#define PCR_TG0_XTAL_RST_EN_V 0x00000001U +#define PCR_TG0_XTAL_RST_EN_S 0 +/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 xtal clock domain + */ +#define PCR_TG1_XTAL_RST_EN (BIT(1)) +#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) +#define PCR_TG1_XTAL_RST_EN_V 0x00000001U +#define PCR_TG1_XTAL_RST_EN_S 1 +/** PCR_TG0_XTAL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable tg0 xtal clock + */ +#define PCR_TG0_XTAL_CLK_EN (BIT(2)) +#define PCR_TG0_XTAL_CLK_EN_M (PCR_TG0_XTAL_CLK_EN_V << PCR_TG0_XTAL_CLK_EN_S) +#define PCR_TG0_XTAL_CLK_EN_V 0x00000001U +#define PCR_TG0_XTAL_CLK_EN_S 2 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 37753376; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pcr_struct.h b/components/soc/esp32c61/include/soc/pcr_struct.h new file mode 100644 index 0000000000..78d68658ca --- /dev/null +++ b/components/soc/esp32c61/include/soc/pcr_struct.h @@ -0,0 +1,2052 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of uart0_conf register + * UART0 configuration register + */ +typedef union { + struct { + /** uart0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ + uint32_t uart0_clk_en:1; + /** uart0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ + uint32_t uart0_rst_en:1; + /** uart0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ + uint32_t uart0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_conf_reg_t; + +/** Type of uart0_sclk_conf register + * UART0_SCLK configuration register + */ +typedef union { + struct { + /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_a:6; + /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_b:6; + /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_num:8; + /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART0.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t uart0_sclk_sel:2; + /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart0_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart0_sclk_conf_reg_t; + +/** Type of uart0_pd_ctrl register + * UART0 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ + uint32_t uart0_mem_force_pu:1; + /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ + uint32_t uart0_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_pd_ctrl_reg_t; + +/** Type of uart1_conf register + * UART1 configuration register + */ +typedef union { + struct { + /** uart1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ + uint32_t uart1_clk_en:1; + /** uart1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ + uint32_t uart1_rst_en:1; + /** uart1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ + uint32_t uart1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_conf_reg_t; + +/** Type of uart1_sclk_conf register + * UART1_SCLK configuration register + */ +typedef union { + struct { + /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_a:6; + /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_b:6; + /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_num:8; + /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART1.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t uart1_sclk_sel:2; + /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart1 function clock + */ + uint32_t uart1_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart1_sclk_conf_reg_t; + +/** Type of uart1_pd_ctrl register + * UART1 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ + uint32_t uart1_mem_force_pu:1; + /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ + uint32_t uart1_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_pd_ctrl_reg_t; + +/** Type of uart2_conf register + * UART2 configuration register + */ +typedef union { + struct { + /** uart2_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart2 apb clock + */ + uint32_t uart2_clk_en:1; + /** uart2_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart2 module + */ + uint32_t uart2_rst_en:1; + /** uart2_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart2 module + */ + uint32_t uart2_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart2_conf_reg_t; + +/** Type of uart2_sclk_conf register + * UART2_SCLK configuration register + */ +typedef union { + struct { + /** uart2_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart2 function clock. + */ + uint32_t uart2_sclk_div_a:6; + /** uart2_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart2 function clock. + */ + uint32_t uart2_sclk_div_b:6; + /** uart2_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart2 function clock. + */ + uint32_t uart2_sclk_div_num:8; + /** uart2_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART2.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t uart2_sclk_sel:2; + /** uart2_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart2 function clock + */ + uint32_t uart2_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart2_sclk_conf_reg_t; + +/** Type of uart2_pd_ctrl register + * UART2 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart2_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART2 memory. + */ + uint32_t uart2_mem_force_pu:1; + /** uart2_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART2 memory. + */ + uint32_t uart2_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart2_pd_ctrl_reg_t; + +/** Type of mspi_conf register + * MSPI configuration register + */ +typedef union { + struct { + /** mspi_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ + uint32_t mspi_clk_en:1; + /** mspi_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ + uint32_t mspi_rst_en:1; + /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ + uint32_t mspi_pll_clk_en:1; + /** mspi_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ + uint32_t mspi_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_mspi_conf_reg_t; + +/** Type of mspi_clk_conf register + * MSPI_CLK configuration register + */ +typedef union { + struct { + /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ + uint32_t mspi_fast_div_num:8; + /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; + * Configures the clock source for MSPI.\\ + * 0(default): XTAL_CLK\\ + * 1 RC_FAST_CLK\\ + * 2: PLL_F480M_CLK\\ + */ + uint32_t mspi_func_clk_sel:2; + /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ + uint32_t mspi_func_clk_en:1; + /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; + * Set 0 to reset axi_clock domain of mspi module + */ + uint32_t mspi_axi_rst_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} pcr_mspi_clk_conf_reg_t; + +/** Type of i2c_conf register + * I2C configuration register + */ +typedef union { + struct { + /** i2c_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ + uint32_t i2c_clk_en:1; + /** i2c_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ + uint32_t i2c_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_i2c_conf_reg_t; + +/** Type of i2c_sclk_conf register + * I2C_SCLK configuration register + */ +typedef union { + struct { + /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_a:6; + /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_b:6; + /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_num:8; + /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; + * Configures the clock source of I2C.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + */ + uint32_t i2c_sclk_sel:1; + uint32_t reserved_21:1; + /** i2c_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ + uint32_t i2c_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2c_sclk_conf_reg_t; + +/** Type of ledc_conf register + * LEDC configuration register + */ +typedef union { + struct { + /** ledc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ + uint32_t ledc_clk_en:1; + /** ledc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ + uint32_t ledc_rst_en:1; + /** ledc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ + uint32_t ledc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ledc_conf_reg_t; + +/** Type of ledc_sclk_conf register + * LEDC_SCLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of LEDC.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t ledc_sclk_sel:2; + /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ + uint32_t ledc_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_ledc_sclk_conf_reg_t; + +/** Type of ledc_pd_ctrl register + * LEDC power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** ledc_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down LEDC memory. + */ + uint32_t ledc_mem_force_pu:1; + /** ledc_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up LEDC memory. + */ + uint32_t ledc_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ledc_pd_ctrl_reg_t; + +/** Type of timergroup0_conf register + * TIMERGROUP0 configuration register + */ +typedef union { + struct { + /** tg0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ + uint32_t tg0_clk_en:1; + /** tg0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ + uint32_t tg0_rst_en:1; + /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ + uint32_t tg0_wdt_ready:1; + /** tg0_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ + uint32_t tg0_timer0_ready:1; + /** tg0_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg0_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup0_conf_reg_t; + +/** Type of timergroup0_timer_clk_conf register + * TIMERGROUP0_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 0.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t tg0_timer_clk_sel:2; + /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ + uint32_t tg0_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_timer_clk_conf_reg_t; + +/** Type of timergroup0_wdt_clk_conf register + * TIMERGROUP0_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 0.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t tg0_wdt_clk_sel:2; + /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg0_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_wdt_clk_conf_reg_t; + +/** Type of timergroup1_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ + uint32_t tg1_clk_en:1; + /** tg1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ + uint32_t tg1_rst_en:1; + /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ + uint32_t tg1_wdt_ready:1; + /** tg1_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ + uint32_t tg1_timer0_ready:1; + /** tg1_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg1_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup1_conf_reg_t; + +/** Type of timergroup1_timer_clk_conf register + * TIMERGROUP1_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 1.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t tg1_timer_clk_sel:2; + /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ + uint32_t tg1_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_timer_clk_conf_reg_t; + +/** Type of timergroup1_wdt_clk_conf register + * TIMERGROUP1_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 1.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t tg1_wdt_clk_sel:2; + /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg1_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_wdt_clk_conf_reg_t; + +/** Type of systimer_conf register + * SYSTIMER configuration register + */ +typedef union { + struct { + /** systimer_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ + uint32_t systimer_clk_en:1; + /** systimer_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ + uint32_t systimer_rst_en:1; + /** systimer_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ + uint32_t systimer_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_systimer_conf_reg_t; + +/** Type of systimer_func_clk_conf register + * SYSTIMER_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; + * Configures the clock source of System Timer.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + */ + uint32_t systimer_func_clk_sel:1; + uint32_t reserved_21:1; + /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ + uint32_t systimer_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_systimer_func_clk_conf_reg_t; + +/** Type of i2s_conf register + * I2S configuration register + */ +typedef union { + struct { + /** i2s_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ + uint32_t i2s_clk_en:1; + /** i2s_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ + uint32_t i2s_rst_en:1; + /** i2s_rx_ready : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ + uint32_t i2s_rx_ready:1; + /** i2s_tx_ready : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ + uint32_t i2s_tx_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_i2s_conf_reg_t; + +/** Type of i2s_tx_clkm_conf register + * I2S_TX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t i2s_tx_clkm_div_num:8; + /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S TX.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F120M_CLK\\ + * 2: PLL_F160M_CLK\\ + * 3: I2S_MCLK_in\\ + */ + uint32_t i2s_tx_clkm_sel:2; + /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ + uint32_t i2s_tx_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2s_tx_clkm_conf_reg_t; + +/** Type of i2s_tx_clkm_div_conf register + * I2S_TX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_tx_clkm_div_z:9; + /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_tx_clkm_div_y:9; + /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_tx_clkm_div_x:9; + /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_tx_clkm_div_conf_reg_t; + +/** Type of i2s_rx_clkm_conf register + * I2S_RX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ + uint32_t i2s_rx_clkm_div_num:8; + /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S RX.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F120M_CLK\\ + * 2: PLL_F160M_CLK\\ + * 3: I2S_MCLK_in\\ + */ + uint32_t i2s_rx_clkm_sel:2; + /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ + uint32_t i2s_rx_clkm_en:1; + /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; + * Configures to select master clock.\\ + * 0 (default): I2S_TX_CLK\\ + * 1: I2S_RX_CLK\\ + */ + uint32_t i2s_mclk_sel:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_i2s_rx_clkm_conf_reg_t; + +/** Type of i2s_rx_clkm_div_conf register + * I2S_RX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_rx_clkm_div_z:9; + /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_rx_clkm_div_y:9; + /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_rx_clkm_div_x:9; + /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_rx_clkm_div_conf_reg_t; + +/** Type of saradc_conf register + * SARADC configuration register + */ +typedef union { + struct { + /** saradc_clk_en : R/W; bitpos: [0]; default: 1; + * no use + */ + uint32_t saradc_clk_en:1; + /** saradc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ + uint32_t saradc_rst_en:1; + /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ + uint32_t saradc_reg_clk_en:1; + /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ + uint32_t saradc_reg_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_saradc_conf_reg_t; + +/** Type of saradc_clkm_conf register + * SARADC_CLKM configuration register + */ +typedef union { + struct { + /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SAR ADC.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t saradc_clkm_sel:2; + /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ + uint32_t saradc_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_saradc_clkm_conf_reg_t; + +/** Type of tsens_clk_conf register + * TSENS_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; + * Configures the clock source of the temperature sensor.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + */ + uint32_t tsens_clk_sel:1; + uint32_t reserved_21:1; + /** tsens_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ + uint32_t tsens_clk_en:1; + /** tsens_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ + uint32_t tsens_rst_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_tsens_clk_conf_reg_t; + +/** Type of usb_device_conf register + * USB_DEVICE configuration register + */ +typedef union { + struct { + /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ + uint32_t usb_device_clk_en:1; + /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ + uint32_t usb_device_rst_en:1; + /** usb_device_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ + uint32_t usb_device_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_usb_device_conf_reg_t; + +/** Type of intmtx_conf register + * INTMTX configuration register + */ +typedef union { + struct { + /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ + uint32_t intmtx_clk_en:1; + /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ + uint32_t intmtx_rst_en:1; + /** intmtx_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ + uint32_t intmtx_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_intmtx_conf_reg_t; + +/** Type of pvt_monitor_conf register + * PVT_MONITOR configuration register + */ +typedef union { + struct { + /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ + uint32_t pvt_monitor_clk_en:1; + /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 1 to reset all pvt monitor module + */ + uint32_t pvt_monitor_rst_en:1; + uint32_t reserved_2:1; + /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ + uint32_t pvt_monitor_site2_clk_en:1; + /** pvt_monitor_site2_rst_en : R/W; bitpos: [4]; default: 0; + * Set 1 to reset cpu pvt monitor site + */ + uint32_t pvt_monitor_site2_rst_en:1; + /** pvt_monitor_site3_clk_en : R/W; bitpos: [5]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ + uint32_t pvt_monitor_site3_clk_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pcr_pvt_monitor_conf_reg_t; + +/** Type of pvt_monitor_func_clk_conf register + * PVT_MONITOR function clock configuration register + */ +typedef union { + struct { + /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ + uint32_t pvt_monitor_func_clk_div_num:4; + uint32_t reserved_4:16; + /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; + * Configures the clock source of PVT MONITER.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F160M_CLK\\ + */ + uint32_t pvt_monitor_func_clk_sel:1; + uint32_t reserved_21:1; + /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ + uint32_t pvt_monitor_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pvt_monitor_func_clk_conf_reg_t; + +/** Type of gdma_conf register + * GDMA configuration register + */ +typedef union { + struct { + /** gdma_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ + uint32_t gdma_clk_en:1; + /** gdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ + uint32_t gdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_gdma_conf_reg_t; + +/** Type of spi2_conf register + * SPI2 configuration register + */ +typedef union { + struct { + /** spi2_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ + uint32_t spi2_clk_en:1; + /** spi2_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ + uint32_t spi2_rst_en:1; + /** spi2_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ + uint32_t spi2_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_spi2_conf_reg_t; + +/** Type of spi2_clkm_conf register + * SPI2_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** spi2_clkm_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ + uint32_t spi2_clkm_div_num:8; + /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SPI2.\\ + * 0 (default): XTAL_CLK\\ + * 1: PLL_F160M_CLK\\ + * 2: RC_FAST_CLK\\ + */ + uint32_t spi2_clkm_sel:2; + /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ + uint32_t spi2_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_spi2_clkm_conf_reg_t; + +/** Type of aes_conf register + * AES configuration register + */ +typedef union { + struct { + /** aes_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ + uint32_t aes_clk_en:1; + /** aes_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ + uint32_t aes_rst_en:1; + /** aes_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ + uint32_t aes_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_aes_conf_reg_t; + +/** Type of sha_conf register + * SHA configuration register + */ +typedef union { + struct { + /** sha_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ + uint32_t sha_clk_en:1; + /** sha_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ + uint32_t sha_rst_en:1; + /** sha_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ + uint32_t sha_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sha_conf_reg_t; + +/** Type of rsa_conf register + * RSA configuration register + */ +typedef union { + struct { + /** rsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ + uint32_t rsa_clk_en:1; + /** rsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ + uint32_t rsa_rst_en:1; + /** rsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ + uint32_t rsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_conf_reg_t; + +/** Type of rsa_pd_ctrl register + * RSA power control register + */ +typedef union { + struct { + /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ + uint32_t rsa_mem_pd:1; + /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ + uint32_t rsa_mem_force_pu:1; + /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ + uint32_t rsa_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_pd_ctrl_reg_t; + +/** Type of ecc_conf register + * ECC configuration register + */ +typedef union { + struct { + /** ecc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ + uint32_t ecc_clk_en:1; + /** ecc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ + uint32_t ecc_rst_en:1; + /** ecc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ + uint32_t ecc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_conf_reg_t; + +/** Type of ecc_pd_ctrl register + * ECC power control register + */ +typedef union { + struct { + /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ + uint32_t ecc_mem_pd:1; + /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ + uint32_t ecc_mem_force_pu:1; + /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ + uint32_t ecc_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_pd_ctrl_reg_t; + +/** Type of ds_conf register + * DS configuration register + */ +typedef union { + struct { + /** ds_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ + uint32_t ds_clk_en:1; + /** ds_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ + uint32_t ds_rst_en:1; + /** ds_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ + uint32_t ds_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ds_conf_reg_t; + +/** Type of hmac_conf register + * HMAC configuration register + */ +typedef union { + struct { + /** hmac_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ + uint32_t hmac_clk_en:1; + /** hmac_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ + uint32_t hmac_rst_en:1; + /** hmac_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ + uint32_t hmac_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_hmac_conf_reg_t; + +/** Type of ecdsa_conf register + * ECDSA configuration register + */ +typedef union { + struct { + /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ + uint32_t ecdsa_clk_en:1; + /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ + uint32_t ecdsa_rst_en:1; + /** ecdsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ + uint32_t ecdsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecdsa_conf_reg_t; + +/** Type of iomux_conf register + * IOMUX configuration register + */ +typedef union { + struct { + /** iomux_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ + uint32_t iomux_clk_en:1; + /** iomux_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ + uint32_t iomux_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_iomux_conf_reg_t; + +/** Type of iomux_clk_conf register + * IOMUX_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of IO MUX.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F80M_CLK\\ + */ + uint32_t iomux_func_clk_sel:2; + /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ + uint32_t iomux_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_iomux_clk_conf_reg_t; + +/** Type of tcm_mem_monitor_conf register + * TCM_MEM_MONITOR configuration register + */ +typedef union { + struct { + /** tcm_mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable tcm_mem_monitor clock + */ + uint32_t tcm_mem_monitor_clk_en:1; + /** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset tcm_mem_monitor module + */ + uint32_t tcm_mem_monitor_rst_en:1; + /** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset tcm_mem_monitor module + */ + uint32_t tcm_mem_monitor_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_tcm_mem_monitor_conf_reg_t; + +/** Type of psram_mem_monitor_conf register + * PSRAM_MEM_MONITOR configuration register + */ +typedef union { + struct { + /** psram_mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable psram_mem_monitor clock + */ + uint32_t psram_mem_monitor_clk_en:1; + /** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset psram_mem_monitor module + */ + uint32_t psram_mem_monitor_rst_en:1; + /** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset psram_mem_monitor module + */ + uint32_t psram_mem_monitor_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_psram_mem_monitor_conf_reg_t; + +/** Type of trace_conf register + * TRACE configuration register + */ +typedef union { + struct { + /** trace_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ + uint32_t trace_clk_en:1; + /** trace_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ + uint32_t trace_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_trace_conf_reg_t; + +/** Type of assist_conf register + * ASSIST configuration register + */ +typedef union { + struct { + /** assist_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ + uint32_t assist_clk_en:1; + /** assist_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ + uint32_t assist_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_assist_conf_reg_t; + +/** Type of cache_conf register + * CACHE configuration register + */ +typedef union { + struct { + /** cache_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ + uint32_t cache_clk_en:1; + /** cache_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ + uint32_t cache_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_cache_conf_reg_t; + +/** Type of cache_pd_ctrl register + * CACHE power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cache_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down CACHE memory. + */ + uint32_t cache_mem_force_pu:1; + /** cache_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up CACHE memory. + */ + uint32_t cache_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_cache_pd_ctrl_reg_t; + +/** Type of modem_conf register + * MODEM_APB configuration register + */ +typedef union { + struct { + /** modem_apb_clk_en : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ + uint32_t modem_apb_clk_en:1; + /** modem_rst_en : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ + uint32_t modem_rst_en:1; + /** modem_clk_en : R/W; bitpos: [2]; default: 1; + * This field indicates if modem source clock is enable. 0: disable, 1: + * enable(default). + */ + uint32_t modem_clk_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_modem_conf_reg_t; + +/** Type of timeout_conf register + * TIMEOUT configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ + uint32_t cpu_timeout_rst_en:1; + /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ + uint32_t hp_timeout_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_timeout_conf_reg_t; + +/** Type of sysclk_conf register + * SYSCLK configuration register + */ +typedef union { + struct { + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; + /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; + * Configures to select the clock source of HP_ROOT_CLK.\\ + * 0 (default): XTAL_CLK\\ + * 1: RC_FAST_CLK\\ + * 2: PLL_F160M_CLK\\ + */ + uint32_t soc_clk_sel:2; + uint32_t reserved_18:6; + /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ + uint32_t clk_xtal_freq:7; + /** cpu_dbgmd_clk_en : R/W; bitpos: [31]; default: 1; + * This field indicates if cpu debug mode clock is enable. 0: disable, 1: + * enable(default). + */ + uint32_t cpu_dbgmd_clk_en:1; + }; + uint32_t val; +} pcr_sysclk_conf_reg_t; + +/** Type of cpu_waiti_conf register + * CPU_WAITI configuration register + */ +typedef union { + struct { + /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ + uint32_t cpuperiod_sel:2; + /** pll_freq_sel : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ + uint32_t pll_freq_sel:1; + /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ + uint32_t cpu_wait_mode_force_on:1; + /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ + uint32_t cpu_waiti_delay_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_waiti_conf_reg_t; + +/** Type of cpu_freq_conf register + * CPU_FREQ configuration register + */ +typedef union { + struct { + /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ + uint32_t cpu_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_freq_conf_reg_t; + +/** Type of ahb_freq_conf register + * AHB_FREQ configuration register + */ +typedef union { + struct { + /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ + uint32_t ahb_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_ahb_freq_conf_reg_t; + +/** Type of apb_freq_conf register + * APB_FREQ configuration register + */ +typedef union { + struct { + /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ + uint32_t apb_decrease_div_num:8; + /** apb_div_num : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ + uint32_t apb_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_apb_freq_conf_reg_t; + +/** Type of pll_div_clk_en register + * SPLL DIV clock-gating configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_160m_clk_en:1; + /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_120m_clk_en:1; + /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_80m_clk_en:1; + /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_60m_clk_en:1; + /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_48m_clk_en:1; + /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_40m_clk_en:1; + /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_20m_clk_en:1; + /** pll_12m_clk_en : HRO; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_12m_clk_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pll_div_clk_en_reg_t; + +/** Type of ctrl_clk_out_en register + * CLK_OUT_EN configuration register + */ +typedef union { + struct { + /** clk20_oen : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ + uint32_t clk20_oen:1; + /** clk22_oen : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ + uint32_t clk22_oen:1; + /** clk44_oen : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ + uint32_t clk44_oen:1; + /** clk_bb_oen : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ + uint32_t clk_bb_oen:1; + /** clk80_oen : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ + uint32_t clk80_oen:1; + /** clk160_oen : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ + uint32_t clk160_oen:1; + /** clk_320m_oen : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ + uint32_t clk_320m_oen:1; + /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1; + * Reserved + */ + uint32_t clk_adc_inf_oen:1; + /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t clk_dac_cpu_oen:1; + /** clk_xtal_oen : R/W; bitpos: [9]; default: 1; + * Set 1 to enable xtal clock + */ + uint32_t clk_xtal_oen:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pcr_ctrl_clk_out_en_reg_t; + +/** Type of ctrl_32k_conf register + * 32KHz clock configuration register + */ +typedef union { + struct { + /** 32k_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP.\\ + * 0 (default): RC32K_CLK\\ + * 1: XTAL32K_CLK\\ + * 2: OSC_SLOW_CLK\\ + * 3: RC_SLOW_CLK\\ + * 4: RC_FAST_CLK\\ + */ + uint32_t 32k_sel:3; + uint32_t reserved_3:5; + /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; + * When PCR_32K_SEL set as 4, This field PCR_FOSC_TICK_NUM is used to set the divider + * number of fosc. + */ + uint32_t fosc_tick_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_ctrl_32k_conf_reg_t; + +/** Type of sram_power_conf_0 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** rom_force_pu : R/W; bitpos: [1:0]; default: 3; + * Set this bit to force power up ROM + */ + uint32_t rom_force_pu:2; + /** rom_force_pd : R/W; bitpos: [3:2]; default: 0; + * Set this bit to force power down ROM. + */ + uint32_t rom_force_pd:2; + /** rom_clkgate_force_on : R/W; bitpos: [5:4]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ + uint32_t rom_clkgate_force_on:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} pcr_sram_power_conf_0_reg_t; + +/** Type of sram_power_conf_1 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** sram_force_pu : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ + uint32_t sram_force_pu:5; + uint32_t reserved_5:5; + /** sram_force_pd : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ + uint32_t sram_force_pd:5; + uint32_t reserved_15:5; + /** sram_clkgate_force_on : R/W; bitpos: [24:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ + uint32_t sram_clkgate_force_on:5; + uint32_t reserved_25:7; + }; + uint32_t val; +} pcr_sram_power_conf_1_reg_t; + +/** Type of sec_conf register + * Clock source configuration register for External Memory Encryption and Decryption + */ +typedef union { + struct { + /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the External Memory Encryption and Decryption + * module.\\ + * 0(default): XTAL_CLK\\ + * 1 RC_FAST_CLK\\ + * 2: PLL_F480M_CLK\\ + */ + uint32_t sec_clk_sel:2; + /** sec_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset sec module + */ + uint32_t sec_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sec_conf_reg_t; + +/** Type of adc_dac_inv_phase_conf register + * xxxx + */ +typedef union { + struct { + /** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t clk_rx_adc_inv_phase_ena:1; + /** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0; + * xxxx + */ + uint32_t clk_tx_dac_inv_phase_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_adc_dac_inv_phase_conf_reg_t; + +/** Type of bus_clk_update register + * Configuration register for applying updated high-performance system clock sources + */ +typedef union { + struct { + /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; + * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK + * division and HP_ROOT_CLK clock source selection.\\ + * 0: Not update configurations\\ + * 1: Update configurations\\ + * This bit is automatically cleared when configurations have been updated.\\ + */ + uint32_t bus_clock_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_bus_clk_update_reg_t; + +/** Type of sar_clk_div register + * SAR ADC clock divisor configuration register + */ +typedef union { + struct { + /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control + * signals.\\ + */ + uint32_t sar2_clk_div_num:8; + /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control + * signals.\\ + */ + uint32_t sar1_clk_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_sar_clk_div_reg_t; + +/** Type of pwdet_sar_clk_conf register + * xxxx + */ +typedef union { + struct { + /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ + uint32_t pwdet_sar_clk_div_num:8; + /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; + * xxxx + */ + uint32_t pwdet_sar_clk_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pwdet_sar_clk_conf_reg_t; + +/** Type of timergroup_wdt_conf register + * TIMERGROUP_WDT configuration register + */ +typedef union { + struct { + /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 wdt module + */ + uint32_t tg0_wdt_rst_en:1; + /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 wdt module + */ + uint32_t tg1_wdt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup_wdt_conf_reg_t; + +/** Type of timergroup_xtal_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 xtal clock domain + */ + uint32_t tg0_xtal_rst_en:1; + /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 xtal clock domain + */ + uint32_t tg1_xtal_rst_en:1; + /** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable tg0 xtal clock + */ + uint32_t tg0_xtal_clk_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_timergroup_xtal_conf_reg_t; + +/** Type of reset_event_bypass register + * reset event bypass backdoor configuration register + */ +typedef union { + struct { + /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ + uint32_t reset_event_bypass_apm:1; + /** reset_event_bypass : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ + uint32_t reset_event_bypass:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_reset_event_bypass_reg_t; + +/** Type of regdma_conf register + * REGDMA configuration register + */ +typedef union { + struct { + /** regdma_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ + uint32_t regdma_clk_en:1; + /** regdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ + uint32_t regdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_regdma_conf_reg_t; + +/** Type of etm_conf register + * ETM configuration register + */ +typedef union { + struct { + /** etm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ + uint32_t etm_clk_en:1; + /** etm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ + uint32_t etm_rst_en:1; + /** etm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ + uint32_t etm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_etm_conf_reg_t; + +/** Type of clock_gate register + * PCR clock gating configure register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_clock_gate_reg_t; + + +/** Group: Frequency Statistics Register */ +/** Type of sysclk_freq_query_0 register + * SYSCLK frequency query 0 register + */ +typedef union { + struct { + /** fosc_freq : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ + uint32_t fosc_freq:8; + /** pll_freq : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ + uint32_t pll_freq:10; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_sysclk_freq_query_0_reg_t; + + +/** Group: FPGA Debug Register */ +/** Type of fpga_debug register + * fpga debug register + */ +typedef union { + struct { + /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ + uint32_t fpga_debug:32; + }; + uint32_t val; +} pcr_fpga_debug_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37753376; + * PCR version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_date_reg_t; + + +typedef struct { + volatile pcr_uart0_conf_reg_t uart0_conf; + volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; + volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; + volatile pcr_uart1_conf_reg_t uart1_conf; + volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; + volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; + volatile pcr_uart2_conf_reg_t uart2_conf; + volatile pcr_uart2_sclk_conf_reg_t uart2_sclk_conf; + volatile pcr_uart2_pd_ctrl_reg_t uart2_pd_ctrl; + volatile pcr_mspi_conf_reg_t mspi_conf; + volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; + volatile pcr_i2c_conf_reg_t i2c_conf; + volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; + volatile pcr_ledc_conf_reg_t ledc_conf; + volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; + volatile pcr_ledc_pd_ctrl_reg_t ledc_pd_ctrl; + volatile pcr_timergroup0_conf_reg_t timergroup0_conf; + volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; + volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; + volatile pcr_timergroup1_conf_reg_t timergroup1_conf; + volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; + volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; + volatile pcr_systimer_conf_reg_t systimer_conf; + volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; + volatile pcr_i2s_conf_reg_t i2s_conf; + volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; + volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; + volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; + volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; + volatile pcr_saradc_conf_reg_t saradc_conf; + volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; + volatile pcr_usb_device_conf_reg_t usb_device_conf; + volatile pcr_intmtx_conf_reg_t intmtx_conf; + volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; + volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; + volatile pcr_gdma_conf_reg_t gdma_conf; + volatile pcr_spi2_conf_reg_t spi2_conf; + volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; + volatile pcr_aes_conf_reg_t aes_conf; + volatile pcr_sha_conf_reg_t sha_conf; + volatile pcr_rsa_conf_reg_t rsa_conf; + volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + volatile pcr_ecc_conf_reg_t ecc_conf; + volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; + volatile pcr_ds_conf_reg_t ds_conf; + volatile pcr_hmac_conf_reg_t hmac_conf; + volatile pcr_ecdsa_conf_reg_t ecdsa_conf; + volatile pcr_iomux_conf_reg_t iomux_conf; + volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; + volatile pcr_tcm_mem_monitor_conf_reg_t tcm_mem_monitor_conf; + volatile pcr_psram_mem_monitor_conf_reg_t psram_mem_monitor_conf; + volatile pcr_trace_conf_reg_t trace_conf; + volatile pcr_assist_conf_reg_t assist_conf; + volatile pcr_cache_conf_reg_t cache_conf; + volatile pcr_cache_pd_ctrl_reg_t cache_pd_ctrl; + volatile pcr_modem_conf_reg_t modem_conf; + volatile pcr_timeout_conf_reg_t timeout_conf; + volatile pcr_sysclk_conf_reg_t sysclk_conf; + volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; + volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; + volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; + volatile pcr_apb_freq_conf_reg_t apb_freq_conf; + volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; + volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; + volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; + uint32_t reserved_108; + volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; + volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; + volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; + volatile pcr_sec_conf_reg_t sec_conf; + volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf; + volatile pcr_bus_clk_update_reg_t bus_clk_update; + volatile pcr_sar_clk_div_reg_t sar_clk_div; + volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf; + volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf; + volatile pcr_reset_event_bypass_reg_t reset_event_bypass; + volatile pcr_regdma_conf_reg_t regdma_conf; + volatile pcr_etm_conf_reg_t etm_conf; + uint32_t reserved_140[941]; + volatile pcr_fpga_debug_reg_t fpga_debug; + volatile pcr_clock_gate_reg_t clock_gate; + volatile pcr_date_reg_t date; +} pcr_dev_t; + +extern pcr_dev_t PCR; + +#ifndef __cplusplus +_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..95dfeae588 --- /dev/null +++ b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define PMU_ICG_APB_ENA_CAN0 18 +#define PMU_ICG_APB_ENA_CAN1 19 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_I2C 13 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_FUNC_ENA_CAN0 31 +#define PMU_ICG_FUNC_ENA_CAN1 30 +#define PMU_ICG_FUNC_ENA_I2C 29 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_RETENTION 9 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_HPBUS 15 diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h new file mode 100644 index 0000000000..9ffd96ae8a --- /dev/null +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DR_REG_UART0_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_MSPI0_BASE 0x60002000 +#define DR_REG_MSPI1_BASE 0x60003000 +#define DR_REG_I2C_BASE 0x60004000 +#define DR_REG_UART2_BASE 0x60006000 +#define DR_REG_LEDC_BASE 0x60007000 +#define DR_REG_TIMG0_BASE 0x60008000 +#define DR_REG_TIMG1_BASE 0x60009000 +#define DR_REG_SYSTIMER_BASE 0x6000A000 +#define DR_REG_I2S_BASE 0x6000C000 +#define DR_REG_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_PVT_MONITOR_BASE 0x60019000 +#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 +#define DR_REG_AHB_GDMA_BASE 0x60080000 +#define DR_REG_GPSPI_BASE 0x60081000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_ECC_BASE 0x6008B000 +#define DR_REG_ECDSA_BASE 0x6008E000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_REG_BASE 0x60095000 +#define DR_REG_PCR_REG_BASE 0x60096000 +#define DR_REG_TEE_REG_BASE 0x60098000 +#define DR_REG_HP_APM_REG_BASE 0x60099000 +#define DR_REG_MISC_BASE 0x6009F000 +#define DR_REG_MODEM0_BASE 0x600A0000 +#define DR_REG_MODEM1_BASE 0x600AC000 +#define DR_REG_MODEM_PWR0_BASE 0x600AD000 +#define DR_REG_MODEM_PWR1_BASE 0x600AF000 +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANA_REG_BASE 0x600B2C00 +#define DR_REG_LP_TEE_BASE 0x600B3400 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_LP_IO_MUX_BASE 0x600B4000 +#define DR_REG_LP_GPIO_BASE 0x600B4400 +#define DR_REG_EFUSE_AND_OTP_DEBUG0_BASE 0x600B4800 +#define DR_REG_EFUSE_AND_OTP_DEBUG1_BASE 0x600B4C00 +#define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_BUS_MONITOR_BASE 0x600C2000 +#define DR_REG_INTPRI_REG_BASE 0x600C5000 +#define DR_REG_CACHE_CFG_BASE 0x600C8000 diff --git a/components/soc/esp32c61/include/soc/soc_etm_reg.h b/components/soc/esp32c61/include/soc/soc_etm_reg.h new file mode 100644 index 0000000000..c8e4b8d4d1 --- /dev/null +++ b/components/soc/esp32c61/include/soc/soc_etm_reg.h @@ -0,0 +1,6146 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SOC_ETM_CH_ENA_AD0_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED0 (BIT(0)) +#define SOC_ETM_CH_ENABLED0_M (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S) +#define SOC_ETM_CH_ENABLED0_V 0x00000001U +#define SOC_ETM_CH_ENABLED0_S 0 +/** SOC_ETM_CH_ENABLED1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED1 (BIT(1)) +#define SOC_ETM_CH_ENABLED1_M (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S) +#define SOC_ETM_CH_ENABLED1_V 0x00000001U +#define SOC_ETM_CH_ENABLED1_S 1 +/** SOC_ETM_CH_ENABLED2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED2 (BIT(2)) +#define SOC_ETM_CH_ENABLED2_M (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S) +#define SOC_ETM_CH_ENABLED2_V 0x00000001U +#define SOC_ETM_CH_ENABLED2_S 2 +/** SOC_ETM_CH_ENABLED3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED3 (BIT(3)) +#define SOC_ETM_CH_ENABLED3_M (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S) +#define SOC_ETM_CH_ENABLED3_V 0x00000001U +#define SOC_ETM_CH_ENABLED3_S 3 +/** SOC_ETM_CH_ENABLED4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED4 (BIT(4)) +#define SOC_ETM_CH_ENABLED4_M (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S) +#define SOC_ETM_CH_ENABLED4_V 0x00000001U +#define SOC_ETM_CH_ENABLED4_S 4 +/** SOC_ETM_CH_ENABLED5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED5 (BIT(5)) +#define SOC_ETM_CH_ENABLED5_M (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S) +#define SOC_ETM_CH_ENABLED5_V 0x00000001U +#define SOC_ETM_CH_ENABLED5_S 5 +/** SOC_ETM_CH_ENABLED6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED6 (BIT(6)) +#define SOC_ETM_CH_ENABLED6_M (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S) +#define SOC_ETM_CH_ENABLED6_V 0x00000001U +#define SOC_ETM_CH_ENABLED6_S 6 +/** SOC_ETM_CH_ENABLED7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED7 (BIT(7)) +#define SOC_ETM_CH_ENABLED7_M (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S) +#define SOC_ETM_CH_ENABLED7_V 0x00000001U +#define SOC_ETM_CH_ENABLED7_S 7 +/** SOC_ETM_CH_ENABLED8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED8 (BIT(8)) +#define SOC_ETM_CH_ENABLED8_M (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S) +#define SOC_ETM_CH_ENABLED8_V 0x00000001U +#define SOC_ETM_CH_ENABLED8_S 8 +/** SOC_ETM_CH_ENABLED9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED9 (BIT(9)) +#define SOC_ETM_CH_ENABLED9_M (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S) +#define SOC_ETM_CH_ENABLED9_V 0x00000001U +#define SOC_ETM_CH_ENABLED9_S 9 +/** SOC_ETM_CH_ENABLED10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED10 (BIT(10)) +#define SOC_ETM_CH_ENABLED10_M (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S) +#define SOC_ETM_CH_ENABLED10_V 0x00000001U +#define SOC_ETM_CH_ENABLED10_S 10 +/** SOC_ETM_CH_ENABLED11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED11 (BIT(11)) +#define SOC_ETM_CH_ENABLED11_M (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S) +#define SOC_ETM_CH_ENABLED11_V 0x00000001U +#define SOC_ETM_CH_ENABLED11_S 11 +/** SOC_ETM_CH_ENABLED12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED12 (BIT(12)) +#define SOC_ETM_CH_ENABLED12_M (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S) +#define SOC_ETM_CH_ENABLED12_V 0x00000001U +#define SOC_ETM_CH_ENABLED12_S 12 +/** SOC_ETM_CH_ENABLED13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED13 (BIT(13)) +#define SOC_ETM_CH_ENABLED13_M (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S) +#define SOC_ETM_CH_ENABLED13_V 0x00000001U +#define SOC_ETM_CH_ENABLED13_S 13 +/** SOC_ETM_CH_ENABLED14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED14 (BIT(14)) +#define SOC_ETM_CH_ENABLED14_M (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S) +#define SOC_ETM_CH_ENABLED14_V 0x00000001U +#define SOC_ETM_CH_ENABLED14_S 14 +/** SOC_ETM_CH_ENABLED15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED15 (BIT(15)) +#define SOC_ETM_CH_ENABLED15_M (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S) +#define SOC_ETM_CH_ENABLED15_V 0x00000001U +#define SOC_ETM_CH_ENABLED15_S 15 +/** SOC_ETM_CH_ENABLED16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED16 (BIT(16)) +#define SOC_ETM_CH_ENABLED16_M (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S) +#define SOC_ETM_CH_ENABLED16_V 0x00000001U +#define SOC_ETM_CH_ENABLED16_S 16 +/** SOC_ETM_CH_ENABLED17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED17 (BIT(17)) +#define SOC_ETM_CH_ENABLED17_M (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S) +#define SOC_ETM_CH_ENABLED17_V 0x00000001U +#define SOC_ETM_CH_ENABLED17_S 17 +/** SOC_ETM_CH_ENABLED18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED18 (BIT(18)) +#define SOC_ETM_CH_ENABLED18_M (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S) +#define SOC_ETM_CH_ENABLED18_V 0x00000001U +#define SOC_ETM_CH_ENABLED18_S 18 +/** SOC_ETM_CH_ENABLED19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED19 (BIT(19)) +#define SOC_ETM_CH_ENABLED19_M (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S) +#define SOC_ETM_CH_ENABLED19_V 0x00000001U +#define SOC_ETM_CH_ENABLED19_S 19 +/** SOC_ETM_CH_ENABLED20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED20 (BIT(20)) +#define SOC_ETM_CH_ENABLED20_M (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S) +#define SOC_ETM_CH_ENABLED20_V 0x00000001U +#define SOC_ETM_CH_ENABLED20_S 20 +/** SOC_ETM_CH_ENABLED21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED21 (BIT(21)) +#define SOC_ETM_CH_ENABLED21_M (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S) +#define SOC_ETM_CH_ENABLED21_V 0x00000001U +#define SOC_ETM_CH_ENABLED21_S 21 +/** SOC_ETM_CH_ENABLED22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED22 (BIT(22)) +#define SOC_ETM_CH_ENABLED22_M (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S) +#define SOC_ETM_CH_ENABLED22_V 0x00000001U +#define SOC_ETM_CH_ENABLED22_S 22 +/** SOC_ETM_CH_ENABLED23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED23 (BIT(23)) +#define SOC_ETM_CH_ENABLED23_M (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S) +#define SOC_ETM_CH_ENABLED23_V 0x00000001U +#define SOC_ETM_CH_ENABLED23_S 23 +/** SOC_ETM_CH_ENABLED24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED24 (BIT(24)) +#define SOC_ETM_CH_ENABLED24_M (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S) +#define SOC_ETM_CH_ENABLED24_V 0x00000001U +#define SOC_ETM_CH_ENABLED24_S 24 +/** SOC_ETM_CH_ENABLED25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED25 (BIT(25)) +#define SOC_ETM_CH_ENABLED25_M (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S) +#define SOC_ETM_CH_ENABLED25_V 0x00000001U +#define SOC_ETM_CH_ENABLED25_S 25 +/** SOC_ETM_CH_ENABLED26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED26 (BIT(26)) +#define SOC_ETM_CH_ENABLED26_M (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S) +#define SOC_ETM_CH_ENABLED26_V 0x00000001U +#define SOC_ETM_CH_ENABLED26_S 26 +/** SOC_ETM_CH_ENABLED27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED27 (BIT(27)) +#define SOC_ETM_CH_ENABLED27_M (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S) +#define SOC_ETM_CH_ENABLED27_V 0x00000001U +#define SOC_ETM_CH_ENABLED27_S 27 +/** SOC_ETM_CH_ENABLED28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED28 (BIT(28)) +#define SOC_ETM_CH_ENABLED28_M (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S) +#define SOC_ETM_CH_ENABLED28_V 0x00000001U +#define SOC_ETM_CH_ENABLED28_S 28 +/** SOC_ETM_CH_ENABLED29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED29 (BIT(29)) +#define SOC_ETM_CH_ENABLED29_M (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S) +#define SOC_ETM_CH_ENABLED29_V 0x00000001U +#define SOC_ETM_CH_ENABLED29_S 29 +/** SOC_ETM_CH_ENABLED30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED30 (BIT(30)) +#define SOC_ETM_CH_ENABLED30_M (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S) +#define SOC_ETM_CH_ENABLED30_V 0x00000001U +#define SOC_ETM_CH_ENABLED30_S 30 +/** SOC_ETM_CH_ENABLED31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED31 (BIT(31)) +#define SOC_ETM_CH_ENABLED31_M (SOC_ETM_CH_ENABLED31_V << SOC_ETM_CH_ENABLED31_S) +#define SOC_ETM_CH_ENABLED31_V 0x00000001U +#define SOC_ETM_CH_ENABLED31_S 31 + +/** SOC_ETM_CH_ENA_AD0_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE0 (BIT(0)) +#define SOC_ETM_CH_ENABLE0_M (SOC_ETM_CH_ENABLE0_V << SOC_ETM_CH_ENABLE0_S) +#define SOC_ETM_CH_ENABLE0_V 0x00000001U +#define SOC_ETM_CH_ENABLE0_S 0 +/** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE1 (BIT(1)) +#define SOC_ETM_CH_ENABLE1_M (SOC_ETM_CH_ENABLE1_V << SOC_ETM_CH_ENABLE1_S) +#define SOC_ETM_CH_ENABLE1_V 0x00000001U +#define SOC_ETM_CH_ENABLE1_S 1 +/** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE2 (BIT(2)) +#define SOC_ETM_CH_ENABLE2_M (SOC_ETM_CH_ENABLE2_V << SOC_ETM_CH_ENABLE2_S) +#define SOC_ETM_CH_ENABLE2_V 0x00000001U +#define SOC_ETM_CH_ENABLE2_S 2 +/** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE3 (BIT(3)) +#define SOC_ETM_CH_ENABLE3_M (SOC_ETM_CH_ENABLE3_V << SOC_ETM_CH_ENABLE3_S) +#define SOC_ETM_CH_ENABLE3_V 0x00000001U +#define SOC_ETM_CH_ENABLE3_S 3 +/** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE4 (BIT(4)) +#define SOC_ETM_CH_ENABLE4_M (SOC_ETM_CH_ENABLE4_V << SOC_ETM_CH_ENABLE4_S) +#define SOC_ETM_CH_ENABLE4_V 0x00000001U +#define SOC_ETM_CH_ENABLE4_S 4 +/** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE5 (BIT(5)) +#define SOC_ETM_CH_ENABLE5_M (SOC_ETM_CH_ENABLE5_V << SOC_ETM_CH_ENABLE5_S) +#define SOC_ETM_CH_ENABLE5_V 0x00000001U +#define SOC_ETM_CH_ENABLE5_S 5 +/** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE6 (BIT(6)) +#define SOC_ETM_CH_ENABLE6_M (SOC_ETM_CH_ENABLE6_V << SOC_ETM_CH_ENABLE6_S) +#define SOC_ETM_CH_ENABLE6_V 0x00000001U +#define SOC_ETM_CH_ENABLE6_S 6 +/** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE7 (BIT(7)) +#define SOC_ETM_CH_ENABLE7_M (SOC_ETM_CH_ENABLE7_V << SOC_ETM_CH_ENABLE7_S) +#define SOC_ETM_CH_ENABLE7_V 0x00000001U +#define SOC_ETM_CH_ENABLE7_S 7 +/** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE8 (BIT(8)) +#define SOC_ETM_CH_ENABLE8_M (SOC_ETM_CH_ENABLE8_V << SOC_ETM_CH_ENABLE8_S) +#define SOC_ETM_CH_ENABLE8_V 0x00000001U +#define SOC_ETM_CH_ENABLE8_S 8 +/** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE9 (BIT(9)) +#define SOC_ETM_CH_ENABLE9_M (SOC_ETM_CH_ENABLE9_V << SOC_ETM_CH_ENABLE9_S) +#define SOC_ETM_CH_ENABLE9_V 0x00000001U +#define SOC_ETM_CH_ENABLE9_S 9 +/** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE10 (BIT(10)) +#define SOC_ETM_CH_ENABLE10_M (SOC_ETM_CH_ENABLE10_V << SOC_ETM_CH_ENABLE10_S) +#define SOC_ETM_CH_ENABLE10_V 0x00000001U +#define SOC_ETM_CH_ENABLE10_S 10 +/** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE11 (BIT(11)) +#define SOC_ETM_CH_ENABLE11_M (SOC_ETM_CH_ENABLE11_V << SOC_ETM_CH_ENABLE11_S) +#define SOC_ETM_CH_ENABLE11_V 0x00000001U +#define SOC_ETM_CH_ENABLE11_S 11 +/** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE12 (BIT(12)) +#define SOC_ETM_CH_ENABLE12_M (SOC_ETM_CH_ENABLE12_V << SOC_ETM_CH_ENABLE12_S) +#define SOC_ETM_CH_ENABLE12_V 0x00000001U +#define SOC_ETM_CH_ENABLE12_S 12 +/** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE13 (BIT(13)) +#define SOC_ETM_CH_ENABLE13_M (SOC_ETM_CH_ENABLE13_V << SOC_ETM_CH_ENABLE13_S) +#define SOC_ETM_CH_ENABLE13_V 0x00000001U +#define SOC_ETM_CH_ENABLE13_S 13 +/** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE14 (BIT(14)) +#define SOC_ETM_CH_ENABLE14_M (SOC_ETM_CH_ENABLE14_V << SOC_ETM_CH_ENABLE14_S) +#define SOC_ETM_CH_ENABLE14_V 0x00000001U +#define SOC_ETM_CH_ENABLE14_S 14 +/** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE15 (BIT(15)) +#define SOC_ETM_CH_ENABLE15_M (SOC_ETM_CH_ENABLE15_V << SOC_ETM_CH_ENABLE15_S) +#define SOC_ETM_CH_ENABLE15_V 0x00000001U +#define SOC_ETM_CH_ENABLE15_S 15 +/** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE16 (BIT(16)) +#define SOC_ETM_CH_ENABLE16_M (SOC_ETM_CH_ENABLE16_V << SOC_ETM_CH_ENABLE16_S) +#define SOC_ETM_CH_ENABLE16_V 0x00000001U +#define SOC_ETM_CH_ENABLE16_S 16 +/** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE17 (BIT(17)) +#define SOC_ETM_CH_ENABLE17_M (SOC_ETM_CH_ENABLE17_V << SOC_ETM_CH_ENABLE17_S) +#define SOC_ETM_CH_ENABLE17_V 0x00000001U +#define SOC_ETM_CH_ENABLE17_S 17 +/** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE18 (BIT(18)) +#define SOC_ETM_CH_ENABLE18_M (SOC_ETM_CH_ENABLE18_V << SOC_ETM_CH_ENABLE18_S) +#define SOC_ETM_CH_ENABLE18_V 0x00000001U +#define SOC_ETM_CH_ENABLE18_S 18 +/** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE19 (BIT(19)) +#define SOC_ETM_CH_ENABLE19_M (SOC_ETM_CH_ENABLE19_V << SOC_ETM_CH_ENABLE19_S) +#define SOC_ETM_CH_ENABLE19_V 0x00000001U +#define SOC_ETM_CH_ENABLE19_S 19 +/** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE20 (BIT(20)) +#define SOC_ETM_CH_ENABLE20_M (SOC_ETM_CH_ENABLE20_V << SOC_ETM_CH_ENABLE20_S) +#define SOC_ETM_CH_ENABLE20_V 0x00000001U +#define SOC_ETM_CH_ENABLE20_S 20 +/** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE21 (BIT(21)) +#define SOC_ETM_CH_ENABLE21_M (SOC_ETM_CH_ENABLE21_V << SOC_ETM_CH_ENABLE21_S) +#define SOC_ETM_CH_ENABLE21_V 0x00000001U +#define SOC_ETM_CH_ENABLE21_S 21 +/** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE22 (BIT(22)) +#define SOC_ETM_CH_ENABLE22_M (SOC_ETM_CH_ENABLE22_V << SOC_ETM_CH_ENABLE22_S) +#define SOC_ETM_CH_ENABLE22_V 0x00000001U +#define SOC_ETM_CH_ENABLE22_S 22 +/** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE23 (BIT(23)) +#define SOC_ETM_CH_ENABLE23_M (SOC_ETM_CH_ENABLE23_V << SOC_ETM_CH_ENABLE23_S) +#define SOC_ETM_CH_ENABLE23_V 0x00000001U +#define SOC_ETM_CH_ENABLE23_S 23 +/** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE24 (BIT(24)) +#define SOC_ETM_CH_ENABLE24_M (SOC_ETM_CH_ENABLE24_V << SOC_ETM_CH_ENABLE24_S) +#define SOC_ETM_CH_ENABLE24_V 0x00000001U +#define SOC_ETM_CH_ENABLE24_S 24 +/** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE25 (BIT(25)) +#define SOC_ETM_CH_ENABLE25_M (SOC_ETM_CH_ENABLE25_V << SOC_ETM_CH_ENABLE25_S) +#define SOC_ETM_CH_ENABLE25_V 0x00000001U +#define SOC_ETM_CH_ENABLE25_S 25 +/** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE26 (BIT(26)) +#define SOC_ETM_CH_ENABLE26_M (SOC_ETM_CH_ENABLE26_V << SOC_ETM_CH_ENABLE26_S) +#define SOC_ETM_CH_ENABLE26_V 0x00000001U +#define SOC_ETM_CH_ENABLE26_S 26 +/** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE27 (BIT(27)) +#define SOC_ETM_CH_ENABLE27_M (SOC_ETM_CH_ENABLE27_V << SOC_ETM_CH_ENABLE27_S) +#define SOC_ETM_CH_ENABLE27_V 0x00000001U +#define SOC_ETM_CH_ENABLE27_S 27 +/** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE28 (BIT(28)) +#define SOC_ETM_CH_ENABLE28_M (SOC_ETM_CH_ENABLE28_V << SOC_ETM_CH_ENABLE28_S) +#define SOC_ETM_CH_ENABLE28_V 0x00000001U +#define SOC_ETM_CH_ENABLE28_S 28 +/** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE29 (BIT(29)) +#define SOC_ETM_CH_ENABLE29_M (SOC_ETM_CH_ENABLE29_V << SOC_ETM_CH_ENABLE29_S) +#define SOC_ETM_CH_ENABLE29_V 0x00000001U +#define SOC_ETM_CH_ENABLE29_S 29 +/** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE30 (BIT(30)) +#define SOC_ETM_CH_ENABLE30_M (SOC_ETM_CH_ENABLE30_V << SOC_ETM_CH_ENABLE30_S) +#define SOC_ETM_CH_ENABLE30_V 0x00000001U +#define SOC_ETM_CH_ENABLE30_S 30 +/** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE31 (BIT(31)) +#define SOC_ETM_CH_ENABLE31_M (SOC_ETM_CH_ENABLE31_V << SOC_ETM_CH_ENABLE31_S) +#define SOC_ETM_CH_ENABLE31_V 0x00000001U +#define SOC_ETM_CH_ENABLE31_S 31 + +/** SOC_ETM_CH_ENA_AD0_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE0 (BIT(0)) +#define SOC_ETM_CH_DISABLE0_M (SOC_ETM_CH_DISABLE0_V << SOC_ETM_CH_DISABLE0_S) +#define SOC_ETM_CH_DISABLE0_V 0x00000001U +#define SOC_ETM_CH_DISABLE0_S 0 +/** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE1 (BIT(1)) +#define SOC_ETM_CH_DISABLE1_M (SOC_ETM_CH_DISABLE1_V << SOC_ETM_CH_DISABLE1_S) +#define SOC_ETM_CH_DISABLE1_V 0x00000001U +#define SOC_ETM_CH_DISABLE1_S 1 +/** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE2 (BIT(2)) +#define SOC_ETM_CH_DISABLE2_M (SOC_ETM_CH_DISABLE2_V << SOC_ETM_CH_DISABLE2_S) +#define SOC_ETM_CH_DISABLE2_V 0x00000001U +#define SOC_ETM_CH_DISABLE2_S 2 +/** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE3 (BIT(3)) +#define SOC_ETM_CH_DISABLE3_M (SOC_ETM_CH_DISABLE3_V << SOC_ETM_CH_DISABLE3_S) +#define SOC_ETM_CH_DISABLE3_V 0x00000001U +#define SOC_ETM_CH_DISABLE3_S 3 +/** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE4 (BIT(4)) +#define SOC_ETM_CH_DISABLE4_M (SOC_ETM_CH_DISABLE4_V << SOC_ETM_CH_DISABLE4_S) +#define SOC_ETM_CH_DISABLE4_V 0x00000001U +#define SOC_ETM_CH_DISABLE4_S 4 +/** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE5 (BIT(5)) +#define SOC_ETM_CH_DISABLE5_M (SOC_ETM_CH_DISABLE5_V << SOC_ETM_CH_DISABLE5_S) +#define SOC_ETM_CH_DISABLE5_V 0x00000001U +#define SOC_ETM_CH_DISABLE5_S 5 +/** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE6 (BIT(6)) +#define SOC_ETM_CH_DISABLE6_M (SOC_ETM_CH_DISABLE6_V << SOC_ETM_CH_DISABLE6_S) +#define SOC_ETM_CH_DISABLE6_V 0x00000001U +#define SOC_ETM_CH_DISABLE6_S 6 +/** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE7 (BIT(7)) +#define SOC_ETM_CH_DISABLE7_M (SOC_ETM_CH_DISABLE7_V << SOC_ETM_CH_DISABLE7_S) +#define SOC_ETM_CH_DISABLE7_V 0x00000001U +#define SOC_ETM_CH_DISABLE7_S 7 +/** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE8 (BIT(8)) +#define SOC_ETM_CH_DISABLE8_M (SOC_ETM_CH_DISABLE8_V << SOC_ETM_CH_DISABLE8_S) +#define SOC_ETM_CH_DISABLE8_V 0x00000001U +#define SOC_ETM_CH_DISABLE8_S 8 +/** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE9 (BIT(9)) +#define SOC_ETM_CH_DISABLE9_M (SOC_ETM_CH_DISABLE9_V << SOC_ETM_CH_DISABLE9_S) +#define SOC_ETM_CH_DISABLE9_V 0x00000001U +#define SOC_ETM_CH_DISABLE9_S 9 +/** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE10 (BIT(10)) +#define SOC_ETM_CH_DISABLE10_M (SOC_ETM_CH_DISABLE10_V << SOC_ETM_CH_DISABLE10_S) +#define SOC_ETM_CH_DISABLE10_V 0x00000001U +#define SOC_ETM_CH_DISABLE10_S 10 +/** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE11 (BIT(11)) +#define SOC_ETM_CH_DISABLE11_M (SOC_ETM_CH_DISABLE11_V << SOC_ETM_CH_DISABLE11_S) +#define SOC_ETM_CH_DISABLE11_V 0x00000001U +#define SOC_ETM_CH_DISABLE11_S 11 +/** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE12 (BIT(12)) +#define SOC_ETM_CH_DISABLE12_M (SOC_ETM_CH_DISABLE12_V << SOC_ETM_CH_DISABLE12_S) +#define SOC_ETM_CH_DISABLE12_V 0x00000001U +#define SOC_ETM_CH_DISABLE12_S 12 +/** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE13 (BIT(13)) +#define SOC_ETM_CH_DISABLE13_M (SOC_ETM_CH_DISABLE13_V << SOC_ETM_CH_DISABLE13_S) +#define SOC_ETM_CH_DISABLE13_V 0x00000001U +#define SOC_ETM_CH_DISABLE13_S 13 +/** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE14 (BIT(14)) +#define SOC_ETM_CH_DISABLE14_M (SOC_ETM_CH_DISABLE14_V << SOC_ETM_CH_DISABLE14_S) +#define SOC_ETM_CH_DISABLE14_V 0x00000001U +#define SOC_ETM_CH_DISABLE14_S 14 +/** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE15 (BIT(15)) +#define SOC_ETM_CH_DISABLE15_M (SOC_ETM_CH_DISABLE15_V << SOC_ETM_CH_DISABLE15_S) +#define SOC_ETM_CH_DISABLE15_V 0x00000001U +#define SOC_ETM_CH_DISABLE15_S 15 +/** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE16 (BIT(16)) +#define SOC_ETM_CH_DISABLE16_M (SOC_ETM_CH_DISABLE16_V << SOC_ETM_CH_DISABLE16_S) +#define SOC_ETM_CH_DISABLE16_V 0x00000001U +#define SOC_ETM_CH_DISABLE16_S 16 +/** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE17 (BIT(17)) +#define SOC_ETM_CH_DISABLE17_M (SOC_ETM_CH_DISABLE17_V << SOC_ETM_CH_DISABLE17_S) +#define SOC_ETM_CH_DISABLE17_V 0x00000001U +#define SOC_ETM_CH_DISABLE17_S 17 +/** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE18 (BIT(18)) +#define SOC_ETM_CH_DISABLE18_M (SOC_ETM_CH_DISABLE18_V << SOC_ETM_CH_DISABLE18_S) +#define SOC_ETM_CH_DISABLE18_V 0x00000001U +#define SOC_ETM_CH_DISABLE18_S 18 +/** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE19 (BIT(19)) +#define SOC_ETM_CH_DISABLE19_M (SOC_ETM_CH_DISABLE19_V << SOC_ETM_CH_DISABLE19_S) +#define SOC_ETM_CH_DISABLE19_V 0x00000001U +#define SOC_ETM_CH_DISABLE19_S 19 +/** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE20 (BIT(20)) +#define SOC_ETM_CH_DISABLE20_M (SOC_ETM_CH_DISABLE20_V << SOC_ETM_CH_DISABLE20_S) +#define SOC_ETM_CH_DISABLE20_V 0x00000001U +#define SOC_ETM_CH_DISABLE20_S 20 +/** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE21 (BIT(21)) +#define SOC_ETM_CH_DISABLE21_M (SOC_ETM_CH_DISABLE21_V << SOC_ETM_CH_DISABLE21_S) +#define SOC_ETM_CH_DISABLE21_V 0x00000001U +#define SOC_ETM_CH_DISABLE21_S 21 +/** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE22 (BIT(22)) +#define SOC_ETM_CH_DISABLE22_M (SOC_ETM_CH_DISABLE22_V << SOC_ETM_CH_DISABLE22_S) +#define SOC_ETM_CH_DISABLE22_V 0x00000001U +#define SOC_ETM_CH_DISABLE22_S 22 +/** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE23 (BIT(23)) +#define SOC_ETM_CH_DISABLE23_M (SOC_ETM_CH_DISABLE23_V << SOC_ETM_CH_DISABLE23_S) +#define SOC_ETM_CH_DISABLE23_V 0x00000001U +#define SOC_ETM_CH_DISABLE23_S 23 +/** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE24 (BIT(24)) +#define SOC_ETM_CH_DISABLE24_M (SOC_ETM_CH_DISABLE24_V << SOC_ETM_CH_DISABLE24_S) +#define SOC_ETM_CH_DISABLE24_V 0x00000001U +#define SOC_ETM_CH_DISABLE24_S 24 +/** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE25 (BIT(25)) +#define SOC_ETM_CH_DISABLE25_M (SOC_ETM_CH_DISABLE25_V << SOC_ETM_CH_DISABLE25_S) +#define SOC_ETM_CH_DISABLE25_V 0x00000001U +#define SOC_ETM_CH_DISABLE25_S 25 +/** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE26 (BIT(26)) +#define SOC_ETM_CH_DISABLE26_M (SOC_ETM_CH_DISABLE26_V << SOC_ETM_CH_DISABLE26_S) +#define SOC_ETM_CH_DISABLE26_V 0x00000001U +#define SOC_ETM_CH_DISABLE26_S 26 +/** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE27 (BIT(27)) +#define SOC_ETM_CH_DISABLE27_M (SOC_ETM_CH_DISABLE27_V << SOC_ETM_CH_DISABLE27_S) +#define SOC_ETM_CH_DISABLE27_V 0x00000001U +#define SOC_ETM_CH_DISABLE27_S 27 +/** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE28 (BIT(28)) +#define SOC_ETM_CH_DISABLE28_M (SOC_ETM_CH_DISABLE28_V << SOC_ETM_CH_DISABLE28_S) +#define SOC_ETM_CH_DISABLE28_V 0x00000001U +#define SOC_ETM_CH_DISABLE28_S 28 +/** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE29 (BIT(29)) +#define SOC_ETM_CH_DISABLE29_M (SOC_ETM_CH_DISABLE29_V << SOC_ETM_CH_DISABLE29_S) +#define SOC_ETM_CH_DISABLE29_V 0x00000001U +#define SOC_ETM_CH_DISABLE29_S 29 +/** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE30 (BIT(30)) +#define SOC_ETM_CH_DISABLE30_M (SOC_ETM_CH_DISABLE30_V << SOC_ETM_CH_DISABLE30_S) +#define SOC_ETM_CH_DISABLE30_V 0x00000001U +#define SOC_ETM_CH_DISABLE30_S 30 +/** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE31 (BIT(31)) +#define SOC_ETM_CH_DISABLE31_M (SOC_ETM_CH_DISABLE31_V << SOC_ETM_CH_DISABLE31_S) +#define SOC_ETM_CH_DISABLE31_V 0x00000001U +#define SOC_ETM_CH_DISABLE31_S 31 + +/** SOC_ETM_CH_ENA_AD1_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED32 (BIT(0)) +#define SOC_ETM_CH_ENABLED32_M (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S) +#define SOC_ETM_CH_ENABLED32_V 0x00000001U +#define SOC_ETM_CH_ENABLED32_S 0 +/** SOC_ETM_CH_ENABLED33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED33 (BIT(1)) +#define SOC_ETM_CH_ENABLED33_M (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S) +#define SOC_ETM_CH_ENABLED33_V 0x00000001U +#define SOC_ETM_CH_ENABLED33_S 1 +/** SOC_ETM_CH_ENABLED34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED34 (BIT(2)) +#define SOC_ETM_CH_ENABLED34_M (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S) +#define SOC_ETM_CH_ENABLED34_V 0x00000001U +#define SOC_ETM_CH_ENABLED34_S 2 +/** SOC_ETM_CH_ENABLED35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED35 (BIT(3)) +#define SOC_ETM_CH_ENABLED35_M (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S) +#define SOC_ETM_CH_ENABLED35_V 0x00000001U +#define SOC_ETM_CH_ENABLED35_S 3 +/** SOC_ETM_CH_ENABLED36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED36 (BIT(4)) +#define SOC_ETM_CH_ENABLED36_M (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S) +#define SOC_ETM_CH_ENABLED36_V 0x00000001U +#define SOC_ETM_CH_ENABLED36_S 4 +/** SOC_ETM_CH_ENABLED37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED37 (BIT(5)) +#define SOC_ETM_CH_ENABLED37_M (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S) +#define SOC_ETM_CH_ENABLED37_V 0x00000001U +#define SOC_ETM_CH_ENABLED37_S 5 +/** SOC_ETM_CH_ENABLED38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED38 (BIT(6)) +#define SOC_ETM_CH_ENABLED38_M (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S) +#define SOC_ETM_CH_ENABLED38_V 0x00000001U +#define SOC_ETM_CH_ENABLED38_S 6 +/** SOC_ETM_CH_ENABLED39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED39 (BIT(7)) +#define SOC_ETM_CH_ENABLED39_M (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S) +#define SOC_ETM_CH_ENABLED39_V 0x00000001U +#define SOC_ETM_CH_ENABLED39_S 7 +/** SOC_ETM_CH_ENABLED40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED40 (BIT(8)) +#define SOC_ETM_CH_ENABLED40_M (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S) +#define SOC_ETM_CH_ENABLED40_V 0x00000001U +#define SOC_ETM_CH_ENABLED40_S 8 +/** SOC_ETM_CH_ENABLED41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED41 (BIT(9)) +#define SOC_ETM_CH_ENABLED41_M (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S) +#define SOC_ETM_CH_ENABLED41_V 0x00000001U +#define SOC_ETM_CH_ENABLED41_S 9 +/** SOC_ETM_CH_ENABLED42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED42 (BIT(10)) +#define SOC_ETM_CH_ENABLED42_M (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S) +#define SOC_ETM_CH_ENABLED42_V 0x00000001U +#define SOC_ETM_CH_ENABLED42_S 10 +/** SOC_ETM_CH_ENABLED43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED43 (BIT(11)) +#define SOC_ETM_CH_ENABLED43_M (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S) +#define SOC_ETM_CH_ENABLED43_V 0x00000001U +#define SOC_ETM_CH_ENABLED43_S 11 +/** SOC_ETM_CH_ENABLED44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED44 (BIT(12)) +#define SOC_ETM_CH_ENABLED44_M (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S) +#define SOC_ETM_CH_ENABLED44_V 0x00000001U +#define SOC_ETM_CH_ENABLED44_S 12 +/** SOC_ETM_CH_ENABLED45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED45 (BIT(13)) +#define SOC_ETM_CH_ENABLED45_M (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S) +#define SOC_ETM_CH_ENABLED45_V 0x00000001U +#define SOC_ETM_CH_ENABLED45_S 13 +/** SOC_ETM_CH_ENABLED46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED46 (BIT(14)) +#define SOC_ETM_CH_ENABLED46_M (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S) +#define SOC_ETM_CH_ENABLED46_V 0x00000001U +#define SOC_ETM_CH_ENABLED46_S 14 +/** SOC_ETM_CH_ENABLED47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED47 (BIT(15)) +#define SOC_ETM_CH_ENABLED47_M (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S) +#define SOC_ETM_CH_ENABLED47_V 0x00000001U +#define SOC_ETM_CH_ENABLED47_S 15 +/** SOC_ETM_CH_ENABLED48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED48 (BIT(16)) +#define SOC_ETM_CH_ENABLED48_M (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S) +#define SOC_ETM_CH_ENABLED48_V 0x00000001U +#define SOC_ETM_CH_ENABLED48_S 16 +/** SOC_ETM_CH_ENABLED49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED49 (BIT(17)) +#define SOC_ETM_CH_ENABLED49_M (SOC_ETM_CH_ENABLED49_V << SOC_ETM_CH_ENABLED49_S) +#define SOC_ETM_CH_ENABLED49_V 0x00000001U +#define SOC_ETM_CH_ENABLED49_S 17 + +/** SOC_ETM_CH_ENA_AD1_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE32 (BIT(0)) +#define SOC_ETM_CH_ENABLE32_M (SOC_ETM_CH_ENABLE32_V << SOC_ETM_CH_ENABLE32_S) +#define SOC_ETM_CH_ENABLE32_V 0x00000001U +#define SOC_ETM_CH_ENABLE32_S 0 +/** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE33 (BIT(1)) +#define SOC_ETM_CH_ENABLE33_M (SOC_ETM_CH_ENABLE33_V << SOC_ETM_CH_ENABLE33_S) +#define SOC_ETM_CH_ENABLE33_V 0x00000001U +#define SOC_ETM_CH_ENABLE33_S 1 +/** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE34 (BIT(2)) +#define SOC_ETM_CH_ENABLE34_M (SOC_ETM_CH_ENABLE34_V << SOC_ETM_CH_ENABLE34_S) +#define SOC_ETM_CH_ENABLE34_V 0x00000001U +#define SOC_ETM_CH_ENABLE34_S 2 +/** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE35 (BIT(3)) +#define SOC_ETM_CH_ENABLE35_M (SOC_ETM_CH_ENABLE35_V << SOC_ETM_CH_ENABLE35_S) +#define SOC_ETM_CH_ENABLE35_V 0x00000001U +#define SOC_ETM_CH_ENABLE35_S 3 +/** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE36 (BIT(4)) +#define SOC_ETM_CH_ENABLE36_M (SOC_ETM_CH_ENABLE36_V << SOC_ETM_CH_ENABLE36_S) +#define SOC_ETM_CH_ENABLE36_V 0x00000001U +#define SOC_ETM_CH_ENABLE36_S 4 +/** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE37 (BIT(5)) +#define SOC_ETM_CH_ENABLE37_M (SOC_ETM_CH_ENABLE37_V << SOC_ETM_CH_ENABLE37_S) +#define SOC_ETM_CH_ENABLE37_V 0x00000001U +#define SOC_ETM_CH_ENABLE37_S 5 +/** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE38 (BIT(6)) +#define SOC_ETM_CH_ENABLE38_M (SOC_ETM_CH_ENABLE38_V << SOC_ETM_CH_ENABLE38_S) +#define SOC_ETM_CH_ENABLE38_V 0x00000001U +#define SOC_ETM_CH_ENABLE38_S 6 +/** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE39 (BIT(7)) +#define SOC_ETM_CH_ENABLE39_M (SOC_ETM_CH_ENABLE39_V << SOC_ETM_CH_ENABLE39_S) +#define SOC_ETM_CH_ENABLE39_V 0x00000001U +#define SOC_ETM_CH_ENABLE39_S 7 +/** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE40 (BIT(8)) +#define SOC_ETM_CH_ENABLE40_M (SOC_ETM_CH_ENABLE40_V << SOC_ETM_CH_ENABLE40_S) +#define SOC_ETM_CH_ENABLE40_V 0x00000001U +#define SOC_ETM_CH_ENABLE40_S 8 +/** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE41 (BIT(9)) +#define SOC_ETM_CH_ENABLE41_M (SOC_ETM_CH_ENABLE41_V << SOC_ETM_CH_ENABLE41_S) +#define SOC_ETM_CH_ENABLE41_V 0x00000001U +#define SOC_ETM_CH_ENABLE41_S 9 +/** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE42 (BIT(10)) +#define SOC_ETM_CH_ENABLE42_M (SOC_ETM_CH_ENABLE42_V << SOC_ETM_CH_ENABLE42_S) +#define SOC_ETM_CH_ENABLE42_V 0x00000001U +#define SOC_ETM_CH_ENABLE42_S 10 +/** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE43 (BIT(11)) +#define SOC_ETM_CH_ENABLE43_M (SOC_ETM_CH_ENABLE43_V << SOC_ETM_CH_ENABLE43_S) +#define SOC_ETM_CH_ENABLE43_V 0x00000001U +#define SOC_ETM_CH_ENABLE43_S 11 +/** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE44 (BIT(12)) +#define SOC_ETM_CH_ENABLE44_M (SOC_ETM_CH_ENABLE44_V << SOC_ETM_CH_ENABLE44_S) +#define SOC_ETM_CH_ENABLE44_V 0x00000001U +#define SOC_ETM_CH_ENABLE44_S 12 +/** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE45 (BIT(13)) +#define SOC_ETM_CH_ENABLE45_M (SOC_ETM_CH_ENABLE45_V << SOC_ETM_CH_ENABLE45_S) +#define SOC_ETM_CH_ENABLE45_V 0x00000001U +#define SOC_ETM_CH_ENABLE45_S 13 +/** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE46 (BIT(14)) +#define SOC_ETM_CH_ENABLE46_M (SOC_ETM_CH_ENABLE46_V << SOC_ETM_CH_ENABLE46_S) +#define SOC_ETM_CH_ENABLE46_V 0x00000001U +#define SOC_ETM_CH_ENABLE46_S 14 +/** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE47 (BIT(15)) +#define SOC_ETM_CH_ENABLE47_M (SOC_ETM_CH_ENABLE47_V << SOC_ETM_CH_ENABLE47_S) +#define SOC_ETM_CH_ENABLE47_V 0x00000001U +#define SOC_ETM_CH_ENABLE47_S 15 +/** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE48 (BIT(16)) +#define SOC_ETM_CH_ENABLE48_M (SOC_ETM_CH_ENABLE48_V << SOC_ETM_CH_ENABLE48_S) +#define SOC_ETM_CH_ENABLE48_V 0x00000001U +#define SOC_ETM_CH_ENABLE48_S 16 +/** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE49 (BIT(17)) +#define SOC_ETM_CH_ENABLE49_M (SOC_ETM_CH_ENABLE49_V << SOC_ETM_CH_ENABLE49_S) +#define SOC_ETM_CH_ENABLE49_V 0x00000001U +#define SOC_ETM_CH_ENABLE49_S 17 + +/** SOC_ETM_CH_ENA_AD1_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE32 (BIT(0)) +#define SOC_ETM_CH_DISABLE32_M (SOC_ETM_CH_DISABLE32_V << SOC_ETM_CH_DISABLE32_S) +#define SOC_ETM_CH_DISABLE32_V 0x00000001U +#define SOC_ETM_CH_DISABLE32_S 0 +/** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE33 (BIT(1)) +#define SOC_ETM_CH_DISABLE33_M (SOC_ETM_CH_DISABLE33_V << SOC_ETM_CH_DISABLE33_S) +#define SOC_ETM_CH_DISABLE33_V 0x00000001U +#define SOC_ETM_CH_DISABLE33_S 1 +/** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE34 (BIT(2)) +#define SOC_ETM_CH_DISABLE34_M (SOC_ETM_CH_DISABLE34_V << SOC_ETM_CH_DISABLE34_S) +#define SOC_ETM_CH_DISABLE34_V 0x00000001U +#define SOC_ETM_CH_DISABLE34_S 2 +/** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE35 (BIT(3)) +#define SOC_ETM_CH_DISABLE35_M (SOC_ETM_CH_DISABLE35_V << SOC_ETM_CH_DISABLE35_S) +#define SOC_ETM_CH_DISABLE35_V 0x00000001U +#define SOC_ETM_CH_DISABLE35_S 3 +/** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE36 (BIT(4)) +#define SOC_ETM_CH_DISABLE36_M (SOC_ETM_CH_DISABLE36_V << SOC_ETM_CH_DISABLE36_S) +#define SOC_ETM_CH_DISABLE36_V 0x00000001U +#define SOC_ETM_CH_DISABLE36_S 4 +/** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE37 (BIT(5)) +#define SOC_ETM_CH_DISABLE37_M (SOC_ETM_CH_DISABLE37_V << SOC_ETM_CH_DISABLE37_S) +#define SOC_ETM_CH_DISABLE37_V 0x00000001U +#define SOC_ETM_CH_DISABLE37_S 5 +/** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE38 (BIT(6)) +#define SOC_ETM_CH_DISABLE38_M (SOC_ETM_CH_DISABLE38_V << SOC_ETM_CH_DISABLE38_S) +#define SOC_ETM_CH_DISABLE38_V 0x00000001U +#define SOC_ETM_CH_DISABLE38_S 6 +/** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE39 (BIT(7)) +#define SOC_ETM_CH_DISABLE39_M (SOC_ETM_CH_DISABLE39_V << SOC_ETM_CH_DISABLE39_S) +#define SOC_ETM_CH_DISABLE39_V 0x00000001U +#define SOC_ETM_CH_DISABLE39_S 7 +/** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE40 (BIT(8)) +#define SOC_ETM_CH_DISABLE40_M (SOC_ETM_CH_DISABLE40_V << SOC_ETM_CH_DISABLE40_S) +#define SOC_ETM_CH_DISABLE40_V 0x00000001U +#define SOC_ETM_CH_DISABLE40_S 8 +/** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE41 (BIT(9)) +#define SOC_ETM_CH_DISABLE41_M (SOC_ETM_CH_DISABLE41_V << SOC_ETM_CH_DISABLE41_S) +#define SOC_ETM_CH_DISABLE41_V 0x00000001U +#define SOC_ETM_CH_DISABLE41_S 9 +/** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE42 (BIT(10)) +#define SOC_ETM_CH_DISABLE42_M (SOC_ETM_CH_DISABLE42_V << SOC_ETM_CH_DISABLE42_S) +#define SOC_ETM_CH_DISABLE42_V 0x00000001U +#define SOC_ETM_CH_DISABLE42_S 10 +/** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE43 (BIT(11)) +#define SOC_ETM_CH_DISABLE43_M (SOC_ETM_CH_DISABLE43_V << SOC_ETM_CH_DISABLE43_S) +#define SOC_ETM_CH_DISABLE43_V 0x00000001U +#define SOC_ETM_CH_DISABLE43_S 11 +/** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE44 (BIT(12)) +#define SOC_ETM_CH_DISABLE44_M (SOC_ETM_CH_DISABLE44_V << SOC_ETM_CH_DISABLE44_S) +#define SOC_ETM_CH_DISABLE44_V 0x00000001U +#define SOC_ETM_CH_DISABLE44_S 12 +/** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE45 (BIT(13)) +#define SOC_ETM_CH_DISABLE45_M (SOC_ETM_CH_DISABLE45_V << SOC_ETM_CH_DISABLE45_S) +#define SOC_ETM_CH_DISABLE45_V 0x00000001U +#define SOC_ETM_CH_DISABLE45_S 13 +/** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE46 (BIT(14)) +#define SOC_ETM_CH_DISABLE46_M (SOC_ETM_CH_DISABLE46_V << SOC_ETM_CH_DISABLE46_S) +#define SOC_ETM_CH_DISABLE46_V 0x00000001U +#define SOC_ETM_CH_DISABLE46_S 14 +/** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE47 (BIT(15)) +#define SOC_ETM_CH_DISABLE47_M (SOC_ETM_CH_DISABLE47_V << SOC_ETM_CH_DISABLE47_S) +#define SOC_ETM_CH_DISABLE47_V 0x00000001U +#define SOC_ETM_CH_DISABLE47_S 15 +/** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE48 (BIT(16)) +#define SOC_ETM_CH_DISABLE48_M (SOC_ETM_CH_DISABLE48_V << SOC_ETM_CH_DISABLE48_S) +#define SOC_ETM_CH_DISABLE48_V 0x00000001U +#define SOC_ETM_CH_DISABLE48_S 16 +/** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE49 (BIT(17)) +#define SOC_ETM_CH_DISABLE49_M (SOC_ETM_CH_DISABLE49_V << SOC_ETM_CH_DISABLE49_S) +#define SOC_ETM_CH_DISABLE49_V 0x00000001U +#define SOC_ETM_CH_DISABLE49_S 17 + +/** SOC_ETM_CH0_EVT_ID_REG register + * Channel0 event id register + */ +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) +/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch0_evt_id + */ +#define SOC_ETM_CH0_EVT_ID 0x0000007FU +#define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) +#define SOC_ETM_CH0_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH0_EVT_ID_S 0 + +/** SOC_ETM_CH0_TASK_ID_REG register + * Channel0 task id register + */ +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) +/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_task_id + */ +#define SOC_ETM_CH0_TASK_ID 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) +#define SOC_ETM_CH0_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_S 0 + +/** SOC_ETM_CH1_EVT_ID_REG register + * Channel1 event id register + */ +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) +/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch1_evt_id + */ +#define SOC_ETM_CH1_EVT_ID 0x0000007FU +#define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) +#define SOC_ETM_CH1_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH1_EVT_ID_S 0 + +/** SOC_ETM_CH1_TASK_ID_REG register + * Channel1 task id register + */ +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) +/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_task_id + */ +#define SOC_ETM_CH1_TASK_ID 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) +#define SOC_ETM_CH1_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_S 0 + +/** SOC_ETM_CH2_EVT_ID_REG register + * Channel2 event id register + */ +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) +/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch2_evt_id + */ +#define SOC_ETM_CH2_EVT_ID 0x0000007FU +#define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) +#define SOC_ETM_CH2_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH2_EVT_ID_S 0 + +/** SOC_ETM_CH2_TASK_ID_REG register + * Channel2 task id register + */ +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) +/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_task_id + */ +#define SOC_ETM_CH2_TASK_ID 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) +#define SOC_ETM_CH2_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_S 0 + +/** SOC_ETM_CH3_EVT_ID_REG register + * Channel3 event id register + */ +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) +/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch3_evt_id + */ +#define SOC_ETM_CH3_EVT_ID 0x0000007FU +#define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) +#define SOC_ETM_CH3_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH3_EVT_ID_S 0 + +/** SOC_ETM_CH3_TASK_ID_REG register + * Channel3 task id register + */ +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) +/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_task_id + */ +#define SOC_ETM_CH3_TASK_ID 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) +#define SOC_ETM_CH3_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_S 0 + +/** SOC_ETM_CH4_EVT_ID_REG register + * Channel4 event id register + */ +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) +/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch4_evt_id + */ +#define SOC_ETM_CH4_EVT_ID 0x0000007FU +#define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) +#define SOC_ETM_CH4_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH4_EVT_ID_S 0 + +/** SOC_ETM_CH4_TASK_ID_REG register + * Channel4 task id register + */ +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) +/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_task_id + */ +#define SOC_ETM_CH4_TASK_ID 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) +#define SOC_ETM_CH4_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_S 0 + +/** SOC_ETM_CH5_EVT_ID_REG register + * Channel5 event id register + */ +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) +/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch5_evt_id + */ +#define SOC_ETM_CH5_EVT_ID 0x0000007FU +#define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) +#define SOC_ETM_CH5_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH5_EVT_ID_S 0 + +/** SOC_ETM_CH5_TASK_ID_REG register + * Channel5 task id register + */ +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) +/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_task_id + */ +#define SOC_ETM_CH5_TASK_ID 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) +#define SOC_ETM_CH5_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_S 0 + +/** SOC_ETM_CH6_EVT_ID_REG register + * Channel6 event id register + */ +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) +/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch6_evt_id + */ +#define SOC_ETM_CH6_EVT_ID 0x0000007FU +#define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) +#define SOC_ETM_CH6_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH6_EVT_ID_S 0 + +/** SOC_ETM_CH6_TASK_ID_REG register + * Channel6 task id register + */ +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) +/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_task_id + */ +#define SOC_ETM_CH6_TASK_ID 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) +#define SOC_ETM_CH6_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_S 0 + +/** SOC_ETM_CH7_EVT_ID_REG register + * Channel7 event id register + */ +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) +/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch7_evt_id + */ +#define SOC_ETM_CH7_EVT_ID 0x0000007FU +#define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) +#define SOC_ETM_CH7_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH7_EVT_ID_S 0 + +/** SOC_ETM_CH7_TASK_ID_REG register + * Channel7 task id register + */ +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) +/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_task_id + */ +#define SOC_ETM_CH7_TASK_ID 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) +#define SOC_ETM_CH7_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_S 0 + +/** SOC_ETM_CH8_EVT_ID_REG register + * Channel8 event id register + */ +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) +/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch8_evt_id + */ +#define SOC_ETM_CH8_EVT_ID 0x0000007FU +#define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) +#define SOC_ETM_CH8_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH8_EVT_ID_S 0 + +/** SOC_ETM_CH8_TASK_ID_REG register + * Channel8 task id register + */ +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) +/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_task_id + */ +#define SOC_ETM_CH8_TASK_ID 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) +#define SOC_ETM_CH8_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_S 0 + +/** SOC_ETM_CH9_EVT_ID_REG register + * Channel9 event id register + */ +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) +/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch9_evt_id + */ +#define SOC_ETM_CH9_EVT_ID 0x0000007FU +#define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) +#define SOC_ETM_CH9_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH9_EVT_ID_S 0 + +/** SOC_ETM_CH9_TASK_ID_REG register + * Channel9 task id register + */ +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) +/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_task_id + */ +#define SOC_ETM_CH9_TASK_ID 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) +#define SOC_ETM_CH9_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_S 0 + +/** SOC_ETM_CH10_EVT_ID_REG register + * Channel10 event id register + */ +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) +/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch10_evt_id + */ +#define SOC_ETM_CH10_EVT_ID 0x0000007FU +#define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) +#define SOC_ETM_CH10_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH10_EVT_ID_S 0 + +/** SOC_ETM_CH10_TASK_ID_REG register + * Channel10 task id register + */ +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) +/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_task_id + */ +#define SOC_ETM_CH10_TASK_ID 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) +#define SOC_ETM_CH10_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_S 0 + +/** SOC_ETM_CH11_EVT_ID_REG register + * Channel11 event id register + */ +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) +/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch11_evt_id + */ +#define SOC_ETM_CH11_EVT_ID 0x0000007FU +#define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) +#define SOC_ETM_CH11_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH11_EVT_ID_S 0 + +/** SOC_ETM_CH11_TASK_ID_REG register + * Channel11 task id register + */ +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) +/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_task_id + */ +#define SOC_ETM_CH11_TASK_ID 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) +#define SOC_ETM_CH11_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_S 0 + +/** SOC_ETM_CH12_EVT_ID_REG register + * Channel12 event id register + */ +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) +/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch12_evt_id + */ +#define SOC_ETM_CH12_EVT_ID 0x0000007FU +#define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) +#define SOC_ETM_CH12_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH12_EVT_ID_S 0 + +/** SOC_ETM_CH12_TASK_ID_REG register + * Channel12 task id register + */ +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) +/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_task_id + */ +#define SOC_ETM_CH12_TASK_ID 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) +#define SOC_ETM_CH12_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_S 0 + +/** SOC_ETM_CH13_EVT_ID_REG register + * Channel13 event id register + */ +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) +/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch13_evt_id + */ +#define SOC_ETM_CH13_EVT_ID 0x0000007FU +#define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) +#define SOC_ETM_CH13_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH13_EVT_ID_S 0 + +/** SOC_ETM_CH13_TASK_ID_REG register + * Channel13 task id register + */ +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) +/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_task_id + */ +#define SOC_ETM_CH13_TASK_ID 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) +#define SOC_ETM_CH13_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_S 0 + +/** SOC_ETM_CH14_EVT_ID_REG register + * Channel14 event id register + */ +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) +/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch14_evt_id + */ +#define SOC_ETM_CH14_EVT_ID 0x0000007FU +#define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) +#define SOC_ETM_CH14_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH14_EVT_ID_S 0 + +/** SOC_ETM_CH14_TASK_ID_REG register + * Channel14 task id register + */ +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) +/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_task_id + */ +#define SOC_ETM_CH14_TASK_ID 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) +#define SOC_ETM_CH14_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_S 0 + +/** SOC_ETM_CH15_EVT_ID_REG register + * Channel15 event id register + */ +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) +/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch15_evt_id + */ +#define SOC_ETM_CH15_EVT_ID 0x0000007FU +#define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) +#define SOC_ETM_CH15_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH15_EVT_ID_S 0 + +/** SOC_ETM_CH15_TASK_ID_REG register + * Channel15 task id register + */ +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) +/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_task_id + */ +#define SOC_ETM_CH15_TASK_ID 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) +#define SOC_ETM_CH15_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_S 0 + +/** SOC_ETM_CH16_EVT_ID_REG register + * Channel16 event id register + */ +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) +/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch16_evt_id + */ +#define SOC_ETM_CH16_EVT_ID 0x0000007FU +#define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) +#define SOC_ETM_CH16_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH16_EVT_ID_S 0 + +/** SOC_ETM_CH16_TASK_ID_REG register + * Channel16 task id register + */ +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) +/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_task_id + */ +#define SOC_ETM_CH16_TASK_ID 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) +#define SOC_ETM_CH16_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_S 0 + +/** SOC_ETM_CH17_EVT_ID_REG register + * Channel17 event id register + */ +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) +/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch17_evt_id + */ +#define SOC_ETM_CH17_EVT_ID 0x0000007FU +#define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) +#define SOC_ETM_CH17_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH17_EVT_ID_S 0 + +/** SOC_ETM_CH17_TASK_ID_REG register + * Channel17 task id register + */ +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) +/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_task_id + */ +#define SOC_ETM_CH17_TASK_ID 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) +#define SOC_ETM_CH17_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_S 0 + +/** SOC_ETM_CH18_EVT_ID_REG register + * Channel18 event id register + */ +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) +/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch18_evt_id + */ +#define SOC_ETM_CH18_EVT_ID 0x0000007FU +#define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) +#define SOC_ETM_CH18_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH18_EVT_ID_S 0 + +/** SOC_ETM_CH18_TASK_ID_REG register + * Channel18 task id register + */ +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) +/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_task_id + */ +#define SOC_ETM_CH18_TASK_ID 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) +#define SOC_ETM_CH18_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_S 0 + +/** SOC_ETM_CH19_EVT_ID_REG register + * Channel19 event id register + */ +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) +/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch19_evt_id + */ +#define SOC_ETM_CH19_EVT_ID 0x0000007FU +#define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) +#define SOC_ETM_CH19_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH19_EVT_ID_S 0 + +/** SOC_ETM_CH19_TASK_ID_REG register + * Channel19 task id register + */ +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) +/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_task_id + */ +#define SOC_ETM_CH19_TASK_ID 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) +#define SOC_ETM_CH19_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_S 0 + +/** SOC_ETM_CH20_EVT_ID_REG register + * Channel20 event id register + */ +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) +/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch20_evt_id + */ +#define SOC_ETM_CH20_EVT_ID 0x0000007FU +#define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) +#define SOC_ETM_CH20_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH20_EVT_ID_S 0 + +/** SOC_ETM_CH20_TASK_ID_REG register + * Channel20 task id register + */ +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) +/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_task_id + */ +#define SOC_ETM_CH20_TASK_ID 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) +#define SOC_ETM_CH20_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_S 0 + +/** SOC_ETM_CH21_EVT_ID_REG register + * Channel21 event id register + */ +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) +/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch21_evt_id + */ +#define SOC_ETM_CH21_EVT_ID 0x0000007FU +#define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) +#define SOC_ETM_CH21_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH21_EVT_ID_S 0 + +/** SOC_ETM_CH21_TASK_ID_REG register + * Channel21 task id register + */ +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) +/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_task_id + */ +#define SOC_ETM_CH21_TASK_ID 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) +#define SOC_ETM_CH21_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_S 0 + +/** SOC_ETM_CH22_EVT_ID_REG register + * Channel22 event id register + */ +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) +/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch22_evt_id + */ +#define SOC_ETM_CH22_EVT_ID 0x0000007FU +#define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) +#define SOC_ETM_CH22_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH22_EVT_ID_S 0 + +/** SOC_ETM_CH22_TASK_ID_REG register + * Channel22 task id register + */ +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) +/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_task_id + */ +#define SOC_ETM_CH22_TASK_ID 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) +#define SOC_ETM_CH22_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_S 0 + +/** SOC_ETM_CH23_EVT_ID_REG register + * Channel23 event id register + */ +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) +/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch23_evt_id + */ +#define SOC_ETM_CH23_EVT_ID 0x0000007FU +#define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) +#define SOC_ETM_CH23_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH23_EVT_ID_S 0 + +/** SOC_ETM_CH23_TASK_ID_REG register + * Channel23 task id register + */ +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) +/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_task_id + */ +#define SOC_ETM_CH23_TASK_ID 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) +#define SOC_ETM_CH23_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_S 0 + +/** SOC_ETM_CH24_EVT_ID_REG register + * Channel24 event id register + */ +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) +/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch24_evt_id + */ +#define SOC_ETM_CH24_EVT_ID 0x0000007FU +#define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) +#define SOC_ETM_CH24_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH24_EVT_ID_S 0 + +/** SOC_ETM_CH24_TASK_ID_REG register + * Channel24 task id register + */ +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) +/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_task_id + */ +#define SOC_ETM_CH24_TASK_ID 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) +#define SOC_ETM_CH24_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_S 0 + +/** SOC_ETM_CH25_EVT_ID_REG register + * Channel25 event id register + */ +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) +/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch25_evt_id + */ +#define SOC_ETM_CH25_EVT_ID 0x0000007FU +#define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) +#define SOC_ETM_CH25_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH25_EVT_ID_S 0 + +/** SOC_ETM_CH25_TASK_ID_REG register + * Channel25 task id register + */ +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) +/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_task_id + */ +#define SOC_ETM_CH25_TASK_ID 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) +#define SOC_ETM_CH25_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_S 0 + +/** SOC_ETM_CH26_EVT_ID_REG register + * Channel26 event id register + */ +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) +/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch26_evt_id + */ +#define SOC_ETM_CH26_EVT_ID 0x0000007FU +#define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) +#define SOC_ETM_CH26_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH26_EVT_ID_S 0 + +/** SOC_ETM_CH26_TASK_ID_REG register + * Channel26 task id register + */ +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) +/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_task_id + */ +#define SOC_ETM_CH26_TASK_ID 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) +#define SOC_ETM_CH26_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_S 0 + +/** SOC_ETM_CH27_EVT_ID_REG register + * Channel27 event id register + */ +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) +/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch27_evt_id + */ +#define SOC_ETM_CH27_EVT_ID 0x0000007FU +#define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) +#define SOC_ETM_CH27_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH27_EVT_ID_S 0 + +/** SOC_ETM_CH27_TASK_ID_REG register + * Channel27 task id register + */ +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) +/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_task_id + */ +#define SOC_ETM_CH27_TASK_ID 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) +#define SOC_ETM_CH27_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_S 0 + +/** SOC_ETM_CH28_EVT_ID_REG register + * Channel28 event id register + */ +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) +/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch28_evt_id + */ +#define SOC_ETM_CH28_EVT_ID 0x0000007FU +#define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) +#define SOC_ETM_CH28_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH28_EVT_ID_S 0 + +/** SOC_ETM_CH28_TASK_ID_REG register + * Channel28 task id register + */ +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) +/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_task_id + */ +#define SOC_ETM_CH28_TASK_ID 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) +#define SOC_ETM_CH28_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_S 0 + +/** SOC_ETM_CH29_EVT_ID_REG register + * Channel29 event id register + */ +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) +/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch29_evt_id + */ +#define SOC_ETM_CH29_EVT_ID 0x0000007FU +#define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) +#define SOC_ETM_CH29_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH29_EVT_ID_S 0 + +/** SOC_ETM_CH29_TASK_ID_REG register + * Channel29 task id register + */ +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) +/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_task_id + */ +#define SOC_ETM_CH29_TASK_ID 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) +#define SOC_ETM_CH29_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_S 0 + +/** SOC_ETM_CH30_EVT_ID_REG register + * Channel30 event id register + */ +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) +/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch30_evt_id + */ +#define SOC_ETM_CH30_EVT_ID 0x0000007FU +#define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) +#define SOC_ETM_CH30_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH30_EVT_ID_S 0 + +/** SOC_ETM_CH30_TASK_ID_REG register + * Channel30 task id register + */ +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) +/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_task_id + */ +#define SOC_ETM_CH30_TASK_ID 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) +#define SOC_ETM_CH30_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_S 0 + +/** SOC_ETM_CH31_EVT_ID_REG register + * Channel31 event id register + */ +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) +/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch31_evt_id + */ +#define SOC_ETM_CH31_EVT_ID 0x0000007FU +#define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) +#define SOC_ETM_CH31_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH31_EVT_ID_S 0 + +/** SOC_ETM_CH31_TASK_ID_REG register + * Channel31 task id register + */ +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) +/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_task_id + */ +#define SOC_ETM_CH31_TASK_ID 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) +#define SOC_ETM_CH31_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_S 0 + +/** SOC_ETM_CH32_EVT_ID_REG register + * Channel32 event id register + */ +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) +/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch32_evt_id + */ +#define SOC_ETM_CH32_EVT_ID 0x0000007FU +#define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) +#define SOC_ETM_CH32_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH32_EVT_ID_S 0 + +/** SOC_ETM_CH32_TASK_ID_REG register + * Channel32 task id register + */ +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) +/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_task_id + */ +#define SOC_ETM_CH32_TASK_ID 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) +#define SOC_ETM_CH32_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_S 0 + +/** SOC_ETM_CH33_EVT_ID_REG register + * Channel33 event id register + */ +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) +/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch33_evt_id + */ +#define SOC_ETM_CH33_EVT_ID 0x0000007FU +#define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) +#define SOC_ETM_CH33_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH33_EVT_ID_S 0 + +/** SOC_ETM_CH33_TASK_ID_REG register + * Channel33 task id register + */ +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) +/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_task_id + */ +#define SOC_ETM_CH33_TASK_ID 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) +#define SOC_ETM_CH33_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_S 0 + +/** SOC_ETM_CH34_EVT_ID_REG register + * Channel34 event id register + */ +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) +/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch34_evt_id + */ +#define SOC_ETM_CH34_EVT_ID 0x0000007FU +#define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) +#define SOC_ETM_CH34_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH34_EVT_ID_S 0 + +/** SOC_ETM_CH34_TASK_ID_REG register + * Channel34 task id register + */ +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) +/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_task_id + */ +#define SOC_ETM_CH34_TASK_ID 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) +#define SOC_ETM_CH34_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_S 0 + +/** SOC_ETM_CH35_EVT_ID_REG register + * Channel35 event id register + */ +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) +/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch35_evt_id + */ +#define SOC_ETM_CH35_EVT_ID 0x0000007FU +#define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) +#define SOC_ETM_CH35_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH35_EVT_ID_S 0 + +/** SOC_ETM_CH35_TASK_ID_REG register + * Channel35 task id register + */ +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) +/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_task_id + */ +#define SOC_ETM_CH35_TASK_ID 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) +#define SOC_ETM_CH35_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_S 0 + +/** SOC_ETM_CH36_EVT_ID_REG register + * Channel36 event id register + */ +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) +/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch36_evt_id + */ +#define SOC_ETM_CH36_EVT_ID 0x0000007FU +#define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) +#define SOC_ETM_CH36_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH36_EVT_ID_S 0 + +/** SOC_ETM_CH36_TASK_ID_REG register + * Channel36 task id register + */ +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) +/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_task_id + */ +#define SOC_ETM_CH36_TASK_ID 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) +#define SOC_ETM_CH36_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_S 0 + +/** SOC_ETM_CH37_EVT_ID_REG register + * Channel37 event id register + */ +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) +/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch37_evt_id + */ +#define SOC_ETM_CH37_EVT_ID 0x0000007FU +#define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) +#define SOC_ETM_CH37_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH37_EVT_ID_S 0 + +/** SOC_ETM_CH37_TASK_ID_REG register + * Channel37 task id register + */ +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) +/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_task_id + */ +#define SOC_ETM_CH37_TASK_ID 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) +#define SOC_ETM_CH37_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_S 0 + +/** SOC_ETM_CH38_EVT_ID_REG register + * Channel38 event id register + */ +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) +/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch38_evt_id + */ +#define SOC_ETM_CH38_EVT_ID 0x0000007FU +#define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) +#define SOC_ETM_CH38_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH38_EVT_ID_S 0 + +/** SOC_ETM_CH38_TASK_ID_REG register + * Channel38 task id register + */ +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) +/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_task_id + */ +#define SOC_ETM_CH38_TASK_ID 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) +#define SOC_ETM_CH38_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_S 0 + +/** SOC_ETM_CH39_EVT_ID_REG register + * Channel39 event id register + */ +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) +/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch39_evt_id + */ +#define SOC_ETM_CH39_EVT_ID 0x0000007FU +#define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) +#define SOC_ETM_CH39_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH39_EVT_ID_S 0 + +/** SOC_ETM_CH39_TASK_ID_REG register + * Channel39 task id register + */ +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) +/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_task_id + */ +#define SOC_ETM_CH39_TASK_ID 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) +#define SOC_ETM_CH39_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_S 0 + +/** SOC_ETM_CH40_EVT_ID_REG register + * Channel40 event id register + */ +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) +/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch40_evt_id + */ +#define SOC_ETM_CH40_EVT_ID 0x0000007FU +#define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) +#define SOC_ETM_CH40_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH40_EVT_ID_S 0 + +/** SOC_ETM_CH40_TASK_ID_REG register + * Channel40 task id register + */ +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) +/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_task_id + */ +#define SOC_ETM_CH40_TASK_ID 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) +#define SOC_ETM_CH40_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_S 0 + +/** SOC_ETM_CH41_EVT_ID_REG register + * Channel41 event id register + */ +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) +/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch41_evt_id + */ +#define SOC_ETM_CH41_EVT_ID 0x0000007FU +#define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) +#define SOC_ETM_CH41_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH41_EVT_ID_S 0 + +/** SOC_ETM_CH41_TASK_ID_REG register + * Channel41 task id register + */ +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) +/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_task_id + */ +#define SOC_ETM_CH41_TASK_ID 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) +#define SOC_ETM_CH41_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_S 0 + +/** SOC_ETM_CH42_EVT_ID_REG register + * Channel42 event id register + */ +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) +/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch42_evt_id + */ +#define SOC_ETM_CH42_EVT_ID 0x0000007FU +#define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) +#define SOC_ETM_CH42_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH42_EVT_ID_S 0 + +/** SOC_ETM_CH42_TASK_ID_REG register + * Channel42 task id register + */ +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) +/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_task_id + */ +#define SOC_ETM_CH42_TASK_ID 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) +#define SOC_ETM_CH42_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_S 0 + +/** SOC_ETM_CH43_EVT_ID_REG register + * Channel43 event id register + */ +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) +/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch43_evt_id + */ +#define SOC_ETM_CH43_EVT_ID 0x0000007FU +#define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) +#define SOC_ETM_CH43_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH43_EVT_ID_S 0 + +/** SOC_ETM_CH43_TASK_ID_REG register + * Channel43 task id register + */ +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) +/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_task_id + */ +#define SOC_ETM_CH43_TASK_ID 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) +#define SOC_ETM_CH43_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_S 0 + +/** SOC_ETM_CH44_EVT_ID_REG register + * Channel44 event id register + */ +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) +/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch44_evt_id + */ +#define SOC_ETM_CH44_EVT_ID 0x0000007FU +#define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) +#define SOC_ETM_CH44_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH44_EVT_ID_S 0 + +/** SOC_ETM_CH44_TASK_ID_REG register + * Channel44 task id register + */ +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) +/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_task_id + */ +#define SOC_ETM_CH44_TASK_ID 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) +#define SOC_ETM_CH44_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_S 0 + +/** SOC_ETM_CH45_EVT_ID_REG register + * Channel45 event id register + */ +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) +/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch45_evt_id + */ +#define SOC_ETM_CH45_EVT_ID 0x0000007FU +#define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) +#define SOC_ETM_CH45_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH45_EVT_ID_S 0 + +/** SOC_ETM_CH45_TASK_ID_REG register + * Channel45 task id register + */ +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) +/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_task_id + */ +#define SOC_ETM_CH45_TASK_ID 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) +#define SOC_ETM_CH45_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_S 0 + +/** SOC_ETM_CH46_EVT_ID_REG register + * Channel46 event id register + */ +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) +/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch46_evt_id + */ +#define SOC_ETM_CH46_EVT_ID 0x0000007FU +#define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) +#define SOC_ETM_CH46_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH46_EVT_ID_S 0 + +/** SOC_ETM_CH46_TASK_ID_REG register + * Channel46 task id register + */ +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) +/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_task_id + */ +#define SOC_ETM_CH46_TASK_ID 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) +#define SOC_ETM_CH46_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_S 0 + +/** SOC_ETM_CH47_EVT_ID_REG register + * Channel47 event id register + */ +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) +/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch47_evt_id + */ +#define SOC_ETM_CH47_EVT_ID 0x0000007FU +#define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) +#define SOC_ETM_CH47_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH47_EVT_ID_S 0 + +/** SOC_ETM_CH47_TASK_ID_REG register + * Channel47 task id register + */ +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) +/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_task_id + */ +#define SOC_ETM_CH47_TASK_ID 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) +#define SOC_ETM_CH47_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_S 0 + +/** SOC_ETM_CH48_EVT_ID_REG register + * Channel48 event id register + */ +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) +/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch48_evt_id + */ +#define SOC_ETM_CH48_EVT_ID 0x0000007FU +#define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) +#define SOC_ETM_CH48_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH48_EVT_ID_S 0 + +/** SOC_ETM_CH48_TASK_ID_REG register + * Channel48 task id register + */ +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) +/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_task_id + */ +#define SOC_ETM_CH48_TASK_ID 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) +#define SOC_ETM_CH48_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_S 0 + +/** SOC_ETM_CH49_EVT_ID_REG register + * Channel49 event id register + */ +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) +/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [6:0]; default: 0; + * Configures ch49_evt_id + */ +#define SOC_ETM_CH49_EVT_ID 0x0000007FU +#define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) +#define SOC_ETM_CH49_EVT_ID_V 0x0000007FU +#define SOC_ETM_CH49_EVT_ID_S 0 + +/** SOC_ETM_CH49_TASK_ID_REG register + * Channel49 task id register + */ +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) +/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_task_id + */ +#define SOC_ETM_CH49_TASK_ID 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) +#define SOC_ETM_CH49_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_S 0 + +/** SOC_ETM_EVT_ST0_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S 31 + +/** SOC_ETM_EVT_ST0_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST1_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST (BIT(0)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S 0 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST (BIT(1)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S 1 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST (BIT(2)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S 2 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST (BIT(3)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S 5 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST (BIT(6)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S 6 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST (BIT(7)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S 7 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST (BIT(8)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S 8 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST (BIT(9)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S 9 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST (BIT(10)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S 10 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST (BIT(11)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S 11 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S 12 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S 13 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST (BIT(14)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S 14 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST (BIT(15)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S 15 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST (BIT(16)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S 16 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST (BIT(17)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S 17 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST (BIT(18)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S 18 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST (BIT(19)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S 19 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST (BIT(20)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S 20 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST (BIT(21)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S 21 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST (BIT(22)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S 22 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST (BIT(23)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S 23 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST (BIT(24)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S 24 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST (BIT(25)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S 25 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST (BIT(26)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S 26 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST (BIT(27)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S 27 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST (BIT(28)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S 28 +/** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST (BIT(29)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_M (SOC_ETM_ADC_EVT_STOPPED0_ST_V << SOC_ETM_ADC_EVT_STOPPED0_ST_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_S 29 +/** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST (BIT(30)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_M (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_S 30 +/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST (BIT(31)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_M (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_S 31 + +/** SOC_ETM_EVT_ST1_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S 0 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S 1 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S 2 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S 5 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S 6 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S 7 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S 8 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S 9 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S 10 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S 11 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S 12 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S 13 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S 14 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S 15 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(16)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S 16 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(17)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S 17 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(18)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S 18 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(19)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S 19 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR (BIT(20)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S 20 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR (BIT(21)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S 21 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR (BIT(22)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S 22 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR (BIT(23)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S 23 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR (BIT(24)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S 24 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR (BIT(25)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S 25 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR (BIT(26)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S 26 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR (BIT(27)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S 27 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR (BIT(28)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S 28 +/** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR (BIT(29)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_M (SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V << SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S 29 +/** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR (BIT(30)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S 30 +/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR (BIT(31)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST2_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) +/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST (BIT(0)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_M (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_S 0 +/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_M (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_S 1 +/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_M (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_S 2 +/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST (BIT(3)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_M (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_S 3 +/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST (BIT(4)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_M (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_S 4 +/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_M (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_S 5 +/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_M (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_S 6 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST (BIT(7)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S 7 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST (BIT(8)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_S 8 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST (BIT(9)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_S 9 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST (BIT(10)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S 10 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST (BIT(11)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S 11 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST (BIT(12)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_S 12 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST (BIT(13)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_S 13 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST (BIT(14)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S 14 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST (BIT(15)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S 15 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST (BIT(16)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S 16 +/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_HALT_ST (BIT(17)) +#define SOC_ETM_ULP_EVT_HALT_ST_M (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S) +#define SOC_ETM_ULP_EVT_HALT_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_S 17 +/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST (BIT(18)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_M (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_S 18 +/** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_TICK_ST (BIT(19)) +#define SOC_ETM_RTC_EVT_TICK_ST_M (SOC_ETM_RTC_EVT_TICK_ST_V << SOC_ETM_RTC_EVT_TICK_ST_S) +#define SOC_ETM_RTC_EVT_TICK_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_S 19 +/** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_OVF_ST (BIT(20)) +#define SOC_ETM_RTC_EVT_OVF_ST_M (SOC_ETM_RTC_EVT_OVF_ST_V << SOC_ETM_RTC_EVT_OVF_ST_S) +#define SOC_ETM_RTC_EVT_OVF_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_S 20 +/** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_CMP_ST (BIT(21)) +#define SOC_ETM_RTC_EVT_CMP_ST_M (SOC_ETM_RTC_EVT_CMP_ST_V << SOC_ETM_RTC_EVT_CMP_ST_S) +#define SOC_ETM_RTC_EVT_CMP_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_S 21 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST (BIT(22)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_S 22 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST (BIT(23)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_S 23 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST (BIT(24)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_S 24 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST (BIT(25)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S 25 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST (BIT(26)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S 26 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST (BIT(27)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S 27 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST (BIT(28)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S 28 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST (BIT(29)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S 29 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(30)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S 30 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST (BIT(31)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S 31 + +/** SOC_ETM_EVT_ST2_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) +/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR (BIT(0)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S 0 +/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S 1 +/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S 2 +/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR (BIT(3)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S 3 +/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR (BIT(4)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S 4 +/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S 5 +/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S 6 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR (BIT(7)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S 7 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR (BIT(8)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S 8 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR (BIT(9)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S 9 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(10)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S 10 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR (BIT(11)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S 11 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR (BIT(12)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S 12 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR (BIT(13)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S 13 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(14)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S 14 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR (BIT(15)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S 15 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR (BIT(16)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S 16 +/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_HALT_ST_CLR (BIT(17)) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S 17 +/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR (BIT(18)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S 18 +/** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_TICK_ST_CLR (BIT(19)) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_M (SOC_ETM_RTC_EVT_TICK_ST_CLR_V << SOC_ETM_RTC_EVT_TICK_ST_CLR_S) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_S 19 +/** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_OVF_ST_CLR (BIT(20)) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_M (SOC_ETM_RTC_EVT_OVF_ST_CLR_V << SOC_ETM_RTC_EVT_OVF_ST_CLR_S) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_S 20 +/** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_CMP_ST_CLR (BIT(21)) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_M (SOC_ETM_RTC_EVT_CMP_ST_CLR_V << SOC_ETM_RTC_EVT_CMP_ST_CLR_S) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_S 21 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR (BIT(22)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S 22 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR (BIT(23)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S 23 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR (BIT(24)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S 24 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(25)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S 25 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(26)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S 26 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(27)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S 27 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 28 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 29 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 30 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(31)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST3_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST (BIT(0)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S 0 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST (BIT(1)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S 1 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST (BIT(2)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_S 2 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST (BIT(3)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_S 3 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST (BIT(4)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_S 4 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST (BIT(5)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_S 5 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST (BIT(6)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_S 6 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST (BIT(7)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_S 7 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST (BIT(8)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S 8 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST (BIT(9)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S 9 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(10)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S 10 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST (BIT(11)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S 11 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST (BIT(12)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S 12 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(13)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S 13 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST (BIT(14)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S 14 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST (BIT(15)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S 15 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST (BIT(16)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S 16 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST (BIT(17)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S 17 + +/** SOC_ETM_EVT_ST3_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(0)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 0 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 1 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR (BIT(2)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S 2 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR (BIT(3)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S 3 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR (BIT(4)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S 4 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR (BIT(5)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S 5 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR (BIT(6)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S 6 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR (BIT(7)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S 7 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(8)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 8 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(9)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 9 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(10)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 10 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(11)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 11 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(12)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 12 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(13)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 13 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(14)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 14 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(15)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 15 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(16)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 16 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR (BIT(17)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S 17 + +/** SOC_ETM_TASK_ST0_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1c8) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S 31 + +/** SOC_ETM_TASK_ST0_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST1_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1d0) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S 1 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S 2 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S 3 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S 4 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S 5 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S 6 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S 11 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S 12 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S 13 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S 14 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S 17 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST (BIT(18)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S 18 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST (BIT(19)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S 19 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST (BIT(20)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S 20 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST (BIT(21)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S 21 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST (BIT(22)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S 22 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST (BIT(23)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S 27 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S 28 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S 29 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S 30 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S 31 + +/** SOC_ETM_TASK_ST1_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S 17 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR (BIT(18)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S 18 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR (BIT(19)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S 19 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR (BIT(20)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S 20 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR (BIT(21)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S 21 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR (BIT(22)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S 22 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR (BIT(23)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST2_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1d8) +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S 0 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S 1 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S 2 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S 15 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST (BIT(16)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S 16 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST (BIT(17)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S 17 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST (BIT(18)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S 18 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST (BIT(19)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S 19 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST (BIT(20)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S 20 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST (BIT(21)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S 21 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST (BIT(22)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S 22 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST (BIT(23)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S 23 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST (BIT(24)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S 24 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST (BIT(25)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S 25 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST (BIT(26)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S 26 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST (BIT(27)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S 27 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST (BIT(28)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S 28 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST (BIT(29)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S 29 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST (BIT(30)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S 30 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST (BIT(31)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S 31 + +/** SOC_ETM_TASK_ST2_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S 15 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR (BIT(16)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S 16 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR (BIT(17)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S 17 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(18)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S 18 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(19)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 19 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(20)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S 20 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR (BIT(21)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S 21 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR (BIT(22)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S 22 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(23)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S 23 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(24)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 24 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(25)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S 25 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR (BIT(26)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S 26 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR (BIT(27)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S 27 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(28)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S 28 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(29)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 29 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(30)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S 30 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR (BIT(31)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST3_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1e0) +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST (BIT(0)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S 0 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST (BIT(1)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S 1 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST (BIT(2)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S 2 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST (BIT(3)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S 3 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST (BIT(4)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 4 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(5)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 5 +/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_START0_ST (BIT(6)) +#define SOC_ETM_ADC_TASK_START0_ST_M (SOC_ETM_ADC_TASK_START0_ST_V << SOC_ETM_ADC_TASK_START0_ST_S) +#define SOC_ETM_ADC_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_S 6 +/** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_STOP0_ST (BIT(7)) +#define SOC_ETM_ADC_TASK_STOP0_ST_M (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_S 7 +/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START0_ST (BIT(8)) +#define SOC_ETM_REGDMA_TASK_START0_ST_M (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_S 8 +/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START1_ST (BIT(9)) +#define SOC_ETM_REGDMA_TASK_START1_ST_M (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_S 9 +/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START2_ST (BIT(10)) +#define SOC_ETM_REGDMA_TASK_START2_ST_M (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_S 10 +/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START3_ST (BIT(11)) +#define SOC_ETM_REGDMA_TASK_START3_ST_M (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_S 11 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST (BIT(12)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S 12 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST (BIT(13)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S 13 +/** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST (BIT(14)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_M (SOC_ETM_I2S0_TASK_START_RX_ST_V << SOC_ETM_I2S0_TASK_START_RX_ST_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_S 14 +/** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST (BIT(15)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_M (SOC_ETM_I2S0_TASK_START_TX_ST_V << SOC_ETM_I2S0_TASK_START_TX_ST_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_S 15 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST (BIT(16)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_S 16 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST (BIT(17)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_S 17 +/** SOC_ETM_I2S1_TASK_START_RX_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST (BIT(18)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_M (SOC_ETM_I2S1_TASK_START_RX_ST_V << SOC_ETM_I2S1_TASK_START_RX_ST_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_S 18 +/** SOC_ETM_I2S1_TASK_START_TX_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST (BIT(19)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_M (SOC_ETM_I2S1_TASK_START_TX_ST_V << SOC_ETM_I2S1_TASK_START_TX_ST_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_S 19 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST (BIT(20)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_S 20 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST (BIT(21)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_S 21 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST (BIT(22)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S 22 +/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST (BIT(23)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_M (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_S 23 +/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_START_ST (BIT(24)) +#define SOC_ETM_RTC_TASK_START_ST_M (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S) +#define SOC_ETM_RTC_TASK_START_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_S 24 +/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_STOP_ST (BIT(25)) +#define SOC_ETM_RTC_TASK_STOP_ST_M (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S) +#define SOC_ETM_RTC_TASK_STOP_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_S 25 +/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_CLR_ST (BIT(26)) +#define SOC_ETM_RTC_TASK_CLR_ST_M (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S) +#define SOC_ETM_RTC_TASK_CLR_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_S 26 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST (BIT(27)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S 27 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST (BIT(28)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_S 28 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST (BIT(29)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_S 29 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST (BIT(30)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_S 30 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST (BIT(31)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_S 31 + +/** SOC_ETM_TASK_ST3_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR (BIT(0)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S 0 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(1)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S 1 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(2)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 2 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(3)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S 3 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR (BIT(4)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 4 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(5)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 5 +/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_START0_ST_CLR (BIT(6)) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_M (SOC_ETM_ADC_TASK_START0_ST_CLR_V << SOC_ETM_ADC_TASK_START0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_CLR_S 6 +/** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR (BIT(7)) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S 7 +/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR (BIT(8)) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S 8 +/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR (BIT(9)) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S 9 +/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR (BIT(10)) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S 10 +/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR (BIT(11)) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S 11 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR (BIT(12)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S 12 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR (BIT(13)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S 13 +/** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR (BIT(14)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S 14 +/** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR (BIT(15)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S 15 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR (BIT(16)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S 16 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR (BIT(17)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S 17 +/** SOC_ETM_I2S1_TASK_START_RX_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR (BIT(18)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S 18 +/** SOC_ETM_I2S1_TASK_START_TX_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR (BIT(19)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S 19 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR (BIT(20)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S 20 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR (BIT(21)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S 21 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR (BIT(22)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S 22 +/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR (BIT(23)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S 23 +/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_START_ST_CLR (BIT(24)) +#define SOC_ETM_RTC_TASK_START_ST_CLR_M (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S) +#define SOC_ETM_RTC_TASK_START_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_CLR_S 24 +/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_STOP_ST_CLR (BIT(25)) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S 25 +/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_CLR_ST_CLR (BIT(26)) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S 26 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR (BIT(27)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S 27 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_S 28 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_S 29 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_S 30 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR (BIT(31)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST4_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1e8) +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST (BIT(0)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_S 0 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST (BIT(1)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_S 1 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST (BIT(2)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S 2 + +/** SOC_ETM_TASK_ST4_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR (BIT(0)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S 0 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S 1 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR (BIT(2)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S 2 + +/** SOC_ETM_CLK_EN_REG register + * ETM clock enable register + */ +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1f0) +/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define SOC_ETM_CLK_EN (BIT(0)) +#define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) +#define SOC_ETM_CLK_EN_V 0x00000001U +#define SOC_ETM_CLK_EN_S 0 + +/** SOC_ETM_DATE_REG register + * ETM date register + */ +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1f4) +/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36737361; + * Configures the version. + */ +#define SOC_ETM_DATE 0x0FFFFFFFU +#define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) +#define SOC_ETM_DATE_V 0x0FFFFFFFU +#define SOC_ETM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/soc_etm_source.h b/components/soc/esp32c61/include/soc/soc_etm_source.h new file mode 100644 index 0000000000..cd7bcec1a9 --- /dev/null +++ b/components/soc/esp32c61/include/soc/soc_etm_source.h @@ -0,0 +1,253 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define GPIO_EVT_ZERO_DET_POS0 25 +#define GPIO_EVT_ZERO_DET_NEG0 26 +#define GPIO_EVT_ZERO_DET_POS1 27 +#define GPIO_EVT_ZERO_DET_NEG1 28 +#define LEDC_EVT_DUTY_CHNG_END_CH0 29 +#define LEDC_EVT_DUTY_CHNG_END_CH1 30 +#define LEDC_EVT_DUTY_CHNG_END_CH2 31 +#define LEDC_EVT_DUTY_CHNG_END_CH3 32 +#define LEDC_EVT_DUTY_CHNG_END_CH4 33 +#define LEDC_EVT_DUTY_CHNG_END_CH5 34 +#define LEDC_EVT_OVF_CNT_PLS_CH0 35 +#define LEDC_EVT_OVF_CNT_PLS_CH1 36 +#define LEDC_EVT_OVF_CNT_PLS_CH2 37 +#define LEDC_EVT_OVF_CNT_PLS_CH3 38 +#define LEDC_EVT_OVF_CNT_PLS_CH4 39 +#define LEDC_EVT_OVF_CNT_PLS_CH5 40 +#define LEDC_EVT_TIME_OVF_TIMER0 41 +#define LEDC_EVT_TIME_OVF_TIMER1 42 +#define LEDC_EVT_TIME_OVF_TIMER2 43 +#define LEDC_EVT_TIME_OVF_TIMER3 44 +#define LEDC_EVT_TIMER0_CMP 45 +#define LEDC_EVT_TIMER1_CMP 46 +#define LEDC_EVT_TIMER2_CMP 47 +#define LEDC_EVT_TIMER3_CMP 48 +#define TG0_EVT_CNT_CMP_TIMER0 49 +#define TG0_EVT_CNT_CMP_TIMER1 50 +#define TG1_EVT_CNT_CMP_TIMER0 51 +#define TG1_EVT_CNT_CMP_TIMER1 52 +#define SYSTIMER_EVT_CNT_CMP0 53 +#define SYSTIMER_EVT_CNT_CMP1 54 +#define SYSTIMER_EVT_CNT_CMP2 55 +#define ADC_EVT_CONV_CMPLT0 56 +#define ADC_EVT_EQ_ABOVE_THRESH0 57 +#define ADC_EVT_EQ_ABOVE_THRESH1 58 +#define ADC_EVT_EQ_BELOW_THRESH0 59 +#define ADC_EVT_EQ_BELOW_THRESH1 60 +#define ADC_EVT_RESULT_DONE0 61 +#define ADC_EVT_STOPPED0 62 +#define ADC_EVT_STARTED0 63 +#define REGDMA_EVT_DONE0 64 +#define REGDMA_EVT_DONE1 65 +#define REGDMA_EVT_DONE2 66 +#define REGDMA_EVT_DONE3 67 +#define REGDMA_EVT_ERR0 68 +#define REGDMA_EVT_ERR1 69 +#define REGDMA_EVT_ERR2 70 +#define REGDMA_EVT_ERR3 71 +#define TMPSNSR_EVT_OVER_LIMIT 72 +#define I2S0_EVT_RX_DONE 73 +#define I2S0_EVT_TX_DONE 74 +#define I2S0_EVT_X_WORDS_RECEIVED 75 +#define I2S0_EVT_X_WORDS_SENT 76 +#define I2S1_EVT_RX_DONE 77 +#define I2S1_EVT_TX_DONE 78 +#define I2S1_EVT_X_WORDS_RECEIVED 79 +#define I2S1_EVT_X_WORDS_SENT 80 +#define ULP_EVT_ERR_INTR 81 +#define ULP_EVT_HALT 82 +#define ULP_EVT_START_INTR 83 +#define RTC_EVT_TICK 84 +#define RTC_EVT_OVF 85 +#define RTC_EVT_CMP 86 +#define GDMA_AHB_EVT_IN_DONE_CH0 87 +#define GDMA_AHB_EVT_IN_DONE_CH1 88 +#define GDMA_AHB_EVT_IN_DONE_CH2 89 +#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 90 +#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 91 +#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 92 +#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 93 +#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 94 +#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 95 +#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 96 +#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 97 +#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 98 +#define GDMA_AHB_EVT_OUT_DONE_CH0 99 +#define GDMA_AHB_EVT_OUT_DONE_CH1 100 +#define GDMA_AHB_EVT_OUT_DONE_CH2 101 +#define GDMA_AHB_EVT_OUT_EOF_CH0 102 +#define GDMA_AHB_EVT_OUT_EOF_CH1 103 +#define GDMA_AHB_EVT_OUT_EOF_CH2 104 +#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 105 +#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 106 +#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 107 +#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 108 +#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 109 +#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 110 +#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 111 +#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 112 +#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 113 +#define PMU_EVT_SLEEP_WEEKUP 114 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34 +#define LEDC_TASK_TIMER0_CAP 35 +#define LEDC_TASK_TIMER1_CAP 36 +#define LEDC_TASK_TIMER2_CAP 37 +#define LEDC_TASK_TIMER3_CAP 38 +#define LEDC_TASK_SIG_OUT_DIS_CH0 39 +#define LEDC_TASK_SIG_OUT_DIS_CH1 40 +#define LEDC_TASK_SIG_OUT_DIS_CH2 41 +#define LEDC_TASK_SIG_OUT_DIS_CH3 42 +#define LEDC_TASK_SIG_OUT_DIS_CH4 43 +#define LEDC_TASK_SIG_OUT_DIS_CH5 44 +#define LEDC_TASK_OVF_CNT_RST_CH0 45 +#define LEDC_TASK_OVF_CNT_RST_CH1 46 +#define LEDC_TASK_OVF_CNT_RST_CH2 47 +#define LEDC_TASK_OVF_CNT_RST_CH3 48 +#define LEDC_TASK_OVF_CNT_RST_CH4 49 +#define LEDC_TASK_OVF_CNT_RST_CH5 50 +#define LEDC_TASK_TIMER0_RST 51 +#define LEDC_TASK_TIMER1_RST 52 +#define LEDC_TASK_TIMER2_RST 53 +#define LEDC_TASK_TIMER3_RST 54 +#define LEDC_TASK_TIMER0_RESUME 55 +#define LEDC_TASK_TIMER1_RESUME 56 +#define LEDC_TASK_TIMER2_RESUME 57 +#define LEDC_TASK_TIMER3_RESUME 58 +#define LEDC_TASK_TIMER0_PAUSE 59 +#define LEDC_TASK_TIMER1_PAUSE 60 +#define LEDC_TASK_TIMER2_PAUSE 61 +#define LEDC_TASK_TIMER3_PAUSE 62 +#define LEDC_TASK_GAMMA_RESTART_CH0 63 +#define LEDC_TASK_GAMMA_RESTART_CH1 64 +#define LEDC_TASK_GAMMA_RESTART_CH2 65 +#define LEDC_TASK_GAMMA_RESTART_CH3 66 +#define LEDC_TASK_GAMMA_RESTART_CH4 67 +#define LEDC_TASK_GAMMA_RESTART_CH5 68 +#define LEDC_TASK_GAMMA_PAUSE_CH0 69 +#define LEDC_TASK_GAMMA_PAUSE_CH1 70 +#define LEDC_TASK_GAMMA_PAUSE_CH2 71 +#define LEDC_TASK_GAMMA_PAUSE_CH3 72 +#define LEDC_TASK_GAMMA_PAUSE_CH4 73 +#define LEDC_TASK_GAMMA_PAUSE_CH5 74 +#define LEDC_TASK_GAMMA_RESUME_CH0 75 +#define LEDC_TASK_GAMMA_RESUME_CH1 76 +#define LEDC_TASK_GAMMA_RESUME_CH2 77 +#define LEDC_TASK_GAMMA_RESUME_CH3 78 +#define LEDC_TASK_GAMMA_RESUME_CH4 79 +#define LEDC_TASK_GAMMA_RESUME_CH5 80 +#define TG0_TASK_CNT_START_TIMER0 81 +#define TG0_TASK_ALARM_START_TIMER0 82 +#define TG0_TASK_CNT_STOP_TIMER0 83 +#define TG0_TASK_CNT_RELOAD_TIMER0 84 +#define TG0_TASK_CNT_CAP_TIMER0 85 +#define TG0_TASK_CNT_START_TIMER1 86 +#define TG0_TASK_ALARM_START_TIMER1 87 +#define TG0_TASK_CNT_STOP_TIMER1 88 +#define TG0_TASK_CNT_RELOAD_TIMER1 89 +#define TG0_TASK_CNT_CAP_TIMER1 90 +#define TG1_TASK_CNT_START_TIMER0 91 +#define TG1_TASK_ALARM_START_TIMER0 92 +#define TG1_TASK_CNT_STOP_TIMER0 93 +#define TG1_TASK_CNT_RELOAD_TIMER0 94 +#define TG1_TASK_CNT_CAP_TIMER0 95 +#define TG1_TASK_CNT_START_TIMER1 96 +#define TG1_TASK_ALARM_START_TIMER1 97 +#define TG1_TASK_CNT_STOP_TIMER1 98 +#define TG1_TASK_CNT_RELOAD_TIMER1 99 +#define TG1_TASK_CNT_CAP_TIMER1 100 +#define ADC_TASK_SAMPLE0 101 +#define ADC_TASK_SAMPLE1 102 +#define ADC_TASK_START0 103 +#define ADC_TASK_STOP0 104 +#define REGDMA_TASK_START0 105 +#define REGDMA_TASK_START1 106 +#define REGDMA_TASK_START2 107 +#define REGDMA_TASK_START3 108 +#define TMPSNSR_TASK_START_SAMPLE 109 +#define TMPSNSR_TASK_STOP_SAMPLE 110 +#define I2S0_TASK_START_RX 111 +#define I2S0_TASK_START_TX 112 +#define I2S0_TASK_STOP_RX 113 +#define I2S0_TASK_STOP_TX 114 +#define I2S1_TASK_START_RX 115 +#define I2S1_TASK_START_TX 116 +#define I2S1_TASK_STOP_RX 117 +#define I2S1_TASK_STOP_TX 118 +#define ULP_TASK_WAKEUP_CPU 119 +#define ULP_TASK_INT_CPU 120 +#define RTC_TASK_START 121 +#define RTC_TASK_STOP 122 +#define RTC_TASK_CLR 123 +#define RTC_TASK_TRIGGERFLW 124 +#define GDMA_AHB_TASK_IN_START_CH0 125 +#define GDMA_AHB_TASK_IN_START_CH1 126 +#define GDMA_AHB_TASK_IN_START_CH2 127 +#define GDMA_AHB_TASK_OUT_START_CH0 128 +#define GDMA_AHB_TASK_OUT_START_CH1 129 +#define GDMA_AHB_TASK_OUT_START_CH2 130 +#define PMU_TASK_SLEEP_REQ 131 diff --git a/components/soc/esp32c61/include/soc/soc_etm_struct.h b/components/soc/esp32c61/include/soc/soc_etm_struct.h new file mode 100644 index 0000000000..464ab7f33e --- /dev/null +++ b/components/soc/esp32c61/include/soc/soc_etm_struct.h @@ -0,0 +1,3301 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status register */ +/** Type of ch_ena_ad0 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_enabled0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled0:1; + /** ch_enabled1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled1:1; + /** ch_enabled2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled2:1; + /** ch_enabled3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled3:1; + /** ch_enabled4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled4:1; + /** ch_enabled5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled5:1; + /** ch_enabled6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled6:1; + /** ch_enabled7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled7:1; + /** ch_enabled8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled8:1; + /** ch_enabled9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled9:1; + /** ch_enabled10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled10:1; + /** ch_enabled11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled11:1; + /** ch_enabled12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled12:1; + /** ch_enabled13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled13:1; + /** ch_enabled14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled14:1; + /** ch_enabled15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled15:1; + /** ch_enabled16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled16:1; + /** ch_enabled17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled17:1; + /** ch_enabled18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled18:1; + /** ch_enabled19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled19:1; + /** ch_enabled20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled20:1; + /** ch_enabled21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled21:1; + /** ch_enabled22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled22:1; + /** ch_enabled23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled23:1; + /** ch_enabled24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled24:1; + /** ch_enabled25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled25:1; + /** ch_enabled26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled26:1; + /** ch_enabled27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled27:1; + /** ch_enabled28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled28:1; + /** ch_enabled29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled29:1; + /** ch_enabled30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled30:1; + /** ch_enabled31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_reg_t; + +/** Type of ch_ena_ad1 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_enabled32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled32:1; + /** ch_enabled33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled33:1; + /** ch_enabled34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled34:1; + /** ch_enabled35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled35:1; + /** ch_enabled36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled36:1; + /** ch_enabled37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled37:1; + /** ch_enabled38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled38:1; + /** ch_enabled39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled39:1; + /** ch_enabled40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled40:1; + /** ch_enabled41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled41:1; + /** ch_enabled42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled42:1; + /** ch_enabled43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled43:1; + /** ch_enabled44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled44:1; + /** ch_enabled45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled45:1; + /** ch_enabled46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled46:1; + /** ch_enabled47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled47:1; + /** ch_enabled48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled48:1; + /** ch_enabled49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_reg_t; + +/** Type of evt_st0 register + * Events trigger status register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_rise_edge_st:1; + /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_rise_edge_st:1; + /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_rise_edge_st:1; + /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_rise_edge_st:1; + /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_rise_edge_st:1; + /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_rise_edge_st:1; + /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_rise_edge_st:1; + /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_rise_edge_st:1; + /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_fall_edge_st:1; + /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_fall_edge_st:1; + /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_fall_edge_st:1; + /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_fall_edge_st:1; + /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_fall_edge_st:1; + /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_fall_edge_st:1; + /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_fall_edge_st:1; + /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_fall_edge_st:1; + /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_any_edge_st:1; + /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_any_edge_st:1; + /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_any_edge_st:1; + /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_any_edge_st:1; + /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_any_edge_st:1; + /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_any_edge_st:1; + /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_any_edge_st:1; + /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_any_edge_st:1; + /** gpio_evt_zero_det_pos0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_pos0_st:1; + /** gpio_evt_zero_det_neg0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_neg0_st:1; + /** gpio_evt_zero_det_pos1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_pos1_st:1; + /** gpio_evt_zero_det_neg1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_neg1_st:1; + /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch0_st:1; + /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch1_st:1; + /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch2_st:1; + /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch3_st:1; + }; + uint32_t val; +} soc_etm_evt_st0_reg_t; + +/** Type of evt_st1 register + * Events trigger status register + */ +typedef union { + struct { + /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch4_st:1; + /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch5_st:1; + /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1; + /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1; + /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1; + /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1; + /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1; + /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1; + /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer0_st:1; + /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer1_st:1; + /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer2_st:1; + /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer3_st:1; + /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer0_cmp_st:1; + /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer1_cmp_st:1; + /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer2_cmp_st:1; + /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer3_cmp_st:1; + /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer0_st:1; + /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer1_st:1; + /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer0_st:1; + /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer1_st:1; + /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp0_st:1; + /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp1_st:1; + /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp2_st:1; + /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_conv_cmplt0_st:1; + /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh0_st:1; + /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh1_st:1; + /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh0_st:1; + /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh1_st:1; + /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_result_done0_st:1; + /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_stopped0_st:1; + /** adc_evt_started0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_started0_st:1; + /** regdma_evt_done0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done0_st:1; + }; + uint32_t val; +} soc_etm_evt_st1_reg_t; + +/** Type of evt_st2 register + * Events trigger status register + */ +typedef union { + struct { + /** regdma_evt_done1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done1_st:1; + /** regdma_evt_done2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done2_st:1; + /** regdma_evt_done3_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done3_st:1; + /** regdma_evt_err0_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err0_st:1; + /** regdma_evt_err1_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err1_st:1; + /** regdma_evt_err2_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err2_st:1; + /** regdma_evt_err3_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err3_st:1; + /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_evt_over_limit_st:1; + /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_rx_done_st:1; + /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_tx_done_st:1; + /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_received_st:1; + /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_sent_st:1; + /** i2s1_evt_rx_done_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_rx_done_st:1; + /** i2s1_evt_tx_done_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_tx_done_st:1; + /** i2s1_evt_x_words_received_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_x_words_received_st:1; + /** i2s1_evt_x_words_sent_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_x_words_sent_st:1; + /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_err_intr_st:1; + /** ulp_evt_halt_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_halt_st:1; + /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_start_intr_st:1; + /** rtc_evt_tick_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_tick_st:1; + /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_ovf_st:1; + /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_cmp_st:1; + /** gdma_ahb_evt_in_done_ch0_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_in_done_ch0_st:1; + /** gdma_ahb_evt_in_done_ch1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_in_done_ch1_st:1; + /** gdma_ahb_evt_in_done_ch2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_in_done_ch2_st:1; + /** gdma_ahb_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch0_st:1; + /** gdma_ahb_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch1_st:1; + /** gdma_ahb_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch2_st:1; + /** gdma_ahb_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch0_st:1; + /** gdma_ahb_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch1_st:1; + /** gdma_ahb_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch2_st:1; + /** gdma_ahb_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch0_st:1; + }; + uint32_t val; +} soc_etm_evt_st2_reg_t; + +/** Type of evt_st3 register + * Events trigger status register + */ +typedef union { + struct { + /** gdma_ahb_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch1_st:1; + /** gdma_ahb_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch2_st:1; + /** gdma_ahb_evt_out_done_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_out_done_ch0_st:1; + /** gdma_ahb_evt_out_done_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_out_done_ch1_st:1; + /** gdma_ahb_evt_out_done_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_out_done_ch2_st:1; + /** gdma_ahb_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_out_eof_ch0_st:1; + /** gdma_ahb_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_out_eof_ch1_st:1; + /** gdma_ahb_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_ahb_evt_out_eof_ch2_st:1; + /** gdma_ahb_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_total_eof_ch0_st:1; + /** gdma_ahb_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_total_eof_ch1_st:1; + /** gdma_ahb_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_total_eof_ch2_st:1; + /** gdma_ahb_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch0_st:1; + /** gdma_ahb_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch1_st:1; + /** gdma_ahb_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch2_st:1; + /** gdma_ahb_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch0_st:1; + /** gdma_ahb_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch1_st:1; + /** gdma_ahb_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch2_st:1; + /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_evt_sleep_weekup_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_evt_st3_reg_t; + +/** Type of task_st0 register + * Tasks trigger status register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_set_st:1; + /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_set_st:1; + /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_set_st:1; + /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_set_st:1; + /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_set_st:1; + /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_set_st:1; + /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_set_st:1; + /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_set_st:1; + /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_clear_st:1; + /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_clear_st:1; + /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_clear_st:1; + /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_clear_st:1; + /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_clear_st:1; + /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_clear_st:1; + /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_clear_st:1; + /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_clear_st:1; + /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_toggle_st:1; + /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_toggle_st:1; + /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_toggle_st:1; + /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_toggle_st:1; + /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_toggle_st:1; + /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_toggle_st:1; + /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_toggle_st:1; + /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_toggle_st:1; + /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer0_res_update_st:1; + /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer1_res_update_st:1; + /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer2_res_update_st:1; + /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer3_res_update_st:1; + /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch0_st:1; + /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch1_st:1; + /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch2_st:1; + /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch3_st:1; + }; + uint32_t val; +} soc_etm_task_st0_reg_t; + +/** Type of task_st1 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch4_st:1; + /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch5_st:1; + /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_cap_st:1; + /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_cap_st:1; + /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_cap_st:1; + /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_cap_st:1; + /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch0_st:1; + /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch1_st:1; + /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch2_st:1; + /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch3_st:1; + /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch4_st:1; + /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch5_st:1; + /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st:1; + /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st:1; + /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st:1; + /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st:1; + /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st:1; + /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st:1; + /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_rst_st:1; + /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_rst_st:1; + /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_rst_st:1; + /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_rst_st:1; + /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_resume_st:1; + /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_resume_st:1; + /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_resume_st:1; + /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_resume_st:1; + /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_pause_st:1; + /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_pause_st:1; + /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_pause_st:1; + /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_pause_st:1; + /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch0_st:1; + /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch1_st:1; + }; + uint32_t val; +} soc_etm_task_st1_reg_t; + +/** Type of task_st2 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch2_st:1; + /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch3_st:1; + /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch4_st:1; + /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch5_st:1; + /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch0_st:1; + /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch1_st:1; + /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch2_st:1; + /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch3_st:1; + /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch4_st:1; + /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch5_st:1; + /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch0_st:1; + /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch1_st:1; + /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch2_st:1; + /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch3_st:1; + /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch4_st:1; + /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch5_st:1; + /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer0_st:1; + /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer0_st:1; + /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer0_st:1; + /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer0_st:1; + /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer0_st:1; + /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer1_st:1; + /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer1_st:1; + /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer1_st:1; + /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer1_st:1; + /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer1_st:1; + /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer0_st:1; + /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer0_st:1; + /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer0_st:1; + /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer0_st:1; + /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer0_st:1; + /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer1_st:1; + }; + uint32_t val; +} soc_etm_task_st2_reg_t; + +/** Type of task_st3 register + * Tasks trigger status register + */ +typedef union { + struct { + /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer1_st:1; + /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer1_st:1; + /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer1_st:1; + /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer1_st:1; + /** adc_task_sample0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample0_st:1; + /** adc_task_sample1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample1_st:1; + /** adc_task_start0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_start0_st:1; + /** adc_task_stop0_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_stop0_st:1; + /** regdma_task_start0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start0_st:1; + /** regdma_task_start1_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start1_st:1; + /** regdma_task_start2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start2_st:1; + /** regdma_task_start3_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start3_st:1; + /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_start_sample_st:1; + /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_stop_sample_st:1; + /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_rx_st:1; + /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_tx_st:1; + /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_rx_st:1; + /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_tx_st:1; + /** i2s1_task_start_rx_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_start_rx_st:1; + /** i2s1_task_start_tx_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_start_tx_st:1; + /** i2s1_task_stop_rx_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_stop_rx_st:1; + /** i2s1_task_stop_tx_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_stop_tx_st:1; + /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_wakeup_cpu_st:1; + /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_int_cpu_st:1; + /** rtc_task_start_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_start_st:1; + /** rtc_task_stop_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_stop_st:1; + /** rtc_task_clr_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_clr_st:1; + /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_triggerflw_st:1; + /** gdma_ahb_task_in_start_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_task_in_start_ch0_st:1; + /** gdma_ahb_task_in_start_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_task_in_start_ch1_st:1; + /** gdma_ahb_task_in_start_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_task_in_start_ch2_st:1; + /** gdma_ahb_task_out_start_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_task_out_start_ch0_st:1; + }; + uint32_t val; +} soc_etm_task_st3_reg_t; + +/** Type of task_st4 register + * Tasks trigger status register + */ +typedef union { + struct { + /** gdma_ahb_task_out_start_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_task_out_start_ch1_st:1; + /** gdma_ahb_task_out_start_ch2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_ahb_task_out_start_ch2_st:1; + /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_task_sleep_req_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} soc_etm_task_st4_reg_t; + + +/** Group: Configuration Register */ +/** Type of ch_ena_ad0_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_enable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable0:1; + /** ch_enable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable1:1; + /** ch_enable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable2:1; + /** ch_enable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable3:1; + /** ch_enable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable4:1; + /** ch_enable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable5:1; + /** ch_enable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable6:1; + /** ch_enable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable7:1; + /** ch_enable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable8:1; + /** ch_enable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable9:1; + /** ch_enable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable10:1; + /** ch_enable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable11:1; + /** ch_enable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable12:1; + /** ch_enable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable13:1; + /** ch_enable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable14:1; + /** ch_enable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable15:1; + /** ch_enable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable16:1; + /** ch_enable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable17:1; + /** ch_enable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable18:1; + /** ch_enable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable19:1; + /** ch_enable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable20:1; + /** ch_enable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable21:1; + /** ch_enable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable22:1; + /** ch_enable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable23:1; + /** ch_enable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable24:1; + /** ch_enable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable25:1; + /** ch_enable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable26:1; + /** ch_enable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable27:1; + /** ch_enable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable28:1; + /** ch_enable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable29:1; + /** ch_enable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable30:1; + /** ch_enable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_set_reg_t; + +/** Type of ch_ena_ad0_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_disable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable0:1; + /** ch_disable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable1:1; + /** ch_disable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable2:1; + /** ch_disable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable3:1; + /** ch_disable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable4:1; + /** ch_disable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable5:1; + /** ch_disable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable6:1; + /** ch_disable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable7:1; + /** ch_disable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable8:1; + /** ch_disable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable9:1; + /** ch_disable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable10:1; + /** ch_disable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable11:1; + /** ch_disable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable12:1; + /** ch_disable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable13:1; + /** ch_disable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable14:1; + /** ch_disable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable15:1; + /** ch_disable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable16:1; + /** ch_disable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable17:1; + /** ch_disable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable18:1; + /** ch_disable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable19:1; + /** ch_disable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable20:1; + /** ch_disable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable21:1; + /** ch_disable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable22:1; + /** ch_disable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable23:1; + /** ch_disable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable24:1; + /** ch_disable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable25:1; + /** ch_disable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable26:1; + /** ch_disable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable27:1; + /** ch_disable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable28:1; + /** ch_disable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable29:1; + /** ch_disable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable30:1; + /** ch_disable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_clr_reg_t; + +/** Type of ch_ena_ad1_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_enable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable32:1; + /** ch_enable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable33:1; + /** ch_enable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable34:1; + /** ch_enable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable35:1; + /** ch_enable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable36:1; + /** ch_enable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable37:1; + /** ch_enable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable38:1; + /** ch_enable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable39:1; + /** ch_enable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable40:1; + /** ch_enable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable41:1; + /** ch_enable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable42:1; + /** ch_enable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable43:1; + /** ch_enable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable44:1; + /** ch_enable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable45:1; + /** ch_enable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable46:1; + /** ch_enable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable47:1; + /** ch_enable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable48:1; + /** ch_enable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_set_reg_t; + +/** Type of ch_ena_ad1_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_disable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable32:1; + /** ch_disable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable33:1; + /** ch_disable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable34:1; + /** ch_disable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable35:1; + /** ch_disable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable36:1; + /** ch_disable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable37:1; + /** ch_disable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable38:1; + /** ch_disable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable39:1; + /** ch_disable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable40:1; + /** ch_disable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable41:1; + /** ch_disable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable42:1; + /** ch_disable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable43:1; + /** ch_disable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable44:1; + /** ch_disable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable45:1; + /** ch_disable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable46:1; + /** ch_disable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable47:1; + /** ch_disable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable48:1; + /** ch_disable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_clr_reg_t; + +/** Type of chn_evt_id register + * Channeln event id register + */ +typedef union { + struct { + /** chn_evt_id : R/W; bitpos: [6:0]; default: 0; + * Configures chn_evt_id + */ + uint32_t chn_evt_id:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} soc_etm_chn_evt_id_reg_t; + +/** Type of chn_task_id register + * Channeln task id register + */ +typedef union { + struct { + /** chn_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures chn_task_id + */ + uint32_t chn_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_chn_task_id_reg_t; + +/** Type of evt_st0_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_rise_edge_st_clr:1; + /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_rise_edge_st_clr:1; + /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_rise_edge_st_clr:1; + /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_rise_edge_st_clr:1; + /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_rise_edge_st_clr:1; + /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_rise_edge_st_clr:1; + /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_rise_edge_st_clr:1; + /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_rise_edge_st_clr:1; + /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_fall_edge_st_clr:1; + /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_fall_edge_st_clr:1; + /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_fall_edge_st_clr:1; + /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_fall_edge_st_clr:1; + /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_fall_edge_st_clr:1; + /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_fall_edge_st_clr:1; + /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_fall_edge_st_clr:1; + /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_fall_edge_st_clr:1; + /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_any_edge_st_clr:1; + /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_any_edge_st_clr:1; + /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_any_edge_st_clr:1; + /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_any_edge_st_clr:1; + /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_any_edge_st_clr:1; + /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_any_edge_st_clr:1; + /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_any_edge_st_clr:1; + /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_any_edge_st_clr:1; + /** gpio_evt_zero_det_pos0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_pos0_st_clr:1; + /** gpio_evt_zero_det_neg0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_neg0_st_clr:1; + /** gpio_evt_zero_det_pos1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_pos1_st_clr:1; + /** gpio_evt_zero_det_neg1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_neg1_st_clr:1; + /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1; + /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1; + /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1; + /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st0_clr_reg_t; + +/** Type of evt_st1_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1; + /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1; + /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer0_st_clr:1; + /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer1_st_clr:1; + /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer2_st_clr:1; + /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer3_st_clr:1; + /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer0_cmp_st_clr:1; + /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer1_cmp_st_clr:1; + /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer2_cmp_st_clr:1; + /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer3_cmp_st_clr:1; + /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1; + /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1; + /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1; + /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1; + /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp0_st_clr:1; + /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp1_st_clr:1; + /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp2_st_clr:1; + /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t adc_evt_conv_cmplt0_st_clr:1; + /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh0_st_clr:1; + /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh1_st_clr:1; + /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh0_st_clr:1; + /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh1_st_clr:1; + /** adc_evt_result_done0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_result_done0_st_clr:1; + /** adc_evt_stopped0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_stopped0_st_clr:1; + /** adc_evt_started0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_started0_st_clr:1; + /** regdma_evt_done0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done0_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st1_clr_reg_t; + +/** Type of evt_st2_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** regdma_evt_done1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done1_st_clr:1; + /** regdma_evt_done2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done2_st_clr:1; + /** regdma_evt_done3_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done3_st_clr:1; + /** regdma_evt_err0_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err0_st_clr:1; + /** regdma_evt_err1_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err1_st_clr:1; + /** regdma_evt_err2_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err2_st_clr:1; + /** regdma_evt_err3_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err3_st_clr:1; + /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_evt_over_limit_st_clr:1; + /** i2s0_evt_rx_done_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_rx_done_st_clr:1; + /** i2s0_evt_tx_done_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_tx_done_st_clr:1; + /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_received_st_clr:1; + /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_sent_st_clr:1; + /** i2s1_evt_rx_done_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s1_evt_rx_done_st_clr:1; + /** i2s1_evt_tx_done_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s1_evt_tx_done_st_clr:1; + /** i2s1_evt_x_words_received_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s1_evt_x_words_received_st_clr:1; + /** i2s1_evt_x_words_sent_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s1_evt_x_words_sent_st_clr:1; + /** ulp_evt_err_intr_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_err_intr_st_clr:1; + /** ulp_evt_halt_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_halt_st_clr:1; + /** ulp_evt_start_intr_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_evt_start_intr_st_clr:1; + /** rtc_evt_tick_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_tick_st_clr:1; + /** rtc_evt_ovf_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_ovf_st_clr:1; + /** rtc_evt_cmp_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_cmp_st_clr:1; + /** gdma_ahb_evt_in_done_ch0_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_done_ch0_st_clr:1; + /** gdma_ahb_evt_in_done_ch1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_done_ch1_st_clr:1; + /** gdma_ahb_evt_in_done_ch2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_done_ch2_st_clr:1; + /** gdma_ahb_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch0_st_clr:1; + /** gdma_ahb_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch1_st_clr:1; + /** gdma_ahb_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch2_st_clr:1; + /** gdma_ahb_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch0_st_clr:1; + /** gdma_ahb_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch1_st_clr:1; + /** gdma_ahb_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch2_st_clr:1; + /** gdma_ahb_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch0_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st2_clr_reg_t; + +/** Type of evt_st3_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gdma_ahb_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch1_st_clr:1; + /** gdma_ahb_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch2_st_clr:1; + /** gdma_ahb_evt_out_done_ch0_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_done_ch0_st_clr:1; + /** gdma_ahb_evt_out_done_ch1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_done_ch1_st_clr:1; + /** gdma_ahb_evt_out_done_ch2_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_done_ch2_st_clr:1; + /** gdma_ahb_evt_out_eof_ch0_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_eof_ch0_st_clr:1; + /** gdma_ahb_evt_out_eof_ch1_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_eof_ch1_st_clr:1; + /** gdma_ahb_evt_out_eof_ch2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_eof_ch2_st_clr:1; + /** gdma_ahb_evt_out_total_eof_ch0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_total_eof_ch0_st_clr:1; + /** gdma_ahb_evt_out_total_eof_ch1_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_total_eof_ch1_st_clr:1; + /** gdma_ahb_evt_out_total_eof_ch2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_total_eof_ch2_st_clr:1; + /** gdma_ahb_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch0_st_clr:1; + /** gdma_ahb_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch1_st_clr:1; + /** gdma_ahb_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch2_st_clr:1; + /** gdma_ahb_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch0_st_clr:1; + /** gdma_ahb_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch1_st_clr:1; + /** gdma_ahb_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch2_st_clr:1; + /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pmu_evt_sleep_weekup_st_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_evt_st3_clr_reg_t; + +/** Type of task_st0_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_set_st_clr:1; + /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_set_st_clr:1; + /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_set_st_clr:1; + /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_set_st_clr:1; + /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_set_st_clr:1; + /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_set_st_clr:1; + /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_set_st_clr:1; + /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_set_st_clr:1; + /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_clear_st_clr:1; + /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_clear_st_clr:1; + /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_clear_st_clr:1; + /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_clear_st_clr:1; + /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_clear_st_clr:1; + /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_clear_st_clr:1; + /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_clear_st_clr:1; + /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_clear_st_clr:1; + /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch0_toggle_st_clr:1; + /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch1_toggle_st_clr:1; + /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch2_toggle_st_clr:1; + /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch3_toggle_st_clr:1; + /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch4_toggle_st_clr:1; + /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch5_toggle_st_clr:1; + /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch6_toggle_st_clr:1; + /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch7_toggle_st_clr:1; + /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_res_update_st_clr:1; + /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_res_update_st_clr:1; + /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_res_update_st_clr:1; + /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_res_update_st_clr:1; + /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch0_st_clr:1; + /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch1_st_clr:1; + /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch2_st_clr:1; + /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch3_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st0_clr_reg_t; + +/** Type of task_st1_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch4_st_clr:1; + /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch5_st_clr:1; + /** ledc_task_timer0_cap_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_cap_st_clr:1; + /** ledc_task_timer1_cap_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_cap_st_clr:1; + /** ledc_task_timer2_cap_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_cap_st_clr:1; + /** ledc_task_timer3_cap_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_cap_st_clr:1; + /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch0_st_clr:1; + /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch1_st_clr:1; + /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch2_st_clr:1; + /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch3_st_clr:1; + /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch4_st_clr:1; + /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch5_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1; + /** ledc_task_timer0_rst_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_rst_st_clr:1; + /** ledc_task_timer1_rst_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_rst_st_clr:1; + /** ledc_task_timer2_rst_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_rst_st_clr:1; + /** ledc_task_timer3_rst_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_rst_st_clr:1; + /** ledc_task_timer0_resume_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_resume_st_clr:1; + /** ledc_task_timer1_resume_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_resume_st_clr:1; + /** ledc_task_timer2_resume_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_resume_st_clr:1; + /** ledc_task_timer3_resume_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_resume_st_clr:1; + /** ledc_task_timer0_pause_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_pause_st_clr:1; + /** ledc_task_timer1_pause_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_pause_st_clr:1; + /** ledc_task_timer2_pause_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_pause_st_clr:1; + /** ledc_task_timer3_pause_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_pause_st_clr:1; + /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch0_st_clr:1; + /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st1_clr_reg_t; + +/** Type of task_st2_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch2_st_clr:1; + /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch3_st_clr:1; + /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch4_st_clr:1; + /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch5_st_clr:1; + /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch0_st_clr:1; + /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch1_st_clr:1; + /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch2_st_clr:1; + /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch3_st_clr:1; + /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch4_st_clr:1; + /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch5_st_clr:1; + /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch0_st_clr:1; + /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch1_st_clr:1; + /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch2_st_clr:1; + /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch3_st_clr:1; + /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch4_st_clr:1; + /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch5_st_clr:1; + /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer0_st_clr:1; + /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer0_st_clr:1; + /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer0_st_clr:1; + /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer0_st_clr:1; + /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer0_st_clr:1; + /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer1_st_clr:1; + /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer1_st_clr:1; + /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer1_st_clr:1; + /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer1_st_clr:1; + /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer1_st_clr:1; + /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer0_st_clr:1; + /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer0_st_clr:1; + /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer0_st_clr:1; + /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer0_st_clr:1; + /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer0_st_clr:1; + /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st2_clr_reg_t; + +/** Type of task_st3_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer1_st_clr:1; + /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer1_st_clr:1; + /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer1_st_clr:1; + /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer1_st_clr:1; + /** adc_task_sample0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample0_st_clr:1; + /** adc_task_sample1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample1_st_clr:1; + /** adc_task_start0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_start0_st_clr:1; + /** adc_task_stop0_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_stop0_st_clr:1; + /** regdma_task_start0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start0_st_clr:1; + /** regdma_task_start1_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start1_st_clr:1; + /** regdma_task_start2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start2_st_clr:1; + /** regdma_task_start3_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start3_st_clr:1; + /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_start_sample_st_clr:1; + /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_stop_sample_st_clr:1; + /** i2s0_task_start_rx_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_rx_st_clr:1; + /** i2s0_task_start_tx_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_tx_st_clr:1; + /** i2s0_task_stop_rx_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_rx_st_clr:1; + /** i2s0_task_stop_tx_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_tx_st_clr:1; + /** i2s1_task_start_rx_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_start_rx_st_clr:1; + /** i2s1_task_start_tx_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_start_tx_st_clr:1; + /** i2s1_task_stop_rx_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_stop_rx_st_clr:1; + /** i2s1_task_stop_tx_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_stop_tx_st_clr:1; + /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_task_wakeup_cpu_st_clr:1; + /** ulp_task_int_cpu_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_task_int_cpu_st_clr:1; + /** rtc_task_start_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_start_st_clr:1; + /** rtc_task_stop_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_stop_st_clr:1; + /** rtc_task_clr_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_clr_st_clr:1; + /** rtc_task_triggerflw_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t rtc_task_triggerflw_st_clr:1; + /** gdma_ahb_task_in_start_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_task_in_start_ch0_st_clr:1; + /** gdma_ahb_task_in_start_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_task_in_start_ch1_st_clr:1; + /** gdma_ahb_task_in_start_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_task_in_start_ch2_st_clr:1; + /** gdma_ahb_task_out_start_ch0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_task_out_start_ch0_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st3_clr_reg_t; + +/** Type of task_st4_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** gdma_ahb_task_out_start_ch1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_task_out_start_ch1_st_clr:1; + /** gdma_ahb_task_out_start_ch2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_ahb_task_out_start_ch2_st_clr:1; + /** pmu_task_sleep_req_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t pmu_task_sleep_req_st_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} soc_etm_task_st4_clr_reg_t; + +/** Type of clk_en register + * ETM clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} soc_etm_clk_en_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * ETM date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36737361; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} soc_etm_date_reg_t; + + +typedef struct { + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile soc_etm_chn_evt_id_reg_t ch0_evt_id; + volatile soc_etm_chn_task_id_reg_t ch0_task_id; + volatile soc_etm_chn_evt_id_reg_t ch1_evt_id; + volatile soc_etm_chn_task_id_reg_t ch1_task_id; + volatile soc_etm_chn_evt_id_reg_t ch2_evt_id; + volatile soc_etm_chn_task_id_reg_t ch2_task_id; + volatile soc_etm_chn_evt_id_reg_t ch3_evt_id; + volatile soc_etm_chn_task_id_reg_t ch3_task_id; + volatile soc_etm_chn_evt_id_reg_t ch4_evt_id; + volatile soc_etm_chn_task_id_reg_t ch4_task_id; + volatile soc_etm_chn_evt_id_reg_t ch5_evt_id; + volatile soc_etm_chn_task_id_reg_t ch5_task_id; + volatile soc_etm_chn_evt_id_reg_t ch6_evt_id; + volatile soc_etm_chn_task_id_reg_t ch6_task_id; + volatile soc_etm_chn_evt_id_reg_t ch7_evt_id; + volatile soc_etm_chn_task_id_reg_t ch7_task_id; + volatile soc_etm_chn_evt_id_reg_t ch8_evt_id; + volatile soc_etm_chn_task_id_reg_t ch8_task_id; + volatile soc_etm_chn_evt_id_reg_t ch9_evt_id; + volatile soc_etm_chn_task_id_reg_t ch9_task_id; + volatile soc_etm_chn_evt_id_reg_t ch10_evt_id; + volatile soc_etm_chn_task_id_reg_t ch10_task_id; + volatile soc_etm_chn_evt_id_reg_t ch11_evt_id; + volatile soc_etm_chn_task_id_reg_t ch11_task_id; + volatile soc_etm_chn_evt_id_reg_t ch12_evt_id; + volatile soc_etm_chn_task_id_reg_t ch12_task_id; + volatile soc_etm_chn_evt_id_reg_t ch13_evt_id; + volatile soc_etm_chn_task_id_reg_t ch13_task_id; + volatile soc_etm_chn_evt_id_reg_t ch14_evt_id; + volatile soc_etm_chn_task_id_reg_t ch14_task_id; + volatile soc_etm_chn_evt_id_reg_t ch15_evt_id; + volatile soc_etm_chn_task_id_reg_t ch15_task_id; + volatile soc_etm_chn_evt_id_reg_t ch16_evt_id; + volatile soc_etm_chn_task_id_reg_t ch16_task_id; + volatile soc_etm_chn_evt_id_reg_t ch17_evt_id; + volatile soc_etm_chn_task_id_reg_t ch17_task_id; + volatile soc_etm_chn_evt_id_reg_t ch18_evt_id; + volatile soc_etm_chn_task_id_reg_t ch18_task_id; + volatile soc_etm_chn_evt_id_reg_t ch19_evt_id; + volatile soc_etm_chn_task_id_reg_t ch19_task_id; + volatile soc_etm_chn_evt_id_reg_t ch20_evt_id; + volatile soc_etm_chn_task_id_reg_t ch20_task_id; + volatile soc_etm_chn_evt_id_reg_t ch21_evt_id; + volatile soc_etm_chn_task_id_reg_t ch21_task_id; + volatile soc_etm_chn_evt_id_reg_t ch22_evt_id; + volatile soc_etm_chn_task_id_reg_t ch22_task_id; + volatile soc_etm_chn_evt_id_reg_t ch23_evt_id; + volatile soc_etm_chn_task_id_reg_t ch23_task_id; + volatile soc_etm_chn_evt_id_reg_t ch24_evt_id; + volatile soc_etm_chn_task_id_reg_t ch24_task_id; + volatile soc_etm_chn_evt_id_reg_t ch25_evt_id; + volatile soc_etm_chn_task_id_reg_t ch25_task_id; + volatile soc_etm_chn_evt_id_reg_t ch26_evt_id; + volatile soc_etm_chn_task_id_reg_t ch26_task_id; + volatile soc_etm_chn_evt_id_reg_t ch27_evt_id; + volatile soc_etm_chn_task_id_reg_t ch27_task_id; + volatile soc_etm_chn_evt_id_reg_t ch28_evt_id; + volatile soc_etm_chn_task_id_reg_t ch28_task_id; + volatile soc_etm_chn_evt_id_reg_t ch29_evt_id; + volatile soc_etm_chn_task_id_reg_t ch29_task_id; + volatile soc_etm_chn_evt_id_reg_t ch30_evt_id; + volatile soc_etm_chn_task_id_reg_t ch30_task_id; + volatile soc_etm_chn_evt_id_reg_t ch31_evt_id; + volatile soc_etm_chn_task_id_reg_t ch31_task_id; + volatile soc_etm_chn_evt_id_reg_t ch32_evt_id; + volatile soc_etm_chn_task_id_reg_t ch32_task_id; + volatile soc_etm_chn_evt_id_reg_t ch33_evt_id; + volatile soc_etm_chn_task_id_reg_t ch33_task_id; + volatile soc_etm_chn_evt_id_reg_t ch34_evt_id; + volatile soc_etm_chn_task_id_reg_t ch34_task_id; + volatile soc_etm_chn_evt_id_reg_t ch35_evt_id; + volatile soc_etm_chn_task_id_reg_t ch35_task_id; + volatile soc_etm_chn_evt_id_reg_t ch36_evt_id; + volatile soc_etm_chn_task_id_reg_t ch36_task_id; + volatile soc_etm_chn_evt_id_reg_t ch37_evt_id; + volatile soc_etm_chn_task_id_reg_t ch37_task_id; + volatile soc_etm_chn_evt_id_reg_t ch38_evt_id; + volatile soc_etm_chn_task_id_reg_t ch38_task_id; + volatile soc_etm_chn_evt_id_reg_t ch39_evt_id; + volatile soc_etm_chn_task_id_reg_t ch39_task_id; + volatile soc_etm_chn_evt_id_reg_t ch40_evt_id; + volatile soc_etm_chn_task_id_reg_t ch40_task_id; + volatile soc_etm_chn_evt_id_reg_t ch41_evt_id; + volatile soc_etm_chn_task_id_reg_t ch41_task_id; + volatile soc_etm_chn_evt_id_reg_t ch42_evt_id; + volatile soc_etm_chn_task_id_reg_t ch42_task_id; + volatile soc_etm_chn_evt_id_reg_t ch43_evt_id; + volatile soc_etm_chn_task_id_reg_t ch43_task_id; + volatile soc_etm_chn_evt_id_reg_t ch44_evt_id; + volatile soc_etm_chn_task_id_reg_t ch44_task_id; + volatile soc_etm_chn_evt_id_reg_t ch45_evt_id; + volatile soc_etm_chn_task_id_reg_t ch45_task_id; + volatile soc_etm_chn_evt_id_reg_t ch46_evt_id; + volatile soc_etm_chn_task_id_reg_t ch46_task_id; + volatile soc_etm_chn_evt_id_reg_t ch47_evt_id; + volatile soc_etm_chn_task_id_reg_t ch47_task_id; + volatile soc_etm_chn_evt_id_reg_t ch48_evt_id; + volatile soc_etm_chn_task_id_reg_t ch48_task_id; + volatile soc_etm_chn_evt_id_reg_t ch49_evt_id; + volatile soc_etm_chn_task_id_reg_t ch49_task_id; + volatile soc_etm_evt_st0_reg_t evt_st0; + volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; + volatile soc_etm_evt_st1_reg_t evt_st1; + volatile soc_etm_evt_st1_clr_reg_t evt_st1_clr; + volatile soc_etm_evt_st2_reg_t evt_st2; + volatile soc_etm_evt_st2_clr_reg_t evt_st2_clr; + volatile soc_etm_evt_st3_reg_t evt_st3; + volatile soc_etm_evt_st3_clr_reg_t evt_st3_clr; + volatile soc_etm_task_st0_reg_t task_st0; + volatile soc_etm_task_st0_clr_reg_t task_st0_clr; + volatile soc_etm_task_st1_reg_t task_st1; + volatile soc_etm_task_st1_clr_reg_t task_st1_clr; + volatile soc_etm_task_st2_reg_t task_st2; + volatile soc_etm_task_st2_clr_reg_t task_st2_clr; + volatile soc_etm_task_st3_reg_t task_st3; + volatile soc_etm_task_st3_clr_reg_t task_st3_clr; + volatile soc_etm_task_st4_reg_t task_st4; + volatile soc_etm_task_st4_clr_reg_t task_st4_clr; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; +} soc_etm_dev_t; + +extern soc_etm_dev_t SOC_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(soc_etm_dev_t) == 0x1f8, "Invalid size of soc_etm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/spi1_mem_reg.h b/components/soc/esp32c61/include/soc/spi1_mem_reg.h new file mode 100644 index 0000000000..d92aeec9a6 --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi1_mem_reg.h @@ -0,0 +1,1514 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_CMD_REG register + * SPI1 memory command register + */ +#define SPI_MEM_CMD_REG (DR_REG_SPI_MEM_BASE + 0x0) +/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ +#define SPI_MEM_MST_ST 0x0000000FU +#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) +#define SPI_MEM_MST_ST_V 0x0000000FU +#define SPI_MEM_MST_ST_S 0 +/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_SLV_ST 0x0000000FU +#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) +#define SPI_MEM_SLV_ST_V 0x0000000FU +#define SPI_MEM_SLV_ST_S 4 +/** SPI_MEM_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; + * In user mode, it is set to indicate that program/erase operation will be triggered. + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the + * operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S) +#define SPI_MEM_FLASH_PE_V 0x00000001U +#define SPI_MEM_FLASH_PE_S 17 +/** SPI_MEM_USR : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) +#define SPI_MEM_USR_V 0x00000001U +#define SPI_MEM_USR_S 18 +/** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; + * Drive Flash into high performance mode. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S) +#define SPI_MEM_FLASH_HPM_V 0x00000001U +#define SPI_MEM_FLASH_HPM_S 19 +/** SPI_MEM_FLASH_RES : R/W/SC; bitpos: [20]; default: 0; + * This bit combined with reg_resandres bit releases Flash from the power-down state + * or high performance mode and obtains the devices ID. The bit will be cleared once + * the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S) +#define SPI_MEM_FLASH_RES_V 0x00000001U +#define SPI_MEM_FLASH_RES_S 20 +/** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; + * Drive Flash into power down. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S) +#define SPI_MEM_FLASH_DP_V 0x00000001U +#define SPI_MEM_FLASH_DP_S 21 +/** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; + * Chip erase enable. Chip erase operation will be triggered when the bit is set. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S) +#define SPI_MEM_FLASH_CE_V 0x00000001U +#define SPI_MEM_FLASH_CE_S 22 +/** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; + * Block erase enable(32KB) . Block erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S) +#define SPI_MEM_FLASH_BE_V 0x00000001U +#define SPI_MEM_FLASH_BE_S 23 +/** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; + * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S) +#define SPI_MEM_FLASH_SE_V 0x00000001U +#define SPI_MEM_FLASH_SE_S 24 +/** SPI_MEM_FLASH_PP : R/W/SC; bitpos: [25]; default: 0; + * Page program enable(1 byte ~256 bytes data to be programmed). Page program + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done .1: enable 0: disable. + */ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S) +#define SPI_MEM_FLASH_PP_V 0x00000001U +#define SPI_MEM_FLASH_PP_S 25 +/** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; + * Write status register enable. Write status operation will be triggered when the + * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S) +#define SPI_MEM_FLASH_WRSR_V 0x00000001U +#define SPI_MEM_FLASH_WRSR_S 26 +/** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; + * Read status register-1. Read status operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S) +#define SPI_MEM_FLASH_RDSR_V 0x00000001U +#define SPI_MEM_FLASH_RDSR_S 27 +/** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; + * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be + * cleared once the operation done. 1: enable 0: disable. + */ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S) +#define SPI_MEM_FLASH_RDID_V 0x00000001U +#define SPI_MEM_FLASH_RDID_S 28 +/** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; + * Write flash disable. Write disable command will be sent when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S) +#define SPI_MEM_FLASH_WRDI_V 0x00000001U +#define SPI_MEM_FLASH_WRDI_S 29 +/** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; + * Write flash enable. Write enable command will be sent when the bit is set. The bit + * will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S) +#define SPI_MEM_FLASH_WREN_V 0x00000001U +#define SPI_MEM_FLASH_WREN_S 30 +/** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; + * Read flash enable. Read flash operation will be triggered when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S) +#define SPI_MEM_FLASH_READ_V 0x00000001U +#define SPI_MEM_FLASH_READ_S 31 + +/** SPI_MEM_ADDR_REG register + * SPI1 address register + */ +#define SPI_MEM_ADDR_REG (DR_REG_SPI_MEM_BASE + 0x4) +/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_MEM_USR_ADDR_VALUE_M (SPI_MEM_USR_ADDR_VALUE_V << SPI_MEM_USR_ADDR_VALUE_S) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +/** SPI_MEM_CTRL_REG register + * SPI1 control register. + */ +#define SPI_MEM_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x8) +/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) +#define SPI_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_FDUMMY_RIN_S 2 +/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) +#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_FDUMMY_WOUT_S 3 +/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) +#define SPI_MEM_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_FDOUT_OCT_S 4 +/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) +#define SPI_MEM_FDIN_OCT_V 0x00000001U +#define SPI_MEM_FDIN_OCT_S 5 +/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) +#define SPI_MEM_FADDR_OCT_V 0x00000001U +#define SPI_MEM_FADDR_OCT_S 6 +/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) +#define SPI_MEM_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_FCMD_QUAD_S 8 +/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) +#define SPI_MEM_FCMD_OCT_V 0x00000001U +#define SPI_MEM_FCMD_OCT_S 9 +/** SPI_MEM_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; + * For SPI1, initialize crc32 module before writing encrypted data to flash. Active + * low. + */ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S) +#define SPI_MEM_FCS_CRC_EN_V 0x00000001U +#define SPI_MEM_FCS_CRC_EN_S 10 +/** SPI_MEM_TX_CRC_EN : R/W; bitpos: [11]; default: 0; + * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + */ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S) +#define SPI_MEM_TX_CRC_EN_V 0x00000001U +#define SPI_MEM_TX_CRC_EN_S 11 +/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. + */ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) +#define SPI_MEM_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_FASTRD_MODE_S 13 +/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) +#define SPI_MEM_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_FREAD_DUAL_S 14 +/** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1; + * The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with + * spi_mem_flash_res bit. 1: enable 0: disable. + */ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S) +#define SPI_MEM_RESANDRES_V 0x00000001U +#define SPI_MEM_RESANDRES_S 15 +/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) +#define SPI_MEM_Q_POL_V 0x00000001U +#define SPI_MEM_Q_POL_S 18 +/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) +#define SPI_MEM_D_POL_V 0x00000001U +#define SPI_MEM_D_POL_S 19 +/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) +#define SPI_MEM_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_FREAD_QUAD_S 20 +/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) +#define SPI_MEM_WP_REG_V 0x00000001U +#define SPI_MEM_WP_REG_S 21 +/** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0; + * two bytes data will be written to status register when it is set. 1: enable 0: + * disable. + */ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S) +#define SPI_MEM_WRSR_2B_V 0x00000001U +#define SPI_MEM_WRSR_2B_S 22 +/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) +#define SPI_MEM_FREAD_DIO_V 0x00000001U +#define SPI_MEM_FREAD_DIO_S 23 +/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) +#define SPI_MEM_FREAD_QIO_V 0x00000001U +#define SPI_MEM_FREAD_QIO_S 24 + +/** SPI_MEM_CTRL1_REG register + * SPI1 control1 register. + */ +#define SPI_MEM_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xc) +/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ +#define SPI_MEM_CLK_MODE 0x00000003U +#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) +#define SPI_MEM_CLK_MODE_V 0x00000003U +#define SPI_MEM_CLK_MODE_S 0 +/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; + * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) + * SPI_CLK cycles. + */ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 + +/** SPI_MEM_CTRL2_REG register + * SPI1 control2 register. + */ +#define SPI_MEM_CTRL2_REG (DR_REG_SPI_MEM_BASE + 0x10) +/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) +#define SPI_MEM_SYNC_RESET_V 0x00000001U +#define SPI_MEM_SYNC_RESET_S 31 + +/** SPI_MEM_CLOCK_REG register + * SPI1 clock division control register. + */ +#define SPI_MEM_CLOCK_REG (DR_REG_SPI_MEM_BASE + 0x14) +/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_CLKCNT_L 0x000000FFU +#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) +#define SPI_MEM_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_CLKCNT_L_S 0 +/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_CLKCNT_H 0x000000FFU +#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) +#define SPI_MEM_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_CLKCNT_H_S 8 +/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_CLKCNT_N 0x000000FFU +#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) +#define SPI_MEM_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_CLKCNT_N_S 16 +/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_USER_REG register + * SPI1 user register. + */ +#define SPI_MEM_USER_REG (DR_REG_SPI_MEM_BASE + 0x18) +/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + */ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) +#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_CK_OUT_EDGE_S 9 +/** SPI_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (SPI_MEM_FWRITE_DUAL_V << SPI_MEM_FWRITE_DUAL_S) +#define SPI_MEM_FWRITE_DUAL_V 0x00000001U +#define SPI_MEM_FWRITE_DUAL_S 12 +/** SPI_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (SPI_MEM_FWRITE_QUAD_V << SPI_MEM_FWRITE_QUAD_S) +#define SPI_MEM_FWRITE_QUAD_V 0x00000001U +#define SPI_MEM_FWRITE_QUAD_S 13 +/** SPI_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (SPI_MEM_FWRITE_DIO_V << SPI_MEM_FWRITE_DIO_S) +#define SPI_MEM_FWRITE_DIO_V 0x00000001U +#define SPI_MEM_FWRITE_DIO_S 14 +/** SPI_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (SPI_MEM_FWRITE_QIO_V << SPI_MEM_FWRITE_QIO_S) +#define SPI_MEM_FWRITE_QIO_V 0x00000001U +#define SPI_MEM_FWRITE_QIO_S 15 +/** SPI_MEM_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: + * enable 0: disable. + */ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (SPI_MEM_USR_MISO_HIGHPART_V << SPI_MEM_USR_MISO_HIGHPART_S) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/** SPI_MEM_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: + * enable 0: disable. + */ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (SPI_MEM_USR_MOSI_HIGHPART_V << SPI_MEM_USR_MOSI_HIGHPART_S) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (SPI_MEM_USR_MOSI_V << SPI_MEM_USR_MOSI_S) +#define SPI_MEM_USR_MOSI_V 0x00000001U +#define SPI_MEM_USR_MOSI_S 27 +/** SPI_MEM_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (SPI_MEM_USR_MISO_V << SPI_MEM_USR_MISO_S) +#define SPI_MEM_USR_MISO_V 0x00000001U +#define SPI_MEM_USR_MISO_S 28 +/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) +#define SPI_MEM_USR_DUMMY_V 0x00000001U +#define SPI_MEM_USR_DUMMY_S 29 +/** SPI_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (SPI_MEM_USR_ADDR_V << SPI_MEM_USR_ADDR_S) +#define SPI_MEM_USR_ADDR_V 0x00000001U +#define SPI_MEM_USR_ADDR_S 30 +/** SPI_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (SPI_MEM_USR_COMMAND_V << SPI_MEM_USR_COMMAND_S) +#define SPI_MEM_USR_COMMAND_V 0x00000001U +#define SPI_MEM_USR_COMMAND_S 31 + +/** SPI_MEM_USER1_REG register + * SPI1 user1 register. + */ +#define SPI_MEM_USER1_REG (DR_REG_SPI_MEM_BASE + 0x1c) +/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_USER2_REG register + * SPI1 user2 register. + */ +#define SPI_MEM_USER2_REG (DR_REG_SPI_MEM_BASE + 0x20) +/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) +#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_MOSI_DLEN_REG register + * SPI1 send data bit length control register. + */ +#define SPI_MEM_MOSI_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x24) +/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FFU +#define SPI_MEM_USR_MOSI_DBITLEN_M (SPI_MEM_USR_MOSI_DBITLEN_V << SPI_MEM_USR_MOSI_DBITLEN_S) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x000003FFU +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +/** SPI_MEM_MISO_DLEN_REG register + * SPI1 receive data bit length control register. + */ +#define SPI_MEM_MISO_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x28) +/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FFU +#define SPI_MEM_USR_MISO_DBITLEN_M (SPI_MEM_USR_MISO_DBITLEN_V << SPI_MEM_USR_MISO_DBITLEN_S) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x000003FFU +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +/** SPI_MEM_RD_STATUS_REG register + * SPI1 status register. + */ +#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_MEM_BASE + 0x2c) +/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + */ +#define SPI_MEM_STATUS 0x0000FFFFU +#define SPI_MEM_STATUS_M (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S) +#define SPI_MEM_STATUS_V 0x0000FFFFU +#define SPI_MEM_STATUS_S 0 +/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + */ +#define SPI_MEM_WB_MODE 0x000000FFU +#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) +#define SPI_MEM_WB_MODE_V 0x000000FFU +#define SPI_MEM_WB_MODE_S 16 +/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + */ +#define SPI_MEM_WB_MODE_BITLEN 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) +#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_S 24 +/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + */ +#define SPI_MEM_WB_MODE_EN (BIT(27)) +#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) +#define SPI_MEM_WB_MODE_EN_V 0x00000001U +#define SPI_MEM_WB_MODE_EN_S 27 + +/** SPI_MEM_MISC_REG register + * SPI1 misc register + */ +#define SPI_MEM_MISC_REG (DR_REG_SPI_MEM_BASE + 0x34) +/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (SPI_MEM_CS0_DIS_V << SPI_MEM_CS0_DIS_S) +#define SPI_MEM_CS0_DIS_V 0x00000001U +#define SPI_MEM_CS0_DIS_S 0 +/** SPI_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (SPI_MEM_CS1_DIS_V << SPI_MEM_CS1_DIS_S) +#define SPI_MEM_CS1_DIS_V 0x00000001U +#define SPI_MEM_CS1_DIS_S 1 +/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) +#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_TX_CRC_REG register + * SPI1 TX CRC data register. + */ +#define SPI_MEM_TX_CRC_REG (DR_REG_SPI_MEM_BASE + 0x38) +/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; + * For SPI1, the value of crc32. + */ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFFU +#define SPI_MEM_TX_CRC_DATA_M (SPI_MEM_TX_CRC_DATA_V << SPI_MEM_TX_CRC_DATA_S) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFFU +#define SPI_MEM_TX_CRC_DATA_S 0 + +/** SPI_MEM_CACHE_FCTRL_REG register + * SPI1 bit mode control register. + */ +#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_MEM_BASE + 0x3c) +/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with + * spi_mem_fread_dio. + */ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) +#define SPI_MEM_FDIN_DUAL_V 0x00000001U +#define SPI_MEM_FDIN_DUAL_S 3 +/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_dio. + */ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) +#define SPI_MEM_FDOUT_DUAL_V 0x00000001U +#define SPI_MEM_FDOUT_DUAL_S 4 +/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_dio. + */ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) +#define SPI_MEM_FADDR_DUAL_V 0x00000001U +#define SPI_MEM_FADDR_DUAL_S 5 +/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_qio. + */ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) +#define SPI_MEM_FDIN_QUAD_V 0x00000001U +#define SPI_MEM_FDIN_QUAD_S 6 +/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_qio. + */ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) +#define SPI_MEM_FDOUT_QUAD_V 0x00000001U +#define SPI_MEM_FDOUT_QUAD_S 7 +/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_qio. + */ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) +#define SPI_MEM_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_FADDR_QUAD_S 8 + +/** SPI_MEM_W0_REG register + * SPI1 memory data buffer0 + */ +#define SPI_MEM_W0_REG (DR_REG_SPI_MEM_BASE + 0x58) +/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF0 0xFFFFFFFFU +#define SPI_MEM_BUF0_M (SPI_MEM_BUF0_V << SPI_MEM_BUF0_S) +#define SPI_MEM_BUF0_V 0xFFFFFFFFU +#define SPI_MEM_BUF0_S 0 + +/** SPI_MEM_W1_REG register + * SPI1 memory data buffer1 + */ +#define SPI_MEM_W1_REG (DR_REG_SPI_MEM_BASE + 0x5c) +/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF1 0xFFFFFFFFU +#define SPI_MEM_BUF1_M (SPI_MEM_BUF1_V << SPI_MEM_BUF1_S) +#define SPI_MEM_BUF1_V 0xFFFFFFFFU +#define SPI_MEM_BUF1_S 0 + +/** SPI_MEM_W2_REG register + * SPI1 memory data buffer2 + */ +#define SPI_MEM_W2_REG (DR_REG_SPI_MEM_BASE + 0x60) +/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF2 0xFFFFFFFFU +#define SPI_MEM_BUF2_M (SPI_MEM_BUF2_V << SPI_MEM_BUF2_S) +#define SPI_MEM_BUF2_V 0xFFFFFFFFU +#define SPI_MEM_BUF2_S 0 + +/** SPI_MEM_W3_REG register + * SPI1 memory data buffer3 + */ +#define SPI_MEM_W3_REG (DR_REG_SPI_MEM_BASE + 0x64) +/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF3 0xFFFFFFFFU +#define SPI_MEM_BUF3_M (SPI_MEM_BUF3_V << SPI_MEM_BUF3_S) +#define SPI_MEM_BUF3_V 0xFFFFFFFFU +#define SPI_MEM_BUF3_S 0 + +/** SPI_MEM_W4_REG register + * SPI1 memory data buffer4 + */ +#define SPI_MEM_W4_REG (DR_REG_SPI_MEM_BASE + 0x68) +/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF4 0xFFFFFFFFU +#define SPI_MEM_BUF4_M (SPI_MEM_BUF4_V << SPI_MEM_BUF4_S) +#define SPI_MEM_BUF4_V 0xFFFFFFFFU +#define SPI_MEM_BUF4_S 0 + +/** SPI_MEM_W5_REG register + * SPI1 memory data buffer5 + */ +#define SPI_MEM_W5_REG (DR_REG_SPI_MEM_BASE + 0x6c) +/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF5 0xFFFFFFFFU +#define SPI_MEM_BUF5_M (SPI_MEM_BUF5_V << SPI_MEM_BUF5_S) +#define SPI_MEM_BUF5_V 0xFFFFFFFFU +#define SPI_MEM_BUF5_S 0 + +/** SPI_MEM_W6_REG register + * SPI1 memory data buffer6 + */ +#define SPI_MEM_W6_REG (DR_REG_SPI_MEM_BASE + 0x70) +/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF6 0xFFFFFFFFU +#define SPI_MEM_BUF6_M (SPI_MEM_BUF6_V << SPI_MEM_BUF6_S) +#define SPI_MEM_BUF6_V 0xFFFFFFFFU +#define SPI_MEM_BUF6_S 0 + +/** SPI_MEM_W7_REG register + * SPI1 memory data buffer7 + */ +#define SPI_MEM_W7_REG (DR_REG_SPI_MEM_BASE + 0x74) +/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF7 0xFFFFFFFFU +#define SPI_MEM_BUF7_M (SPI_MEM_BUF7_V << SPI_MEM_BUF7_S) +#define SPI_MEM_BUF7_V 0xFFFFFFFFU +#define SPI_MEM_BUF7_S 0 + +/** SPI_MEM_W8_REG register + * SPI1 memory data buffer8 + */ +#define SPI_MEM_W8_REG (DR_REG_SPI_MEM_BASE + 0x78) +/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF8 0xFFFFFFFFU +#define SPI_MEM_BUF8_M (SPI_MEM_BUF8_V << SPI_MEM_BUF8_S) +#define SPI_MEM_BUF8_V 0xFFFFFFFFU +#define SPI_MEM_BUF8_S 0 + +/** SPI_MEM_W9_REG register + * SPI1 memory data buffer9 + */ +#define SPI_MEM_W9_REG (DR_REG_SPI_MEM_BASE + 0x7c) +/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF9 0xFFFFFFFFU +#define SPI_MEM_BUF9_M (SPI_MEM_BUF9_V << SPI_MEM_BUF9_S) +#define SPI_MEM_BUF9_V 0xFFFFFFFFU +#define SPI_MEM_BUF9_S 0 + +/** SPI_MEM_W10_REG register + * SPI1 memory data buffer10 + */ +#define SPI_MEM_W10_REG (DR_REG_SPI_MEM_BASE + 0x80) +/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF10 0xFFFFFFFFU +#define SPI_MEM_BUF10_M (SPI_MEM_BUF10_V << SPI_MEM_BUF10_S) +#define SPI_MEM_BUF10_V 0xFFFFFFFFU +#define SPI_MEM_BUF10_S 0 + +/** SPI_MEM_W11_REG register + * SPI1 memory data buffer11 + */ +#define SPI_MEM_W11_REG (DR_REG_SPI_MEM_BASE + 0x84) +/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF11 0xFFFFFFFFU +#define SPI_MEM_BUF11_M (SPI_MEM_BUF11_V << SPI_MEM_BUF11_S) +#define SPI_MEM_BUF11_V 0xFFFFFFFFU +#define SPI_MEM_BUF11_S 0 + +/** SPI_MEM_W12_REG register + * SPI1 memory data buffer12 + */ +#define SPI_MEM_W12_REG (DR_REG_SPI_MEM_BASE + 0x88) +/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF12 0xFFFFFFFFU +#define SPI_MEM_BUF12_M (SPI_MEM_BUF12_V << SPI_MEM_BUF12_S) +#define SPI_MEM_BUF12_V 0xFFFFFFFFU +#define SPI_MEM_BUF12_S 0 + +/** SPI_MEM_W13_REG register + * SPI1 memory data buffer13 + */ +#define SPI_MEM_W13_REG (DR_REG_SPI_MEM_BASE + 0x8c) +/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF13 0xFFFFFFFFU +#define SPI_MEM_BUF13_M (SPI_MEM_BUF13_V << SPI_MEM_BUF13_S) +#define SPI_MEM_BUF13_V 0xFFFFFFFFU +#define SPI_MEM_BUF13_S 0 + +/** SPI_MEM_W14_REG register + * SPI1 memory data buffer14 + */ +#define SPI_MEM_W14_REG (DR_REG_SPI_MEM_BASE + 0x90) +/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF14 0xFFFFFFFFU +#define SPI_MEM_BUF14_M (SPI_MEM_BUF14_V << SPI_MEM_BUF14_S) +#define SPI_MEM_BUF14_V 0xFFFFFFFFU +#define SPI_MEM_BUF14_S 0 + +/** SPI_MEM_W15_REG register + * SPI1 memory data buffer15 + */ +#define SPI_MEM_W15_REG (DR_REG_SPI_MEM_BASE + 0x94) +/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_MEM_BUF15 0xFFFFFFFFU +#define SPI_MEM_BUF15_M (SPI_MEM_BUF15_V << SPI_MEM_BUF15_S) +#define SPI_MEM_BUF15_V 0xFFFFFFFFU +#define SPI_MEM_BUF15_S 0 + +/** SPI_MEM_FLASH_WAITI_CTRL_REG register + * SPI1 wait idle control register + */ +#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x98) +/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (SPI_MEM_WAITI_EN_V << SPI_MEM_WAITI_EN_S) +#define SPI_MEM_WAITI_EN_V 0x00000001U +#define SPI_MEM_WAITI_EN_S 0 +/** SPI_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (SPI_MEM_WAITI_DUMMY_V << SPI_MEM_WAITI_DUMMY_S) +#define SPI_MEM_WAITI_DUMMY_V 0x00000001U +#define SPI_MEM_WAITI_DUMMY_S 1 +/** SPI_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ +#define SPI_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_M (SPI_MEM_WAITI_ADDR_EN_V << SPI_MEM_WAITI_ADDR_EN_S) +#define SPI_MEM_WAITI_ADDR_EN_V 0x00000001U +#define SPI_MEM_WAITI_ADDR_EN_S 2 +/** SPI_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; + * When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when + * SPI_MEM_WAITI_ADDR_EN is cleared. + */ +#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003U +#define SPI_MEM_WAITI_ADDR_CYCLELEN_M (SPI_MEM_WAITI_ADDR_CYCLELEN_V << SPI_MEM_WAITI_ADDR_CYCLELEN_S) +#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x00000003U +#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 +/** SPI_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ +#define SPI_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_M (SPI_MEM_WAITI_CMD_2B_V << SPI_MEM_WAITI_CMD_2B_S) +#define SPI_MEM_WAITI_CMD_2B_V 0x00000001U +#define SPI_MEM_WAITI_CMD_2B_S 9 +/** SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M (SPI_MEM_WAITI_DUMMY_CYCLELEN_V << SPI_MEM_WAITI_DUMMY_CYCLELEN_S) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/** SPI_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ +#define SPI_MEM_WAITI_CMD 0x0000FFFFU +#define SPI_MEM_WAITI_CMD_M (SPI_MEM_WAITI_CMD_V << SPI_MEM_WAITI_CMD_S) +#define SPI_MEM_WAITI_CMD_V 0x0000FFFFU +#define SPI_MEM_WAITI_CMD_S 16 + +/** SPI_MEM_FLASH_SUS_CTRL_REG register + * SPI1 flash suspend control register + */ +#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x9c) +/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (SPI_MEM_FLASH_PER_V << SPI_MEM_FLASH_PER_S) +#define SPI_MEM_FLASH_PER_V 0x00000001U +#define SPI_MEM_FLASH_PER_S 0 +/** SPI_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (SPI_MEM_FLASH_PES_V << SPI_MEM_FLASH_PES_S) +#define SPI_MEM_FLASH_PES_V 0x00000001U +#define SPI_MEM_FLASH_PES_S 1 +/** SPI_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (SPI_MEM_FLASH_PER_WAIT_EN_V << SPI_MEM_FLASH_PER_WAIT_EN_S) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x00000001U +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/** SPI_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (SPI_MEM_FLASH_PES_WAIT_EN_V << SPI_MEM_FLASH_PES_WAIT_EN_S) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x00000001U +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/** SPI_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (SPI_MEM_PES_PER_EN_V << SPI_MEM_PES_PER_EN_S) +#define SPI_MEM_PES_PER_EN_V 0x00000001U +#define SPI_MEM_PES_PER_EN_S 4 +/** SPI_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ +#define SPI_MEM_FLASH_PES_EN (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_M (SPI_MEM_FLASH_PES_EN_V << SPI_MEM_FLASH_PES_EN_S) +#define SPI_MEM_FLASH_PES_EN_V 0x00000001U +#define SPI_MEM_FLASH_PES_EN_S 5 +/** SPI_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + */ +#define SPI_MEM_PESR_END_MSK 0x0000FFFFU +#define SPI_MEM_PESR_END_MSK_M (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S) +#define SPI_MEM_PESR_END_MSK_V 0x0000FFFFU +#define SPI_MEM_PESR_END_MSK_S 6 +/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ +#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_M (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S) +#define SPI_MEM_FMEM_RD_SUS_2B_V 0x00000001U +#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +/** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ +#define SPI_MEM_PER_END_EN (BIT(23)) +#define SPI_MEM_PER_END_EN_M (SPI_MEM_PER_END_EN_V << SPI_MEM_PER_END_EN_S) +#define SPI_MEM_PER_END_EN_V 0x00000001U +#define SPI_MEM_PER_END_EN_S 23 +/** SPI_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ +#define SPI_MEM_PES_END_EN (BIT(24)) +#define SPI_MEM_PES_END_EN_M (SPI_MEM_PES_END_EN_V << SPI_MEM_PES_END_EN_S) +#define SPI_MEM_PES_END_EN_V 0x00000001U +#define SPI_MEM_PES_END_EN_S 24 +/** SPI_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it + * will be treated as check pass. + */ +#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007FU +#define SPI_MEM_SUS_TIMEOUT_CNT_M (SPI_MEM_SUS_TIMEOUT_CNT_V << SPI_MEM_SUS_TIMEOUT_CNT_S) +#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x0000007FU +#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 + +/** SPI_MEM_FLASH_SUS_CMD_REG register + * SPI1 flash suspend command register + */ +#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI_MEM_BASE + 0xa0) +/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ +#define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFFU +#define SPI_MEM_FLASH_PES_COMMAND_M (SPI_MEM_FLASH_PES_COMMAND_V << SPI_MEM_FLASH_PES_COMMAND_S) +#define SPI_MEM_FLASH_PES_COMMAND_V 0x0000FFFFU +#define SPI_MEM_FLASH_PES_COMMAND_S 0 +/** SPI_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ +#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFFU +#define SPI_MEM_WAIT_PESR_COMMAND_M (SPI_MEM_WAIT_PESR_COMMAND_V << SPI_MEM_WAIT_PESR_COMMAND_S) +#define SPI_MEM_WAIT_PESR_COMMAND_V 0x0000FFFFU +#define SPI_MEM_WAIT_PESR_COMMAND_S 16 + +/** SPI_MEM_SUS_STATUS_REG register + * SPI1 flash suspend status register + */ +#define SPI_MEM_SUS_STATUS_REG (DR_REG_SPI_MEM_BASE + 0xa4) +/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (SPI_MEM_FLASH_SUS_V << SPI_MEM_FLASH_SUS_S) +#define SPI_MEM_FLASH_SUS_V 0x00000001U +#define SPI_MEM_FLASH_SUS_S 0 +/** SPI_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ +#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_M (SPI_MEM_WAIT_PESR_CMD_2B_V << SPI_MEM_WAIT_PESR_CMD_2B_S) +#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x00000001U +#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 +/** SPI_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ +#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_M (SPI_MEM_FLASH_HPM_DLY_128_V << SPI_MEM_FLASH_HPM_DLY_128_S) +#define SPI_MEM_FLASH_HPM_DLY_128_V 0x00000001U +#define SPI_MEM_FLASH_HPM_DLY_128_S 2 +/** SPI_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ +#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_M (SPI_MEM_FLASH_RES_DLY_128_V << SPI_MEM_FLASH_RES_DLY_128_S) +#define SPI_MEM_FLASH_RES_DLY_128_V 0x00000001U +#define SPI_MEM_FLASH_RES_DLY_128_S 3 +/** SPI_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ +#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_M (SPI_MEM_FLASH_DP_DLY_128_V << SPI_MEM_FLASH_DP_DLY_128_S) +#define SPI_MEM_FLASH_DP_DLY_128_V 0x00000001U +#define SPI_MEM_FLASH_DP_DLY_128_S 4 +/** SPI_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: + * SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is + * sent. + */ +#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_M (SPI_MEM_FLASH_PER_DLY_128_V << SPI_MEM_FLASH_PER_DLY_128_S) +#define SPI_MEM_FLASH_PER_DLY_128_V 0x00000001U +#define SPI_MEM_FLASH_PER_DLY_128_S 5 +/** SPI_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: + * SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is + * sent. + */ +#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_M (SPI_MEM_FLASH_PES_DLY_128_V << SPI_MEM_FLASH_PES_DLY_128_S) +#define SPI_MEM_FLASH_PES_DLY_128_V 0x00000001U +#define SPI_MEM_FLASH_PES_DLY_128_S 6 +/** SPI_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ +#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_M (SPI_MEM_SPI0_LOCK_EN_V << SPI_MEM_SPI0_LOCK_EN_S) +#define SPI_MEM_SPI0_LOCK_EN_V 0x00000001U +#define SPI_MEM_SPI0_LOCK_EN_S 7 +/** SPI_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ +#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_M (SPI_MEM_FLASH_PESR_CMD_2B_V << SPI_MEM_FLASH_PESR_CMD_2B_S) +#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x00000001U +#define SPI_MEM_FLASH_PESR_CMD_2B_S 15 +/** SPI_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ +#define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFFU +#define SPI_MEM_FLASH_PER_COMMAND_M (SPI_MEM_FLASH_PER_COMMAND_V << SPI_MEM_FLASH_PER_COMMAND_S) +#define SPI_MEM_FLASH_PER_COMMAND_V 0x0000FFFFU +#define SPI_MEM_FLASH_PER_COMMAND_S 16 + +/** SPI_MEM_FLASH_WAITI_CTRL1_REG register + * SPI1 wait idle control register + */ +#define SPI_MEM_FLASH_WAITI_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xac) +/** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0; + * SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE. + */ +#define SPI_MEM_WAITI_IDLE_DELAY_TIME 0x000003FFU +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_M (SPI_MEM_WAITI_IDLE_DELAY_TIME_V << SPI_MEM_WAITI_IDLE_DELAY_TIME_S) +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_V 0x000003FFU +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_S 0 +/** SPI_MEM_WAITI_IDLE_DELAY_TIME_EN : R/W; bitpos: [10]; default: 0; + * Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable. + */ +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN (BIT(10)) +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_M (SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V << SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S) +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V 0x00000001U +#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S 10 + +/** SPI_MEM_INT_ENA_REG register + * SPI1 interrupt enable register + */ +#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_MEM_BASE + 0xc0) +/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_MEM_PER_END_INT interrupt. + */ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (SPI_MEM_PER_END_INT_ENA_V << SPI_MEM_PER_END_INT_ENA_S) +#define SPI_MEM_PER_END_INT_ENA_V 0x00000001U +#define SPI_MEM_PER_END_INT_ENA_S 0 +/** SPI_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_MEM_PES_END_INT interrupt. + */ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (SPI_MEM_PES_END_INT_ENA_V << SPI_MEM_PES_END_INT_ENA_S) +#define SPI_MEM_PES_END_INT_ENA_V 0x00000001U +#define SPI_MEM_PES_END_INT_ENA_S 1 +/** SPI_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI_MEM_WPE_END_INT interrupt. + */ +#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_M (SPI_MEM_WPE_END_INT_ENA_V << SPI_MEM_WPE_END_INT_ENA_S) +#define SPI_MEM_WPE_END_INT_ENA_V 0x00000001U +#define SPI_MEM_WPE_END_INT_ENA_S 2 +/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (SPI_MEM_BROWN_OUT_INT_ENA_V << SPI_MEM_BROWN_OUT_INT_ENA_S) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x00000001U +#define SPI_MEM_BROWN_OUT_INT_ENA_S 10 + +/** SPI_MEM_INT_CLR_REG register + * SPI1 interrupt clear register + */ +#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_MEM_BASE + 0xc4) +/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_MEM_PER_END_INT interrupt. + */ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (SPI_MEM_PER_END_INT_CLR_V << SPI_MEM_PER_END_INT_CLR_S) +#define SPI_MEM_PER_END_INT_CLR_V 0x00000001U +#define SPI_MEM_PER_END_INT_CLR_S 0 +/** SPI_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_MEM_PES_END_INT interrupt. + */ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (SPI_MEM_PES_END_INT_CLR_V << SPI_MEM_PES_END_INT_CLR_S) +#define SPI_MEM_PES_END_INT_CLR_V 0x00000001U +#define SPI_MEM_PES_END_INT_CLR_S 1 +/** SPI_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI_MEM_WPE_END_INT interrupt. + */ +#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_M (SPI_MEM_WPE_END_INT_CLR_V << SPI_MEM_WPE_END_INT_CLR_S) +#define SPI_MEM_WPE_END_INT_CLR_V 0x00000001U +#define SPI_MEM_WPE_END_INT_CLR_S 2 +/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0; + * The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (SPI_MEM_BROWN_OUT_INT_CLR_V << SPI_MEM_BROWN_OUT_INT_CLR_S) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x00000001U +#define SPI_MEM_BROWN_OUT_INT_CLR_S 10 + +/** SPI_MEM_INT_RAW_REG register + * SPI1 interrupt raw register + */ +#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_MEM_BASE + 0xc8) +/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (SPI_MEM_PER_END_INT_RAW_V << SPI_MEM_PER_END_INT_RAW_S) +#define SPI_MEM_PER_END_INT_RAW_V 0x00000001U +#define SPI_MEM_PER_END_INT_RAW_S 0 +/** SPI_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (SPI_MEM_PES_END_INT_RAW_V << SPI_MEM_PES_END_INT_RAW_S) +#define SPI_MEM_PES_END_INT_RAW_V 0x00000001U +#define SPI_MEM_PES_END_INT_RAW_S 1 +/** SPI_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ +#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_M (SPI_MEM_WPE_END_INT_RAW_V << SPI_MEM_WPE_END_INT_RAW_S) +#define SPI_MEM_WPE_END_INT_RAW_V 0x00000001U +#define SPI_MEM_WPE_END_INT_RAW_S 2 +/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is loosing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (SPI_MEM_BROWN_OUT_INT_RAW_V << SPI_MEM_BROWN_OUT_INT_RAW_S) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x00000001U +#define SPI_MEM_BROWN_OUT_INT_RAW_S 10 + +/** SPI_MEM_INT_ST_REG register + * SPI1 interrupt status register + */ +#define SPI_MEM_INT_ST_REG (DR_REG_SPI_MEM_BASE + 0xcc) +/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_MEM_PER_END_INT interrupt. + */ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (SPI_MEM_PER_END_INT_ST_V << SPI_MEM_PER_END_INT_ST_S) +#define SPI_MEM_PER_END_INT_ST_V 0x00000001U +#define SPI_MEM_PER_END_INT_ST_S 0 +/** SPI_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_MEM_PES_END_INT interrupt. + */ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (SPI_MEM_PES_END_INT_ST_V << SPI_MEM_PES_END_INT_ST_S) +#define SPI_MEM_PES_END_INT_ST_V 0x00000001U +#define SPI_MEM_PES_END_INT_ST_S 1 +/** SPI_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI_MEM_WPE_END_INT interrupt. + */ +#define SPI_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_M (SPI_MEM_WPE_END_INT_ST_V << SPI_MEM_WPE_END_INT_ST_S) +#define SPI_MEM_WPE_END_INT_ST_V 0x00000001U +#define SPI_MEM_WPE_END_INT_ST_S 2 +/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (SPI_MEM_BROWN_OUT_INT_ST_V << SPI_MEM_BROWN_OUT_INT_ST_S) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x00000001U +#define SPI_MEM_BROWN_OUT_INT_ST_S 10 + +/** SPI_MEM_DDR_REG register + * SPI1 DDR control register + */ +#define SPI_MEM_DDR_REG (DR_REG_SPI_MEM_BASE + 0xd4) +/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ +#define SPI_MEM_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_M (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S) +#define SPI_MEM_FMEM_DDR_EN_V 0x00000001U +#define SPI_MEM_FMEM_DDR_EN_S 0 +/** SPI_MEM_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ +#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_M (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S) +#define SPI_MEM_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_MEM_FMEM_VAR_DUMMY_S 1 +/** SPI_MEM_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ +#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_MEM_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ +#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_MEM_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ +#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_M (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S) +#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 +/** SPI_MEM_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_FMEM_OUTMINBYTELEN_M (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S) +#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 +/** SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S) +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_MEM_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_MEM_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_M (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S) +#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 +/** SPI_MEM_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_M (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S) +#define SPI_MEM_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_MEM_FMEM_DQS_CA_IN_S 26 +/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_M (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S) +#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 +/** SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_MEM_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_M (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S) +#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_FMEM_HYPERBUS_CA_S 30 + +/** SPI_MEM_TIMING_CALI_REG register + * SPI1 timing control register + */ +#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_MEM_BASE + 0x180) +/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) +#define SPI_MEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_TIMING_CALI_S 1 +/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/** SPI_MEM_CLOCK_GATE_REG register + * SPI1 clk_gate register + */ +#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_MEM_BASE + 0x200) +/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (SPI_MEM_CLK_EN_V << SPI_MEM_CLK_EN_S) +#define SPI_MEM_CLK_EN_V 0x00000001U +#define SPI_MEM_CLK_EN_S 0 + +/** SPI_MEM_DATE_REG register + * Version control register + */ +#define SPI_MEM_DATE_REG (DR_REG_SPI_MEM_BASE + 0x3fc) +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400; + * Version control register + */ +#define SPI_MEM_DATE 0x0FFFFFFFU +#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) +#define SPI_MEM_DATE_V 0x0FFFFFFFU +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/spi1_mem_struct.h b/components/soc/esp32c61/include/soc/spi1_mem_struct.h new file mode 100644 index 0000000000..e002a4017e --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi1_mem_struct.h @@ -0,0 +1,1282 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * SPI1 memory command register + */ +typedef union { + struct { + /** mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t slv_st:4; + uint32_t reserved_8:9; + /** flash_pe : R/W/SC; bitpos: [17]; default: 0; + * In user mode, it is set to indicate that program/erase operation will be triggered. + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the + * operation done.1: enable 0: disable. + */ + uint32_t flash_pe:1; + /** usr : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t usr:1; + /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; + * Drive Flash into high performance mode. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t flash_hpm:1; + /** flash_res : R/W/SC; bitpos: [20]; default: 0; + * This bit combined with reg_resandres bit releases Flash from the power-down state + * or high performance mode and obtains the devices ID. The bit will be cleared once + * the operation done.1: enable 0: disable. + */ + uint32_t flash_res:1; + /** flash_dp : R/W/SC; bitpos: [21]; default: 0; + * Drive Flash into power down. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_dp:1; + /** flash_ce : R/W/SC; bitpos: [22]; default: 0; + * Chip erase enable. Chip erase operation will be triggered when the bit is set. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_ce:1; + /** flash_be : R/W/SC; bitpos: [23]; default: 0; + * Block erase enable(32KB) . Block erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_be:1; + /** flash_se : R/W/SC; bitpos: [24]; default: 0; + * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_se:1; + /** flash_pp : R/W/SC; bitpos: [25]; default: 0; + * Page program enable(1 byte ~256 bytes data to be programmed). Page program + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done .1: enable 0: disable. + */ + uint32_t flash_pp:1; + /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; + * Write status register enable. Write status operation will be triggered when the + * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_wrsr:1; + /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; + * Read status register-1. Read status operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_rdsr:1; + /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; + * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be + * cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_rdid:1; + /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; + * Write flash disable. Write disable command will be sent when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_wrdi:1; + /** flash_wren : R/W/SC; bitpos: [30]; default: 0; + * Write flash enable. Write enable command will be sent when the bit is set. The bit + * will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_wren:1; + /** flash_read : R/W/SC; bitpos: [31]; default: 0; + * Read flash enable. Read flash operation will be triggered when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_read:1; + }; + uint32_t val; +} spi_mem_cmd_reg_t; + +/** Type of addr register + * SPI1 address register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_mem_addr_reg_t; + +/** Type of user register + * SPI1 user register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + uint32_t fwrite_quad:1; + /** fwrite_dio : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ + uint32_t fwrite_dio:1; + /** fwrite_qio : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ + uint32_t fwrite_qio:1; + uint32_t reserved_16:8; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: + * enable 0: disable. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: + * enable 0: disable. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_mem_user_reg_t; + +/** Type of user1 register + * SPI1 user1 register. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t usr_dummy_cyclelen:6; + uint32_t reserved_6:20; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_user1_reg_t; + +/** Type of user2 register + * SPI1 user2 register. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI1 control register. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_wout:1; + /** fdout_oct : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t fdout_oct:1; + /** fdin_oct : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t fdin_oct:1; + /** faddr_oct : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t faddr_oct:1; + uint32_t reserved_7:1; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_oct:1; + /** fcs_crc_en : R/W; bitpos: [10]; default: 0; + * For SPI1, initialize crc32 module before writing encrypted data to flash. Active + * low. + */ + uint32_t fcs_crc_en:1; + /** tx_crc_en : R/W; bitpos: [11]; default: 0; + * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + */ + uint32_t tx_crc_en:1; + uint32_t reserved_12:1; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. + */ + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t fread_dual:1; + /** resandres : R/W; bitpos: [15]; default: 1; + * The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with + * spi_mem_flash_res bit. 1: enable 0: disable. + */ + uint32_t resandres:1; + uint32_t reserved_16:2; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t wp_reg:1; + /** wrsr_2b : R/W; bitpos: [22]; default: 0; + * two bytes data will be written to status register when it is set. 1: enable 0: + * disable. + */ + uint32_t wrsr_2b:1; + /** fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t fread_qio:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_mem_ctrl_reg_t; + +/** Type of ctrl1 register + * SPI1 control1 register. + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ + uint32_t clk_mode:2; + /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; + * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_res:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_ctrl1_reg_t; + +/** Type of ctrl2 register + * SPI1 control2 register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sync_reset : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ + uint32_t sync_reset:1; + }; + uint32_t val; +} spi_mem_ctrl2_reg_t; + +/** Type of clock register + * SPI1 clock division control register. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ + uint32_t clkcnt_n:8; + uint32_t reserved_24:7; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_clock_reg_t; + +/** Type of mosi_dlen register + * SPI1 send data bit length control register. + */ +typedef union { + struct { + /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + uint32_t usr_mosi_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_mosi_dlen_reg_t; + +/** Type of miso_dlen register + * SPI1 receive data bit length control register. + */ +typedef union { + struct { + /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + uint32_t usr_miso_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_miso_dlen_reg_t; + +/** Type of rd_status register + * SPI1 status register. + */ +typedef union { + struct { + /** status : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + */ + uint32_t status:16; + /** wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + */ + uint32_t wb_mode:8; + /** wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + */ + uint32_t wb_mode_bitlen:3; + /** wb_mode_en : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + */ + uint32_t wb_mode_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_rd_status_reg_t; + +/** Type of misc register + * SPI1 misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs1_dis:1; + uint32_t reserved_2:7; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ + uint32_t cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_misc_reg_t; + +/** Type of cache_fctrl register + * SPI1 bit mode control register. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ + uint32_t cache_usr_addr_4byte:1; + uint32_t reserved_2:1; + /** fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with + * spi_mem_fread_dio. + */ + uint32_t fdin_dual:1; + /** fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_dio. + */ + uint32_t fdout_dual:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_dio. + */ + uint32_t faddr_dual:1; + /** fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_qio. + */ + uint32_t fdin_quad:1; + /** fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_qio. + */ + uint32_t fdout_quad:1; + /** faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi_mem_fread_qio. + */ + uint32_t faddr_quad:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_cache_fctrl_reg_t; + +/** Type of flash_waiti_ctrl register + * SPI1 wait idle control register + */ +typedef union { + struct { + /** waiti_en : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ + uint32_t waiti_en:1; + /** waiti_dummy : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ + uint32_t waiti_dummy:1; + /** waiti_addr_en : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ + uint32_t waiti_addr_en:1; + /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; + * When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when + * SPI_MEM_WAITI_ADDR_EN is cleared. + */ + uint32_t waiti_addr_cyclelen:2; + uint32_t reserved_5:4; + /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ + uint32_t waiti_cmd_2b:1; + /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ + uint32_t waiti_dummy_cyclelen:6; + /** waiti_cmd : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ + uint32_t waiti_cmd:16; + }; + uint32_t val; +} spi_mem_flash_waiti_ctrl_reg_t; + +/** Type of flash_sus_ctrl register + * SPI1 flash suspend control register + */ +typedef union { + struct { + /** flash_per : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_per:1; + /** flash_pes : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_pes:1; + /** flash_per_wait_en : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ + uint32_t flash_per_wait_en:1; + /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ + uint32_t flash_pes_wait_en:1; + /** pes_per_en : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ + uint32_t pes_per_en:1; + /** flash_pes_en : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ + uint32_t flash_pes_en:1; + /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + */ + uint32_t pesr_end_msk:16; + /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ + uint32_t fmem_rd_sus_2b:1; + /** per_end_en : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ + uint32_t per_end_en:1; + /** pes_end_en : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ + uint32_t pes_end_en:1; + /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it + * will be treated as check pass. + */ + uint32_t sus_timeout_cnt:7; + }; + uint32_t val; +} spi_mem_flash_sus_ctrl_reg_t; + +/** Type of flash_sus_cmd register + * SPI1 flash suspend command register + */ +typedef union { + struct { + /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ + uint32_t flash_pes_command:16; + /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ + uint32_t wait_pesr_command:16; + }; + uint32_t val; +} spi_mem_flash_sus_cmd_reg_t; + +/** Type of sus_status register + * SPI1 flash suspend status register + */ +typedef union { + struct { + /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ + uint32_t flash_sus:1; + /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ + uint32_t wait_pesr_cmd_2b:1; + /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ + uint32_t flash_hpm_dly_128:1; + /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ + uint32_t flash_res_dly_128:1; + /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ + uint32_t flash_dp_dly_128:1; + /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: + * SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is + * sent. + */ + uint32_t flash_per_dly_128:1; + /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: + * SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is + * sent. + */ + uint32_t flash_pes_dly_128:1; + /** spi0_lock_en : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ + uint32_t spi0_lock_en:1; + uint32_t reserved_8:7; + /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ + uint32_t flash_pesr_cmd_2b:1; + /** flash_per_command : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ + uint32_t flash_per_command:16; + }; + uint32_t val; +} spi_mem_sus_status_reg_t; + +/** Type of flash_waiti_ctrl1 register + * SPI1 wait idle control register + */ +typedef union { + struct { + /** waiti_idle_delay_time : R/W; bitpos: [9:0]; default: 0; + * SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE. + */ + uint32_t waiti_idle_delay_time:10; + /** waiti_idle_delay_time_en : R/W; bitpos: [10]; default: 0; + * Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable. + */ + uint32_t waiti_idle_delay_time_en:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_flash_waiti_ctrl1_reg_t; + +/** Type of ddr register + * SPI1 DDR control register + */ +typedef union { + struct { + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + uint32_t reserved_12:2; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_ddr_reg_t; + +/** Type of clock_gate register + * SPI1 clk_gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_clock_gate_reg_t; + + +/** Group: Status register */ +/** Type of tx_crc register + * SPI1 TX CRC data register. + */ +typedef union { + struct { + /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295; + * For SPI1, the value of crc32. + */ + uint32_t tx_crc_data:32; + }; + uint32_t val; +} spi_mem_tx_crc_reg_t; + + +/** Group: Memory data buffer register */ +/** Type of word buffer register + * SPI1 memory data buffer_n + */ +typedef union { + struct { + /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi_mem_buffer_reg_t; + +/** Type of w1 register + * SPI1 memory data buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi_mem_w1_reg_t; + +/** Type of w2 register + * SPI1 memory data buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi_mem_w2_reg_t; + +/** Type of w3 register + * SPI1 memory data buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi_mem_w3_reg_t; + +/** Type of w4 register + * SPI1 memory data buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi_mem_w4_reg_t; + +/** Type of w5 register + * SPI1 memory data buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi_mem_w5_reg_t; + +/** Type of w6 register + * SPI1 memory data buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi_mem_w6_reg_t; + +/** Type of w7 register + * SPI1 memory data buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi_mem_w7_reg_t; + +/** Type of w8 register + * SPI1 memory data buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi_mem_w8_reg_t; + +/** Type of w9 register + * SPI1 memory data buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi_mem_w9_reg_t; + +/** Type of w10 register + * SPI1 memory data buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi_mem_w10_reg_t; + +/** Type of w11 register + * SPI1 memory data buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi_mem_w11_reg_t; + +/** Type of w12 register + * SPI1 memory data buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi_mem_w12_reg_t; + +/** Type of w13 register + * SPI1 memory data buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi_mem_w13_reg_t; + +/** Type of w14 register + * SPI1 memory data buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi_mem_w14_reg_t; + +/** Type of w15 register + * SPI1 memory data buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi_mem_w15_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena register + * SPI1 interrupt enable register + */ +typedef union { + struct { + /** per_end_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_ena:1; + /** pes_end_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_ena:1; + /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_ena:1; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_ena:1; + uint32_t reserved_5:5; + /** brown_out_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_ena:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_int_ena_reg_t; + +/** Type of int_clr register + * SPI1 interrupt clear register + */ +typedef union { + struct { + /** per_end_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_clr:1; + /** pes_end_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_clr:1; + /** wpe_end_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_clr:1; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_clr:1; + uint32_t reserved_5:5; + /** brown_out_int_clr : WT; bitpos: [10]; default: 0; + * The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_clr:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_int_clr_reg_t; + +/** Type of int_raw register + * SPI1 interrupt raw register + */ +typedef union { + struct { + /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ + uint32_t per_end_int_raw:1; + /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ + uint32_t pes_end_int_raw:1; + /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ + uint32_t wpe_end_int_raw:1; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mst_st_end_int_raw:1; + uint32_t reserved_5:5; + /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is loosing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ + uint32_t brown_out_int_raw:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_int_raw_reg_t; + +/** Type of int_st register + * SPI1 interrupt status register + */ +typedef union { + struct { + /** per_end_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_st:1; + /** pes_end_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_st:1; + /** wpe_end_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_st:1; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_st:1; + uint32_t reserved_5:5; + /** brown_out_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_st:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_int_st_reg_t; + + +/** Group: Timing registers */ +/** Type of timing_cali register + * SPI1 timing control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t extra_dummy_cyclelen:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_timing_cali_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36774400; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_date_reg_t; + + +typedef struct { + volatile spi_mem_cmd_reg_t cmd; + volatile spi_mem_addr_reg_t addr; + volatile spi_mem_ctrl_reg_t ctrl; + volatile spi_mem_ctrl1_reg_t ctrl1; + volatile spi_mem_ctrl2_reg_t ctrl2; + volatile spi_mem_clock_reg_t clock; + volatile spi_mem_user_reg_t user; + volatile spi_mem_user1_reg_t user1; + volatile spi_mem_user2_reg_t user2; + volatile spi_mem_mosi_dlen_reg_t mosi_dlen; + volatile spi_mem_miso_dlen_reg_t miso_dlen; + volatile spi_mem_rd_status_reg_t rd_status; + uint32_t reserved_030; + volatile spi_mem_misc_reg_t misc; + volatile spi_mem_tx_crc_reg_t tx_crc; + volatile spi_mem_cache_fctrl_reg_t cache_fctrl; + uint32_t reserved_040[6]; + volatile spi_mem_buffer_reg_t word[16]; + volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl; + volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl; + volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd; + volatile spi_mem_sus_status_reg_t sus_status; + uint32_t reserved_0a8; + volatile spi_mem_flash_waiti_ctrl1_reg_t flash_waiti_ctrl1; + uint32_t reserved_0b0[4]; + volatile spi_mem_int_ena_reg_t int_ena; + volatile spi_mem_int_clr_reg_t int_clr; + volatile spi_mem_int_raw_reg_t int_raw; + volatile spi_mem_int_st_reg_t int_st; + uint32_t reserved_0d0; + volatile spi_mem_ddr_reg_t ddr; + uint32_t reserved_0d8[42]; + volatile spi_mem_timing_cali_reg_t timing_cali; + uint32_t reserved_184[31]; + volatile spi_mem_clock_gate_reg_t clock_gate; + uint32_t reserved_204[126]; + volatile spi_mem_date_reg_t date; +} spi_mem_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/spi_mem_reg.h b/components/soc/esp32c61/include/soc/spi_mem_reg.h new file mode 100644 index 0000000000..cb2bf6b5b7 --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi_mem_reg.h @@ -0,0 +1,3907 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_CMD_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0) +/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ +#define SPI_MEM_MST_ST 0x0000000FU +#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) +#define SPI_MEM_MST_ST_V 0x0000000FU +#define SPI_MEM_MST_ST_S 0 +/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_SLV_ST 0x0000000FU +#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) +#define SPI_MEM_SLV_ST_V 0x0000000FU +#define SPI_MEM_SLV_ST_S 4 +/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) +#define SPI_MEM_USR_V 0x00000001U +#define SPI_MEM_USR_S 18 + +/** SPI_MEM_CTRL_REG register + * SPI0 control register. + */ +#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8) +/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) +#define SPI_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_FDUMMY_RIN_S 2 +/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) +#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_FDUMMY_WOUT_S 3 +/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) +#define SPI_MEM_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_FDOUT_OCT_S 4 +/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) +#define SPI_MEM_FDIN_OCT_V 0x00000001U +#define SPI_MEM_FDIN_OCT_S 5 +/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) +#define SPI_MEM_FADDR_OCT_V 0x00000001U +#define SPI_MEM_FADDR_OCT_S 6 +/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) +#define SPI_MEM_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_FCMD_QUAD_S 8 +/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) +#define SPI_MEM_FCMD_OCT_V 0x00000001U +#define SPI_MEM_FCMD_OCT_S 9 +/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) +#define SPI_MEM_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_FASTRD_MODE_S 13 +/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) +#define SPI_MEM_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_FREAD_DUAL_S 14 +/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) +#define SPI_MEM_Q_POL_V 0x00000001U +#define SPI_MEM_Q_POL_S 18 +/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) +#define SPI_MEM_D_POL_V 0x00000001U +#define SPI_MEM_D_POL_S 19 +/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) +#define SPI_MEM_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_FREAD_QUAD_S 20 +/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) +#define SPI_MEM_WP_REG_V 0x00000001U +#define SPI_MEM_WP_REG_S 21 +/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) +#define SPI_MEM_FREAD_DIO_V 0x00000001U +#define SPI_MEM_FREAD_DIO_S 23 +/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) +#define SPI_MEM_FREAD_QIO_V 0x00000001U +#define SPI_MEM_FREAD_QIO_S 24 +/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_CTRL1_REG register + * SPI0 control1 register. + */ +#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc) +/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ +#define SPI_MEM_CLK_MODE 0x00000003U +#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) +#define SPI_MEM_CLK_MODE_V 0x00000003U +#define SPI_MEM_CLK_MODE_S 0 +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ +#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) +#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U +#define SPI_AXI_RDATA_BACK_FAST_S 23 +/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) +#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AR_SPLICE_EN_S 25 +/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) +#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AW_SPLICE_EN_S 26 +/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) +#define SPI_MEM_RAM0_EN_V 0x00000001U +#define SPI_MEM_RAM0_EN_S 27 +/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) +#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_DUAL_RAM_EN_S 28 +/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) +#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_FAST_WRITE_EN_S 29 +/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) +#define SPI_MEM_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_RXFIFO_RST_S 30 +/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) +#define SPI_MEM_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_TXFIFO_RST_S 31 + +/** SPI_MEM_CTRL2_REG register + * SPI0 control2 register. + */ +#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10) +/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ +#define SPI_MEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) +#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_S 0 +/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ +#define SPI_MEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) +#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_S 5 +/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) +#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) +#define SPI_MEM_SYNC_RESET_V 0x00000001U +#define SPI_MEM_SYNC_RESET_S 31 + +/** SPI_MEM_CLOCK_REG register + * SPI clock division control register. + */ +#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14) +/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_CLKCNT_L 0x000000FFU +#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) +#define SPI_MEM_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_CLKCNT_L_S 0 +/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_CLKCNT_H 0x000000FFU +#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) +#define SPI_MEM_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_CLKCNT_H_S 8 +/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_CLKCNT_N 0x000000FFU +#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) +#define SPI_MEM_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_CLKCNT_N_S 16 +/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_USER_REG register + * SPI0 user register. + */ +#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18) +/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) +#define SPI_MEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_CS_HOLD_S 6 +/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) +#define SPI_MEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_CS_SETUP_S 7 +/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) +#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_CK_OUT_EDGE_S 9 +/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) +#define SPI_MEM_USR_DUMMY_V 0x00000001U +#define SPI_MEM_USR_DUMMY_S 29 + +/** SPI_MEM_USER1_REG register + * SPI0 user1 register. + */ +#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c) +/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ +#define SPI_MEM_USR_DBYTELEN 0x0000003FU +#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) +#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU +#define SPI_MEM_USR_DBYTELEN_S 6 +/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_USER2_REG register + * SPI0 user2 register. + */ +#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20) +/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) +#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_RD_STATUS_REG register + * SPI0 read control register. + */ +#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_BASE + 0x2c) +/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + */ +#define SPI_MEM_WB_MODE 0x000000FFU +#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) +#define SPI_MEM_WB_MODE_V 0x000000FFU +#define SPI_MEM_WB_MODE_S 16 +/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + */ +#define SPI_MEM_WB_MODE_BITLEN 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) +#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_S 24 +/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + */ +#define SPI_MEM_WB_MODE_EN (BIT(27)) +#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) +#define SPI_MEM_WB_MODE_EN_V 0x00000001U +#define SPI_MEM_WB_MODE_EN_S 27 + +/** SPI_MEM_MISC_REG register + * SPI0 misc register + */ +#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34) +/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) +#define SPI_MEM_FSUB_PIN_V 0x00000001U +#define SPI_MEM_FSUB_PIN_S 7 +/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) +#define SPI_MEM_SSUB_PIN_V 0x00000001U +#define SPI_MEM_SSUB_PIN_S 8 +/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) +#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_CACHE_FCTRL_REG register + * SPI0 bit mode control register. + */ +#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c) +/** SPI_MEM_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + */ +#define SPI_MEM_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_M (SPI_MEM_AXI_REQ_EN_V << SPI_MEM_AXI_REQ_EN_S) +#define SPI_MEM_AXI_REQ_EN_V 0x00000001U +#define SPI_MEM_AXI_REQ_EN_S 0 +/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI_MEM_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + */ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (SPI_MEM_CACHE_FLASH_USR_CMD_V << SPI_MEM_CACHE_FLASH_USR_CMD_S) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x00000001U +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + */ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) +#define SPI_MEM_FDIN_DUAL_V 0x00000001U +#define SPI_MEM_FDIN_DUAL_S 3 +/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + */ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) +#define SPI_MEM_FDOUT_DUAL_V 0x00000001U +#define SPI_MEM_FDOUT_DUAL_S 4 +/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + */ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) +#define SPI_MEM_FADDR_DUAL_V 0x00000001U +#define SPI_MEM_FADDR_DUAL_S 5 +/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + */ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) +#define SPI_MEM_FDIN_QUAD_V 0x00000001U +#define SPI_MEM_FDIN_QUAD_S 6 +/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + */ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) +#define SPI_MEM_FDOUT_QUAD_V 0x00000001U +#define SPI_MEM_FDOUT_QUAD_S 7 +/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + */ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) +#define SPI_MEM_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_FADDR_QUAD_S 8 +/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ +#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ +#define SPI_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_CLOSE_AXI_INF_EN_S 31 + +/** SPI_MEM_CACHE_SCTRL_REG register + * SPI0 external RAM control register + */ +#define SPI_MEM_CACHE_SCTRL_REG (DR_REG_SPI_BASE + 0x40) +/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + */ +#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 +/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + */ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) +#define SPI_MEM_USR_SRAM_DIO_V 0x00000001U +#define SPI_MEM_USR_SRAM_DIO_S 1 +/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + */ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) +#define SPI_MEM_USR_SRAM_QIO_V 0x00000001U +#define SPI_MEM_USR_SRAM_QIO_S 2 +/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + */ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + */ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + */ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + */ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + */ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + */ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) +#define SPI_MEM_SRAM_OCT_V 0x00000001U +#define SPI_MEM_SRAM_OCT_S 21 +/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + */ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_SRAM_WDUMMY_CYCLELEN_S) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 + +/** SPI_MEM_SRAM_CMD_REG register + * SPI0 external RAM mode control register + */ +#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44) +/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI_MEM_SCLK_MODE 0x00000003U +#define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) +#define SPI_MEM_SCLK_MODE_V 0x00000003U +#define SPI_MEM_SCLK_MODE_S 0 +/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + */ +#define SPI_MEM_SWB_MODE 0x000000FFU +#define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) +#define SPI_MEM_SWB_MODE_V 0x000000FFU +#define SPI_MEM_SWB_MODE_S 2 +/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + */ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) +#define SPI_MEM_SDIN_DUAL_V 0x00000001U +#define SPI_MEM_SDIN_DUAL_S 10 +/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + */ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) +#define SPI_MEM_SDOUT_DUAL_V 0x00000001U +#define SPI_MEM_SDOUT_DUAL_S 11 +/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + */ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) +#define SPI_MEM_SADDR_DUAL_V 0x00000001U +#define SPI_MEM_SADDR_DUAL_S 12 +/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) +#define SPI_MEM_SDIN_QUAD_V 0x00000001U +#define SPI_MEM_SDIN_QUAD_S 14 +/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) +#define SPI_MEM_SDOUT_QUAD_V 0x00000001U +#define SPI_MEM_SDOUT_QUAD_S 15 +/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) +#define SPI_MEM_SADDR_QUAD_V 0x00000001U +#define SPI_MEM_SADDR_QUAD_S 16 +/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) +#define SPI_MEM_SCMD_QUAD_V 0x00000001U +#define SPI_MEM_SCMD_QUAD_S 17 +/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + */ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) +#define SPI_MEM_SDIN_OCT_V 0x00000001U +#define SPI_MEM_SDIN_OCT_S 18 +/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + */ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) +#define SPI_MEM_SDOUT_OCT_V 0x00000001U +#define SPI_MEM_SDOUT_OCT_S 19 +/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) +#define SPI_MEM_SADDR_OCT_V 0x00000001U +#define SPI_MEM_SADDR_OCT_S 20 +/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + */ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (SPI_MEM_SCMD_OCT_V << SPI_MEM_SCMD_OCT_S) +#define SPI_MEM_SCMD_OCT_V 0x00000001U +#define SPI_MEM_SCMD_OCT_S 21 +/** SPI_MEM_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ +#define SPI_MEM_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) +#define SPI_MEM_SDUMMY_RIN_V 0x00000001U +#define SPI_MEM_SDUMMY_RIN_S 22 +/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ +#define SPI_MEM_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) +#define SPI_MEM_SDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_SDUMMY_WOUT_S 23 +/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_MEM_SDIN_HEX : HRO; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + */ +#define SPI_MEM_SDIN_HEX (BIT(26)) +#define SPI_MEM_SDIN_HEX_M (SPI_MEM_SDIN_HEX_V << SPI_MEM_SDIN_HEX_S) +#define SPI_MEM_SDIN_HEX_V 0x00000001U +#define SPI_MEM_SDIN_HEX_S 26 +/** SPI_MEM_SDOUT_HEX : HRO; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + */ +#define SPI_MEM_SDOUT_HEX (BIT(27)) +#define SPI_MEM_SDOUT_HEX_M (SPI_MEM_SDOUT_HEX_V << SPI_MEM_SDOUT_HEX_S) +#define SPI_MEM_SDOUT_HEX_V 0x00000001U +#define SPI_MEM_SDOUT_HEX_S 27 +/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ +#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ +#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_SRAM_DRD_CMD_REG register + * SPI0 external RAM DDR read command control register + */ +#define SPI_MEM_SRAM_DRD_CMD_REG (DR_REG_SPI_BASE + 0x48) +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + */ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + */ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/** SPI_MEM_SRAM_DWR_CMD_REG register + * SPI0 external RAM DDR write command control register + */ +#define SPI_MEM_SRAM_DWR_CMD_REG (DR_REG_SPI_BASE + 0x4c) +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + */ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + */ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/** SPI_MEM_SRAM_CLK_REG register + * SPI0 external RAM clock control register + */ +#define SPI_MEM_SRAM_CLK_REG (DR_REG_SPI_BASE + 0x50) +/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_SCLKCNT_L 0x000000FFU +#define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) +#define SPI_MEM_SCLKCNT_L_V 0x000000FFU +#define SPI_MEM_SCLKCNT_L_S 0 +/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_SCLKCNT_H 0x000000FFU +#define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) +#define SPI_MEM_SCLKCNT_H_V 0x000000FFU +#define SPI_MEM_SCLKCNT_H_S 8 +/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_SCLKCNT_N 0x000000FFU +#define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) +#define SPI_MEM_SCLKCNT_N_V 0x000000FFU +#define SPI_MEM_SCLKCNT_N_S 16 +/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk + * is divided from system clock. + */ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_FSM_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54) +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_S 7 +/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [12]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_FLASH_LOCK_EN (BIT(12)) +#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) +#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U +#define SPI_MEM_FLASH_LOCK_EN_S 12 +/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [13]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_SRAM_LOCK_EN (BIT(13)) +#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) +#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U +#define SPI_MEM_SRAM_LOCK_EN_S 13 + +/** SPI_MEM_INT_ENA_REG register + * SPI0 interrupt enable register + */ +#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0) +/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 + +/** SPI_MEM_INT_CLR_REG register + * SPI0 interrupt clear register + */ +#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4) +/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 + +/** SPI_MEM_INT_RAW_REG register + * SPI0 interrupt raw register + */ +#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8) +/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 + +/** SPI_MEM_INT_ST_REG register + * SPI0 interrupt status register + */ +#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc) +/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 + +/** SPI_MEM_DDR_REG register + * SPI0 flash DDR mode control register + */ +#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4) +/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) +#define SPI_FMEM_DDR_EN_V 0x00000001U +#define SPI_FMEM_DDR_EN_S 0 +/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) +#define SPI_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_FMEM_VAR_DUMMY_S 1 +/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) +#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) +#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) +#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_FMEM_DDR_CMD_DIS_S 4 +/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) +#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_S 5 +/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ +#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) +#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_TX_DDR_MSK_EN_S 12 +/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ +#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) +#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_RX_DDR_MSK_EN_S 13 +/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) +#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) +#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) +#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_EN_S 24 +/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) +#define SPI_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_FMEM_DQS_CA_IN_S 26 +/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) +#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_INV_S 28 +/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) +#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) +#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_FMEM_HYPERBUS_CA_S 30 + +/** SPI_SMEM_DDR_REG register + * SPI0 external RAM DDR mode control register + */ +#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8) +/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) +#define SPI_SMEM_DDR_EN_V 0x00000001U +#define SPI_SMEM_DDR_EN_S 0 +/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) +#define SPI_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_SMEM_VAR_DUMMY_S 1 +/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) +#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) +#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) +#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_SMEM_DDR_CMD_DIS_S 4 +/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ +#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) +#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_S 5 +/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) +#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) +#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) +#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) +#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) +#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_EN_S 24 +/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) +#define SPI_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_SMEM_DQS_CA_IN_S 26 +/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ +#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) +#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_INV_S 28 +/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ +#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) +#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) +#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_SMEM_HYPERBUS_CA_S 30 + +/** SPI_FMEM_PMS0_ATTR_REG register + * MSPI flash PMS section 0 attribute register + */ +#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100) +/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) +#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_RD_ATTR_S 0 +/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) +#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_WR_ATTR_S 1 +/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and + * SPI_FMEM_PMS0_SIZE_REG. + */ +#define SPI_FMEM_PMS0_ECC (BIT(2)) +#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) +#define SPI_FMEM_PMS0_ECC_V 0x00000001U +#define SPI_FMEM_PMS0_ECC_S 2 + +/** SPI_FMEM_PMS1_ATTR_REG register + * MSPI flash PMS section 1 attribute register + */ +#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104) +/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) +#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_RD_ATTR_S 0 +/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) +#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_WR_ATTR_S 1 +/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and + * SPI_FMEM_PMS1_SIZE_REG. + */ +#define SPI_FMEM_PMS1_ECC (BIT(2)) +#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) +#define SPI_FMEM_PMS1_ECC_V 0x00000001U +#define SPI_FMEM_PMS1_ECC_S 2 + +/** SPI_FMEM_PMS2_ATTR_REG register + * MSPI flash PMS section 2 attribute register + */ +#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108) +/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) +#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_RD_ATTR_S 0 +/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) +#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_WR_ATTR_S 1 +/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and + * SPI_FMEM_PMS2_SIZE_REG. + */ +#define SPI_FMEM_PMS2_ECC (BIT(2)) +#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) +#define SPI_FMEM_PMS2_ECC_V 0x00000001U +#define SPI_FMEM_PMS2_ECC_S 2 + +/** SPI_FMEM_PMS3_ATTR_REG register + * MSPI flash PMS section 3 attribute register + */ +#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c) +/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) +#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_RD_ATTR_S 0 +/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) +#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_WR_ATTR_S 1 +/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and + * SPI_FMEM_PMS3_SIZE_REG. + */ +#define SPI_FMEM_PMS3_ECC (BIT(2)) +#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) +#define SPI_FMEM_PMS3_ECC_V 0x00000001U +#define SPI_FMEM_PMS3_ECC_S 2 + +/** SPI_FMEM_PMS0_ADDR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110) +/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 0 start address value + */ +#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) +#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_S 0 + +/** SPI_FMEM_PMS1_ADDR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114) +/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 1 start address value + */ +#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) +#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_S 0 + +/** SPI_FMEM_PMS2_ADDR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118) +/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 2 start address value + */ +#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) +#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_S 0 + +/** SPI_FMEM_PMS3_ADDR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c) +/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section 3 start address value + */ +#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) +#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_S 0 + +/** SPI_FMEM_PMS0_SIZE_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120) +/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, + * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) + */ +#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) +#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS0_SIZE_S 0 + +/** SPI_FMEM_PMS1_SIZE_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124) +/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, + * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) + */ +#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) +#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS1_SIZE_S 0 + +/** SPI_FMEM_PMS2_SIZE_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128) +/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, + * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) + */ +#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) +#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS2_SIZE_S 0 + +/** SPI_FMEM_PMS3_SIZE_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c) +/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, + * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) + */ +#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU +#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) +#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU +#define SPI_FMEM_PMS3_SIZE_S 0 + +/** SPI_SMEM_PMS0_ATTR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130) +/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) +#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) +#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and + * SPI_SMEM_PMS0_SIZE_REG. + */ +#define SPI_SMEM_PMS0_ECC (BIT(2)) +#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) +#define SPI_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_SMEM_PMS0_ECC_S 2 + +/** SPI_SMEM_PMS1_ATTR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134) +/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) +#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) +#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and + * SPI_SMEM_PMS1_SIZE_REG. + */ +#define SPI_SMEM_PMS1_ECC (BIT(2)) +#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) +#define SPI_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_SMEM_PMS1_ECC_S 2 + +/** SPI_SMEM_PMS2_ATTR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138) +/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) +#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) +#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and + * SPI_SMEM_PMS2_SIZE_REG. + */ +#define SPI_SMEM_PMS2_ECC (BIT(2)) +#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) +#define SPI_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_SMEM_PMS2_ECC_S 2 + +/** SPI_SMEM_PMS3_ATTR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c) +/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) +#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) +#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and + * SPI_SMEM_PMS3_SIZE_REG. + */ +#define SPI_SMEM_PMS3_ECC (BIT(2)) +#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) +#define SPI_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_SMEM_PMS3_ECC_S 2 + +/** SPI_SMEM_PMS0_ADDR_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140) +/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 0 start address value + */ +#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) +#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_S 0 + +/** SPI_SMEM_PMS1_ADDR_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144) +/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value + */ +#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) +#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_S 0 + +/** SPI_SMEM_PMS2_ADDR_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148) +/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value + */ +#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) +#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_S 0 + +/** SPI_SMEM_PMS3_ADDR_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c) +/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value + */ +#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) +#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_S 0 + +/** SPI_SMEM_PMS0_SIZE_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150) +/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, + * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) + */ +#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) +#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS0_SIZE_S 0 + +/** SPI_SMEM_PMS1_SIZE_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154) +/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, + * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) + */ +#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) +#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS1_SIZE_S 0 + +/** SPI_SMEM_PMS2_SIZE_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158) +/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, + * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) + */ +#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) +#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS2_SIZE_S 0 + +/** SPI_SMEM_PMS3_SIZE_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c) +/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, + * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) + */ +#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU +#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) +#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU +#define SPI_SMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_PMS_REJECT_REG register + * SPI1 access reject register + */ +#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x160) +/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ +#define SPI_MEM_PM_EN (BIT(27)) +#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) +#define SPI_MEM_PM_EN_V 0x00000001U +#define SPI_MEM_PM_EN_S 27 +/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) +#define SPI_MEM_PMS_LD_V 0x00000001U +#define SPI_MEM_PMS_LD_S 28 +/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) +#define SPI_MEM_PMS_ST_V 0x00000001U +#define SPI_MEM_PMS_ST_S 29 +/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) +#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) +#define SPI_MEM_PMS_IVD_V 0x00000001U +#define SPI_MEM_PMS_IVD_S 31 + +/** SPI_MEM_PMS_REJECT_ADDR_REG register + * SPI1 access reject addr register + */ +#define SPI_MEM_PMS_REJECT_ADDR_REG (DR_REG_SPI_BASE + 0x164) +/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) +#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_S 0 + +/** SPI_MEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168) +/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) +#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_S 5 +/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) +#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 +/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ +#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) +#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_FMEM_ECC_ERR_INT_EN_S 17 +/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ +#define SPI_FMEM_PAGE_SIZE 0x00000003U +#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) +#define SPI_FMEM_PAGE_SIZE_V 0x00000003U +#define SPI_FMEM_PAGE_SIZE_S 18 +/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ +#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) +#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) +#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_FMEM_ECC_ADDR_EN_S 21 +/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_USR_ECC_ADDR_EN_S 22 +/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ +#define SPI_MEM_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) +#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_S 25 + +/** SPI_MEM_ECC_ERR_ADDR_REG register + * MSPI ECC error address register + */ +#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c) +/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) +#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +/** SPI_MEM_AXI_ERR_ADDR_REG register + * SPI0 AXI request error address. + */ +#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170) +/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ +#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) +#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +/** SPI_SMEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174) +/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ +#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) +#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ +#define SPI_SMEM_PAGE_SIZE 0x00000003U +#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) +#define SPI_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_SMEM_PAGE_SIZE_S 18 +/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ +#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) +#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_SMEM_ECC_ADDR_EN_S 20 + +/** SPI_SMEM_AXI_ADDR_CTRL_REG register + * SPI0 AXI address control register + */ +#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178) +/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 +/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) +#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_RDATA_AFIFO_REMPTY_S 27 +/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) +#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_RADDR_AFIFO_REMPTY_S 28 +/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) +#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_WDATA_AFIFO_REMPTY_S 29 +/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) +#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 + +/** SPI_MEM_AXI_ERR_RESP_EN_REG register + * SPI0 AXI error response enable register + */ +#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c) +/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 + +/** SPI_MEM_TIMING_CALI_REG register + * SPI0 flash timing calibration register + */ +#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180) +/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) +#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) +#define SPI_MEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_TIMING_CALI_S 1 +/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) +#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 + +/** SPI_MEM_DIN_MODE_REG register + * MSPI flash input timing delay mode control register + */ +#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184) +/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN0_MODE 0x00000007U +#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) +#define SPI_MEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_DIN0_MODE_S 0 +/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN1_MODE 0x00000007U +#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) +#define SPI_MEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_DIN1_MODE_S 3 +/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN2_MODE 0x00000007U +#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) +#define SPI_MEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_DIN2_MODE_S 6 +/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN3_MODE 0x00000007U +#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) +#define SPI_MEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_DIN3_MODE_S 9 +/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN4_MODE 0x00000007U +#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) +#define SPI_MEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_DIN4_MODE_S 12 +/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN5_MODE 0x00000007U +#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) +#define SPI_MEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_DIN5_MODE_S 15 +/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN6_MODE 0x00000007U +#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) +#define SPI_MEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_DIN6_MODE_S 18 +/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN7_MODE 0x00000007U +#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) +#define SPI_MEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_DIN7_MODE_S 21 +/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DINS_MODE 0x00000007U +#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) +#define SPI_MEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_DINS_MODE_S 24 + +/** SPI_MEM_DIN_NUM_REG register + * MSPI flash input timing delay number control register + */ +#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188) +/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN0_NUM 0x00000003U +#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) +#define SPI_MEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_DIN0_NUM_S 0 +/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN1_NUM 0x00000003U +#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) +#define SPI_MEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_DIN1_NUM_S 2 +/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN2_NUM 0x00000003U +#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) +#define SPI_MEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_DIN2_NUM_S 4 +/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN3_NUM 0x00000003U +#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) +#define SPI_MEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_DIN3_NUM_S 6 +/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN4_NUM 0x00000003U +#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) +#define SPI_MEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_DIN4_NUM_S 8 +/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN5_NUM 0x00000003U +#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) +#define SPI_MEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_DIN5_NUM_S 10 +/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN6_NUM 0x00000003U +#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) +#define SPI_MEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_DIN6_NUM_S 12 +/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN7_NUM 0x00000003U +#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) +#define SPI_MEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_DIN7_NUM_S 14 +/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DINS_NUM 0x00000003U +#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) +#define SPI_MEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_DINS_NUM_S 16 + +/** SPI_MEM_DOUT_MODE_REG register + * MSPI flash output timing adjustment control register + */ +#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c) +/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) +#define SPI_MEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_DOUT0_MODE_S 0 +/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) +#define SPI_MEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_DOUT1_MODE_S 1 +/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) +#define SPI_MEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_DOUT2_MODE_S 2 +/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) +#define SPI_MEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_DOUT3_MODE_S 3 +/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) +#define SPI_MEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_DOUT4_MODE_S 4 +/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) +#define SPI_MEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_DOUT5_MODE_S 5 +/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) +#define SPI_MEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_DOUT6_MODE_S 6 +/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) +#define SPI_MEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_DOUT7_MODE_S 7 +/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) +#define SPI_MEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_TIMING_CALI_REG register + * MSPI external RAM timing calibration register + */ +#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190) +/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) +#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ +#define SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) +#define SPI_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_TIMING_CALI_S 1 +/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ +#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) +#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_DLL_TIMING_CALI_S 5 +/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_270_SEL 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) +#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_S 7 +/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_90_SEL 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) +#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_S 9 + +/** SPI_SMEM_DIN_MODE_REG register + * MSPI external RAM input timing delay mode control register + */ +#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194) +/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN0_MODE 0x00000007U +#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) +#define SPI_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_SMEM_DIN0_MODE_S 0 +/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN1_MODE 0x00000007U +#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) +#define SPI_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_SMEM_DIN1_MODE_S 3 +/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN2_MODE 0x00000007U +#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) +#define SPI_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_SMEM_DIN2_MODE_S 6 +/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN3_MODE 0x00000007U +#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) +#define SPI_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_SMEM_DIN3_MODE_S 9 +/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN4_MODE 0x00000007U +#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) +#define SPI_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_SMEM_DIN4_MODE_S 12 +/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN5_MODE 0x00000007U +#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) +#define SPI_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_SMEM_DIN5_MODE_S 15 +/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN6_MODE 0x00000007U +#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) +#define SPI_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_SMEM_DIN6_MODE_S 18 +/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN7_MODE 0x00000007U +#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) +#define SPI_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_SMEM_DIN7_MODE_S 21 +/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DINS_MODE 0x00000007U +#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) +#define SPI_SMEM_DINS_MODE_V 0x00000007U +#define SPI_SMEM_DINS_MODE_S 24 + +/** SPI_SMEM_DIN_NUM_REG register + * MSPI external RAM input timing delay number control register + */ +#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198) +/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN0_NUM 0x00000003U +#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) +#define SPI_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_SMEM_DIN0_NUM_S 0 +/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN1_NUM 0x00000003U +#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) +#define SPI_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_SMEM_DIN1_NUM_S 2 +/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN2_NUM 0x00000003U +#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) +#define SPI_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_SMEM_DIN2_NUM_S 4 +/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN3_NUM 0x00000003U +#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) +#define SPI_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_SMEM_DIN3_NUM_S 6 +/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN4_NUM 0x00000003U +#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) +#define SPI_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_SMEM_DIN4_NUM_S 8 +/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN5_NUM 0x00000003U +#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) +#define SPI_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_SMEM_DIN5_NUM_S 10 +/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN6_NUM 0x00000003U +#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) +#define SPI_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_SMEM_DIN6_NUM_S 12 +/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN7_NUM 0x00000003U +#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) +#define SPI_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_SMEM_DIN7_NUM_S 14 +/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DINS_NUM 0x00000003U +#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) +#define SPI_SMEM_DINS_NUM_V 0x00000003U +#define SPI_SMEM_DINS_NUM_S 16 + +/** SPI_SMEM_DOUT_MODE_REG register + * MSPI external RAM output timing adjustment control register + */ +#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c) +/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) +#define SPI_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_SMEM_DOUT0_MODE_S 0 +/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) +#define SPI_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_SMEM_DOUT1_MODE_S 1 +/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) +#define SPI_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_SMEM_DOUT2_MODE_S 2 +/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) +#define SPI_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_SMEM_DOUT3_MODE_S 3 +/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) +#define SPI_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_SMEM_DOUT4_MODE_S 4 +/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) +#define SPI_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_SMEM_DOUT5_MODE_S 5 +/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) +#define SPI_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_SMEM_DOUT6_MODE_S 6 +/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) +#define SPI_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_SMEM_DOUT7_MODE_S 7 +/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) +#define SPI_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_SMEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_AC_REG register + * MSPI external RAM ECC and SPI CS timing control register + */ +#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0) +/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ +#define SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) +#define SPI_SMEM_CS_SETUP_V 0x00000001U +#define SPI_SMEM_CS_SETUP_S 0 +/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) +#define SPI_SMEM_CS_HOLD_V 0x00000001U +#define SPI_SMEM_CS_HOLD_S 1 +/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ +#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) +#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_S 2 +/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ +#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) +#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_S 7 +/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ +#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ +#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) +#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ +#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) +#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_SMEM_SPLIT_TRANS_EN_S 31 + +/** SPI_SMEM_DIN_HEX_MODE_REG register + * MSPI 16x external RAM input timing delay mode control register + */ +#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1a4) +/** SPI_SMEM_DIN08_MODE : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN08_MODE 0x00000007U +#define SPI_SMEM_DIN08_MODE_M (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S) +#define SPI_SMEM_DIN08_MODE_V 0x00000007U +#define SPI_SMEM_DIN08_MODE_S 0 +/** SPI_SMEM_DIN09_MODE : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN09_MODE 0x00000007U +#define SPI_SMEM_DIN09_MODE_M (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S) +#define SPI_SMEM_DIN09_MODE_V 0x00000007U +#define SPI_SMEM_DIN09_MODE_S 3 +/** SPI_SMEM_DIN10_MODE : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN10_MODE 0x00000007U +#define SPI_SMEM_DIN10_MODE_M (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S) +#define SPI_SMEM_DIN10_MODE_V 0x00000007U +#define SPI_SMEM_DIN10_MODE_S 6 +/** SPI_SMEM_DIN11_MODE : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN11_MODE 0x00000007U +#define SPI_SMEM_DIN11_MODE_M (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S) +#define SPI_SMEM_DIN11_MODE_V 0x00000007U +#define SPI_SMEM_DIN11_MODE_S 9 +/** SPI_SMEM_DIN12_MODE : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN12_MODE 0x00000007U +#define SPI_SMEM_DIN12_MODE_M (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S) +#define SPI_SMEM_DIN12_MODE_V 0x00000007U +#define SPI_SMEM_DIN12_MODE_S 12 +/** SPI_SMEM_DIN13_MODE : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN13_MODE 0x00000007U +#define SPI_SMEM_DIN13_MODE_M (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S) +#define SPI_SMEM_DIN13_MODE_V 0x00000007U +#define SPI_SMEM_DIN13_MODE_S 15 +/** SPI_SMEM_DIN14_MODE : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN14_MODE 0x00000007U +#define SPI_SMEM_DIN14_MODE_M (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S) +#define SPI_SMEM_DIN14_MODE_V 0x00000007U +#define SPI_SMEM_DIN14_MODE_S 18 +/** SPI_SMEM_DIN15_MODE : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN15_MODE 0x00000007U +#define SPI_SMEM_DIN15_MODE_M (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S) +#define SPI_SMEM_DIN15_MODE_V 0x00000007U +#define SPI_SMEM_DIN15_MODE_S 21 +/** SPI_SMEM_DINS_HEX_MODE : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DINS_HEX_MODE 0x00000007U +#define SPI_SMEM_DINS_HEX_MODE_M (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S) +#define SPI_SMEM_DINS_HEX_MODE_V 0x00000007U +#define SPI_SMEM_DINS_HEX_MODE_S 24 + +/** SPI_SMEM_DIN_HEX_NUM_REG register + * MSPI 16x external RAM input timing delay number control register + */ +#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_SPI_BASE + 0x1a8) +/** SPI_SMEM_DIN08_NUM : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN08_NUM 0x00000003U +#define SPI_SMEM_DIN08_NUM_M (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S) +#define SPI_SMEM_DIN08_NUM_V 0x00000003U +#define SPI_SMEM_DIN08_NUM_S 0 +/** SPI_SMEM_DIN09_NUM : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN09_NUM 0x00000003U +#define SPI_SMEM_DIN09_NUM_M (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S) +#define SPI_SMEM_DIN09_NUM_V 0x00000003U +#define SPI_SMEM_DIN09_NUM_S 2 +/** SPI_SMEM_DIN10_NUM : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN10_NUM 0x00000003U +#define SPI_SMEM_DIN10_NUM_M (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S) +#define SPI_SMEM_DIN10_NUM_V 0x00000003U +#define SPI_SMEM_DIN10_NUM_S 4 +/** SPI_SMEM_DIN11_NUM : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN11_NUM 0x00000003U +#define SPI_SMEM_DIN11_NUM_M (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S) +#define SPI_SMEM_DIN11_NUM_V 0x00000003U +#define SPI_SMEM_DIN11_NUM_S 6 +/** SPI_SMEM_DIN12_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN12_NUM 0x00000003U +#define SPI_SMEM_DIN12_NUM_M (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S) +#define SPI_SMEM_DIN12_NUM_V 0x00000003U +#define SPI_SMEM_DIN12_NUM_S 8 +/** SPI_SMEM_DIN13_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN13_NUM 0x00000003U +#define SPI_SMEM_DIN13_NUM_M (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S) +#define SPI_SMEM_DIN13_NUM_V 0x00000003U +#define SPI_SMEM_DIN13_NUM_S 10 +/** SPI_SMEM_DIN14_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN14_NUM 0x00000003U +#define SPI_SMEM_DIN14_NUM_M (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S) +#define SPI_SMEM_DIN14_NUM_V 0x00000003U +#define SPI_SMEM_DIN14_NUM_S 12 +/** SPI_SMEM_DIN15_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN15_NUM 0x00000003U +#define SPI_SMEM_DIN15_NUM_M (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S) +#define SPI_SMEM_DIN15_NUM_V 0x00000003U +#define SPI_SMEM_DIN15_NUM_S 14 +/** SPI_SMEM_DINS_HEX_NUM : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DINS_HEX_NUM 0x00000003U +#define SPI_SMEM_DINS_HEX_NUM_M (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S) +#define SPI_SMEM_DINS_HEX_NUM_V 0x00000003U +#define SPI_SMEM_DINS_HEX_NUM_S 16 + +/** SPI_SMEM_DOUT_HEX_MODE_REG register + * MSPI 16x external RAM output timing adjustment control register + */ +#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1ac) +/** SPI_SMEM_DOUT08_MODE : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT08_MODE (BIT(0)) +#define SPI_SMEM_DOUT08_MODE_M (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S) +#define SPI_SMEM_DOUT08_MODE_V 0x00000001U +#define SPI_SMEM_DOUT08_MODE_S 0 +/** SPI_SMEM_DOUT09_MODE : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT09_MODE (BIT(1)) +#define SPI_SMEM_DOUT09_MODE_M (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S) +#define SPI_SMEM_DOUT09_MODE_V 0x00000001U +#define SPI_SMEM_DOUT09_MODE_S 1 +/** SPI_SMEM_DOUT10_MODE : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT10_MODE (BIT(2)) +#define SPI_SMEM_DOUT10_MODE_M (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S) +#define SPI_SMEM_DOUT10_MODE_V 0x00000001U +#define SPI_SMEM_DOUT10_MODE_S 2 +/** SPI_SMEM_DOUT11_MODE : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT11_MODE (BIT(3)) +#define SPI_SMEM_DOUT11_MODE_M (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S) +#define SPI_SMEM_DOUT11_MODE_V 0x00000001U +#define SPI_SMEM_DOUT11_MODE_S 3 +/** SPI_SMEM_DOUT12_MODE : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT12_MODE (BIT(4)) +#define SPI_SMEM_DOUT12_MODE_M (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S) +#define SPI_SMEM_DOUT12_MODE_V 0x00000001U +#define SPI_SMEM_DOUT12_MODE_S 4 +/** SPI_SMEM_DOUT13_MODE : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT13_MODE (BIT(5)) +#define SPI_SMEM_DOUT13_MODE_M (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S) +#define SPI_SMEM_DOUT13_MODE_V 0x00000001U +#define SPI_SMEM_DOUT13_MODE_S 5 +/** SPI_SMEM_DOUT14_MODE : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT14_MODE (BIT(6)) +#define SPI_SMEM_DOUT14_MODE_M (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S) +#define SPI_SMEM_DOUT14_MODE_V 0x00000001U +#define SPI_SMEM_DOUT14_MODE_S 6 +/** SPI_SMEM_DOUT15_MODE : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT15_MODE (BIT(7)) +#define SPI_SMEM_DOUT15_MODE_M (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S) +#define SPI_SMEM_DOUT15_MODE_V 0x00000001U +#define SPI_SMEM_DOUT15_MODE_S 7 +/** SPI_SMEM_DOUTS_HEX_MODE : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) +#define SPI_SMEM_DOUTS_HEX_MODE_M (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S) +#define SPI_SMEM_DOUTS_HEX_MODE_V 0x00000001U +#define SPI_SMEM_DOUTS_HEX_MODE_S 8 + +/** SPI_MEM_CLOCK_GATE_REG register + * SPI0 clock gate register + */ +#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 + +/** SPI_MEM_NAND_FLASH_EN_REG register + * NAND FLASH control register + */ +#define SPI_MEM_NAND_FLASH_EN_REG (DR_REG_SPI_BASE + 0x204) +/** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; + * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: + * Disable NAND FLASH, Enable NOR FLASH. + */ +#define SPI_MEM_NAND_FLASH_EN (BIT(0)) +#define SPI_MEM_NAND_FLASH_EN_M (SPI_MEM_NAND_FLASH_EN_V << SPI_MEM_NAND_FLASH_EN_S) +#define SPI_MEM_NAND_FLASH_EN_V 0x00000001U +#define SPI_MEM_NAND_FLASH_EN_S 0 +/** SPI_MEM_NAND_FLASH_SEQ_HD_INDEX : HRO; bitpos: [15:1]; default: 32767; + * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st + * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. + */ +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX 0x00007FFFU +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_M (SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V << SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S) +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V 0x00007FFFU +#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S 1 +/** SPI_MEM_NAND_FLASH_SEQ_USR_TRIG : HRO; bitpos: [16]; default: 0; + * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG + * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. + */ +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG (BIT(16)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_M (SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V << SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S) +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S 16 +/** SPI_MEM_NAND_FLASH_LUT_EN : HRO; bitpos: [17]; default: 0; + * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. + */ +#define SPI_MEM_NAND_FLASH_LUT_EN (BIT(17)) +#define SPI_MEM_NAND_FLASH_LUT_EN_M (SPI_MEM_NAND_FLASH_LUT_EN_V << SPI_MEM_NAND_FLASH_LUT_EN_S) +#define SPI_MEM_NAND_FLASH_LUT_EN_V 0x00000001U +#define SPI_MEM_NAND_FLASH_LUT_EN_S 17 +/** SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO; bitpos: [18]; default: 0; + * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and to + * excute page excute. 1: write end 0: write in a page size. + */ +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND (BIT(18)) +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M (SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V << SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S) +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S 18 + +/** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG (DR_REG_SPI_BASE + 0x208) +/** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR0 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR0_M (SPI_MEM_NAND_FLASH_SR_ADDR0_V << SPI_MEM_NAND_FLASH_SR_ADDR0_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR0_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR0_S 0 +/** SPI_MEM_NAND_FLASH_SR_ADDR1 : HRO; bitpos: [15:8]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR1 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR1_M (SPI_MEM_NAND_FLASH_SR_ADDR1_V << SPI_MEM_NAND_FLASH_SR_ADDR1_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR1_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR1_S 8 +/** SPI_MEM_NAND_FLASH_SR_ADDR2 : HRO; bitpos: [23:16]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR2 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR2_M (SPI_MEM_NAND_FLASH_SR_ADDR2_V << SPI_MEM_NAND_FLASH_SR_ADDR2_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR2_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR2_S 16 +/** SPI_MEM_NAND_FLASH_SR_ADDR3 : HRO; bitpos: [31:24]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ +#define SPI_MEM_NAND_FLASH_SR_ADDR3 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR3_M (SPI_MEM_NAND_FLASH_SR_ADDR3_V << SPI_MEM_NAND_FLASH_SR_ADDR3_S) +#define SPI_MEM_NAND_FLASH_SR_ADDR3_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_ADDR3_S 24 + +/** SPI_MEM_NAND_FLASH_SR_DIN0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_SR_DIN0_REG (DR_REG_SPI_BASE + 0x20c) +/** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN0 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN0_M (SPI_MEM_NAND_FLASH_SR_DIN0_V << SPI_MEM_NAND_FLASH_SR_DIN0_S) +#define SPI_MEM_NAND_FLASH_SR_DIN0_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN0_S 0 +/** SPI_MEM_NAND_FLASH_SR_DIN1 : RO; bitpos: [15:8]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN1 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN1_M (SPI_MEM_NAND_FLASH_SR_DIN1_V << SPI_MEM_NAND_FLASH_SR_DIN1_S) +#define SPI_MEM_NAND_FLASH_SR_DIN1_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN1_S 8 +/** SPI_MEM_NAND_FLASH_SR_DIN2 : RO; bitpos: [23:16]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN2 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN2_M (SPI_MEM_NAND_FLASH_SR_DIN2_V << SPI_MEM_NAND_FLASH_SR_DIN2_S) +#define SPI_MEM_NAND_FLASH_SR_DIN2_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN2_S 16 +/** SPI_MEM_NAND_FLASH_SR_DIN3 : RO; bitpos: [31:24]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ +#define SPI_MEM_NAND_FLASH_SR_DIN3 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN3_M (SPI_MEM_NAND_FLASH_SR_DIN3_V << SPI_MEM_NAND_FLASH_SR_DIN3_S) +#define SPI_MEM_NAND_FLASH_SR_DIN3_V 0x000000FFU +#define SPI_MEM_NAND_FLASH_SR_DIN3_S 24 + +/** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG (DR_REG_SPI_BASE + 0x210) +/** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA0 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA0_M (SPI_MEM_NAND_FLASH_CFG_DATA0_V << SPI_MEM_NAND_FLASH_CFG_DATA0_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA0_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA0_S 0 +/** SPI_MEM_NAND_FLASH_CFG_DATA1 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA1 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA1_M (SPI_MEM_NAND_FLASH_CFG_DATA1_V << SPI_MEM_NAND_FLASH_CFG_DATA1_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA1_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA1_S 16 + +/** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG (DR_REG_SPI_BASE + 0x214) +/** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA2 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA2_M (SPI_MEM_NAND_FLASH_CFG_DATA2_V << SPI_MEM_NAND_FLASH_CFG_DATA2_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA2_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA2_S 0 +/** SPI_MEM_NAND_FLASH_CFG_DATA3 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA3 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA3_M (SPI_MEM_NAND_FLASH_CFG_DATA3_V << SPI_MEM_NAND_FLASH_CFG_DATA3_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA3_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA3_S 16 + +/** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG (DR_REG_SPI_BASE + 0x218) +/** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA4 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA4_M (SPI_MEM_NAND_FLASH_CFG_DATA4_V << SPI_MEM_NAND_FLASH_CFG_DATA4_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA4_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA4_S 0 +/** SPI_MEM_NAND_FLASH_CFG_DATA5 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ +#define SPI_MEM_NAND_FLASH_CFG_DATA5 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA5_M (SPI_MEM_NAND_FLASH_CFG_DATA5_V << SPI_MEM_NAND_FLASH_CFG_DATA5_S) +#define SPI_MEM_NAND_FLASH_CFG_DATA5_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_CFG_DATA5_S 16 + +/** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register + * MSPI NAND FLASH CMD LUT control register + */ +#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG (DR_REG_SPI_BASE + 0x240) +/** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; + * MSPI NAND FLASH config cmd value at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_M (SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V << SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S) +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V 0x0000FFFFU +#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S 0 +/** SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 : HRO; bitpos: [19:16]; default: 0; + * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; + * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. + */ +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_M (SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V << SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S) +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S 16 +/** SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 : HRO; bitpos: [23:20]; default: 0; + * MSPI NAND FLASH config cmd length at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_M (SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V << SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S) +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S 20 +/** SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 : HRO; bitpos: [27:24]; default: 0; + * MSPI NAND FLASH config address length at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_M (SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V << SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S) +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S 24 +/** SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 : HRO; bitpos: [29:28]; default: 0; + * MSPI NAND FLASH config data length at cmd lut address 0. + */ +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 0x00000003U +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_M (SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V << SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S) +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V 0x00000003U +#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S 28 +/** SPI_MEM_NAND_FLASH_LUT_BUS_EN0 : HRO; bitpos: [30]; default: 0; + * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode + * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note + * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's + * field. The number of CMD LUT entries can be defined by the user, but cannot exceed + * 16 ) + */ +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0 (BIT(30)) +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_M (SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V << SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S) +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S 30 + +/** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register + * NAND FLASH SPI SEQ control register + */ +#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG (DR_REG_SPI_BASE + 0x280) +/** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; + * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for + * sequence. 0: Not the last index. + */ +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 (BIT(0)) +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_M (SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V << SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S) +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S 0 +/** SPI_MEM_NAND_FLASH_SR_CHK_EN0 : HRO; bitpos: [1]; default: 0; + * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. + */ +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0 (BIT(1)) +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_M (SPI_MEM_NAND_FLASH_SR_CHK_EN0_V << SPI_MEM_NAND_FLASH_SR_CHK_EN0_S) +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_S 1 +/** SPI_MEM_NAND_FLASH_DIN_INDEX0 : HRO; bitpos: [5:2]; default: 0; + * MSPI NAND FLASH config din_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_CFG_DATA + */ +#define SPI_MEM_NAND_FLASH_DIN_INDEX0 0x0000000FU +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_M (SPI_MEM_NAND_FLASH_DIN_INDEX0_V << SPI_MEM_NAND_FLASH_DIN_INDEX0_S) +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_DIN_INDEX0_S 2 +/** SPI_MEM_NAND_FLASH_ADDR_INDEX0 : HRO; bitpos: [9:6]; default: 0; + * MSPI NAND FLASH config addr_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_SR_ADDR + */ +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0 0x0000000FU +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_M (SPI_MEM_NAND_FLASH_ADDR_INDEX0_V << SPI_MEM_NAND_FLASH_ADDR_INDEX0_S) +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_S 6 +/** SPI_MEM_NAND_FLASH_REQ_OR_CFG0 : HRO; bitpos: [10]; default: 0; + * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI + * SEQ configuration. + */ +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0 (BIT(10)) +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_M (SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V << SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S) +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V 0x00000001U +#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S 10 +/** SPI_MEM_NAND_FLASH_CMD_INDEX0 : HRO; bitpos: [14:11]; default: 0; + * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in + * CMD LUT.(Note these registers are described to indicate the + * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined + * by the user, but cannot exceed 16 ) + */ +#define SPI_MEM_NAND_FLASH_CMD_INDEX0 0x0000000FU +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_M (SPI_MEM_NAND_FLASH_CMD_INDEX0_V << SPI_MEM_NAND_FLASH_CMD_INDEX0_S) +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_V 0x0000000FU +#define SPI_MEM_NAND_FLASH_CMD_INDEX0_S 11 + +/** SPI_MEM_XTS_PLAIN_BASE_REG register + * The base address of the memory that stores plaintext in Manual Encryption + */ +#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300) +/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ +#define SPI_XTS_PLAIN 0xFFFFFFFFU +#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_XTS_PLAIN_S 0 + +/** SPI_MEM_XTS_LINESIZE_REG register + * Manual Encryption Line-Size register + */ +#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340) +/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ +#define SPI_XTS_LINESIZE 0x00000003U +#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_XTS_LINESIZE_V 0x00000003U +#define SPI_XTS_LINESIZE_S 0 + +/** SPI_MEM_XTS_DESTINATION_REG register + * Manual Encryption destination register + */ +#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344) +/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ +#define SPI_XTS_DESTINATION (BIT(0)) +#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_XTS_DESTINATION_V 0x00000001U +#define SPI_XTS_DESTINATION_S 0 + +/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348) +/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ +#define SPI_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) +#define SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_S 0 + +/** SPI_MEM_XTS_TRIGGER_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c) +/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ +#define SPI_XTS_TRIGGER (BIT(0)) +#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) +#define SPI_XTS_TRIGGER_V 0x00000001U +#define SPI_XTS_TRIGGER_S 0 + +/** SPI_MEM_XTS_RELEASE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350) +/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ +#define SPI_XTS_RELEASE (BIT(0)) +#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_XTS_RELEASE_V 0x00000001U +#define SPI_XTS_RELEASE_S 0 + +/** SPI_MEM_XTS_DESTROY_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354) +/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ +#define SPI_XTS_DESTROY (BIT(0)) +#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_XTS_DESTROY_V 0x00000001U +#define SPI_XTS_DESTROY_S 0 + +/** SPI_MEM_XTS_STATE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358) +/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ +#define SPI_XTS_STATE 0x00000003U +#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_XTS_STATE_V 0x00000003U +#define SPI_XTS_STATE_S 0 + +/** SPI_MEM_XTS_DATE_REG register + * Manual Encryption version register + */ +#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c) +/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; + * This bits stores the last modified-time of manual encryption feature. + */ +#define SPI_XTS_DATE 0x3FFFFFFFU +#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_XTS_DATE_V 0x3FFFFFFFU +#define SPI_XTS_DATE_S 0 + +/** SPI_MEM_MMU_ITEM_CONTENT_REG register + * MSPI-MMU item content register + */ +#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c) +/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ +#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_S 0 + +/** SPI_MEM_MMU_ITEM_INDEX_REG register + * MSPI-MMU item index register + */ +#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380) +/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ +#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_S 0 + +/** SPI_MEM_MMU_POWER_CTRL_REG register + * MSPI MMU power control register + */ +#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384) +/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ +#define SPI_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MMU_MEM_FORCE_ON_S 0 +/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 1; + * Set this bit to force mmu-memory powerdown + */ +#define SPI_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PD_S 1 +/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ +#define SPI_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PU_S 2 +/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MMU_PAGE_SIZE 0x00000003U +#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MMU_PAGE_SIZE_S 3 +/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ +#define SPI_MEM_AUX_CTRL 0x00003FFFU +#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) +#define SPI_MEM_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_AUX_CTRL_S 16 +/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; + * ECO register enable bit + */ +#define SPI_MEM_RDN_ENA (BIT(30)) +#define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) +#define SPI_MEM_RDN_ENA_V 0x00000001U +#define SPI_MEM_RDN_ENA_S 30 +/** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + */ +#define SPI_MEM_RDN_RESULT (BIT(31)) +#define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) +#define SPI_MEM_RDN_RESULT_V 0x00000001U +#define SPI_MEM_RDN_RESULT_S 31 + +/** SPI_MEM_DPA_CTRL_REG register + * SPI memory cryption DPA register + */ +#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388) +/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ +#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ +#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ +#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 + +/** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register + * SPI memory cryption PSEUDO register + */ +#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_SPI_BASE + 0x38c) +/** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define SPI_MEM_MODE_PSEUDO 0x00000003U +#define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) +#define SPI_MEM_MODE_PSEUDO_V 0x00000003U +#define SPI_MEM_MODE_PSEUDO_S 0 +/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be peformed. + */ +#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) +#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be peformed. + */ +#define SPI_MEM_PSEUDO_BASE 0x0000000FU +#define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) +#define SPI_MEM_PSEUDO_BASE_V 0x0000000FU +#define SPI_MEM_PSEUDO_BASE_S 5 +/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be peformed randomly between 0 & + * 2**(inc+1). + */ +#define SPI_MEM_PSEUDO_INC 0x00000003U +#define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) +#define SPI_MEM_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_PSEUDO_INC_S 9 + +/** SPI_MEM_REGISTERRND_ECO_HIGH_REG register + * MSPI ECO high register + */ +#define SPI_MEM_REGISTERRND_ECO_HIGH_REG (DR_REG_SPI_BASE + 0x3f0) +/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; + * ECO high register + */ +#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_HIGH_M (SPI_MEM_REGISTERRND_ECO_HIGH_V << SPI_MEM_REGISTERRND_ECO_HIGH_S) +#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 + +/** SPI_MEM_REGISTERRND_ECO_LOW_REG register + * MSPI ECO low register + */ +#define SPI_MEM_REGISTERRND_ECO_LOW_REG (DR_REG_SPI_BASE + 0x3f4) +/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; + * ECO low register + */ +#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_LOW_M (SPI_MEM_REGISTERRND_ECO_LOW_V << SPI_MEM_REGISTERRND_ECO_LOW_S) +#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU +#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 + +/** SPI_MEM_DATE_REG register + * SPI0 version control register + */ +#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc) +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37753200; + * SPI0 register version. + */ +#define SPI_MEM_DATE 0x0FFFFFFFU +#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) +#define SPI_MEM_DATE_V 0x0FFFFFFFU +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/spi_mem_struct.h b/components/soc/esp32c61/include/soc/spi_mem_struct.h new file mode 100644 index 0000000000..43766b272a --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi_mem_struct.h @@ -0,0 +1,2922 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status and state control register */ +/** Type of mem_cmd register + * SPI0 FSM status register + */ +typedef union { + struct { + /** mem_mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ + uint32_t mem_mst_st:4; + /** mem_slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t mem_slv_st:4; + uint32_t reserved_8:10; + /** mem_usr : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t mem_usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_cmd_reg_t; + +/** Type of mem_axi_err_addr register + * SPI0 AXI request error address. + */ +typedef union { + struct { + /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ + uint32_t mem_axi_err_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_axi_err_addr_reg_t; + + +/** Group: Flash Control and configuration registers */ +/** Type of mem_ctrl register + * SPI0 control register. + */ +typedef union { + struct { + /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ + uint32_t mem_wdummy_dqs_always_out:1; + /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t mem_wdummy_always_out:1; + /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ + uint32_t mem_fdummy_rin:1; + /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ + uint32_t mem_fdummy_wout:1; + /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t mem_fdout_oct:1; + /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t mem_fdin_oct:1; + /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t mem_faddr_oct:1; + uint32_t reserved_7:1; + /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_quad:1; + /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_oct:1; + uint32_t reserved_10:3; + /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ + uint32_t mem_fastrd_mode:1; + /** mem_fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_dual:1; + uint32_t reserved_15:3; + /** mem_q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t mem_q_pol:1; + /** mem_d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t mem_d_pol:1; + /** mem_fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_quad:1; + /** mem_wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t mem_wp_reg:1; + uint32_t reserved_22:1; + /** mem_fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_dio:1; + /** mem_fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_qio:1; + uint32_t reserved_25:5; + /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ + uint32_t mem_dqs_ie_always_on:1; + /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ + uint32_t mem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_ctrl_reg_t; + +/** Type of mem_ctrl1 register + * SPI0 control1 register. + */ +typedef union { + struct { + /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ + uint32_t mem_clk_mode:2; + uint32_t reserved_2:19; + /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t ar_size0_1_support_en:1; + /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t aw_size0_1_support_en:1; + /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ + uint32_t axi_rdata_back_fast:1; + /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ + uint32_t mem_rresp_ecc_err_en:1; + /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ + uint32_t mem_ar_splice_en:1; + /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ + uint32_t mem_aw_splice_en:1; + /** mem_ram0_en : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ + uint32_t mem_ram0_en:1; + /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ + uint32_t mem_dual_ram_en:1; + /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ + uint32_t mem_fast_write_en:1; + /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_rxfifo_rst:1; + /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_txfifo_rst:1; + }; + uint32_t val; +} spi_mem_ctrl1_reg_t; + +/** Type of mem_ctrl2 register + * SPI0 control2 register. + */ +typedef union { + struct { + /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ + uint32_t mem_cs_setup_time:5; + /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ + uint32_t mem_cs_hold_time:5; + /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ + uint32_t mem_ecc_cs_hold_time:3; + /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ + uint32_t mem_ecc_skip_page_corner:1; + /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ + uint32_t mem_ecc_16to18_byte_en:1; + uint32_t reserved_15:9; + /** mem_split_trans_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ + uint32_t mem_split_trans_en:1; + /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ + uint32_t mem_cs_hold_delay:6; + /** mem_sync_reset : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ + uint32_t mem_sync_reset:1; + }; + uint32_t val; +} spi_mem_ctrl2_reg_t; + +/** Type of mem_misc register + * SPI0 misc register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ + uint32_t mem_fsub_pin:1; + /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ + uint32_t mem_ssub_pin:1; + /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ + uint32_t mem_ck_idle_edge:1; + /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ + uint32_t mem_cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_misc_reg_t; + +/** Type of mem_cache_fctrl register + * SPI0 bit mode control register. + */ +typedef union { + struct { + /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + */ + uint32_t mem_axi_req_en:1; + /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ + uint32_t mem_cache_usr_addr_4byte:1; + /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + */ + uint32_t mem_cache_flash_usr_cmd:1; + /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + */ + uint32_t mem_fdin_dual:1; + /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + */ + uint32_t mem_fdout_dual:1; + /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + */ + uint32_t mem_faddr_dual:1; + /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + */ + uint32_t mem_fdin_quad:1; + /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + */ + uint32_t mem_fdout_quad:1; + /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + */ + uint32_t mem_faddr_quad:1; + uint32_t reserved_9:21; + /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ + uint32_t same_aw_ar_addr_chk_en:1; + /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ + uint32_t close_axi_inf_en:1; + }; + uint32_t val; +} spi_mem_cache_fctrl_reg_t; + +/** Type of mem_ddr register + * SPI0 flash DDR mode control register + */ +typedef union { + struct { + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ + uint32_t fmem_tx_ddr_msk_en:1; + /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ + uint32_t fmem_rx_ddr_msk_en:1; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_ddr_reg_t; + + +/** Group: Clock control and configuration registers */ +/** Type of mem_clock register + * SPI clock division control register. + */ +typedef union { + struct { + /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ + uint32_t mem_clkcnt_l:8; + /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t mem_clkcnt_h:8; + /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ + uint32_t mem_clkcnt_n:8; + uint32_t reserved_24:7; + /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ + uint32_t mem_clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_clock_reg_t; + +/** Type of mem_sram_clk register + * SPI0 external RAM clock control register + */ +typedef union { + struct { + /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + */ + uint32_t mem_sclkcnt_l:8; + /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t mem_sclkcnt_h:8; + /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(spi_mem_clkcnt_N+1) + */ + uint32_t mem_sclkcnt_n:8; + uint32_t reserved_24:7; + /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk + * is divided from system clock. + */ + uint32_t mem_sclk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_sram_clk_reg_t; + +/** Type of mem_clock_gate register + * SPI0 clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_clock_gate_reg_t; + + +/** Group: Flash User-defined control registers */ +/** Type of mem_user register + * SPI0 user register. + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** mem_cs_hold : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t mem_cs_hold:1; + /** mem_cs_setup : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + uint32_t mem_cs_setup:1; + uint32_t reserved_8:1; + /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ + uint32_t mem_ck_out_edge:1; + uint32_t reserved_10:16; + /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + uint32_t mem_usr_dummy_idle:1; + uint32_t reserved_27:2; + /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t mem_usr_dummy:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_user_reg_t; + +/** Type of mem_user1 register + * SPI0 user1 register. + */ +typedef union { + struct { + /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t mem_usr_dummy_cyclelen:6; + /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ + uint32_t mem_usr_dbytelen:6; + uint32_t reserved_12:14; + /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t mem_usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_user1_reg_t; + +/** Type of mem_user2 register + * SPI0 user2 register. + */ +typedef union { + struct { + /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t mem_usr_command_value:16; + uint32_t reserved_16:12; + /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t mem_usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_user2_reg_t; + +/** Type of mem_rd_status register + * SPI0 read control register. + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + */ + uint32_t mem_wb_mode:8; + /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + */ + uint32_t mem_wb_mode_bitlen:3; + /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + */ + uint32_t mem_wb_mode_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_rd_status_reg_t; + + +/** Group: External RAM Control and configuration registers */ +/** Type of mem_cache_sctrl register + * SPI0 external RAM control register + */ +typedef union { + struct { + /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + */ + uint32_t mem_cache_usr_saddr_4byte:1; + /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + */ + uint32_t mem_usr_sram_dio:1; + /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + */ + uint32_t mem_usr_sram_qio:1; + /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + */ + uint32_t mem_usr_wr_sram_dummy:1; + /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + */ + uint32_t mem_usr_rd_sram_dummy:1; + /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + */ + uint32_t mem_cache_sram_usr_rcmd:1; + /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + */ + uint32_t mem_sram_rdummy_cyclelen:6; + uint32_t reserved_12:2; + /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + */ + uint32_t mem_sram_addr_bitlen:6; + /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + */ + uint32_t mem_cache_sram_usr_wcmd:1; + /** mem_sram_oct : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t mem_sram_oct:1; + /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + */ + uint32_t mem_sram_wdummy_cyclelen:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_cache_sctrl_reg_t; + +/** Type of mem_sram_cmd register + * SPI0 external RAM mode control register + */ +typedef union { + struct { + /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t mem_sclk_mode:2; + /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + */ + uint32_t mem_swb_mode:8; + /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + */ + uint32_t mem_sdin_dual:1; + /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + */ + uint32_t mem_sdout_dual:1; + /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + */ + uint32_t mem_saddr_dual:1; + uint32_t reserved_13:1; + /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + */ + uint32_t mem_sdin_quad:1; + /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + */ + uint32_t mem_sdout_quad:1; + /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + */ + uint32_t mem_saddr_quad:1; + /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + */ + uint32_t mem_scmd_quad:1; + /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + */ + uint32_t mem_sdin_oct:1; + /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + */ + uint32_t mem_sdout_oct:1; + /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_saddr_oct:1; + /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + */ + uint32_t mem_scmd_oct:1; + /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ + uint32_t mem_sdummy_rin:1; + /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ + uint32_t mem_sdummy_wout:1; + /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ + uint32_t smem_wdummy_dqs_always_out:1; + /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t smem_wdummy_always_out:1; + /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + */ + uint32_t mem_sdin_hex:1; + /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + */ + uint32_t mem_sdout_hex:1; + uint32_t reserved_28:2; + /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ + uint32_t smem_dqs_ie_always_on:1; + /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ + uint32_t smem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_sram_cmd_reg_t; + +/** Type of mem_sram_drd_cmd register + * SPI0 external RAM DDR read command control register + */ +typedef union { + struct { + /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + */ + uint32_t mem_cache_sram_usr_rd_cmd_value:16; + uint32_t reserved_16:12; + /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + */ + uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_sram_drd_cmd_reg_t; + +/** Type of mem_sram_dwr_cmd register + * SPI0 external RAM DDR write command control register + */ +typedef union { + struct { + /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + */ + uint32_t mem_cache_sram_usr_wr_cmd_value:16; + uint32_t reserved_16:12; + /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + */ + uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_sram_dwr_cmd_reg_t; + +/** Type of smem_ddr register + * SPI0 external RAM DDR mode control register + */ +typedef union { + struct { + /** smem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t smem_ddr_en:1; + /** smem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t smem_var_dummy:1; + /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_rdat_swp:1; + /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_wdat_swp:1; + /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t smem_ddr_cmd_dis:1; + /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ + uint32_t smem_outminbytelen:7; + /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ + uint32_t smem_tx_ddr_msk_en:1; + /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ + uint32_t smem_rx_ddr_msk_en:1; + /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t smem_usr_ddr_dqs_thd:7; + /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t smem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t smem_clk_diff_en:1; + uint32_t reserved_25:1; + /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t smem_dqs_ca_in:1; + /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t smem_hyperbus_dummy_2x:1; + /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ + uint32_t smem_clk_diff_inv:1; + /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ + uint32_t smem_octa_ram_addr:1; + /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t smem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_smem_ddr_reg_t; + +/** Type of smem_ac register + * MSPI external RAM ECC and SPI CS timing control register + */ +typedef union { + struct { + /** smem_cs_setup : R/W; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ + uint32_t smem_cs_setup:1; + /** smem_cs_hold : R/W; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t smem_cs_hold:1; + /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ + uint32_t smem_cs_setup_time:5; + /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ + uint32_t smem_cs_hold_time:5; + /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ + uint32_t smem_ecc_cs_hold_time:3; + /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ + uint32_t smem_ecc_skip_page_corner:1; + /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ + uint32_t smem_ecc_16to18_byte_en:1; + uint32_t reserved_17:8; + /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ + uint32_t smem_cs_hold_delay:6; + /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ + uint32_t smem_split_trans_en:1; + }; + uint32_t val; +} spi_smem_ac_reg_t; + + +/** Group: State control register */ +/** Type of mem_fsm register + * SPI0 FSM status register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ + uint32_t mem_lock_delay_time:5; + /** mem_flash_lock_en : R/W; bitpos: [12]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_flash_lock_en:1; + /** mem_sram_lock_en : R/W; bitpos: [13]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_sram_lock_en:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} spi_mem_fsm_reg_t; + + +/** Group: Interrupt registers */ +/** Type of mem_int_ena register + * SPI0 interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_ena:1; + /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_ena:1; + /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_ena:1; + /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_ena:1; + /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_ena:1; + /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_ena:1; + /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int__ena:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_ena:1; + /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_ena:1; + /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_ena:1; + /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_ena:1; + }; + uint32_t val; +} spi_mem_int_ena_reg_t; + +/** Type of mem_int_clr register + * SPI0 interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_clr:1; + /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_clr:1; + /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_clr:1; + /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_clr:1; + /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_clr:1; + /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_clr:1; + /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_clr:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_clr:1; + /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_clr:1; + /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_clr:1; + /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_clr:1; + }; + uint32_t val; +} spi_mem_int_clr_reg_t; + +/** Type of mem_int_raw register + * SPI0 interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t mem_slv_st_end_int_raw:1; + /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mem_mst_st_end_int_raw:1; + /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ + uint32_t mem_ecc_err_int_raw:1; + /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ + uint32_t mem_pms_reject_int_raw:1; + /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_raddr_err_int_raw:1; + /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ + uint32_t mem_axi_wr_flash_err_int_raw:1; + /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_waddr_err_int_raw:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ + uint32_t mem_dqs0_afifo_ovf_int_raw:1; + /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ + uint32_t mem_dqs1_afifo_ovf_int_raw:1; + /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo1_udf_int_raw:1; + /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo0_udf_int_raw:1; + }; + uint32_t val; +} spi_mem_int_raw_reg_t; + +/** Type of mem_int_st register + * SPI0 interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_st:1; + /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_st:1; + /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_st:1; + /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_st:1; + /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_st:1; + /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_st:1; + /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_st:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_st:1; + /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_st:1; + /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_st:1; + /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_st:1; + }; + uint32_t val; +} spi_mem_int_st_reg_t; + + +/** Group: PMS control and configuration registers */ +/** Type of fmem_pmsn_attr register + * MSPI flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_fmem_pmsn_attr_reg_t; + +/** Type of fmem_pmsn_addr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; + * SPI1 flash PMS section n start address value + */ + uint32_t fmem_pmsn_addr_s:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_fmem_pmsn_addr_reg_t; + +/** Type of fmem_pmsn_size register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; + * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, + * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) + */ + uint32_t fmem_pmsn_size:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_fmem_pmsn_size_reg_t; + +/** Type of smem_pmsn_attr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_rd_attr:1; + /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_wr_attr:1; + /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_smem_pmsn_attr_reg_t; + +/** Type of smem_pmsn_addr register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; + * SPI1 external RAM PMS section n start address value + */ + uint32_t smem_pmsn_addr_s:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_smem_pmsn_addr_reg_t; + +/** Type of smem_pmsn_size register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) + */ + uint32_t smem_pmsn_size:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_smem_pmsn_size_reg_t; + +/** Type of mem_pms_reject register + * SPI1 access reject register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** mem_pm_en : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ + uint32_t mem_pm_en:1; + /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ld:1; + /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_st:1; + /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_multi_hit:1; + /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ivd:1; + }; + uint32_t val; +} spi_mem_pms_reject_reg_t; + +/** Type of mem_pms_reject_addr register + * SPI1 access reject addr register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_pms_reject_addr_reg_t; + + +/** Group: MSPI ECC registers */ +/** Type of mem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_cnt:6; + /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t fmem_ecc_err_int_num:6; + /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ + uint32_t fmem_ecc_err_int_en:1; + /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + uint32_t fmem_page_size:2; + uint32_t reserved_20:1; + /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ + uint32_t fmem_ecc_addr_en:1; + /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ + uint32_t mem_usr_ecc_addr_en:1; + uint32_t reserved_23:1; + /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ + uint32_t mem_ecc_continue_record_err_en:1; + /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ + uint32_t mem_ecc_err_bits:7; + }; + uint32_t val; +} spi_mem_ecc_ctrl_reg_t; + +/** Type of mem_ecc_err_addr register + * MSPI ECC error address register + */ +typedef union { + struct { + /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_ecc_err_addr_reg_t; + +/** Type of smem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ + uint32_t smem_ecc_err_int_en:1; + /** smem_page_size : R/W; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ + uint32_t smem_page_size:2; + /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ + uint32_t smem_ecc_addr_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_smem_ecc_ctrl_reg_t; + + +/** Group: Status and state control registers */ +/** Type of smem_axi_addr_ctrl register + * SPI0 AXI address control register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ + uint32_t mem_all_fifo_empty:1; + /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t rdata_afifo_rempty:1; + /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t raddr_afifo_rempty:1; + /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wdata_afifo_rempty:1; + /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wblen_afifo_rempty:1; + /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ + uint32_t all_axi_trans_afifo_empty:1; + }; + uint32_t val; +} spi_smem_axi_addr_ctrl_reg_t; + +/** Type of mem_axi_err_resp_en register + * SPI0 AXI error response enable register + */ +typedef union { + struct { + /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_vld:1; + /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_gid:1; + /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_size:1; + /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_flash:1; + /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_ecc:1; + /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_sens:1; + /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_wstrb:1; + /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_vld:1; + /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_gid:1; + /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_ecc:1; + /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ + uint32_t mem_ar_resp_en_mmu_sens:1; + /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ + uint32_t mem_ar_resp_en_axi_size:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_axi_err_resp_en_reg_t; + + +/** Group: Flash timing registers */ +/** Type of mem_timing_cali register + * SPI0 flash timing calibration register + */ +typedef union { + struct { + /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t mem_timing_clk_ena:1; + /** mem_timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t mem_timing_cali:1; + /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t mem_extra_dummy_cyclelen:3; + /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ + uint32_t mem_dll_timing_cali:1; + /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ + uint32_t mem_timing_cali_update:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} spi_mem_timing_cali_reg_t; + +/** Type of mem_din_mode register + * MSPI flash input timing delay mode control register + */ +typedef union { + struct { + /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din0_mode:3; + /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din1_mode:3; + /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din2_mode:3; + /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din3_mode:3; + /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din4_mode:3; + /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din5_mode:3; + /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din6_mode:3; + /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din7_mode:3; + /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_din_mode_reg_t; + +/** Type of mem_din_num register + * MSPI flash input timing delay number control register + */ +typedef union { + struct { + /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din0_num:2; + /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din1_num:2; + /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din2_num:2; + /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din3_num:2; + /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din4_num:2; + /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din5_num:2; + /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din6_num:2; + /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din7_num:2; + /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_din_num_reg_t; + +/** Type of mem_dout_mode register + * MSPI flash output timing adjustment control register + */ +typedef union { + struct { + /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout0_mode:1; + /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout1_mode:1; + /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout2_mode:1; + /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout3_mode:1; + /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout4_mode:1; + /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout5_mode:1; + /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout6_mode:1; + /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout7_mode:1; + /** mem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_dout_mode_reg_t; + + +/** Group: External RAM timing registers */ +/** Type of smem_timing_cali register + * MSPI external RAM timing calibration register + */ +typedef union { + struct { + /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t smem_timing_clk_ena:1; + /** smem_timing_cali : R/W; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ + uint32_t smem_timing_cali:1; + /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t smem_extra_dummy_cyclelen:3; + /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ + uint32_t smem_dll_timing_cali:1; + uint32_t reserved_6:1; + /** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_270_sel:2; + /** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_90_sel:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_smem_timing_cali_reg_t; + +/** Type of smem_din_mode register + * MSPI external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din0_mode:3; + /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din1_mode:3; + /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din2_mode:3; + /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din3_mode:3; + /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din4_mode:3; + /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din5_mode:3; + /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din6_mode:3; + /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din7_mode:3; + /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_din_mode_reg_t; + +/** Type of smem_din_num register + * MSPI external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din0_num:2; + /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din1_num:2; + /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din2_num:2; + /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din3_num:2; + /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din4_num:2; + /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din5_num:2; + /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din6_num:2; + /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din7_num:2; + /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_smem_din_num_reg_t; + +/** Type of smem_dout_mode register + * MSPI external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout0_mode:1; + /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout1_mode:1; + /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout2_mode:1; + /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout3_mode:1; + /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout4_mode:1; + /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout5_mode:1; + /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout6_mode:1; + /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout7_mode:1; + /** smem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_smem_dout_mode_reg_t; + +/** Type of smem_din_hex_mode register + * MSPI 16x external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din08_mode : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din08_mode:3; + /** smem_din09_mode : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din09_mode:3; + /** smem_din10_mode : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din10_mode:3; + /** smem_din11_mode : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din11_mode:3; + /** smem_din12_mode : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din12_mode:3; + /** smem_din13_mode : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din13_mode:3; + /** smem_din14_mode : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din14_mode:3; + /** smem_din15_mode : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din15_mode:3; + /** smem_dins_hex_mode : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_hex_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_din_hex_mode_reg_t; + +/** Type of smem_din_hex_num register + * MSPI 16x external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din08_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din08_num:2; + /** smem_din09_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din09_num:2; + /** smem_din10_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din10_num:2; + /** smem_din11_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din11_num:2; + /** smem_din12_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din12_num:2; + /** smem_din13_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din13_num:2; + /** smem_din14_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din14_num:2; + /** smem_din15_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din15_num:2; + /** smem_dins_hex_num : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_hex_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_smem_din_hex_num_reg_t; + +/** Type of smem_dout_hex_mode register + * MSPI 16x external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout08_mode : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout08_mode:1; + /** smem_dout09_mode : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout09_mode:1; + /** smem_dout10_mode : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout10_mode:1; + /** smem_dout11_mode : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout11_mode:1; + /** smem_dout12_mode : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout12_mode:1; + /** smem_dout13_mode : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout13_mode:1; + /** smem_dout14_mode : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout14_mode:1; + /** smem_dout15_mode : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout15_mode:1; + /** smem_douts_hex_mode : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_hex_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_smem_dout_hex_mode_reg_t; + + +/** Group: NAND FLASH control and status registers */ +/** Type of mem_nand_flash_en register + * NAND FLASH control register + */ +typedef union { + struct { + /** mem_nand_flash_en : HRO; bitpos: [0]; default: 0; + * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: + * Disable NAND FLASH, Enable NOR FLASH. + */ + uint32_t mem_nand_flash_en:1; + /** mem_nand_flash_seq_hd_index : HRO; bitpos: [15:1]; default: 32767; + * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st + * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. + */ + uint32_t mem_nand_flash_seq_hd_index:15; + /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; + * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG + * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. + */ + uint32_t mem_nand_flash_seq_usr_trig:1; + /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; + * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. + */ + uint32_t mem_nand_flash_lut_en:1; + /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; + * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and to + * excute page excute. 1: write end 0: write in a page size. + */ + uint32_t mem_nand_flash_seq_usr_wend:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_nand_flash_en_reg_t; + +/** Type of mem_nand_flash_sr_addr0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_sr_addr0 : HRO; bitpos: [7:0]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr0:8; + /** mem_nand_flash_sr_addr1 : HRO; bitpos: [15:8]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr1:8; + /** mem_nand_flash_sr_addr2 : HRO; bitpos: [23:16]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr2:8; + /** mem_nand_flash_sr_addr3 : HRO; bitpos: [31:24]; default: 0; + * configure state register address for SPI SEQ need. If OIP is in address C0H , user + * could configure C0H into this register + */ + uint32_t mem_nand_flash_sr_addr3:8; + }; + uint32_t val; +} spi_mem_nand_flash_sr_addr0_reg_t; + +/** Type of mem_nand_flash_sr_din0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din0:8; + /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din1:8; + /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din2:8; + /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; + * spi read state register data to this register for SPI SEQ need. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. + */ + uint32_t mem_nand_flash_sr_din3:8; + }; + uint32_t val; +} spi_mem_nand_flash_sr_din0_reg_t; + +/** Type of mem_nand_flash_cfg_data0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_cfg_data0 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data0:16; + /** mem_nand_flash_cfg_data1 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data1:16; + }; + uint32_t val; +} spi_mem_nand_flash_cfg_data0_reg_t; + +/** Type of mem_nand_flash_cfg_data1 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_cfg_data2 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data2:16; + /** mem_nand_flash_cfg_data3 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data3:16; + }; + uint32_t val; +} spi_mem_nand_flash_cfg_data1_reg_t; + +/** Type of mem_nand_flash_cfg_data2 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_cfg_data4 : HRO; bitpos: [15:0]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data4:16; + /** mem_nand_flash_cfg_data5 : HRO; bitpos: [31:16]; default: 0; + * configure data for SPI SEQ din/dout need. The data could be use to configure NAND + * FLASH or compare read data + */ + uint32_t mem_nand_flash_cfg_data5:16; + }; + uint32_t val; +} spi_mem_nand_flash_cfg_data2_reg_t; + +/** Type of mem_nand_flash_cmd_lut0 register + * MSPI NAND FLASH CMD LUT control register + */ +typedef union { + struct { + /** mem_nand_flash_lut_cmd_value0 : HRO; bitpos: [15:0]; default: 0; + * MSPI NAND FLASH config cmd value at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_cmd_value0:16; + /** mem_nand_flash_lut_sfsm_st_en0 : HRO; bitpos: [19:16]; default: 0; + * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; + * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. + */ + uint32_t mem_nand_flash_lut_sfsm_st_en0:4; + /** mem_nand_flash_lut_cmd_len0 : HRO; bitpos: [23:20]; default: 0; + * MSPI NAND FLASH config cmd length at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_cmd_len0:4; + /** mem_nand_flash_lut_addr_len0 : HRO; bitpos: [27:24]; default: 0; + * MSPI NAND FLASH config address length at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_addr_len0:4; + /** mem_nand_flash_lut_data_len0 : HRO; bitpos: [29:28]; default: 0; + * MSPI NAND FLASH config data length at cmd lut address 0. + */ + uint32_t mem_nand_flash_lut_data_len0:2; + /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; + * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode + * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note + * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's + * field. The number of CMD LUT entries can be defined by the user, but cannot exceed + * 16 ) + */ + uint32_t mem_nand_flash_lut_bus_en0:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_nand_flash_cmd_lut0_reg_t; + +/** Type of mem_nand_flash_spi_seq0 register + * NAND FLASH SPI SEQ control register + */ +typedef union { + struct { + /** mem_nand_flash_seq_tail_flg0 : HRO; bitpos: [0]; default: 0; + * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for + * sequence. 0: Not the last index. + */ + uint32_t mem_nand_flash_seq_tail_flg0:1; + /** mem_nand_flash_sr_chk_en0 : HRO; bitpos: [1]; default: 0; + * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. + */ + uint32_t mem_nand_flash_sr_chk_en0:1; + /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; + * MSPI NAND FLASH config din_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_CFG_DATA + */ + uint32_t mem_nand_flash_din_index0:4; + /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; + * MSPI NAND FLASH config addr_index at spi seq index 0. Use with + * SPI_MEM_NAND_FLASH_SR_ADDR + */ + uint32_t mem_nand_flash_addr_index0:4; + /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; + * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI + * SEQ configuration. + */ + uint32_t mem_nand_flash_req_or_cfg0:1; + /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; + * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in + * CMD LUT.(Note these registers are described to indicate the + * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined + * by the user, but cannot exceed 16 ) + */ + uint32_t mem_nand_flash_cmd_index0:4; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_mem_nand_flash_spi_seq0_reg_t; + + +/** Group: Manual Encryption plaintext Memory */ +/** Type of mem_xts_plain_base register + * The base address of the memory that stores plaintext in Manual Encryption + */ +typedef union { + struct { + /** xts_plain : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ + uint32_t xts_plain:32; + }; + uint32_t val; +} spi_mem_xts_plain_base_reg_t; + + +/** Group: Manual Encryption configuration registers */ +/** Type of mem_xts_linesize register + * Manual Encryption Line-Size register + */ +typedef union { + struct { + /** xts_linesize : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ + uint32_t xts_linesize:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_linesize_reg_t; + +/** Type of mem_xts_destination register + * Manual Encryption destination register + */ +typedef union { + struct { + /** xts_destination : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ + uint32_t xts_destination:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destination_reg_t; + +/** Type of mem_xts_physical_address register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ + uint32_t xts_physical_address:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_xts_physical_address_reg_t; + + +/** Group: Manual Encryption control and status registers */ +/** Type of mem_xts_trigger register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_trigger : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ + uint32_t xts_trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_trigger_reg_t; + +/** Type of mem_xts_release register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_release : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ + uint32_t xts_release:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_release_reg_t; + +/** Type of mem_xts_destroy register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_destroy : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ + uint32_t xts_destroy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destroy_reg_t; + +/** Type of mem_xts_state register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_state : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ + uint32_t xts_state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_state_reg_t; + + +/** Group: Manual Encryption version control register */ +/** Type of mem_xts_date register + * Manual Encryption version register + */ +typedef union { + struct { + /** xts_date : R/W; bitpos: [29:0]; default: 539035911; + * This bits stores the last modified-time of manual encryption feature. + */ + uint32_t xts_date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_xts_date_reg_t; + + +/** Group: MMU access registers */ +/** Type of mem_mmu_item_content register + * MSPI-MMU item content register + */ +typedef union { + struct { + /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ + uint32_t mmu_item_content:32; + }; + uint32_t val; +} spi_mem_mmu_item_content_reg_t; + +/** Type of mem_mmu_item_index register + * MSPI-MMU item index register + */ +typedef union { + struct { + /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ + uint32_t mmu_item_index:32; + }; + uint32_t val; +} spi_mem_mmu_item_index_reg_t; + + +/** Group: MMU power control and configuration registers */ +/** Type of mem_mmu_power_ctrl register + * MSPI MMU power control register + */ +typedef union { + struct { + /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ + uint32_t mmu_mem_force_on:1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 1; + * Set this bit to force mmu-memory powerdown + */ + uint32_t mmu_mem_force_pd:1; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ + uint32_t mmu_mem_force_pu:1; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; + /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ + uint32_t mem_aux_ctrl:14; + /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; + * ECO register enable bit + */ + uint32_t mem_rdn_ena:1; + /** mem_rdn_result : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + */ + uint32_t mem_rdn_result:1; + }; + uint32_t val; +} spi_mem_mmu_power_ctrl_reg_t; + + +/** Group: External mem cryption DPA registers */ +/** Type of mem_dpa_ctrl register + * SPI memory cryption DPA register + */ +typedef union { + struct { + /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ + uint32_t crypt_security_level:3; + /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ + uint32_t crypt_calc_d_dpa_en:1; + /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ + uint32_t crypt_dpa_select_register:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_dpa_ctrl_reg_t; + + +/** Group: External mem cryption PSEUDO registers */ +/** Type of mem_xts_pseudo_round_conf register + * SPI memory cryption PSEUDO register + */ +typedef union { + struct { + /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ + uint32_t mem_mode_pseudo:2; + /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be peformed. + */ + uint32_t mem_pseudo_rng_cnt:3; + /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be peformed. + */ + uint32_t mem_pseudo_base:4; + /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be peformed randomly between 0 & + * 2**(inc+1). + */ + uint32_t mem_pseudo_inc:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_xts_pseudo_round_conf_reg_t; + + +/** Group: ECO registers */ +/** Type of mem_registerrnd_eco_high register + * MSPI ECO high register + */ +typedef union { + struct { + /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; + * ECO high register + */ + uint32_t mem_registerrnd_eco_high:32; + }; + uint32_t val; +} spi_mem_registerrnd_eco_high_reg_t; + +/** Type of mem_registerrnd_eco_low register + * MSPI ECO low register + */ +typedef union { + struct { + /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; + * ECO low register + */ + uint32_t mem_registerrnd_eco_low:32; + }; + uint32_t val; +} spi_mem_registerrnd_eco_low_reg_t; + + +/** Group: Version control register */ +/** Type of mem_date register + * SPI0 version control register + */ +typedef union { + struct { + /** mem_date : R/W; bitpos: [27:0]; default: 37753200; + * SPI0 register version. + */ + uint32_t mem_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_date_reg_t; + + +typedef struct { + volatile spi_mem_cmd_reg_t mem_cmd; + uint32_t reserved_004; + volatile spi_mem_ctrl_reg_t mem_ctrl; + volatile spi_mem_ctrl1_reg_t mem_ctrl1; + volatile spi_mem_ctrl2_reg_t mem_ctrl2; + volatile spi_mem_clock_reg_t mem_clock; + volatile spi_mem_user_reg_t mem_user; + volatile spi_mem_user1_reg_t mem_user1; + volatile spi_mem_user2_reg_t mem_user2; + uint32_t reserved_024[2]; + volatile spi_mem_rd_status_reg_t mem_rd_status; + uint32_t reserved_030; + volatile spi_mem_misc_reg_t mem_misc; + uint32_t reserved_038; + volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; + volatile spi_mem_cache_sctrl_reg_t mem_cache_sctrl; + volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; + volatile spi_mem_sram_drd_cmd_reg_t mem_sram_drd_cmd; + volatile spi_mem_sram_dwr_cmd_reg_t mem_sram_dwr_cmd; + volatile spi_mem_sram_clk_reg_t mem_sram_clk; + volatile spi_mem_fsm_reg_t mem_fsm; + uint32_t reserved_058[26]; + volatile spi_mem_int_ena_reg_t mem_int_ena; + volatile spi_mem_int_clr_reg_t mem_int_clr; + volatile spi_mem_int_raw_reg_t mem_int_raw; + volatile spi_mem_int_st_reg_t mem_int_st; + uint32_t reserved_0d0; + volatile spi_mem_ddr_reg_t mem_ddr; + volatile spi_smem_ddr_reg_t smem_ddr; + uint32_t reserved_0dc[9]; + volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; + volatile spi_mem_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_pms_reject_addr_reg_t mem_pms_reject_addr; + volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; + volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; + volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; + volatile spi_mem_timing_cali_reg_t mem_timing_cali; + volatile spi_mem_din_mode_reg_t mem_din_mode; + volatile spi_mem_din_num_reg_t mem_din_num; + volatile spi_mem_dout_mode_reg_t mem_dout_mode; + volatile spi_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_smem_din_mode_reg_t smem_din_mode; + volatile spi_smem_din_num_reg_t smem_din_num; + volatile spi_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_smem_ac_reg_t smem_ac; + volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode; + volatile spi_smem_din_hex_num_reg_t smem_din_hex_num; + volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode; + uint32_t reserved_1b0[20]; + volatile spi_mem_clock_gate_reg_t mem_clock_gate; + volatile spi_mem_nand_flash_en_reg_t mem_nand_flash_en; + volatile spi_mem_nand_flash_sr_addr0_reg_t mem_nand_flash_sr_addr0; + volatile spi_mem_nand_flash_sr_din0_reg_t mem_nand_flash_sr_din0; + volatile spi_mem_nand_flash_cfg_data0_reg_t mem_nand_flash_cfg_data0; + volatile spi_mem_nand_flash_cfg_data1_reg_t mem_nand_flash_cfg_data1; + volatile spi_mem_nand_flash_cfg_data2_reg_t mem_nand_flash_cfg_data2; + uint32_t reserved_21c[9]; + volatile spi_mem_nand_flash_cmd_lut0_reg_t mem_nand_flash_cmd_lut0; + uint32_t reserved_244[15]; + volatile spi_mem_nand_flash_spi_seq0_reg_t mem_nand_flash_spi_seq0; + uint32_t reserved_284[31]; + volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; + uint32_t reserved_304[15]; + volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; + volatile spi_mem_xts_destination_reg_t mem_xts_destination; + volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; + volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; + volatile spi_mem_xts_release_reg_t mem_xts_release; + volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; + volatile spi_mem_xts_state_reg_t mem_xts_state; + volatile spi_mem_xts_date_reg_t mem_xts_date; + uint32_t reserved_360[7]; + volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; + volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; + volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; + volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; + volatile spi_mem_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; + uint32_t reserved_390[24]; + volatile spi_mem_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; + volatile spi_mem_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; + uint32_t reserved_3f8; + volatile spi_mem_date_reg_t mem_date; +} spi_mem_dev_t; + +extern spi_mem_dev_t SPIMEM0; +extern spi_mem_dev_t SPIMEM1; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/spi_reg.h b/components/soc/esp32c61/include/soc/spi_reg.h new file mode 100644 index 0000000000..66a09daf9f --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi_reg.h @@ -0,0 +1,2336 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_CMD_REG register + * Command control register + */ +#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0) +/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Configures the SPI_CLK cycles of SPI CONF state. + * Measurement unit: SPI_CLK clock cycle.\\ + * Can be configured in CONF state. + */ +#define SPI_CONF_BITLEN 0x0003FFFFU +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFFU +#define SPI_CONF_BITLEN_S 0 +/** SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Configures whether or not to synchronize SPI registers from APB clock domain into + * SPI module clock domain. \\ + * 0: Not synchronize \\ + * 1: Synchronize \\ + * This bit is only used in SPI master transfer. + */ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001U +#define SPI_UPDATE_S 23 +/** SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * Configures whether or not to enable user-defined command. \\ + * 0: Not enable \\ + * 1: Enable \\ + * An SPI operation will be triggered when the bit is set. This bit will be cleared + * once the operation is done. Can not be changed by CONF_buf. + */ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001U +#define SPI_USR_S 24 + +/** SPI_ADDR_REG register + * Address value register + */ +#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4) +/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Configures the address to slave. + * Can be configured in CONF state. + */ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_S 0 + +/** SPI_CTRL_REG register + * SPI control register + */ +#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8) +/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ + * 0: Not output \\ + * 1: Output \\ + * Can be configured in CONF state. + */ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001U +#define SPI_DUMMY_OUT_S 3 +/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001U +#define SPI_FADDR_DUAL_S 5 +/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001U +#define SPI_FADDR_QUAD_S 6 +/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; + * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001U +#define SPI_FADDR_OCT_S 7 +/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001U +#define SPI_FCMD_DUAL_S 8 +/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001U +#define SPI_FCMD_QUAD_S 9 +/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; + * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001U +#define SPI_FCMD_OCT_S 10 +/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read + * operations. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001U +#define SPI_FREAD_DUAL_S 14 +/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read + * operations. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001U +#define SPI_FREAD_QUAD_S 15 +/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; + * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read + * operations. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001U +#define SPI_FREAD_OCT_S 16 +/** SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * Configures MISO line polarity. \\ + * 0: Low \\ + * 1: High \\ + * Can be configured in CONF state. + */ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001U +#define SPI_Q_POL_S 18 +/** SPI_D_POL : R/W; bitpos: [19]; default: 1; + * Configures MOSI line polarity. \\ + * 0: Low \\ + * 1: High \\ + * Can be configured in CONF state. + */ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001U +#define SPI_D_POL_S 19 +/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * Configures SPI_HOLD output value when SPI is in idle. \\ + * 0: Output low \\ + * 1: Output high \\ + * Can be configured in CONF state. + */ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001U +#define SPI_HOLD_POL_S 20 +/** SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Configures the output value of write-protect signal when SPI is in idle. \\ + * 0: Output low \\ + * 1: Output high \\ + * Can be configured in CONF state. + */ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001U +#define SPI_WP_POL_S 21 +/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; + * Configures the bit order in read-data (MISO) state. \\ + * 0: MSB first \\ + * 1: LSB first \\ + * Can be configured in CONF state. + */ +#define SPI_RD_BIT_ORDER 0x00000003U +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000003U +#define SPI_RD_BIT_ORDER_S 23 +/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; + * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) + * states. \\ + * 0: MSB first \\ + * 1: LSB first \\ + * Can be configured in CONF state. + */ +#define SPI_WR_BIT_ORDER 0x00000003U +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000003U +#define SPI_WR_BIT_ORDER_S 25 + +/** SPI_CLOCK_REG register + * SPI clock control register + */ +#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc) +/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it + * must be 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_L 0x0000003FU +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003FU +#define SPI_CLKCNT_L_S 0 +/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * Configures the duty cycle of SPI_CLK (high level) in master transfer. + * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). + * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it + * must be 0. \\ + * Can be configured in CONF state. + */ +#define SPI_CLKCNT_H 0x0000003FU +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003FU +#define SPI_CLKCNT_H_S 6 +/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * Configures the divider of SPI_CLK in master transfer. + * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + + * 1). \\ + * Can be configured in CONF state. + */ +#define SPI_CLKCNT_N 0x0000003FU +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003FU +#define SPI_CLKCNT_N_S 12 +/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * Configures the pre-divider of SPI_CLK in master transfer. + * Can be configured in CONF state. + */ +#define SPI_CLKDIV_PRE 0x0000000FU +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000FU +#define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ + * 0: SPI_CLK is divided from APB_CLK.\\ + * 1: SPI_CLK is eqaul to APB_CLK.\\ + * Can be configured in CONF state. + */ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_CLK_EQU_SYSCLK_S 31 + +/** SPI_USER_REG register + * SPI USER control register + */ +#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10) +/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable full-duplex communication. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001U +#define SPI_DOUTDIN_S 0 +/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Configures whether or not to enable QPI mode. \\ + * 0: Disable \\ + * 1: Enable \\ + * This configuration is applicable when the SPI controller works as master or slave. + * Can be configured in CONF state. + */ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001U +#define SPI_QPI_MODE_S 3 +/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001U +#define SPI_OPI_MODE_S 4 +/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * Configures whether or not to change the polarity of TSCK in slave transfer. \\ + * 0: TSCK = SPI_CK_I \\ + * 1: TSCK = !SPI_CK_I \\ + */ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001U +#define SPI_TSCK_I_EDGE_S 5 +/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ + * 0: Not keep low \\ + * 1: Keep low \\ + * Can be configured in CONF state. + */ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001U +#define SPI_CS_HOLD_S 6 +/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001U +#define SPI_CS_SETUP_S 7 +/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * Configures whether or not to change the polarity of RSCK in slave transfer. \\ + * 0: RSCK = !SPI_CK_I \\ + * 1: RSCK = SPI_CK_I \\ + */ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001U +#define SPI_RSCK_I_EDGE_S 8 +/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. + * Can be configured in CONF state. For more information, see Section link. + */ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001U +#define SPI_CK_OUT_EDGE_S 9 +/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the 2-bit mode of read-data phase in write + * operations.\\ + * 0: Not enable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001U +#define SPI_FWRITE_DUAL_S 12 +/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the 4-bit mode of read-data phase in write + * operations. \\ + * 0: Not enable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001U +#define SPI_FWRITE_QUAD_S 13 +/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001U +#define SPI_FWRITE_OCT_S 14 +/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the CONF state for the next transaction + * (segment) in a configurable segmented transfer. \\ + * 0: this transfer will end after the current transaction (segment) is finished. Or + * this is not a configurable segmented transfer. \\ + * 1: this configurable segmented transfer will continue its next transaction + * (segment). \\ + * Can be configured in CONF state. + */ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001U +#define SPI_USR_CONF_NXT_S 15 +/** SPI_SIO : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable 3-line half-duplex communication, where MOSI + * and MISO signals share the same pin.\\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001U +#define SPI_SIO_S 17 +/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable high part mode, i.e., only access to high part + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_USR_MISO_HIGHPART_S 24 +/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable high part mode, i.e., only access to high part + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_USR_MOSI_HIGHPART_S 25 +/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * Configures whether or not to disable SPI clock in DUMMY state. \\ + * 0: Not disable \\ + * 1: Disable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_USR_DUMMY_IDLE_S 26 +/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001U +#define SPI_USR_MOSI_S 27 +/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the read-data (DIN) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001U +#define SPI_USR_MISO_S 28 +/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the DUMMY state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001U +#define SPI_USR_DUMMY_S 29 +/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the address (ADDR) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001U +#define SPI_USR_ADDR_S 30 +/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * Configures whether or not to enable the command (CMD) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001U +#define SPI_USR_COMMAND_S 31 + +/** SPI_USER1_REG register + * SPI USER control register 1 + */ +#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14) +/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * Configures the length of DUMMY state. + * Measurement unit: SPI_CLK clock cycles.\\ + * This value is (the expected cycle number - 1). Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error + * occurs in master full-/half-duplex transfers. \\ + * 0: Not end \\ + * 1: End \\ + */ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001U +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * Configures the length of prepare (PREP) state. + * Measurement unit: SPI_CLK clock cycles.\\ + * This value is equal to the expected cycles - 1. This field is used together with + * SPI_CS_SETUP. Can be configured in CONF state. + */ +#define SPI_CS_SETUP_TIME 0x0000001FU +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001FU +#define SPI_CS_SETUP_TIME_S 17 +/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * Configures the delay cycles of CS pin. + * Measurement unit: SPI_CLK clock cycles. \\ + * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. + */ +#define SPI_CS_HOLD_TIME 0x0000001FU +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001FU +#define SPI_CS_HOLD_TIME_S 22 +/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * Configures the bit length in address state. + * This value is (expected bit number - 1). Can be configured in CONF state. + */ +#define SPI_USR_ADDR_BITLEN 0x0000001FU +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001FU +#define SPI_USR_ADDR_BITLEN_S 27 + +/** SPI_USER2_REG register + * SPI USER control register 2 + */ +#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18) +/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * Configures the command value. + * Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_S 0 +/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty + * error occurs in master full-/half-duplex transfers. \\ + * 0: Not end \\ + * 1: End \\ + */ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * Configures the bit length of command state. + * This value is (expected bit number - 1). Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_S 28 + +/** SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c) +/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Configures the data bit length of SPI transfer in DMA-controlled master transfer or + * in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer + * in DMA-controlled slave transfer. + * This value shall be (expected bit_num - 1). Can be configured in CONF state. + */ +#define SPI_MS_DATA_BITLEN 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_S 0 + +/** SPI_MISC_REG register + * SPI misc register + */ +#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20) +/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001U +#define SPI_CS0_DIS_S 0 +/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001U +#define SPI_CS1_DIS_S 1 +/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001U +#define SPI_CS2_DIS_S 2 +/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001U +#define SPI_CS3_DIS_S 3 +/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001U +#define SPI_CS4_DIS_S 4 +/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001U +#define SPI_CS5_DIS_S 5 +/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * Configures whether or not to disable SPI_CLK output.\\ + * 0: Enable\\ + * 1: Disable\\ + * Can be configured in CONF state. + */ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001U +#define SPI_CK_DIS_S 6 +/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ + * 0: SPI_CS$n is low active.\\ + * 1: SPI_CS$n is high active.\\ + * Can be configured in CONF state. + */ +#define SPI_MASTER_CS_POL 0x0000003FU +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003FU +#define SPI_MASTER_CS_POL_S 7 +/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S) +#define SPI_CLK_DATA_DTR_EN_V 0x00000001U +#define SPI_CLK_DATA_DTR_EN_S 16 +/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S) +#define SPI_DATA_DTR_EN_V 0x00000001U +#define SPI_DATA_DTR_EN_S 17 +/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S) +#define SPI_ADDR_DTR_EN_V 0x00000001U +#define SPI_ADDR_DTR_EN_S 18 +/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S) +#define SPI_CMD_DTR_EN_V 0x00000001U +#define SPI_CMD_DTR_EN_S 19 +/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * Configures whether or not invert SPI slave input CS polarity.\\ + * 0: Not change\\ + * 1: Invert\\ + * Can be configured in CONF state. + */ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001U +#define SPI_SLAVE_CS_POL_S 23 +/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001U +#define SPI_DQS_IDLE_EDGE_S 24 +/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ + * 0: Low\\ + * 1: High\\ + * Can be configured in CONF state. + */ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001U +#define SPI_CK_IDLE_EDGE_S 29 +/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * Configures whether or not to keep the SPI_CS line low.\\ + * 0: Not keep low\\ + * 1: Keep low\\ + * Can be configured in CONF state. + */ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_CS_KEEP_ACTIVE_S 30 +/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001U +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/** SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24) +/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures the input mode for FSPID signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + */ +#define SPI_DIN0_MODE 0x00000003U +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003U +#define SPI_DIN0_MODE_S 0 +/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * Configures the input mode for FSPIQ signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + */ +#define SPI_DIN1_MODE 0x00000003U +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003U +#define SPI_DIN1_MODE_S 2 +/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * Configures the input mode for FSPIWP signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + */ +#define SPI_DIN2_MODE 0x00000003U +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003U +#define SPI_DIN2_MODE_S 4 +/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures the input mode for FSPIHD signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + * + */ +#define SPI_DIN3_MODE 0x00000003U +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003U +#define SPI_DIN3_MODE_S 6 +/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN4_MODE 0x00000003U +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000003U +#define SPI_DIN4_MODE_S 8 +/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN5_MODE 0x00000003U +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000003U +#define SPI_DIN5_MODE_S 10 +/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN6_MODE 0x00000003U +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000003U +#define SPI_DIN6_MODE_S 12 +/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN7_MODE 0x00000003U +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000003U +#define SPI_DIN7_MODE_S 14 +/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing + * module.\\ + * 0: Disable\\ + * 1: Enable\\ + * Can be configured in CONF state. + */ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001U +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/** SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28) +/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ +#define SPI_DIN0_NUM 0x00000003U +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003U +#define SPI_DIN0_NUM_S 0 +/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ +#define SPI_DIN1_NUM 0x00000003U +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003U +#define SPI_DIN1_NUM_S 2 +/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * Configures the delays to input signal FSPIWP based on the setting of + * SPI_DIN2_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ +#define SPI_DIN2_NUM 0x00000003U +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003U +#define SPI_DIN2_NUM_S 4 +/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * Configures the delays to input signal FSPIHD based on the setting of + * SPI_DIN3_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ +#define SPI_DIN3_NUM 0x00000003U +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003U +#define SPI_DIN3_NUM_S 6 +/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN4_NUM 0x00000003U +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003U +#define SPI_DIN4_NUM_S 8 +/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN5_NUM 0x00000003U +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003U +#define SPI_DIN5_NUM_S 10 +/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN6_NUM 0x00000003U +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003U +#define SPI_DIN6_NUM_S 12 +/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN7_NUM 0x00000003U +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003U +#define SPI_DIN7_NUM_S 14 + +/** SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c) +/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * Configures the output mode for FSPID signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001U +#define SPI_DOUT0_MODE_S 0 +/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * Configures the output mode for FSPIQ signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001U +#define SPI_DOUT1_MODE_S 1 +/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * Configures the output mode for FSPIWP signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001U +#define SPI_DOUT2_MODE_S 2 +/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * Configures the output mode for FSPIHD signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001U +#define SPI_DOUT3_MODE_S 3 +/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000001U +#define SPI_DOUT4_MODE_S 4 +/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000001U +#define SPI_DOUT5_MODE_S 5 +/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000001U +#define SPI_DOUT6_MODE_S 6 +/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000001U +#define SPI_DOUT7_MODE_S 7 +/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000001U +#define SPI_D_DQS_MODE_S 8 + +/** SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30) +/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Represents whether or not the DMA TX FIFO is ready for sending data.\\ + * 0: Ready\\ + * 1: Not ready\\ + */ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_S 0 +/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; + * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ + * 0: Ready\\ + * 1: Not ready\\ + */ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_S 1 +/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable DMA-controlled segmented transfer in slave + * half-duplex communication.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001U +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the + * size of the received data, \\1: the data in all the following Wr_DMA transactions + * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, + * but in the following transactions,\\ + * + * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions + * will be received. + * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will + * not be received. + */ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the + * size of the transmitted data,\\ + * 1: the data in the following transactions will not be updated, i.e. the old data is + * transmitted repeatedly.\\ + * 0: the data in this transaction will not be updated. But in the following + * transactions,\\ + * + * - if new data is filled in DMA TX FIFO, new data will be transmitted. + * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. + */ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: In a DAM-controlled transfer, if the bit number of transferred data is equal to + * (SPI_MS_DATA_BITLEN + 1), then GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW will be set by + * hardware. 0: GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW is set by SPI_TRANS_DONE_INT event in + * a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented + * transfer. + */ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001U +#define SPI_RX_EOF_EN_S 21 +/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable DMA-controlled receive data transfer.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001U +#define SPI_DMA_RX_ENA_S 27 +/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable DMA-controlled send data transfer.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001U +#define SPI_DMA_TX_ENA_S 28 +/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ + * 0: Not reset\\ + * 1: Reset\\ + * spi_rx_afifo is used to receive data in SPI master and slave transfer. + */ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001U +#define SPI_RX_AFIFO_RST_S 29 +/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ + * 0: Not reset\\ + * 1: Reset\\ + * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. + */ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001U +#define SPI_BUF_AFIFO_RST_S 30 +/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ + * 0: Not reset\\ + * 1: Reset\\ + * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. + */ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001U +#define SPI_DMA_AFIFO_RST_S 31 + +/** SPI_DMA_INT_ENA_REG register + * SPI interrupt enable register + */ +#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable SPI_SLV_EX_QPI_INT interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable SPI_SLV_EN_QPI_INT interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable SPI_SLV_CMD7_INT interrupt. + */ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD7_INT_ENA_S 4 +/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable SPI_SLV_CMD8_INT interrupt. + */ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD8_INT_ENA_S 5 +/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable SPI_SLV_CMD9_INT interrupt. + */ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD9_INT_ENA_S 6 +/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable SPI_SLV_CMDA_INT interrupt. + */ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001U +#define SPI_SLV_CMDA_INT_ENA_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to enable SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_TRANS_DONE_INT_ENA_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * Write 1 to enable SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001U +#define SPI_APP2_INT_ENA_S 19 +/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * Write 1 to enable SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001U +#define SPI_APP1_INT_ENA_S 20 + +/** SPI_DMA_INT_CLR_REG register + * SPI interrupt clear register + */ +#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38) +/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear SPI_SLV_EX_QPI_INT interrupt. + */ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear SPI_SLV_EN_QPI_INT interrupt. + */ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear SPI_SLV_CMD7_INT interrupt. + */ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD7_INT_CLR_S 4 +/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear SPI_SLV_CMD8_INT interrupt. + */ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD8_INT_CLR_S 5 +/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear SPI_SLV_CMD9_INT interrupt. + */ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD9_INT_CLR_S 6 +/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear SPI_SLV_CMDA_INT interrupt. + */ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001U +#define SPI_SLV_CMDA_INT_CLR_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_TRANS_DONE_INT_CLR_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * Write 1 to clear SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001U +#define SPI_APP2_INT_CLR_S 19 +/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * Write 1 to clear SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001U +#define SPI_APP1_INT_CLR_S 20 + +/** SPI_DMA_INT_RAW_REG register + * SPI interrupt raw register + */ +#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c) +/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt. + */ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt. + */ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of SPI_SLV_CMD7_INT interrupt. + */ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD7_INT_RAW_S 4 +/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of SPI_SLV_CMD8_INT interrupt. + */ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD8_INT_RAW_S 5 +/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of SPI_SLV_CMD9_INT interrupt. + */ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD9_INT_RAW_S 6 +/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of SPI_SLV_CMDA_INT interrupt. + */ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001U +#define SPI_SLV_CMDA_INT_RAW_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt status of SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_TRANS_DONE_INT_RAW_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by + * the application. + */ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001U +#define SPI_APP2_INT_RAW_S 19 +/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by + * the application. + */ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001U +#define SPI_APP1_INT_RAW_S 20 + +/** SPI_DMA_INT_ST_REG register + * SPI interrupt status register + */ +#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The interrupt status of SPI_SLV_EX_QPI_INT interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The interrupt status of SPI_SLV_EN_QPI_INT interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The interrupt status of SPI_SLV_CMD7_INT interrupt. + */ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001U +#define SPI_SLV_CMD7_INT_ST_S 4 +/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The interrupt status of SPI_SLV_CMD8_INT interrupt. + */ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001U +#define SPI_SLV_CMD8_INT_ST_S 5 +/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The interrupt status of SPI_SLV_CMD9_INT interrupt. + */ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001U +#define SPI_SLV_CMD9_INT_ST_S 6 +/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The interrupt status of SPI_SLV_CMDA_INT interrupt. + */ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001U +#define SPI_SLV_CMDA_INT_ST_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The interrupt status of SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_TRANS_DONE_INT_ST_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The interrupt status of SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The interrupt status of SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001U +#define SPI_APP2_INT_ST_S 19 +/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The interrupt status of SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001U +#define SPI_APP1_INT_ST_S 20 + +/** SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44) +/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; + * Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0; + * Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0; + * Write 1 to set SPI_SLV_EX_QPI_INT interrupt. + */ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S) +#define SPI_SLV_EX_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0; + * Write 1 to set SPI_SLV_EN_QPI_INT interrupt. + */ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S) +#define SPI_SLV_EN_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0; + * Write 1 to set SPI_SLV_CMD7_INT interrupt. + */ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S) +#define SPI_SLV_CMD7_INT_SET_V 0x00000001U +#define SPI_SLV_CMD7_INT_SET_S 4 +/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0; + * Write 1 to set SPI_SLV_CMD8_INT interrupt. + */ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S) +#define SPI_SLV_CMD8_INT_SET_V 0x00000001U +#define SPI_SLV_CMD8_INT_SET_S 5 +/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0; + * Write 1 to set SPI_SLV_CMD9_INT interrupt. + */ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S) +#define SPI_SLV_CMD9_INT_SET_V 0x00000001U +#define SPI_SLV_CMD9_INT_SET_S 6 +/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0; + * Write 1 to set SPI_SLV_CMDA_INT interrupt. + */ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S) +#define SPI_SLV_CMDA_INT_SET_V 0x00000001U +#define SPI_SLV_CMDA_INT_SET_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0; + * Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0; + * Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * Write 1 to set SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S) +#define SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_TRANS_DONE_INT_SET_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0; + * Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0; + * Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * Write 1 to set SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * Write 1 to set SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S) +#define SPI_APP2_INT_SET_V 0x00000001U +#define SPI_APP2_INT_SET_S 19 +/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * Write 1 to set SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S) +#define SPI_APP1_INT_SET_V 0x00000001U +#define SPI_APP1_INT_SET_S 20 + +/** SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98) +/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF0 0xFFFFFFFFU +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFFU +#define SPI_BUF0_S 0 + +/** SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c) +/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF1 0xFFFFFFFFU +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFFU +#define SPI_BUF1_S 0 + +/** SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0) +/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF2 0xFFFFFFFFU +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFFU +#define SPI_BUF2_S 0 + +/** SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4) +/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF3 0xFFFFFFFFU +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFFU +#define SPI_BUF3_S 0 + +/** SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8) +/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF4 0xFFFFFFFFU +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFFU +#define SPI_BUF4_S 0 + +/** SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac) +/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF5 0xFFFFFFFFU +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFFU +#define SPI_BUF5_S 0 + +/** SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0) +/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF6 0xFFFFFFFFU +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFFU +#define SPI_BUF6_S 0 + +/** SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4) +/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF7 0xFFFFFFFFU +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFFU +#define SPI_BUF7_S 0 + +/** SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8) +/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF8 0xFFFFFFFFU +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFFU +#define SPI_BUF8_S 0 + +/** SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc) +/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF9 0xFFFFFFFFU +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFFU +#define SPI_BUF9_S 0 + +/** SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0) +/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF10 0xFFFFFFFFU +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFFU +#define SPI_BUF10_S 0 + +/** SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4) +/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF11 0xFFFFFFFFU +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFFU +#define SPI_BUF11_S 0 + +/** SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8) +/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF12 0xFFFFFFFFU +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFFU +#define SPI_BUF12_S 0 + +/** SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc) +/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF13 0xFFFFFFFFU +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFFU +#define SPI_BUF13_S 0 + +/** SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0) +/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF14 0xFFFFFFFFU +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFFU +#define SPI_BUF14_S 0 + +/** SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4) +/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * 32-bit data buffer $n. + */ +#define SPI_BUF15 0xFFFFFFFFU +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFFU +#define SPI_BUF15_S 0 + +/** SPI_SLAVE_REG register + * SPI slave control register + */ +#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0) +/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures SPI clock mode.\\ + * 0: SPI clock is off when CS becomes inactive.\\ + * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ + * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ + * 3: SPI clock is always on.\\ + * Can be configured in CONF state. + */ +#define SPI_CLK_MODE 0x00000003U +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003U +#define SPI_CLK_MODE_S 0 +/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * Configure clock mode.\\ + * 0: Support SPI clock mode 0 or 2. See Table link.\\ + * 1: Support SPI clock mode 1 or 3. See Table link.\\ + */ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001U +#define SPI_CLK_MODE_13_S 2 +/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * Configures the edge of output data.\\ + * 0: Output data at TSCK rising edge.\\ + * 1: Output data at RSCK rising edge.\\ + */ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001U +#define SPI_RSCK_DATA_OUT_S 3 +/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Rd_DMA transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Wr_DMA transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Rd_BUF transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Wr_BUF transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ +#define SPI_SLV_LAST_BYTE_STRB 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_M (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S) +#define SPI_SLV_LAST_BYTE_STRB_V 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_S 12 +/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * Configures the magic value of BM table in DMA-controlled configurable segmented + * transfer. + */ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Configures SPI work mode.\\ + * 0: Master\\ + * 1: Slave\\ + */ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001U +#define SPI_SLAVE_MODE_S 26 +/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Configures whether to reset the SPI clock line, CS line, and data line via + * software.\\ + * 0: Not reset\\ + * 1: Reset\\ + * Can be configured in CONF state. + */ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001U +#define SPI_SOFT_RESET_S 27 +/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the CONF state of current DMA-controlled + * configurable segmented transfer.\\ + * 0: No effect, which means the current transfer is not a configurable segmented + * transfer.\\ + * 1: Enable, which means a configurable segmented transfer is started.\\ + */ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001U +#define SPI_USR_CONF_S 28 +/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; + * Configures whether or not to wait DMA TX data gets ready before starting SPI + * transfer in master full-duplex transfer.\\ + * 0: Not wait\\ + * 1: Wait\\ + */ +#define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_V 0x00000001U +#define SPI_MST_FD_WAIT_DMA_TX_DATA_S 29 + +/** SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4) +/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * Configures the transferred data bit length in SPI slave full-/half-duplex modes. + */ +#define SPI_SLV_DATA_BITLEN 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_S 0 +/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * Configures the command value in slave mode. + */ +#define SPI_SLV_LAST_COMMAND 0x000000FFU +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FFU +#define SPI_SLV_LAST_COMMAND_S 18 +/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * Configures the address value in slave mode. + */ +#define SPI_SLV_LAST_ADDR 0x0000003FU +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003FU +#define SPI_SLV_LAST_ADDR_S 26 + +/** SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable clock gate.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001U +#define SPI_MST_CLK_ACTIVE_S 1 +/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001U +#define SPI_MST_CLK_SEL_S 2 + +/** SPI_DATE_REG register + * Version control + */ +#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0) +/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931; + * Version control register. + */ +#define SPI_DATE 0x0FFFFFFFU +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFFU +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/spi_struct.h b/components/soc/esp32c61/include/soc/spi_struct.h new file mode 100644 index 0000000000..f84df62b84 --- /dev/null +++ b/components/soc/esp32c61/include/soc/spi_struct.h @@ -0,0 +1,1625 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Configures the SPI_CLK cycles of SPI CONF state. + * Measurement unit: SPI_CLK clock cycle.\\ + * Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Configures whether or not to synchronize SPI registers from APB clock domain into + * SPI module clock domain. \\ + * 0: Not synchronize \\ + * 1: Synchronize \\ + * This bit is only used in SPI master transfer. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * Configures whether or not to enable user-defined command. \\ + * 0: Not enable \\ + * 1: Enable \\ + * An SPI operation will be triggered when the bit is set. This bit will be cleared + * once the operation is done. Can not be changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Configures the address to slave. + * Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable full-duplex communication. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Configures whether or not to enable QPI mode. \\ + * 0: Disable \\ + * 1: Enable \\ + * This configuration is applicable when the SPI controller works as master or slave. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * Configures whether or not to change the polarity of TSCK in slave transfer. \\ + * 0: TSCK = SPI_CK_I \\ + * 1: TSCK = !SPI_CK_I \\ + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ + * 0: Not keep low \\ + * 1: Keep low \\ + * Can be configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * Configures whether or not to change the polarity of RSCK in slave transfer. \\ + * 0: RSCK = !SPI_CK_I \\ + * 1: RSCK = SPI_CK_I \\ + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. + * Can be configured in CONF state. For more information, see Section link. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the 2-bit mode of read-data phase in write + * operations.\\ + * 0: Not enable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the 4-bit mode of read-data phase in write + * operations. \\ + * 0: Not enable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the CONF state for the next transaction + * (segment) in a configurable segmented transfer. \\ + * 0: this transfer will end after the current transaction (segment) is finished. Or + * this is not a configurable segmented transfer. \\ + * 1: this configurable segmented transfer will continue its next transaction + * (segment). \\ + * Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable 3-line half-duplex communication, where MOSI + * and MISO signals share the same pin.\\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable high part mode, i.e., only access to high part + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable high part mode, i.e., only access to high part + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * Configures whether or not to disable SPI clock in DUMMY state. \\ + * 0: Not disable \\ + * 1: Disable \\ + * Can be configured in CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the read-data (DIN) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the DUMMY state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the address (ADDR) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * Configures whether or not to enable the command (CMD) state of an operation. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * Configures the length of DUMMY state. + * Measurement unit: SPI_CLK clock cycles.\\ + * This value is (the expected cycle number - 1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error + * occurs in master full-/half-duplex transfers. \\ + * 0: Not end \\ + * 1: End \\ + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * Configures the length of prepare (PREP) state. + * Measurement unit: SPI_CLK clock cycles.\\ + * This value is equal to the expected cycles - 1. This field is used together with + * SPI_CS_SETUP. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * Configures the delay cycles of CS pin. + * Measurement unit: SPI_CLK clock cycles. \\ + * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * Configures the bit length in address state. + * This value is (expected bit number - 1). Can be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * Configures the command value. + * Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty + * error occurs in master full-/half-duplex transfers. \\ + * 0: Not end \\ + * 1: End \\ + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * Configures the bit length of command state. + * This value is (expected bit number - 1). Can be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ + * 0: Not output \\ + * 1: Output \\ + * Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read + * operations. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read + * operations. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read + * operations. \\ + * 0: Disable \\ + * 1: Enable \\ + * Can be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * Configures MISO line polarity. \\ + * 0: Low \\ + * 1: High \\ + * Can be configured in CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * Configures MOSI line polarity. \\ + * 0: Low \\ + * 1: High \\ + * Can be configured in CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * Configures SPI_HOLD output value when SPI is in idle. \\ + * 0: Output low \\ + * 1: Output high \\ + * Can be configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Configures the output value of write-protect signal when SPI is in idle. \\ + * 0: Output low \\ + * 1: Output high \\ + * Can be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * Configures the bit order in read-data (MISO) state. \\ + * 0: MSB first \\ + * 1: LSB first \\ + * Can be configured in CONF state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) + * states. \\ + * 0: MSB first \\ + * 1: LSB first \\ + * Can be configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * Configures the data bit length of SPI transfer in DMA-controlled master transfer or + * in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer + * in DMA-controlled slave transfer. + * This value shall be (expected bit_num - 1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * Configures whether or not to disable SPI_CS$n pin.\\ + * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ + * 1: Disable SPI_CS$n pin.\\ + * Can be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * Configures whether or not to disable SPI_CLK output.\\ + * 0: Enable\\ + * 1: Disable\\ + * Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ + * 0: SPI_CS$n is low active.\\ + * 1: SPI_CS$n is high active.\\ + * Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * Configures whether or not invert SPI slave input CS polarity.\\ + * 0: Not change\\ + * 1: Invert\\ + * Can be configured in CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ + * 0: Low\\ + * 1: High\\ + * Can be configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * Configures whether or not to keep the SPI_CS line low.\\ + * 0: Not keep low\\ + * 1: Keep low\\ + * Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Represents whether or not the DMA TX FIFO is ready for sending data.\\ + * 0: Ready\\ + * 1: Not ready\\ + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ + * 0: Ready\\ + * 1: Not ready\\ + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable DMA-controlled segmented transfer in slave + * half-duplex communication.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the + * size of the received data, \\1: the data in all the following Wr_DMA transactions + * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, + * but in the following transactions,\\ + * + * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions + * will be received. + * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will + * not be received. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the + * size of the transmitted data,\\ + * 1: the data in the following transactions will not be updated, i.e. the old data is + * transmitted repeatedly.\\ + * 0: the data in this transaction will not be updated. But in the following + * transactions,\\ + * + * - if new data is filled in DMA TX FIFO, new data will be transmitted. + * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: In a DAM-controlled transfer, if the bit number of transferred data is equal to + * (SPI_MS_DATA_BITLEN + 1), then GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW will be set by + * hardware. 0: GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW is set by SPI_TRANS_DONE_INT event in + * a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented + * transfer. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable DMA-controlled receive data transfer.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable DMA-controlled send data transfer.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ + * 0: Not reset\\ + * 1: Reset\\ + * spi_rx_afifo is used to receive data in SPI master and slave transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ + * 0: Not reset\\ + * 1: Reset\\ + * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ + * 0: Not reset\\ + * 1: Reset\\ + * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * Configures SPI clock mode.\\ + * 0: SPI clock is off when CS becomes inactive.\\ + * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ + * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ + * 3: SPI clock is always on.\\ + * Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * Configure clock mode.\\ + * 0: Support SPI clock mode 0 or 2. See Table link.\\ + * 1: Support SPI clock mode 1 or 3. See Table link.\\ + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * Configures the edge of output data.\\ + * 0: Output data at TSCK rising edge.\\ + * 1: Output data at RSCK rising edge.\\ + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Rd_DMA transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Wr_DMA transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Rd_BUF transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length + * of Wr_BUF transfer.\\ + * 0: Not use\\ + * 1: Use\\ + */ + uint32_t slv_wrbuf_bitlen_en:1; + /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ + uint32_t slv_last_byte_strb:8; + uint32_t reserved_20:2; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * Configures the magic value of BM table in DMA-controlled configurable segmented + * transfer. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Configures SPI work mode.\\ + * 0: Master\\ + * 1: Slave\\ + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Configures whether to reset the SPI clock line, CS line, and data line via + * software.\\ + * 0: Not reset\\ + * 1: Reset\\ + * Can be configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the CONF state of current DMA-controlled + * configurable segmented transfer.\\ + * 0: No effect, which means the current transfer is not a configurable segmented + * transfer.\\ + * 1: Enable, which means a configurable segmented transfer is started.\\ + */ + uint32_t usr_conf:1; + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * Configures whether or not to wait DMA TX data gets ready before starting SPI + * transfer in master full-duplex transfer.\\ + * 0: Not wait\\ + * 1: Wait\\ + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * Configures the transferred data bit length in SPI slave full-/half-duplex modes. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * Configures the command value in slave mode. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * Configures the address value in slave mode. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * Configures the duty cycle of SPI_CLK (high level) in master transfer. + * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). + * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it + * must be 0. \\ + * Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * Configures the divider of SPI_CLK in master transfer. + * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + + * 1). \\ + * Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * Configures the pre-divider of SPI_CLK in master transfer. + * Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ + * 0: SPI_CLK is divided from APB_CLK.\\ + * 1: SPI_CLK is eqaul to APB_CLK.\\ + * Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable clock gate.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * Configures the input mode for FSPID signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * Configures the input mode for FSPIQ signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * Configures the input mode for FSPIWP signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * Configures the input mode for FSPIHD signal.\\ + * 0: Input without delay\\ + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * rising edge cycle\\ + * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle\\ + * Can be configured in CONF state. + * + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing + * module.\\ + * 0: Disable\\ + * 1: Enable\\ + * Can be configured in CONF state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * Configures the delays to input signal FSPIWP based on the setting of + * SPI_DIN2_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * Configures the delays to input signal FSPIHD based on the setting of + * SPI_DIN3_MODE.\\ + * 0: Delayed by 1 clock cycle\\ + * 1: Delayed by 2 clock cycles\\ + * 2: Delayed by 3 clock cycles\\ + * 3: Delayed by 4 clock cycles\\ + * Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * Configures the output mode for FSPID signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * Configures the output mode for FSPIQ signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * Configures the output mode for FSPIWP signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * Configures the output mode for FSPIHD signal.\\ + * 0: Output without delay\\ + * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Can be configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable SPI_SLV_EX_QPI_INT interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable SPI_SLV_EN_QPI_INT interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable SPI_SLV_CMD7_INT interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable SPI_SLV_CMD8_INT interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable SPI_SLV_CMD9_INT interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable SPI_SLV_CMDA_INT interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to enable SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * Write 1 to enable SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * Write 1 to enable SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear SPI_SLV_EX_QPI_INT interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear SPI_SLV_EN_QPI_INT interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear SPI_SLV_CMD7_INT interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear SPI_SLV_CMD8_INT interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear SPI_SLV_CMD9_INT interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear SPI_SLV_CMDA_INT interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * Write 1 to clear SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * Write 1 to clear SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of SPI_SLV_CMD7_INT interrupt. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of SPI_SLV_CMD8_INT interrupt. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of SPI_SLV_CMD9_INT interrupt. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of SPI_SLV_CMDA_INT interrupt. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt status of SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by + * the application. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by + * the application. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The interrupt status of SPI_SLV_EX_QPI_INT interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The interrupt status of SPI_SLV_EN_QPI_INT interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The interrupt status of SPI_SLV_CMD7_INT interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The interrupt status of SPI_SLV_CMD8_INT interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The interrupt status of SPI_SLV_CMD9_INT interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The interrupt status of SPI_SLV_CMDA_INT interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The interrupt status of SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The interrupt status of SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The interrupt status of SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The interrupt status of SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * Write 1 to set SPI_SLV_EX_QPI_INT interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * Write 1 to set SPI_SLV_EN_QPI_INT interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * Write 1 to set SPI_SLV_CMD7_INT interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * Write 1 to set SPI_SLV_CMD8_INT interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * Write 1 to set SPI_SLV_CMD9_INT interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * Write 1 to set SPI_SLV_CMDA_INT interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * Write 1 to set SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * Write 1 to set SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * Write 1 to set SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * Write 1 to set SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + + +/** Group: CPU-controlled data buffer */ +/** Type of wn register + * SPI CPU-controlled buffer n + */ +typedef union { + struct { + /** buf : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf:32; + }; + uint32_t val; +} spi_wn_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716931; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_wn_reg_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/sys_timer_reg.h b/components/soc/esp32c61/include/soc/sys_timer_reg.h new file mode 100644 index 0000000000..5a3520b185 --- /dev/null +++ b/components/soc/esp32c61/include/soc/sys_timer_reg.h @@ -0,0 +1,680 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable generation of ETM events.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SYSTIMER_ETM_EN (BIT(1)) +#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) +#define SYSTIMER_ETM_EN_V 0x00000001U +#define SYSTIMER_ETM_EN_S 1 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable COMP2.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN. + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN. + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * Configures whether or not UNIT1 is stalled when CORE1 is stalled. \\ + * 0: UNIT1 is not stalled. \\ + * 1: UNIT1 is stalled.\\ + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in + * SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in + * SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in + * SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable UNIT1. \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * Configures whether or not to enable UNIT0. \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * Configures register clock gating. \\ + * 0: Only enable needed clock for register read or write operations. \\ + * 1: Register clock is always enabled for read and write operations. \\ + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * Read UNIT0 value to registers + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * Represents UNIT0 value is synchronized and valid. + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value + * to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\ + * 0: No effect\\ + * 1: Update timer UNIT0 \\ + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * Read UNIT1 value to registers + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * Represents UNIT1 value is synchronized and valid. + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * Configures whether or not to update timer UNIT1, i.e., reads the UNIT1 count value + * to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO. \\ + * 0: No effect \\ + * 1: Update timer UNIT1\\ + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * High 20 bits to be loaded to UNIT0 + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * Configures the value to be loaded to UNIT0, high 20 bits. + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * Low 32 bits to be loaded to UNIT0 + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Configures the value to be loaded to UNIT0, low 32 bits. + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * High 20 bits to be loaded to UNIT1 + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * Configures the value to be loaded to UNIT1, high 20 bits. + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * Low 32 bits to be loaded to UNIT1 + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Configures the value to be loaded to UNIT1, low 32 bits. + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * Alarm value to be loaded to COMP0, high 20 bits + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * Configures the alarm value to be loaded to COMP0, high 20 bits. + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * Alarm value to be loaded to COMP0, low 32 bits + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * Configures the alarm value to be loaded to COMP0, low 32 bits. + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * Alarm value to be loaded to COMP1, high 20 bits + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * Configures the alarm value to be loaded to COMP1, high 20 bits. + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * Alarm value to be loaded to COMP1, low 32 bits + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * Configures the alarm value to be loaded to COMP1, low 32 bits. + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * Alarm value to be loaded to COMP2, high 20 bits + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * Configures the alarm value to be loaded to COMP2, high 20 bits. + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * Alarm value to be loaded to COMP2, low 32 bits + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * Configures the alarm value to be loaded to COMP2, low 32 bits. + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * Configure COMP0 alarm mode + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * Configures COMP0 alarm period. + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Selects the two alarm modes for COMP0. \\ + * 0: Target mode\\ + * 1: Period mode\\ + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * Chooses the counter value for comparison with COMP0.\\ + * 0: Use the count value from UNIT$0\\ + * 1: Use the count value from UNIT$1\\ + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * Configure COMP1 alarm mode + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * Configures COMP1 alarm period. + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE. + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * Chooses the counter value for comparison with COMP1. See details in + * SYSTIMER_TARGET0_TIMER_UNIT_SEL. + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * Configure COMP2 alarm mode + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * Configures COMP2 alarm period. + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Configures Configures the two alarm modes for COMP2. See details in + * SYSTIMER_TARGET0_PERIOD_MODE. + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * Chooses the counter value for comparison with COMP2. See details in + * SYSTIMER_TARGET0_TIMER_UNIT_SEL. + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * UNIT0 value, high 20 bits + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * Represents UNIT0 read value, high 20 bits. + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * UNIT0 value, low 32 bits + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * Represents UNIT0 read value, low 32 bits. + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * UNIT1 value, high 20 bits + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * Represents UNIT1 read value, high 20 bits. + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * UNIT1 value, low 32 bits + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * Represents UNIT1 read value, low 32 bits. + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * COMP0 synchronization register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm + * value/period to COMP0.\\ + * 0: No effect \\ + * 1: Enable COMP0 synchronization\\ + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * COMP1 synchronization register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable COMP1 synchronization, i.e., reload the alarm + * value/period to COMP1. \\ + * 0: No effect \\ + * 1: Enable COMP1 synchronization\\ + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * COMP2 synchronization register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable COMP2 synchronization, i.e., reload the alarm + * value/period to COMP2.\\ + * 0: No effect \\ + * 1: Enable COMP2 synchronization\\ + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * UNIT0 synchronization register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * Configures whether or not to reload the value of UNIT0, i.e., reloads the values of + * SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0. \\ + * 0: No effect \\ + * 1: Reload the value of UNIT0\\ + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * UNIT1 synchronization register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * Configures whether or not to reload the value of UNIT1, i.e., reload the values of + * SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1. \\ + * 0: No effect \\ + * 1: Reload the value of UNIT1\\ + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * Interrupt enable register of system timer + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable SYSTIMER_TARGET0_INT. + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable SYSTIMER_TARGET1_INT. + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable SYSTIMER_TARGET2_INT. + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * Interrupt raw register of system timer + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of SYSTIMER_TARGET0_INT. + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of SYSTIMER_TARGET1_INT. + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of SYSTIMER_TARGET2_INT. + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * Interrupt clear register of system timer + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear SYSTIMER_TARGET0_INT. + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear SYSTIMER_TARGET1_INT. + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear SYSTIMER_TARGET2_INT. + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * Interrupt status register of system timer + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * The interrupt status of SYSTIMER_TARGET0_INT. + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * The interrupt status of SYSTIMER_TARGET1_INT. + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * The interrupt status of SYSTIMER_TARGET2_INT. + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * Actual target value of COMP0, low 32 bits + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * Represents the actual target value of COMP0, low 32 bits. + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * Actual target value of COMP0, high 20 bits + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * Represents the actual target value of COMP0, high 20 bits. + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * Actual target value of COMP1, low 32 bits + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * Represents the actual target value of COMP1, low 32 bits. + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * Actual target value of COMP1, high 20 bits + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * Represents the actual target value of COMP1, high 20 bits. + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * Actual target value of COMP2, low 32 bits + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * Represents the actual target value of COMP2, low 32 bits. + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * Actual target value of COMP2, high 20 bits + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * Represents the actual target value of COMP2, high 20 bits. + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * Version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 36774432; + * Version control register. + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/sys_timer_struct.h b/components/soc/esp32c61/include/soc/sys_timer_struct.h new file mode 100644 index 0000000000..df6721e4a1 --- /dev/null +++ b/components/soc/esp32c61/include/soc/sys_timer_struct.h @@ -0,0 +1,729 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo:1; + /** etm_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable generation of ETM events.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t etm_en:1; + uint32_t reserved_2:20; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable COMP2.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t target2_work_en:1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN. + */ + uint32_t target1_work_en:1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN. + */ + uint32_t target0_work_en:1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * Configures whether or not UNIT1 is stalled when CORE1 is stalled. \\ + * 0: UNIT1 is not stalled. \\ + * 1: UNIT1 is stalled.\\ + */ + uint32_t timer_unit1_core1_stall_en:1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in + * SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. + */ + uint32_t timer_unit1_core0_stall_en:1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in + * SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. + */ + uint32_t timer_unit0_core1_stall_en:1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in + * SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. + */ + uint32_t timer_unit0_core0_stall_en:1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable UNIT1. \\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t timer_unit1_work_en:1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * Configures whether or not to enable UNIT0. \\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t timer_unit0_work_en:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures register clock gating. \\ + * 0: Only enable needed clock for register read or write operations. \\ + * 1: Register clock is always enabled for read and write operations. \\ + */ + uint32_t clk_en:1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit0_op register + * Read UNIT0 value to registers + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * Represents UNIT0 value is synchronized and valid. + */ + uint32_t timer_unit0_value_valid:1; + /** timer_unit0_update : WT; bitpos: [30]; default: 0; + * Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value + * to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\ + * 0: No effect\\ + * 1: Update timer UNIT0 \\ + */ + uint32_t timer_unit0_update:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} systimer_unit0_op_reg_t; + +/** Type of unit0_load_hi register + * High 20 bits to be loaded to UNIT0 + */ +typedef union { + struct { + /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0; + * Configures the value to be loaded to UNIT0, high 20 bits. + */ + uint32_t timer_unit0_load_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit0_load_hi_reg_t; + +/** Type of unit0_load_lo register + * Low 32 bits to be loaded to UNIT0 + */ +typedef union { + struct { + /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0; + * Configures the value to be loaded to UNIT0, low 32 bits. + */ + uint32_t timer_unit0_load_lo:32; + }; + uint32_t val; +} systimer_unit0_load_lo_reg_t; + +/** Type of unit0_value_hi register + * UNIT0 value, high 20 bits + */ +typedef union { + struct { + /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0; + * Represents UNIT0 read value, high 20 bits. + */ + uint32_t timer_unit0_value_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit0_value_hi_reg_t; + +/** Type of unit0_value_lo register + * UNIT0 value, low 32 bits + */ +typedef union { + struct { + /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0; + * Represents UNIT0 read value, low 32 bits. + */ + uint32_t timer_unit0_value_lo:32; + }; + uint32_t val; +} systimer_unit0_value_lo_reg_t; + +/** Type of unit0_load register + * UNIT0 synchronization register + */ +typedef union { + struct { + /** timer_unit0_load : WT; bitpos: [0]; default: 0; + * Configures whether or not to reload the value of UNIT0, i.e., reloads the values of + * SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0. \\ + * 0: No effect \\ + * 1: Reload the value of UNIT0\\ + */ + uint32_t timer_unit0_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_unit0_load_reg_t; + + +/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit1_op register + * Read UNIT1 value to registers + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * Represents UNIT1 value is synchronized and valid. + */ + uint32_t timer_unit1_value_valid:1; + /** timer_unit1_update : WT; bitpos: [30]; default: 0; + * Configures whether or not to update timer UNIT1, i.e., reads the UNIT1 count value + * to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO. \\ + * 0: No effect \\ + * 1: Update timer UNIT1\\ + */ + uint32_t timer_unit1_update:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} systimer_unit1_op_reg_t; + +/** Type of unit1_load_hi register + * High 20 bits to be loaded to UNIT1 + */ +typedef union { + struct { + /** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0; + * Configures the value to be loaded to UNIT1, high 20 bits. + */ + uint32_t timer_unit1_load_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit1_load_hi_reg_t; + +/** Type of unit1_load_lo register + * Low 32 bits to be loaded to UNIT1 + */ +typedef union { + struct { + /** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0; + * Configures the value to be loaded to UNIT1, low 32 bits. + */ + uint32_t timer_unit1_load_lo:32; + }; + uint32_t val; +} systimer_unit1_load_lo_reg_t; + +/** Type of unit1_value_hi register + * UNIT1 value, high 20 bits + */ +typedef union { + struct { + /** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0; + * Represents UNIT1 read value, high 20 bits. + */ + uint32_t timer_unit1_value_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit1_value_hi_reg_t; + +/** Type of unit1_value_lo register + * UNIT1 value, low 32 bits + */ +typedef union { + struct { + /** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0; + * Represents UNIT1 read value, low 32 bits. + */ + uint32_t timer_unit1_value_lo:32; + }; + uint32_t val; +} systimer_unit1_value_lo_reg_t; + +/** Type of unit1_load register + * UNIT1 synchronization register + */ +typedef union { + struct { + /** timer_unit1_load : WT; bitpos: [0]; default: 0; + * Configures whether or not to reload the value of UNIT1, i.e., reload the values of + * SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1. \\ + * 0: No effect \\ + * 1: Reload the value of UNIT1\\ + */ + uint32_t timer_unit1_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_unit1_load_reg_t; + + +/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target0_hi register + * Alarm value to be loaded to COMP0, high 20 bits + */ +typedef union { + struct { + /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0; + * Configures the alarm value to be loaded to COMP0, high 20 bits. + */ + uint32_t timer_target0_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target0_hi_reg_t; + +/** Type of target0_lo register + * Alarm value to be loaded to COMP0, low 32 bits + */ +typedef union { + struct { + /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0; + * Configures the alarm value to be loaded to COMP0, low 32 bits. + */ + uint32_t timer_target0_lo:32; + }; + uint32_t val; +} systimer_target0_lo_reg_t; + +/** Type of target0_conf register + * Configure COMP0 alarm mode + */ +typedef union { + struct { + /** target0_period : R/W; bitpos: [25:0]; default: 0; + * Configures COMP0 alarm period. + */ + uint32_t target0_period:26; + uint32_t reserved_26:4; + /** target0_period_mode : R/W; bitpos: [30]; default: 0; + * Selects the two alarm modes for COMP0. \\ + * 0: Target mode\\ + * 1: Period mode\\ + */ + uint32_t target0_period_mode:1; + /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * Chooses the counter value for comparison with COMP0.\\ + * 0: Use the count value from UNIT$0\\ + * 1: Use the count value from UNIT$1\\ + */ + uint32_t target0_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target0_conf_reg_t; + +/** Type of comp0_load register + * COMP0 synchronization register + */ +typedef union { + struct { + /** timer_comp0_load : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm + * value/period to COMP0.\\ + * 0: No effect \\ + * 1: Enable COMP0 synchronization\\ + */ + uint32_t timer_comp0_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp0_load_reg_t; + + +/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target1_hi register + * Alarm value to be loaded to COMP1, high 20 bits + */ +typedef union { + struct { + /** timer_target1_hi : R/W; bitpos: [19:0]; default: 0; + * Configures the alarm value to be loaded to COMP1, high 20 bits. + */ + uint32_t timer_target1_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target1_hi_reg_t; + +/** Type of target1_lo register + * Alarm value to be loaded to COMP1, low 32 bits + */ +typedef union { + struct { + /** timer_target1_lo : R/W; bitpos: [31:0]; default: 0; + * Configures the alarm value to be loaded to COMP1, low 32 bits. + */ + uint32_t timer_target1_lo:32; + }; + uint32_t val; +} systimer_target1_lo_reg_t; + +/** Type of target1_conf register + * Configure COMP1 alarm mode + */ +typedef union { + struct { + /** target1_period : R/W; bitpos: [25:0]; default: 0; + * Configures COMP1 alarm period. + */ + uint32_t target1_period:26; + uint32_t reserved_26:4; + /** target1_period_mode : R/W; bitpos: [30]; default: 0; + * Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE. + */ + uint32_t target1_period_mode:1; + /** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * Chooses the counter value for comparison with COMP1. See details in + * SYSTIMER_TARGET0_TIMER_UNIT_SEL. + */ + uint32_t target1_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target1_conf_reg_t; + +/** Type of comp1_load register + * COMP1 synchronization register + */ +typedef union { + struct { + /** timer_comp1_load : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable COMP1 synchronization, i.e., reload the alarm + * value/period to COMP1. \\ + * 0: No effect \\ + * 1: Enable COMP1 synchronization\\ + */ + uint32_t timer_comp1_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp1_load_reg_t; + + +/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target2_hi register + * Alarm value to be loaded to COMP2, high 20 bits + */ +typedef union { + struct { + /** timer_target2_hi : R/W; bitpos: [19:0]; default: 0; + * Configures the alarm value to be loaded to COMP2, high 20 bits. + */ + uint32_t timer_target2_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target2_hi_reg_t; + +/** Type of target2_lo register + * Alarm value to be loaded to COMP2, low 32 bits + */ +typedef union { + struct { + /** timer_target2_lo : R/W; bitpos: [31:0]; default: 0; + * Configures the alarm value to be loaded to COMP2, low 32 bits. + */ + uint32_t timer_target2_lo:32; + }; + uint32_t val; +} systimer_target2_lo_reg_t; + +/** Type of target2_conf register + * Configure COMP2 alarm mode + */ +typedef union { + struct { + /** target2_period : R/W; bitpos: [25:0]; default: 0; + * Configures COMP2 alarm period. + */ + uint32_t target2_period:26; + uint32_t reserved_26:4; + /** target2_period_mode : R/W; bitpos: [30]; default: 0; + * Configures Configures the two alarm modes for COMP2. See details in + * SYSTIMER_TARGET0_PERIOD_MODE. + */ + uint32_t target2_period_mode:1; + /** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * Chooses the counter value for comparison with COMP2. See details in + * SYSTIMER_TARGET0_TIMER_UNIT_SEL. + */ + uint32_t target2_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target2_conf_reg_t; + +/** Type of comp2_load register + * COMP2 synchronization register + */ +typedef union { + struct { + /** timer_comp2_load : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable COMP2 synchronization, i.e., reload the alarm + * value/period to COMP2.\\ + * 0: No effect \\ + * 1: Enable COMP2 synchronization\\ + */ + uint32_t timer_comp2_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp2_load_reg_t; + + +/** Group: SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * Interrupt enable register of system timer + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable SYSTIMER_TARGET0_INT. + */ + uint32_t target0_int_ena:1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable SYSTIMER_TARGET1_INT. + */ + uint32_t target1_int_ena:1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable SYSTIMER_TARGET2_INT. + */ + uint32_t target2_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * Interrupt raw register of system timer + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of SYSTIMER_TARGET0_INT. + */ + uint32_t target0_int_raw:1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of SYSTIMER_TARGET1_INT. + */ + uint32_t target1_int_raw:1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of SYSTIMER_TARGET2_INT. + */ + uint32_t target2_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear register of system timer + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear SYSTIMER_TARGET0_INT. + */ + uint32_t target0_int_clr:1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear SYSTIMER_TARGET1_INT. + */ + uint32_t target1_int_clr:1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear SYSTIMER_TARGET2_INT. + */ + uint32_t target2_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * Interrupt status register of system timer + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * The interrupt status of SYSTIMER_TARGET0_INT. + */ + uint32_t target0_int_st:1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * The interrupt status of SYSTIMER_TARGET1_INT. + */ + uint32_t target1_int_st:1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * The interrupt status of SYSTIMER_TARGET2_INT. + */ + uint32_t target2_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */ +/** Type of real_target0_lo register + * Actual target value of COMP0, low 32 bits + */ +typedef union { + struct { + /** target0_lo_ro : RO; bitpos: [31:0]; default: 0; + * Represents the actual target value of COMP0, low 32 bits. + */ + uint32_t target0_lo_ro:32; + }; + uint32_t val; +} systimer_real_target0_lo_reg_t; + +/** Type of real_target0_hi register + * Actual target value of COMP0, high 20 bits + */ +typedef union { + struct { + /** target0_hi_ro : RO; bitpos: [19:0]; default: 0; + * Represents the actual target value of COMP0, high 20 bits. + */ + uint32_t target0_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target0_hi_reg_t; + + +/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */ +/** Type of real_target1_lo register + * Actual target value of COMP1, low 32 bits + */ +typedef union { + struct { + /** target1_lo_ro : RO; bitpos: [31:0]; default: 0; + * Represents the actual target value of COMP1, low 32 bits. + */ + uint32_t target1_lo_ro:32; + }; + uint32_t val; +} systimer_real_target1_lo_reg_t; + +/** Type of real_target1_hi register + * Actual target value of COMP1, high 20 bits + */ +typedef union { + struct { + /** target1_hi_ro : RO; bitpos: [19:0]; default: 0; + * Represents the actual target value of COMP1, high 20 bits. + */ + uint32_t target1_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target1_hi_reg_t; + + +/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */ +/** Type of real_target2_lo register + * Actual target value of COMP2, low 32 bits + */ +typedef union { + struct { + /** target2_lo_ro : RO; bitpos: [31:0]; default: 0; + * Represents the actual target value of COMP2, low 32 bits. + */ + uint32_t target2_lo_ro:32; + }; + uint32_t val; +} systimer_real_target2_lo_reg_t; + +/** Type of real_target2_hi register + * Actual target value of COMP2, high 20 bits + */ +typedef union { + struct { + /** target2_hi_ro : RO; bitpos: [19:0]; default: 0; + * Represents the actual target value of COMP2, high 20 bits. + */ + uint32_t target2_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target2_hi_reg_t; + + +/** Group: VERSION REGISTER */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36774432; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit0_op_reg_t unit0_op; + volatile systimer_unit1_op_reg_t unit1_op; + volatile systimer_unit0_load_hi_reg_t unit0_load_hi; + volatile systimer_unit0_load_lo_reg_t unit0_load_lo; + volatile systimer_unit1_load_hi_reg_t unit1_load_hi; + volatile systimer_unit1_load_lo_reg_t unit1_load_lo; + volatile systimer_target0_hi_reg_t target0_hi; + volatile systimer_target0_lo_reg_t target0_lo; + volatile systimer_target1_hi_reg_t target1_hi; + volatile systimer_target1_lo_reg_t target1_lo; + volatile systimer_target2_hi_reg_t target2_hi; + volatile systimer_target2_lo_reg_t target2_lo; + volatile systimer_target0_conf_reg_t target0_conf; + volatile systimer_target1_conf_reg_t target1_conf; + volatile systimer_target2_conf_reg_t target2_conf; + volatile systimer_unit0_value_hi_reg_t unit0_value_hi; + volatile systimer_unit0_value_lo_reg_t unit0_value_lo; + volatile systimer_unit1_value_hi_reg_t unit1_value_hi; + volatile systimer_unit1_value_lo_reg_t unit1_value_lo; + volatile systimer_comp0_load_reg_t comp0_load; + volatile systimer_comp1_load_reg_t comp1_load; + volatile systimer_comp2_load_reg_t comp2_load; + volatile systimer_unit0_load_reg_t unit0_load; + volatile systimer_unit1_load_reg_t unit1_load; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target0_lo_reg_t real_target0_lo; + volatile systimer_real_target0_hi_reg_t real_target0_hi; + volatile systimer_real_target1_lo_reg_t real_target1_lo; + volatile systimer_real_target1_hi_reg_t real_target1_hi; + volatile systimer_real_target2_lo_reg_t real_target2_lo; + volatile systimer_real_target2_hi_reg_t real_target2_hi; + uint32_t reserved_08c[28]; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/timer_group_reg.h b/components/soc/esp32c61/include/soc/timer_group_reg.h new file mode 100644 index 0000000000..761db43060 --- /dev/null +++ b/components/soc/esp32c61/include/soc/timer_group_reg.h @@ -0,0 +1,753 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0) +/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) +#define TIMG_T0_USE_XTAL_V 0x00000001U +#define TIMG_T0_USE_XTAL_S 9 +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_T1CONFIG_REG register + * Timer 1 configuration register + */ +#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24) +/** TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ +#define TIMG_T1_USE_XTAL (BIT(9)) +#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S) +#define TIMG_T1_USE_XTAL_V 0x00000001U +#define TIMG_T1_USE_XTAL_S 9 +/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) +#define TIMG_T1_ALARM_EN_V 0x00000001U +#define TIMG_T1_ALARM_EN_S 10 +/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 1 's clock divider counter will be reset. + */ +#define TIMG_T1_DIVCNT_RST (BIT(12)) +#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S) +#define TIMG_T1_DIVCNT_RST_V 0x00000001U +#define TIMG_T1_DIVCNT_RST_S 12 +/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 1 clock (T1_clk) prescaler value. + */ +#define TIMG_T1_DIVIDER 0x0000FFFFU +#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) +#define TIMG_T1_DIVIDER_V 0x0000FFFFU +#define TIMG_T1_DIVIDER_S 13 +/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 1 auto-reload at alarm is enabled. + */ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) +#define TIMG_T1_AUTORELOAD_V 0x00000001U +#define TIMG_T1_AUTORELOAD_S 29 +/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 1 time-base counter will increment every clock tick. When + * cleared, the timer 1 time-base counter will decrement. + */ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) +#define TIMG_T1_INCREASE_V 0x00000001U +#define TIMG_T1_INCREASE_S 30 +/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 1 time-base counter is enabled. + */ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) +#define TIMG_T1_EN_V 0x00000001U +#define TIMG_T1_EN_S 31 + +/** TIMG_T1LO_REG register + * Timer 1 current value, low 32 bits + */ +#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28) +/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter + * of timer 1 can be read here. + */ +#define TIMG_T1_LO 0xFFFFFFFFU +#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) +#define TIMG_T1_LO_V 0xFFFFFFFFU +#define TIMG_T1_LO_S 0 + +/** TIMG_T1HI_REG register + * Timer 1 current value, high 22 bits + */ +#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c) +/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter + * of timer 1 can be read here. + */ +#define TIMG_T1_HI 0x003FFFFFU +#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) +#define TIMG_T1_HI_V 0x003FFFFFU +#define TIMG_T1_HI_S 0 + +/** TIMG_T1UPDATE_REG register + * Write to copy current timer value to TIMGn_T1_(LO/HI)_REG + */ +#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30) +/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched. + */ +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) +#define TIMG_T1_UPDATE_V 0x00000001U +#define TIMG_T1_UPDATE_S 31 + +/** TIMG_T1ALARMLO_REG register + * Timer 1 alarm value, low 32 bits + */ +#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34) +/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T1_ALARM_LO 0xFFFFFFFFU +#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T1_ALARM_LO_S 0 + +/** TIMG_T1ALARMHI_REG register + * Timer 1 alarm value, high bits + */ +#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38) +/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T1_ALARM_HI 0x003FFFFFU +#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) +#define TIMG_T1_ALARM_HI_V 0x003FFFFFU +#define TIMG_T1_ALARM_HI_S 0 + +/** TIMG_T1LOADLO_REG register + * Timer 1 reload value, low 32 bits + */ +#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c) +/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 1 time-base + * Counter. + */ +#define TIMG_T1_LOAD_LO 0xFFFFFFFFU +#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T1_LOAD_LO_S 0 + +/** TIMG_T1LOADHI_REG register + * Timer 1 reload value, high 22 bits + */ +#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40) +/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 1 time-base + * counter. + */ +#define TIMG_T1_LOAD_HI 0x003FFFFFU +#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) +#define TIMG_T1_LOAD_HI_V 0x003FFFFFU +#define TIMG_T1_LOAD_HI_S 0 + +/** TIMG_T1LOAD_REG register + * Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG + */ +#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44) +/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 1 time-base counter reload. + */ +#define TIMG_T1_LOAD 0xFFFFFFFFU +#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) +#define TIMG_T1_LOAD_V 0xFFFFFFFFU +#define TIMG_T1_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0; + * choose WDT clock:0-apb_clk, 1-xtal_clk. + */ +#define TIMG_WDT_USE_XTAL (BIT(21)) +#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S) +#define TIMG_WDT_USE_XTAL_V 0x00000001U +#define TIMG_WDT_USE_XTAL_S 21 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) +#define TIMG_T1_INT_ENA_V 0x00000001U +#define TIMG_T1_INT_ENA_S 1 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 2 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) +#define TIMG_T1_INT_RAW_V 0x00000001U +#define TIMG_T1_INT_RAW_S 1 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 2 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) +#define TIMG_T1_INT_ST_V 0x00000001U +#define TIMG_T1_INT_ST_S 1 +/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 2 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) +#define TIMG_T1_INT_CLR_V 0x00000001U +#define TIMG_T1_INT_CLR_S 1 +/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 2 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1; + * enable WDT's clock + */ +#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S) +#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U +#define TIMG_WDT_CLK_IS_ACTIVE_S 29 +/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1; + * enable Timer $x's clock + */ +#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S) +#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U +#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/timer_group_struct.h b/components/soc/esp32c61/include/soc/timer_group_struct.h new file mode 100644 index 0000000000..d3edcc9e0e --- /dev/null +++ b/components/soc/esp32c61/include/soc/timer_group_struct.h @@ -0,0 +1,740 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_use_xtal : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ + uint32_t tx_use_xtal:1; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + + +/** Group: T1 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_use_xtal : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ + uint32_t tx_use_xtal:1; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_use_xtal : R/W; bitpos: [21]; default: 0; + * choose WDT clock:0-apb_clk, 1-xtal_clk. + */ + uint32_t wdt_use_xtal:1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en:1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3:2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2:2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1:2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0:2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale:16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed:32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling:1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel:2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy:1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max:15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start:1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value:25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena:1; + /** t1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_ena:1; + /** wdt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw:1; + /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_raw:1; + /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st:1; + /** t1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_st:1; + /** wdt_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr:1; + /** t1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_clr:1; + /** wdt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en:1; + /** wdt_clk_is_active : R/W; bitpos: [29]; default: 1; + * enable WDT's clock + */ + uint32_t wdt_clk_is_active:1; + /** timer_clk_is_active : R/W; bitpos: [30]; default: 1; + * enable Timer $x's clock + */ + uint32_t timer_clk_is_active:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} timg_regclk_reg_t; + + +typedef struct { + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; + + +typedef struct { + volatile timg_hwtimer_reg_t hw_timer[2]; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/uart_reg.h b/components/soc/esp32c61/include/soc/uart_reg.h new file mode 100644 index 0000000000..73577ca963 --- /dev/null +++ b/components/soc/esp32c61/include/soc/uart_reg.h @@ -0,0 +1,1657 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UART_FIFO_REG register + * FIFO data register + */ +#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * Represents the data UART $n read from FIFO.\\ + * Measurement unit: byte. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG register + * Raw interrupt status + */ +#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of UART_RXFIFO_FULL_INT. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * The raw interrupt status of UART_TXFIFO_EMPTY_INT. + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of UART_PARITY_ERR_INT. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of UART_FRM_ERR_INT. + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of UART_RXFIFO_OVF_INT. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of UART_DSR_CHG_INT. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of UART_CTS_CHG_INT. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of UART_BRK_DET_INT. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt status of UART_RXFIFO_TOUT_INT. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt status of UART_SW_XON_INT. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * UART_SW_XOFF_INT. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt status of UART_GLITCH_DET_INT. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt status of UART_TX_BRK_DONE_INT. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt status of UART_TX_DONE_INT. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt status of UART_RS485_PARITY_ERR_INT. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt status of UART_RS485_FRM_ERR_INT. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt status of UART_RS485_CLASH_INT. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt status of UART_AT_CMD_CHAR_DET_INT. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt status of UART_WAKEUP_INT. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG register + * Masked interrupt status + */ +#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of UART_RXFIFO_FULL_INT. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of UART_TXFIFO_EMPTY_INT. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of UART_PARITY_ERR_INT. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status of UART_FRM_ERR_INT. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status of UART_RXFIFO_OVF_INT. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status of UART_DSR_CHG_INT. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of UART_CTS_CHG_INT. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of UART_BRK_DET_INT. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status of UART_RXFIFO_TOUT_INT. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status of UART_SW_XON_INT. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status of UART_SW_XOFF_INT. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status of UART_GLITCH_DET_INT. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status of UART_TX_BRK_DONE_INT. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status of UART_TX_DONE_INT. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status of UART_RS485_PARITY_ERR_INT. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status of UART_RS485_FRM_ERR_INT. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status of UART_RS485_CLASH_INT. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status of UART_AT_CMD_CHAR_DET_INT. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status of UART_WAKEUP_INT. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable UART_RXFIFO_FULL_INT. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable UART_TXFIFO_EMPTY_INT. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable UART_PARITY_ERR_INT. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable UART_FRM_ERR_INT. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable UART_RXFIFO_OVF_INT. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable UART_DSR_CHG_INT. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable UART_CTS_CHG_INT. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable UART_BRK_DET_INT. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to enable UART_RXFIFO_TOUT_INT. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to enable UART_SW_XON_INT. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to enable UART_SW_XOFF_INT. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to enable UART_GLITCH_DET_INT. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to enable UART_TX_BRK_DONE_INT. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to enable UART_TX_BRK_IDLE_DONE_INT. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to enable UART_TX_DONE_INT. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * Write 1 to enable UART_RS485_PARITY_ERR_INT. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * Write 1 to enable UART_RS485_FRM_ERR_INT. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * Write 1 to enable UART_RS485_CLASH_INT. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * Write 1 to enable UART_AT_CMD_CHAR_DET_INT. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * Write 1 to enable UART_WAKEUP_INT. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear UART_RXFIFO_FULL_INT. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear UART_TXFIFO_EMPTY_INT. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear UART_PARITY_ERR_INT. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear UART_FRM_ERR_INT. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear UART_RXFIFO_OVF_INT. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear UART_DSR_CHG_INT. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear UART_CTS_CHG_INT. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear UART_BRK_DET_INT. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear UART_RXFIFO_TOUT_INT. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear UART_SW_XON_INT. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear UART_SW_XOFF_INT. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear UART_GLITCH_DET_INT. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear UART_TX_BRK_DONE_INT. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear UART_TX_BRK_IDLE_DONE_INT. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear UART_TX_DONE_INT. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Write 1 to clear UART_RS485_PARITY_ERR_INT. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Write 1 to clear UART_RS485_FRM_ERR_INT. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Write 1 to clear UART_RS485_CLASH_INT. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Write 1 to clear UART_AT_CMD_CHAR_DET_INT. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Write 1 to clear UART_WAKEUP_INT. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * Configures the integral part of the divisor for baud rate generation. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * Configures the fractional part of the divisor for baud rate generation. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG register + * RX filter configuration + */ +#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's + * clock cycle.\\Pulses whose width is lower than this value will be ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable RX signal filter.\\ + * 0: Disable\\ + * 1: Enable + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG register + * UART status register + */ +#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Represents the number of valid data bytes in RX FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * Represents the level of the internal UART DSR signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * Represents the level of the internal UART CTS signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * Represents the level of the internal UART RXD signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Represents the number of valid data bytes in RX FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * Represents the level of the internal UART DTR signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * Represents the level of the internal UART RTS signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * Represents the level of the internal UART TXD signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG register + * Configuration register 0 + */ +#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * Configures the parity check mode.\\ + * 0: Even parity\\ + * 1: Odd parity\\ + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable UART parity check.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * Configures the number of data bits.\\ + * 0: 5 bits\\ + * 1: 6 bits\\ + * 2: 7 bits\\ + * 3: 8 bits\\ + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * Configures the number of stop bits.\\ + * 0: Invalid. No effect\\ + * 1: 1 bits\\ + * 2: 1.5 bits\\ + * 3: 2 bits\\ + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Configures whether or not to send NULL characters when finishing data + * transmission.\\ + * 0: Not send\\ + * 1: Send\\ + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable IrDA loopback test.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the IrDA transmitter.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * Configures the 11th bit of the IrDA transmitter.\\ + * 0: This bit is 0.\\ + * 1: This bit is the same as the 10th bit.\\ + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert the level of the IrDA transmitter.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the level of the IrDA receiver.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable UART loopback test.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable flow control for the transmitter.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable IrDA protocol.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Configures whether or not to invert the level of UART RXD signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Configures whether or not to invert the level of UART TXD signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Configures whether or not to disable data overflow detection for the UART + * receiver.\\ + * 0: Enable\\ + * 1: Disable\\ + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * Configures whether or not to store the received data with errors into FIFO.\\ + * 0: Store\\ + * 1: Not store\\ + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable baud rate detection.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable clock gating for UART memory.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * Configures the RTS signal used in software flow control.\\ + * 0: The UART transmitter is allowed to send data.\\ + * 1: The UART transmitted is not allowed to send data.\\ + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Configures whether or not to reset the UART RX FIFO.\\ + * 0: Not reset\\ + * 1: Reset\\ + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Configures whether or not to reset the UART TX FIFO.\\ + * 0: Not reset\\ + * 1: Reset\\ + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG register + * Configuration register 1 + */ +#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * Configures the threshold for RX FIFO being full.\\Measurement unit: byte. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * Configures the threshold for TX FIFO being empty.\\Measurement unit: byte. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Configures whether or not to invert the level of UART CTS signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Configures whether or not to invert the level of UART DSR signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Configures whether or not to invert the level of UART RTS signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Configures whether or not to invert the level of UART DTR signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * Configures the DTR signal used in software flow control.\\ + * 0: Data to be transmitted is not ready.\\ + * 1: Data to be transmitted is ready.\\ + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * Configures clock gating.\\ + * 0: Support clock only when the application writes registers.\\ + * 1: Always force the clock on for registers.\\ + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG register + * Hardware flow control configuration + */ +#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * Configures the maximum number of data bytes that can be received during hardware + * flow control.\\Measurement unit: byte. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the UART receiver.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG register + * UART sleep configuration register 0 + */ +#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * Configures wakeup character 1. + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * Configures wakeup character 2. + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * Configures wakeup character 3. + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * Configures wakeup character 4. + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG register + * UART sleep configuration register 1 + */ +#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * Configures wakeup character 0. + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG register + * UART sleep configuration register 2 + */ +#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * Configures the number of RXD edge changes to wake up the chip in wakeup mode 0. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * Configures the number of received data bytes to wake up the chip in wakeup mode 1. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * Configures the number of wakeup characters. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * Configures whether or not to mask wakeup characters.\\ + * 0: Not mask\\ + * 1: Mask\\ + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * Configures which wakeup mode to select.\\ + * 0: Mode 0\\ + * 1: Mode 1\\ + * 2: Mode 2\\ + * 3: Mode 3\\ + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG register + * Software flow control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * Configures the XON character for flow control. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * Configures the XOFF character for flow control. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * Configures whether the UART transmitter can send XON or XOFF characters when it is + * disabled.\\ + * 0: Cannot send\\ + * 1: Can send\\ + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable software flow control.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Configures whether or not to remove flow control characters from the received + * data.\\ + * 0: Not move\\ + * 1: Move\\ + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Configures whether the transmitter continues to sending data.\\ + * 0: Not send\\ + * 1: Send\\ + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Configures whether or not to stop the transmitter from sending data.\\ + * 0: Not stop\\ + * 1: Stop\\ + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Configures whether or not to send XON characters.\\ + * 0: Not send\\ + * 1: Send\\ + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Configures whether or not to send XOFF characters.\\ + * 0: Not send\\ + * 1: Send\\ + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG register + * Software flow control character configuration + */ +#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * Configures the threshold for data in RX FIFO to send XON characters in software + * flow control.\\Measurement unit: byte. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * Configures the threshold for data in RX FIFO to send XOFF characters in software + * flow control.\\Measurement unit: byte. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG register + * TX break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * Configures the number of NULL characters to be sent after finishing data + * transmission.\\Valid only when UART_TXD_BRK is 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG register + * Frame end idle time configuration + */ +#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * Configures the threshold to generate a frame end signal when the receiver takes + * more time to receive one data byte data.\\Measurement unit: bit time (the time to + * transmit 1 bit). + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * Configures the interval between two data transfers.\\Measurement unit: bit time + * (the time to transmit 1 bit). + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable RS485 mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\ + * 0: Not add\\ + * 1: Add\\ + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\ + * 0: Not add\\ + * 1: Add\\ + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the receiver for data reception when the + * transmitter is transmitting data in RS485 mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * Configures whether to enable the RS485 transmitter for data transmission when the + * RS485 receiver is busy.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * Configures the delay of internal data signals in the receiver.\\Measurement unit: + * bit time (the time to transmit 1 bit).. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * Configures the delay of internal data signals in the transmitter.\\Measurement + * unit: bit time (the time to transmit 1 bit). + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * Configures the idle time before the receiver receives the first + * AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit). + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * Configures the interval between the last AT_CMD and subsequent data.\\Measurement + * unit: bit time (the time to transmit 1 bit). + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * Configures the interval between two AT_CMD characters.\\Measurement unit: bit time + * (the time to transmit 1 bit). + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * Configures the AT_CMD character. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * Configures the number of continuous AT_CMD characters a receiver can receive. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable UART receiver's timeout function.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * Configures the amount of time that the bus can remain idle before timeout.\\ + * Measurement unit: bit time (the time to transmit 1 bit). + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG register + * TX FIFO write and read offset address + */ +#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * Represents the offset address to write TX FIFO. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * Represents the offset address to read TX FIFO. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG register + * Rx FIFO write and read offset address + */ +#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * Represents the offset address to read RX FIFO. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * Represents the offset address to write RX FIFO. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG register + * UART transmit and receive status + */ +#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * Represents the status of the receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * Represents the status of the transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * Represents the minimal input clock counter value between two positive edges. It is + * used for baud rate detection. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * Represents the minimal input clock counter value between two negative edges. It is + * used for baud rate detection. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * Represents the minimum duration time of a low-level pulse. It is used for baud rate + * detection.\\Measurement unit: APB_CLK clock cycle. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * Represents the maximum duration time for a high-level pulse. It is used for baud + * rate detection.\\Measurement unit: APB_CLK clock cycle. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * Represents the number of RXD edge changes. It is used for baud rate detection. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Configures whether or not to enable UART TX clock.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Configures whether or not to enable UART RX clock.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 and then write 0 to reset UART TX. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 and then write 0 to reset UART RX. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG register + * UART version control register + */ +#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 36774432; + * Version control register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG register + * UART asynchronous FIFO status + */ +#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Represents whether or not the APB TX asynchronous FIFO is full.\\ + * 0: Not full\\ + * 1: Full\\ + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Represents whether or not the APB TX asynchronous FIFO is empty.\\ + * 0: Not empty\\ + * 1: Empty\\ + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Represents whether or not the APB RX asynchronous FIFO is full.\\ + * 0: Not full\\ + * 1: Full\\ + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Represents whether or not the APB RX asynchronous FIFO is empty.\\ + * 0: Not empty\\ + * 1: Empty\\ + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG register + * UART register configuration update + */ +#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Configures whether or not to synchronize registers.\\ + * 0: Not synchronize\\ + * 1: Synchronize\\ + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG register + * UART ID register + */ +#define UART_ID_REG (DR_REG_UART_BASE + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * Configures the UART ID. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/uart_struct.h b/components/soc/esp32c61/include/soc/uart_struct.h new file mode 100644 index 0000000000..24f1dd55eb --- /dev/null +++ b/components/soc/esp32c61/include/soc/uart_struct.h @@ -0,0 +1,1350 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * Represents the data UART $n read from FIFO.\\ + * Measurement unit: byte. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable UART receiver's timeout function.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * Configures the amount of time that the bus can remain idle before timeout.\\ + * Measurement unit: bit time (the time to transmit 1 bit). + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of UART_RXFIFO_FULL_INT. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * The raw interrupt status of UART_TXFIFO_EMPTY_INT. + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of UART_PARITY_ERR_INT. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status of UART_FRM_ERR_INT. + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status of UART_RXFIFO_OVF_INT. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status of UART_DSR_CHG_INT. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of UART_CTS_CHG_INT. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of UART_BRK_DET_INT. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt status of UART_RXFIFO_TOUT_INT. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt status of UART_SW_XON_INT. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * UART_SW_XOFF_INT. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt status of UART_GLITCH_DET_INT. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt status of UART_TX_BRK_DONE_INT. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt status of UART_TX_DONE_INT. + */ + uint32_t tx_done_int_raw:1; + /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt status of UART_RS485_PARITY_ERR_INT. + */ + uint32_t rs485_parity_err_int_raw:1; + /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt status of UART_RS485_FRM_ERR_INT. + */ + uint32_t rs485_frm_err_int_raw:1; + /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt status of UART_RS485_CLASH_INT. + */ + uint32_t rs485_clash_int_raw:1; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt status of UART_AT_CMD_CHAR_DET_INT. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt status of UART_WAKEUP_INT. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of UART_RXFIFO_FULL_INT. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of UART_TXFIFO_EMPTY_INT. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of UART_PARITY_ERR_INT. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status of UART_FRM_ERR_INT. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status of UART_RXFIFO_OVF_INT. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status of UART_DSR_CHG_INT. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of UART_CTS_CHG_INT. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status of UART_BRK_DET_INT. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status of UART_RXFIFO_TOUT_INT. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status of UART_SW_XON_INT. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status of UART_SW_XOFF_INT. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status of UART_GLITCH_DET_INT. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status of UART_TX_BRK_DONE_INT. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status of UART_TX_DONE_INT. + */ + uint32_t tx_done_int_st:1; + /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status of UART_RS485_PARITY_ERR_INT. + */ + uint32_t rs485_parity_err_int_st:1; + /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status of UART_RS485_FRM_ERR_INT. + */ + uint32_t rs485_frm_err_int_st:1; + /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status of UART_RS485_CLASH_INT. + */ + uint32_t rs485_clash_int_st:1; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status of UART_AT_CMD_CHAR_DET_INT. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status of UART_WAKEUP_INT. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable UART_RXFIFO_FULL_INT. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable UART_TXFIFO_EMPTY_INT. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable UART_PARITY_ERR_INT. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable UART_FRM_ERR_INT. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable UART_RXFIFO_OVF_INT. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable UART_DSR_CHG_INT. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable UART_CTS_CHG_INT. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable UART_BRK_DET_INT. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to enable UART_RXFIFO_TOUT_INT. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to enable UART_SW_XON_INT. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to enable UART_SW_XOFF_INT. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to enable UART_GLITCH_DET_INT. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to enable UART_TX_BRK_DONE_INT. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to enable UART_TX_BRK_IDLE_DONE_INT. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to enable UART_TX_DONE_INT. + */ + uint32_t tx_done_int_ena:1; + /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; + * Write 1 to enable UART_RS485_PARITY_ERR_INT. + */ + uint32_t rs485_parity_err_int_ena:1; + /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; + * Write 1 to enable UART_RS485_FRM_ERR_INT. + */ + uint32_t rs485_frm_err_int_ena:1; + /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; + * Write 1 to enable UART_RS485_CLASH_INT. + */ + uint32_t rs485_clash_int_ena:1; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * Write 1 to enable UART_AT_CMD_CHAR_DET_INT. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * Write 1 to enable UART_WAKEUP_INT. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear UART_RXFIFO_FULL_INT. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear UART_TXFIFO_EMPTY_INT. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear UART_PARITY_ERR_INT. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear UART_FRM_ERR_INT. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear UART_RXFIFO_OVF_INT. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear UART_DSR_CHG_INT. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear UART_CTS_CHG_INT. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear UART_BRK_DET_INT. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear UART_RXFIFO_TOUT_INT. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear UART_SW_XON_INT. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear UART_SW_XOFF_INT. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear UART_GLITCH_DET_INT. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear UART_TX_BRK_DONE_INT. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear UART_TX_BRK_IDLE_DONE_INT. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear UART_TX_DONE_INT. + */ + uint32_t tx_done_int_clr:1; + /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; + * Write 1 to clear UART_RS485_PARITY_ERR_INT. + */ + uint32_t rs485_parity_err_int_clr:1; + /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; + * Write 1 to clear UART_RS485_FRM_ERR_INT. + */ + uint32_t rs485_frm_err_int_clr:1; + /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; + * Write 1 to clear UART_RS485_CLASH_INT. + */ + uint32_t rs485_clash_int_clr:1; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Write 1 to clear UART_AT_CMD_CHAR_DET_INT. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Write 1 to clear UART_WAKEUP_INT. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * Configures the integral part of the divisor for baud rate generation. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * Configures the fractional part of the divisor for baud rate generation. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * RX filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's + * clock cycle.\\Pulses whose width is lower than this value will be ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable RX signal filter.\\ + * 0: Disable\\ + * 1: Enable + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * Configuration register 0 + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * Configures the parity check mode.\\ + * 0: Even parity\\ + * 1: Odd parity\\ + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable UART parity check.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * Configures the number of data bits.\\ + * 0: 5 bits\\ + * 1: 6 bits\\ + * 2: 7 bits\\ + * 3: 8 bits\\ + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * Configures the number of stop bits.\\ + * 0: Invalid. No effect\\ + * 1: 1 bits\\ + * 2: 1.5 bits\\ + * 3: 2 bits\\ + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Configures whether or not to send NULL characters when finishing data + * transmission.\\ + * 0: Not send\\ + * 1: Send\\ + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable IrDA loopback test.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the IrDA transmitter.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * Configures the 11th bit of the IrDA transmitter.\\ + * 0: This bit is 0.\\ + * 1: This bit is the same as the 10th bit.\\ + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert the level of the IrDA transmitter.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the level of the IrDA receiver.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable UART loopback test.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable flow control for the transmitter.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable IrDA protocol.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Configures whether or not to invert the level of UART RXD signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Configures whether or not to invert the level of UART TXD signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Configures whether or not to disable data overflow detection for the UART + * receiver.\\ + * 0: Enable\\ + * 1: Disable\\ + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * Configures whether or not to store the received data with errors into FIFO.\\ + * 0: Store\\ + * 1: Not store\\ + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable baud rate detection.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable clock gating for UART memory.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * Configures the RTS signal used in software flow control.\\ + * 0: The UART transmitter is allowed to send data.\\ + * 1: The UART transmitted is not allowed to send data.\\ + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Configures whether or not to reset the UART RX FIFO.\\ + * 0: Not reset\\ + * 1: Reset\\ + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Configures whether or not to reset the UART TX FIFO.\\ + * 0: Not reset\\ + * 1: Reset\\ + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * Configures the threshold for RX FIFO being full.\\Measurement unit: byte. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * Configures the threshold for TX FIFO being empty.\\Measurement unit: byte. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Configures whether or not to invert the level of UART CTS signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Configures whether or not to invert the level of UART DSR signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Configures whether or not to invert the level of UART RTS signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Configures whether or not to invert the level of UART DTR signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * Configures the DTR signal used in software flow control.\\ + * 0: Data to be transmitted is not ready.\\ + * 1: Data to be transmitted is ready.\\ + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * Configures clock gating.\\ + * 0: Support clock only when the application writes registers.\\ + * 1: Always force the clock on for registers.\\ + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * Configures the maximum number of data bytes that can be received during hardware + * flow control.\\Measurement unit: byte. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the UART receiver.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configuration register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * Configures wakeup character 1. + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * Configures wakeup character 2. + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * Configures wakeup character 3. + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * Configures wakeup character 4. + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configuration register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * Configures wakeup character 0. + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configuration register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * Configures the number of RXD edge changes to wake up the chip in wakeup mode 0. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * Configures the number of received data bytes to wake up the chip in wakeup mode 1. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * Configures the number of wakeup characters. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * Configures whether or not to mask wakeup characters.\\ + * 0: Not mask\\ + * 1: Mask\\ + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * Configures which wakeup mode to select.\\ + * 0: Mode 0\\ + * 1: Mode 1\\ + * 2: Mode 2\\ + * 3: Mode 3\\ + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * Configures the XON character for flow control. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * Configures the XOFF character for flow control. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * Configures whether the UART transmitter can send XON or XOFF characters when it is + * disabled.\\ + * 0: Cannot send\\ + * 1: Can send\\ + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable software flow control.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Configures whether or not to remove flow control characters from the received + * data.\\ + * 0: Not move\\ + * 1: Move\\ + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Configures whether the transmitter continues to sending data.\\ + * 0: Not send\\ + * 1: Send\\ + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Configures whether or not to stop the transmitter from sending data.\\ + * 0: Not stop\\ + * 1: Stop\\ + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Configures whether or not to send XON characters.\\ + * 0: Not send\\ + * 1: Send\\ + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Configures whether or not to send XOFF characters.\\ + * 0: Not send\\ + * 1: Send\\ + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * Configures the threshold for data in RX FIFO to send XON characters in software + * flow control.\\Measurement unit: byte. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * Configures the threshold for data in RX FIFO to send XOFF characters in software + * flow control.\\Measurement unit: byte. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * TX break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * Configures the number of NULL characters to be sent after finishing data + * transmission.\\Valid only when UART_TXD_BRK is 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame end idle time configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * Configures the threshold to generate a frame end signal when the receiver takes + * more time to receive one data byte data.\\Measurement unit: bit time (the time to + * transmit 1 bit). + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * Configures the interval between two data transfers.\\Measurement unit: bit time + * (the time to transmit 1 bit). + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable RS485 mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\ + * 0: Not add\\ + * 1: Add\\ + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\ + * 0: Not add\\ + * 1: Add\\ + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the receiver for data reception when the + * transmitter is transmitting data in RS485 mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * Configures whether to enable the RS485 transmitter for data transmission when the + * RS485 receiver is busy.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * Configures the delay of internal data signals in the receiver.\\Measurement unit: + * bit time (the time to transmit 1 bit).. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * Configures the delay of internal data signals in the transmitter.\\Measurement + * unit: bit time (the time to transmit 1 bit). + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Configures whether or not to enable UART TX clock.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Configures whether or not to enable UART RX clock.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 and then write 0 to reset UART TX. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 and then write 0 to reset UART RX. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Represents the number of valid data bytes in RX FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * Represents the level of the internal UART DSR signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * Represents the level of the internal UART CTS signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * Represents the level of the internal UART RXD signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Represents the number of valid data bytes in RX FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * Represents the level of the internal UART DTR signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * Represents the level of the internal UART RTS signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * Represents the level of the internal UART TXD signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * TX FIFO write and read offset address + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * Represents the offset address to write TX FIFO. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * Represents the offset address to read TX FIFO. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx FIFO write and read offset address + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * Represents the offset address to read RX FIFO. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * Represents the offset address to write RX FIFO. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * Represents the status of the receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * Represents the status of the transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART asynchronous FIFO status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Represents whether or not the APB TX asynchronous FIFO is full.\\ + * 0: Not full\\ + * 1: Full\\ + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Represents whether or not the APB TX asynchronous FIFO is empty.\\ + * 0: Not empty\\ + * 1: Empty\\ + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Represents whether or not the APB RX asynchronous FIFO is full.\\ + * 0: Not full\\ + * 1: Full\\ + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Represents whether or not the APB RX asynchronous FIFO is empty.\\ + * 0: Not empty\\ + * 1: Empty\\ + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * Configures the idle time before the receiver receives the first + * AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit). + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * Configures the interval between the last AT_CMD and subsequent data.\\Measurement + * unit: bit time (the time to transmit 1 bit). + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * Configures the interval between two AT_CMD characters.\\Measurement unit: bit time + * (the time to transmit 1 bit). + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * Configures the AT_CMD character. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * Configures the number of continuous AT_CMD characters a receiver can receive. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * Represents the minimal input clock counter value between two positive edges. It is + * used for baud rate detection. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * Represents the minimal input clock counter value between two negative edges. It is + * used for baud rate detection. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * Represents the minimum duration time of a low-level pulse. It is used for baud rate + * detection.\\Measurement unit: APB_CLK clock cycle. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * Represents the maximum duration time for a high-level pulse. It is used for baud + * rate detection.\\Measurement unit: APB_CLK clock cycle. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * Represents the number of RXD edge changes. It is used for baud rate detection. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36774432; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART register configuration update + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Configures whether or not to synchronize registers.\\ + * 0: Not synchronize\\ + * 1: Synchronize\\ + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * Configures the UART ID. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; +extern uart_dev_t UART2; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..e9e9b83373 --- /dev/null +++ b/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1228 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG register + * USB uart out endpoint timeout configuration. + */ +#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN : R/W; bitpos: [0]; default: 0; + * USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer + * is automatically cleared and reg_serial_timeout_status is asserted. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S 0 +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS : R/WTC/SS; bitpos: [1]; default: 0; + * Serial out ep triggers a timeout event. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S 1 +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear reg_serial_timeout_status. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S 2 + +/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG register + * USB uart out endpoint timeout configuration. + */ +#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX : R/W; bitpos: [31:0]; default: 4800768; + * USB serial out ep timeout max threshold value, indicates the maximum time that + * waiting for ESP to take away data in memory. This value is in steps of 20.83ns. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX 0xFFFFFFFFU +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..b9149fef7a --- /dev/null +++ b/components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,980 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t test_enable:1; + /** test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t test_usb_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t usb_mem_pd:1; + /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t rts:1; + /** dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t dtr:1; + /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bdata_bits:8; + /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bparity_type:8; + /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_in_afifo_reset_wr:1; + /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_in_afifo_reset_rd:1; + /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_out_afifo_reset_wr:1; + /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_out_afifo_reset_rd:1; + /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_out_afifo_rempty:1; + /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + +/** Type of serial_ep_timeout0 register + * USB uart out endpoint timeout configuration. + */ +typedef union { + struct { + /** serial_timeout_en : R/W; bitpos: [0]; default: 0; + * USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer + * is automatically cleared and reg_serial_timeout_status is asserted. + */ + uint32_t serial_timeout_en:1; + /** serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0; + * Serial out ep triggers a timeout event. + */ + uint32_t serial_timeout_status:1; + /** serial_timeout_status_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear reg_serial_timeout_status. + */ + uint32_t serial_timeout_status_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_serial_ep_timeout0_reg_t; + +/** Type of serial_ep_timeout1 register + * USB uart out endpoint timeout configuration. + */ +typedef union { + struct { + /** serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768; + * USB serial out ep timeout max threshold value, indicates the maximum time that + * waiting for ESP to take away data in memory. This value is in steps of 20.83ns. + */ + uint32_t serial_timeout_max:32; + }; + uint32_t val; +} usb_serial_jtag_serial_ep_timeout1_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t jtag_in_flush_int_raw:1; + /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t sof_int_raw:1; + /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_out_recv_pkt_int_raw:1; + /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_in_empty_int_raw:1; + /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t pid_err_int_raw:1; + /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t crc5_err_int_raw:1; + /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t crc16_err_int_raw:1; + /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t stuff_err_int_raw:1; + /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t in_token_rec_in_ep1_int_raw:1; + /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t usb_bus_reset_int_raw:1; + /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t out_ep1_zero_payload_int_raw:1; + /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t out_ep2_zero_payload_int_raw:1; + /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t rts_chg_int_raw:1; + /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t dtr_chg_int_raw:1; + /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t get_line_code_int_raw:1; + /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_st:1; + /** sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_st:1; + /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ + uint32_t serial_out_recv_pkt_int_st:1; + /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_st:1; + /** pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_st:1; + /** crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_st:1; + /** crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_st:1; + /** stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_st:1; + /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ + uint32_t in_token_rec_in_ep1_int_st:1; + /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_st:1; + /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep1_zero_payload_int_st:1; + /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep2_zero_payload_int_st:1; + /** rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_st:1; + /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_st:1; + /** get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_st:1; + /** set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_ena:1; + /** sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_ena:1; + /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_ena:1; + /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_ena:1; + /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_ena:1; + /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_ena:1; + /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_ena:1; + /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_ena:1; + /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_ena:1; + /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_ena:1; + /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_ena:1; + /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_ena:1; + /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_ena:1; + /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_ena:1; + /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_ena:1; + /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_clr:1; + /** sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_clr:1; + /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_clr:1; + /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_clr:1; + /** pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_clr:1; + /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_clr:1; + /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_clr:1; + /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_clr:1; + /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_clr:1; + /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_clr:1; + /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_clr:1; + /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_clr:1; + /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_clr:1; + /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_clr:1; + /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_clr:1; + /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t in_fifo_cnt:2; + /** in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t in_fifo_empty:1; + /** in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t in_fifo_full:1; + /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t out_fifo_cnt:2; + /** out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t out_fifo_empty:1; + /** out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t out_fifo_full:1; + /** in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t in_fifo_reset:1; + /** out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t in_ep0_state:2; + /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t in_ep0_wr_addr:7; + /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t in_ep1_state:2; + /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t in_ep1_wr_addr:7; + /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t in_ep2_state:2; + /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t in_ep2_wr_addr:7; + /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t in_ep3_state:2; + /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t in_ep3_wr_addr:7; + /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t out_ep0_state:2; + /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t out_ep0_wr_addr:7; + /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t out_ep1_state:2; + /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t out_ep1_wr_addr:7; + /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t out_ep1_rd_addr:7; + /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t out_ep2_state:2; + /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t out_ep2_wr_addr:7; + /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t bchar_format:8; + /** bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t bparity_type:8; + /** bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36770368; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_ep_timeout0; + volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_ep_timeout1; + uint32_t reserved_074[3]; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/interrupts.c b/components/soc/esp32c61/interrupts.c new file mode 100644 index 0000000000..8ed40cbd50 --- /dev/null +++ b/components/soc/esp32c61/interrupts.c @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "WIFI_MAC", + [1] = "WIFI_MAC_NMI", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "LP_TIMER", + [8] = "COEX", + [9] = "BLE_TIMER", + [10] = "BLE_SEC", + [11] = "I2C_MST", + [12] = "ZB_MAC", + [13] = "PMU", + [14] = "EFUSE", + [15] = "LP_RTC_TIMER", + [16] = "LP_WDT", + [17] = "LP_PERI_TIMEOUT", + [18] = "LP_APM_M0", + [19] = "CPU_FROM_CPU_0", + [20] = "CPU_FROM_CPU_1", + [21] = "CPU_FROM_CPU_2", + [22] = "CPU_FROM_CPU_3", + [23] = "ASSIST_DEBUG", + [24] = "TRACE", + [25] = "CACHE", + [26] = "CPU_PERI_TIMEOUT", + [27] = "GPIO_INTERRUPT_PRO", + [28] = "GPIO_INTERRUPT_EXT", + [29] = "PAU", + [30] = "HP_PERI_TIMEOUT", + [31] = "MODEM_PERI_TIMEOUT", + [32] = "HP_APM_M0", + [33] = "HP_APM_M1", + [34] = "HP_APM_M2", + [35] = "HP_APM_M3", + [36] = "MSPI", + [37] = "I2S1", + [38] = "UART0", + [39] = "UART1", + [40] = "UART2", + [41] = "LEDC", + [42] = "USB", + [43] = "I2C_EXT0", + [44] = "TG0_T0", + [45] = "TG0_T1", + [46] = "TG0_WDT", + [47] = "TG1_T0", + [48] = "TG1_T1", + [49] = "TG1_WDT", + [50] = "SYSTIMER_TARGET0", + [51] = "SYSTIMER_TARGET1", + [52] = "SYSTIMER_TARGET2", + [53] = "APB_ADC", + [54] = "DMA_IN_CH0", + [55] = "DMA_IN_CH1", + [56] = "DMA_OUT_CH0", + [57] = "DMA_OUT_CH1", + [58] = "GPSPI2", + [59] = "SHA", + [60] = "ECC", + [61] = "ECDSA", +}; diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld new file mode 100644 index 0000000000..27f74d56ac --- /dev/null +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C = 0x60004000 ); +PROVIDE ( UART2 = 0x60006000 ); +PROVIDE ( LEDC = 0x60007000 ); +PROVIDE ( TIMERG0 = 0x60008000 ); +PROVIDE ( TIMERG1 = 0x60009000 ); +PROVIDE ( SYSTIMER = 0x6000A000 ); +PROVIDE ( I2S = 0x6000C000 ); +PROVIDE ( ADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( PVT_MONITOR = 0x60019000 ); +PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 ); +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( ECDSA = 0x6008E000 ); +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( TCM_MEM_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( MISC = 0x6009F000 ); +PROVIDE ( MODEM0 = 0x600A0000 ); +PROVIDE ( MODEM1 = 0x600AC000 ); +PROVIDE ( MODEM_PWR0 = 0x600AD000 ); +PROVIDE ( MODEM_PWR1 = 0x600AF000 ); +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( LPPERI = 0x600B2800 ); +PROVIDE ( LP_ANA = 0x600B2C00 ); +PROVIDE ( LP_TEE = 0x600B3400 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( LP_IO_MUX = 0x600B4000 ); +PROVIDE ( LP_GPIO = 0x600B4400 ); +PROVIDE ( EFUSE_AND_OTP_DEBUG0= 0x600B4800 ); +PROVIDE ( EFUSE_AND_OTP_DEBUG1= 0x600B4C00 ); +PROVIDE ( TRACE = 0x600C0000 ); +PROVIDE ( BUS_MONITOR = 0x600C2000 ); +PROVIDE ( INTPRI_REG = 0x600C5000 ); +PROVIDE ( CACHE_CFG = 0x600C8000 );