From a76e84a1e1c9759a3409b6bd5a1aeeaedc92dedf Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Thu, 9 May 2024 12:26:40 +0530 Subject: [PATCH] feat: enabled aes and sha support for esp32c5 mp version This commit enabled AES and SHA support for esp32c5. --- .../mp/include/soc/Kconfig.soc_caps.in | 52 +++++++++++++++++++ .../soc/esp32c5/mp/include/soc/soc_caps.h | 26 +++++----- 2 files changed, 65 insertions(+), 13 deletions(-) diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index f979c3a8f5..e86a802b46 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -63,10 +63,18 @@ config SOC_SYSTIMER_SUPPORTED bool default y +config SOC_AES_SUPPORTED + bool + default y + config SOC_MPI_SUPPORTED bool default y +config SOC_SHA_SUPPORTED + bool + default y + config SOC_RSA_SUPPORTED bool default y @@ -95,6 +103,22 @@ config SOC_XTAL_SUPPORT_48M bool default y +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + config SOC_ADC_PERIPH_NUM int default 1 @@ -387,6 +411,34 @@ config SOC_RSA_MAX_BIT_LEN int default 3072 +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + config SOC_SPI_PERIPH_NUM int default 2 diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index f732abb49c..74831b79bf 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -45,9 +45,9 @@ // #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 // #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 -// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627 +#define SOC_AES_SUPPORTED 1 #define SOC_MPI_SUPPORTED 1 -// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624 +#define SOC_SHA_SUPPORTED 1 #define SOC_RSA_SUPPORTED 1 // #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616 // #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619 @@ -80,13 +80,13 @@ #define SOC_XTAL_SUPPORT_48M 1 /*-------------------------- AES CAPS -----------------------------------------*/ -// #define SOC_AES_SUPPORT_DMA (1) +#define SOC_AES_SUPPORT_DMA (1) /* Has a centralized DMA, which is shared with all peripherals */ -// #define SOC_AES_GDMA (1) +#define SOC_AES_GDMA (1) -// #define SOC_AES_SUPPORT_AES_128 (1) -// #define SOC_AES_SUPPORT_AES_256 (1) +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ @@ -362,19 +362,19 @@ for SHA this means that the biggest safe amount of bytes is 31 blocks of 128 bytes = 3968 */ -// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) -// #define SOC_SHA_SUPPORT_DMA (1) +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) /* The SHA engine is able to resume hashing from a user */ -// #define SOC_SHA_SUPPORT_RESUME (1) +#define SOC_SHA_SUPPORT_RESUME (1) /* Has a centralized DMA, which is shared with all peripherals */ -// #define SOC_SHA_GDMA (1) +#define SOC_SHA_GDMA (1) /* Supported HW algorithms */ -// #define SOC_SHA_SUPPORT_SHA1 (1) -// #define SOC_SHA_SUPPORT_SHA224 (1) -// #define SOC_SHA_SUPPORT_SHA256 (1) +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) /*--------------------------- ECDSA CAPS ---------------------------------------*/ // #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)