From 7c6f50b7448eb6f531c4c61c24cc6fedfc7df912 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 23 Dec 2024 12:21:08 +0800 Subject: [PATCH 1/2] fix(i2s): fixed some missing content and updates --- components/esp_driver_i2s/i2s_pdm.c | 2 +- components/hal/esp32c61/include/hal/i2s_ll.h | 37 +++++++++++++++++++ .../esp32c61/include/soc/Kconfig.soc_caps.in | 8 ++++ .../soc/esp32c61/include/soc/soc_caps.h | 2 + 4 files changed, 48 insertions(+), 1 deletion(-) diff --git a/components/esp_driver_i2s/i2s_pdm.c b/components/esp_driver_i2s/i2s_pdm.c index 82cb7f29e9..64c2d00f81 100644 --- a/components/esp_driver_i2s/i2s_pdm.c +++ b/components/esp_driver_i2s/i2s_pdm.c @@ -368,7 +368,7 @@ static esp_err_t i2s_pdm_rx_calculate_clock(i2s_chan_handle_t handle, const i2s_ clk_info->mclk_div = clk_info->sclk / clk_info->mclk; /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */ - ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk >= 0.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); + ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); #if SOC_I2S_SUPPORTS_PDM2PCM if (!handle->is_raw_pdm) { /* Set down-sampling configuration */ diff --git a/components/hal/esp32c61/include/hal/i2s_ll.h b/components/hal/esp32c61/include/hal/i2s_ll.h index 501790a0fd..2e901c79e7 100644 --- a/components/hal/esp32c61/include/hal/i2s_ll.h +++ b/components/hal/esp32c61/include/hal/i2s_ll.h @@ -986,6 +986,43 @@ static inline void i2s_ll_rx_set_pdm_amplify_num(i2s_dev_t *hw, uint32_t amp_num hw->rx_pdm2pcm_conf.rx_pdm2pcm_amplify_num = amp_num; } +/** + * @brief Set I2S RX PDM high pass filter param0 (only for compatibility) + * + * @param hw Peripheral I2S hardware instance address. + * @param param no effect + */ +static inline void i2s_ll_rx_set_pdm_hp_filter_param0(i2s_dev_t *hw, uint32_t param) +{ + // Can't configure HP filter param on this target + (void) hw; + (void) param; +} + +/** + * @brief Set I2S RX PDM high pass filter param5 (only for compatibility) + * + * @param hw Peripheral I2S hardware instance address. + * @param param no effect + */ +static inline void i2s_ll_rx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t param) +{ + // Can't configure HP filter param on this target + (void) hw; + (void) param; +} + +/** + * @brief Enable I2S RX PDM high pass filter + * + * @param hw Peripheral I2S hardware instance address. + * @param enable Set true to enable I2S RX PDM high pass filter, set false to bypass it + */ +static inline void i2s_ll_rx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable) +{ + hw->rx_pdm2pcm_conf.rx_pdm_hp_bypass = !enable; +} + /** * @brief Configura TX a/u-law decompress or compress * diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index bf70d0811d..0285265f7c 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -591,6 +591,10 @@ config SOC_I2S_SUPPORTS_PDM2PCM bool default y +config SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER + bool + default y + config SOC_I2S_SUPPORTS_TX_SYNC_CNT bool default y @@ -607,6 +611,10 @@ config SOC_I2S_SUPPORTS_TDM bool default y +config SOC_I2S_TDM_FULL_DATA_WIDTH + bool + default y + config SOC_I2S_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index cf21801b94..634a9ee88c 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -249,10 +249,12 @@ #define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter #define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data #define SOC_I2S_SUPPORTS_PDM2PCM (1) // Support to input PDM format but read PCM format data with the help of PDM to PCM filter +#define SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER (1) #define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1) #define SOC_I2S_PDM_MAX_TX_LINES (2) #define SOC_I2S_PDM_MAX_RX_LINES (1U) #define SOC_I2S_SUPPORTS_TDM (1) +#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ #define SOC_I2S_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- LEDC CAPS ---------------------------------------*/ From 7086f4ca6d226063af7e067467b81d0059ed606c Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 23 Dec 2024 12:22:23 +0800 Subject: [PATCH 2/2] fix(i2s): add check for the tdm frame bits num --- components/esp_driver_i2s/i2s_tdm.c | 4 ++++ components/hal/esp32c3/include/hal/i2s_ll.h | 1 + components/hal/esp32c5/include/hal/i2s_ll.h | 2 ++ components/hal/esp32c6/include/hal/i2s_ll.h | 1 + components/hal/esp32c61/include/hal/i2s_ll.h | 2 ++ components/hal/esp32h2/include/hal/i2s_ll.h | 2 ++ components/hal/esp32p4/include/hal/i2s_ll.h | 2 ++ components/hal/esp32s3/include/hal/i2s_ll.h | 1 + 8 files changed, 15 insertions(+) diff --git a/components/esp_driver_i2s/i2s_tdm.c b/components/esp_driver_i2s/i2s_tdm.c index 8f48f91ea4..3029255dc5 100644 --- a/components/esp_driver_i2s/i2s_tdm.c +++ b/components/esp_driver_i2s/i2s_tdm.c @@ -107,6 +107,10 @@ static esp_err_t i2s_tdm_set_slot(i2s_chan_handle_t handle, const i2s_tdm_slot_c handle->total_slot = slot_cfg->total_slot < max_slot_num ? max_slot_num : slot_cfg->total_slot; // At least two slots in a frame if not using PCM short format handle->total_slot = ((handle->total_slot < 2) && (slot_cfg->ws_width != 1)) ? 2 : handle->total_slot; + uint32_t slot_bits = slot_cfg->slot_bit_width == I2S_SLOT_BIT_WIDTH_AUTO ? slot_cfg->data_bit_width : slot_cfg->slot_bit_width; + ESP_RETURN_ON_FALSE(handle->total_slot * slot_bits <= I2S_LL_SLOT_FRAME_BIT_MAX, ESP_ERR_INVALID_ARG, TAG, + "total slots(%"PRIu32") * slot_bit_width(%"PRIu32") exceeds the maximum %d", + handle->total_slot, slot_bits, (int)I2S_LL_SLOT_FRAME_BIT_MAX); uint32_t buf_size = i2s_get_buf_size(handle, slot_cfg->data_bit_width, handle->dma.frame_num); /* The DMA buffer need to re-allocate if the buffer size changed */ if (handle->dma.buf_size != buf_size) { diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h index ef76e3349b..7e1b046678 100644 --- a/components/hal/esp32c3/include/hal/i2s_ll.h +++ b/components/hal/esp32c3/include/hal/i2s_ll.h @@ -33,6 +33,7 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +#define I2S_LL_SLOT_FRAME_BIT_MAX 128 // Up-to 128 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz #define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT diff --git a/components/hal/esp32c5/include/hal/i2s_ll.h b/components/hal/esp32c5/include/hal/i2s_ll.h index 6ba954e554..0a33745fd7 100644 --- a/components/hal/esp32c5/include/hal/i2s_ll.h +++ b/components/hal/esp32c5/include/hal/i2s_ll.h @@ -36,6 +36,8 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +/* Add SOC_I2S_TDM_FULL_DATA_WIDTH in the soc_caps to indicate there is no limitation to support full data width (i.e., 16 slots * 32 bits) */ +#define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz #define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT diff --git a/components/hal/esp32c6/include/hal/i2s_ll.h b/components/hal/esp32c6/include/hal/i2s_ll.h index 7369b1cc41..7ddd8517b4 100644 --- a/components/hal/esp32c6/include/hal/i2s_ll.h +++ b/components/hal/esp32c6/include/hal/i2s_ll.h @@ -34,6 +34,7 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +#define I2S_LL_SLOT_FRAME_BIT_MAX 128 // Up-to 128 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz #define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT diff --git a/components/hal/esp32c61/include/hal/i2s_ll.h b/components/hal/esp32c61/include/hal/i2s_ll.h index 2e901c79e7..85414173ff 100644 --- a/components/hal/esp32c61/include/hal/i2s_ll.h +++ b/components/hal/esp32c61/include/hal/i2s_ll.h @@ -36,6 +36,8 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +/* Add SOC_I2S_TDM_FULL_DATA_WIDTH in the soc_caps to indicate there is no limitation to support full data width (i.e., 16 slots * 32 bits) */ +#define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz #define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h index 2b2f5e90c8..d97a9fbc5d 100644 --- a/components/hal/esp32h2/include/hal/i2s_ll.h +++ b/components/hal/esp32h2/include/hal/i2s_ll.h @@ -34,6 +34,8 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +/* Add SOC_I2S_TDM_FULL_DATA_WIDTH in the soc_caps to indicate there is no limitation to support full data width (i.e., 16 slots * 32 bits) */ +#define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_PLL_F96M_CLK_FREQ (96 * 1000000) // PLL_F96M_CLK: 96MHz #define I2S_LL_PLL_F64M_CLK_FREQ (64 * 1000000) // PLL_F64M_CLK: 64MHz diff --git a/components/hal/esp32p4/include/hal/i2s_ll.h b/components/hal/esp32p4/include/hal/i2s_ll.h index a6d84c84e5..d39d8df29a 100644 --- a/components/hal/esp32p4/include/hal/i2s_ll.h +++ b/components/hal/esp32p4/include/hal/i2s_ll.h @@ -37,6 +37,8 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +/* Add SOC_I2S_TDM_FULL_DATA_WIDTH in the soc_caps to indicate there is no limitation to support full data width (i.e., 16 slots * 32 bits) */ +#define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_XTAL_CLK_FREQ (40 * 1000000) // XTAL_CLK: 40MHz #define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source on P4, use XTAL as default diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h index 97d7aacec7..25310ca4de 100644 --- a/components/hal/esp32s3/include/hal/i2s_ll.h +++ b/components/hal/esp32s3/include/hal/i2s_ll.h @@ -34,6 +34,7 @@ extern "C" { #define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width #define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +#define I2S_LL_SLOT_FRAME_BIT_MAX 128 // Up-to 128 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz #define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT