diff --git a/components/esp_rom/esp32c3/include/esp32c3/rom/aes.h b/components/esp_rom/esp32c3/include/esp32c3/rom/aes.h
index b5445e1dae..42c0cf7c31 100644
--- a/components/esp_rom/esp32c3/include/esp32c3/rom/aes.h
+++ b/components/esp_rom/esp32c3/include/esp32c3/rom/aes.h
@@ -23,8 +23,7 @@ enum AES_TYPE {
 
 enum AES_BITS {
     AES128,
-    AES192,
-    AES256
+    AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
 };
 
 void ets_aes_enable(void);
diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/aes.h b/components/esp_rom/esp32c5/include/esp32c5/rom/aes.h
index e579c669b5..b252e2a5f5 100644
--- a/components/esp_rom/esp32c5/include/esp32c5/rom/aes.h
+++ b/components/esp_rom/esp32c5/include/esp32c5/rom/aes.h
@@ -23,8 +23,7 @@ enum AES_TYPE {
 
 enum AES_BITS {
     AES128,
-    AES192,
-    AES256
+    AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
 };
 
 void ets_aes_enable(void);
diff --git a/components/esp_rom/esp32c6/include/esp32c6/rom/aes.h b/components/esp_rom/esp32c6/include/esp32c6/rom/aes.h
index 0af2066637..d9bdcf6fa8 100644
--- a/components/esp_rom/esp32c6/include/esp32c6/rom/aes.h
+++ b/components/esp_rom/esp32c6/include/esp32c6/rom/aes.h
@@ -23,8 +23,7 @@ enum AES_TYPE {
 
 enum AES_BITS {
     AES128,
-    AES192,
-    AES256
+    AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
 };
 
 void ets_aes_enable(void);
diff --git a/components/esp_rom/esp32h2/include/esp32h2/rom/aes.h b/components/esp_rom/esp32h2/include/esp32h2/rom/aes.h
index 0af2066637..d9bdcf6fa8 100644
--- a/components/esp_rom/esp32h2/include/esp32h2/rom/aes.h
+++ b/components/esp_rom/esp32h2/include/esp32h2/rom/aes.h
@@ -23,8 +23,7 @@ enum AES_TYPE {
 
 enum AES_BITS {
     AES128,
-    AES192,
-    AES256
+    AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
 };
 
 void ets_aes_enable(void);
diff --git a/components/esp_rom/esp32p4/include/esp32p4/rom/aes.h b/components/esp_rom/esp32p4/include/esp32p4/rom/aes.h
index ae30dee344..28e0287d59 100644
--- a/components/esp_rom/esp32p4/include/esp32p4/rom/aes.h
+++ b/components/esp_rom/esp32p4/include/esp32p4/rom/aes.h
@@ -23,8 +23,7 @@ enum AES_TYPE {
 
 enum AES_BITS {
     AES128,
-    AES192,
-    AES256
+    AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
 };
 
 void ets_aes_enable(void);
diff --git a/components/esp_rom/esp32s3/include/esp32s3/rom/aes.h b/components/esp_rom/esp32s3/include/esp32s3/rom/aes.h
index 06e834fff3..54b8112c23 100644
--- a/components/esp_rom/esp32s3/include/esp32s3/rom/aes.h
+++ b/components/esp_rom/esp32s3/include/esp32s3/rom/aes.h
@@ -20,8 +20,7 @@ enum AES_TYPE {
 
 enum AES_BITS {
     AES128,
-    AES192,
-    AES256
+    AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
 };
 
 void ets_aes_enable(void);
diff --git a/components/soc/esp32c5/register/soc/aes_reg.h b/components/soc/esp32c5/register/soc/aes_reg.h
index 8dbcb778d7..f55e5e1729 100644
--- a/components/soc/esp32c5/register/soc/aes_reg.h
+++ b/components/soc/esp32c5/register/soc/aes_reg.h
@@ -210,11 +210,11 @@ extern "C" {
 /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
  *  Configures the key length and encryption / decryption of the AES accelerator.\\
  *  0: AES-128 encryption\\
- *  1: AES-192 encryption\\
+ *  1: Reserved\\
  *  2: AES-256 encryption\\
  *  3: Reserved\\
  *  4: AES-128 decryption\\
- *  5: AES-192 decryption\\
+ *  5: Reserved\\
  *  6: AES-256 decryption\\
  *  7: Reserved\\
  */
diff --git a/components/soc/esp32c6/register/soc/aes_reg.h b/components/soc/esp32c6/register/soc/aes_reg.h
index c096489ca4..51deae6b02 100644
--- a/components/soc/esp32c6/register/soc/aes_reg.h
+++ b/components/soc/esp32c6/register/soc/aes_reg.h
@@ -209,7 +209,7 @@ extern "C" {
 #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
 /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
  *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
- *  AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+ *  Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
  */
 #define AES_MODE    0x00000007U
 #define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
diff --git a/components/soc/esp32h2/register/soc/aes_reg.h b/components/soc/esp32h2/register/soc/aes_reg.h
index bf09b4b34a..9db86bf483 100644
--- a/components/soc/esp32h2/register/soc/aes_reg.h
+++ b/components/soc/esp32h2/register/soc/aes_reg.h
@@ -209,7 +209,7 @@ extern "C" {
 #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
 /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
  *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
- *  AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+ *  Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
  */
 #define AES_MODE    0x00000007U
 #define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
diff --git a/components/soc/esp32h4/register/soc/aes_reg.h b/components/soc/esp32h4/register/soc/aes_reg.h
index 5d8b0b9a53..08a7c79e7b 100644
--- a/components/soc/esp32h4/register/soc/aes_reg.h
+++ b/components/soc/esp32h4/register/soc/aes_reg.h
@@ -210,11 +210,11 @@ extern "C" {
 /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
  *  Configures the key length and encryption / decryption of the AES accelerator.
  *  0: AES-128 encryption
- *  1: AES-192 encryption
+ *  1: Reserved
  *  2: AES-256 encryption
  *  3: Reserved
  *  4: AES-128 decryption
- *  5: AES-192 decryption
+ *  5: Reserved
  *  6: AES-256 decryption
  *  7: Reserved
  */
diff --git a/components/soc/esp32p4/register/soc/aes_reg.h b/components/soc/esp32p4/register/soc/aes_reg.h
index 89c229b1dc..fb5caabeb1 100644
--- a/components/soc/esp32p4/register/soc/aes_reg.h
+++ b/components/soc/esp32p4/register/soc/aes_reg.h
@@ -209,7 +209,7 @@ extern "C" {
 #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
 /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
  *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
- *  AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+ *  Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
  */
 #define AES_MODE    0x00000007U
 #define AES_MODE_M  (AES_MODE_V << AES_MODE_S)