From 42cf1d8867e3659162fe46e535e4eecacf13fa7f Mon Sep 17 00:00:00 2001 From: Armando Date: Sun, 8 Sep 2024 10:03:45 +0800 Subject: [PATCH 1/3] fix(mspi): fixed mspi clock wrong on ram loadable app on c5 --- .../esp_private/bootloader_flash_internal.h | 6 ++---- .../src/bootloader_flash_config_esp32c5.c | 16 +++++++++++----- .../src/bootloader_flash_config_esp32p4.c | 4 ++-- .../src/esp32p4/bootloader_esp32p4.c | 2 +- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h index b63d83a311..f79cefbdbd 100644 --- a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h +++ b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h @@ -28,12 +28,10 @@ esp_err_t bootloader_init_spi_flash(void); void bootloader_flash_hardware_init(void); #endif -#if SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT /** - * @brief Initialise flash core clock + * @brief Initialise mspi core clock */ -void bootloader_flash_init_core_clock(void); -#endif //SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT +void bootloader_init_mspi_clock(void); #ifdef __cplusplus } diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c index 92d259b3e9..a876c04173 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c @@ -48,8 +48,18 @@ void IRAM_ATTR bootloader_flash_cs_timing_config() SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); } +void IRAM_ATTR bootloader_init_mspi_clock(void) +{ + // Set source mspi pll clock as 80M in bootloader stage. + // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz + // in this stage, set divider as 6 + mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); + mspi_ll_fast_set_hs_divider(6); +} + void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) { + bootloader_init_mspi_clock(); uint32_t spi_clk_div = 0; switch (pfhdr->spi_speed) { case ESP_IMAGE_SPI_SPEED_DIV_1: @@ -204,11 +214,7 @@ static void bootloader_spi_flash_resume(void) esp_err_t bootloader_init_spi_flash(void) { - // Set source mspi pll clock as 80M in bootloader stage. - // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz - // in this stage, set divider as 6 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); - mspi_ll_fast_set_hs_divider(6); + bootloader_init_mspi_clock(); bootloader_init_flash_configure(); bootloader_spi_flash_resume(); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index c38157840c..78a53b4a6c 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -42,7 +42,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void) SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S); } -void IRAM_ATTR bootloader_flash_init_core_clock(void) +void IRAM_ATTR bootloader_init_mspi_clock(void) { _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL); _spimem_ctrlr_ll_set_core_clock(0, 6); @@ -50,7 +50,7 @@ void IRAM_ATTR bootloader_flash_init_core_clock(void) void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) { - bootloader_flash_init_core_clock(); + bootloader_init_mspi_clock(); uint32_t spi_clk_div = 0; switch (pfhdr->spi_speed) { diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index 950bb1fbd6..9b70bf6817 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -112,7 +112,7 @@ static inline void bootloader_hardware_init(void) #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used. if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) { - bootloader_flash_init_core_clock(); + bootloader_init_mspi_clock(); } #endif } From 17fc026c482efdc27890b1979d01f18a0e5de5ae Mon Sep 17 00:00:00 2001 From: Armando Date: Sun, 8 Sep 2024 10:04:31 +0800 Subject: [PATCH 2/3] fix(pma): fixed pma 15 occupied by rom on c5 issue --- components/esp_hw_support/port/esp32c5/cpu_region_protect.c | 2 ++ components/riscv/include/riscv/csr.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c index cd054372da..95055058c4 100644 --- a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c @@ -69,6 +69,8 @@ static void esp_cpu_configure_invalid_regions(void) // 8. End of address space PMA_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE); + + PMA_ENTRY_CFG_RESET(15); PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE); } diff --git a/components/riscv/include/riscv/csr.h b/components/riscv/include/riscv/csr.h index f393f635ac..5640151c75 100644 --- a/components/riscv/include/riscv/csr.h +++ b/components/riscv/include/riscv/csr.h @@ -136,6 +136,12 @@ extern "C" { RV_CLEAR_CSR((CSR_PMPCFG0) + (ENTRY)/4, (0xFF) << (ENTRY%4)*8); \ } while(0) +/*Reset all permissions of a particular PMACFG entry*/ +#define PMA_ENTRY_CFG_RESET(ENTRY) do {\ + RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY) , 0); \ + RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY) , 0); \ + } while(0) + /******************************************************** Trigger Module register fields (Debug specification) ********************************************************/ From 9c81fe6114d0d2118835713e839b07633be89977 Mon Sep 17 00:00:00 2001 From: Armando Date: Sun, 8 Sep 2024 10:06:07 +0800 Subject: [PATCH 3/3] fix(mspi): fixed mspi clock wrong on ram loadable app on c61, enable tests on c5 c61 --- .../src/bootloader_flash_config_esp32c61.c | 19 ++++++++++++------- .../sdspi/sdkconfig.defaults.esp32c5 | 1 + .../sd_card/sdspi/sdkconfig.defaults.esp32c5 | 1 + tools/test_apps/system/.build-test-rules.yml | 6 ------ .../system/ram_loadable_app/README.md | 4 ++-- .../pytest_ram_loadable_app.py | 7 ++----- .../sdkconfig.defaults.esp32c5 | 1 + 7 files changed, 19 insertions(+), 20 deletions(-) create mode 100644 examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 create mode 100644 tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index 077d67afa2..5cb2c24047 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -46,8 +46,19 @@ void IRAM_ATTR bootloader_flash_cs_timing_config() SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); } +void IRAM_ATTR bootloader_init_mspi_clock(void) +{ + // Set source mspi pll clock as 80M in bootloader stage. + // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz + // in this stage, set divider as 6 + mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); + mspi_ll_fast_set_hs_divider(6); +} + void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) { + bootloader_init_mspi_clock(); + uint32_t spi_clk_div = 0; switch (pfhdr->spi_speed) { case ESP_IMAGE_SPI_SPEED_DIV_1: @@ -198,13 +209,7 @@ static void bootloader_spi_flash_resume(void) esp_err_t bootloader_init_spi_flash(void) { - - // Set source mspi pll clock as 80M in bootloader stage. - // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz - // in this stage, set divider as 6 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); - mspi_ll_fast_set_hs_divider(6); - + bootloader_init_mspi_clock(); bootloader_init_flash_configure(); bootloader_spi_flash_resume(); bootloader_flash_unlock(); diff --git a/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 b/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 index 6b415e1dff..ad99756571 100644 --- a/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 +++ b/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 @@ -1 +1,2 @@ CONFIG_SDMMC_BOARD_ESP32C5_BREAKOUT=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y diff --git a/examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 b/examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 new file mode 100644 index 0000000000..5e9f8e25bd --- /dev/null +++ b/examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 @@ -0,0 +1 @@ +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml index df9884ab56..c2bf739295 100644 --- a/tools/test_apps/system/.build-test-rules.yml +++ b/tools/test_apps/system/.build-test-rules.yml @@ -80,12 +80,6 @@ tools/test_apps/system/panic: temporary: true reason: not supported # TODO: [ESP32c61] IDF-9268 -tools/test_apps/system/ram_loadable_app: - disable: - - if: IDF_TARGET == "esp32c5" - temporary: true - reason: not supported # TODO: [ESP32C5] IDF-8644, IDF-10315 - tools/test_apps/system/rtc_mem_reserve: enable: - if: IDF_TARGET in ["esp32p4"] diff --git a/tools/test_apps/system/ram_loadable_app/README.md b/tools/test_apps/system/ram_loadable_app/README.md index d284a950d8..a9d46976d3 100644 --- a/tools/test_apps/system/ram_loadable_app/README.md +++ b/tools/test_apps/system/ram_loadable_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # RAM loadable app Example diff --git a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py index af446a6749..8329cfc3f6 100644 --- a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py +++ b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py @@ -4,7 +4,6 @@ import pytest from pytest_embedded_idf.dut import IdfDut -@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='esp32c5 support TBD') # TODO: [ESP32C5] IDF-8644, IDF-10315 @pytest.mark.esp32 @pytest.mark.esp32s2 @pytest.mark.esp32s3 @@ -12,7 +11,6 @@ from pytest_embedded_idf.dut import IdfDut @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 -@pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,) @@ -21,8 +19,6 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None: dut.expect('Time since boot: 3 seconds...', timeout=10) -# TODO: [ESP32C5] IDF-8644, IDF-10315, [ESP32C61] IDF-10951 -@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='support TBD') @pytest.mark.esp32 @pytest.mark.esp32s2 @pytest.mark.esp32s3 @@ -30,7 +26,6 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None: @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 -@pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize('config', ['defaults',], indirect=True,) @@ -41,6 +36,7 @@ def test_ram_loadable_app(dut: IdfDut) -> None: # Tests with ram_app runners @pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.ram_app @pytest.mark.parametrize('config', ['defaults',], indirect=True,) def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: @@ -49,6 +45,7 @@ def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: @pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.ram_app @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,) def test_pure_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: diff --git a/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 b/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 new file mode 100644 index 0000000000..5e9f8e25bd --- /dev/null +++ b/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 @@ -0,0 +1 @@ +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y