diff --git a/components/efuse/esp32h2/esp_efuse_table.c b/components/efuse/esp32h2/esp_efuse_table.c index f59aa56de8..31482481ed 100644 --- a/components/efuse/esp32h2/esp_efuse_table.c +++ b/components/efuse/esp32h2/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table e3fb625011fff48d5d8b7569075d0bb3 +// md5_digest_table 1b79da735c5daed71ed7a91a0c55c5b6 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -195,6 +195,22 @@ static const esp_efuse_desc_t WR_DIS_RXIQ_1[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_1, }; +static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DBIAS_VOL_GAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DBIAS_VOL_GAP, +}; + static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, }; @@ -554,23 +570,39 @@ static const esp_efuse_desc_t MAC_EXT[] = { }; static const esp_efuse_desc_t RXIQ_VERSION[] = { - {EFUSE_BLK1, 64, 3}, // [] RF Calibration data. RXIQ version, + {EFUSE_BLK1, 64, 3}, // [] Stores RF Calibration data. RXIQ version, }; static const esp_efuse_desc_t RXIQ_0[] = { - {EFUSE_BLK1, 67, 7}, // [] RF Calibration data. RXIQ data 0, + {EFUSE_BLK1, 67, 7}, // [] Stores RF Calibration data. RXIQ data 0, }; static const esp_efuse_desc_t RXIQ_1[] = { - {EFUSE_BLK1, 74, 7}, // [] RF Calibration data. RXIQ data 1, + {EFUSE_BLK1, 74, 7}, // [] Stores RF Calibration data. RXIQ data 1, +}; + +static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK1, 81, 5}, // [] Stores the PMU active hp dbias, +}; + +static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK1, 86, 5}, // [] Stores the PMU active lp dbias, +}; + +static const esp_efuse_desc_t DSLP_DBIAS[] = { + {EFUSE_BLK1, 91, 4}, // [] Stores the PMU sleep dbias, +}; + +static const esp_efuse_desc_t DBIAS_VOL_GAP[] = { + {EFUSE_BLK1, 95, 5}, // [] Stores the low 1 bit of dbias_vol_gap, }; static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 3}, // [], + {EFUSE_BLK1, 114, 3}, // [] Stores the wafer version minor, }; static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 117, 2}, // [], + {EFUSE_BLK1, 117, 2}, // [] Stores the wafer version major, }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { @@ -578,15 +610,15 @@ static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { }; static const esp_efuse_desc_t FLASH_CAP[] = { - {EFUSE_BLK1, 120, 3}, // [], + {EFUSE_BLK1, 120, 3}, // [] Stores the flash cap, }; static const esp_efuse_desc_t FLASH_TEMP[] = { - {EFUSE_BLK1, 123, 2}, // [], + {EFUSE_BLK1, 123, 2}, // [] Stores the flash temp, }; static const esp_efuse_desc_t FLASH_VENDOR[] = { - {EFUSE_BLK1, 125, 3}, // [], + {EFUSE_BLK1, 125, 3}, // [] Stores the flash vendor, }; static const esp_efuse_desc_t PKG_VERSION[] = { @@ -930,6 +962,26 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { + &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { + &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBIAS[] = { + &WR_DIS_DSLP_DBIAS[0], // [] wr_dis of DSLP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[] = { + &WR_DIS_DBIAS_VOL_GAP[0], // [] wr_dis of DBIAS_VOL_GAP + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR NULL @@ -1377,27 +1429,47 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { }; const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[] = { - &RXIQ_VERSION[0], // [] RF Calibration data. RXIQ version + &RXIQ_VERSION[0], // [] Stores RF Calibration data. RXIQ version NULL }; const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[] = { - &RXIQ_0[0], // [] RF Calibration data. RXIQ data 0 + &RXIQ_0[0], // [] Stores RF Calibration data. RXIQ data 0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[] = { - &RXIQ_1[0], // [] RF Calibration data. RXIQ data 1 + &RXIQ_1[0], // [] Stores RF Calibration data. RXIQ data 1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { + &ACTIVE_HP_DBIAS[0], // [] Stores the PMU active hp dbias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { + &ACTIVE_LP_DBIAS[0], // [] Stores the PMU active lp dbias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBIAS[] = { + &DSLP_DBIAS[0], // [] Stores the PMU sleep dbias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[] = { + &DBIAS_VOL_GAP[0], // [] Stores the low 1 bit of dbias_vol_gap NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // [] + &WAFER_VERSION_MINOR[0], // [] Stores the wafer version minor NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // [] + &WAFER_VERSION_MAJOR[0], // [] Stores the wafer version major NULL }; @@ -1407,17 +1479,17 @@ const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { - &FLASH_CAP[0], // [] + &FLASH_CAP[0], // [] Stores the flash cap NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { - &FLASH_TEMP[0], // [] + &FLASH_TEMP[0], // [] Stores the flash temp NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { - &FLASH_VENDOR[0], // [] + &FLASH_VENDOR[0], // [] Stores the flash vendor NULL }; diff --git a/components/efuse/esp32h2/esp_efuse_table.csv b/components/efuse/esp32h2/esp_efuse_table.csv index 3ddbe98d7f..20b5cec21d 100644 --- a/components/efuse/esp32h2/esp_efuse_table.csv +++ b/components/efuse/esp32h2/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: b69ddcfb39a412df490e3facbbfb46b2 +# This file was generated by regtools.py based on the efuses.yaml file with the version: ef562916e77cf77203c1a4c0cff35ac5 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -56,6 +56,10 @@ WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.RXIQ_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_VERSION WR_DIS.RXIQ_0, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_0 WR_DIS.RXIQ_1, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_1 +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS +WR_DIS.DSLP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBIAS +WR_DIS.DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of DBIAS_VOL_GAP WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR @@ -150,15 +154,19 @@ MAC, EFUSE_BLK1, 40, 8, [MAC_FACT , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address , EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address -RXIQ_VERSION, EFUSE_BLK1, 64, 3, [] RF Calibration data. RXIQ version -RXIQ_0, EFUSE_BLK1, 67, 7, [] RF Calibration data. RXIQ data 0 -RXIQ_1, EFUSE_BLK1, 74, 7, [] RF Calibration data. RXIQ data 1 -WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, [] -WAFER_VERSION_MAJOR, EFUSE_BLK1, 117, 2, [] +RXIQ_VERSION, EFUSE_BLK1, 64, 3, [] Stores RF Calibration data. RXIQ version +RXIQ_0, EFUSE_BLK1, 67, 7, [] Stores RF Calibration data. RXIQ data 0 +RXIQ_1, EFUSE_BLK1, 74, 7, [] Stores RF Calibration data. RXIQ data 1 +ACTIVE_HP_DBIAS, EFUSE_BLK1, 81, 5, [] Stores the PMU active hp dbias +ACTIVE_LP_DBIAS, EFUSE_BLK1, 86, 5, [] Stores the PMU active lp dbias +DSLP_DBIAS, EFUSE_BLK1, 91, 4, [] Stores the PMU sleep dbias +DBIAS_VOL_GAP, EFUSE_BLK1, 95, 5, [] Stores the low 1 bit of dbias_vol_gap +WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, [] Stores the wafer version minor +WAFER_VERSION_MAJOR, EFUSE_BLK1, 117, 2, [] Stores the wafer version major DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 119, 1, [] Disables check of wafer version major -FLASH_CAP, EFUSE_BLK1, 120, 3, [] -FLASH_TEMP, EFUSE_BLK1, 123, 2, [] -FLASH_VENDOR, EFUSE_BLK1, 125, 3, [] +FLASH_CAP, EFUSE_BLK1, 120, 3, [] Stores the flash cap +FLASH_TEMP, EFUSE_BLK1, 123, 2, [] Stores the flash temp +FLASH_VENDOR, EFUSE_BLK1, 125, 3, [] Stores the flash vendor PKG_VERSION, EFUSE_BLK1, 128, 3, [] Package version OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID BLK_VERSION_MINOR, EFUSE_BLK2, 130, 3, [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 diff --git a/components/efuse/esp32h2/include/esp_efuse_table.h b/components/efuse/esp32h2/include/esp_efuse_table.h index fbe83816b0..2aa6a22ee4 100644 --- a/components/efuse/esp32h2/include/esp_efuse_table.h +++ b/components/efuse/esp32h2/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table e3fb625011fff48d5d8b7569075d0bb3 +// md5_digest_table 1b79da735c5daed71ed7a91a0c55c5b6 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -71,6 +71,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; @@ -188,6 +192,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[]; extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/include/soc/efuse_reg.h index aaaaf8b212..532514d587 100644 --- a/components/soc/esp32h2/include/soc/efuse_reg.h +++ b/components/soc/esp32h2/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -612,74 +612,119 @@ extern "C" { * BLOCK1 data register $n. */ #define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_RXIQ_VERSION : R; bitpos: [2:0]; default: 0; - * RF Calibration data. RXIQ version +/** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0; + * Stores RF Calibration data. RXIQ version. */ #define EFUSE_RXIQ_VERSION 0x00000007U #define EFUSE_RXIQ_VERSION_M (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S) #define EFUSE_RXIQ_VERSION_V 0x00000007U #define EFUSE_RXIQ_VERSION_S 0 -/** EFUSE_RXIQ_0 : R; bitpos: [9:3]; default: 0; - * RF Calibration data. RXIQ data 0 +/** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0; + * Stores RF Calibration data. RXIQ data 0. */ #define EFUSE_RXIQ_0 0x0000007FU #define EFUSE_RXIQ_0_M (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S) #define EFUSE_RXIQ_0_V 0x0000007FU #define EFUSE_RXIQ_0_S 3 -/** EFUSE_RXIQ_1 : R; bitpos: [16:10]; default: 0; - * RF Calibration data. RXIQ data 1 +/** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0; + * Stores RF Calibration data. RXIQ data 1. */ #define EFUSE_RXIQ_1 0x0000007FU #define EFUSE_RXIQ_1_M (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S) #define EFUSE_RXIQ_1_V 0x0000007FU #define EFUSE_RXIQ_1_S 10 -/** EFUSE_RESERVED_1_81 : R; bitpos: [31:17]; default: 0; - * reserved +/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0; + * Stores the PMU active hp dbias. */ -#define EFUSE_RESERVED_1_81 0x00007FFFU -#define EFUSE_RESERVED_1_81_M (EFUSE_RESERVED_1_81_V << EFUSE_RESERVED_1_81_S) -#define EFUSE_RESERVED_1_81_V 0x00007FFFU -#define EFUSE_RESERVED_1_81_S 17 +#define EFUSE_ACTIVE_HP_DBIAS 0x0000001FU +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000001FU +#define EFUSE_ACTIVE_HP_DBIAS_S 17 +/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0; + * Stores the PMU active lp dbias. + */ +#define EFUSE_ACTIVE_LP_DBIAS 0x0000001FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000001FU +#define EFUSE_ACTIVE_LP_DBIAS_S 22 +/** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0; + * Stores the PMU sleep dbias. + */ +#define EFUSE_DSLP_DBIAS 0x0000000FU +#define EFUSE_DSLP_DBIAS_M (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S) +#define EFUSE_DSLP_DBIAS_V 0x0000000FU +#define EFUSE_DSLP_DBIAS_S 27 +/** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0; + * Stores the low 1 bit of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_VALUE1 (BIT(31)) +#define EFUSE_DBIAS_VOL_GAP_VALUE1_M (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S) +#define EFUSE_DBIAS_VOL_GAP_VALUE1_V 0x00000001U +#define EFUSE_DBIAS_VOL_GAP_VALUE1_S 31 /** EFUSE_RD_MAC_SYS_3_REG register * BLOCK1 data register $n. */ #define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; +/** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0; + * Stores the high 3 bits of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_VALUE2 0x00000007U +#define EFUSE_DBIAS_VOL_GAP_VALUE2_M (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S) +#define EFUSE_DBIAS_VOL_GAP_VALUE2_V 0x00000007U +#define EFUSE_DBIAS_VOL_GAP_VALUE2_S 0 +/** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0; + * Stores the sign bit of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_SIGN (BIT(3)) +#define EFUSE_DBIAS_VOL_GAP_SIGN_M (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S) +#define EFUSE_DBIAS_VOL_GAP_SIGN_V 0x00000001U +#define EFUSE_DBIAS_VOL_GAP_SIGN_S 3 +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0; * Reserved. */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2 0x00003FFFU #define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [20:18]; default: 0; */ +#define EFUSE_MAC_RESERVED_2_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_2_S 4 +/** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0; + * Stores the wafer version minor. + */ #define EFUSE_WAFER_VERSION_MINOR 0x00000007U #define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) #define EFUSE_WAFER_VERSION_MINOR_V 0x00000007U #define EFUSE_WAFER_VERSION_MINOR_S 18 -/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [22:21]; default: 0; */ +/** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0; + * Stores the wafer version major. + */ #define EFUSE_WAFER_VERSION_MAJOR 0x00000003U #define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) #define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U #define EFUSE_WAFER_VERSION_MAJOR_S 21 -/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [23]; default: 0; - * Disables check of wafer version major +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0; + * Disables check of wafer version major. */ #define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(23)) #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 23 -/** EFUSE_FLASH_CAP : R; bitpos: [26:24]; default: 0; */ +/** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0; + * Stores the flash cap. + */ #define EFUSE_FLASH_CAP 0x00000007U #define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) #define EFUSE_FLASH_CAP_V 0x00000007U #define EFUSE_FLASH_CAP_S 24 -/** EFUSE_FLASH_TEMP : R; bitpos: [28:27]; default: 0; */ +/** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0; + * Stores the flash temp. + */ #define EFUSE_FLASH_TEMP 0x00000003U #define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) #define EFUSE_FLASH_TEMP_V 0x00000003U #define EFUSE_FLASH_TEMP_S 27 -/** EFUSE_FLASH_VENDOR : R; bitpos: [31:29]; default: 0; */ +/** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0; + * Stores the flash vendor. + */ #define EFUSE_FLASH_VENDOR 0x00000007U #define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) #define EFUSE_FLASH_VENDOR_V 0x00000007U diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/include/soc/efuse_struct.h index a1029528ce..c64eaa140c 100644 --- a/components/soc/esp32h2/include/soc/efuse_struct.h +++ b/components/soc/esp32h2/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -486,22 +486,34 @@ typedef union { */ typedef union { struct { - /** rxiq_version : R; bitpos: [2:0]; default: 0; - * RF Calibration data. RXIQ version + /** rxiq_version : RO; bitpos: [2:0]; default: 0; + * Stores RF Calibration data. RXIQ version. */ uint32_t rxiq_version:3; - /** rxiq_0 : R; bitpos: [9:3]; default: 0; - * RF Calibration data. RXIQ data 0 + /** rxiq_0 : RO; bitpos: [9:3]; default: 0; + * Stores RF Calibration data. RXIQ data 0. */ uint32_t rxiq_0:7; - /** rxiq_1 : R; bitpos: [16:10]; default: 0; - * RF Calibration data. RXIQ data 1 + /** rxiq_1 : RO; bitpos: [16:10]; default: 0; + * Stores RF Calibration data. RXIQ data 1. */ uint32_t rxiq_1:7; - /** reserved_1_81 : R; bitpos: [31:17]; default: 0; - * reserved + /** active_hp_dbias : RO; bitpos: [21:17]; default: 0; + * Stores the PMU active hp dbias. */ - uint32_t reserved_1_81:15; + uint32_t active_hp_dbias:5; + /** active_lp_dbias : RO; bitpos: [26:22]; default: 0; + * Stores the PMU active lp dbias. + */ + uint32_t active_lp_dbias:5; + /** dslp_dbias : RO; bitpos: [30:27]; default: 0; + * Stores the PMU sleep dbias. + */ + uint32_t dslp_dbias:4; + /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0; + * Stores the low 1 bit of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_value1:1; }; uint32_t val; } efuse_rd_mac_sys_2_reg_t; @@ -511,23 +523,41 @@ typedef union { */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0; + * Stores the high 3 bits of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_value2:3; + /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0; + * Stores the sign bit of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_sign:1; + /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0; * Reserved. */ - uint32_t mac_reserved_2:18; - /** wafer_version_minor : R; bitpos: [20:18]; default: 0; */ + uint32_t mac_reserved_2:14; + /** wafer_version_minor : RO; bitpos: [20:18]; default: 0; + * Stores the wafer version minor. + */ uint32_t wafer_version_minor:3; - /** wafer_version_major : R; bitpos: [22:21]; default: 0; */ + /** wafer_version_major : RO; bitpos: [22:21]; default: 0; + * Stores the wafer version major. + */ uint32_t wafer_version_major:2; - /** disable_wafer_version_major : R; bitpos: [23]; default: 0; - * Disables check of wafer version major + /** disable_wafer_version_major : RO; bitpos: [23]; default: 0; + * Disables check of wafer version major. */ uint32_t disable_wafer_version_major:1; - /** flash_cap : R; bitpos: [26:24]; default: 0; */ + /** flash_cap : RO; bitpos: [26:24]; default: 0; + * Stores the flash cap. + */ uint32_t flash_cap:3; - /** flash_temp : R; bitpos: [28:27]; default: 0; */ + /** flash_temp : RO; bitpos: [28:27]; default: 0; + * Stores the flash temp. + */ uint32_t flash_temp:2; - /** flash_vendor : R; bitpos: [31:29]; default: 0; */ + /** flash_vendor : RO; bitpos: [31:29]; default: 0; + * Stores the flash vendor. + */ uint32_t flash_vendor:3; }; uint32_t val;