diff --git a/components/efuse/esp32c61/esp_efuse_table.c b/components/efuse/esp32c61/esp_efuse_table.c index 4ff8c7c62f..1130f42b5a 100644 --- a/components/efuse/esp32c61/esp_efuse_table.c +++ b/components/efuse/esp32c61/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table af9aaa79feb0970d90f35360a5113f03 +// md5_digest_table 0edc6a5b20a41c88fdc0cf51a810c53e // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -231,6 +231,34 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; +static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBG, +}; + +static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBG, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP, +}; + static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; @@ -368,43 +396,43 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 39, 1}, // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 39, 1}, // [] Represents whether cache is disabled. 1: Disabled 0: Enabled., }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged, + {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged, }; static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 52, 1}, // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned, + {EFUSE_BLK0, 52, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 53, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16, + {EFUSE_BLK0, 53, 2}, // [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)), }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { @@ -452,11 +480,11 @@ static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled, + {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled, + {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable, }; static const esp_efuse_desc_t FLASH_TPUW[] = { @@ -464,23 +492,23 @@ static const esp_efuse_desc_t FLASH_TPUW[] = { }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable, + {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable, }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable, + {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 98, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable, + {EFUSE_BLK0, 98, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable, + {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable, + {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { @@ -500,27 +528,47 @@ static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { }; static const esp_efuse_desc_t HYS_EN_PAD[] = { - {EFUSE_BLK0, 121, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled, + {EFUSE_BLK0, 121, 1}, // [] Set bits to enable hysteresis function of PAD0~27, }; static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { - {EFUSE_BLK0, 122, 1}, // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable, + {EFUSE_BLK0, 122, 1}, // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable., }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { - {EFUSE_BLK0, 123, 2}, // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration, + {EFUSE_BLK0, 123, 2}, // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled, }; static const esp_efuse_desc_t DIS_WIFI6[] = { - {EFUSE_BLK0, 125, 1}, // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled., + {EFUSE_BLK0, 125, 1}, // [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled, }; static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = { - {EFUSE_BLK0, 126, 1}, // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable, + {EFUSE_BLK0, 126, 1}, // [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled, }; static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { - {EFUSE_BLK0, 127, 1}, // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable, + {EFUSE_BLK0, 127, 1}, // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable, +}; + +static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { + {EFUSE_BLK0, 128, 4}, // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader, +}; + +static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_EN[] = { + {EFUSE_BLK0, 132, 1}, // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled, +}; + +static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { + {EFUSE_BLK0, 133, 1}, // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { + {EFUSE_BLK0, 134, 12}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t REPEAT_DATA4[] = { + {EFUSE_BLK0, 160, 24}, // [] Reserved, }; static const esp_efuse_desc_t MAC[] = { @@ -580,6 +628,34 @@ static const esp_efuse_desc_t PKG_VERSION[] = { {EFUSE_BLK1, 90, 3}, // [] Package version, }; +static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK1, 93, 4}, // [] Active HP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK1, 97, 4}, // [] Active LP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t LSLP_HP_DBG[] = { + {EFUSE_BLK1, 101, 2}, // [] LSLP HP DBG of fixed voltage, +}; + +static const esp_efuse_desc_t LSLP_HP_DBIAS[] = { + {EFUSE_BLK1, 103, 4}, // [] LSLP HP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t DSLP_LP_DBG[] = { + {EFUSE_BLK1, 107, 4}, // [] DSLP LP DBG of fixed voltage, +}; + +static const esp_efuse_desc_t DSLP_LP_DBIAS[] = { + {EFUSE_BLK1, 111, 5}, // [] DSLP LP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = { + {EFUSE_BLK1, 116, 5}, // [] DBIAS gap between LP and HP, +}; + static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; @@ -950,6 +1026,41 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { + &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { + &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = { + &WR_DIS_LSLP_HP_DBG[0], // [] wr_dis of LSLP_HP_DBG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = { + &WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = { + &WR_DIS_DSLP_LP_DBG[0], // [] wr_dis of DSLP_LP_DBG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = { + &WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { + &WR_DIS_LP_HP_DBIAS_VOL_GAP[0], // [] wr_dis of LP_HP_DBIAS_VOL_GAP + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL @@ -1121,52 +1232,52 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_ICACHE[0], // [] Represents whether cache is disabled. 1: Disabled 0: Enabled. NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned + &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 + &WDT_DELAY_SEL[0], // [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)) NULL }; @@ -1226,12 +1337,12 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable NULL }; @@ -1241,27 +1352,27 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable NULL }; @@ -1286,32 +1397,57 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { - &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled + &HYS_EN_PAD[0], // [] Set bits to enable hysteresis function of PAD0~27 NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { - &XTS_DPA_CLK_ENABLE[0], // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable. NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { - &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[] = { - &DIS_WIFI6[0], // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled. + &DIS_WIFI6[0], // [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = { - &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable + &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { - &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable + &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { + &BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[0], // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[] = { + &BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { + &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_REPEAT_DATA4[] = { + &REPEAT_DATA4[0], // [] Reserved NULL }; @@ -1385,6 +1521,41 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { + &ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { + &ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = { + &LSLP_HP_DBG[0], // [] LSLP HP DBG of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = { + &LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = { + &DSLP_LP_DBG[0], // [] DSLP LP DBG of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = { + &DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = { + &LP_HP_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and HP + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID NULL diff --git a/components/efuse/esp32c61/esp_efuse_table.csv b/components/efuse/esp32c61/esp_efuse_table.csv index 2a82ff95b5..a4ce7e0a20 100644 --- a/components/efuse/esp32c61/esp_efuse_table.csv +++ b/components/efuse/esp32c61/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f05ff9d292b10d2360200fae1d15e8d +# This file was generated by regtools.py based on the efuses.yaml file with the version: d435ade68d90ef96b0522478b2d8ba75 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -65,6 +65,13 @@ WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS +WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG +WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS +WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG +WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS +WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE @@ -99,16 +106,16 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ -DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\ -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\ -USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\ -VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\ -WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\ +DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether cache is disabled. 1: Disabled 0: Enabled. +DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled +JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled +DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled +USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged +VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned +WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)) SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 55, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 58, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 59, 1, [] Revoke 2nd secure boot key @@ -120,24 +127,29 @@ KEY_PURPOSE_3, EFUSE_BLK0, 76, 4, [KEY3_PUR KEY_PURPOSE_4, EFUSE_BLK0, 80, 4, [KEY4_PURPOSE] Represents the purpose of Key4 KEY_PURPOSE_5, EFUSE_BLK0, 84, 4, [KEY5_PURPOSE] Represents the purpose of Key5 SEC_DPA_LEVEL, EFUSE_BLK0, 88, 2, [] Represents the spa secure level by configuring the clock random divide mode -SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\ +SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable FLASH_TPUW, EFUSE_BLK0, 92, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ -DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable\\ -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable\\ -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\ -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\ +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable +DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Represents the types of UART printing FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot SECURE_VERSION, EFUSE_BLK0, 104, 16, [] Represents the version used by ESP-IDF anti-rollback feature SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable -HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\ -XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable\\ -XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration\\ -DIS_WIFI6, EFUSE_BLK0, 125, 1, [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.\\ -ECDSA_DISABLE_P192, EFUSE_BLK0, 126, 1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable -ECC_FORCE_CONST_TIME, EFUSE_BLK0, 127, 1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable +HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Set bits to enable hysteresis function of PAD0~27 +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable. +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled +DIS_WIFI6, EFUSE_BLK0, 125, 1, [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled +ECDSA_DISABLE_P192, EFUSE_BLK0, 126, 1, [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 127, 1, [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable +BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION, EFUSE_BLK0, 128, 4, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader +BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 132, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled +BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 133, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable +RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 134, 12, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +REPEAT_DATA4, EFUSE_BLK0, 160, 24, [] Reserved MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address @@ -156,6 +168,13 @@ PSRAM_CAP, EFUSE_BLK1, 83, 3, [] PSRAM PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] PSRAM vendor TEMP, EFUSE_BLK1, 88, 2, [] Temperature PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version +ACTIVE_HP_DBIAS, EFUSE_BLK1, 93, 4, [] Active HP DBIAS of fixed voltage +ACTIVE_LP_DBIAS, EFUSE_BLK1, 97, 4, [] Active LP DBIAS of fixed voltage +LSLP_HP_DBG, EFUSE_BLK1, 101, 2, [] LSLP HP DBG of fixed voltage +LSLP_HP_DBIAS, EFUSE_BLK1, 103, 4, [] LSLP HP DBIAS of fixed voltage +DSLP_LP_DBG, EFUSE_BLK1, 107, 4, [] DSLP LP DBG of fixed voltage +DSLP_LP_DBIAS, EFUSE_BLK1, 111, 5, [] DSLP LP DBIAS of fixed voltage +LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 116, 5, [] DBIAS gap between LP and HP OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode calibration diff --git a/components/efuse/esp32c61/include/esp_efuse_table.h b/components/efuse/esp32c61/include/esp_efuse_table.h index 40844a0581..81b5a77bef 100644 --- a/components/efuse/esp32c61/include/esp_efuse_table.h +++ b/components/efuse/esp32c61/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table af9aaa79feb0970d90f35360a5113f03 +// md5_digest_table 0edc6a5b20a41c88fdc0cf51a810c53e // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -78,6 +78,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; @@ -174,6 +181,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_REPEAT_DATA4[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; @@ -188,6 +200,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; diff --git a/components/soc/esp32c61/register/soc/efuse_reg.h b/components/soc/esp32c61/register/soc/efuse_reg.h index fa1866d023..1bf75495d7 100644 --- a/components/soc/esp32c61/register/soc/efuse_reg.h +++ b/components/soc/esp32c61/register/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -169,7 +169,7 @@ extern "C" { #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 /** EFUSE_DIS_ICACHE : RO; bitpos: [7]; default: 0; - * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether cache is disabled.\\ 1: Disabled\\ 0: Enabled.\\ */ #define EFUSE_DIS_ICACHE (BIT(7)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) @@ -233,22 +233,24 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 14 /** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) #define EFUSE_USB_DREFH_V 0x00000003U #define EFUSE_USB_DREFH_S 15 /** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) #define EFUSE_USB_DREFL_V 0x00000003U #define EFUSE_USB_DREFL_S 17 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [19]; default: 0; - * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not - * exchanged\\ + * Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged.\\ 1: + * exchanged\\ 0: not exchanged\\ */ #define EFUSE_USB_EXCHG_PINS (BIT(19)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) @@ -263,10 +265,8 @@ extern "C" { #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 20 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [22:21]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ + * lp wdt timeout threshold at startup = initial timeout value * (2 ^ + * (EFUSE_WDT_DELAY_SEL + 1)) */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) @@ -281,24 +281,24 @@ extern "C" { #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 23 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [26]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking first secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(26)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 26 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [27]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking second secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(27)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 27 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [28]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking third secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(28)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) @@ -366,15 +366,15 @@ extern "C" { #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 24 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [26]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether secure boot is enabled or disabled. 1. Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_EN (BIT(26)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 26 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [27]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + * Represents whether revoking aggressive secure boot is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(27)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) @@ -395,23 +395,22 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE0_BASE + 0x38) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ + * Represents whether Download mode is disable or enable. 1. Disable\\ 0: Enable. */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: - * Enable\\ + * Represents whether direct boot mode is disabled or enabled. 1. Disable\\ 0: Enable. */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. - * Disable\\ 0: Enable\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable\\ + * 0: Enable. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) @@ -426,8 +425,7 @@ extern "C" { #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 3 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [4]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: - * Disable\\ + * Represents whether security download is enabled or disabled. 1: Enable\\ 0: Disable. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(4)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) @@ -463,47 +461,46 @@ extern "C" { #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 24 /** EFUSE_HYS_EN_PAD : RO; bitpos: [25]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Set bits to enable hysteresis function of PAD0~27 */ #define EFUSE_HYS_EN_PAD (BIT(25)) #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 25 /** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [26]; default: 0; - * Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: - * Disable\\ + * Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: + * Disable.\\ */ #define EFUSE_XTS_DPA_CLK_ENABLE (BIT(26)) #define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) #define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_S 26 /** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; - * Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: - * Low\\ 0: Decided by register configuration\\ + * Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: + * Moderate 1. Low\\ 0: Disabled\\ */ #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) #define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 /** EFUSE_DIS_WIFI6 : RO; bitpos: [29]; default: 0; - * Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is - * disable\\ 0: WiFi 6 is enabled.\\ + * Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable, 0: + * WIFI6 is enabled. */ #define EFUSE_DIS_WIFI6 (BIT(29)) #define EFUSE_DIS_WIFI6_M (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S) #define EFUSE_DIS_WIFI6_V 0x00000001U #define EFUSE_DIS_WIFI6_S 29 /** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [30]; default: 0; - * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. + * Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled. */ #define EFUSE_ECDSA_DISABLE_P192 (BIT(30)) #define EFUSE_ECDSA_DISABLE_P192_M (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S) #define EFUSE_ECDSA_DISABLE_P192_V 0x00000001U #define EFUSE_ECDSA_DISABLE_P192_S 30 /** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [31]; default: 0; - * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. - * \\ 0: Disable. + * Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: + * Disable */ #define EFUSE_ECC_FORCE_CONST_TIME (BIT(31)) #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) @@ -514,25 +511,65 @@ extern "C" { * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE0_BASE + 0x3c) -/** EFUSE_RD_REPEAT_DATA3 : RO; bitpos: [31:0]; default: 0; - * Reserved. +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION : RO; bitpos: [3:0]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader. */ -#define EFUSE_RD_REPEAT_DATA3 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA3_M (EFUSE_RD_REPEAT_DATA3_V << EFUSE_RD_REPEAT_DATA3_S) -#define EFUSE_RD_REPEAT_DATA3_V 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA3_S 0 +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [4]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is + * enabled.\\1: Enabled\\0: Disabled\\ + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(4)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 4 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [5]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader.\\1: Enable\\0: Disable\\ + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(5)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S 5 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR : RO; bitpos: [17:6]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S 6 +/** EFUSE_RD_RESERVE_0_146 : RW; bitpos: [31:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_146 0x00003FFFU +#define EFUSE_RD_RESERVE_0_146_M (EFUSE_RD_RESERVE_0_146_V << EFUSE_RD_RESERVE_0_146_S) +#define EFUSE_RD_RESERVE_0_146_V 0x00003FFFU +#define EFUSE_RD_RESERVE_0_146_S 18 /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE0_BASE + 0x40) -/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [31:0]; default: 0; +/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [23:0]; default: 0; * Reserved. */ -#define EFUSE_RD_REPEAT_DATA4 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA4 0x00FFFFFFU #define EFUSE_RD_REPEAT_DATA4_M (EFUSE_RD_REPEAT_DATA4_V << EFUSE_RD_REPEAT_DATA4_S) -#define EFUSE_RD_REPEAT_DATA4_V 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA4_V 0x00FFFFFFU #define EFUSE_RD_REPEAT_DATA4_S 0 +/** EFUSE_RD_RESERVE_0_184 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_184 0x000000FFU +#define EFUSE_RD_RESERVE_0_184_M (EFUSE_RD_RESERVE_0_184_V << EFUSE_RD_RESERVE_0_184_S) +#define EFUSE_RD_RESERVE_0_184_V 0x000000FFU +#define EFUSE_RD_RESERVE_0_184_S 24 /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys @@ -653,32 +690,74 @@ extern "C" { #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) #define EFUSE_PKG_VERSION_V 0x00000007U #define EFUSE_PKG_VERSION_S 26 -/** EFUSE_RESERVED_1_93 : R; bitpos: [31:29]; default: 0; - * reserved +/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [31:29]; default: 0; + * Active HP DBIAS of fixed voltage */ -#define EFUSE_RESERVED_1_93 0x00000007U -#define EFUSE_RESERVED_1_93_M (EFUSE_RESERVED_1_93_V << EFUSE_RESERVED_1_93_S) -#define EFUSE_RESERVED_1_93_V 0x00000007U -#define EFUSE_RESERVED_1_93_S 29 +#define EFUSE_ACTIVE_HP_DBIAS 0x00000007U +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x00000007U +#define EFUSE_ACTIVE_HP_DBIAS_S 29 /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE0_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. +/** EFUSE_ACTIVE_HP_DBIAS_1 : R; bitpos: [0]; default: 0; + * Active HP DBIAS of fixed voltage */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. +#define EFUSE_ACTIVE_HP_DBIAS_1 (BIT(0)) +#define EFUSE_ACTIVE_HP_DBIAS_1_M (EFUSE_ACTIVE_HP_DBIAS_1_V << EFUSE_ACTIVE_HP_DBIAS_1_S) +#define EFUSE_ACTIVE_HP_DBIAS_1_V 0x00000001U +#define EFUSE_ACTIVE_HP_DBIAS_1_S 0 +/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [4:1]; default: 0; + * Active LP DBIAS of fixed voltage */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_S 1 +/** EFUSE_LSLP_HP_DBG : R; bitpos: [6:5]; default: 0; + * LSLP HP DBG of fixed voltage + */ +#define EFUSE_LSLP_HP_DBG 0x00000003U +#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S) +#define EFUSE_LSLP_HP_DBG_V 0x00000003U +#define EFUSE_LSLP_HP_DBG_S 5 +/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [10:7]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ +#define EFUSE_LSLP_HP_DBIAS 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S) +#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_S 7 +/** EFUSE_DSLP_LP_DBG : R; bitpos: [14:11]; default: 0; + * DSLP LP DBG of fixed voltage + */ +#define EFUSE_DSLP_LP_DBG 0x0000000FU +#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S) +#define EFUSE_DSLP_LP_DBG_V 0x0000000FU +#define EFUSE_DSLP_LP_DBG_S 11 +/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [19:15]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ +#define EFUSE_DSLP_LP_DBIAS 0x0000001FU +#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S) +#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU +#define EFUSE_DSLP_LP_DBIAS_S 15 +/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [24:20]; default: 0; + * DBIAS gap between LP and HP + */ +#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S) +#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 20 +/** EFUSE_RESERVED_1_121 : R; bitpos: [31:25]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_121 0x0000007FU +#define EFUSE_RESERVED_1_121_M (EFUSE_RESERVED_1_121_V << EFUSE_RESERVED_1_121_S) +#define EFUSE_RESERVED_1_121_V 0x0000007FU +#define EFUSE_RESERVED_1_121_S 25 /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys @@ -2000,25 +2079,46 @@ extern "C" { * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE0_BASE + 0x188) -/** EFUSE_RD_REPEAT_DATA_ERR3 : RO; bitpos: [31:0]; default: 0; - * Reserved. +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION */ -#define EFUSE_RD_REPEAT_DATA_ERR3 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR3_M (EFUSE_RD_REPEAT_DATA_ERR3_V << EFUSE_RD_REPEAT_DATA_ERR3_S) -#define EFUSE_RD_REPEAT_DATA_ERR3_V 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR3_S 0 +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_V 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR (BIT(4)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S 4 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR : RO; bitpos: [5]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR (BIT(5)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S 5 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR : RO; bitpos: [17:6]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_V 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_S 6 /** EFUSE_RD_REPEAT_DATA_ERR4_REG register * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE0_BASE + 0x18c) -/** EFUSE_RD_REPEAT_DATA_ERR4 : RO; bitpos: [31:0]; default: 0; - * Reserved. +/** EFUSE_RD_REPEAT_DATA4_ERR : RO; bitpos: [23:0]; default: 0; + * Represents the programming error of EFUSE_RD_REPEAT_DATA4 */ -#define EFUSE_RD_REPEAT_DATA_ERR4 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR4_M (EFUSE_RD_REPEAT_DATA_ERR4_V << EFUSE_RD_REPEAT_DATA_ERR4_S) -#define EFUSE_RD_REPEAT_DATA_ERR4_V 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR4_S 0 +#define EFUSE_RD_REPEAT_DATA4_ERR 0x00FFFFFFU +#define EFUSE_RD_REPEAT_DATA4_ERR_M (EFUSE_RD_REPEAT_DATA4_ERR_V << EFUSE_RD_REPEAT_DATA4_ERR_S) +#define EFUSE_RD_REPEAT_DATA4_ERR_V 0x00FFFFFFU +#define EFUSE_RD_REPEAT_DATA4_ERR_S 0 /** EFUSE_RD_RS_DATA_ERR0_REG register * Represents rd_rs_data_err @@ -2204,7 +2304,7 @@ extern "C" { * eFuse version register. */ #define EFUSE_DATE_REG (DR_REG_EFUSE0_BASE + 0x198) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37753088; +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 38801520; * Stores eFuse version. */ #define EFUSE_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/efuse_struct.h b/components/soc/esp32c61/register/soc/efuse_struct.h index 291d8b4565..2994dd8836 100644 --- a/components/soc/esp32c61/register/soc/efuse_struct.h +++ b/components/soc/esp32c61/register/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -183,7 +183,7 @@ typedef union { */ uint32_t rd_dis:7; /** dis_icache : RO; bitpos: [7]; default: 0; - * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether cache is disabled.\\ 1: Disabled\\ 0: Enabled.\\ */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [8]; default: 0; @@ -223,16 +223,18 @@ typedef union { */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [16:15]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [18:17]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [19]; default: 0; - * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not - * exchanged\\ + * Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged.\\ 1: + * exchanged\\ 0: not exchanged\\ */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [20]; default: 0; @@ -241,10 +243,8 @@ typedef union { */ uint32_t vdd_spi_as_gpio:1; /** wdt_delay_sel : RO; bitpos: [22:21]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ + * lp wdt timeout threshold at startup = initial timeout value * (2 ^ + * (EFUSE_WDT_DELAY_SEL + 1)) */ uint32_t wdt_delay_sel:2; /** spi_boot_crypt_cnt : RO; bitpos: [25:23]; default: 0; @@ -253,18 +253,18 @@ typedef union { */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [26]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking first secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [27]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking second secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [28]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking third secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_key_revoke2:1; /** rd_reserve_0_61 : RW; bitpos: [31:29]; default: 0; @@ -309,12 +309,12 @@ typedef union { */ uint32_t sec_dpa_level:2; /** secure_boot_en : RO; bitpos: [26]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether secure boot is enabled or disabled. 1. Enable\\ 0: Disable. */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [27]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + * Represents whether revoking aggressive secure boot is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_aggressive_revoke:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; @@ -333,17 +333,16 @@ typedef union { typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ + * Represents whether Download mode is disable or enable. 1. Disable\\ 0: Enable. */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: - * Enable\\ + * Represents whether direct boot mode is disabled or enabled. 1. Disable\\ 0: Enable. */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. - * Disable\\ 0: Enable\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable\\ + * 0: Enable. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [3]; default: 0; @@ -352,8 +351,7 @@ typedef union { */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [4]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: - * Disable\\ + * Represents whether security download is enabled or disabled. 1: Enable\\ 0: Disable. */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [6:5]; default: 0; @@ -374,32 +372,31 @@ typedef union { */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad : RO; bitpos: [25]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Set bits to enable hysteresis function of PAD0~27 */ uint32_t hys_en_pad:1; /** xts_dpa_clk_enable : RO; bitpos: [26]; default: 0; - * Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: - * Disable\\ + * Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: + * Disable.\\ */ uint32_t xts_dpa_clk_enable:1; /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; - * Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: - * Low\\ 0: Decided by register configuration\\ + * Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: + * Moderate 1. Low\\ 0: Disabled\\ */ uint32_t xts_dpa_pseudo_level:2; /** dis_wifi6 : RO; bitpos: [29]; default: 0; - * Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is - * disable\\ 0: WiFi 6 is enabled.\\ + * Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable, 0: + * WIFI6 is enabled. */ uint32_t dis_wifi6:1; /** ecdsa_disable_p192 : RO; bitpos: [30]; default: 0; - * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. + * Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled. */ uint32_t ecdsa_disable_p192:1; /** ecc_force_const_time : RO; bitpos: [31]; default: 0; - * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. - * \\ 0: Disable. + * Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: + * Disable */ uint32_t ecc_force_const_time:1; }; @@ -411,10 +408,31 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data3 : RO; bitpos: [31:0]; default: 0; - * Reserved. + /** bootloader_anti_rollback_secure_version : RO; bitpos: [3:0]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader. */ - uint32_t rd_repeat_data3:32; + uint32_t bootloader_anti_rollback_secure_version:4; + /** bootloader_anti_rollback_en : RO; bitpos: [4]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is + * enabled.\\1: Enabled\\0: Disabled\\ + */ + uint32_t bootloader_anti_rollback_en:1; + /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [5]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader.\\1: Enable\\0: Disable\\ + */ + uint32_t bootloader_anti_rollback_update_in_rom:1; + /** recovery_bootloader_flash_sector : RO; bitpos: [17:6]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. + */ + uint32_t recovery_bootloader_flash_sector:12; + /** rd_reserve_0_146 : RW; bitpos: [31:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_146:14; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; @@ -424,10 +442,14 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data4 : RO; bitpos: [31:0]; default: 0; + /** rd_repeat_data4 : RO; bitpos: [23:0]; default: 0; * Reserved. */ - uint32_t rd_repeat_data4:32; + uint32_t rd_repeat_data4:24; + /** rd_reserve_0_184 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_184:8; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; @@ -517,10 +539,10 @@ typedef union { * Package version */ uint32_t pkg_version:3; - /** reserved_1_93 : R; bitpos: [31:29]; default: 0; - * reserved + /** active_hp_dbias : R; bitpos: [31:29]; default: 0; + * Active HP DBIAS of fixed voltage */ - uint32_t reserved_1_93:3; + uint32_t active_hp_dbias:3; }; uint32_t val; } efuse_rd_mac_sys2_reg_t; @@ -530,14 +552,38 @@ typedef union { */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. + /** active_hp_dbias_1 : R; bitpos: [0]; default: 0; + * Active HP DBIAS of fixed voltage */ - uint32_t mac_reserved_2:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. + uint32_t active_hp_dbias_1:1; + /** active_lp_dbias : R; bitpos: [4:1]; default: 0; + * Active LP DBIAS of fixed voltage */ - uint32_t sys_data_part0_0:14; + uint32_t active_lp_dbias:4; + /** lslp_hp_dbg : R; bitpos: [6:5]; default: 0; + * LSLP HP DBG of fixed voltage + */ + uint32_t lslp_hp_dbg:2; + /** lslp_hp_dbias : R; bitpos: [10:7]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ + uint32_t lslp_hp_dbias:4; + /** dslp_lp_dbg : R; bitpos: [14:11]; default: 0; + * DSLP LP DBG of fixed voltage + */ + uint32_t dslp_lp_dbg:4; + /** dslp_lp_dbias : R; bitpos: [19:15]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ + uint32_t dslp_lp_dbias:5; + /** lp_hp_dbias_vol_gap : R; bitpos: [24:20]; default: 0; + * DBIAS gap between LP and HP + */ + uint32_t lp_hp_dbias_vol_gap:5; + /** reserved_1_121 : R; bitpos: [31:25]; default: 0; + * reserved + */ + uint32_t reserved_1_121:7; }; uint32_t val; } efuse_rd_mac_sys3_reg_t; @@ -1793,10 +1839,23 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data_err3 : RO; bitpos: [31:0]; default: 0; - * Reserved. + /** bootloader_anti_rollback_secure_version_err : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION */ - uint32_t rd_repeat_data_err3:32; + uint32_t bootloader_anti_rollback_secure_version_err:4; + /** bootloader_anti_rollback_en_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ + uint32_t bootloader_anti_rollback_en_err:1; + /** bootloader_anti_rollback_update_in_rom_err : RO; bitpos: [5]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM + */ + uint32_t bootloader_anti_rollback_update_in_rom_err:1; + /** recovery_bootloader_flash_sector_err : RO; bitpos: [17:6]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR + */ + uint32_t recovery_bootloader_flash_sector_err:12; + uint32_t reserved_18:14; }; uint32_t val; } efuse_rd_repeat_data_err3_reg_t; @@ -1806,10 +1865,11 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data_err4 : RO; bitpos: [31:0]; default: 0; - * Reserved. + /** rd_repeat_data4_err : RO; bitpos: [23:0]; default: 0; + * Represents the programming error of EFUSE_RD_REPEAT_DATA4 */ - uint32_t rd_repeat_data_err4:32; + uint32_t rd_repeat_data4_err:24; + uint32_t reserved_24:8; }; uint32_t val; } efuse_rd_repeat_data_err4_reg_t; @@ -1952,7 +2012,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753088; + /** date : R/W; bitpos: [27:0]; default: 38801520; * Stores eFuse version. */ uint32_t date:28; @@ -2010,6 +2070,122 @@ typedef union { uint32_t val; } efuse_conf_reg_t; +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + /** Group: EFUSE Status Registers */ /** Type of status register @@ -2158,124 +2334,6 @@ typedef union { } efuse_int_clr_reg_t; -/** Group: EFUSE Configure Registers */ -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 200; - * Configures the active programming time. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - - /** Group: EFUSE_APB2OTP Block0 Write Disable Data */ /** Type of apb2otp_wr_dis register * eFuse apb2otp block0 data register1. @@ -2890,6 +2948,19 @@ typedef union { uint32_t val; } efuse_apb2otp_blk2_w11_reg_t; +/** Type of apb2otp_blk10_w11 register + * eFuse apb2otp block10 data register11. + */ +typedef union { + struct { + /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t apb2otp_block10_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w11_reg_t; + /** Group: EFUSE_APB2OTP Block3 Word1 Data */ /** Type of apb2otp_blk3_w1 register @@ -4196,21 +4267,6 @@ typedef union { } efuse_apb2otp_blk10_w10_reg_t; -/** Group: EFUSE_APB2OTP Block2 Word11 Data */ -/** Type of apb2otp_blk10_w11 register - * eFuse apb2otp block10 data register11. - */ -typedef union { - struct { - /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t apb2otp_block10_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w11_reg_t; - - /** Group: EFUSE_APB2OTP Function Enable Signal */ /** Type of apb2otp_en register * eFuse apb2otp enable configuration register.