From f7137254e94def968a4c91379a0f7542eb9082f7 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Mon, 28 Sep 2020 10:19:56 +0800 Subject: [PATCH 1/3] flash_mmap: register flash2spiram info to ROM --- components/esp_system/port/cpu_start.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index b51efe895e..0e5498ee64 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -359,9 +359,11 @@ void IRAM_ATTR call_start_cpu0(void) #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /* Configure the Cache MMU size for instruction and rodata in flash. */ extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); - extern int _rodata_reserved_start; + extern int _rodata_reserved_start, _rodata_reserved_end; uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t); + uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE)*sizeof(uint32_t); + Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); #endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 @@ -437,6 +439,8 @@ void IRAM_ATTR call_start_cpu0(void) } #endif + static int s_instr_flash2spiram_off = 0; + static int s_rodata_flash2spiram_off = 0; #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS extern void instruction_flash_page_info_init(void); instruction_flash_page_info_init(); @@ -449,10 +453,22 @@ void IRAM_ATTR call_start_cpu0(void) #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS extern void esp_spiram_enable_instruction_access(void); esp_spiram_enable_instruction_access(); + s_instr_flash2spiram_off = instruction_flash2spiram_offset(); #endif #if CONFIG_SPIRAM_RODATA extern void esp_spiram_enable_rodata_access(void); esp_spiram_enable_rodata_access(); + s_rodata_flash2spiram_off = rodata_flash2spiram_offset(); +#endif + +#if CONFIG_IDF_TARGET_ESP32S3 + extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off); + Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size/sizeof(uint32_t), \ + cache_mmu_drom_size/sizeof(uint32_t), \ + (uint32_t)&_rodata_reserved_start, \ + (uint32_t)&_rodata_reserved_end, \ + s_instr_flash2spiram_off, \ + s_rodata_flash2spiram_off); #endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP From 191a494e08f6779b96743ee722a3c03da19173dd Mon Sep 17 00:00:00 2001 From: gaoxiaojie Date: Sat, 10 Oct 2020 16:22:49 +0800 Subject: [PATCH 2/3] support dcache 64Byte and 16k --- components/esp32s3/Kconfig | 6 +++- components/esp_system/port/cpu_start.c | 31 +++++++++++++++----- components/heap/port/esp32s3/memory_layout.c | 9 ++++-- 3 files changed, 34 insertions(+), 12 deletions(-) diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig index 044d7c593c..b59910fae4 100644 --- a/components/esp32s3/Kconfig +++ b/components/esp32s3/Kconfig @@ -108,7 +108,8 @@ menu "ESP32S3-Specific" config ESP32S3_DATA_CACHE_SIZE hex - default 0x4000 if ESP32S3_DATA_CACHE_16KB + # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup + default 0x8000 if ESP32S3_DATA_CACHE_16KB default 0x8000 if ESP32S3_DATA_CACHE_32KB default 0x10000 if ESP32S3_DATA_CACHE_64KB @@ -140,12 +141,15 @@ menu "ESP32S3-Specific" depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB config ESP32S3_DATA_CACHE_LINE_32B bool "32 Bytes" + config ESP32S3_DATA_CACHE_LINE_64B + bool "64 Bytes" endchoice config ESP32S3_DATA_CACHE_LINE_SIZE int default 16 if ESP32S3_DATA_CACHE_LINE_16B default 32 if ESP32S3_DATA_CACHE_LINE_32B + default 64 if ESP32S3_DATA_CACHE_LINE_64B config ESP32S3_DATA_CACHE_WRAP bool "Enable data cache wrap mode" diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 0e5498ee64..5b76be681c 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -359,10 +359,14 @@ void IRAM_ATTR call_start_cpu0(void) #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /* Configure the Cache MMU size for instruction and rodata in flash. */ extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); - extern int _rodata_reserved_start, _rodata_reserved_end; + extern int _rodata_reserved_start; uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t); + +#if CONFIG_IDF_TARGET_ESP32S3 + extern int _rodata_reserved_end; uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE)*sizeof(uint32_t); +#endif Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); #endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 @@ -439,8 +443,6 @@ void IRAM_ATTR call_start_cpu0(void) } #endif - static int s_instr_flash2spiram_off = 0; - static int s_rodata_flash2spiram_off = 0; #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS extern void instruction_flash_page_info_init(void); instruction_flash_page_info_init(); @@ -453,15 +455,22 @@ void IRAM_ATTR call_start_cpu0(void) #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS extern void esp_spiram_enable_instruction_access(void); esp_spiram_enable_instruction_access(); - s_instr_flash2spiram_off = instruction_flash2spiram_offset(); #endif #if CONFIG_SPIRAM_RODATA extern void esp_spiram_enable_rodata_access(void); esp_spiram_enable_rodata_access(); - s_rodata_flash2spiram_off = rodata_flash2spiram_offset(); #endif #if CONFIG_IDF_TARGET_ESP32S3 + int s_instr_flash2spiram_off = 0; + int s_rodata_flash2spiram_off = 0; +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + s_instr_flash2spiram_off = instruction_flash2spiram_offset(); +#endif +#if CONFIG_SPIRAM_RODATA + s_rodata_flash2spiram_off = rodata_flash2spiram_offset(); +#endif + extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off); Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size/sizeof(uint32_t), \ cache_mmu_drom_size/sizeof(uint32_t), \ @@ -471,18 +480,24 @@ void IRAM_ATTR call_start_cpu0(void) s_rodata_flash2spiram_off); #endif -#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP +#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP || \ + CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0; -#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP +#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP icache_wrap_enable = 1; #endif -#if CONFIG_ESP32S2_DATA_CACHE_WRAP +#if CONFIG_ESP32S2_DATA_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP dcache_wrap_enable = 1; #endif extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable); esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable); #endif +#if CONFIG_ESP32S3_DATA_CACHE_16KB + Cache_Invalidate_DCache_All(); + Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000); +#endif + #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 6a7cfc4869..1bd6ad62fc 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -44,6 +44,8 @@ const soc_memory_type_desc_t soc_memory_types[] = { { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, // Type 4: SPI SRAM data { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false}, + // Type 5: DRAM which is not DMA accesible + { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false}, }; const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -69,11 +71,12 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy { 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task -#if CONFIG_ESP32S3_DATA_CACHE_16KB - { 0x3FCF0000, 0xC000, 0, 0}, //Level 9, DRAM -#elif CONFIG_ESP32S3_DATA_CACHE_32KB +#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM #endif +#if CONFIG_ESP32S3_DATA_CACHE_16KB + { 0x3C000000, 0x4000, 5, 0} +#endif #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, 4, 0}, //Fast RTC memory #endif From c3abbe38668d71997b8b721926f21345de881858 Mon Sep 17 00:00:00 2001 From: wanglei Date: Fri, 30 Jul 2021 11:43:40 +0800 Subject: [PATCH 3/3] cache: Update cache.h and autoload api --- .../esp_rom/include/esp32s3/rom/cache.h | 115 +++++++++++++++--- 1 file changed, 98 insertions(+), 17 deletions(-) diff --git a/components/esp_rom/include/esp32s3/rom/cache.h b/components/esp_rom/include/esp32s3/rom/cache.h index 0ec6308f7c..27780446fe 100644 --- a/components/esp_rom/include/esp32s3/rom/cache.h +++ b/components/esp_rom/include/esp32s3/rom/cache.h @@ -103,6 +103,11 @@ typedef enum { CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ } cache_autoload_order_t; +typedef enum { + CACHE_AUTOLOAD_REGION0 = 0, /*!< cache autoload region0 */ + CACHE_AUTOLOAD_REGION1 = 1, /*!< cache autoload region1 */ +} cache_autoload_region_t; + #define CACHE_AUTOLOAD_STEP(i) ((i) - 1) typedef enum { @@ -144,14 +149,17 @@ struct dcache_tag_item { }; struct autoload_config { + uint8_t ena; /*!< autoload enable */ uint8_t order; /*!< autoload step is positive or negative */ uint8_t trigger; /*!< autoload trigger */ - uint8_t ena0; /*!< autoload region0 enable */ - uint8_t ena1; /*!< autoload region1 enable */ - uint32_t addr0; /*!< autoload region0 start address */ - uint32_t size0; /*!< autoload region0 size */ - uint32_t addr1; /*!< autoload region1 start address */ - uint32_t size1; /*!< autoload region1 size */ + uint8_t size; /*!< autoload size */ +}; + +struct autoload_region_config { + uint8_t region; /*!< autoload region*/ + uint8_t ena; /*!< autoload region enable */ + uint32_t addr; /*!< autoload region start address */ + uint32_t size; /*!< autoload region size */ }; struct tag_group_info { @@ -160,6 +168,7 @@ struct tag_group_info { uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ + uint8_t use_legacy; /*!< 1 for using legacy tag api, 0 for using 2rd tag api */ }; struct lock_config { @@ -168,6 +177,39 @@ struct lock_config { uint16_t group; /*!< manual lock group, 0 or 1*/ }; +struct cache_internal_stub_table { + uint32_t (* icache_line_size)(void); + uint32_t (* dcache_line_size)(void); + uint32_t (* icache_addr)(uint32_t addr); + uint32_t (* dcache_addr)(uint32_t addr); + void (* invalidate_icache_items)(uint32_t addr, uint32_t items); + void (* invalidate_dcache_items)(uint32_t addr, uint32_t items); + void (* clean_items)(uint32_t addr, uint32_t items); + void (* writeback_items)(uint32_t addr, uint32_t items); + void (* lock_icache_items)(uint32_t addr, uint32_t items); + void (* lock_dcache_items)(uint32_t addr, uint32_t items); + void (* unlock_icache_items)(uint32_t addr, uint32_t items); + void (* unlock_dcache_items)(uint32_t addr, uint32_t items); + void (* occupy_items)(uint32_t addr, uint32_t items); + uint32_t (* suspend_icache_autoload)(void); + void (* resume_icache_autoload)(uint32_t autoload); + uint32_t (* suspend_dcache_autoload)(void); + void (* resume_dcache_autoload)(uint32_t autoload); + void (* freeze_icache_enable)(cache_freeze_mode_t mode); + void (* freeze_icache_disable)(void); + void (* freeze_dcache_enable)(cache_freeze_mode_t mode); + void (* freeze_dcache_disable)(void); + int (* op_addr)(uint32_t op_icache, uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t), void(* cache_Dop)(uint32_t, uint32_t)); +}; + +typedef void (* cache_op_start)(void); +typedef void (* cache_op_end)(void); + +typedef struct { + cache_op_start start; + cache_op_end end; +} cache_op_cb_t; + #define ESP_ROM_ERR_INVALID_ARG 1 #define MMU_SET_ADDR_ALIGNED_ERROR 2 #define MMU_SET_PASE_SIZE_ERROR 3 @@ -190,7 +232,7 @@ void Cache_MMU_Init(void); * @brief Set ICache mmu mapping. * Please do not call this function in your SDK application. * - * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. + * @param uint32_t ext_ram : MMU_ACCESS_FLASH for flash, MMU_ACCESS_SPIRAM for spiram, MMU_INVALID for invalid. * * @param uint32_t vaddr : virtual address in CPU address space. * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. @@ -217,7 +259,7 @@ int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32 * @brief Set DCache mmu mapping. * Please do not call this function in your SDK application. * - * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. + * @param uint32_t ext_ram : MMU_ACCESS_FLASH for flash, MMU_ACCESS_SPIRAM for spiram, MMU_INVALID for invalid. * * @param uint32_t vaddr : virtual address in CPU address space. * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. @@ -272,9 +314,9 @@ uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus, uint32_t bus_start_addr, uint3 * @brief allocate memory to used by ICache. * Please do not call this function in your SDK application. * - * @param cache_array_t icache_low : the data array bank used by icache low part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1 + * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0 * - * @param cache_array_t icache_high : the data array bank used by icache high part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1 only if icache_low and icache_high is not CACHE_MEMORY_INVALID + * @param cache_array_t icache_high : the data array bank used by icache high part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, or CACHE_MEMORY_IBANK1 only if icache_low and icache_high is CACHE_MEMORY_IBANK0 * * return none */ @@ -284,9 +326,9 @@ void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low, cache_array_t icache_h * @brief allocate memory to used by DCache. * Please do not call this function in your SDK application. * - * @param cache_array_t dcache_low : the data array bank used by dcache low part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1 + * @param cache_array_t dcache_low : the data array bank used by dcache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK1 * - * @param cache_array_t dcache1_high : the data array bank used by dcache high part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1 only if dcache_low0 and dcache_low1 is not CACHE_MEMORY_INVALID + * @param cache_array_t dcache1_high : the data array bank used by dcache high part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, or CACHE_MEMORY_DBANK0 only if dcache_low0 and dcache_low1 is CACHE_MEMORY_DBANK1 * * return none */ @@ -310,7 +352,7 @@ void Cache_Get_Mode(struct cache_mode *mode); * * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B and CACHE_LINE_SIZE_32B * * return none */ @@ -320,9 +362,9 @@ void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_lin * @brief set DCache modes: cache size, associate ways and cache line size. * Please do not call this function in your SDK application. * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC, only CACHE_4WAYS_ASSOC works * * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B * @@ -351,7 +393,7 @@ uint32_t Cache_Address_Through_ICache(uint32_t addr); uint32_t Cache_Address_Through_DCache(uint32_t addr); /** - * @brief Init mmu owner register to make i/d cache use half mmu entries. + * @brief Init Cache for ROM boot, including resetting the Dcache, initializing Owner, MMU, setting DCache mode, Enabling DCache, unmasking bus. * * @param None * @@ -636,6 +678,16 @@ void Cache_End_DCache_Preload(uint32_t autoload); */ void Cache_Config_ICache_Autoload(const struct autoload_config *config); +/** + * @brief Config region autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_region_config * config : region autoload parameters. + * + * @return ESP_ROM_ERR_INVALID_ARG : invalid param, 0 : success + */ +int Cache_Config_ICache_Region_Autoload(const struct autoload_region_config *config); + /** * @brief Enable auto preload for ICache. * Please do not call this function in your SDK application. @@ -666,6 +718,16 @@ void Cache_Disable_ICache_Autoload(void); */ void Cache_Config_DCache_Autoload(const struct autoload_config *config); +/** + * @brief Config region autoload parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_region_config * config : region autoload parameters. + * + * @return ESP_ROM_ERR_INVALID_ARG : invalid param, 0 : success + */ +int Cache_Config_DCache_Region_Autoload(const struct autoload_region_config *config); + /** * @brief Enable auto preload for DCache. * Please do not call this function in your SDK application. @@ -1008,7 +1070,24 @@ void Cache_Freeze_DCache_Disable(void); * * @return None */ -void Cache_Travel_Tag_Memory(struct cache_mode *mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); +void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Travel tag memory to run a call back function, using 2nd tag registers. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory2(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); /** * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. @@ -1092,6 +1171,8 @@ int flash2spiram_rodata_offset(void); uint32_t flash_instr_rodata_start_page(uint32_t bus); uint32_t flash_instr_rodata_end_page(uint32_t bus); +extern struct cache_internal_stub_table* rom_cache_internal_table_ptr; +extern cache_op_cb_t rom_cache_op_cb; #ifdef __cplusplus } #endif