diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c
index 7cc6fde42a..11176146be 100644
--- a/components/esp_psram/device/esp_psram_impl_ap_quad.c
+++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c
@@ -247,16 +247,22 @@ static void psram_gpio_config(void)
 }
 
 #if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING
-static void s_config_psram_clock(void)
+static void s_config_psram_clock(bool init_state)
 {
-    // This function can be extended if we have other psram frequency
     uint32_t clock_conf = 0;
+    if (init_state) {
+        clock_conf = psram_ctrlr_ll_calculate_clock_reg(4);
+        psram_ctrlr_ll_set_spi1_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_1, clock_conf);
+    } else {
+        // This function can be extended if we have other psram frequency
+
 #if (CONFIG_SPIRAM_SPEED == 80)
-    clock_conf = psram_ctrlr_ll_calculate_clock_reg(1);
+        clock_conf = psram_ctrlr_ll_calculate_clock_reg(1);
 #elif (CONFIG_SPIRAM_SPEED == 40)
-    clock_conf = psram_ctrlr_ll_calculate_clock_reg(2);
+        clock_conf = psram_ctrlr_ll_calculate_clock_reg(2);
 #endif
-    psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_0, clock_conf);
+        psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_0, clock_conf);
+    }
 }
 #endif  //#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING
 
@@ -289,6 +295,8 @@ esp_err_t esp_psram_impl_enable(void)
 #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
     //enter MSPI slow mode to init PSRAM device registers
     mspi_timing_enter_low_speed_mode(true);
+#else
+    s_config_psram_clock(true);
 #endif // SOC_SPI_MEM_SUPPORT_TIMING_TUNING
 
     uint32_t psram_id = 0;
@@ -339,7 +347,7 @@ esp_err_t esp_psram_impl_enable(void)
     //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
     mspi_timing_enter_high_speed_mode(true);
 #else
-    s_config_psram_clock();
+    s_config_psram_clock(false);
     //Configure SPI0 PSRAM related SPI Phases
     config_psram_spi_phases();
 #endif
diff --git a/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h b/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
index 868dcee35c..1be6f3ca7d 100644
--- a/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
+++ b/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
@@ -126,6 +126,19 @@ static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock
     SPIMEM0.mem_sram_clk.val = clock_conf;
 }
 
+/**
+ * @brief Set SPI1 bus clock to initialise PSRAM
+ *
+ * @param mspi_id     mspi_id
+ * @param clock_conf  Configuration value for psram clock
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_set_spi1_bus_clock(uint32_t mspi_id, uint32_t clock_conf)
+{
+    HAL_ASSERT(mspi_id == PSRAM_CTRLR_LL_MSPI_ID_1);
+    SPIMEM1.clock.val = clock_conf;
+}
+
 /**
  * Calculate spi_flash clock frequency division parameters for register.
  *
diff --git a/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h b/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h
index 868dcee35c..1be6f3ca7d 100644
--- a/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h
+++ b/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h
@@ -126,6 +126,19 @@ static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock
     SPIMEM0.mem_sram_clk.val = clock_conf;
 }
 
+/**
+ * @brief Set SPI1 bus clock to initialise PSRAM
+ *
+ * @param mspi_id     mspi_id
+ * @param clock_conf  Configuration value for psram clock
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_set_spi1_bus_clock(uint32_t mspi_id, uint32_t clock_conf)
+{
+    HAL_ASSERT(mspi_id == PSRAM_CTRLR_LL_MSPI_ID_1);
+    SPIMEM1.clock.val = clock_conf;
+}
+
 /**
  * Calculate spi_flash clock frequency division parameters for register.
  *