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feat(psram): ecc feature on c5 c61

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This commit is contained in:
Armando
2025-01-17 14:27:38 +08:00
parent 6505bcd297
commit 8a654ffce1
8 changed files with 560 additions and 13 deletions
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57
components/esp_psram/device/esp_psram_impl_ap_quad.c
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@@ -31,7 +31,7 @@ uint8_t esp_psram_impl_get_cs_io(void)
return s_psram_cs_io; return s_psram_cs_io;
} }
void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode, void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
uint32_t cmd, int cmd_bit_len, uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len, uint32_t addr, int addr_bit_len,
int dummy_bits, int dummy_bits,
@@ -72,7 +72,7 @@ static void psram_disable_qio_mode(int spi_num)
//TODO IDF-4307 //TODO IDF-4307
//switch psram burst length(32 bytes or 1024 bytes) //switch psram burst length(32 bytes or 1024 bytes)
//datasheet says it should be 1024 bytes by default //datasheet says it should be 1024 bytes by default
static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode) static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
{ {
psram_exec_cmd(spi_num, mode, psram_exec_cmd(spi_num, mode,
PSRAM_QUAD_SET_BURST_LEN, 8, /* command and command bit len*/ PSRAM_QUAD_SET_BURST_LEN, 8, /* command and command bit len*/
@@ -170,8 +170,50 @@ static void psram_set_cs_timing(void)
{ {
psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_HOLD_VAL); psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_HOLD_VAL);
psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_SETUP_VAL); psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_SETUP_VAL);
#if CONFIG_SPIRAM_ECC_ENABLE
psram_ctrlr_ll_set_ecc_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL);
#endif
} }
#if CONFIG_SPIRAM_ECC_ENABLE
static void s_mspi_ecc_show_info(void)
{
for (int i = 0; i < PSRAM_CTRLR_LL_PMS_REGION_NUMS; i++) {
ESP_EARLY_LOGV(TAG, "region[%d] addr: 0x%08x", i, psram_ctrlr_ll_get_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_0, i));
ESP_EARLY_LOGV(TAG, "region[%d] size: 0x%08x", i, psram_ctrlr_ll_get_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_0, i));
}
uint32_t page_size = psram_ctrlr_ll_get_page_size(PSRAM_CTRLR_LL_MSPI_ID_0);
ESP_EARLY_LOGV(TAG, "ECC page size: %d", page_size);
}
/**
* Enable error correcting code feature
*
* Can add an input parameter for selecting ECC mode if needed
*/
static void s_configure_psram_ecc(void)
{
psram_ctrlr_ll_set_ecc_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_ECC_MODE_16TO18);
psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_0, true);
psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_0, true);
psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_PAGE_SIZE);
psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_0, true);
/**
* Enable ECC region 0 (ACE0)
* Default: ACE0 range: 0 ~ 256MB
* For current Quad PSRAM, ACE0 is enough
*/
psram_ctrlr_ll_set_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_0, 0, 0);
psram_ctrlr_ll_set_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_0, 0, 4096);
psram_ctrlr_ll_set_pms_region_attr(PSRAM_CTRLR_LL_MSPI_ID_0, 0, PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE | PSRAM_CTRLR_LL_PMS_ATTR_READABLE);
psram_ctrlr_ll_enable_pms_region_ecc(PSRAM_CTRLR_LL_MSPI_ID_0, 0, true);
ESP_EARLY_LOGI(TAG, "ECC is enabled");
s_mspi_ecc_show_info();
}
#endif
static void psram_gpio_config(void) static void psram_gpio_config(void)
{ {
//CS1 //CS1
@@ -240,6 +282,9 @@ esp_err_t esp_psram_impl_enable(void)
{ {
psram_gpio_config(); psram_gpio_config();
psram_set_cs_timing(); psram_set_cs_timing();
#if CONFIG_SPIRAM_ECC_ENABLE
s_configure_psram_ecc();
#endif
#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
//enter MSPI slow mode to init PSRAM device registers //enter MSPI slow mode to init PSRAM device registers
@@ -330,9 +375,7 @@ esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
/** /**
* This function is to get the available physical psram size in bytes. * This function is to get the available physical psram size in bytes.
* * If ECC is enabled, available PSRAM size will be 7/8 times its physical size.
* When ECC is enabled, the available size will be reduced.
* On S3 Quad PSRAM, ECC is not enabled for now.
*/ */
esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes) esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
{ {
@@ -340,6 +383,10 @@ esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
#if CONFIG_SPIRAM_ECC_ENABLE
*out_size_bytes = s_psram_size * 7 / 8;
#else
*out_size_bytes = s_psram_size; *out_size_bytes = s_psram_size;
#endif
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE); return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
} }

4
components/esp_psram/device/esp_quad_psram_defs_ap.h
View File

@@ -73,6 +73,10 @@ extern "C" {
#define PSRAM_QUAD_CS_HOLD_VAL 1 #define PSRAM_QUAD_CS_HOLD_VAL 1
#define PSRAM_QUAD_CS_SETUP_VAL 1 #define PSRAM_QUAD_CS_SETUP_VAL 1
#define PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL 3
#define PSRAM_QUAD_PAGE_SIZE 512
#define PSRAM_QUAD_ECC_ENABLE_MASK BIT(8)
// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these. // QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these.
#define PSRAM_QUAD_QEMU_16MB_ID 0x6a #define PSRAM_QUAD_QEMU_16MB_ID 0x6a

8
components/esp_psram/esp32c5/Kconfig.spiram
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@@ -68,5 +68,13 @@ menu "SPI RAM config"
This is a helper indicating this condition: This is a helper indicating this condition:
`CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C5` `CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C5`
config SPIRAM_ECC_ENABLE
bool "Enable PSRAM ECC"
default n
help
Enable MSPI Error-Correcting Code function when accessing PSRAM.
If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code.
source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here
endmenu endmenu

8
components/esp_psram/esp32c61/Kconfig.spiram
View File

@@ -68,5 +68,13 @@ menu "SPI RAM config"
This is a helper indicating this condition: This is a helper indicating this condition:
`CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C61` `CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C61`
config SPIRAM_ECC_ENABLE
bool "Enable PSRAM ECC"
default n
help
Enable MSPI Error-Correcting Code function when accessing PSRAM.
If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code.
source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here
endmenu endmenu

246
components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -30,7 +30,10 @@ extern "C" {
#define PSRAM_CTRLR_LL_MSPI_ID_0 0 #define PSRAM_CTRLR_LL_MSPI_ID_0 0
#define PSRAM_CTRLR_LL_MSPI_ID_1 1 #define PSRAM_CTRLR_LL_MSPI_ID_1 1
#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M #define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M
#define PSRAM_CTRLR_LL_PMS_REGION_NUMS 4
#define PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE (1<<0)
#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1)
/** /**
* @brief PSRAM enum for cs id. * @brief PSRAM enum for cs id.
@@ -40,6 +43,14 @@ typedef enum {
PSRAM_LL_CS_ID_1 = 1, PSRAM_LL_CS_ID_1 = 1,
} psram_ll_cs_id_t; } psram_ll_cs_id_t;
/**
* @brief PSRAM ECC mode
*/
typedef enum {
PSRAM_LL_ECC_MODE_16TO17 = 0,
PSRAM_LL_ECC_MODE_16TO18 = 1,
} psram_ll_ecc_mode_t;
/** /**
* @brief Set PSRAM write cmd * @brief Set PSRAM write cmd
* *
@@ -140,7 +151,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
* @param mspi_id mspi_id * @param mspi_id mspi_id
* @param read_mode read mode * @param read_mode read mode
*/ */
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode) static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{ {
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl; typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val; mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
@@ -258,6 +269,235 @@ static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena
SPIMEM1.ctrl.fcmd_quad = ena; SPIMEM1.ctrl.fcmd_quad = ena;
} }
/*---------------------------------------------------------------
ECC
---------------------------------------------------------------*/
/**
* @brief Set ECC CS hold
*
* @param mspi_id mspi_id
* @param hold_n cs hold time
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_ecc_cs_hold(uint32_t mspi_id, uint32_t hold_n)
{
HAL_ASSERT(hold_n > 0);
SPIMEM0.smem_ac.smem_ecc_cs_hold_time = hold_n - 1;
}
/**
* @brief Set ECC mode
*
* @param mspi_id mspi_id
* @param mode ecc mode
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_ecc_mode(uint32_t mspi_id, psram_ll_ecc_mode_t mode)
{
SPIMEM0.smem_ac.smem_ecc_16to18_byte_en = mode;
}
/**
* @brief Set page size
*
* @param mspi_id mspi_id
* @param size page size
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t size)
{
uint32_t size_val = 0;
switch (size) {
case 256:
size_val = 0;
break;
case 512:
size_val = 1;
break;
case 1024:
size_val = 2;
break;
case 2048:
size_val = 3;
break;
default:
HAL_ASSERT(false);
break;
}
SPIMEM0.smem_ecc_ctrl.smem_page_size = size_val;
}
/**
* @brief Get page size
*
* @param mspi_id mspi_id
*
* @return page size
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id)
{
(void)mspi_id;
uint32_t page_size = 0;
uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
case 0:
page_size = 256;
break;
case 1:
page_size = 512;
break;
case 2:
page_size = 1024;
break;
case 3:
page_size = 2048;
break;
default:
HAL_ASSERT(false);
}
return page_size;
}
/**
* @brief Skip page corner
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_skip_page_corner(uint32_t mspi_id, bool en)
{
SPIMEM0.smem_ac.smem_ecc_skip_page_corner = en;
}
/**
* @brief Enable splitting transactions
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM0.smem_ac.smem_split_trans_en = en;
}
/**
* @brief Enable ECC address conversion
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_ecc_addr_conversion(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM0.smem_ecc_ctrl.smem_ecc_addr_en = en;
}
/*---------------------------------------------------------------
PMS
---------------------------------------------------------------*/
/**
* @brief Enable PMS ECC
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_pms_region_ecc(uint32_t mspi_id, uint32_t region_id, bool en)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_ecc = en;
}
/**
* @brief Set PMS attr
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param attr_mask attribute mask
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_attr(uint32_t mspi_id, uint32_t region_id, uint32_t attr_mask)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 0;
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 0;
if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE) {
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 1;
}
if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_READABLE) {
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 1;
}
}
/**
* @brief Set PMS address
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param addr start addr
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id, uint32_t addr)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s = addr;
}
/**
* @brief Set PMS size
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param size size
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_size(uint32_t mspi_id, uint32_t region_id, uint32_t size)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size = size;
}
/**
* @brief Get PMS address
*
* @param mspi_id mspi_id
* @param region_id region_id
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
return SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s;
}
/**
* @brief Get PMS size
*
* @param mspi_id mspi_id
* @param region_id region_id
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_pms_region_size(uint32_t mspi_id, uint32_t region_id)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
return SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

246
components/hal/esp32c61/include/hal/psram_ctrlr_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -30,7 +30,10 @@ extern "C" {
#define PSRAM_CTRLR_LL_MSPI_ID_0 0 #define PSRAM_CTRLR_LL_MSPI_ID_0 0
#define PSRAM_CTRLR_LL_MSPI_ID_1 1 #define PSRAM_CTRLR_LL_MSPI_ID_1 1
#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M #define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M
#define PSRAM_CTRLR_LL_PMS_REGION_NUMS 4
#define PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE (1<<0)
#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1)
/** /**
* @brief PSRAM enum for cs id. * @brief PSRAM enum for cs id.
@@ -40,6 +43,14 @@ typedef enum {
PSRAM_LL_CS_ID_1 = 1, PSRAM_LL_CS_ID_1 = 1,
} psram_ll_cs_id_t; } psram_ll_cs_id_t;
/**
* @brief PSRAM ECC mode
*/
typedef enum {
PSRAM_LL_ECC_MODE_16TO17 = 0,
PSRAM_LL_ECC_MODE_16TO18 = 1,
} psram_ll_ecc_mode_t;
/** /**
* @brief Set PSRAM write cmd * @brief Set PSRAM write cmd
* *
@@ -140,7 +151,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
* @param mspi_id mspi_id * @param mspi_id mspi_id
* @param read_mode read mode * @param read_mode read mode
*/ */
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode) static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{ {
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl; typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val; mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
@@ -258,6 +269,235 @@ static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena
SPIMEM1.ctrl.fcmd_quad = ena; SPIMEM1.ctrl.fcmd_quad = ena;
} }
/*---------------------------------------------------------------
ECC
---------------------------------------------------------------*/
/**
* @brief Set ECC CS hold
*
* @param mspi_id mspi_id
* @param hold_n cs hold time
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_ecc_cs_hold(uint32_t mspi_id, uint32_t hold_n)
{
HAL_ASSERT(hold_n > 0);
SPIMEM0.smem_ac.smem_ecc_cs_hold_time = hold_n - 1;
}
/**
* @brief Set ECC mode
*
* @param mspi_id mspi_id
* @param mode ecc mode
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_ecc_mode(uint32_t mspi_id, psram_ll_ecc_mode_t mode)
{
SPIMEM0.smem_ac.smem_ecc_16to18_byte_en = mode;
}
/**
* @brief Set page size
*
* @param mspi_id mspi_id
* @param size page size
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t size)
{
uint32_t size_val = 0;
switch (size) {
case 256:
size_val = 0;
break;
case 512:
size_val = 1;
break;
case 1024:
size_val = 2;
break;
case 2048:
size_val = 3;
break;
default:
HAL_ASSERT(false);
break;
}
SPIMEM0.smem_ecc_ctrl.smem_page_size = size_val;
}
/**
* @brief Get page size
*
* @param mspi_id mspi_id
*
* @return page size
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id)
{
(void)mspi_id;
uint32_t page_size = 0;
uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
case 0:
page_size = 256;
break;
case 1:
page_size = 512;
break;
case 2:
page_size = 1024;
break;
case 3:
page_size = 2048;
break;
default:
HAL_ASSERT(false);
}
return page_size;
}
/**
* @brief Skip page corner
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_skip_page_corner(uint32_t mspi_id, bool en)
{
SPIMEM0.smem_ac.smem_ecc_skip_page_corner = en;
}
/**
* @brief Enable splitting transactions
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM0.smem_ac.smem_split_trans_en = en;
}
/**
* @brief Enable ECC address conversion
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_ecc_addr_conversion(uint32_t mspi_id, bool en)
{
(void)mspi_id;
SPIMEM0.smem_ecc_ctrl.smem_ecc_addr_en = en;
}
/*---------------------------------------------------------------
PMS
---------------------------------------------------------------*/
/**
* @brief Enable PMS ECC
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_pms_region_ecc(uint32_t mspi_id, uint32_t region_id, bool en)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_ecc = en;
}
/**
* @brief Set PMS attr
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param attr_mask attribute mask
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_attr(uint32_t mspi_id, uint32_t region_id, uint32_t attr_mask)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 0;
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 0;
if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE) {
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 1;
}
if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_READABLE) {
SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 1;
}
}
/**
* @brief Set PMS address
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param addr start addr
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id, uint32_t addr)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s = addr;
}
/**
* @brief Set PMS size
*
* @param mspi_id mspi_id
* @param region_id region_id
* @param size size
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_pms_region_size(uint32_t mspi_id, uint32_t region_id, uint32_t size)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size = size;
}
/**
* @brief Get PMS address
*
* @param mspi_id mspi_id
* @param region_id region_id
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
return SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s;
}
/**
* @brief Get PMS size
*
* @param mspi_id mspi_id
* @param region_id region_id
*/
__attribute__((always_inline))
static inline uint32_t psram_ctrlr_ll_get_pms_region_size(uint32_t mspi_id, uint32_t region_id)
{
(void)mspi_id;
HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS);
return SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
View File

@@ -109,7 +109,7 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_
* @param mspi_id mspi_id * @param mspi_id mspi_id
* @param read_mode read mode * @param read_mode read mode
*/ */
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode) static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{ {
typeof (SPIMEM0.cache_sctrl) cache_sctrl; typeof (SPIMEM0.cache_sctrl) cache_sctrl;
cache_sctrl.val = SPIMEM0.cache_sctrl.val; cache_sctrl.val = SPIMEM0.cache_sctrl.val;

2
components/hal/include/hal/psram_types.h
View File

@@ -18,7 +18,7 @@ extern "C" {
typedef enum { typedef enum {
PSRAM_HAL_CMD_QPI, /*!< Quad command for psram command */ PSRAM_HAL_CMD_QPI, /*!< Quad command for psram command */
PSRAM_HAL_CMD_SPI, /*!< SPI command for psram command */ PSRAM_HAL_CMD_SPI, /*!< SPI command for psram command */
} psram_hal_cmd_mode_t; } psram_cmd_mode_t;
#ifdef __cplusplus #ifdef __cplusplus
} }