From e353f92b66f503975a5829b4cc5ae2a8e7d6f870 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Thu, 10 Apr 2025 13:15:46 +0800 Subject: [PATCH 1/2] feat(gdma): support gdma on esp32h4 --- .../hal/esp32h4/include/hal/ahb_dma_ll.h | 671 ++++++++++++++++++ components/hal/esp32h4/include/hal/gdma_ll.h | 37 + components/hal/include/hal/apm_hal.h | 9 +- components/soc/esp32c2/gdma_periph.c | 1 - components/soc/esp32c3/gdma_periph.c | 1 - components/soc/esp32c5/gdma_periph.c | 1 - components/soc/esp32c6/gdma_periph.c | 1 - components/soc/esp32c61/gdma_periph.c | 1 - components/soc/esp32h2/gdma_periph.c | 1 - components/soc/esp32h21/gdma_periph.c | 1 - components/soc/esp32h4/gdma_periph.c | 37 + .../esp32h4/include/soc/Kconfig.soc_caps.in | 36 + .../soc/esp32h4/include/soc/gdma_channel.h | 31 + components/soc/esp32h4/include/soc/soc_caps.h | 22 +- .../soc/esp32h4/ld/esp32h4.peripherals.ld | 2 +- .../soc/esp32h4/register/soc/ahb_dma_struct.h | 317 +++------ .../soc/esp32h4/register/soc/hp_apm_reg.h | 146 ++-- .../soc/esp32h4/register/soc/hp_system_reg.h | 50 +- components/soc/esp32s3/gdma_periph.c | 1 - 19 files changed, 1014 insertions(+), 352 deletions(-) create mode 100644 components/hal/esp32h4/include/hal/ahb_dma_ll.h create mode 100644 components/hal/esp32h4/include/hal/gdma_ll.h create mode 100644 components/soc/esp32h4/gdma_periph.c diff --git a/components/hal/esp32h4/include/hal/ahb_dma_ll.h b/components/hal/esp32h4/include/hal/ahb_dma_ll.h new file mode 100644 index 0000000000..facd2dab5a --- /dev/null +++ b/components/hal/esp32h4/include/hal/ahb_dma_ll.h @@ -0,0 +1,671 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* Required for NULL constant */ +#include +#include +#include "soc/soc_caps.h" +#include "hal/gdma_types.h" +#include "hal/assert.h" +#include "soc/ahb_dma_struct.h" +#include "soc/ahb_dma_reg.h" +#include "soc/soc_etm_source.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL) + +#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] + +#define GDMA_LL_RX_EVENT_MASK (0x7F) +#define GDMA_LL_TX_EVENT_MASK (0x3F) + +// any "dummy" peripheral ID can be used for M2M mode +#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC00) +#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3) +#define GDMA_LL_EVENT_TX_EOF (1<<1) +#define GDMA_LL_EVENT_TX_DONE (1<<0) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0 +#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups +#define GDMA_LL_AHB_PAIRS_PER_GROUP 5 // Number of GDMA pairs in each AHB group + +#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][5][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH3, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH4, \ + }}}[group][chan][event] + +#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][5][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH3, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH4, \ + }}}[group][chan][event] + +#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][5][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH3, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH4, \ + }}}[group][chan][task] + +#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][5][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH3, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH4, \ + }}}[group][chan][task] + +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + +///////////////////////////////////// Common ///////////////////////////////////////// + +/** + * @brief Force enable register clock + */ +static inline void ahb_dma_ll_force_enable_reg_clock(ahb_dma_dev_t *dev, bool enable) +{ + dev->misc_conf.dma_clk_en = enable; +} + +/** + * @brief Disable priority arbitration + * + * @param dev DMA register base address + * @param dis True to disable, false to enable + */ +static inline void ahb_dma_ll_disable_prio_arb(ahb_dma_dev_t *dev, bool dis) +{ + dev->misc_conf.dma_arb_pri_dis = dis; +} + +/** + * @brief Reset DMA FSM + * + * @param dev DMA register base address + */ +static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev) +{ + dev->misc_conf.dma_ahbm_rst_inter = 1; + dev->misc_conf.dma_ahbm_rst_inter = 0; +} + +/** + * @brief Preset valid memory range for AHB-DMA + * + * @param dev DMA register base address + */ +static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev) +{ + // AHB-DMA can access SRAM, ROM, MSPI Flash, MSPI PSRAM + dev->intr_mem_start_addr.val = 0x40810000; // TODO: [ESP32H4] IDF-12517 + dev->intr_mem_end_addr.val = 0x44000000; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void ahb_dma_ll_rx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->in_intr[channel].ena.val |= mask; + } else { + dev->in_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->in_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *ahb_dma_ll_rx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->in_intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void ahb_dma_ll_rx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf1.dma_in_check_owner_chn = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, always enabled + */ +static inline void ahb_dma_ll_rx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.dma_indscr_burst_en_chn = enable; +} + +/** + * @brief Set RX channel burst size + */ +static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz) +{ + uint8_t burst_mode = 0; + switch (sz) { + case 4: + burst_mode = 0; // single + break; + case 16: + burst_mode = 1; // incr4 + break; + case 32: + burst_mode = 2; // incr8 + break; + case 64: + burst_mode = 3; // incr16 + break; + default: + HAL_ASSERT(false); + break; + } + dev->channel[channel].in.in_conf0.dma_in_data_burst_mode_sel_chn = burst_mode; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_conf0.dma_in_rst_chn = 1; + dev->channel[channel].in.in_conf0.dma_in_rst_chn = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_rx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_rx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t ahb_dma_ll_rx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.dma_infifo_cnt_chn; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t ahb_dma_ll_rx_pop_data(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_pop.dma_infifo_pop_chn = 1; + return dev->channel[channel].in.in_pop.dma_infifo_rdata_chn; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].in.in_link_addr.dma_inlink_addr_chn = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_start(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.dma_inlink_start_chn = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_stop(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.dma_inlink_stop_chn = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_restart(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.dma_inlink_restart_chn = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void ahb_dma_ll_rx_enable_auto_return(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_link.dma_inlink_auto_ret_chn = enable; +} + +/** + * @brief Check if DMA RX descriptor FSM is in IDLE state + */ +static inline bool ahb_dma_ll_rx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_link.dma_inlink_park_chn; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_success_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_suc_eof_des_addr.val; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_error_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_err_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched RX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_dscr.val; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].in.in_pri.dma_rx_pri_chn = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + dev->channel[channel].in.in_peri_sel.dma_peri_in_sel_chn = periph_id; + dev->channel[channel].in.in_conf0.dma_mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M); +} + +/** + * @brief Disconnect DMA RX channel from peripheral + */ +static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_peri_sel.dma_peri_in_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID; + dev->channel[channel].in.in_conf0.dma_mem_trans_en_chn = false; +} + +/** + * @brief Whether to enable the ETM subsystem for RX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.dma_in_etm_en_chn = enable; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void ahb_dma_ll_tx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->out_intr[channel].ena.val |= mask; + } else { + dev->out_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->out_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *ahb_dma_ll_tx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->out_intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void ahb_dma_ll_tx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf1.dma_out_check_owner_chn = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, always enabled + */ +static inline void ahb_dma_ll_tx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.dma_outdscr_burst_en_chn = enable; +} + +/** + * @brief Set TX channel burst size + */ +static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz) +{ + uint8_t burst_mode = 0; + switch (sz) { + case 4: + burst_mode = 0; // single + break; + case 16: + burst_mode = 1; // incr4 + break; + case 32: + burst_mode = 2; // incr8 + break; + case 64: + burst_mode = 3; // incr16 + break; + default: + HAL_ASSERT(false); + break; + } + dev->channel[channel].out.out_conf0.dma_out_data_burst_mode_sel_chn = burst_mode; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void ahb_dma_ll_tx_set_eof_mode(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + dev->channel[channel].out.out_conf0.dma_out_eof_mode_chn = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void ahb_dma_ll_tx_enable_auto_write_back(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.dma_out_auto_wrback_chn = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_conf0.dma_out_rst_chn = 1; + dev->channel[channel].out.out_conf0.dma_out_rst_chn = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_tx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_tx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t ahb_dma_ll_tx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.dma_outfifo_cnt_chn; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void ahb_dma_ll_tx_push_data(ahb_dma_dev_t *dev, uint32_t channel, uint32_t data) +{ + dev->channel[channel].out.out_push.dma_outfifo_wdata_chn = data; + dev->channel[channel].out.out_push.dma_outfifo_push_chn = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].out.out_link_addr.dma_outlink_addr_chn = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_start(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.dma_outlink_start_chn = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_stop(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.dma_outlink_stop_chn = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_restart(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.dma_outlink_restart_chn = 1; +} + +/** + * @brief Check if DMA TX descriptor FSM is in IDLE state + */ +static inline bool ahb_dma_ll_tx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_link.dma_outlink_park_chn; +} + +/** + * @brief Get TX EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_tx_get_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched TX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_tx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_dscr.val; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].out.out_pri.dma_tx_pri_chn = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + (void)periph; + dev->channel[channel].out.out_peri_sel.dma_peri_out_sel_chn = periph_id; +} + +/** + * @brief Disconnect DMA TX channel from peripheral + */ +static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_peri_sel.dma_peri_out_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID; +} + +/** + * @brief Whether to enable the ETM subsystem for TX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.dma_out_etm_en_chn = enable; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/gdma_ll.h b/components/hal/esp32h4/include/hal/gdma_ll.h new file mode 100644 index 0000000000..5c7ca2ad77 --- /dev/null +++ b/components/hal/esp32h4/include/hal/gdma_ll.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/pcr_struct.h" +#include "hal/ahb_dma_ll.h" +#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for the DMA module + */ +static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.gdma_conf.gdma_clk_en = enable; +} + +/** + * @brief Reset the DMA module + */ +static inline void gdma_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.gdma_conf.gdma_rst_en = 1; + PCR.gdma_conf.gdma_rst_en = 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/apm_hal.h b/components/hal/include/hal/apm_hal.h index 2e1c64178f..23714f3f62 100644 --- a/components/hal/include/hal/apm_hal.h +++ b/components/hal/include/hal/apm_hal.h @@ -251,6 +251,12 @@ int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path); #endif //CONFIG_IDF_TARGET_ESP32P4 #elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOC_APM_SUPPORTED + +#if CONFIG_IDF_TARGET_ESP32H4 +#include "soc/hp_apm_reg.h" +#define apm_hal_apm_ctrl_filter_enable_all(en) \ + REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); +#else #include "soc/hp_apm_reg.h" #include "soc/lp_apm_reg.h" #include "soc/lp_apm0_reg.h" @@ -259,9 +265,10 @@ int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path); REG_WRITE(LP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \ REG_WRITE(LP_APM0_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \ REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); - #endif +#endif //SOC_APM_CTRL_FILTER_SUPPORTED + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c2/gdma_periph.c b/components/soc/esp32c2/gdma_periph.c index 3fd3493cbd..3cd6ee7e07 100644 --- a/components/soc/esp32c2/gdma_periph.c +++ b/components/soc/esp32c2/gdma_periph.c @@ -9,7 +9,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_CH0_INTR_SOURCE, diff --git a/components/soc/esp32c3/gdma_periph.c b/components/soc/esp32c3/gdma_periph.c index 95f6334112..97ae5b868f 100644 --- a/components/soc/esp32c3/gdma_periph.c +++ b/components/soc/esp32c3/gdma_periph.c @@ -9,7 +9,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_CH0_INTR_SOURCE, diff --git a/components/soc/esp32c5/gdma_periph.c b/components/soc/esp32c5/gdma_periph.c index 7fae53a02e..1d9f4aa808 100644 --- a/components/soc/esp32c5/gdma_periph.c +++ b/components/soc/esp32c5/gdma_periph.c @@ -10,7 +10,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, diff --git a/components/soc/esp32c6/gdma_periph.c b/components/soc/esp32c6/gdma_periph.c index ca0e57f25a..854c5071d1 100644 --- a/components/soc/esp32c6/gdma_periph.c +++ b/components/soc/esp32c6/gdma_periph.c @@ -10,7 +10,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, diff --git a/components/soc/esp32c61/gdma_periph.c b/components/soc/esp32c61/gdma_periph.c index 3710071000..57f237677f 100644 --- a/components/soc/esp32c61/gdma_periph.c +++ b/components/soc/esp32c61/gdma_periph.c @@ -10,7 +10,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, diff --git a/components/soc/esp32h2/gdma_periph.c b/components/soc/esp32h2/gdma_periph.c index 9e6cc78c86..71365cd0f7 100644 --- a/components/soc/esp32h2/gdma_periph.c +++ b/components/soc/esp32h2/gdma_periph.c @@ -10,7 +10,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, diff --git a/components/soc/esp32h21/gdma_periph.c b/components/soc/esp32h21/gdma_periph.c index 720fa30370..d33d1cda5e 100644 --- a/components/soc/esp32h21/gdma_periph.c +++ b/components/soc/esp32h21/gdma_periph.c @@ -10,7 +10,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, diff --git a/components/soc/esp32h4/gdma_periph.c b/components/soc/esp32h4/gdma_periph.c new file mode 100644 index 0000000000..38ba63f7b2 --- /dev/null +++ b/components/soc/esp32h4/gdma_periph.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" +#include "soc/ahb_dma_reg.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE, + }, + [3] = { + .rx_irq_id = ETS_DMA_IN_CH3_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH3_INTR_SOURCE, + }, + [4] = { + .rx_irq_id = ETS_DMA_IN_CH4_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH4_INTR_SOURCE, + }, + } + } + } +}; diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index fbe5352698..86de4dcd6d 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -7,10 +7,22 @@ config SOC_UART_SUPPORTED bool default y +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_AHB_GDMA_SUPPORTED + bool + default y + config SOC_GPTIMER_SUPPORTED bool default y +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y @@ -135,6 +147,26 @@ config SOC_CPU_HAS_LOCKUP_RESET bool default y +config SOC_DMA_CAN_ACCESS_FLASH + bool + default y + +config SOC_AHB_GDMA_VERSION + int + default 2 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 5 + +config SOC_AHB_GDMA_SUPPORT_PSRAM + bool + default y + config SOC_GPIO_PORT int default 1 @@ -367,6 +399,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128 bool default y +config SOC_APM_CTRL_FILTER_SUPPORTED + bool + default y + config SOC_UART_NUM int default 2 diff --git a/components/soc/esp32h4/include/soc/gdma_channel.h b/components/soc/esp32h4/include/soc/gdma_channel.h index 1cfa7a9fcb..57324e850d 100644 --- a/components/soc/esp32h4/include/soc/gdma_channel.h +++ b/components/soc/esp32h4/include/soc/gdma_channel.h @@ -3,3 +3,34 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +#pragma once + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI3 (0) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (1) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_AES0 (4) +#define SOC_GDMA_TRIG_PERIPH_ASRC0 (5) +#define SOC_GDMA_TRIG_PERIPH_ASRC1 (6) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) +#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9) + +// On which system bus is the DMA instance of the peripheral connection mounted +#define SOC_GDMA_BUS_ANY (-1) +#define SOC_GDMA_BUS_AHB (0) + +#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY +#define SOC_GDMA_TRIG_PERIPH_SPI3_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_ASRC0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_ASRC1_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 37bb69e9d5..a9d0b6e918 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -29,8 +29,8 @@ // #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12395 big change!! // #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12401 #define SOC_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12398 -// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12382 -// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12382 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12338 // #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380 @@ -39,7 +39,7 @@ // #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347 // #define SOC_BT_SUPPORTED 1 // #define SOC_IEEE802154_SUPPORTED 1 -// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32H4] IDF-12382 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12396 // #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12404 // #define SOC_SUPPORTS_SECURE_DL_MODE 1 @@ -176,11 +176,16 @@ See TRM DS chapter for more details */ // #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) +/*-------------------------- DMA Common CAPS ----------------------------------------*/ +#define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */ + /*-------------------------- GDMA CAPS -------------------------------------*/ -// #define SOC_AHB_GDMA_VERSION 1U -// #define SOC_GDMA_NUM_GROUPS_MAX 1U -// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 4 -// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_AHB_GDMA_VERSION 2 +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 5 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383 +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12384 +#define SOC_AHB_GDMA_SUPPORT_PSRAM 1 /*-------------------------- ETM CAPS --------------------------------------*/ // #define SOC_ETM_GROUPS 1U // Number of ETM groups @@ -470,6 +475,9 @@ #define SOC_FLASH_ENCRYPTION_XTS_AES 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +/*-------------------------- APM CAPS ----------------------------------------*/ +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ + /*------------------------ Anti DPA (Security) CAPS --------------------------*/ // #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld index fe40c03db8..30eb4fa702 100644 --- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld @@ -24,7 +24,7 @@ PROVIDE ( LEDC = 0x6001B000 ); PROVIDE ( TWAI0 = 0x6001C000 ); PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 ); PROVIDE ( RMT = 0x6001E000 ); -PROVIDE ( GDMA = 0x6001F000 ); +PROVIDE ( AHB_DMA = 0x6001F000 ); PROVIDE ( PAU = 0x60020000 ); PROVIDE ( SOC_ETM = 0x60021000 ); PROVIDE ( ADC = 0x60022000 ); diff --git a/components/soc/esp32h4/register/soc/ahb_dma_struct.h b/components/soc/esp32h4/register/soc/ahb_dma_struct.h index 70c66df72c..9660c08b45 100644 --- a/components/soc/esp32h4/register/soc/ahb_dma_struct.h +++ b/components/soc/esp32h4/register/soc/ahb_dma_struct.h @@ -1326,248 +1326,91 @@ typedef union { uint32_t val; } ahb_dma_out_peri_sel_chn_reg_t; +typedef struct { + volatile ahb_dma_in_int_raw_chn_reg_t raw; + volatile ahb_dma_in_int_st_chn_reg_t st; + volatile ahb_dma_in_int_ena_chn_reg_t ena; + volatile ahb_dma_in_int_clr_chn_reg_t clr; +} ahb_dma_in_int_chn_reg_t; typedef struct { - volatile ahb_dma_in_int_raw_chn_reg_t dma_in_int_raw_ch0; - volatile ahb_dma_in_int_st_chn_reg_t dma_in_int_st_ch0; - volatile ahb_dma_in_int_ena_chn_reg_t dma_in_int_ena_ch0; - volatile ahb_dma_in_int_clr_chn_reg_t dma_in_int_clr_ch0; - volatile ahb_dma_in_int_raw_chn_reg_t dma_in_int_raw_ch1; - volatile ahb_dma_in_int_st_chn_reg_t dma_in_int_st_ch1; - volatile ahb_dma_in_int_ena_chn_reg_t dma_in_int_ena_ch1; - volatile ahb_dma_in_int_clr_chn_reg_t dma_in_int_clr_ch1; - volatile ahb_dma_in_int_raw_chn_reg_t dma_in_int_raw_ch2; - volatile ahb_dma_in_int_st_chn_reg_t dma_in_int_st_ch2; - volatile ahb_dma_in_int_ena_chn_reg_t dma_in_int_ena_ch2; - volatile ahb_dma_in_int_clr_chn_reg_t dma_in_int_clr_ch2; - volatile ahb_dma_in_int_raw_chn_reg_t dma_in_int_raw_ch3; - volatile ahb_dma_in_int_st_chn_reg_t dma_in_int_st_ch3; - volatile ahb_dma_in_int_ena_chn_reg_t dma_in_int_ena_ch3; - volatile ahb_dma_in_int_clr_chn_reg_t dma_in_int_clr_ch3; - volatile ahb_dma_in_int_raw_chn_reg_t dma_in_int_raw_ch4; - volatile ahb_dma_in_int_st_chn_reg_t dma_in_int_st_ch4; - volatile ahb_dma_in_int_ena_chn_reg_t dma_in_int_ena_ch4; - volatile ahb_dma_in_int_clr_chn_reg_t dma_in_int_clr_ch4; - volatile ahb_dma_out_int_raw_chn_reg_t dma_out_int_raw_ch0; - volatile ahb_dma_out_int_st_chn_reg_t dma_out_int_st_ch0; - volatile ahb_dma_out_int_ena_chn_reg_t dma_out_int_ena_ch0; - volatile ahb_dma_out_int_clr_chn_reg_t dma_out_int_clr_ch0; - volatile ahb_dma_out_int_raw_chn_reg_t dma_out_int_raw_ch1; - volatile ahb_dma_out_int_st_chn_reg_t dma_out_int_st_ch1; - volatile ahb_dma_out_int_ena_chn_reg_t dma_out_int_ena_ch1; - volatile ahb_dma_out_int_clr_chn_reg_t dma_out_int_clr_ch1; - volatile ahb_dma_out_int_raw_chn_reg_t dma_out_int_raw_ch2; - volatile ahb_dma_out_int_st_chn_reg_t dma_out_int_st_ch2; - volatile ahb_dma_out_int_ena_chn_reg_t dma_out_int_ena_ch2; - volatile ahb_dma_out_int_clr_chn_reg_t dma_out_int_clr_ch2; - volatile ahb_dma_out_int_raw_chn_reg_t dma_out_int_raw_ch3; - volatile ahb_dma_out_int_st_chn_reg_t dma_out_int_st_ch3; - volatile ahb_dma_out_int_ena_chn_reg_t dma_out_int_ena_ch3; - volatile ahb_dma_out_int_clr_chn_reg_t dma_out_int_clr_ch3; - volatile ahb_dma_out_int_raw_chn_reg_t dma_out_int_raw_ch4; - volatile ahb_dma_out_int_st_chn_reg_t dma_out_int_st_ch4; - volatile ahb_dma_out_int_ena_chn_reg_t dma_out_int_ena_ch4; - volatile ahb_dma_out_int_clr_chn_reg_t dma_out_int_clr_ch4; - volatile ahb_dma_ahb_test_reg_t dma_ahb_test; - volatile ahb_dma_misc_conf_reg_t dma_misc_conf; - volatile ahb_dma_date_reg_t dma_date; - uint32_t reserved_0ac[21]; - volatile ahb_dma_in_conf0_chn_reg_t dma_in_conf0_ch0; - volatile ahb_dma_in_conf1_chn_reg_t dma_in_conf1_ch0; - volatile ahb_dma_infifo_status_chn_reg_t dma_infifo_status_ch0; - volatile ahb_dma_in_pop_chn_reg_t dma_in_pop_ch0; - volatile ahb_dma_in_link_chn_reg_t dma_in_link_ch0; - volatile ahb_dma_in_link_addr_chn_reg_t dma_in_link_addr_ch0; - volatile ahb_dma_in_state_chn_reg_t dma_in_state_ch0; - volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t dma_in_suc_eof_des_addr_ch0; - volatile ahb_dma_in_err_eof_des_addr_chn_reg_t dma_in_err_eof_des_addr_ch0; - volatile ahb_dma_in_done_des_addr_chn_reg_t dma_in_done_des_addr_ch0; - volatile ahb_dma_in_dscr_chn_reg_t dma_in_dscr_ch0; - volatile ahb_dma_in_dscr_bf0_chn_reg_t dma_in_dscr_bf0_ch0; - volatile ahb_dma_in_dscr_bf1_chn_reg_t dma_in_dscr_bf1_ch0; - volatile ahb_dma_in_pri_chn_reg_t dma_in_pri_ch0; - volatile ahb_dma_in_peri_sel_chn_reg_t dma_in_peri_sel_ch0; - volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t dma_rx_ch_arb_weigh_ch0; - volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t dma_rx_arb_weigh_opt_dir_ch0; - uint32_t reserved_144[15]; - volatile ahb_dma_out_conf0_ch0_reg_t dma_out_conf0_ch0; - volatile ahb_dma_out_conf1_chn_reg_t dma_out_conf1_ch0; - volatile ahb_dma_outfifo_status_chn_reg_t dma_outfifo_status_ch0; - volatile ahb_dma_out_push_chn_reg_t dma_out_push_ch0; - volatile ahb_dma_out_link_chn_reg_t dma_out_link_ch0; - volatile ahb_dma_out_link_addr_chn_reg_t dma_out_link_addr_ch0; - volatile ahb_dma_out_state_chn_reg_t dma_out_state_ch0; - volatile ahb_dma_out_eof_des_addr_chn_reg_t dma_out_eof_des_addr_ch0; - volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t dma_out_eof_bfr_des_addr_ch0; - volatile ahb_dma_out_done_des_addr_chn_reg_t dma_out_done_des_addr_ch0; - volatile ahb_dma_out_dscr_chn_reg_t dma_out_dscr_ch0; - volatile ahb_dma_out_dscr_bf0_chn_reg_t dma_out_dscr_bf0_ch0; - volatile ahb_dma_out_dscr_bf1_chn_reg_t dma_out_dscr_bf1_ch0; - volatile ahb_dma_out_pri_chn_reg_t dma_out_pri_ch0; - volatile ahb_dma_out_peri_sel_chn_reg_t dma_out_peri_sel_ch0; - volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t dma_tx_ch_arb_weigh_ch0; - volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t dma_tx_arb_weigh_opt_dir_ch0; - uint32_t reserved_1c4[15]; - volatile ahb_dma_in_conf0_chn_reg_t dma_in_conf0_ch1; - volatile ahb_dma_in_conf1_chn_reg_t dma_in_conf1_ch1; - volatile ahb_dma_infifo_status_chn_reg_t dma_infifo_status_ch1; - volatile ahb_dma_in_pop_chn_reg_t dma_in_pop_ch1; - volatile ahb_dma_in_link_chn_reg_t dma_in_link_ch1; - volatile ahb_dma_in_link_addr_chn_reg_t dma_in_link_addr_ch1; - volatile ahb_dma_in_state_chn_reg_t dma_in_state_ch1; - volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t dma_in_suc_eof_des_addr_ch1; - volatile ahb_dma_in_err_eof_des_addr_chn_reg_t dma_in_err_eof_des_addr_ch1; - volatile ahb_dma_in_done_des_addr_chn_reg_t dma_in_done_des_addr_ch1; - volatile ahb_dma_in_dscr_chn_reg_t dma_in_dscr_ch1; - volatile ahb_dma_in_dscr_bf0_chn_reg_t dma_in_dscr_bf0_ch1; - volatile ahb_dma_in_dscr_bf1_chn_reg_t dma_in_dscr_bf1_ch1; - volatile ahb_dma_in_pri_chn_reg_t dma_in_pri_ch1; - volatile ahb_dma_in_peri_sel_chn_reg_t dma_in_peri_sel_ch1; - volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t dma_rx_ch_arb_weigh_ch1; - volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t dma_rx_arb_weigh_opt_dir_ch1; - uint32_t reserved_244[15]; - volatile ahb_dma_out_conf0_chn_reg_t dma_out_conf0_ch1; - volatile ahb_dma_out_conf1_chn_reg_t dma_out_conf1_ch1; - volatile ahb_dma_outfifo_status_chn_reg_t dma_outfifo_status_ch1; - volatile ahb_dma_out_push_chn_reg_t dma_out_push_ch1; - volatile ahb_dma_out_link_chn_reg_t dma_out_link_ch1; - volatile ahb_dma_out_link_addr_chn_reg_t dma_out_link_addr_ch1; - volatile ahb_dma_out_state_chn_reg_t dma_out_state_ch1; - volatile ahb_dma_out_eof_des_addr_chn_reg_t dma_out_eof_des_addr_ch1; - volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t dma_out_eof_bfr_des_addr_ch1; - volatile ahb_dma_out_done_des_addr_chn_reg_t dma_out_done_des_addr_ch1; - volatile ahb_dma_out_dscr_chn_reg_t dma_out_dscr_ch1; - volatile ahb_dma_out_dscr_bf0_chn_reg_t dma_out_dscr_bf0_ch1; - volatile ahb_dma_out_dscr_bf1_chn_reg_t dma_out_dscr_bf1_ch1; - volatile ahb_dma_out_pri_chn_reg_t dma_out_pri_ch1; - volatile ahb_dma_out_peri_sel_chn_reg_t dma_out_peri_sel_ch1; - volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t dma_tx_ch_arb_weigh_ch1; - volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t dma_tx_arb_weigh_opt_dir_ch1; - uint32_t reserved_2c4[15]; - volatile ahb_dma_in_conf0_chn_reg_t dma_in_conf0_ch2; - volatile ahb_dma_in_conf1_chn_reg_t dma_in_conf1_ch2; - volatile ahb_dma_infifo_status_chn_reg_t dma_infifo_status_ch2; - volatile ahb_dma_in_pop_chn_reg_t dma_in_pop_ch2; - volatile ahb_dma_in_link_chn_reg_t dma_in_link_ch2; - volatile ahb_dma_in_link_addr_chn_reg_t dma_in_link_addr_ch2; - volatile ahb_dma_in_state_chn_reg_t dma_in_state_ch2; - volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t dma_in_suc_eof_des_addr_ch2; - volatile ahb_dma_in_err_eof_des_addr_chn_reg_t dma_in_err_eof_des_addr_ch2; - volatile ahb_dma_in_done_des_addr_chn_reg_t dma_in_done_des_addr_ch2; - volatile ahb_dma_in_dscr_chn_reg_t dma_in_dscr_ch2; - volatile ahb_dma_in_dscr_bf0_chn_reg_t dma_in_dscr_bf0_ch2; - volatile ahb_dma_in_dscr_bf1_chn_reg_t dma_in_dscr_bf1_ch2; - volatile ahb_dma_in_pri_chn_reg_t dma_in_pri_ch2; - volatile ahb_dma_in_peri_sel_chn_reg_t dma_in_peri_sel_ch2; - volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t dma_rx_ch_arb_weigh_ch2; - volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t dma_rx_arb_weigh_opt_dir_ch2; - uint32_t reserved_344[15]; - volatile ahb_dma_out_conf0_chn_reg_t dma_out_conf0_ch2; - volatile ahb_dma_out_conf1_chn_reg_t dma_out_conf1_ch2; - volatile ahb_dma_outfifo_status_chn_reg_t dma_outfifo_status_ch2; - volatile ahb_dma_out_push_chn_reg_t dma_out_push_ch2; - volatile ahb_dma_out_link_chn_reg_t dma_out_link_ch2; - volatile ahb_dma_out_link_addr_chn_reg_t dma_out_link_addr_ch2; - volatile ahb_dma_out_state_chn_reg_t dma_out_state_ch2; - volatile ahb_dma_out_eof_des_addr_chn_reg_t dma_out_eof_des_addr_ch2; - volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t dma_out_eof_bfr_des_addr_ch2; - volatile ahb_dma_out_done_des_addr_chn_reg_t dma_out_done_des_addr_ch2; - volatile ahb_dma_out_dscr_chn_reg_t dma_out_dscr_ch2; - volatile ahb_dma_out_dscr_bf0_chn_reg_t dma_out_dscr_bf0_ch2; - volatile ahb_dma_out_dscr_bf1_chn_reg_t dma_out_dscr_bf1_ch2; - volatile ahb_dma_out_pri_chn_reg_t dma_out_pri_ch2; - volatile ahb_dma_out_peri_sel_chn_reg_t dma_out_peri_sel_ch2; - volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t dma_tx_ch_arb_weigh_ch2; - volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t dma_tx_arb_weigh_opt_dir_ch2; - uint32_t reserved_3c4[15]; - volatile ahb_dma_in_conf0_chn_reg_t dma_in_conf0_ch3; - volatile ahb_dma_in_conf1_chn_reg_t dma_in_conf1_ch3; - volatile ahb_dma_infifo_status_chn_reg_t dma_infifo_status_ch3; - volatile ahb_dma_in_pop_chn_reg_t dma_in_pop_ch3; - volatile ahb_dma_in_link_chn_reg_t dma_in_link_ch3; - volatile ahb_dma_in_link_addr_chn_reg_t dma_in_link_addr_ch3; - volatile ahb_dma_in_state_chn_reg_t dma_in_state_ch3; - volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t dma_in_suc_eof_des_addr_ch3; - volatile ahb_dma_in_err_eof_des_addr_chn_reg_t dma_in_err_eof_des_addr_ch3; - volatile ahb_dma_in_done_des_addr_chn_reg_t dma_in_done_des_addr_ch3; - volatile ahb_dma_in_dscr_chn_reg_t dma_in_dscr_ch3; - volatile ahb_dma_in_dscr_bf0_chn_reg_t dma_in_dscr_bf0_ch3; - volatile ahb_dma_in_dscr_bf1_chn_reg_t dma_in_dscr_bf1_ch3; - volatile ahb_dma_in_pri_chn_reg_t dma_in_pri_ch3; - volatile ahb_dma_in_peri_sel_chn_reg_t dma_in_peri_sel_ch3; - volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t dma_rx_ch_arb_weigh_ch3; - volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t dma_rx_arb_weigh_opt_dir_ch3; - uint32_t reserved_444[15]; - volatile ahb_dma_out_conf0_chn_reg_t dma_out_conf0_ch3; - volatile ahb_dma_out_conf1_chn_reg_t dma_out_conf1_ch3; - volatile ahb_dma_outfifo_status_chn_reg_t dma_outfifo_status_ch3; - volatile ahb_dma_out_push_chn_reg_t dma_out_push_ch3; - volatile ahb_dma_out_link_chn_reg_t dma_out_link_ch3; - volatile ahb_dma_out_link_addr_chn_reg_t dma_out_link_addr_ch3; - volatile ahb_dma_out_state_chn_reg_t dma_out_state_ch3; - volatile ahb_dma_out_eof_des_addr_chn_reg_t dma_out_eof_des_addr_ch3; - volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t dma_out_eof_bfr_des_addr_ch3; - volatile ahb_dma_out_done_des_addr_chn_reg_t dma_out_done_des_addr_ch3; - volatile ahb_dma_out_dscr_chn_reg_t dma_out_dscr_ch3; - volatile ahb_dma_out_dscr_bf0_chn_reg_t dma_out_dscr_bf0_ch3; - volatile ahb_dma_out_dscr_bf1_chn_reg_t dma_out_dscr_bf1_ch3; - volatile ahb_dma_out_pri_chn_reg_t dma_out_pri_ch3; - volatile ahb_dma_out_peri_sel_chn_reg_t dma_out_peri_sel_ch3; - volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t dma_tx_ch_arb_weigh_ch3; - volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t dma_tx_arb_weigh_opt_dir_ch3; - uint32_t reserved_4c4[15]; - volatile ahb_dma_in_conf0_chn_reg_t dma_in_conf0_ch4; - volatile ahb_dma_in_conf1_chn_reg_t dma_in_conf1_ch4; - volatile ahb_dma_infifo_status_chn_reg_t dma_infifo_status_ch4; - volatile ahb_dma_in_pop_chn_reg_t dma_in_pop_ch4; - volatile ahb_dma_in_link_chn_reg_t dma_in_link_ch4; - volatile ahb_dma_in_link_addr_chn_reg_t dma_in_link_addr_ch4; - volatile ahb_dma_in_state_chn_reg_t dma_in_state_ch4; - volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t dma_in_suc_eof_des_addr_ch4; - volatile ahb_dma_in_err_eof_des_addr_chn_reg_t dma_in_err_eof_des_addr_ch4; - volatile ahb_dma_in_done_des_addr_chn_reg_t dma_in_done_des_addr_ch4; - volatile ahb_dma_in_dscr_chn_reg_t dma_in_dscr_ch4; - volatile ahb_dma_in_dscr_bf0_chn_reg_t dma_in_dscr_bf0_ch4; - volatile ahb_dma_in_dscr_bf1_chn_reg_t dma_in_dscr_bf1_ch4; - volatile ahb_dma_in_pri_chn_reg_t dma_in_pri_ch4; - volatile ahb_dma_in_peri_sel_chn_reg_t dma_in_peri_sel_ch4; - volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t dma_rx_ch_arb_weigh_ch4; - volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t dma_rx_arb_weigh_opt_dir_ch4; - uint32_t reserved_544[15]; - volatile ahb_dma_out_conf0_chn_reg_t dma_out_conf0_ch4; - volatile ahb_dma_out_conf1_chn_reg_t dma_out_conf1_ch4; - volatile ahb_dma_outfifo_status_chn_reg_t dma_outfifo_status_ch4; - volatile ahb_dma_out_push_chn_reg_t dma_out_push_ch4; - volatile ahb_dma_out_link_chn_reg_t dma_out_link_ch4; - volatile ahb_dma_out_link_addr_chn_reg_t dma_out_link_addr_ch4; - volatile ahb_dma_out_state_chn_reg_t dma_out_state_ch4; - volatile ahb_dma_out_eof_des_addr_chn_reg_t dma_out_eof_des_addr_ch4; - volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t dma_out_eof_bfr_des_addr_ch4; - volatile ahb_dma_out_done_des_addr_chn_reg_t dma_out_done_des_addr_ch4; - volatile ahb_dma_out_dscr_chn_reg_t dma_out_dscr_ch4; - volatile ahb_dma_out_dscr_bf0_chn_reg_t dma_out_dscr_bf0_ch4; - volatile ahb_dma_out_dscr_bf1_chn_reg_t dma_out_dscr_bf1_ch4; - volatile ahb_dma_out_pri_chn_reg_t dma_out_pri_ch4; - volatile ahb_dma_out_peri_sel_chn_reg_t dma_out_peri_sel_ch4; - volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t dma_tx_ch_arb_weigh_ch4; - volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t dma_tx_arb_weigh_opt_dir_ch4; - uint32_t reserved_5c4[15]; - volatile ahb_dma_intr_mem_start_addr_reg_t dma_intr_mem_start_addr; - volatile ahb_dma_intr_mem_end_addr_reg_t dma_intr_mem_end_addr; - volatile ahb_dma_arb_timeout_reg_t dma_arb_timeout; - uint32_t reserved_60c; - volatile ahb_dma_weight_en_reg_t dma_weight_en; - uint32_t reserved_614; - volatile ahb_dma_module_clk_en_reg_t dma_module_clk_en; - uint32_t reserved_61c; - volatile ahb_dma_ahbinf_resp_err_status0_reg_t dma_ahbinf_resp_err_status0; - volatile ahb_dma_ahbinf_resp_err_status1_reg_t dma_ahbinf_resp_err_status1; -} ahb_dev_t; + volatile ahb_dma_out_int_raw_chn_reg_t raw; + volatile ahb_dma_out_int_st_chn_reg_t st; + volatile ahb_dma_out_int_ena_chn_reg_t ena; + volatile ahb_dma_out_int_clr_chn_reg_t clr; +} ahb_dma_out_int_chn_reg_t; -extern ahb_dev_t AHB_DMA; +typedef struct { + volatile ahb_dma_in_conf0_chn_reg_t in_conf0; + volatile ahb_dma_in_conf1_chn_reg_t in_conf1; + volatile ahb_dma_infifo_status_chn_reg_t infifo_status; + volatile ahb_dma_in_pop_chn_reg_t in_pop; + volatile ahb_dma_in_link_chn_reg_t in_link; + volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr; + volatile ahb_dma_in_state_chn_reg_t in_state; + volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; + volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; + volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr; + volatile ahb_dma_in_dscr_chn_reg_t in_dscr; + volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0; + volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1; + volatile ahb_dma_in_pri_chn_reg_t in_pri; + volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel; + volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh; + volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt; +} ahb_dma_in_chn_reg_t; + +typedef struct { + volatile ahb_dma_out_conf0_chn_reg_t out_conf0; + volatile ahb_dma_out_conf1_chn_reg_t out_conf1; + volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status; + volatile ahb_dma_out_push_chn_reg_t out_push; + volatile ahb_dma_out_link_chn_reg_t out_link; + volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr; + volatile ahb_dma_out_state_chn_reg_t out_state; + volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr; + volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; + volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr; + volatile ahb_dma_out_dscr_chn_reg_t out_dscr; + volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0; + volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1; + volatile ahb_dma_out_pri_chn_reg_t out_pri; + volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel; + volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh; + volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt; +} ahb_dma_out_chn_reg_t; + +typedef struct { + volatile ahb_dma_in_chn_reg_t in; + uint32_t reserved_in[15]; + volatile ahb_dma_out_chn_reg_t out; + uint32_t reserved_out[15]; +} ahb_dma_chn_reg_t; + +typedef struct { + volatile ahb_dma_in_int_chn_reg_t in_intr[5]; + volatile ahb_dma_out_int_chn_reg_t out_intr[5]; + volatile ahb_dma_ahb_test_reg_t ahb_test; + volatile ahb_dma_misc_conf_reg_t misc_conf; + volatile ahb_dma_date_reg_t date; + uint32_t reserved_0ac[21]; + volatile ahb_dma_chn_reg_t channel[5]; + volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr; + volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr; + volatile ahb_dma_arb_timeout_reg_t arb_timeout; + uint32_t reserved_60c; + volatile ahb_dma_weight_en_reg_t weight_en; + uint32_t reserved_614; + volatile ahb_dma_module_clk_en_reg_t module_clk_en; + uint32_t reserved_61c; + volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0; + volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1; +} ahb_dma_dev_t; + +extern ahb_dma_dev_t AHB_DMA; #ifndef __cplusplus -_Static_assert(sizeof(ahb_dev_t) == 0x628, "Invalid size of ahb_dev_t structure"); +_Static_assert(sizeof(ahb_dma_dev_t) == 0x628, "Invalid size of ahb_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h4/register/soc/hp_apm_reg.h b/components/soc/esp32h4/register/soc/hp_apm_reg.h index da5ca675bf..569d70c996 100644 --- a/components/soc/esp32h4/register/soc/hp_apm_reg.h +++ b/components/soc/esp32h4/register/soc/hp_apm_reg.h @@ -14,7 +14,7 @@ extern "C" { /** HP_APM_REGION_FILTER_EN_REG register * Region filter enable register */ -#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_BASE + 0x0) +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) /** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; * Configure bit $n (0-15) to enable region $n. * 0: disable @@ -28,7 +28,7 @@ extern "C" { /** HP_APM_REGION0_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_BASE + 0x4) +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) /** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 0. */ @@ -40,7 +40,7 @@ extern "C" { /** HP_APM_REGION0_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_BASE + 0x8) +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) /** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 0. */ @@ -52,7 +52,7 @@ extern "C" { /** HP_APM_REGION0_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION0_ATTR_REG (DR_REG_HP_BASE + 0xc) +#define HP_APM_REGION0_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) /** HP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 0. */ @@ -127,7 +127,7 @@ extern "C" { /** HP_APM_REGION1_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_BASE + 0x10) +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) /** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 1. */ @@ -139,7 +139,7 @@ extern "C" { /** HP_APM_REGION1_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_BASE + 0x14) +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) /** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 1. */ @@ -151,7 +151,7 @@ extern "C" { /** HP_APM_REGION1_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION1_ATTR_REG (DR_REG_HP_BASE + 0x18) +#define HP_APM_REGION1_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) /** HP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 1. */ @@ -226,7 +226,7 @@ extern "C" { /** HP_APM_REGION2_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_BASE + 0x1c) +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) /** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 2. */ @@ -238,7 +238,7 @@ extern "C" { /** HP_APM_REGION2_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_BASE + 0x20) +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) /** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 2. */ @@ -250,7 +250,7 @@ extern "C" { /** HP_APM_REGION2_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION2_ATTR_REG (DR_REG_HP_BASE + 0x24) +#define HP_APM_REGION2_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) /** HP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 2. */ @@ -325,7 +325,7 @@ extern "C" { /** HP_APM_REGION3_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_BASE + 0x28) +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) /** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 3. */ @@ -337,7 +337,7 @@ extern "C" { /** HP_APM_REGION3_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_BASE + 0x2c) +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) /** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 3. */ @@ -349,7 +349,7 @@ extern "C" { /** HP_APM_REGION3_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION3_ATTR_REG (DR_REG_HP_BASE + 0x30) +#define HP_APM_REGION3_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) /** HP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 3. */ @@ -424,7 +424,7 @@ extern "C" { /** HP_APM_REGION4_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_BASE + 0x34) +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) /** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 4. */ @@ -436,7 +436,7 @@ extern "C" { /** HP_APM_REGION4_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_BASE + 0x38) +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) /** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 4. */ @@ -448,7 +448,7 @@ extern "C" { /** HP_APM_REGION4_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION4_ATTR_REG (DR_REG_HP_BASE + 0x3c) +#define HP_APM_REGION4_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) /** HP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 4. */ @@ -523,7 +523,7 @@ extern "C" { /** HP_APM_REGION5_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_BASE + 0x40) +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) /** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 5. */ @@ -535,7 +535,7 @@ extern "C" { /** HP_APM_REGION5_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_BASE + 0x44) +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) /** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 5. */ @@ -547,7 +547,7 @@ extern "C" { /** HP_APM_REGION5_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION5_ATTR_REG (DR_REG_HP_BASE + 0x48) +#define HP_APM_REGION5_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) /** HP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 5. */ @@ -622,7 +622,7 @@ extern "C" { /** HP_APM_REGION6_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_BASE + 0x4c) +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) /** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 6. */ @@ -634,7 +634,7 @@ extern "C" { /** HP_APM_REGION6_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_BASE + 0x50) +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) /** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 6. */ @@ -646,7 +646,7 @@ extern "C" { /** HP_APM_REGION6_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION6_ATTR_REG (DR_REG_HP_BASE + 0x54) +#define HP_APM_REGION6_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) /** HP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 6. */ @@ -721,7 +721,7 @@ extern "C" { /** HP_APM_REGION7_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_BASE + 0x58) +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) /** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 7. */ @@ -733,7 +733,7 @@ extern "C" { /** HP_APM_REGION7_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_BASE + 0x5c) +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) /** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 7. */ @@ -745,7 +745,7 @@ extern "C" { /** HP_APM_REGION7_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION7_ATTR_REG (DR_REG_HP_BASE + 0x60) +#define HP_APM_REGION7_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) /** HP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 7. */ @@ -820,7 +820,7 @@ extern "C" { /** HP_APM_REGION8_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_BASE + 0x64) +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) /** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 8. */ @@ -832,7 +832,7 @@ extern "C" { /** HP_APM_REGION8_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_BASE + 0x68) +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) /** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 8. */ @@ -844,7 +844,7 @@ extern "C" { /** HP_APM_REGION8_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION8_ATTR_REG (DR_REG_HP_BASE + 0x6c) +#define HP_APM_REGION8_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) /** HP_APM_REGION8_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 8. */ @@ -919,7 +919,7 @@ extern "C" { /** HP_APM_REGION9_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_BASE + 0x70) +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) /** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 9. */ @@ -931,7 +931,7 @@ extern "C" { /** HP_APM_REGION9_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_BASE + 0x74) +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) /** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 9. */ @@ -943,7 +943,7 @@ extern "C" { /** HP_APM_REGION9_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION9_ATTR_REG (DR_REG_HP_BASE + 0x78) +#define HP_APM_REGION9_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) /** HP_APM_REGION9_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 9. */ @@ -1018,7 +1018,7 @@ extern "C" { /** HP_APM_REGION10_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_BASE + 0x7c) +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) /** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 10. */ @@ -1030,7 +1030,7 @@ extern "C" { /** HP_APM_REGION10_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_BASE + 0x80) +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) /** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 10. */ @@ -1042,7 +1042,7 @@ extern "C" { /** HP_APM_REGION10_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION10_ATTR_REG (DR_REG_HP_BASE + 0x84) +#define HP_APM_REGION10_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) /** HP_APM_REGION10_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 10. */ @@ -1117,7 +1117,7 @@ extern "C" { /** HP_APM_REGION11_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_BASE + 0x88) +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) /** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 11. */ @@ -1129,7 +1129,7 @@ extern "C" { /** HP_APM_REGION11_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_BASE + 0x8c) +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) /** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 11. */ @@ -1141,7 +1141,7 @@ extern "C" { /** HP_APM_REGION11_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION11_ATTR_REG (DR_REG_HP_BASE + 0x90) +#define HP_APM_REGION11_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) /** HP_APM_REGION11_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 11. */ @@ -1216,7 +1216,7 @@ extern "C" { /** HP_APM_REGION12_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_BASE + 0x94) +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) /** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 12. */ @@ -1228,7 +1228,7 @@ extern "C" { /** HP_APM_REGION12_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_BASE + 0x98) +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) /** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 12. */ @@ -1240,7 +1240,7 @@ extern "C" { /** HP_APM_REGION12_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION12_ATTR_REG (DR_REG_HP_BASE + 0x9c) +#define HP_APM_REGION12_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) /** HP_APM_REGION12_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 12. */ @@ -1315,7 +1315,7 @@ extern "C" { /** HP_APM_REGION13_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_BASE + 0xa0) +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) /** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 13. */ @@ -1327,7 +1327,7 @@ extern "C" { /** HP_APM_REGION13_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_BASE + 0xa4) +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) /** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 13. */ @@ -1339,7 +1339,7 @@ extern "C" { /** HP_APM_REGION13_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION13_ATTR_REG (DR_REG_HP_BASE + 0xa8) +#define HP_APM_REGION13_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) /** HP_APM_REGION13_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 13. */ @@ -1414,7 +1414,7 @@ extern "C" { /** HP_APM_REGION14_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_BASE + 0xac) +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) /** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 14. */ @@ -1426,7 +1426,7 @@ extern "C" { /** HP_APM_REGION14_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_BASE + 0xb0) +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) /** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 14. */ @@ -1438,7 +1438,7 @@ extern "C" { /** HP_APM_REGION14_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION14_ATTR_REG (DR_REG_HP_BASE + 0xb4) +#define HP_APM_REGION14_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) /** HP_APM_REGION14_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 14. */ @@ -1513,7 +1513,7 @@ extern "C" { /** HP_APM_REGION15_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_BASE + 0xb8) +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) /** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Configures start address of region 15. */ @@ -1525,7 +1525,7 @@ extern "C" { /** HP_APM_REGION15_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_BASE + 0xbc) +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) /** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * Configures end address of region 15. */ @@ -1537,7 +1537,7 @@ extern "C" { /** HP_APM_REGION15_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION15_ATTR_REG (DR_REG_HP_BASE + 0xc0) +#define HP_APM_REGION15_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) /** HP_APM_REGION15_R0_X : R/W; bitpos: [0]; default: 0; * Configures the execution authority of REE_MODE 0 in region 15. */ @@ -1612,7 +1612,7 @@ extern "C" { /** HP_APM_FUNC_CTRL_REG register * APM function control register */ -#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_BASE + 0xc4) +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) /** HP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; * PMS M0 function enable */ @@ -1652,7 +1652,7 @@ extern "C" { /** HP_APM_M0_STATUS_REG register * M0 status register */ -#define HP_APM_M0_STATUS_REG (DR_REG_HP_BASE + 0xc8) +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) /** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1666,7 +1666,7 @@ extern "C" { /** HP_APM_M0_STATUS_CLR_REG register * M0 status clear register */ -#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_BASE + 0xcc) +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) /** HP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1678,7 +1678,7 @@ extern "C" { /** HP_APM_M0_EXCEPTION_INFO0_REG register * M0 exception_info0 register */ -#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xd0) +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) /** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1704,7 +1704,7 @@ extern "C" { /** HP_APM_M0_EXCEPTION_INFO1_REG register * M0 exception_info1 register */ -#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xd4) +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) /** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1716,7 +1716,7 @@ extern "C" { /** HP_APM_M1_STATUS_REG register * M1 status register */ -#define HP_APM_M1_STATUS_REG (DR_REG_HP_BASE + 0xd8) +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) /** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1730,7 +1730,7 @@ extern "C" { /** HP_APM_M1_STATUS_CLR_REG register * M1 status clear register */ -#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_BASE + 0xdc) +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) /** HP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1742,7 +1742,7 @@ extern "C" { /** HP_APM_M1_EXCEPTION_INFO0_REG register * M1 exception_info0 register */ -#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xe0) +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) /** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1768,7 +1768,7 @@ extern "C" { /** HP_APM_M1_EXCEPTION_INFO1_REG register * M1 exception_info1 register */ -#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xe4) +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) /** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1780,7 +1780,7 @@ extern "C" { /** HP_APM_M2_STATUS_REG register * M2 status register */ -#define HP_APM_M2_STATUS_REG (DR_REG_HP_BASE + 0xe8) +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) /** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1794,7 +1794,7 @@ extern "C" { /** HP_APM_M2_STATUS_CLR_REG register * M2 status clear register */ -#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_BASE + 0xec) +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) /** HP_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1806,7 +1806,7 @@ extern "C" { /** HP_APM_M2_EXCEPTION_INFO0_REG register * M2 exception_info0 register */ -#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xf0) +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) /** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1832,7 +1832,7 @@ extern "C" { /** HP_APM_M2_EXCEPTION_INFO1_REG register * M2 exception_info1 register */ -#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xf4) +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) /** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1844,7 +1844,7 @@ extern "C" { /** HP_APM_M3_STATUS_REG register * M3 status register */ -#define HP_APM_M3_STATUS_REG (DR_REG_HP_BASE + 0xf8) +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) /** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1858,7 +1858,7 @@ extern "C" { /** HP_APM_M3_STATUS_CLR_REG register * M3 status clear register */ -#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_BASE + 0xfc) +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) /** HP_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1870,7 +1870,7 @@ extern "C" { /** HP_APM_M3_EXCEPTION_INFO0_REG register * M3 exception_info0 register */ -#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0x100) +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) /** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1896,7 +1896,7 @@ extern "C" { /** HP_APM_M3_EXCEPTION_INFO1_REG register * M3 exception_info1 register */ -#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0x104) +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) /** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1908,7 +1908,7 @@ extern "C" { /** HP_APM_M4_STATUS_REG register * M4 status register */ -#define HP_APM_M4_STATUS_REG (DR_REG_HP_BASE + 0x108) +#define HP_APM_M4_STATUS_REG (DR_REG_HP_APM_BASE + 0x108) /** HP_APM_M4_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. * bit0: 1 represents authority_exception @@ -1922,7 +1922,7 @@ extern "C" { /** HP_APM_M4_STATUS_CLR_REG register * M4 status clear register */ -#define HP_APM_M4_STATUS_CLR_REG (DR_REG_HP_BASE + 0x10c) +#define HP_APM_M4_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x10c) /** HP_APM_M4_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Configures to clear exception status. */ @@ -1934,7 +1934,7 @@ extern "C" { /** HP_APM_M4_EXCEPTION_INFO0_REG register * M4 exception_info0 register */ -#define HP_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0x110) +#define HP_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x110) /** HP_APM_M4_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Represents exception region. */ @@ -1960,7 +1960,7 @@ extern "C" { /** HP_APM_M4_EXCEPTION_INFO1_REG register * M4 exception_info1 register */ -#define HP_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0x114) +#define HP_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x114) /** HP_APM_M4_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Represents exception addr. */ @@ -1972,7 +1972,7 @@ extern "C" { /** HP_APM_INT_EN_REG register * APM interrupt enable register */ -#define HP_APM_INT_EN_REG (DR_REG_HP_BASE + 0x118) +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x118) /** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; * Configures to enable APM M0 interrupt. * 0: disable @@ -2022,7 +2022,7 @@ extern "C" { /** HP_APM_CLOCK_GATE_REG register * Clock gating register */ -#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_BASE + 0x7f8) +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x7f8) /** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: enable automatic clock gating @@ -2036,7 +2036,7 @@ extern "C" { /** HP_APM_DATE_REG register * Version control register */ -#define HP_APM_DATE_REG (DR_REG_HP_BASE + 0x7fc) +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) /** HP_APM_DATE : R/W; bitpos: [27:0]; default: 36773904; * Version control register. */ diff --git a/components/soc/esp32h4/register/soc/hp_system_reg.h b/components/soc/esp32h4/register/soc/hp_system_reg.h index d97fe095cb..2c4bd1bd95 100644 --- a/components/soc/esp32h4/register/soc/hp_system_reg.h +++ b/components/soc/esp32h4/register/soc/hp_system_reg.h @@ -54,7 +54,7 @@ extern "C" { /** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register * CPU_PERI_TIMEOUT configuration register */ -#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_BASE + 0xc) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc) /** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing CPU peripheral * register in the number of clock cycles of the clock domain. @@ -84,7 +84,7 @@ extern "C" { /** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register * CPU_PERI_TIMEOUT_ADDR register */ -#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_BASE + 0x10) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10) /** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ @@ -96,7 +96,7 @@ extern "C" { /** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register * CPU_PERI_TIMEOUT_UID register */ -#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_BASE + 0x14) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14) /** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. @@ -109,7 +109,7 @@ extern "C" { /** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register * HP_PERI_TIMEOUT configuration register */ -#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_BASE + 0x18) +#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18) /** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing HP peripheral * register, corresponding to the number of clock cycles of the clock domain. @@ -141,7 +141,7 @@ extern "C" { /** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register * HP_PERI_TIMEOUT_ADDR register */ -#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_BASE + 0x1c) +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c) /** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ @@ -153,7 +153,7 @@ extern "C" { /** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register * HP_PERI_TIMEOUT_UID register */ -#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_BASE + 0x20) +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20) /** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. @@ -166,7 +166,7 @@ extern "C" { /** HP_SYSTEM_SDIO_CTRL_REG register * SDIO Control configuration register */ -#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_BASE + 0x30) +#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x30) /** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1; * Set this bit as 1 to disable SDIO_PROB function. disable by default. */ @@ -185,7 +185,7 @@ extern "C" { /** HP_SYSTEM_ROM_TABLE_LOCK_REG register * ROM-Table lock register */ -#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_BASE + 0x38) +#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38) /** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. * 0: Unlock @@ -199,7 +199,7 @@ extern "C" { /** HP_SYSTEM_ROM_TABLE_REG register * ROM-Table register */ -#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_BASE + 0x3c) +#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x3c) /** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; * Software ROM-Table register, whose content can be modified only when * HP_SYSTEM_ROM_TABLE_LOCK is 0. @@ -212,7 +212,7 @@ extern "C" { /** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register * Core Debug RunStall configurion register */ -#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_BASE + 0x40) +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40) /** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable debug RunStall functionality between HP CPU and * LP CPU. @@ -243,7 +243,7 @@ extern "C" { /** HP_SYSTEM_SPROM_CTRL_REG register * reserved */ -#define HP_SYSTEM_SPROM_CTRL_REG (DR_REG_HP_BASE + 0x70) +#define HP_SYSTEM_SPROM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x70) /** HP_SYSTEM_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 80; * reserved */ @@ -255,7 +255,7 @@ extern "C" { /** HP_SYSTEM_SPRAM_CTRL_REG register * reserved */ -#define HP_SYSTEM_SPRAM_CTRL_REG (DR_REG_HP_BASE + 0x74) +#define HP_SYSTEM_SPRAM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x74) /** HP_SYSTEM_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 10320; * reserved */ @@ -267,7 +267,7 @@ extern "C" { /** HP_SYSTEM_SPRF_CTRL_REG register * reserved */ -#define HP_SYSTEM_SPRF_CTRL_REG (DR_REG_HP_BASE + 0x78) +#define HP_SYSTEM_SPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x78) /** HP_SYSTEM_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 10320; * reserved */ @@ -279,7 +279,7 @@ extern "C" { /** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register * reserved */ -#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_BASE + 0x80) +#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYSTEM_BASE + 0x80) /** HP_SYSTEM_BITSCRAMBLER_RX_SEL : R/W; bitpos: [3:0]; default: 0; * select peri that will be connected to bitscrambler,dir : receive data from bs */ @@ -298,7 +298,7 @@ extern "C" { /** HP_SYSTEM_APPCPU_BOOT_ADDR_REG register * reserved */ -#define HP_SYSTEM_APPCPU_BOOT_ADDR_REG (DR_REG_HP_BASE + 0x84) +#define HP_SYSTEM_APPCPU_BOOT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x84) /** HP_SYSTEM_APPCPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 0; * reserved */ @@ -310,7 +310,7 @@ extern "C" { /** HP_SYSTEM_AXI_MST_PRI_REG register * AXI mst priority configuration register */ -#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_BASE + 0x88) +#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_SYSTEM_BASE + 0x88) /** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0; * AHB-DMA arbitration priority for command channels between masters connected to * ext_mem_DW_axi @@ -331,7 +331,7 @@ extern "C" { /** HP_SYSTEM_CPU_PERI_PMS_CONF_REG register * CPU Peripherals PMS configuration register */ -#define HP_SYSTEM_CPU_PERI_PMS_CONF_REG (DR_REG_HP_BASE + 0x90) +#define HP_SYSTEM_CPU_PERI_PMS_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x90) /** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear cpu peri_pms_record_reg. * 0: No clear @@ -345,7 +345,7 @@ extern "C" { /** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_INFO_REG register * CPU Peripherals PMS exception info record register */ -#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_BASE + 0x94) +#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_SYSTEM_BASE + 0x94) /** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0; * Represents whether the cpu peripheral pms has been triggered. * 0: No triggered @@ -381,7 +381,7 @@ extern "C" { /** HP_SYSTEM_HP_PERI_PMS_CONF_REG register * HP Peripherals PMS configuration register */ -#define HP_SYSTEM_HP_PERI_PMS_CONF_REG (DR_REG_HP_BASE + 0x98) +#define HP_SYSTEM_HP_PERI_PMS_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x98) /** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear hp peri_pms_record_reg. * 0: No clear @@ -395,7 +395,7 @@ extern "C" { /** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_INFO_REG register * HP Peripherals PMS exception info record register */ -#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_BASE + 0x9c) +#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_SYSTEM_BASE + 0x9c) /** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0; * Represents whether the hp peripheral pms has been triggered. * 0: No triggered @@ -431,7 +431,7 @@ extern "C" { /** HP_SYSTEM_MODEM_PERI_PMS_CONF_REG register * MODEM Peripherals PMS configuration register */ -#define HP_SYSTEM_MODEM_PERI_PMS_CONF_REG (DR_REG_HP_BASE + 0xa0) +#define HP_SYSTEM_MODEM_PERI_PMS_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xa0) /** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear modem peri_pms_record_reg. * 0: No clear @@ -445,7 +445,7 @@ extern "C" { /** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_INFO_REG register * MODEM Peripherals PMS exception info record register */ -#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_BASE + 0xa4) +#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_SYSTEM_BASE + 0xa4) /** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0; * Represents whether the modem peripheral pms has been triggered. * 0: No triggered @@ -481,7 +481,7 @@ extern "C" { /** HP_SYSTEM_ID_REG register * ID register */ -#define HP_SYSTEM_ID_REG (DR_REG_HP_BASE + 0x3dc) +#define HP_SYSTEM_ID_REG (DR_REG_HP_SYSTEM_BASE + 0x3dc) /** HP_SYSTEM_ROM_ID : RO; bitpos: [27:12]; default: 0; * Represents the ROM ID of chip */ @@ -493,7 +493,7 @@ extern "C" { /** HP_SYSTEM_RST_EN_REG register * PCR clock gating configure register */ -#define HP_SYSTEM_RST_EN_REG (DR_REG_HP_BASE + 0x3f0) +#define HP_SYSTEM_RST_EN_REG (DR_REG_HP_SYSTEM_BASE + 0x3f0) /** HP_SYSTEM_HPSYSREG_RST_EN : R/W; bitpos: [0]; default: 0; * Set 0 to reset hp_system_reg module */ @@ -505,7 +505,7 @@ extern "C" { /** HP_SYSTEM_DATE_REG register * Date control and version control register */ -#define HP_SYSTEM_DATE_REG (DR_REG_HP_BASE + 0x3fc) +#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) /** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823056; * Version control register. */ diff --git a/components/soc/esp32s3/gdma_periph.c b/components/soc/esp32s3/gdma_periph.c index d06f8c54da..546bf05f47 100644 --- a/components/soc/esp32s3/gdma_periph.c +++ b/components/soc/esp32s3/gdma_periph.c @@ -9,7 +9,6 @@ const gdma_signal_conn_t gdma_periph_signals = { .groups = { [0] = { - .module = PERIPH_GDMA_MODULE, .pairs = { [0] = { .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, From 3d08799be7b7ca3fcc600786db1c719c899412a5 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Mon, 14 Apr 2025 15:03:55 +0800 Subject: [PATCH 2/2] feat(gdma): support gdma retention on h4 --- .../test_apps/dma/main/test_async_memcpy.c | 8 +- components/soc/esp32h4/gdma_periph.c | 269 ++++++++++++++++++ .../esp32h4/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32h4/include/soc/soc_caps.h | 2 +- 4 files changed, 278 insertions(+), 5 deletions(-) diff --git a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c index e2c7a370dd..7374d0589c 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c +++ b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c @@ -247,9 +247,9 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]") printf("Testing memcpy by AHB GDMA\r\n"); TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver)); test_memcpy_with_dest_addr_unaligned(driver, false, false); -#if SOC_AHB_GDMA_SUPPORT_PSRAM +#if SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED test_memcpy_with_dest_addr_unaligned(driver, true, true); -#endif // SOC_AHB_GDMA_SUPPORT_PSRAM +#endif // SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED TEST_ESP_OK(esp_async_memcpy_uninstall(driver)); #endif // SOC_AHB_GDMA_SUPPORTED @@ -257,9 +257,9 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]") printf("Testing memcpy by AXI GDMA\r\n"); TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver)); test_memcpy_with_dest_addr_unaligned(driver, false, false); -#if SOC_AXI_GDMA_SUPPORT_PSRAM +#if SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED test_memcpy_with_dest_addr_unaligned(driver, true, true); -#endif // SOC_AXI_GDMA_SUPPORT_PSRAM +#endif // SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED TEST_ESP_OK(esp_async_memcpy_uninstall(driver)); #endif // SOC_AXI_GDMA_SUPPORTED } diff --git a/components/soc/esp32h4/gdma_periph.c b/components/soc/esp32h4/gdma_periph.c index 38ba63f7b2..0fed9b87c2 100644 --- a/components/soc/esp32h4/gdma_periph.c +++ b/components/soc/esp32h4/gdma_periph.c @@ -35,3 +35,272 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; + +#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG + AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG + AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG + AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 19 +#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) +#define G0P0_RETENTION_REGS_CNT_1 4 +#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; +static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG + + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG + AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG + AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG + AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ + +#define G0P1_RETENTION_REGS_CNT_0 3 +#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) +#define G0P1_RETENTION_REGS_CNT_1 16 +#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200) +#define G0P1_RETENTION_REGS_CNT_2 4 +#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ + G0P1_RETENTION_REGS_CNT_2, 0, 0, \ + g0p1_regs_map2[0], g0p1_regs_map2[1], \ + g0p1_regs_map2[2], g0p1_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG + + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG + AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG + AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG + AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG + AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 3 +#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) +#define G0P2_RETENTION_REGS_CNT_1 16 +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300) +#define G0P2_RETENTION_REGS_CNT_2 4 +#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ + G0P2_RETENTION_REGS_CNT_2, 0, 0, \ + g0p2_regs_map2[0], g0p2_regs_map2[1], \ + g0p2_regs_map2[2], g0p2_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair3) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG + + AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG + AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG + AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG + AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG + AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG + AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P3_RETENTION_REGS_CNT_0 3 +#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38) +#define G0P3_RETENTION_REGS_CNT_1 16 +#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400) +#define G0P3_RETENTION_REGS_CNT_2 4 +#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ + G0P3_RETENTION_REGS_CNT_0, 0, 0, \ + g0p3_regs_map0[0], g0p3_regs_map0[1], \ + g0p3_regs_map0[2], g0p3_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ + G0P3_RETENTION_REGS_CNT_1, 0, 0, \ + g0p3_regs_map1[0], g0p3_regs_map1[1], \ + g0p3_regs_map1[2], g0p3_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ + G0P3_RETENTION_REGS_CNT_2, 0, 0, \ + g0p3_regs_map2[0], g0p3_regs_map2[1], \ + g0p3_regs_map2[2], g0p3_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair4) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG + + AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG + AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG + AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG + AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG + AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P4_RETENTION_REGS_CNT_0 3 +#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48) +#define G0P4_RETENTION_REGS_CNT_1 20 +#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500) +static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0}; +static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; +static const regdma_entries_config_t gdma_g0p4_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ + G0P4_RETENTION_REGS_CNT_0, 0, 0, \ + g0p4_regs_map0[0], g0p4_regs_map0[1], \ + g0p4_regs_map0[2], g0p4_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ + G0P4_RETENTION_REGS_CNT_1, 0, 0, \ + g0p4_regs_map1[0], g0p4_regs_map1[1], \ + g0p4_regs_map1[2], g0p4_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + }, + [3] = { + gdma_g0p3_regs_retention, + ARRAY_SIZE(gdma_g0p3_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH3, + }, + [4] = { + gdma_g0p4_regs_retention, + ARRAY_SIZE(gdma_g0p4_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH4, + }, + } +}; +#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 86de4dcd6d..4c75f8b563 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -163,6 +163,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 5 +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_AHB_GDMA_SUPPORT_PSRAM bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index a9d0b6e918..4733464237 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -184,7 +184,7 @@ #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 5 // #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383 -// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12384 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 #define SOC_AHB_GDMA_SUPPORT_PSRAM 1 /*-------------------------- ETM CAPS --------------------------------------*/