feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

feat(mmu): support mmu and flash mmap driver on p4

Browse Source
This commit is contained in:
Armando
2023-08-14 13:58:35 +08:00
parent d97b3fec67
commit 8c8affc812
17 changed files with 327 additions and 226 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32p4/include/soc/ext_mem_defs.h
+37 -54
View File
@@ -29,21 +29,16 @@ extern "C" {
#define DRAM_FLASH_ADDRESS_LOW DRAM0_CACHE_ADDRESS_LOW
#define DRAM_FLASH_ADDRESS_HIGH 0x44000000
#define SINGLE_BANK_CACHE_ADDRESS_LOW 0x40000000
#define SINGLE_BANK_CACHE_ADDRESS_HIGH 0x44000000
#define DUAL_BANK_CACHE_ADDRESS_LOW 0x48000000
#define DUAL_BANK_CACHE_ADDRESS_HIGH 0x4C000000
#define DRAM_PSRAM_ADDRESS_LOW 0x48000000
#define DRAM_PSRAM_ADDRESS_HIGH 0x4C000000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define ADDRESS_IN_DRAM_FLASH(vaddr) ADDRESS_IN_BUS(DRAM_FLASH, vaddr)
#define ADDRESS_IN_DRAM_PSRAM(vaddr) ADDRESS_IN_BUS(DRAM_PSRAM, vaddr)
//TODO, remove these cache function dependencies
#define CACHE_IROM_MMU_START 0
@@ -62,91 +57,79 @@ extern "C" {
#define MMU_BUS_START(i) 0
#define MMU_BUS_SIZE(i) (0x400 * 4)
#define MMU_MSPI_ACCESS_FLASH 0
#define MMU_MSPI_ACCESS_SPIRAM BIT(10)
#define MMU_MSPI_VALID BIT(12)
#define MMU_MSPI_INVALID 0
#define MMU_MSPI_SENSITIVE BIT(13)
#define MMU_PSRAM_ACCESS_SPIRAM BIT(10)
#define MMU_FLASH_VALID BIT(12)
#define MMU_FLASH_INVALID 0
#define MMU_PSRAM_VALID BIT(11)
#define MMU_PSRAM_INVALID 0
#define MMU_ACCESS_FLASH 0
#define MMU_ACCESS_PSRAM BIT(10)
#define MMU_FLASH_SENSITIVE BIT(13)
#define MMU_PSRAM_SENSITIVE BIT(12)
#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH
#define MMU_ACCESS_SPIRAM MMU_MSPI_ACCESS_SPIRAM
#define MMU_VALID MMU_MSPI_VALID
#define MMU_SENSITIVE MMU_MSPI_SENSITIVE
#define DMMU_SENSITIVE MMU_PSRAM_SENSITIVE
#define MMU_INVALID_MASK MMU_MSPI_VALID
#define MMU_INVALID MMU_MSPI_INVALID
#define DMMU_INVALID_MASK MMU_PSRAM_VALID
#define DMMU_INVALID 0
#define CACHE_MAX_SYNC_NUM 0x400000
#define CACHE_MAX_LOCK_NUM 0x8000
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(9), so value bits are 0x1ff
* MMU entry valid bit mask for mapping value.
* - For a Flash MMU entry:
* physical page number is BIT(0)~BIT(10), so value bits are 0x7ff
* - For a PSRAM MMU entry:
* physical page number is BIT(0)~BIT(9), so value bits are 0x3ff
*/
#define MMU_VALID_VAL_MASK 0x3ff
#define MMU_FLASH_VALID_VAL_MASK 0x7ff
#define MMU_PSRAM_VALID_VAL_MASK 0x3ff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
* 32768 * 64KB, means MMU can support 2GB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 1024
#define MMU_FLASH_MAX_PADDR_PAGE_NUM 32768
#define MMU_PSRAM_MAX_PADDR_PAGE_NUM 16384
//MMU entry num
#define MMU_ENTRY_NUM 1024
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
* 0x4000_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
#define SOC_MMU_FLASH_VADDR_BASE 0x40000000
#define SOC_MMU_PSRAM_VADDR_BASE 0x48000000
#define SOC_MMU_FLASH_VADDR_START 0x40000000
#define SOC_MMU_FLASH_VADDR_END 0x44000000
#define SOC_MMU_PSRAM_VADDR_START 0x48000000
#define SOC_MMU_PSRAM_VADDR_END 0x4C000000
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 1024 MMU entries, needs 0x3F to hold it.
* - 1024 MMU entries for flash, 1024 MMU entries for psram, needs 0xFFF to hold it.
*
* Therefore, 0x3F,FFFF
*/
#define SOC_MMU_MEM_PHYSICAL_LINEAR_CAP (SOC_MMU_FLASH_VADDR_BASE ^ SOC_MMU_PSRAM_VADDR_BASE)
#define SOC_MMU_LINEAR_FLASH_ADDR_MASK (0xBFFFFFF)
#define SOC_MMU_LINEAR_PARSM_ADDR_MASK (0xBFFFFFF | SOC_MMU_MEM_PHYSICAL_LINEAR_CAP)
#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFFFF
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
* Under this condition, we use the max linear space.
*/
#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW (SOC_MMU_FLASH_VADDR_START & SOC_MMU_LINEAR_FLASH_ADDR_MASK)
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_FLASH_ADDR_MASK + 1)
#define SOC_MMU_FLASH_LINEAR_ADDRESS_SIZE (SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH - SOC_MMU_FLASH_LINEAR_ADDRESS_LOW)
#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW (DRAM_FLASH_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
#if ((DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
#else
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
#endif
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW (SOC_MMU_PSRAM_VADDR_START & SOC_MMU_LINEAR_PARSM_ADDR_MASK)
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_PARSM_ADDR_MASK + 1)
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_SIZE (SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH - SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW)
/**
* I/D share the MMU linear address range
*/
_Static_assert((SOC_MMU_FLASH_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP) == (SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP), \
"IRAM0 and DRAM0 raw linear address should be same");
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW (DRAM_PSRAM_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
#if ((DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
#else
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
#endif
#ifdef __cplusplus