diff --git a/components/esp_hw_support/port/esp32c5/pmu_sleep.c b/components/esp_hw_support/port/esp32c5/pmu_sleep.c index 82a2335a74..7a0586fe13 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c5/pmu_sleep.c @@ -60,17 +60,20 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period); const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \ : rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period); + const int lp_control_wait_time_us = mc->lp.isolate_wait_time_us + mc->lp.reset_wait_time_us; const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \ + lp_wakeup_wait_time_us + lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us \ - + mc->lp.power_up_wait_time_us; + + mc->lp.power_up_wait_time_us + lp_control_wait_time_us; /* HP core hardware wait time, microsecond */ const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us; + const int hp_control_wait_time_us = mc->hp.isolate_wait_time_us + mc->hp.reset_wait_time_us; const int hp_regdma_wait_time_us = MAX(mc->hp.regdma_s2m_work_time_us + mc->hp.regdma_m2a_work_time_us, mc->hp.regdma_s2a_work_time_us); const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us; - const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + MAX(hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us, hp_clock_wait_time_us); + const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + MAX(hp_clock_wait_time_us, \ + hp_digital_power_up_wait_time_us + hp_control_wait_time_us + hp_regdma_wait_time_us); /* When the SOC wakeup (lp timer or GPIO wakeup) and Modem wakeup (Beacon wakeup) complete, the soc * wakeup will be delayed until the RF is turned on in Modem state. @@ -117,6 +120,8 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default( param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period); param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period); param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period); + param->hp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period); + param->hp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period); const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period); const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us; @@ -127,6 +132,8 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default( param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period); param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period); param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period); + param->lp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->lp.isolate_wait_time_us, fastclk_period); + param->lp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->lp.reset_wait_time_us, fastclk_period); if (power->hp_sys.xtal.xpd_xtal) { param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period); @@ -233,6 +240,9 @@ static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_confi pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle); pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle); + pmu_hal_hp_set_control_ready_wait_cycle(ctx->hal, param->hp_sys.isolate_wait_cycle, param->hp_sys.reset_wait_cycle); + pmu_hal_lp_set_control_ready_wait_cycle(ctx->hal, param->lp_sys.isolate_wait_cycle, param->lp_sys.reset_wait_cycle); + pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle); pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle); pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle); diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h index a873be8b25..7d0a1a5b77 100644 --- a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h @@ -218,6 +218,8 @@ typedef struct { uint8_t modify_icg_cntl_wait_cycle; uint8_t switch_icg_cntl_wait_cycle; uint8_t min_slp_slow_clk_cycle; + uint8_t isolate_wait_cycle; + uint8_t reset_wait_cycle; } pmu_hp_param_t; typedef struct { @@ -226,6 +228,8 @@ typedef struct { uint8_t analog_wait_target_cycle; uint8_t digital_power_down_wait_cycle; uint8_t digital_power_up_wait_cycle; + uint8_t isolate_wait_cycle; + uint8_t reset_wait_cycle; } pmu_lp_param_t; typedef struct { @@ -421,11 +425,12 @@ typedef struct pmu_sleep_machine_constant { uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */ uint8_t wakeup_wait_cycle; /* Modem wakeup signal (WiFi MAC and BEACON wakeup) waits for the slow & fast clock domain synchronization and the wakeup signal triggers the PMU FSM switching wait cycle (unit: slow clock cycle) */ uint8_t reserved0; - uint16_t reserved1; uint16_t analog_wait_time_us; /* LP LDO power up wait time (unit: microsecond) */ uint16_t xtal_wait_stable_time_us; /* Main XTAL stabilization wait time (unit: microsecond) */ uint8_t clk_switch_cycle; /* Clock switch to FOSC (unit: slow clock cycle) */ uint8_t clk_power_on_wait_cycle; /* Clock power on wait cycle (unit: slow clock cycle) */ + uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */ + uint8_t reset_wait_time_us; /* Waiting for all reset signals to be ready (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */ } lp; @@ -434,6 +439,8 @@ typedef struct pmu_sleep_machine_constant { uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */ uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */ uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */ + uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */ + uint8_t reset_wait_time_us; /* Waiting for all reset signals to be ready (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */ uint16_t regdma_s2m_work_time_us; /* Modem Subsystem (S2M switch) REGDMA restore time (unit: microsecond) */ @@ -455,6 +462,8 @@ typedef struct pmu_sleep_machine_constant { .xtal_wait_stable_time_us = 250, \ .clk_switch_cycle = 1, \ .clk_power_on_wait_cycle = 1, \ + .isolate_wait_time_us = 1, \ + .reset_wait_time_us = 1, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2 \ }, \ @@ -463,6 +472,8 @@ typedef struct pmu_sleep_machine_constant { .clock_domain_sync_time_us = 150, \ .system_dfs_up_work_time_us = 124, \ .analog_wait_time_us = 154, \ + .isolate_wait_time_us = 1, \ + .reset_wait_time_us = 1, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ .regdma_s2m_work_time_us = 172, \ diff --git a/components/hal/esp32c5/include/hal/pmu_hal.h b/components/hal/esp32c5/include/hal/pmu_hal.h index f4ca27e9e8..7a8795d63b 100644 --- a/components/hal/esp32c5/include/hal/pmu_hal.h +++ b/components/hal/esp32c5/include/hal/pmu_hal.h @@ -28,6 +28,10 @@ void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal); +void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle); + +void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle); + void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal); void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal); diff --git a/components/hal/esp32c5/include/hal/pmu_ll.h b/components/hal/esp32c5/include/hal/pmu_ll.h index 97a15793da..98958f79c4 100644 --- a/components/hal/esp32c5/include/hal/pmu_ll.h +++ b/components/hal/esp32c5/include/hal/pmu_ll.h @@ -637,6 +637,26 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t * return hw->power.wait_timer1.powerup_timer; } +FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle) +{ + hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle) +{ + hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle) +{ + hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle) +{ + hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle; +} + FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle); diff --git a/components/hal/esp32c5/pmu_hal.c b/components/hal/esp32c5/pmu_hal.c index d4e2a7514c..dd6bbd554f 100644 --- a/components/hal/esp32c5/pmu_hal.c +++ b/components/hal/esp32c5/pmu_hal.c @@ -37,6 +37,18 @@ uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal) return power_supply_wait_cycle + power_up_wait_cycle; } +void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle) +{ + pmu_ll_hp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle); + pmu_ll_hp_set_reset_wait_cycle(hal->dev, reset_wait_cycle); +} + +void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle) +{ + pmu_ll_lp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle); + pmu_ll_lp_set_reset_wait_cycle(hal->dev, reset_wait_cycle); +} + void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal) { pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);