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solve memory error bug when in lightsleep mode

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This commit is contained in:
chaijie
2022-04-20 17:52:25 +08:00
parent 5fe7d538a5
commit 908192f504
2 changed files with 4 additions and 3 deletions
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2
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@@ -67,6 +67,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1); rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg); rtc_sleep_pu(pu_cfg);
} }
/* mem force pu */
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
if (cfg.wifi_pd_en) { if (cfg.wifi_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else { } else {

5
components/soc/esp32c3/include/soc/rtc.h
View File

@@ -58,9 +58,8 @@ extern "C" {
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/ */
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias #define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage #define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16 #define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18 #define RTC_CNTL_DBIAS_1V00 18
@@ -105,7 +104,7 @@ extern "C" {
/* /*
set sleep_init default param set sleep_init default param
*/ */
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0