feat: enable RSA support for c5 mp version

This commit enables RSA peripheral support for ESP32-C5 MP version.

components/hal/esp32c5/include/hal/mpi_ll.h

@@ -9,22 +9,17 @@
 #include <string.h>
 #include <sys/param.h>
 #include "soc/soc_caps.h"
-// TODO: [ESP32C5] IDF-8620 remove the cap
-#if SOC_MPI_SUPPORTED
 #include "hal/assert.h"
 #include "hal/mpi_types.h"
 #include "soc/pcr_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/rsa_reg.h"
 #include "soc/mpi_periph.h"
-#endif  // SOC_MPI_SUPPORTED
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-// TODO: [ESP32C5] IDF-8620 remove the cap
-#if SOC_MPI_SUPPORTED
 
 /**
  * @brief Enable the bus clock for MPI peripheral module
@@ -180,7 +175,6 @@ static inline void mpi_ll_set_search_position(size_t pos)
 {
     REG_WRITE(RSA_SEARCH_POS_REG, pos);
 }
-#endif  // SOC_MPI_SUPPORTED
 
 #ifdef __cplusplus
 }

components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in

@@ -47,6 +47,14 @@ config SOC_SYSTIMER_SUPPORTED
     bool
     default y
 
+config SOC_MPI_SUPPORTED
+    bool
+    default y
+
+config SOC_RSA_SUPPORTED
+    bool
+    default y
+
 config SOC_ECC_SUPPORTED
     bool
     default y
@@ -279,6 +287,14 @@ config SOC_RMT_SUPPORT_XTAL
     bool
     default y
 
+config SOC_MPI_MEM_BLOCKS_NUM
+    int
+    default 4
+
+config SOC_MPI_OPERATIONS_NUM
+    int
+    default 3
+
 config SOC_RSA_MAX_BIT_LEN
     int
     default 3072

components/soc/esp32c5/mp/include/soc/soc_caps.h

@@ -46,9 +46,9 @@
 // #define SOC_I2C_SUPPORTED               1  // TODO: [ESP32C5] IDF-8694, IDF-8696
 #define SOC_SYSTIMER_SUPPORTED          1     // TODO: [ESP32C5] IDF-8707
 // #define SOC_AES_SUPPORTED               1  // TODO: [ESP32C5] IDF-8627
-// #define SOC_MPI_SUPPORTED               1
+#define SOC_MPI_SUPPORTED               1
 // #define SOC_SHA_SUPPORTED               1  // TODO: [ESP32C5] IDF-8624
-// #define SOC_RSA_SUPPORTED               1  // TODO: [ESP32C5] IDF-8620
+#define SOC_RSA_SUPPORTED               1
 // #define SOC_HMAC_SUPPORTED              1  // TODO: [ESP32C5] IDF-8616
 // #define SOC_DIG_SIGN_SUPPORTED          1  // TODO: [ESP32C5] IDF-8619
 #define SOC_ECC_SUPPORTED               1
@@ -344,8 +344,8 @@
 // #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/
-// #define SOC_MPI_MEM_BLOCKS_NUM (4)
+#define SOC_MPI_MEM_BLOCKS_NUM (4)
-// #define SOC_MPI_OPERATIONS_NUM (3)
+#define SOC_MPI_OPERATIONS_NUM (3)
 
 /*--------------------------- RSA CAPS ---------------------------------------*/
 #define SOC_RSA_MAX_BIT_LEN    (3072)

components/soc/esp32c5/mp/mpi_periph.c

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rsa_reg.h"
+#include "soc/mpi_periph.h"
+
+const uint32_t MPI_BLOCK_BASES[SOC_MPI_MEM_BLOCKS_NUM] = {
+    RSA_X_MEM,
+    RSA_Y_MEM,
+    RSA_Z_MEM,
+    RSA_M_MEM,
+};
+
+const uint32_t MPI_OPERATIONS_REG[SOC_MPI_OPERATIONS_NUM] = {
+    RSA_SET_START_MULT_REG,
+    RSA_SET_START_MODMULT_REG,
+    RSA_SET_START_MODEXP_REG,
+};