forked from espressif/esp-idf
Merge branch 'bugfix/fix_uart_ll_compatible_with_cpp' into 'master'
fix(uart): Fixed C++ type conversion compile error in uart_ll_get_sclk Closes IDFGH-10573 See merge request espressif/esp-idf!24690
This commit is contained in:
@@ -92,10 +92,10 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
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switch (hw->conf0.tick_ref_always_on) {
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switch (hw->conf0.tick_ref_always_on) {
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default:
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default:
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case 0:
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case 0:
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*source_clk = UART_SCLK_REF_TICK;
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*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
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break;
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break;
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case 1:
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case 1:
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*source_clk = UART_SCLK_APB;
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*source_clk = (soc_module_clk_t)UART_SCLK_APB;
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break;
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break;
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}
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}
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}
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}
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -135,13 +135,13 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
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switch (hw->clk_conf.sclk_sel) {
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switch (hw->clk_conf.sclk_sel) {
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default:
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default:
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case 1:
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case 1:
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*source_clk = UART_SCLK_PLL_F40M;
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*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F40M;
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break;
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break;
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case 2:
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case 2:
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*source_clk = UART_SCLK_RTC;
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*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
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break;
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break;
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case 3:
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case 3:
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*source_clk = UART_SCLK_XTAL;
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*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
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break;
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break;
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}
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}
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}
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}
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -137,13 +137,13 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
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switch (hw->clk_conf.sclk_sel) {
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switch (hw->clk_conf.sclk_sel) {
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default:
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default:
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case 1:
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case 1:
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*source_clk = UART_SCLK_APB;
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*source_clk = (soc_module_clk_t)UART_SCLK_APB;
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break;
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break;
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case 2:
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case 2:
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*source_clk = UART_SCLK_RTC;
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*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
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break;
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break;
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case 3:
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case 3:
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*source_clk = UART_SCLK_XTAL;
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*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
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break;
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break;
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}
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}
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}
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}
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@@ -96,10 +96,10 @@ static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_
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switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
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switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
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default:
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default:
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case 0:
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case 0:
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*source_clk = LP_UART_SCLK_LP_FAST;
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*source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
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break;
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break;
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case 1:
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case 1:
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*source_clk = LP_UART_SCLK_XTAL_D2;
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*source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
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break;
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break;
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}
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}
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}
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}
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@@ -224,13 +224,13 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
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switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
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switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
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default:
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default:
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case 1:
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case 1:
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*source_clk = UART_SCLK_PLL_F80M;
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*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
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break;
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break;
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case 2:
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case 2:
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*source_clk = UART_SCLK_RTC;
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*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
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break;
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break;
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case 3:
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case 3:
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*source_clk = UART_SCLK_XTAL;
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*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
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break;
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break;
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}
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}
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} else {
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} else {
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@@ -169,13 +169,13 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
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switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
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switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
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default:
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default:
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case 1:
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case 1:
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*source_clk = UART_SCLK_PLL_F48M;
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*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
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break;
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break;
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case 2:
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case 2:
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*source_clk = UART_SCLK_RTC;
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*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
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break;
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break;
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case 3:
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case 3:
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*source_clk = UART_SCLK_XTAL;
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*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
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break;
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break;
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}
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}
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}
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}
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@@ -90,10 +90,10 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
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switch (hw->conf0.tick_ref_always_on) {
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switch (hw->conf0.tick_ref_always_on) {
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default:
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default:
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case 0:
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case 0:
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*source_clk = UART_SCLK_REF_TICK;
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*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
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break;
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break;
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case 1:
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case 1:
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*source_clk = UART_SCLK_APB;
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*source_clk = (soc_module_clk_t)UART_SCLK_APB;
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break;
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break;
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}
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}
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}
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}
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -109,13 +109,13 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
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switch (hw->clk_conf.sclk_sel) {
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switch (hw->clk_conf.sclk_sel) {
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default:
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default:
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case 1:
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case 1:
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*source_clk = UART_SCLK_APB;
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*source_clk = (soc_module_clk_t)UART_SCLK_APB;
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break;
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break;
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case 2:
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case 2:
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*source_clk = UART_SCLK_RTC;
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*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
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break;
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break;
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case 3:
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case 3:
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*source_clk = UART_SCLK_XTAL;
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*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
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break;
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break;
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}
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}
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}
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}
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@@ -552,7 +552,6 @@ FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length
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}
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}
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/**
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/**
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FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
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* @brief Set the rts active level.
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* @brief Set the rts active level.
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*
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*
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* @param hw Beginning address of the peripheral registers.
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* @param hw Beginning address of the peripheral registers.
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