feat(riscv): added api to disable branch predictor

This commit is contained in:
Armando
2024-08-13 18:22:30 +08:00
parent 4c53b937b6
commit 95594df093
2 changed files with 20 additions and 4 deletions

View File

@@ -578,6 +578,14 @@ FORCE_INLINE_ATTR void esp_cpu_branch_prediction_enable(void)
{ {
rv_utils_en_branch_predictor(); rv_utils_en_branch_predictor();
} }
/**
* @brief Disable branch prediction
*/
FORCE_INLINE_ATTR void esp_cpu_branch_prediction_disable(void)
{
rv_utils_dis_branch_predictor();
}
#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED #endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
#ifdef __cplusplus #ifdef __cplusplus

View File

@@ -27,6 +27,13 @@ extern "C" {
#define CSR_PCCR_MACHINE 0x7e2 #define CSR_PCCR_MACHINE 0x7e2
#endif /* SOC_CPU_HAS_CSR_PC */ #endif /* SOC_CPU_HAS_CSR_PC */
#if SOC_BRANCH_PREDICTOR_SUPPORTED
#define MHCR 0x7c1
#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
#endif //SOC_BRANCH_PREDICTOR_SUPPORTED
#if SOC_CPU_HAS_FPU #if SOC_CPU_HAS_FPU
/* FPU bits in mstatus start at bit 13 */ /* FPU bits in mstatus start at bit 13 */
@@ -363,12 +370,13 @@ FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_
#if SOC_BRANCH_PREDICTOR_SUPPORTED #if SOC_BRANCH_PREDICTOR_SUPPORTED
FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void) FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
{ {
#define MHCR 0x7c1
#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB); RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
} }
FORCE_INLINE_ATTR void rv_utils_dis_branch_predictor(void)
{
RV_CLEAR_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
}
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus