From 98d9f04b00b5c5aec0c562cd56218b50fab756a4 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 7 Feb 2024 16:56:53 +0800 Subject: [PATCH] feat(gdma): add GDMA support for ESP32C5 --- .../bootloader_support/src/bootloader_mem.c | 15 +- components/esp_hw_support/CMakeLists.txt | 9 +- components/hal/esp32c5/include/hal/cache_ll.h | 45 +- components/hal/esp32c5/include/hal/gdma_ll.h | 627 +++++++++++++++++ components/soc/esp32c5/gdma_periph.c | 121 ++++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 24 + .../soc/esp32c5/include/soc/gdma_channel.h | 4 +- .../soc/esp32c5/include/soc/gdma_struct.h | 633 ++++++++---------- components/soc/esp32c5/include/soc/soc_caps.h | 17 +- .../soc/esp32c5/include/soc/soc_etm_source.h | 300 +++++++++ components/soc/esp32c6/gdma_periph.c | 10 +- .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32c6/include/soc/soc_caps.h | 11 +- components/soc/esp32h2/gdma_periph.c | 10 +- .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32h2/include/soc/soc_caps.h | 11 +- components/soc/esp32p4/include/soc/soc_caps.h | 13 +- components/soc/include/soc/gdma_periph.h | 2 +- 18 files changed, 1453 insertions(+), 407 deletions(-) create mode 100644 components/hal/esp32c5/include/hal/gdma_ll.h create mode 100644 components/soc/esp32c5/gdma_periph.c create mode 100644 components/soc/esp32c5/include/soc/soc_etm_source.h diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index fe6187cc4d..222f870318 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,12 @@ #include "hal/apm_hal.h" #endif +#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5! +#include "soc/hp_apm_reg.h" +#include "soc/lp_apm_reg.h" +#include "soc/lp_apm0_reg.h" +#endif + void bootloader_init_mem(void) { @@ -30,6 +36,13 @@ void bootloader_init_mem(void) apm_hal_apm_ctrl_filter_enable_all(false); #endif +#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5! + // disable apm filter + REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); + REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0); + REG_WRITE(HP_APM_FUNC_CTRL_REG, 0); +#endif + #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE // protect memory region esp_cpu_configure_region_protection(); diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 6b95e82235..339de24e05 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -70,9 +70,12 @@ if(NOT BOOTLOADER_BUILD) if(CONFIG_SOC_GDMA_SUPPORTED) list(APPEND srcs "dma/gdma.c") - if(CONFIG_SOC_PM_SUPPORT_TOP_PD) + if(CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION) list(APPEND srcs "dma/gdma_sleep_retention.c") endif() + if(CONFIG_SOC_GDMA_SUPPORT_ETM) + list(APPEND srcs "dma/gdma_etm.c") + endif() endif() if(CONFIG_SOC_MULTI_USAGE_LDO_SUPPORTED) @@ -92,10 +95,6 @@ if(NOT BOOTLOADER_BUILD) endif() # CONFIG_SOC_CP_DMA_SUPPORTED endif() # CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED - if(CONFIG_SOC_GDMA_SUPPORT_ETM) - list(APPEND srcs "dma/gdma_etm.c") - endif() - if(CONFIG_SOC_DW_GDMA_SUPPORTED) list(APPEND srcs "dma/dw_gdma.c") endif() diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h index 33fce6ff2a..10de78a09c 100644 --- a/components/hal/esp32c5/include/hal/cache_ll.h +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,7 @@ // #include "soc/ext_mem_defs.h" #include "hal/cache_types.h" #include "hal/assert.h" +#include "esp32c5/rom/cache.h" #ifdef __cplusplus extern "C" { @@ -46,13 +47,12 @@ __attribute__((always_inline)) static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); - // bool enabled = false; - // if (REG_GET_BIT(EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG, EXTMEM_L1_CACHE_AUTOLOAD_ENA)) { - // enabled = true; - // } - // return enabled; - return (bool)0; + HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + bool enabled = false; + if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) { + enabled = true; + } + return enabled; } /** @@ -66,8 +66,8 @@ __attribute__((always_inline)) static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // (void) type; - // Cache_Disable_ICache(); + (void) type; + Cache_Disable_ICache(); } /** @@ -83,7 +83,7 @@ __attribute__((always_inline)) static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); + Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); } /** @@ -97,7 +97,7 @@ __attribute__((always_inline)) static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // Cache_Suspend_ICache(); + Cache_Suspend_ICache(); } /** @@ -113,7 +113,7 @@ __attribute__((always_inline)) static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); + Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); } /** @@ -131,7 +131,7 @@ __attribute__((always_inline)) static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // Cache_Invalidate_Addr(vaddr, size); + Cache_Invalidate_Addr(vaddr, size); } /** @@ -145,7 +145,7 @@ __attribute__((always_inline)) static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY); + Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY); } /** @@ -159,7 +159,7 @@ __attribute__((always_inline)) static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // Cache_Freeze_ICache_Disable(); + Cache_Freeze_ICache_Disable(); } /** @@ -175,10 +175,9 @@ __attribute__((always_inline)) static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // uint32_t size = 0; - // size = Cache_Get_ICache_Line_Size(); - // return size; - return (uint32_t)0; + uint32_t size = 0; + size = Cache_Get_ICache_Line_Size(); + return size; } /** @@ -243,6 +242,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) + abort(); // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); // //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first // HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); @@ -268,6 +268,7 @@ __attribute__((always_inline)) static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) + abort(); // bool valid = false; // uint32_t vaddr_end = vaddr_start + len - 1; // // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)); @@ -292,7 +293,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); + SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); } /** @@ -304,7 +305,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); + SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); } /** diff --git a/components/hal/esp32c5/include/hal/gdma_ll.h b/components/hal/esp32c5/include/hal/gdma_ll.h new file mode 100644 index 0000000000..10d3307438 --- /dev/null +++ b/components/hal/esp32c5/include/hal/gdma_ll.h @@ -0,0 +1,627 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* Required for NULL constant */ +#include +#include +#include "hal/gdma_types.h" +#include "soc/gdma_struct.h" +#include "soc/gdma_reg.h" +#include "soc/soc_etm_source.h" +#include "soc/pcr_struct.h" +#include "soc/retention_periph_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id) + +#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) + +#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] + +#define GDMA_LL_RX_EVENT_MASK (0x7F) +#define GDMA_LL_TX_EVENT_MASK (0x3F) + +// any "dummy" peripheral ID can be used for M2M mode +#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32) +#define GDMA_LL_INVALID_PERIPH_ID (0x3F) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3) +#define GDMA_LL_EVENT_TX_EOF (1<<1) +#define GDMA_LL_EVENT_TX_DONE (1<<0) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0 +#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups +#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group + +#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \ + }}}[group][chan][event] + +#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \ + }}}[group][chan][event] + +#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \ + }}}[group][chan][task] + +#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \ + }}}[group][chan][task] + +// TODO: Workaround for C5-beta3 only. C5-mp can still vectorized channels into an array in gdma_struct.h +#define GDMA_LL_CHANNEL_GET_REG_ADDR(dev, ch) ((volatile gdma_chn_reg_t*[]){&dev->channel0, &dev->channel1, &dev->channel2}[(ch)]) + +///////////////////////////////////// Common ///////////////////////////////////////// + +/** + * @brief Enable the bus clock for the DMA module + */ +static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.gdma_conf.gdma_clk_en = enable; +} + +/** + * @brief Reset the DMA module + */ +static inline void gdma_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.gdma_conf.gdma_rst_en = 1; + PCR.gdma_conf.gdma_rst_en = 0; +} + +/** + * @brief Force enable register clock + */ +static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable) +{ + dev->misc_conf.clk_en = enable; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->in_intr[channel].ena.val |= mask; + } else { + dev->in_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->in_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->in_intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_conf1.in_check_owner = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, disabled by default + */ +static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_conf0.in_data_burst_en = enable; +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_conf0.indscr_burst_en = enable; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_conf0.in_rst = 1; + ch->in.in_conf0.in_rst = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.infifo_status.infifo_cnt; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_pop.infifo_pop = 1; + return ch->in.in_pop.infifo_rdata; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_link.inlink_addr = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_link.inlink_start = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_link.inlink_stop = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_link.inlink_restart = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_link.inlink_auto_ret = enable; +} + +/** + * @brief Check if DMA RX descriptor FSM is in IDLE state + */ +static inline bool gdma_ll_rx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.in_link.inlink_park; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.in_suc_eof_des_addr.val; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.in_err_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched RX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->in.in_dscr.val; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_pri.rx_pri = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_peri_sel.peri_in_sel = periph_id; + ch->in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M); +} + +/** + * @brief Disconnect DMA RX channel from peripheral + */ +static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_peri_sel.peri_in_sel = GDMA_LL_INVALID_PERIPH_ID; + ch->in.in_conf0.mem_trans_en = false; +} + +/** + * @brief Whether to enable the ETM subsystem for RX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->in.in_conf0.in_etm_en = enable; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->out_intr[channel].ena.val |= mask; + } else { + dev->out_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->out_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->out_intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf1.out_check_owner = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, disabled by default + */ +static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf0.out_data_burst_en = enable; +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf0.outdscr_burst_en = enable; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf0.out_eof_mode = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf0.out_auto_wrback = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf0.out_rst = 1; + ch->out.out_conf0.out_rst = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->out.outfifo_status.outfifo_cnt; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_push.outfifo_wdata = data; + ch->out.out_push.outfifo_push = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_link.outlink_addr = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_link.outlink_start = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_link.outlink_stop = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_link.outlink_restart = 1; +} + +/** + * @brief Check if DMA TX descriptor FSM is in IDLE state + */ +static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->out.out_link.outlink_park; +} + +/** + * @brief Get TX EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->out.out_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched TX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + return ch->out.out_dscr.val; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_pri.tx_pri = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + (void)periph; + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_peri_sel.peri_out_sel = periph_id; +} + +/** + * @brief Disconnect DMA TX channel from peripheral + */ +static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_peri_sel.peri_out_sel = GDMA_LL_INVALID_PERIPH_ID; +} + +/** + * @brief Whether to enable the ETM subsystem for TX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel); + ch->out.out_conf0.out_etm_en = enable; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/gdma_periph.c b/components/soc/esp32c5/gdma_periph.c new file mode 100644 index 0000000000..943e9bad3d --- /dev/null +++ b/components/soc/esp32c5/gdma_periph.c @@ -0,0 +1,121 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" +#include "soc/gdma_reg.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_GDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE, + } + } + } + } +}; + +#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +/* GDMA Channel (Group0, Pair0) Registers Context + Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG + GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG + GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG + GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 13 +#define G0P0_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH0_REG +#define G0P0_RETENTION_REGS_CNT_1 2 +#define G0P0_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG +static const uint32_t g0p0_regs_map0[4] = {0x4C801001, 0x604C0060, 0, 0}; +static const uint32_t g0p0_regs_map1[4] = {0x3, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, +}; + +/* GDMA Channel (Group0, Pair1) Registers Context + Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG + GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG + GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG + GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG +*/ +#define G0P1_RETENTION_REGS_CNT_0 13 +#define G0P1_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH1_REG +#define G0P1_RETENTION_REGS_CNT_1 2 +#define G0P1_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG +static const uint32_t g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const uint32_t g0p1_regs_map1[4] = {0x3, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, +}; + +/* GDMA Channel (Group0, Pair2) Registers Context + Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG + GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG + GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG + GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG +#define G0P2_RETENTION_REGS_CNT_1 9 +#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t g0p2_regs_map1[4] = {0xf026003, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, +}; + +const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_PAIRS_PER_GROUP_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { + [0] = { + [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)}, + [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)}, + [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)} + } +}; +#endif diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index ce60b9616a..5f195f86ff 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -7,10 +7,22 @@ config SOC_UART_SUPPORTED bool default y +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_AHB_GDMA_SUPPORTED + bool + default y + config SOC_GPTIMER_SUPPORTED bool default y +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y @@ -115,6 +127,18 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP bool default y +config SOC_AHB_GDMA_VERSION + int + default 1 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 3 + config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32c5/include/soc/gdma_channel.h b/components/soc/esp32c5/include/soc/gdma_channel.h index 2fdaa3f146..73ba4976f6 100644 --- a/components/soc/esp32c5/include/soc/gdma_channel.h +++ b/components/soc/esp32c5/include/soc/gdma_channel.h @@ -1,13 +1,11 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -// TODO: [ESP32C5] IDF-8710 - // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) diff --git a/components/soc/esp32c5/include/soc/gdma_struct.h b/components/soc/esp32c5/include/soc/gdma_struct.h index ec5e9a5ad9..f43ed4365b 100644 --- a/components/soc/esp32c5/include/soc/gdma_struct.h +++ b/components/soc/esp32c5/include/soc/gdma_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,45 +16,45 @@ extern "C" { */ typedef union { struct { - /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received for Rx channel n. */ - uint32_t in_done_chn_int_raw:1; - /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + uint32_t in_done_int_raw:1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received for Rx channel n. For UHCI0 the raw interrupt bit * turns to high level when the last data pointed by one inlink descriptor has been * received and no data error is detected for Rx channel n. */ - uint32_t in_suc_eof_chn_int_raw:1; - /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_raw:1; + /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when data error is detected only in the * case that the peripheral is UHCI0 for Rx channel n. For other peripherals this raw * interrupt is reserved. */ - uint32_t in_err_eof_chn_int_raw:1; - /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_raw:1; + /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when detecting inlink descriptor error * including owner error and the second and third word error of inlink descriptor for * Rx channel n. */ - uint32_t in_dscr_err_chn_int_raw:1; - /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_raw:1; + /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full * and receiving data is not completed but there is no more inlink for Rx channel n. */ - uint32_t in_dscr_empty_chn_int_raw:1; - /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + uint32_t in_dscr_empty_int_raw:1; + /** infifo_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is * overflow. */ - uint32_t infifo_ovf_chn_int_raw:1; - /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + uint32_t infifo_ovf_int_raw:1; + /** infifo_udf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is * underflow. */ - uint32_t infifo_udf_chn_int_raw:1; + uint32_t infifo_udf_int_raw:1; uint32_t reserved_7:25; }; uint32_t val; @@ -65,34 +65,34 @@ typedef union { */ typedef union { struct { - /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; + /** in_done_int_st : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_chn_int_st:1; - /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; + uint32_t in_done_int_st:1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_chn_int_st:1; - /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_st:1; + /** in_err_eof_int_st : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t in_err_eof_chn_int_st:1; - /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_st:1; + /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t in_dscr_err_chn_int_st:1; - /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_st:1; + /** in_dscr_empty_int_st : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t in_dscr_empty_chn_int_st:1; - /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; + uint32_t in_dscr_empty_int_st:1; + /** infifo_ovf_int_st : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_chn_int_st:1; - /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; + uint32_t infifo_ovf_int_st:1; + /** infifo_udf_int_st : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_chn_int_st:1; + uint32_t infifo_udf_int_st:1; uint32_t reserved_7:25; }; uint32_t val; @@ -103,34 +103,34 @@ typedef union { */ typedef union { struct { - /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_chn_int_ena:1; - /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + uint32_t in_done_int_ena:1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_chn_int_ena:1; - /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_ena:1; + /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t in_err_eof_chn_int_ena:1; - /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_ena:1; + /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t in_dscr_err_chn_int_ena:1; - /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_ena:1; + /** in_dscr_empty_int_ena : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t in_dscr_empty_chn_int_ena:1; - /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; + uint32_t in_dscr_empty_int_ena:1; + /** infifo_ovf_int_ena : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_chn_int_ena:1; - /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; + uint32_t infifo_ovf_int_ena:1; + /** infifo_udf_int_ena : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_chn_int_ena:1; + uint32_t infifo_udf_int_ena:1; uint32_t reserved_7:25; }; uint32_t val; @@ -141,34 +141,34 @@ typedef union { */ typedef union { struct { - /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; + /** in_done_int_clr : WT; bitpos: [0]; default: 0; * Set this bit to clear the IN_DONE_CH_INT interrupt. */ - uint32_t in_done_chn_int_clr:1; - /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + uint32_t in_done_int_clr:1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t in_suc_eof_chn_int_clr:1; - /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; + uint32_t in_suc_eof_int_clr:1; + /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0; * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t in_err_eof_chn_int_clr:1; - /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; + uint32_t in_err_eof_int_clr:1; + /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0; * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t in_dscr_err_chn_int_clr:1; - /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; + uint32_t in_dscr_err_int_clr:1; + /** in_dscr_empty_int_clr : WT; bitpos: [4]; default: 0; * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t in_dscr_empty_chn_int_clr:1; - /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; + uint32_t in_dscr_empty_int_clr:1; + /** infifo_ovf_int_clr : WT; bitpos: [5]; default: 0; * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t infifo_ovf_chn_int_clr:1; - /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; + uint32_t infifo_ovf_int_clr:1; + /** infifo_udf_int_clr : WT; bitpos: [6]; default: 0; * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t infifo_udf_chn_int_clr:1; + uint32_t infifo_udf_int_clr:1; uint32_t reserved_7:25; }; uint32_t val; @@ -181,38 +181,38 @@ typedef union { */ typedef union { struct { - /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + /** out_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink * descriptor has been transmitted to peripherals for Tx channel n. */ - uint32_t out_done_chn_int_raw:1; - /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + uint32_t out_done_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink * descriptor has been read from memory for Tx channel n. */ - uint32_t out_eof_chn_int_raw:1; - /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + uint32_t out_eof_int_raw:1; + /** out_dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when detecting outlink descriptor error * including owner error and the second and third word error of outlink descriptor for * Tx channel n. */ - uint32_t out_dscr_err_chn_int_raw:1; - /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + uint32_t out_dscr_err_int_raw:1; + /** out_total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when data corresponding a outlink * (includes one link descriptor or few link descriptors) is transmitted out for Tx * channel n. */ - uint32_t out_total_eof_chn_int_raw:1; - /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t out_total_eof_int_raw:1; + /** outfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is * overflow. */ - uint32_t outfifo_ovf_chn_int_raw:1; - /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_int_raw:1; + /** outfifo_udf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is * underflow. */ - uint32_t outfifo_udf_chn_int_raw:1; + uint32_t outfifo_udf_int_raw:1; uint32_t reserved_6:26; }; uint32_t val; @@ -223,30 +223,30 @@ typedef union { */ typedef union { struct { - /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; + /** out_done_int_st : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - uint32_t out_done_chn_int_st:1; - /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; + uint32_t out_done_int_st:1; + /** out_eof_int_st : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - uint32_t out_eof_chn_int_st:1; - /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; + uint32_t out_eof_int_st:1; + /** out_dscr_err_int_st : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_dscr_err_chn_int_st:1; - /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; + uint32_t out_dscr_err_int_st:1; + /** out_total_eof_int_st : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t out_total_eof_chn_int_st:1; - /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; + uint32_t out_total_eof_int_st:1; + /** outfifo_ovf_int_st : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_chn_int_st:1; - /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_int_st:1; + /** outfifo_udf_int_st : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_chn_int_st:1; + uint32_t outfifo_udf_int_st:1; uint32_t reserved_6:26; }; uint32_t val; @@ -257,30 +257,30 @@ typedef union { */ typedef union { struct { - /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + /** out_done_int_ena : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - uint32_t out_done_chn_int_ena:1; - /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + uint32_t out_done_int_ena:1; + /** out_eof_int_ena : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - uint32_t out_eof_chn_int_ena:1; - /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; + uint32_t out_eof_int_ena:1; + /** out_dscr_err_int_ena : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_dscr_err_chn_int_ena:1; - /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; + uint32_t out_dscr_err_int_ena:1; + /** out_total_eof_int_ena : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t out_total_eof_chn_int_ena:1; - /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t out_total_eof_int_ena:1; + /** outfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_chn_int_ena:1; - /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_int_ena:1; + /** outfifo_udf_int_ena : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_chn_int_ena:1; + uint32_t outfifo_udf_int_ena:1; uint32_t reserved_6:26; }; uint32_t val; @@ -291,30 +291,30 @@ typedef union { */ typedef union { struct { - /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; + /** out_done_int_clr : WT; bitpos: [0]; default: 0; * Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - uint32_t out_done_chn_int_clr:1; - /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + uint32_t out_done_int_clr:1; + /** out_eof_int_clr : WT; bitpos: [1]; default: 0; * Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - uint32_t out_eof_chn_int_clr:1; - /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; + uint32_t out_eof_int_clr:1; + /** out_dscr_err_int_clr : WT; bitpos: [2]; default: 0; * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_dscr_err_chn_int_clr:1; - /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; + uint32_t out_dscr_err_int_clr:1; + /** out_total_eof_int_clr : WT; bitpos: [3]; default: 0; * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t out_total_eof_chn_int_clr:1; - /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; + uint32_t out_total_eof_int_clr:1; + /** outfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_chn_int_clr:1; - /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; + uint32_t outfifo_ovf_int_clr:1; + /** outfifo_udf_int_clr : WT; bitpos: [5]; default: 0; * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_chn_int_clr:1; + uint32_t outfifo_udf_int_clr:1; uint32_t reserved_6:26; }; uint32_t val; @@ -389,33 +389,33 @@ typedef union { */ typedef union { struct { - /** in_rst_chn : R/W; bitpos: [0]; default: 0; + /** in_rst : R/W; bitpos: [0]; default: 0; * This bit is used to reset DMA channel n Rx FSM and Rx FIFO pointer. */ - uint32_t in_rst_chn:1; - /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + uint32_t in_rst:1; + /** in_loop_test : R/W; bitpos: [1]; default: 0; * reserved */ - uint32_t in_loop_test_chn:1; - /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + uint32_t in_loop_test:1; + /** indscr_burst_en : R/W; bitpos: [2]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Rx channel n reading link * descriptor when accessing internal SRAM. */ - uint32_t indscr_burst_en_chn:1; - /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + uint32_t indscr_burst_en:1; + /** in_data_burst_en : R/W; bitpos: [3]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Rx channel n receiving data * when accessing internal SRAM. */ - uint32_t in_data_burst_en_chn:1; - /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + uint32_t in_data_burst_en:1; + /** mem_trans_en : R/W; bitpos: [4]; default: 0; * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. */ - uint32_t mem_trans_en_chn:1; - /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + uint32_t mem_trans_en:1; + /** in_etm_en : R/W; bitpos: [5]; default: 0; * Set this bit to 1 to enable etm control mode, dma Rx channel n is triggered by etm * task. */ - uint32_t in_etm_en_chn:1; + uint32_t in_etm_en:1; uint32_t reserved_6:26; }; uint32_t val; @@ -427,10 +427,10 @@ typedef union { typedef union { struct { uint32_t reserved_0:12; - /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + /** in_check_owner : R/W; bitpos: [12]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ - uint32_t in_check_owner_chn:1; + uint32_t in_check_owner:1; uint32_t reserved_13:19; }; uint32_t val; @@ -441,39 +441,39 @@ typedef union { */ typedef union { struct { - /** infifo_full_chn : RO; bitpos: [0]; default: 1; + /** infifo_full : RO; bitpos: [0]; default: 1; * L1 Rx FIFO full signal for Rx channel n. */ - uint32_t infifo_full_chn:1; - /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + uint32_t infifo_full:1; + /** infifo_empty : RO; bitpos: [1]; default: 1; * L1 Rx FIFO empty signal for Rx channel n. */ - uint32_t infifo_empty_chn:1; - /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + uint32_t infifo_empty:1; + /** infifo_cnt : RO; bitpos: [7:2]; default: 0; * The register stores the byte number of the data in L1 Rx FIFO for Rx channel n. */ - uint32_t infifo_cnt_chn:6; + uint32_t infifo_cnt:6; uint32_t reserved_8:15; - /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + /** in_remain_under_1b : RO; bitpos: [23]; default: 1; * reserved */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + uint32_t in_remain_under_1b:1; + /** in_remain_under_2b : RO; bitpos: [24]; default: 1; * reserved */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + uint32_t in_remain_under_2b:1; + /** in_remain_under_3b : RO; bitpos: [25]; default: 1; * reserved */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + uint32_t in_remain_under_3b:1; + /** in_remain_under_4b : RO; bitpos: [26]; default: 1; * reserved */ - uint32_t in_remain_under_4b_chn:1; - /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + uint32_t in_remain_under_4b:1; + /** in_buf_hungry : RO; bitpos: [27]; default: 0; * reserved */ - uint32_t in_buf_hungry_chn:1; + uint32_t in_buf_hungry:1; uint32_t reserved_28:4; }; uint32_t val; @@ -484,14 +484,14 @@ typedef union { */ typedef union { struct { - /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + /** infifo_rdata : RO; bitpos: [11:0]; default: 2048; * This register stores the data popping from DMA FIFO. */ - uint32_t infifo_rdata_chn:12; - /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + uint32_t infifo_rdata:12; + /** infifo_pop : WT; bitpos: [12]; default: 0; * Set this bit to pop data from DMA FIFO. */ - uint32_t infifo_pop_chn:1; + uint32_t infifo_pop:1; uint32_t reserved_13:19; }; uint32_t val; @@ -502,33 +502,33 @@ typedef union { */ typedef union { struct { - /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + /** inlink_addr : R/W; bitpos: [19:0]; default: 0; * This register stores the 20 least significant bits of the first inlink descriptor's * address. */ - uint32_t inlink_addr_chn:20; - /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + uint32_t inlink_addr:20; + /** inlink_auto_ret : R/W; bitpos: [20]; default: 1; * Set this bit to return to current inlink descriptor's address when there are some * errors in current receiving data. */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + uint32_t inlink_auto_ret:1; + /** inlink_stop : WT; bitpos: [21]; default: 0; * Set this bit to stop dealing with the inlink descriptors. */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : WT; bitpos: [22]; default: 0; + uint32_t inlink_stop:1; + /** inlink_start : WT; bitpos: [22]; default: 0; * Set this bit to start dealing with the inlink descriptors. */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + uint32_t inlink_start:1; + /** inlink_restart : WT; bitpos: [23]; default: 0; * Set this bit to mount a new inlink descriptor. */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [24]; default: 1; + uint32_t inlink_restart:1; + /** inlink_park : RO; bitpos: [24]; default: 1; * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is * working. */ - uint32_t inlink_park_chn:1; + uint32_t inlink_park:1; uint32_t reserved_25:7; }; uint32_t val; @@ -539,18 +539,18 @@ typedef union { */ typedef union { struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0; * This register stores the current inlink descriptor's address. */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + uint32_t inlink_dscr_addr:18; + /** in_dscr_state : RO; bitpos: [19:18]; default: 0; * reserved */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; + uint32_t in_dscr_state:2; + /** in_state : RO; bitpos: [22:20]; default: 0; * reserved */ - uint32_t in_state_chn:3; + uint32_t in_state:3; uint32_t reserved_23:9; }; uint32_t val; @@ -561,11 +561,11 @@ typedef union { */ typedef union { struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when the EOF bit in this * descriptor is 1. */ - uint32_t in_suc_eof_des_addr_chn:32; + uint32_t in_suc_eof_des_addr:32; }; uint32_t val; } gdma_in_suc_eof_des_addr_chn_reg_t; @@ -575,11 +575,11 @@ typedef union { */ typedef union { struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when there are some * errors in current receiving data. Only used when peripheral is UHCI0. */ - uint32_t in_err_eof_des_addr_chn:32; + uint32_t in_err_eof_des_addr:32; }; uint32_t val; } gdma_in_err_eof_des_addr_chn_reg_t; @@ -589,10 +589,10 @@ typedef union { */ typedef union { struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + /** inlink_dscr : RO; bitpos: [31:0]; default: 0; * The address of the current inlink descriptor x. */ - uint32_t inlink_dscr_chn:32; + uint32_t inlink_dscr:32; }; uint32_t val; } gdma_in_dscr_chn_reg_t; @@ -602,10 +602,10 @@ typedef union { */ typedef union { struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; * The address of the last inlink descriptor x-1. */ - uint32_t inlink_dscr_bf0_chn:32; + uint32_t inlink_dscr_bf0:32; }; uint32_t val; } gdma_in_dscr_bf0_chn_reg_t; @@ -615,10 +615,10 @@ typedef union { */ typedef union { struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; * The address of the second-to-last inlink descriptor x-2. */ - uint32_t inlink_dscr_bf1_chn:32; + uint32_t inlink_dscr_bf1:32; }; uint32_t val; } gdma_in_dscr_bf1_chn_reg_t; @@ -628,10 +628,10 @@ typedef union { */ typedef union { struct { - /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + /** rx_pri : R/W; bitpos: [3:0]; default: 0; * The priority of Rx channel n. The larger of the value the higher of the priority. */ - uint32_t rx_pri_chn:4; + uint32_t rx_pri:4; uint32_t reserved_4:28; }; uint32_t val; @@ -642,12 +642,12 @@ typedef union { */ typedef union { struct { - /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + /** peri_in_sel : R/W; bitpos: [5:0]; default: 63; * This register is used to select peripheral for Rx channel n. 0:SPI2. 1: Dummy. 2: * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. * 10~15: Dummy */ - uint32_t peri_in_sel_chn:6; + uint32_t peri_in_sel:6; uint32_t reserved_6:26; }; uint32_t val; @@ -658,39 +658,39 @@ typedef union { */ typedef union { struct { - /** out_rst_chn : R/W; bitpos: [0]; default: 0; + /** out_rst : R/W; bitpos: [0]; default: 0; * This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer. */ - uint32_t out_rst_chn:1; - /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + uint32_t out_rst:1; + /** out_loop_test : R/W; bitpos: [1]; default: 0; * reserved */ - uint32_t out_loop_test_chn:1; - /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + uint32_t out_loop_test:1; + /** out_auto_wrback : R/W; bitpos: [2]; default: 0; * Set this bit to enable automatic outlink-writeback when all the data in tx buffer * has been transmitted. */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + uint32_t out_auto_wrback:1; + /** out_eof_mode : R/W; bitpos: [3]; default: 1; * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is * generated when data need to transmit has been popped from FIFO in DMA */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + uint32_t out_eof_mode:1; + /** outdscr_burst_en : R/W; bitpos: [4]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link * descriptor when accessing internal SRAM. */ - uint32_t outdscr_burst_en_chn:1; - /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + uint32_t outdscr_burst_en:1; + /** out_data_burst_en : R/W; bitpos: [5]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data * when accessing internal SRAM. */ - uint32_t out_data_burst_en_chn:1; - /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + uint32_t out_data_burst_en:1; + /** out_etm_en : R/W; bitpos: [6]; default: 0; * Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm * task. */ - uint32_t out_etm_en_chn:1; + uint32_t out_etm_en:1; uint32_t reserved_7:25; }; uint32_t val; @@ -702,10 +702,10 @@ typedef union { typedef union { struct { uint32_t reserved_0:12; - /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + /** out_check_owner : R/W; bitpos: [12]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ - uint32_t out_check_owner_chn:1; + uint32_t out_check_owner:1; uint32_t reserved_13:19; }; uint32_t val; @@ -716,35 +716,35 @@ typedef union { */ typedef union { struct { - /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + /** outfifo_full : RO; bitpos: [0]; default: 0; * L1 Tx FIFO full signal for Tx channel n. */ - uint32_t outfifo_full_chn:1; - /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + uint32_t outfifo_full:1; + /** outfifo_empty : RO; bitpos: [1]; default: 1; * L1 Tx FIFO empty signal for Tx channel n. */ - uint32_t outfifo_empty_chn:1; - /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + uint32_t outfifo_empty:1; + /** outfifo_cnt : RO; bitpos: [7:2]; default: 0; * The register stores the byte number of the data in L1 Tx FIFO for Tx channel n. */ - uint32_t outfifo_cnt_chn:6; + uint32_t outfifo_cnt:6; uint32_t reserved_8:15; - /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + /** out_remain_under_1b : RO; bitpos: [23]; default: 1; * reserved */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + uint32_t out_remain_under_1b:1; + /** out_remain_under_2b : RO; bitpos: [24]; default: 1; * reserved */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + uint32_t out_remain_under_2b:1; + /** out_remain_under_3b : RO; bitpos: [25]; default: 1; * reserved */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + uint32_t out_remain_under_3b:1; + /** out_remain_under_4b : RO; bitpos: [26]; default: 1; * reserved */ - uint32_t out_remain_under_4b_chn:1; + uint32_t out_remain_under_4b:1; uint32_t reserved_27:5; }; uint32_t val; @@ -755,14 +755,14 @@ typedef union { */ typedef union { struct { - /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + /** outfifo_wdata : R/W; bitpos: [8:0]; default: 0; * This register stores the data that need to be pushed into DMA FIFO. */ - uint32_t outfifo_wdata_chn:9; - /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + uint32_t outfifo_wdata:9; + /** outfifo_push : WT; bitpos: [9]; default: 0; * Set this bit to push data into DMA FIFO. */ - uint32_t outfifo_push_chn:1; + uint32_t outfifo_push:1; uint32_t reserved_10:22; }; uint32_t val; @@ -773,28 +773,28 @@ typedef union { */ typedef union { struct { - /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + /** outlink_addr : R/W; bitpos: [19:0]; default: 0; * This register stores the 20 least significant bits of the first outlink * descriptor's address. */ - uint32_t outlink_addr_chn:20; - /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + uint32_t outlink_addr:20; + /** outlink_stop : WT; bitpos: [20]; default: 0; * Set this bit to stop dealing with the outlink descriptors. */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : WT; bitpos: [21]; default: 0; + uint32_t outlink_stop:1; + /** outlink_start : WT; bitpos: [21]; default: 0; * Set this bit to start dealing with the outlink descriptors. */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + uint32_t outlink_start:1; + /** outlink_restart : WT; bitpos: [22]; default: 0; * Set this bit to restart a new outlink from the last address. */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [23]; default: 1; + uint32_t outlink_restart:1; + /** outlink_park : RO; bitpos: [23]; default: 1; * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM * is working. */ - uint32_t outlink_park_chn:1; + uint32_t outlink_park:1; uint32_t reserved_24:8; }; uint32_t val; @@ -805,18 +805,18 @@ typedef union { */ typedef union { struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0; * This register stores the current outlink descriptor's address. */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + uint32_t outlink_dscr_addr:18; + /** out_dscr_state : RO; bitpos: [19:18]; default: 0; * reserved */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [22:20]; default: 0; + uint32_t out_dscr_state:2; + /** out_state : RO; bitpos: [22:20]; default: 0; * reserved */ - uint32_t out_state_chn:3; + uint32_t out_state:3; uint32_t reserved_23:9; }; uint32_t val; @@ -827,11 +827,11 @@ typedef union { */ typedef union { struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the outlink descriptor when the EOF bit in this * descriptor is 1. */ - uint32_t out_eof_des_addr_chn:32; + uint32_t out_eof_des_addr:32; }; uint32_t val; } gdma_out_eof_des_addr_chn_reg_t; @@ -841,11 +841,11 @@ typedef union { */ typedef union { struct { - /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + /** out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; * This register stores the address of the outlink descriptor before the last outlink * descriptor. */ - uint32_t out_eof_bfr_des_addr_chn:32; + uint32_t out_eof_bfr_des_addr:32; }; uint32_t val; } gdma_out_eof_bfr_des_addr_chn_reg_t; @@ -855,10 +855,10 @@ typedef union { */ typedef union { struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + /** outlink_dscr : RO; bitpos: [31:0]; default: 0; * The address of the current outlink descriptor y. */ - uint32_t outlink_dscr_chn:32; + uint32_t outlink_dscr:32; }; uint32_t val; } gdma_out_dscr_chn_reg_t; @@ -868,10 +868,10 @@ typedef union { */ typedef union { struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; * The address of the last outlink descriptor y-1. */ - uint32_t outlink_dscr_bf0_chn:32; + uint32_t outlink_dscr_bf0:32; }; uint32_t val; } gdma_out_dscr_bf0_chn_reg_t; @@ -881,10 +881,10 @@ typedef union { */ typedef union { struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; * The address of the second-to-last inlink descriptor x-2. */ - uint32_t outlink_dscr_bf1_chn:32; + uint32_t outlink_dscr_bf1:32; }; uint32_t val; } gdma_out_dscr_bf1_chn_reg_t; @@ -894,10 +894,10 @@ typedef union { */ typedef union { struct { - /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + /** tx_pri : R/W; bitpos: [3:0]; default: 0; * The priority of Tx channel n. The larger of the value the higher of the priority. */ - uint32_t tx_pri_chn:4; + uint32_t tx_pri:4; uint32_t reserved_4:28; }; uint32_t val; @@ -908,12 +908,12 @@ typedef union { */ typedef union { struct { - /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + /** peri_out_sel : R/W; bitpos: [5:0]; default: 63; * This register is used to select peripheral for Tx channel n. 0:SPI2. 1: Dummy. 2: * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. * 10~15: Dummy */ - uint32_t peri_out_sel_chn:6; + uint32_t peri_out_sel:6; uint32_t reserved_6:26; }; uint32_t val; @@ -965,119 +965,70 @@ typedef union { uint32_t val; } gdma_bt_rx_sel_reg_t; +typedef struct { + volatile gdma_in_int_raw_chn_reg_t raw; + volatile gdma_in_int_st_chn_reg_t st; + volatile gdma_in_int_ena_chn_reg_t ena; + volatile gdma_in_int_clr_chn_reg_t clr; +} gdma_in_int_chn_reg_t; -typedef struct gdma_dev_t { - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch2; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch2; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2; +typedef struct { + volatile gdma_out_int_raw_chn_reg_t raw; + volatile gdma_out_int_st_chn_reg_t st; + volatile gdma_out_int_ena_chn_reg_t ena; + volatile gdma_out_int_clr_chn_reg_t clr; +} gdma_out_int_chn_reg_t; + +typedef struct { + volatile gdma_in_conf0_chn_reg_t in_conf0; + volatile gdma_in_conf1_chn_reg_t in_conf1; + volatile gdma_infifo_status_chn_reg_t infifo_status; + volatile gdma_in_pop_chn_reg_t in_pop; + volatile gdma_in_link_chn_reg_t in_link; + volatile gdma_in_state_chn_reg_t in_state; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; + volatile gdma_in_dscr_chn_reg_t in_dscr; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1; + volatile gdma_in_pri_chn_reg_t in_pri; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel; +} gdma_in_chn_reg_t; + +typedef struct { + volatile gdma_out_conf0_chn_reg_t out_conf0; + volatile gdma_out_conf1_chn_reg_t out_conf1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status; + volatile gdma_out_push_chn_reg_t out_push; + volatile gdma_out_link_chn_reg_t out_link; + volatile gdma_out_state_chn_reg_t out_state; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; + volatile gdma_out_dscr_chn_reg_t out_dscr; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1; + volatile gdma_out_pri_chn_reg_t out_pri; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel; +} gdma_out_chn_reg_t; + +typedef struct { + volatile gdma_in_chn_reg_t in; + uint32_t reserved_in[11]; + volatile gdma_out_chn_reg_t out; +} gdma_chn_reg_t; + +typedef struct gdma_dev_s { + volatile gdma_in_int_chn_reg_t in_intr[3]; + volatile gdma_out_int_chn_reg_t out_intr[3]; volatile gdma_ahb_test_reg_t ahb_test; volatile gdma_misc_conf_reg_t misc_conf; volatile gdma_date_reg_t date; uint32_t reserved_06c; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; - volatile gdma_in_pop_chn_reg_t in_pop_ch0; - volatile gdma_in_link_chn_reg_t in_link_ch0; - volatile gdma_in_state_chn_reg_t in_state_ch0; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; - volatile gdma_in_pri_chn_reg_t in_pri_ch0; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; - uint32_t reserved_0a4[11]; - volatile gdma_out_conf0_chn_reg_t out_conf0_ch0; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; - volatile gdma_out_push_chn_reg_t out_push_ch0; - volatile gdma_out_link_chn_reg_t out_link_ch0; - volatile gdma_out_state_chn_reg_t out_state_ch0; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; - volatile gdma_out_pri_chn_reg_t out_pri_ch0; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; + volatile gdma_chn_reg_t channel0; uint32_t reserved_104[11]; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; - volatile gdma_in_pop_chn_reg_t in_pop_ch1; - volatile gdma_in_link_chn_reg_t in_link_ch1; - volatile gdma_in_state_chn_reg_t in_state_ch1; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; - volatile gdma_in_pri_chn_reg_t in_pri_ch1; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; - uint32_t reserved_164[11]; - volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; - volatile gdma_out_push_chn_reg_t out_push_ch1; - volatile gdma_out_link_chn_reg_t out_link_ch1; - volatile gdma_out_state_chn_reg_t out_state_ch1; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; - volatile gdma_out_pri_chn_reg_t out_pri_ch1; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; + volatile gdma_chn_reg_t channel1; uint32_t reserved_1c4[11]; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch2; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch2; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch2; - volatile gdma_in_pop_chn_reg_t in_pop_ch2; - volatile gdma_in_link_chn_reg_t in_link_ch2; - volatile gdma_in_state_chn_reg_t in_state_ch2; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch2; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; - volatile gdma_in_pri_chn_reg_t in_pri_ch2; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2; - uint32_t reserved_224[11]; - volatile gdma_out_conf0_chn_reg_t out_conf0_ch2; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch2; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2; - volatile gdma_out_push_chn_reg_t out_push_ch2; - volatile gdma_out_link_chn_reg_t out_link_ch2; - volatile gdma_out_state_chn_reg_t out_state_ch2; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch2; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; - volatile gdma_out_pri_chn_reg_t out_pri_ch2; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2; + volatile gdma_chn_reg_t channel2; volatile gdma_bt_tx_sel_reg_t bt_tx_sel; volatile gdma_bt_rx_sel_reg_t bt_rx_sel; } gdma_dev_t; diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index abd5b015c6..ec53f6e3bb 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -20,15 +20,15 @@ // #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701 // #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725 #define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722 -// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 -// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683 // #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 // #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693 // #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686 -// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32C5] IDF-8716 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 // #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 // #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 @@ -56,7 +56,7 @@ #define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622 // #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 -// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614 +// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615 // #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 // #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 // #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 @@ -164,10 +164,11 @@ // #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ -// #define SOC_AHB_GDMA_VERSION 1U -// #define SOC_GDMA_NUM_GROUPS_MAX 1U -// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9224 +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225 /*-------------------------- ETM CAPS --------------------------------------*/ // #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32c5/include/soc/soc_etm_source.h b/components/soc/esp32c5/include/soc/soc_etm_source.h new file mode 100644 index 0000000000..e8b7e4a951 --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_etm_source.h @@ -0,0 +1,300 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define GPIO_EVT_ZERO_DET_POS 25 +#define GPIO_EVT_ZERO_DET_NEG 26 +#define LEDC_EVT_DUTY_CHNG_END_CH0 27 +#define LEDC_EVT_DUTY_CHNG_END_CH1 28 +#define LEDC_EVT_DUTY_CHNG_END_CH2 29 +#define LEDC_EVT_DUTY_CHNG_END_CH3 30 +#define LEDC_EVT_DUTY_CHNG_END_CH4 31 +#define LEDC_EVT_DUTY_CHNG_END_CH5 32 +#define LEDC_EVT_OVF_CNT_PLS_CH0 33 +#define LEDC_EVT_OVF_CNT_PLS_CH1 34 +#define LEDC_EVT_OVF_CNT_PLS_CH2 35 +#define LEDC_EVT_OVF_CNT_PLS_CH3 36 +#define LEDC_EVT_OVF_CNT_PLS_CH4 37 +#define LEDC_EVT_OVF_CNT_PLS_CH5 38 +#define LEDC_EVT_TIME_OVF_TIMER0 39 +#define LEDC_EVT_TIME_OVF_TIMER1 40 +#define LEDC_EVT_TIME_OVF_TIMER2 41 +#define LEDC_EVT_TIME_OVF_TIMER3 42 +#define LEDC_EVT_TIMER0_CMP 43 +#define LEDC_EVT_TIMER1_CMP 44 +#define LEDC_EVT_TIMER2_CMP 45 +#define LEDC_EVT_TIMER3_CMP 46 +#define TG0_EVT_CNT_CMP_TIMER0 47 +#define TG0_EVT_CNT_CMP_TIMER1 48 +#define TG1_EVT_CNT_CMP_TIMER0 49 +#define TG1_EVT_CNT_CMP_TIMER1 50 +#define SYSTIMER_EVT_CNT_CMP0 51 +#define SYSTIMER_EVT_CNT_CMP1 52 +#define SYSTIMER_EVT_CNT_CMP2 53 +#define MCPWM0_EVT_TIMER0_STOP 54 +#define MCPWM0_EVT_TIMER1_STOP 55 +#define MCPWM0_EVT_TIMER2_STOP 56 +#define MCPWM0_EVT_TIMER0_TEZ 57 +#define MCPWM0_EVT_TIMER1_TEZ 58 +#define MCPWM0_EVT_TIMER2_TEZ 59 +#define MCPWM0_EVT_TIMER0_TEP 60 +#define MCPWM0_EVT_TIMER1_TEP 61 +#define MCPWM0_EVT_TIMER2_TEP 62 +#define MCPWM0_EVT_OP0_TEA 63 +#define MCPWM0_EVT_OP1_TEA 64 +#define MCPWM0_EVT_OP2_TEA 65 +#define MCPWM0_EVT_OP0_TEB 66 +#define MCPWM0_EVT_OP1_TEB 67 +#define MCPWM0_EVT_OP2_TEB 68 +#define MCPWM0_EVT_F0 69 +#define MCPWM0_EVT_F1 70 +#define MCPWM0_EVT_F2 71 +#define MCPWM0_EVT_F0_CLR 72 +#define MCPWM0_EVT_F1_CLR 73 +#define MCPWM0_EVT_F2_CLR 74 +#define MCPWM0_EVT_TZ0_CBC 75 +#define MCPWM0_EVT_TZ1_CBC 76 +#define MCPWM0_EVT_TZ2_CBC 77 +#define MCPWM0_EVT_TZ0_OST 78 +#define MCPWM0_EVT_TZ1_OST 79 +#define MCPWM0_EVT_TZ2_OST 80 +#define MCPWM0_EVT_CAP0 81 +#define MCPWM0_EVT_CAP1 82 +#define MCPWM0_EVT_CAP2 83 +#define MCPWM0_EVT_OP0_TEE1 84 +#define MCPWM0_EVT_OP1_TEE1 85 +#define MCPWM0_EVT_OP2_TEE1 86 +#define MCPWM0_EVT_OP0_TEE2 87 +#define MCPWM0_EVT_OP1_TEE2 88 +#define MCPWM0_EVT_OP2_TEE2 89 +#define ADC_EVT_CONV_CMPLT0 90 +#define ADC_EVT_EQ_ABOVE_THRESH0 91 +#define ADC_EVT_EQ_ABOVE_THRESH1 92 +#define ADC_EVT_EQ_BELOW_THRESH0 93 +#define ADC_EVT_EQ_BELOW_THRESH1 94 +#define ADC_EVT_RESULT_DONE0 95 +#define ADC_EVT_STOPPED0 96 +#define ADC_EVT_STARTED0 97 +#define REGDMA_EVT_DONE0 98 +#define REGDMA_EVT_DONE1 99 +#define REGDMA_EVT_DONE2 100 +#define REGDMA_EVT_DONE3 101 +#define REGDMA_EVT_ERR0 102 +#define REGDMA_EVT_ERR1 103 +#define REGDMA_EVT_ERR2 104 +#define REGDMA_EVT_ERR3 105 +#define GDMA_EVT_IN_DONE_CH0 106 +#define GDMA_EVT_IN_DONE_CH1 107 +#define GDMA_EVT_IN_DONE_CH2 108 +#define GDMA_EVT_IN_SUC_EOF_CH0 109 +#define GDMA_EVT_IN_SUC_EOF_CH1 110 +#define GDMA_EVT_IN_SUC_EOF_CH2 111 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 112 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 113 +#define GDMA_EVT_IN_FIFO_EMPTY_CH2 114 +#define GDMA_EVT_IN_FIFO_FULL_CH0 115 +#define GDMA_EVT_IN_FIFO_FULL_CH1 116 +#define GDMA_EVT_IN_FIFO_FULL_CH2 117 +#define GDMA_EVT_OUT_DONE_CH0 118 +#define GDMA_EVT_OUT_DONE_CH1 119 +#define GDMA_EVT_OUT_DONE_CH2 120 +#define GDMA_EVT_OUT_EOF_CH0 121 +#define GDMA_EVT_OUT_EOF_CH1 122 +#define GDMA_EVT_OUT_EOF_CH2 123 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 124 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 125 +#define GDMA_EVT_OUT_TOTAL_EOF_CH2 126 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 127 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 128 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 129 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 130 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 131 +#define GDMA_EVT_OUT_FIFO_FULL_CH2 132 +#define TMPSNSR_EVT_OVER_LIMIT 133 +#define I2S0_EVT_RX_DONE 134 +#define I2S0_EVT_TX_DONE 135 +#define I2S0_EVT_X_WORDS_RECEIVED 136 +#define I2S0_EVT_X_WORDS_SENT 137 +#define ULP_EVT_ERR_INTR 138 +#define ULP_EVT_HALT 139 +#define ULP_EVT_START_INTR 140 +#define RTC_EVT_TICK 141 +#define RTC_EVT_OVF 142 +#define RTC_EVT_CMP 143 +#define PMU_EVT_SLEEP_WEEKUP 144 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34 +#define LEDC_TASK_TIMER0_CAP 35 +#define LEDC_TASK_TIMER1_CAP 36 +#define LEDC_TASK_TIMER2_CAP 37 +#define LEDC_TASK_TIMER3_CAP 38 +#define LEDC_TASK_SIG_OUT_DIS_CH0 39 +#define LEDC_TASK_SIG_OUT_DIS_CH1 40 +#define LEDC_TASK_SIG_OUT_DIS_CH2 41 +#define LEDC_TASK_SIG_OUT_DIS_CH3 42 +#define LEDC_TASK_SIG_OUT_DIS_CH4 43 +#define LEDC_TASK_SIG_OUT_DIS_CH5 44 +#define LEDC_TASK_OVF_CNT_RST_CH0 45 +#define LEDC_TASK_OVF_CNT_RST_CH1 46 +#define LEDC_TASK_OVF_CNT_RST_CH2 47 +#define LEDC_TASK_OVF_CNT_RST_CH3 48 +#define LEDC_TASK_OVF_CNT_RST_CH4 49 +#define LEDC_TASK_OVF_CNT_RST_CH5 50 +#define LEDC_TASK_TIMER0_RST 51 +#define LEDC_TASK_TIMER1_RST 52 +#define LEDC_TASK_TIMER2_RST 53 +#define LEDC_TASK_TIMER3_RST 54 +#define LEDC_TASK_TIMER0_RESUME 55 +#define LEDC_TASK_TIMER1_RESUME 56 +#define LEDC_TASK_TIMER2_RESUME 57 +#define LEDC_TASK_TIMER3_RESUME 58 +#define LEDC_TASK_TIMER0_PAUSE 59 +#define LEDC_TASK_TIMER1_PAUSE 60 +#define LEDC_TASK_TIMER2_PAUSE 61 +#define LEDC_TASK_TIMER3_PAUSE 62 +#define LEDC_TASK_GAMMA_RESTART_CH0 63 +#define LEDC_TASK_GAMMA_RESTART_CH1 64 +#define LEDC_TASK_GAMMA_RESTART_CH2 65 +#define LEDC_TASK_GAMMA_RESTART_CH3 66 +#define LEDC_TASK_GAMMA_RESTART_CH4 67 +#define LEDC_TASK_GAMMA_RESTART_CH5 68 +#define LEDC_TASK_GAMMA_PAUSE_CH0 69 +#define LEDC_TASK_GAMMA_PAUSE_CH1 70 +#define LEDC_TASK_GAMMA_PAUSE_CH2 71 +#define LEDC_TASK_GAMMA_PAUSE_CH3 72 +#define LEDC_TASK_GAMMA_PAUSE_CH4 73 +#define LEDC_TASK_GAMMA_PAUSE_CH5 74 +#define LEDC_TASK_GAMMA_RESUME_CH0 75 +#define LEDC_TASK_GAMMA_RESUME_CH1 76 +#define LEDC_TASK_GAMMA_RESUME_CH2 77 +#define LEDC_TASK_GAMMA_RESUME_CH3 78 +#define LEDC_TASK_GAMMA_RESUME_CH4 79 +#define LEDC_TASK_GAMMA_RESUME_CH5 80 +#define TG0_TASK_CNT_START_TIMER0 81 +#define TG0_TASK_ALARM_START_TIMER0 82 +#define TG0_TASK_CNT_STOP_TIMER0 83 +#define TG0_TASK_CNT_RELOAD_TIMER0 84 +#define TG0_TASK_CNT_CAP_TIMER0 85 +#define TG0_TASK_CNT_START_TIMER1 86 +#define TG0_TASK_ALARM_START_TIMER1 87 +#define TG0_TASK_CNT_STOP_TIMER1 88 +#define TG0_TASK_CNT_RELOAD_TIMER1 89 +#define TG0_TASK_CNT_CAP_TIMER1 90 +#define TG1_TASK_CNT_START_TIMER0 91 +#define TG1_TASK_ALARM_START_TIMER0 92 +#define TG1_TASK_CNT_STOP_TIMER0 93 +#define TG1_TASK_CNT_RELOAD_TIMER0 94 +#define TG1_TASK_CNT_CAP_TIMER0 95 +#define TG1_TASK_CNT_START_TIMER1 96 +#define TG1_TASK_ALARM_START_TIMER1 97 +#define TG1_TASK_CNT_STOP_TIMER1 98 +#define TG1_TASK_CNT_RELOAD_TIMER1 99 +#define TG1_TASK_CNT_CAP_TIMER1 100 +#define MCPWM0_TASK_CMPR0_A_UP 101 +#define MCPWM0_TASK_CMPR1_A_UP 102 +#define MCPWM0_TASK_CMPR2_A_UP 103 +#define MCPWM0_TASK_CMPR0_B_UP 104 +#define MCPWM0_TASK_CMPR1_B_UP 105 +#define MCPWM0_TASK_CMPR2_B_UP 106 +#define MCPWM0_TASK_GEN_STOP 107 +#define MCPWM0_TASK_TIMER0_SYN 108 +#define MCPWM0_TASK_TIMER1_SYN 109 +#define MCPWM0_TASK_TIMER2_SYN 110 +#define MCPWM0_TASK_TIMER0_PERIOD_UP 111 +#define MCPWM0_TASK_TIMER1_PERIOD_UP 112 +#define MCPWM0_TASK_TIMER2_PERIOD_UP 113 +#define MCPWM0_TASK_TZ0_OST 114 +#define MCPWM0_TASK_TZ1_OST 115 +#define MCPWM0_TASK_TZ2_OST 116 +#define MCPWM0_TASK_CLR0_OST 117 +#define MCPWM0_TASK_CLR1_OST 118 +#define MCPWM0_TASK_CLR2_OST 119 +#define MCPWM0_TASK_CAP0 120 +#define MCPWM0_TASK_CAP1 121 +#define MCPWM0_TASK_CAP2 122 +#define ADC_TASK_SAMPLE0 123 +#define ADC_TASK_SAMPLE1 124 +#define ADC_TASK_START0 125 +#define ADC_TASK_STOP0 126 +#define REGDMA_TASK_START0 127 +#define REGDMA_TASK_START1 128 +#define REGDMA_TASK_START2 129 +#define REGDMA_TASK_START3 130 +#define GDMA_TASK_IN_START_CH0 131 +#define GDMA_TASK_IN_START_CH1 132 +#define GDMA_TASK_IN_START_CH2 133 +#define GDMA_TASK_OUT_START_CH0 134 +#define GDMA_TASK_OUT_START_CH1 135 +#define GDMA_TASK_OUT_START_CH2 136 +#define TMPSNSR_TASK_START_SAMPLE 137 +#define TMPSNSR_TASK_STOP_SAMPLE 138 +#define I2S0_TASK_START_RX 139 +#define I2S0_TASK_START_TX 140 +#define I2S0_TASK_STOP_RX 141 +#define I2S0_TASK_STOP_TX 142 +#define ULP_TASK_WAKEUP_CPU 143 +#define ULP_TASK_INT_CPU 144 +#define RTC_TASK_START 145 +#define RTC_TASK_STOP 146 +#define RTC_TASK_CLR 147 +#define RTC_TASK_TRIGGERFLW 148 +#define PMU_TASK_SLEEP_REQ 149 diff --git a/components/soc/esp32c6/gdma_periph.c b/components/soc/esp32c6/gdma_periph.c index 0af0fe475b..40d421a6e7 100644 --- a/components/soc/esp32c6/gdma_periph.c +++ b/components/soc/esp32c6/gdma_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,22 +71,22 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG */ -#define G0P1_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_REGS_CNT_0 6 #define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG -#define G0P1_RETENTION_REGS_CNT_1 7 +#define G0P2_RETENTION_REGS_CNT_1 7 #define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ g0p2_regs_map0[2], g0p2_regs_map0[3]), \ .owner = ENTRY(0) | ENTRY(2) }, [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ g0p2_regs_map1[2], g0p2_regs_map1[3]), \ .owner = ENTRY(0) | ENTRY(2) }, diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 8ae015c118..79b2b3b9c6 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -419,6 +419,10 @@ config SOC_GDMA_SUPPORT_ETM bool default y +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_ETM_GROUPS int default 1 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 55c0ebf027..c4f060e221 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -162,10 +162,11 @@ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ -#define SOC_AHB_GDMA_VERSION 1U -#define SOC_GDMA_NUM_GROUPS_MAX 1U -#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32h2/gdma_periph.c b/components/soc/esp32h2/gdma_periph.c index 0af0fe475b..40d421a6e7 100644 --- a/components/soc/esp32h2/gdma_periph.c +++ b/components/soc/esp32h2/gdma_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,22 +71,22 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG */ -#define G0P1_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_REGS_CNT_0 6 #define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG -#define G0P1_RETENTION_REGS_CNT_1 7 +#define G0P2_RETENTION_REGS_CNT_1 7 #define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ g0p2_regs_map0[2], g0p2_regs_map0[3]), \ .owner = ENTRY(0) | ENTRY(2) }, [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ g0p2_regs_map1[2], g0p2_regs_map1[3]), \ .owner = ENTRY(0) | ENTRY(2) }, diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index e599f317a9..385bd0abde 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -423,6 +423,10 @@ config SOC_GDMA_SUPPORT_ETM bool default y +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_ETM_GROUPS int default 1 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index e90213a2dc..d024c53146 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -164,10 +164,11 @@ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ -#define SOC_AHB_GDMA_VERSION 1U -#define SOC_GDMA_NUM_GROUPS_MAX 1U -#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 93274a13f8..f138e25e2a 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -176,12 +176,13 @@ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ -#define SOC_AHB_GDMA_VERSION 2 -#define SOC_GDMA_SUPPORT_CRC 1 -#define SOC_GDMA_NUM_GROUPS_MAX 2 -#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -#define SOC_AXI_GDMA_SUPPORT_PSRAM 1 -#define SOC_GDMA_SUPPORT_ETM 1 +#define SOC_AHB_GDMA_VERSION 2 +#define SOC_GDMA_SUPPORT_CRC 1 +#define SOC_GDMA_NUM_GROUPS_MAX 2 +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +#define SOC_AXI_GDMA_SUPPORT_PSRAM 1 +#define SOC_GDMA_SUPPORT_ETM 1 +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- 2D-DMA CAPS -------------------------------------*/ #define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups diff --git a/components/soc/include/soc/gdma_periph.h b/components/soc/include/soc/gdma_periph.h index 5b2d9fc16c..2d44598080 100644 --- a/components/soc/include/soc/gdma_periph.h +++ b/components/soc/include/soc/gdma_periph.h @@ -30,7 +30,7 @@ typedef struct { extern const gdma_signal_conn_t gdma_periph_signals; -#if SOC_PM_SUPPORT_TOP_PD +#if SOC_GDMA_SUPPORT_SLEEP_RETENTION typedef struct { const regdma_entries_config_t *link_list; uint32_t link_num;