diff --git a/components/app_update/test_apps/test_app_update/README.md b/components/app_update/test_apps/test_app_update/README.md index 3a502b1f86..7b96141437 100644 --- a/components/app_update/test_apps/test_app_update/README.md +++ b/components/app_update/test_apps/test_app_update/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 5d4e92ffae..1955320698 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -751,7 +751,7 @@ void IRAM_ATTR call_start_cpu0(void) #endif #endif -#if SOC_DEEP_SLEEP_SUPPORTED //TODO: IDF-9245 +#if SOC_DEEP_SLEEP_SUPPORTED // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) { esp_deep_sleep_wakeup_io_reset(); diff --git a/components/hal/esp32c61/modem_clock_hal.c b/components/hal/esp32c61/modem_clock_hal.c index bfcf6cd2c7..fe84dcfb85 100644 --- a/components/hal/esp32c61/modem_clock_hal.c +++ b/components/hal/esp32c61/modem_clock_hal.c @@ -59,7 +59,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte } } -uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain) +uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index e39e711a97..4a904e190f 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -107,6 +107,10 @@ config SOC_LP_TIMER_SUPPORTED bool default y +config SOC_LP_AON_SUPPORTED + bool + default y + config SOC_CLK_TREE_SUPPORTED bool default y @@ -131,6 +135,10 @@ config SOC_LIGHT_SLEEP_SUPPORTED bool default y +config SOC_DEEP_SLEEP_SUPPORTED + bool + default y + config SOC_PM_SUPPORTED bool default y @@ -295,6 +303,10 @@ config SOC_GPIO_OUT_RANGE_MAX int default 21 +config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP + bool + default y + config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 @@ -783,6 +795,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH int default 12 +config SOC_PM_SUPPORT_EXT1_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + bool + default y + config SOC_PM_SUPPORT_CPU_PD bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 8c9259baed..62086ac264 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -48,7 +48,7 @@ #define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */ #define SOC_PMU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 -// \#define SOC_LP_AON_SUPPORTED 1 +#define SOC_LP_AON_SUPPORTED 1 // \#define SOC_LP_PERIPHERALS_SUPPORTED 1 #define SOC_CLK_TREE_SUPPORTED 1 // \#define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9269 @@ -61,6 +61,7 @@ // \#define SOC_SDIO_SLAVE_SUPPORTED 0 // \#define SOC_PAU_SUPPORTED 0 #define SOC_LIGHT_SLEEP_SUPPORTED 1 +#define SOC_DEEP_SLEEP_SUPPORTED 1 #define SOC_PM_SUPPORTED 1 #define SOC_ECDSA_SUPPORTED 1 #define SOC_SPIRAM_SUPPORTED 1 @@ -179,7 +180,7 @@ #define SOC_GPIO_OUT_RANGE_MAX 21 // GPIO0~6 on ESP32C61 can support chip deep sleep wakeup -// \#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) //TODO: IDF-9245 +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) #define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7) @@ -414,8 +415,8 @@ // #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) // #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) // #define SOC_PM_SUPPORT_BT_WAKEUP (1) -// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) -// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!