diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index 077d67afa2..5cb2c24047 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -46,8 +46,19 @@ void IRAM_ATTR bootloader_flash_cs_timing_config() SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); } +void IRAM_ATTR bootloader_init_mspi_clock(void) +{ + // Set source mspi pll clock as 80M in bootloader stage. + // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz + // in this stage, set divider as 6 + mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); + mspi_ll_fast_set_hs_divider(6); +} + void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) { + bootloader_init_mspi_clock(); + uint32_t spi_clk_div = 0; switch (pfhdr->spi_speed) { case ESP_IMAGE_SPI_SPEED_DIV_1: @@ -198,13 +209,7 @@ static void bootloader_spi_flash_resume(void) esp_err_t bootloader_init_spi_flash(void) { - - // Set source mspi pll clock as 80M in bootloader stage. - // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz - // in this stage, set divider as 6 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); - mspi_ll_fast_set_hs_divider(6); - + bootloader_init_mspi_clock(); bootloader_init_flash_configure(); bootloader_spi_flash_resume(); bootloader_flash_unlock(); diff --git a/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 b/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 index 6b415e1dff..ad99756571 100644 --- a/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 +++ b/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5 @@ -1 +1,2 @@ CONFIG_SDMMC_BOARD_ESP32C5_BREAKOUT=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y diff --git a/examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 b/examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 new file mode 100644 index 0000000000..5e9f8e25bd --- /dev/null +++ b/examples/storage/sd_card/sdspi/sdkconfig.defaults.esp32c5 @@ -0,0 +1 @@ +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml index df9884ab56..c2bf739295 100644 --- a/tools/test_apps/system/.build-test-rules.yml +++ b/tools/test_apps/system/.build-test-rules.yml @@ -80,12 +80,6 @@ tools/test_apps/system/panic: temporary: true reason: not supported # TODO: [ESP32c61] IDF-9268 -tools/test_apps/system/ram_loadable_app: - disable: - - if: IDF_TARGET == "esp32c5" - temporary: true - reason: not supported # TODO: [ESP32C5] IDF-8644, IDF-10315 - tools/test_apps/system/rtc_mem_reserve: enable: - if: IDF_TARGET in ["esp32p4"] diff --git a/tools/test_apps/system/ram_loadable_app/README.md b/tools/test_apps/system/ram_loadable_app/README.md index d284a950d8..a9d46976d3 100644 --- a/tools/test_apps/system/ram_loadable_app/README.md +++ b/tools/test_apps/system/ram_loadable_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # RAM loadable app Example diff --git a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py index af446a6749..8329cfc3f6 100644 --- a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py +++ b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py @@ -4,7 +4,6 @@ import pytest from pytest_embedded_idf.dut import IdfDut -@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='esp32c5 support TBD') # TODO: [ESP32C5] IDF-8644, IDF-10315 @pytest.mark.esp32 @pytest.mark.esp32s2 @pytest.mark.esp32s3 @@ -12,7 +11,6 @@ from pytest_embedded_idf.dut import IdfDut @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 -@pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,) @@ -21,8 +19,6 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None: dut.expect('Time since boot: 3 seconds...', timeout=10) -# TODO: [ESP32C5] IDF-8644, IDF-10315, [ESP32C61] IDF-10951 -@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='support TBD') @pytest.mark.esp32 @pytest.mark.esp32s2 @pytest.mark.esp32s3 @@ -30,7 +26,6 @@ def test_pure_ram_loadable_app(dut: IdfDut) -> None: @pytest.mark.esp32c3 @pytest.mark.esp32c6 @pytest.mark.esp32h2 -@pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize('config', ['defaults',], indirect=True,) @@ -41,6 +36,7 @@ def test_ram_loadable_app(dut: IdfDut) -> None: # Tests with ram_app runners @pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.ram_app @pytest.mark.parametrize('config', ['defaults',], indirect=True,) def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: @@ -49,6 +45,7 @@ def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: @pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.ram_app @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,) def test_pure_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: diff --git a/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 b/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 new file mode 100644 index 0000000000..5e9f8e25bd --- /dev/null +++ b/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32c5 @@ -0,0 +1 @@ +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y