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feat(i2s): add bclk_div config for std mode

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laokaiyao
2025-03-28 15:41:08 +08:00
parent 7dd1f9eb41
commit 9d33cd4947
2 changed files with 9 additions and 2 deletions
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8
components/esp_driver_i2s/i2s_std.c
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@@ -43,8 +43,12 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std
ESP_LOGW(TAG, "the current mclk multiple cannot perform integer division (slot_num: %"PRIu32", slot_bits: %"PRIu32")", handle->total_slot, slot_bits);
}
} else {
/* For slave mode, mclk >= bclk * 8, so fix bclk_div to 2 first */
clk_info->bclk_div = 8;
if (clk_cfg->bclk_div < 8) {
ESP_LOGW(TAG, "the current bclk division is too small, adjust the bclk division to 8");
clk_info->bclk_div = 8;
} else {
clk_info->bclk_div = clk_cfg->bclk_div;
}
clk_info->bclk = rate * handle->total_slot * slot_bits;
clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
}

3
components/esp_driver_i2s/include/driver/i2s_std.h
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@@ -204,6 +204,7 @@ extern "C" {
.sample_rate_hz = rate, \
.clk_src = I2S_CLK_SRC_DEFAULT, \
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
.bclk_div = 8, \
}
#else
/**
@@ -217,6 +218,7 @@ extern "C" {
.clk_src = I2S_CLK_SRC_DEFAULT, \
.ext_clk_freq_hz = 0, \
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
.bclk_div = 8, \
}
#endif
@@ -265,6 +267,7 @@ typedef struct {
* but please set this field a multiple of `3` (like 384) when using 24-bit data width,
* otherwise the sample rate might be inaccurate
*/
uint32_t bclk_div; /*!< The division from MCLK to BCLK, only take effect for slave role, it shouldn't be smaller than 8. Increase this field when data sent by slave lag behind */
} i2s_std_clk_config_t;
/**