diff --git a/components/soc/esp32p4/include/soc/efuse_mem_reg.h b/components/soc/esp32p4/include/soc/efuse_mem_reg.h deleted file mode 100644 index e982d77684..0000000000 --- a/components/soc/esp32p4/include/soc/efuse_mem_reg.h +++ /dev/null @@ -1,4139 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_0 0xFFFFFFFFU -#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_0_S 0 - -/** EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_1 0xFFFFFFFFU -#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_1_S 0 - -/** EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_2 0xFFFFFFFFU -#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_2_S 0 - -/** EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) -/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_3 0xFFFFFFFFU -#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_3_S 0 - -/** EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_4 0xFFFFFFFFU -#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_4_S 0 - -/** EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_5 0xFFFFFFFFU -#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_5_S 0 - -/** EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_6 0xFFFFFFFFU -#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_6_S 0 - -/** EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) -/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_7 0xFFFFFFFFU -#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_7_S 0 - -/** EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. - */ -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_0_S 0 - -/** EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. - */ -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_1_S 0 - -/** EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. - */ -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_2_S 0 - -/** EFUSE_RD_WR_DIS_REG register - * BLOCK0 data register 0. - */ -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) -/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. - */ -#define EFUSE_WR_DIS 0xFFFFFFFFU -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xFFFFFFFFU -#define EFUSE_WR_DIS_S 0 - -/** EFUSE_RD_REPEAT_DATA0_REG register - * BLOCK0 data register 1. - */ -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_RD_DIS 0x0000007FU -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007FU -#define EFUSE_RD_DIS_S 0 -/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0; - * Enable usb device exchange pins of D+ and D-. - */ -#define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(7)) -#define EFUSE_USB_DEVICE_EXCHG_PINS_M (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S) -#define EFUSE_USB_DEVICE_EXCHG_PINS_V 0x00000001U -#define EFUSE_USB_DEVICE_EXCHG_PINS_S 7 -/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0; - * Enable usb otg11 exchange pins of D+ and D-. - */ -#define EFUSE_USB_OTG11_EXCHG_PINS (BIT(8)) -#define EFUSE_USB_OTG11_EXCHG_PINS_M (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S) -#define EFUSE_USB_OTG11_EXCHG_PINS_V 0x00000001U -#define EFUSE_USB_OTG11_EXCHG_PINS_S 8 -/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. 1: - * disabled. 0: enabled. - */ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) -#define EFUSE_DIS_USB_JTAG_V 0x00000001U -#define EFUSE_DIS_USB_JTAG_S 9 -/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. - */ -#define EFUSE_POWERGLITCH_EN (BIT(10)) -#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) -#define EFUSE_POWERGLITCH_EN_V 0x00000001U -#define EFUSE_POWERGLITCH_EN_S 10 -/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during - * boot_mode_download. - */ -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 -/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) -#define EFUSE_DIS_TWAI_V 0x00000001U -#define EFUSE_DIS_TWAI_S 14 -/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Represents whether the selection between usb_to_jtag and pad_to_jtag through - * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled. 1: enabled. 0: disabled. - */ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) -#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. - */ -#define EFUSE_SOFT_DIS_JTAG 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) -#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_S 16 -/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. - */ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) -#define EFUSE_DIS_PAD_JTAG_V 0x00000001U -#define EFUSE_DIS_PAD_JTAG_S 19 -/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). 1: disabled. 0: enabled. - */ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; - * TBD - */ -#define EFUSE_USB_PHY_SEL (BIT(25)) -#define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) -#define EFUSE_USB_PHY_SEL_V 0x00000001U -#define EFUSE_USB_PHY_SEL_S 25 -/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. - */ -#define EFUSE_KM_HUK_GEN_STATE_LOW 0x0000003FU -#define EFUSE_KM_HUK_GEN_STATE_LOW_M (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S) -#define EFUSE_KM_HUK_GEN_STATE_LOW_V 0x0000003FU -#define EFUSE_KM_HUK_GEN_STATE_LOW_S 26 - -/** EFUSE_RD_REPEAT_DATA1_REG register - * BLOCK0 data register 2. - */ -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. - */ -#define EFUSE_KM_HUK_GEN_STATE_HIGH 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_M (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S) -#define EFUSE_KM_HUK_GEN_STATE_HIGH_V 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_S 0 -/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0; - * Set bits to control key manager random number switch cycle. 0: control by register. - * 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. - */ -#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) -#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_S 3 -/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0; - * Set each bit to control whether corresponding key can only be deployed once. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - */ -#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) -#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 5 -/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0; - * Set each bit to control whether corresponding key must come from key manager.. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - */ -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 9 -/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0; - * Set this bit to disable software written init key, and force use efuse_init_key. - */ -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(13)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 13 -/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0; - * Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. - */ -#define EFUSE_XTS_KEY_LENGTH_256 (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_M (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S) -#define EFUSE_XTS_KEY_LENGTH_256_V 0x00000001U -#define EFUSE_XTS_KEY_LENGTH_256_S 14 -/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. - */ -#define EFUSE_WDT_DELAY_SEL 0x00000003U -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_S 16 -/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of - * 1: enabled. Even number of 1: disabled. - */ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. - */ -#define EFUSE_KEY_PURPOSE_0 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_S 24 -/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. - */ -#define EFUSE_KEY_PURPOSE_1 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_S 28 - -/** EFUSE_RD_REPEAT_DATA2_REG register - * BLOCK0 data register 3. - */ -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. - */ -#define EFUSE_KEY_PURPOSE_2 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_S 0 -/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. - */ -#define EFUSE_KEY_PURPOSE_3 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_S 4 -/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. - */ -#define EFUSE_KEY_PURPOSE_4 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_S 8 -/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. - */ -#define EFUSE_KEY_PURPOSE_5 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_S 12 -/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. - */ -#define EFUSE_SEC_DPA_LEVEL 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) -#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0; - * Represents whether hardware random number k is forced used in ESDCA. 1: force used. - * 0: not force used. - */ -#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_M (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S) -#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x00000001U -#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 -/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. - */ -#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) -#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U -#define EFUSE_CRYPT_DPA_ENABLE_S 19 -/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. - */ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) -#define EFUSE_SECURE_BOOT_EN_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_S 20 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. 1: - * enabled. 0: disabled. - */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0; - * The type of interfaced flash. 0: four data lines, 1: eight data lines. - */ -#define EFUSE_FLASH_TYPE (BIT(23)) -#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) -#define EFUSE_FLASH_TYPE_V 0x00000001U -#define EFUSE_FLASH_TYPE_S 23 -/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0; - * Set flash page size. - */ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) -#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_S 24 -/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0; - * Set this bit to enable ecc for flash boot. - */ -#define EFUSE_FLASH_ECC_EN (BIT(26)) -#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) -#define EFUSE_FLASH_ECC_EN_V 0x00000001U -#define EFUSE_FLASH_ECC_EN_S 26 -/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0; - * Set this bit to disable download via USB-OTG. - */ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(27)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 27 -/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. - */ -#define EFUSE_FLASH_TPUW 0x0000000FU -#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) -#define EFUSE_FLASH_TPUW_V 0x0000000FU -#define EFUSE_FLASH_TPUW_S 28 - -/** EFUSE_RD_REPEAT_DATA3_REG register - * BLOCK0 data register 4. - */ -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) -/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 -/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) -#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. - * 0: enabled. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; - * TBD - */ -#define EFUSE_LOCK_KM_KEY (BIT(3)) -#define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) -#define EFUSE_LOCK_KM_KEY_V 0x00000001U -#define EFUSE_LOCK_KM_KEY_S 3 -/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled. 1: enabled. 0: - * disabled. - */ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. 00: force enable printing. 01: enable - * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset - * at high level. 11: force disable printing. - */ -#define EFUSE_UART_PRINT_CONTROL 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) -#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_S 6 -/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. - */ -#define EFUSE_FORCE_SEND_RESUME (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) -#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U -#define EFUSE_FORCE_SEND_RESUME_S 8 -/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. - */ -#define EFUSE_SECURE_VERSION 0x0000FFFFU -#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x0000FFFFU -#define EFUSE_SECURE_VERSION_S 9 -/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 -/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled. 1: - * enabled. 0:disabled. - */ -#define EFUSE_HYS_EN_PAD (BIT(26)) -#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) -#define EFUSE_HYS_EN_PAD_V 0x00000001U -#define EFUSE_HYS_EN_PAD_S 26 -/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0; - * Set the dcdc voltage default. - */ -#define EFUSE_DCDC_VSET 0x0000001FU -#define EFUSE_DCDC_VSET_M (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S) -#define EFUSE_DCDC_VSET_V 0x0000001FU -#define EFUSE_DCDC_VSET_S 27 - -/** EFUSE_RD_REPEAT_DATA4_REG register - * BLOCK0 data register 5. - */ -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/** EFUSE_0PXA_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0; - * TBD - */ -#define EFUSE_0PXA_TIEH_SEL_0 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_0_M (EFUSE_0PXA_TIEH_SEL_0_V << EFUSE_0PXA_TIEH_SEL_0_S) -#define EFUSE_0PXA_TIEH_SEL_0_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_0_S 0 -/** EFUSE_0PXA_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0; - * TBD. - */ -#define EFUSE_0PXA_TIEH_SEL_1 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_1_M (EFUSE_0PXA_TIEH_SEL_1_V << EFUSE_0PXA_TIEH_SEL_1_S) -#define EFUSE_0PXA_TIEH_SEL_1_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_1_S 2 -/** EFUSE_0PXA_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0; - * TBD. - */ -#define EFUSE_0PXA_TIEH_SEL_2 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_2_M (EFUSE_0PXA_TIEH_SEL_2_V << EFUSE_0PXA_TIEH_SEL_2_S) -#define EFUSE_0PXA_TIEH_SEL_2_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_2_S 4 -/** EFUSE_0PXA_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0; - * TBD. - */ -#define EFUSE_0PXA_TIEH_SEL_3 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_3_M (EFUSE_0PXA_TIEH_SEL_3_V << EFUSE_0PXA_TIEH_SEL_3_S) -#define EFUSE_0PXA_TIEH_SEL_3_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_3_S 6 -/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0; - * TBD. - */ -#define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8 -/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0; - * HP system power source select. 0:LDO. 1: DCDC. - */ -#define EFUSE_HP_PWR_SRC_SEL (BIT(18)) -#define EFUSE_HP_PWR_SRC_SEL_M (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S) -#define EFUSE_HP_PWR_SRC_SEL_V 0x00000001U -#define EFUSE_HP_PWR_SRC_SEL_S 18 -/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0; - * Select dcdc vset use efuse_dcdc_vset. - */ -#define EFUSE_DCDC_VSET_EN (BIT(19)) -#define EFUSE_DCDC_VSET_EN_M (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S) -#define EFUSE_DCDC_VSET_EN_V 0x00000001U -#define EFUSE_DCDC_VSET_EN_S 19 -/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0; - * Set this bit to disable watch dog. - */ -#define EFUSE_DIS_WDT (BIT(20)) -#define EFUSE_DIS_WDT_M (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S) -#define EFUSE_DIS_WDT_V 0x00000001U -#define EFUSE_DIS_WDT_S 20 -/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0; - * Set this bit to disable super-watchdog. - */ -#define EFUSE_DIS_SWD (BIT(21)) -#define EFUSE_DIS_SWD_M (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S) -#define EFUSE_DIS_SWD_V 0x00000001U -#define EFUSE_DIS_SWD_S 21 - -/** EFUSE_RD_MAC_SYS_0_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) -/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ -#define EFUSE_MAC_0 0xFFFFFFFFU -#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) -#define EFUSE_MAC_0_V 0xFFFFFFFFU -#define EFUSE_MAC_0_S 0 - -/** EFUSE_RD_MAC_SYS_1_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) -/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ -#define EFUSE_MAC_1 0x0000FFFFU -#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) -#define EFUSE_MAC_1_V 0x0000FFFFU -#define EFUSE_MAC_1_S 0 -/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. - */ -#define EFUSE_MAC_EXT 0x0000FFFFU -#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) -#define EFUSE_MAC_EXT_V 0x0000FFFFU -#define EFUSE_MAC_EXT_S 16 - -/** EFUSE_RD_MAC_SYS_2_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_1 0x00003FFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_1_S 0 -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_0 0x0003FFFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_0_S 14 - -/** EFUSE_RD_MAC_SYS_3_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the first 14 bits of the zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 - -/** EFUSE_RD_MAC_SYS_4_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_S 0 - -/** EFUSE_RD_MAC_SYS_5_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 0 - -/** EFUSE_RD_SYS_PART1_DATA0_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 - -/** EFUSE_RD_SYS_PART1_DATA1_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 - -/** EFUSE_RD_SYS_PART1_DATA2_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 - -/** EFUSE_RD_SYS_PART1_DATA3_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 - -/** EFUSE_RD_SYS_PART1_DATA4_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 - -/** EFUSE_RD_SYS_PART1_DATA5_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_S 0 - -/** EFUSE_RD_SYS_PART1_DATA6_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_S 0 - -/** EFUSE_RD_SYS_PART1_DATA7_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_S 0 - -/** EFUSE_RD_USR_DATA0_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) -/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA0 0xFFFFFFFFU -#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) -#define EFUSE_USR_DATA0_V 0xFFFFFFFFU -#define EFUSE_USR_DATA0_S 0 - -/** EFUSE_RD_USR_DATA1_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) -/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA1 0xFFFFFFFFU -#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) -#define EFUSE_USR_DATA1_V 0xFFFFFFFFU -#define EFUSE_USR_DATA1_S 0 - -/** EFUSE_RD_USR_DATA2_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) -/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA2 0xFFFFFFFFU -#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) -#define EFUSE_USR_DATA2_V 0xFFFFFFFFU -#define EFUSE_USR_DATA2_S 0 - -/** EFUSE_RD_USR_DATA3_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) -/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA3 0xFFFFFFFFU -#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) -#define EFUSE_USR_DATA3_V 0xFFFFFFFFU -#define EFUSE_USR_DATA3_S 0 - -/** EFUSE_RD_USR_DATA4_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) -/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA4 0xFFFFFFFFU -#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) -#define EFUSE_USR_DATA4_V 0xFFFFFFFFU -#define EFUSE_USR_DATA4_S 0 - -/** EFUSE_RD_USR_DATA5_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) -/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA5 0xFFFFFFFFU -#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) -#define EFUSE_USR_DATA5_V 0xFFFFFFFFU -#define EFUSE_USR_DATA5_S 0 - -/** EFUSE_RD_USR_DATA6_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 - -/** EFUSE_RD_USR_DATA7_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 - -/** EFUSE_RD_KEY0_DATA0_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) -/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA0 0xFFFFFFFFU -#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA0_S 0 - -/** EFUSE_RD_KEY0_DATA1_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) -/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA1 0xFFFFFFFFU -#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA1_S 0 - -/** EFUSE_RD_KEY0_DATA2_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) -/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA2 0xFFFFFFFFU -#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA2_S 0 - -/** EFUSE_RD_KEY0_DATA3_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) -/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA3 0xFFFFFFFFU -#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA3_S 0 - -/** EFUSE_RD_KEY0_DATA4_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) -/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA4 0xFFFFFFFFU -#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA4_S 0 - -/** EFUSE_RD_KEY0_DATA5_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) -/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA5 0xFFFFFFFFU -#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA5_S 0 - -/** EFUSE_RD_KEY0_DATA6_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) -/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA6 0xFFFFFFFFU -#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA6_S 0 - -/** EFUSE_RD_KEY0_DATA7_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) -/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA7 0xFFFFFFFFU -#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA7_S 0 - -/** EFUSE_RD_KEY1_DATA0_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) -/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA0 0xFFFFFFFFU -#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA0_S 0 - -/** EFUSE_RD_KEY1_DATA1_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) -/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA1 0xFFFFFFFFU -#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA1_S 0 - -/** EFUSE_RD_KEY1_DATA2_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) -/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA2 0xFFFFFFFFU -#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA2_S 0 - -/** EFUSE_RD_KEY1_DATA3_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) -/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA3 0xFFFFFFFFU -#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA3_S 0 - -/** EFUSE_RD_KEY1_DATA4_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) -/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA4 0xFFFFFFFFU -#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA4_S 0 - -/** EFUSE_RD_KEY1_DATA5_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) -/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA5 0xFFFFFFFFU -#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA5_S 0 - -/** EFUSE_RD_KEY1_DATA6_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) -/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA6 0xFFFFFFFFU -#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA6_S 0 - -/** EFUSE_RD_KEY1_DATA7_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) -/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA7 0xFFFFFFFFU -#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA7_S 0 - -/** EFUSE_RD_KEY2_DATA0_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) -/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA0 0xFFFFFFFFU -#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA0_S 0 - -/** EFUSE_RD_KEY2_DATA1_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) -/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA1 0xFFFFFFFFU -#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA1_S 0 - -/** EFUSE_RD_KEY2_DATA2_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) -/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA2 0xFFFFFFFFU -#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA2_S 0 - -/** EFUSE_RD_KEY2_DATA3_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) -/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA3 0xFFFFFFFFU -#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA3_S 0 - -/** EFUSE_RD_KEY2_DATA4_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) -/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA4 0xFFFFFFFFU -#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA4_S 0 - -/** EFUSE_RD_KEY2_DATA5_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) -/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA5 0xFFFFFFFFU -#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA5_S 0 - -/** EFUSE_RD_KEY2_DATA6_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) -/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA6 0xFFFFFFFFU -#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA6_S 0 - -/** EFUSE_RD_KEY2_DATA7_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) -/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA7 0xFFFFFFFFU -#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA7_S 0 - -/** EFUSE_RD_KEY3_DATA0_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) -/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA0 0xFFFFFFFFU -#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA0_S 0 - -/** EFUSE_RD_KEY3_DATA1_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA1 0xFFFFFFFFU -#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA1_S 0 - -/** EFUSE_RD_KEY3_DATA2_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA2 0xFFFFFFFFU -#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA2_S 0 - -/** EFUSE_RD_KEY3_DATA3_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA3 0xFFFFFFFFU -#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA3_S 0 - -/** EFUSE_RD_KEY3_DATA4_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) -/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA4 0xFFFFFFFFU -#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA4_S 0 - -/** EFUSE_RD_KEY3_DATA5_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA5 0xFFFFFFFFU -#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA5_S 0 - -/** EFUSE_RD_KEY3_DATA6_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA6 0xFFFFFFFFU -#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA6_S 0 - -/** EFUSE_RD_KEY3_DATA7_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA7 0xFFFFFFFFU -#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA7_S 0 - -/** EFUSE_RD_KEY4_DATA0_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) -/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA0 0xFFFFFFFFU -#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA0_S 0 - -/** EFUSE_RD_KEY4_DATA1_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA1 0xFFFFFFFFU -#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA1_S 0 - -/** EFUSE_RD_KEY4_DATA2_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA2 0xFFFFFFFFU -#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA2_S 0 - -/** EFUSE_RD_KEY4_DATA3_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA3 0xFFFFFFFFU -#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA3_S 0 - -/** EFUSE_RD_KEY4_DATA4_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) -/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA4 0xFFFFFFFFU -#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA4_S 0 - -/** EFUSE_RD_KEY4_DATA5_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA5 0xFFFFFFFFU -#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA5_S 0 - -/** EFUSE_RD_KEY4_DATA6_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA6 0xFFFFFFFFU -#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA6_S 0 - -/** EFUSE_RD_KEY4_DATA7_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA7 0xFFFFFFFFU -#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA7_S 0 - -/** EFUSE_RD_KEY5_DATA0_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) -/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA0 0xFFFFFFFFU -#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA0_S 0 - -/** EFUSE_RD_KEY5_DATA1_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA1 0xFFFFFFFFU -#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA1_S 0 - -/** EFUSE_RD_KEY5_DATA2_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA2 0xFFFFFFFFU -#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA2_S 0 - -/** EFUSE_RD_KEY5_DATA3_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA3 0xFFFFFFFFU -#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA3_S 0 - -/** EFUSE_RD_KEY5_DATA4_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) -/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA4 0xFFFFFFFFU -#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA4_S 0 - -/** EFUSE_RD_KEY5_DATA5_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA5 0xFFFFFFFFU -#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA5_S 0 - -/** EFUSE_RD_KEY5_DATA6_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA6 0xFFFFFFFFU -#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA6_S 0 - -/** EFUSE_RD_KEY5_DATA7_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA7 0xFFFFFFFFU -#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA7_S 0 - -/** EFUSE_RD_SYS_PART2_DATA0_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_S 0 - -/** EFUSE_RD_SYS_PART2_DATA1_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_S 0 - -/** EFUSE_RD_SYS_PART2_DATA2_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_S 0 - -/** EFUSE_RD_SYS_PART2_DATA3_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_S 0 - -/** EFUSE_RD_SYS_PART2_DATA4_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) -/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_4_S 0 - -/** EFUSE_RD_SYS_PART2_DATA5_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_5_S 0 - -/** EFUSE_RD_SYS_PART2_DATA6_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_S 0 - -/** EFUSE_RD_SYS_PART2_DATA7_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_S 0 - -/** EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) -/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. - */ -#define EFUSE_RD_DIS_ERR 0x0000007FU -#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) -#define EFUSE_RD_DIS_ERR_V 0x0000007FU -#define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0; - * Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. - */ -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR (BIT(7)) -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S) -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V 0x00000001U -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S 7 -/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. - */ -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR (BIT(8)) -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S) -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V 0x00000001U -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S 8 -/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. - */ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; - * Indicates a programming error of POWERGLITCH_EN. - */ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) -#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U -#define EFUSE_POWERGLITCH_EN_ERR_S 10 -/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. - */ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. - */ -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 -/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_TWAI. - */ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) -#define EFUSE_DIS_TWAI_ERR_V 0x00000001U -#define EFUSE_DIS_TWAI_ERR_S 14 -/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. - */ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. - */ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. - */ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_PHY_SEL. - */ -#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) -#define EFUSE_USB_PHY_SEL_ERR_V 0x00000001U -#define EFUSE_USB_PHY_SEL_ERR_S 25 -/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_LOW. - */ -#define EFUSE_HUK_GEN_STATE_LOW_ERR 0x0000003FU -#define EFUSE_HUK_GEN_STATE_LOW_ERR_M (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S) -#define EFUSE_HUK_GEN_STATE_LOW_ERR_V 0x0000003FU -#define EFUSE_HUK_GEN_STATE_LOW_ERR_S 26 - -/** EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_HIGH. - */ -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S) -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S 0 -/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0; - * Indicates a programming error of KM_RND_SWITCH_CYCLE. - */ -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 3 -/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0; - * Indicates a programming error of KM_DEPLOY_ONLY_ONCE. - */ -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 5 -/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0; - * Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. - */ -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 9 -/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0; - * Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. - */ -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(13)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 13 -/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of XTS_KEY_LENGTH_256. - */ -#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x00000001U -#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 14 -/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. - */ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. - */ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. - */ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. - */ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 - -/** EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. - */ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 -/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. - */ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. - */ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. - */ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. - */ -#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) -#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0; - * Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. - */ -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x00000001U -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 -/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. - */ -#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U -#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 -/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. - */ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. - */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0; - * Indicates a programming error of FLASH_TYPE. - */ -#define EFUSE_FLASH_TYPE_ERR (BIT(23)) -#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) -#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U -#define EFUSE_FLASH_TYPE_ERR_S 23 -/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0; - * Indicates a programming error of FLASH_PAGE_SIZE. - */ -#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) -#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_ERR_S 24 -/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of FLASH_ECC_EN. - */ -#define EFUSE_FLASH_ECC_EN_ERR (BIT(26)) -#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) -#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U -#define EFUSE_FLASH_ECC_EN_ERR_S 26 -/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0; - * Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. - */ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR (BIT(27)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S 27 -/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. - */ -#define EFUSE_FLASH_TPUW_ERR 0x0000000FU -#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) -#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU -#define EFUSE_FLASH_TPUW_ERR_S 28 - -/** EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. - */ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 -/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. - */ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; - * TBD - */ -#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) -#define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) -#define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U -#define EFUSE_LOCK_KM_KEY_ERR_S 3 -/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. - */ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. - */ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. - */ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U -#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 -/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. - */ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU -#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU -#define EFUSE_SECURE_VERSION_ERR_S 9 -/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. - */ -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 -/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of HYS_EN_PAD. - */ -#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) -#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) -#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U -#define EFUSE_HYS_EN_PAD_ERR_S 26 -/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0; - * Indicates a programming error of DCDC_VSET. - */ -#define EFUSE_DCDC_VSET_ERR 0x0000001FU -#define EFUSE_DCDC_VSET_ERR_M (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S) -#define EFUSE_DCDC_VSET_ERR_V 0x0000001FU -#define EFUSE_DCDC_VSET_ERR_S 27 - -/** EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) -/** EFUSE_0PXA_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_0. - */ -#define EFUSE_0PXA_TIEH_SEL_0_ERR 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_0_ERR_M (EFUSE_0PXA_TIEH_SEL_0_ERR_V << EFUSE_0PXA_TIEH_SEL_0_ERR_S) -#define EFUSE_0PXA_TIEH_SEL_0_ERR_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_0_ERR_S 0 -/** EFUSE_0PXA_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_1. - */ -#define EFUSE_0PXA_TIEH_SEL_1_ERR 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_1_ERR_M (EFUSE_0PXA_TIEH_SEL_1_ERR_V << EFUSE_0PXA_TIEH_SEL_1_ERR_S) -#define EFUSE_0PXA_TIEH_SEL_1_ERR_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_1_ERR_S 2 -/** EFUSE_0PXA_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_2. - */ -#define EFUSE_0PXA_TIEH_SEL_2_ERR 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_2_ERR_M (EFUSE_0PXA_TIEH_SEL_2_ERR_V << EFUSE_0PXA_TIEH_SEL_2_ERR_S) -#define EFUSE_0PXA_TIEH_SEL_2_ERR_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_2_ERR_S 4 -/** EFUSE_0PXA_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_3. - */ -#define EFUSE_0PXA_TIEH_SEL_3_ERR 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_3_ERR_M (EFUSE_0PXA_TIEH_SEL_3_ERR_V << EFUSE_0PXA_TIEH_SEL_3_ERR_S) -#define EFUSE_0PXA_TIEH_SEL_3_ERR_V 0x00000003U -#define EFUSE_0PXA_TIEH_SEL_3_ERR_S 6 -/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0; - * TBD. - */ -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 8 -/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0; - * Indicates a programming error of USB_DEVICE_DREFL. - */ -#define EFUSE_USB_DEVICE_DREFL_ERR 0x00000003U -#define EFUSE_USB_DEVICE_DREFL_ERR_M (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S) -#define EFUSE_USB_DEVICE_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_DEVICE_DREFL_ERR_S 12 -/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0; - * Indicates a programming error of USB_OTG11_DREFL. - */ -#define EFUSE_USB_OTG11_DREFL_ERR 0x00000003U -#define EFUSE_USB_OTG11_DREFL_ERR_M (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S) -#define EFUSE_USB_OTG11_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_OTG11_DREFL_ERR_S 14 -/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0; - * Indicates a programming error of HP_PWR_SRC_SEL. - */ -#define EFUSE_HP_PWR_SRC_SEL_ERR (BIT(18)) -#define EFUSE_HP_PWR_SRC_SEL_ERR_M (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S) -#define EFUSE_HP_PWR_SRC_SEL_ERR_V 0x00000001U -#define EFUSE_HP_PWR_SRC_SEL_ERR_S 18 -/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DCDC_VSET_EN. - */ -#define EFUSE_DCDC_VSET_EN_ERR (BIT(19)) -#define EFUSE_DCDC_VSET_EN_ERR_M (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S) -#define EFUSE_DCDC_VSET_EN_ERR_V 0x00000001U -#define EFUSE_DCDC_VSET_EN_ERR_S 19 -/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_WDT. - */ -#define EFUSE_DIS_WDT_ERR (BIT(20)) -#define EFUSE_DIS_WDT_ERR_M (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S) -#define EFUSE_DIS_WDT_ERR_V 0x00000001U -#define EFUSE_DIS_WDT_ERR_S 20 -/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of DIS_SWD. - */ -#define EFUSE_DIS_SWD_ERR (BIT(21)) -#define EFUSE_DIS_SWD_ERR_M (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S) -#define EFUSE_DIS_SWD_ERR_V 0x00000001U -#define EFUSE_DIS_SWD_ERR_S 21 - -/** EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. - */ -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_MAC_SYS_ERR_NUM 0x00000007U -#define EFUSE_MAC_SYS_ERR_NUM_M (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S) -#define EFUSE_MAC_SYS_ERR_NUM_V 0x00000007U -#define EFUSE_MAC_SYS_ERR_NUM_S 0 -/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ -#define EFUSE_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_MAC_SYS_FAIL_M (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S) -#define EFUSE_MAC_SYS_FAIL_V 0x00000001U -#define EFUSE_MAC_SYS_FAIL_S 3 -/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_SYS_PART1_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART1_ERR_NUM_M (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S) -#define EFUSE_SYS_PART1_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART1_ERR_NUM_S 4 -/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001U -#define EFUSE_SYS_PART1_FAIL_S 7 -/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_USR_DATA_FAIL_S 11 -/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY0_ERR_NUM 0x00000007U -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007U -#define EFUSE_KEY0_ERR_NUM_S 12 -/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001U -#define EFUSE_KEY0_FAIL_S 15 -/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY1_ERR_NUM 0x00000007U -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007U -#define EFUSE_KEY1_ERR_NUM_S 16 -/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001U -#define EFUSE_KEY1_FAIL_S 19 -/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY2_ERR_NUM 0x00000007U -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007U -#define EFUSE_KEY2_ERR_NUM_S 20 -/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001U -#define EFUSE_KEY2_FAIL_S 23 -/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY3_ERR_NUM 0x00000007U -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007U -#define EFUSE_KEY3_ERR_NUM_S 24 -/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001U -#define EFUSE_KEY3_FAIL_S 27 -/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY4_ERR_NUM 0x00000007U -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007U -#define EFUSE_KEY4_ERR_NUM_S 28 -/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001U -#define EFUSE_KEY4_FAIL_S 31 - -/** EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. - */ -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY5_ERR_NUM 0x00000007U -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007U -#define EFUSE_KEY5_ERR_NUM_S 0 -/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001U -#define EFUSE_KEY5_FAIL_S 3 -/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001U -#define EFUSE_SYS_PART2_FAIL_S 7 - -/** EFUSE_CLK_REG register - * eFuse clcok configuration register. - */ -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) -/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) -#define EFUSE_MEM_FORCE_PD_V 0x00000001U -#define EFUSE_MEM_FORCE_PD_S 0 -/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U -#define EFUSE_MEM_CLK_FORCE_ON_S 1 -/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) -#define EFUSE_MEM_FORCE_PU_V 0x00000001U -#define EFUSE_MEM_FORCE_PU_S 2 -/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. - */ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) -#define EFUSE_CLK_EN_V 0x00000001U -#define EFUSE_CLK_EN_S 16 - -/** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register - */ -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) -/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. - */ -#define EFUSE_OP_CODE 0x0000FFFFU -#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) -#define EFUSE_OP_CODE_V 0x0000FFFFU -#define EFUSE_OP_CODE_S 0 -/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. - */ -#define EFUSE_CFG_ECDSA_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) -#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_S 16 - -/** EFUSE_STATUS_REG register - * eFuse status register. - */ -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) -/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ -#define EFUSE_STATE 0x0000000FU -#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) -#define EFUSE_STATE_V 0x0000000FU -#define EFUSE_STATE_S 0 -/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. - */ -#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU -#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) -#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU -#define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. - */ -#define EFUSE_CUR_ECDSA_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) -#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_S 20 - -/** EFUSE_CMD_REG register - * eFuse command register. - */ -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) -/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) -#define EFUSE_READ_CMD_V 0x00000001U -#define EFUSE_READ_CMD_S 0 -/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) -#define EFUSE_PGM_CMD_V 0x00000001U -#define EFUSE_PGM_CMD_S 1 -/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ -#define EFUSE_BLK_NUM 0x0000000FU -#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) -#define EFUSE_BLK_NUM_V 0x0000000FU -#define EFUSE_BLK_NUM_S 2 - -/** EFUSE_INT_RAW_REG register - * eFuse raw interrupt register. - */ -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) -/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) -#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U -#define EFUSE_READ_DONE_INT_RAW_S 0 -/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) -#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/** EFUSE_INT_ST_REG register - * eFuse interrupt status register. - */ -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) -/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) -#define EFUSE_READ_DONE_INT_ST_V 0x00000001U -#define EFUSE_READ_DONE_INT_ST_S 0 -/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) -#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/** EFUSE_INT_ENA_REG register - * eFuse interrupt enable register. - */ -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) -/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) -#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U -#define EFUSE_READ_DONE_INT_ENA_S 0 -/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) -#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/** EFUSE_INT_CLR_REG register - * eFuse interrupt clear register. - */ -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) -/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) -#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U -#define EFUSE_READ_DONE_INT_CLR_S 0 -/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) -#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/** EFUSE_DAC_CONF_REG register - * Controls the eFuse programming voltage. - */ -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ -#define EFUSE_DAC_CLK_DIV 0x000000FFU -#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) -#define EFUSE_DAC_CLK_DIV_V 0x000000FFU -#define EFUSE_DAC_CLK_DIV_S 0 -/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; - * Don't care. - */ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ -#define EFUSE_DAC_NUM 0x000000FFU -#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) -#define EFUSE_DAC_NUM_V 0x000000FFU -#define EFUSE_DAC_NUM_S 9 -/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) -#define EFUSE_OE_CLR_V 0x00000001U -#define EFUSE_OE_CLR_S 17 - -/** EFUSE_RD_TIM_CONF_REG register - * Configures read timing parameters. - */ -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) -/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ -#define EFUSE_THR_A 0x000000FFU -#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) -#define EFUSE_THR_A_V 0x000000FFU -#define EFUSE_THR_A_S 0 -/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ -#define EFUSE_TRD 0x000000FFU -#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) -#define EFUSE_TRD_V 0x000000FFU -#define EFUSE_TRD_S 8 -/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ -#define EFUSE_TSUR_A 0x000000FFU -#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) -#define EFUSE_TSUR_A_V 0x000000FFU -#define EFUSE_TSUR_A_S 16 -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; - * Configures the waiting time of reading eFuse memory. - */ -#define EFUSE_READ_INIT_NUM 0x000000FFU -#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) -#define EFUSE_READ_INIT_NUM_V 0x000000FFU -#define EFUSE_READ_INIT_NUM_S 24 - -/** EFUSE_WR_TIM_CONF1_REG register - * Configurarion register 1 of eFuse programming timing parameters. - */ -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) -/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ -#define EFUSE_TSUP_A 0x000000FFU -#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) -#define EFUSE_TSUP_A_V 0x000000FFU -#define EFUSE_TSUP_A_S 0 -/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. - */ -#define EFUSE_PWR_ON_NUM 0x0000FFFFU -#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) -#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU -#define EFUSE_PWR_ON_NUM_S 8 -/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ -#define EFUSE_THP_A 0x000000FFU -#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) -#define EFUSE_THP_A_V 0x000000FFU -#define EFUSE_THP_A_S 24 - -/** EFUSE_WR_TIM_CONF2_REG register - * Configurarion register 2 of eFuse programming timing parameters. - */ -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) -/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. - */ -#define EFUSE_PWR_OFF_NUM 0x0000FFFFU -#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) -#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU -#define EFUSE_PWR_OFF_NUM_S 0 -/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. - */ -#define EFUSE_TPGM 0x0000FFFFU -#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) -#define EFUSE_TPGM_V 0x0000FFFFU -#define EFUSE_TPGM_S 16 - -/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) -/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ -#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) -#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) -#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U -#define EFUSE_BYPASS_RS_CORRECTION_S 0 -/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ -#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU -#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) -#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU -#define EFUSE_BYPASS_RS_BLK_NUM_S 1 -/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ -#define EFUSE_UPDATE (BIT(12)) -#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) -#define EFUSE_UPDATE_V 0x00000001U -#define EFUSE_UPDATE_S 12 -/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ -#define EFUSE_TPGM_INACTIVE 0x000000FFU -#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) -#define EFUSE_TPGM_INACTIVE_V 0x000000FFU -#define EFUSE_TPGM_INACTIVE_S 13 - -/** EFUSE_DATE_REG register - * eFuse version register. - */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720; - * Stores eFuse version. - */ -#define EFUSE_DATE 0x0FFFFFFFU -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0FFFFFFFU -#define EFUSE_DATE_S 0 - -/** EFUSE_APB2OTP_WR_DIS_REG register - * eFuse apb2otp block0 data register1. - */ -#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800) -/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ -#define EFUSE_APB2OTP_BLOCK0_WR_DIS 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S) -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register - * eFuse apb2otp block0 data register2. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register - * eFuse apb2otp block0 data register3. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register - * eFuse apb2otp block0 data register4. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register - * eFuse apb2otp block0 data register5. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register - * eFuse apb2otp block0 data register6. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register - * eFuse apb2otp block0 data register7. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register - * eFuse apb2otp block0 data register8. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register - * eFuse apb2otp block0 data register9. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register - * eFuse apb2otp block0 data register10. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register - * eFuse apb2otp block0 data register11. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register - * eFuse apb2otp block0 data register12. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register - * eFuse apb2otp block0 data register13. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register - * eFuse apb2otp block0 data register14. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register - * eFuse apb2otp block0 data register15. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register - * eFuse apb2otp block0 data register16. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register - * eFuse apb2otp block0 data register17. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register - * eFuse apb2otp block0 data register18. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register - * eFuse apb2otp block0 data register19. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register - * eFuse apb2otp block0 data register20. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register - * eFuse apb2otp block0 data register21. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S 0 - -/** EFUSE_APB2OTP_BLK1_W1_REG register - * eFuse apb2otp block1 data register1. - */ -#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854) -/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W1_M (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S) -#define EFUSE_APB2OTP_BLOCK1_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W1_S 0 - -/** EFUSE_APB2OTP_BLK1_W2_REG register - * eFuse apb2otp block1 data register2. - */ -#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858) -/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W2_M (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S) -#define EFUSE_APB2OTP_BLOCK1_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W2_S 0 - -/** EFUSE_APB2OTP_BLK1_W3_REG register - * eFuse apb2otp block1 data register3. - */ -#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c) -/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W3_M (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S) -#define EFUSE_APB2OTP_BLOCK1_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W3_S 0 - -/** EFUSE_APB2OTP_BLK1_W4_REG register - * eFuse apb2otp block1 data register4. - */ -#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860) -/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W4_M (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S) -#define EFUSE_APB2OTP_BLOCK1_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W4_S 0 - -/** EFUSE_APB2OTP_BLK1_W5_REG register - * eFuse apb2otp block1 data register5. - */ -#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864) -/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W5_M (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S) -#define EFUSE_APB2OTP_BLOCK1_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W5_S 0 - -/** EFUSE_APB2OTP_BLK1_W6_REG register - * eFuse apb2otp block1 data register6. - */ -#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868) -/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W6_M (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S) -#define EFUSE_APB2OTP_BLOCK1_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W6_S 0 - -/** EFUSE_APB2OTP_BLK1_W7_REG register - * eFuse apb2otp block1 data register7. - */ -#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c) -/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W7_M (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S) -#define EFUSE_APB2OTP_BLOCK1_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W7_S 0 - -/** EFUSE_APB2OTP_BLK1_W8_REG register - * eFuse apb2otp block1 data register8. - */ -#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870) -/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W8_M (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S) -#define EFUSE_APB2OTP_BLOCK1_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W8_S 0 - -/** EFUSE_APB2OTP_BLK1_W9_REG register - * eFuse apb2otp block1 data register9. - */ -#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874) -/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W9_M (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S) -#define EFUSE_APB2OTP_BLOCK1_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W9_S 0 - -/** EFUSE_APB2OTP_BLK2_W1_REG register - * eFuse apb2otp block2 data register1. - */ -#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878) -/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W1_M (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S) -#define EFUSE_APB2OTP_BLOCK2_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W1_S 0 - -/** EFUSE_APB2OTP_BLK2_W2_REG register - * eFuse apb2otp block2 data register2. - */ -#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c) -/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W2_M (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S) -#define EFUSE_APB2OTP_BLOCK2_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W2_S 0 - -/** EFUSE_APB2OTP_BLK2_W3_REG register - * eFuse apb2otp block2 data register3. - */ -#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880) -/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W3_M (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S) -#define EFUSE_APB2OTP_BLOCK2_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W3_S 0 - -/** EFUSE_APB2OTP_BLK2_W4_REG register - * eFuse apb2otp block2 data register4. - */ -#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884) -/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W4_M (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S) -#define EFUSE_APB2OTP_BLOCK2_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W4_S 0 - -/** EFUSE_APB2OTP_BLK2_W5_REG register - * eFuse apb2otp block2 data register5. - */ -#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888) -/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W5_M (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S) -#define EFUSE_APB2OTP_BLOCK2_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W5_S 0 - -/** EFUSE_APB2OTP_BLK2_W6_REG register - * eFuse apb2otp block2 data register6. - */ -#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c) -/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W6_M (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S) -#define EFUSE_APB2OTP_BLOCK2_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W6_S 0 - -/** EFUSE_APB2OTP_BLK2_W7_REG register - * eFuse apb2otp block2 data register7. - */ -#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890) -/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W7_M (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S) -#define EFUSE_APB2OTP_BLOCK2_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W7_S 0 - -/** EFUSE_APB2OTP_BLK2_W8_REG register - * eFuse apb2otp block2 data register8. - */ -#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894) -/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W8_M (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S) -#define EFUSE_APB2OTP_BLOCK2_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W8_S 0 - -/** EFUSE_APB2OTP_BLK2_W9_REG register - * eFuse apb2otp block2 data register9. - */ -#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898) -/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W9_M (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S) -#define EFUSE_APB2OTP_BLOCK2_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W9_S 0 - -/** EFUSE_APB2OTP_BLK2_W10_REG register - * eFuse apb2otp block2 data register10. - */ -#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c) -/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W10_M (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S) -#define EFUSE_APB2OTP_BLOCK2_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W10_S 0 - -/** EFUSE_APB2OTP_BLK2_W11_REG register - * eFuse apb2otp block2 data register11. - */ -#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0) -/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W11_M (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S) -#define EFUSE_APB2OTP_BLOCK2_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W11_S 0 - -/** EFUSE_APB2OTP_BLK3_W1_REG register - * eFuse apb2otp block3 data register1. - */ -#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4) -/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W1_M (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S) -#define EFUSE_APB2OTP_BLOCK3_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W1_S 0 - -/** EFUSE_APB2OTP_BLK3_W2_REG register - * eFuse apb2otp block3 data register2. - */ -#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8) -/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W2_M (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S) -#define EFUSE_APB2OTP_BLOCK3_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W2_S 0 - -/** EFUSE_APB2OTP_BLK3_W3_REG register - * eFuse apb2otp block3 data register3. - */ -#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac) -/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W3_M (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S) -#define EFUSE_APB2OTP_BLOCK3_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W3_S 0 - -/** EFUSE_APB2OTP_BLK3_W4_REG register - * eFuse apb2otp block3 data register4. - */ -#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0) -/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W4_M (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S) -#define EFUSE_APB2OTP_BLOCK3_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W4_S 0 - -/** EFUSE_APB2OTP_BLK3_W5_REG register - * eFuse apb2otp block3 data register5. - */ -#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4) -/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W5_M (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S) -#define EFUSE_APB2OTP_BLOCK3_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W5_S 0 - -/** EFUSE_APB2OTP_BLK3_W6_REG register - * eFuse apb2otp block3 data register6. - */ -#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8) -/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W6_M (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S) -#define EFUSE_APB2OTP_BLOCK3_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W6_S 0 - -/** EFUSE_APB2OTP_BLK3_W7_REG register - * eFuse apb2otp block3 data register7. - */ -#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc) -/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W7_M (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S) -#define EFUSE_APB2OTP_BLOCK3_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W7_S 0 - -/** EFUSE_APB2OTP_BLK3_W8_REG register - * eFuse apb2otp block3 data register8. - */ -#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0) -/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W8_M (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S) -#define EFUSE_APB2OTP_BLOCK3_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W8_S 0 - -/** EFUSE_APB2OTP_BLK3_W9_REG register - * eFuse apb2otp block3 data register9. - */ -#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4) -/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W9_M (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S) -#define EFUSE_APB2OTP_BLOCK3_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W9_S 0 - -/** EFUSE_APB2OTP_BLK3_W10_REG register - * eFuse apb2otp block3 data register10. - */ -#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8) -/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W10_M (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S) -#define EFUSE_APB2OTP_BLOCK3_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W10_S 0 - -/** EFUSE_APB2OTP_BLK3_W11_REG register - * eFuse apb2otp block3 data register11. - */ -#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc) -/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W11_M (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S) -#define EFUSE_APB2OTP_BLOCK3_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W11_S 0 - -/** EFUSE_APB2OTP_BLK4_W1_REG register - * eFuse apb2otp block4 data register1. - */ -#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0) -/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W1_M (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S) -#define EFUSE_APB2OTP_BLOCK4_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W1_S 0 - -/** EFUSE_APB2OTP_BLK4_W2_REG register - * eFuse apb2otp block4 data register2. - */ -#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4) -/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W2_M (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S) -#define EFUSE_APB2OTP_BLOCK4_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W2_S 0 - -/** EFUSE_APB2OTP_BLK4_W3_REG register - * eFuse apb2otp block4 data register3. - */ -#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8) -/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W3_M (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S) -#define EFUSE_APB2OTP_BLOCK4_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W3_S 0 - -/** EFUSE_APB2OTP_BLK4_W4_REG register - * eFuse apb2otp block4 data register4. - */ -#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc) -/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W4_M (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S) -#define EFUSE_APB2OTP_BLOCK4_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W4_S 0 - -/** EFUSE_APB2OTP_BLK4_W5_REG register - * eFuse apb2otp block4 data register5. - */ -#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0) -/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W5_M (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S) -#define EFUSE_APB2OTP_BLOCK4_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W5_S 0 - -/** EFUSE_APB2OTP_BLK4_W6_REG register - * eFuse apb2otp block4 data register6. - */ -#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4) -/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W6_M (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S) -#define EFUSE_APB2OTP_BLOCK4_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W6_S 0 - -/** EFUSE_APB2OTP_BLK4_W7_REG register - * eFuse apb2otp block4 data register7. - */ -#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8) -/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W7_M (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S) -#define EFUSE_APB2OTP_BLOCK4_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W7_S 0 - -/** EFUSE_APB2OTP_BLK4_W8_REG register - * eFuse apb2otp block4 data register8. - */ -#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec) -/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W8_M (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S) -#define EFUSE_APB2OTP_BLOCK4_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W8_S 0 - -/** EFUSE_APB2OTP_BLK4_W9_REG register - * eFuse apb2otp block4 data register9. - */ -#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0) -/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W9_M (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S) -#define EFUSE_APB2OTP_BLOCK4_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W9_S 0 - -/** EFUSE_APB2OTP_BLK4_W10_REG register - * eFuse apb2otp block4 data registe10. - */ -#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4) -/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W10_M (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S) -#define EFUSE_APB2OTP_BLOCK4_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W10_S 0 - -/** EFUSE_APB2OTP_BLK4_W11_REG register - * eFuse apb2otp block4 data register11. - */ -#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8) -/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W11_M (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S) -#define EFUSE_APB2OTP_BLOCK4_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W11_S 0 - -/** EFUSE_APB2OTP_BLK5_W1_REG register - * eFuse apb2otp block5 data register1. - */ -#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc) -/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W1_M (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S) -#define EFUSE_APB2OTP_BLOCK5_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W1_S 0 - -/** EFUSE_APB2OTP_BLK5_W2_REG register - * eFuse apb2otp block5 data register2. - */ -#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900) -/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W2_M (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S) -#define EFUSE_APB2OTP_BLOCK5_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W2_S 0 - -/** EFUSE_APB2OTP_BLK5_W3_REG register - * eFuse apb2otp block5 data register3. - */ -#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904) -/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W3_M (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S) -#define EFUSE_APB2OTP_BLOCK5_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W3_S 0 - -/** EFUSE_APB2OTP_BLK5_W4_REG register - * eFuse apb2otp block5 data register4. - */ -#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908) -/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W4_M (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S) -#define EFUSE_APB2OTP_BLOCK5_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W4_S 0 - -/** EFUSE_APB2OTP_BLK5_W5_REG register - * eFuse apb2otp block5 data register5. - */ -#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c) -/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W5_M (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S) -#define EFUSE_APB2OTP_BLOCK5_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W5_S 0 - -/** EFUSE_APB2OTP_BLK5_W6_REG register - * eFuse apb2otp block5 data register6. - */ -#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910) -/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W6_M (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S) -#define EFUSE_APB2OTP_BLOCK5_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W6_S 0 - -/** EFUSE_APB2OTP_BLK5_W7_REG register - * eFuse apb2otp block5 data register7. - */ -#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914) -/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W7_M (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S) -#define EFUSE_APB2OTP_BLOCK5_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W7_S 0 - -/** EFUSE_APB2OTP_BLK5_W8_REG register - * eFuse apb2otp block5 data register8. - */ -#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918) -/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W8_M (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S) -#define EFUSE_APB2OTP_BLOCK5_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W8_S 0 - -/** EFUSE_APB2OTP_BLK5_W9_REG register - * eFuse apb2otp block5 data register9. - */ -#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c) -/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W9_M (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S) -#define EFUSE_APB2OTP_BLOCK5_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W9_S 0 - -/** EFUSE_APB2OTP_BLK5_W10_REG register - * eFuse apb2otp block5 data register10. - */ -#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920) -/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W10_M (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S) -#define EFUSE_APB2OTP_BLOCK5_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W10_S 0 - -/** EFUSE_APB2OTP_BLK5_W11_REG register - * eFuse apb2otp block5 data register11. - */ -#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924) -/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W11_M (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S) -#define EFUSE_APB2OTP_BLOCK5_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W11_S 0 - -/** EFUSE_APB2OTP_BLK6_W1_REG register - * eFuse apb2otp block6 data register1. - */ -#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928) -/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W1_M (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S) -#define EFUSE_APB2OTP_BLOCK6_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W1_S 0 - -/** EFUSE_APB2OTP_BLK6_W2_REG register - * eFuse apb2otp block6 data register2. - */ -#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c) -/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W2_M (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S) -#define EFUSE_APB2OTP_BLOCK6_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W2_S 0 - -/** EFUSE_APB2OTP_BLK6_W3_REG register - * eFuse apb2otp block6 data register3. - */ -#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930) -/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W3_M (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S) -#define EFUSE_APB2OTP_BLOCK6_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W3_S 0 - -/** EFUSE_APB2OTP_BLK6_W4_REG register - * eFuse apb2otp block6 data register4. - */ -#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934) -/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W4_M (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S) -#define EFUSE_APB2OTP_BLOCK6_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W4_S 0 - -/** EFUSE_APB2OTP_BLK6_W5_REG register - * eFuse apb2otp block6 data register5. - */ -#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938) -/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W5_M (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S) -#define EFUSE_APB2OTP_BLOCK6_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W5_S 0 - -/** EFUSE_APB2OTP_BLK6_W6_REG register - * eFuse apb2otp block6 data register6. - */ -#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c) -/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W6_M (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S) -#define EFUSE_APB2OTP_BLOCK6_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W6_S 0 - -/** EFUSE_APB2OTP_BLK6_W7_REG register - * eFuse apb2otp block6 data register7. - */ -#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940) -/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W7_M (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S) -#define EFUSE_APB2OTP_BLOCK6_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W7_S 0 - -/** EFUSE_APB2OTP_BLK6_W8_REG register - * eFuse apb2otp block6 data register8. - */ -#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944) -/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W8_M (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S) -#define EFUSE_APB2OTP_BLOCK6_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W8_S 0 - -/** EFUSE_APB2OTP_BLK6_W9_REG register - * eFuse apb2otp block6 data register9. - */ -#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948) -/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W9_M (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S) -#define EFUSE_APB2OTP_BLOCK6_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W9_S 0 - -/** EFUSE_APB2OTP_BLK6_W10_REG register - * eFuse apb2otp block6 data register10. - */ -#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c) -/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W10_M (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S) -#define EFUSE_APB2OTP_BLOCK6_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W10_S 0 - -/** EFUSE_APB2OTP_BLK6_W11_REG register - * eFuse apb2otp block6 data register11. - */ -#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950) -/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W11_M (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S) -#define EFUSE_APB2OTP_BLOCK6_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W11_S 0 - -/** EFUSE_APB2OTP_BLK7_W1_REG register - * eFuse apb2otp block7 data register1. - */ -#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954) -/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W1_M (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S) -#define EFUSE_APB2OTP_BLOCK7_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W1_S 0 - -/** EFUSE_APB2OTP_BLK7_W2_REG register - * eFuse apb2otp block7 data register2. - */ -#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958) -/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W2_M (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S) -#define EFUSE_APB2OTP_BLOCK7_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W2_S 0 - -/** EFUSE_APB2OTP_BLK7_W3_REG register - * eFuse apb2otp block7 data register3. - */ -#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c) -/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W3_M (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S) -#define EFUSE_APB2OTP_BLOCK7_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W3_S 0 - -/** EFUSE_APB2OTP_BLK7_W4_REG register - * eFuse apb2otp block7 data register4. - */ -#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960) -/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W4_M (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S) -#define EFUSE_APB2OTP_BLOCK7_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W4_S 0 - -/** EFUSE_APB2OTP_BLK7_W5_REG register - * eFuse apb2otp block7 data register5. - */ -#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964) -/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W5_M (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S) -#define EFUSE_APB2OTP_BLOCK7_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W5_S 0 - -/** EFUSE_APB2OTP_BLK7_W6_REG register - * eFuse apb2otp block7 data register6. - */ -#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968) -/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W6_M (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S) -#define EFUSE_APB2OTP_BLOCK7_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W6_S 0 - -/** EFUSE_APB2OTP_BLK7_W7_REG register - * eFuse apb2otp block7 data register7. - */ -#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c) -/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W7_M (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S) -#define EFUSE_APB2OTP_BLOCK7_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W7_S 0 - -/** EFUSE_APB2OTP_BLK7_W8_REG register - * eFuse apb2otp block7 data register8. - */ -#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970) -/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W8_M (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S) -#define EFUSE_APB2OTP_BLOCK7_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W8_S 0 - -/** EFUSE_APB2OTP_BLK7_W9_REG register - * eFuse apb2otp block7 data register9. - */ -#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974) -/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W9_M (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S) -#define EFUSE_APB2OTP_BLOCK7_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W9_S 0 - -/** EFUSE_APB2OTP_BLK7_W10_REG register - * eFuse apb2otp block7 data register10. - */ -#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978) -/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W10_M (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S) -#define EFUSE_APB2OTP_BLOCK7_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W10_S 0 - -/** EFUSE_APB2OTP_BLK7_W11_REG register - * eFuse apb2otp block7 data register11. - */ -#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c) -/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W11_M (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S) -#define EFUSE_APB2OTP_BLOCK7_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W11_S 0 - -/** EFUSE_APB2OTP_BLK8_W1_REG register - * eFuse apb2otp block8 data register1. - */ -#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980) -/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W1_M (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S) -#define EFUSE_APB2OTP_BLOCK8_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W1_S 0 - -/** EFUSE_APB2OTP_BLK8_W2_REG register - * eFuse apb2otp block8 data register2. - */ -#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984) -/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W2_M (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S) -#define EFUSE_APB2OTP_BLOCK8_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W2_S 0 - -/** EFUSE_APB2OTP_BLK8_W3_REG register - * eFuse apb2otp block8 data register3. - */ -#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988) -/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W3_M (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S) -#define EFUSE_APB2OTP_BLOCK8_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W3_S 0 - -/** EFUSE_APB2OTP_BLK8_W4_REG register - * eFuse apb2otp block8 data register4. - */ -#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c) -/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W4_M (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S) -#define EFUSE_APB2OTP_BLOCK8_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W4_S 0 - -/** EFUSE_APB2OTP_BLK8_W5_REG register - * eFuse apb2otp block8 data register5. - */ -#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990) -/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W5_M (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S) -#define EFUSE_APB2OTP_BLOCK8_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W5_S 0 - -/** EFUSE_APB2OTP_BLK8_W6_REG register - * eFuse apb2otp block8 data register6. - */ -#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994) -/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W6_M (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S) -#define EFUSE_APB2OTP_BLOCK8_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W6_S 0 - -/** EFUSE_APB2OTP_BLK8_W7_REG register - * eFuse apb2otp block8 data register7. - */ -#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998) -/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W7_M (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S) -#define EFUSE_APB2OTP_BLOCK8_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W7_S 0 - -/** EFUSE_APB2OTP_BLK8_W8_REG register - * eFuse apb2otp block8 data register8. - */ -#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c) -/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W8_M (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S) -#define EFUSE_APB2OTP_BLOCK8_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W8_S 0 - -/** EFUSE_APB2OTP_BLK8_W9_REG register - * eFuse apb2otp block8 data register9. - */ -#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0) -/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W9_M (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S) -#define EFUSE_APB2OTP_BLOCK8_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W9_S 0 - -/** EFUSE_APB2OTP_BLK8_W10_REG register - * eFuse apb2otp block8 data register10. - */ -#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4) -/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W10_M (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S) -#define EFUSE_APB2OTP_BLOCK8_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W10_S 0 - -/** EFUSE_APB2OTP_BLK8_W11_REG register - * eFuse apb2otp block8 data register11. - */ -#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8) -/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W11_M (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S) -#define EFUSE_APB2OTP_BLOCK8_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W11_S 0 - -/** EFUSE_APB2OTP_BLK9_W1_REG register - * eFuse apb2otp block9 data register1. - */ -#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac) -/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W1_M (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S) -#define EFUSE_APB2OTP_BLOCK9_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W1_S 0 - -/** EFUSE_APB2OTP_BLK9_W2_REG register - * eFuse apb2otp block9 data register2. - */ -#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0) -/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W2_M (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S) -#define EFUSE_APB2OTP_BLOCK9_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W2_S 0 - -/** EFUSE_APB2OTP_BLK9_W3_REG register - * eFuse apb2otp block9 data register3. - */ -#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4) -/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W3_M (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S) -#define EFUSE_APB2OTP_BLOCK9_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W3_S 0 - -/** EFUSE_APB2OTP_BLK9_W4_REG register - * eFuse apb2otp block9 data register4. - */ -#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8) -/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W4_M (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S) -#define EFUSE_APB2OTP_BLOCK9_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W4_S 0 - -/** EFUSE_APB2OTP_BLK9_W5_REG register - * eFuse apb2otp block9 data register5. - */ -#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc) -/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W5_M (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S) -#define EFUSE_APB2OTP_BLOCK9_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W5_S 0 - -/** EFUSE_APB2OTP_BLK9_W6_REG register - * eFuse apb2otp block9 data register6. - */ -#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0) -/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W6_M (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S) -#define EFUSE_APB2OTP_BLOCK9_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W6_S 0 - -/** EFUSE_APB2OTP_BLK9_W7_REG register - * eFuse apb2otp block9 data register7. - */ -#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4) -/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W7_M (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S) -#define EFUSE_APB2OTP_BLOCK9_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W7_S 0 - -/** EFUSE_APB2OTP_BLK9_W8_REG register - * eFuse apb2otp block9 data register8. - */ -#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8) -/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W8_M (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S) -#define EFUSE_APB2OTP_BLOCK9_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W8_S 0 - -/** EFUSE_APB2OTP_BLK9_W9_REG register - * eFuse apb2otp block9 data register9. - */ -#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc) -/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W9_M (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S) -#define EFUSE_APB2OTP_BLOCK9_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W9_S 0 - -/** EFUSE_APB2OTP_BLK9_W10_REG register - * eFuse apb2otp block9 data register10. - */ -#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0) -/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W10_M (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S) -#define EFUSE_APB2OTP_BLOCK9_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W10_S 0 - -/** EFUSE_APB2OTP_BLK9_W11_REG register - * eFuse apb2otp block9 data register11. - */ -#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4) -/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W11_M (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S) -#define EFUSE_APB2OTP_BLOCK9_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W11_S 0 - -/** EFUSE_APB2OTP_BLK10_W1_REG register - * eFuse apb2otp block10 data register1. - */ -#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8) -/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W1_M (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S) -#define EFUSE_APB2OTP_BLOCK10_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W1_S 0 - -/** EFUSE_APB2OTP_BLK10_W2_REG register - * eFuse apb2otp block10 data register2. - */ -#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc) -/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W2_M (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S) -#define EFUSE_APB2OTP_BLOCK10_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W2_S 0 - -/** EFUSE_APB2OTP_BLK10_W3_REG register - * eFuse apb2otp block10 data register3. - */ -#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0) -/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W3_M (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S) -#define EFUSE_APB2OTP_BLOCK10_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W3_S 0 - -/** EFUSE_APB2OTP_BLK10_W4_REG register - * eFuse apb2otp block10 data register4. - */ -#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4) -/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W4_M (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S) -#define EFUSE_APB2OTP_BLOCK10_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W4_S 0 - -/** EFUSE_APB2OTP_BLK10_W5_REG register - * eFuse apb2otp block10 data register5. - */ -#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8) -/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W5_M (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S) -#define EFUSE_APB2OTP_BLOCK10_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W5_S 0 - -/** EFUSE_APB2OTP_BLK10_W6_REG register - * eFuse apb2otp block10 data register6. - */ -#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec) -/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W6_M (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S) -#define EFUSE_APB2OTP_BLOCK10_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W6_S 0 - -/** EFUSE_APB2OTP_BLK10_W7_REG register - * eFuse apb2otp block10 data register7. - */ -#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0) -/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W7_M (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S) -#define EFUSE_APB2OTP_BLOCK10_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W7_S 0 - -/** EFUSE_APB2OTP_BLK10_W8_REG register - * eFuse apb2otp block10 data register8. - */ -#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4) -/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W8_M (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S) -#define EFUSE_APB2OTP_BLOCK10_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W8_S 0 - -/** EFUSE_APB2OTP_BLK10_W9_REG register - * eFuse apb2otp block10 data register9. - */ -#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8) -/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W9_M (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S) -#define EFUSE_APB2OTP_BLOCK10_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W9_S 0 - -/** EFUSE_APB2OTP_BLK10_W10_REG register - * eFuse apb2otp block10 data register10. - */ -#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc) -/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK19_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK19_W10_M (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S) -#define EFUSE_APB2OTP_BLOCK19_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK19_W10_S 0 - -/** EFUSE_APB2OTP_BLK10_W11_REG register - * eFuse apb2otp block10 data register11. - */ -#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00) -/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W11_M (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S) -#define EFUSE_APB2OTP_BLOCK10_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W11_S 0 - -/** EFUSE_APB2OTP_EN_REG register - * eFuse apb2otp enable configuration register. - */ -#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08) -/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0; - * Apb2otp mode enable signal. - */ -#define EFUSE_APB2OTP_APB2OTP_EN (BIT(0)) -#define EFUSE_APB2OTP_APB2OTP_EN_M (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S) -#define EFUSE_APB2OTP_APB2OTP_EN_V 0x00000001U -#define EFUSE_APB2OTP_APB2OTP_EN_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/efuse_mem_struct.h b/components/soc/esp32p4/include/soc/efuse_mem_struct.h deleted file mode 100644 index 5db3b2ace5..0000000000 --- a/components/soc/esp32p4/include/soc/efuse_mem_struct.h +++ /dev/null @@ -1,4449 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: PGM Data Register */ -/** Type of pgm_data0 register - * Register 0 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_0:32; - }; - uint32_t val; -} efuse_pgm_data0_reg_t; - -/** Type of pgm_data1 register - * Register 1 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. - */ - uint32_t pgm_data_1:32; - }; - uint32_t val; -} efuse_pgm_data1_reg_t; - -/** Type of pgm_data2 register - * Register 2 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. - */ - uint32_t pgm_data_2:32; - }; - uint32_t val; -} efuse_pgm_data2_reg_t; - -/** Type of pgm_data3 register - * Register 3 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. - */ - uint32_t pgm_data_3:32; - }; - uint32_t val; -} efuse_pgm_data3_reg_t; - -/** Type of pgm_data4 register - * Register 4 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. - */ - uint32_t pgm_data_4:32; - }; - uint32_t val; -} efuse_pgm_data4_reg_t; - -/** Type of pgm_data5 register - * Register 5 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. - */ - uint32_t pgm_data_5:32; - }; - uint32_t val; -} efuse_pgm_data5_reg_t; - -/** Type of pgm_data6 register - * Register 6 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. - */ - uint32_t pgm_data_6:32; - }; - uint32_t val; -} efuse_pgm_data6_reg_t; - -/** Type of pgm_data7 register - * Register 7 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. - */ - uint32_t pgm_data_7:32; - }; - uint32_t val; -} efuse_pgm_data7_reg_t; - -/** Type of pgm_check_value0 register - * Register 0 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_0:32; - }; - uint32_t val; -} efuse_pgm_check_value0_reg_t; - -/** Type of pgm_check_value1 register - * Register 1 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_1:32; - }; - uint32_t val; -} efuse_pgm_check_value1_reg_t; - -/** Type of pgm_check_value2 register - * Register 2 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_2:32; - }; - uint32_t val; -} efuse_pgm_check_value2_reg_t; - - -/** Group: ******** Registers */ -/** Type of rd_wr_dis register - * BLOCK0 data register 0. - */ -typedef union { - struct { - /** wr_dis : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. - */ - uint32_t wr_dis:32; - }; - uint32_t val; -} efuse_rd_wr_dis_reg_t; - -/** Type of rd_repeat_data0 register - * BLOCK0 data register 1. - */ -typedef union { - struct { - /** rd_dis : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. 1: disabled. 0: enabled. - */ - uint32_t rd_dis:7; - /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0; - * Enable usb device exchange pins of D+ and D-. - */ - uint32_t usb_device_exchg_pins:1; - /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0; - * Enable usb otg11 exchange pins of D+ and D-. - */ - uint32_t usb_otg11_exchg_pins:1; - /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. 1: - * disabled. 0: enabled. - */ - uint32_t dis_usb_jtag:1; - /** powerglitch_en : RO; bitpos: [10]; default: 0; - * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. - */ - uint32_t powerglitch_en:1; - uint32_t reserved_11:1; - /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled. 1: disabled. 0: enabled. - */ - uint32_t dis_force_download:1; - /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during - * boot_mode_download. - */ - uint32_t spi_download_mspi_dis:1; - /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. - */ - uint32_t dis_twai:1; - /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Represents whether the selection between usb_to_jtag and pad_to_jtag through - * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled. 1: enabled. 0: disabled. - */ - uint32_t jtag_sel_enable:1; - /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. - */ - uint32_t soft_dis_jtag:3; - /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. - */ - uint32_t dis_pad_jtag:1; - /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). 1: disabled. 0: enabled. - */ - uint32_t dis_download_manual_encrypt:1; - uint32_t reserved_21:4; - /** usb_phy_sel : RO; bitpos: [25]; default: 0; - * TBD - */ - uint32_t usb_phy_sel:1; - /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. - */ - uint32_t km_huk_gen_state_low:6; - }; - uint32_t val; -} efuse_rd_repeat_data0_reg_t; - -/** Type of rd_repeat_data1 register - * BLOCK0 data register 2. - */ -typedef union { - struct { - /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. - */ - uint32_t km_huk_gen_state_high:3; - /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0; - * Set bits to control key manager random number switch cycle. 0: control by register. - * 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. - */ - uint32_t km_rnd_switch_cycle:2; - /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0; - * Set each bit to control whether corresponding key can only be deployed once. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - */ - uint32_t km_deploy_only_once:4; - /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0; - * Set each bit to control whether corresponding key must come from key manager.. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - */ - uint32_t force_use_key_manager_key:4; - /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0; - * Set this bit to disable software written init key, and force use efuse_init_key. - */ - uint32_t force_disable_sw_init_key:1; - /** xts_key_length_256 : RO; bitpos: [14]; default: 0; - * Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. - */ - uint32_t xts_key_length_256:1; - uint32_t reserved_15:1; - /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. - */ - uint32_t wdt_delay_sel:2; - /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of - * 1: enabled. Even number of 1: disabled. - */ - uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. - */ - uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. - */ - uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. - */ - uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. - */ - uint32_t key_purpose_0:4; - /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. - */ - uint32_t key_purpose_1:4; - }; - uint32_t val; -} efuse_rd_repeat_data1_reg_t; - -/** Type of rd_repeat_data2 register - * BLOCK0 data register 3. - */ -typedef union { - struct { - /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. - */ - uint32_t key_purpose_2:4; - /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. - */ - uint32_t key_purpose_3:4; - /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. - */ - uint32_t key_purpose_4:4; - /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. - */ - uint32_t key_purpose_5:4; - /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. - */ - uint32_t sec_dpa_level:2; - /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0; - * Represents whether hardware random number k is forced used in ESDCA. 1: force used. - * 0: not force used. - */ - uint32_t ecdsa_enable_soft_k:1; - /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. - */ - uint32_t crypt_dpa_enable:1; - /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. - */ - uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. 1: - * enabled. 0: disabled. - */ - uint32_t secure_boot_aggressive_revoke:1; - uint32_t reserved_22:1; - /** flash_type : RO; bitpos: [23]; default: 0; - * The type of interfaced flash. 0: four data lines, 1: eight data lines. - */ - uint32_t flash_type:1; - /** flash_page_size : RO; bitpos: [25:24]; default: 0; - * Set flash page size. - */ - uint32_t flash_page_size:2; - /** flash_ecc_en : RO; bitpos: [26]; default: 0; - * Set this bit to enable ecc for flash boot. - */ - uint32_t flash_ecc_en:1; - /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0; - * Set this bit to disable download via USB-OTG. - */ - uint32_t dis_usb_otg_download_mode:1; - /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. - */ - uint32_t flash_tpuw:4; - }; - uint32_t val; -} efuse_rd_repeat_data2_reg_t; - -/** Type of rd_repeat_data3 register - * BLOCK0 data register 4. - */ -typedef union { - struct { - /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. - */ - uint32_t dis_download_mode:1; - /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. - */ - uint32_t dis_direct_boot:1; - /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. - * 0: enabled. - */ - uint32_t dis_usb_serial_jtag_rom_print:1; - /** lock_km_key : RO; bitpos: [3]; default: 0; - * TBD - */ - uint32_t lock_km_key:1; - /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. - */ - uint32_t dis_usb_serial_jtag_download_mode:1; - /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled. 1: enabled. 0: - * disabled. - */ - uint32_t enable_security_download:1; - /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. 00: force enable printing. 01: enable - * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset - * at high level. 11: force disable printing. - */ - uint32_t uart_print_control:2; - /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. - */ - uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. - */ - uint32_t secure_version:16; - /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. 1: disabled. 0: enabled. - */ - uint32_t secure_boot_disable_fast_wake:1; - /** hys_en_pad : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled. 1: - * enabled. 0:disabled. - */ - uint32_t hys_en_pad:1; - /** dcdc_vset : RO; bitpos: [31:27]; default: 0; - * Set the dcdc voltage default. - */ - uint32_t dcdc_vset:5; - }; - uint32_t val; -} efuse_rd_repeat_data3_reg_t; - -/** Type of rd_repeat_data4 register - * BLOCK0 data register 5. - */ -typedef union { - struct { - /** 0pxa_tieh_sel_0 : RO; bitpos: [1:0]; default: 0; - * TBD - */ - uint32_t rd_0pxa_tieh_sel_0:2; - /** 0pxa_tieh_sel_1 : RO; bitpos: [3:2]; default: 0; - * TBD. - */ - uint32_t rd_0pxa_tieh_sel_1:2; - /** 0pxa_tieh_sel_2 : RO; bitpos: [5:4]; default: 0; - * TBD. - */ - uint32_t rd_0pxa_tieh_sel_2:2; - /** 0pxa_tieh_sel_3 : RO; bitpos: [7:6]; default: 0; - * TBD. - */ - uint32_t rd_0pxa_tieh_sel_3:2; - /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0; - * TBD. - */ - uint32_t km_disable_deploy_mode:4; - uint32_t reserved_12:6; - /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0; - * HP system power source select. 0:LDO. 1: DCDC. - */ - uint32_t hp_pwr_src_sel:1; - /** dcdc_vset_en : RO; bitpos: [19]; default: 0; - * Select dcdc vset use efuse_dcdc_vset. - */ - uint32_t dcdc_vset_en:1; - /** dis_wdt : RO; bitpos: [20]; default: 0; - * Set this bit to disable watch dog. - */ - uint32_t dis_wdt:1; - /** dis_swd : RO; bitpos: [21]; default: 0; - * Set this bit to disable super-watchdog. - */ - uint32_t dis_swd:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} efuse_rd_repeat_data4_reg_t; - -/** Type of rd_mac_sys_0 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ - uint32_t mac_0:32; - }; - uint32_t val; -} efuse_rd_mac_sys_0_reg_t; - -/** Type of rd_mac_sys_1 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ - uint32_t mac_1:16; - /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. - */ - uint32_t mac_ext:16; - }; - uint32_t val; -} efuse_rd_mac_sys_1_reg_t; - -/** Type of rd_mac_sys_2 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_1:14; - /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_0:18; - }; - uint32_t val; -} efuse_rd_mac_sys_2_reg_t; - -/** Type of rd_mac_sys_3 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_2:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the first 14 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_0:14; - }; - uint32_t val; -} efuse_rd_mac_sys_3_reg_t; - -/** Type of rd_mac_sys_4 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_1:32; - }; - uint32_t val; -} efuse_rd_mac_sys_4_reg_t; - -/** Type of rd_mac_sys_5 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_2:32; - }; - uint32_t val; -} efuse_rd_mac_sys_5_reg_t; - -/** Type of rd_sys_part1_data0 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_0:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data0_reg_t; - -/** Type of rd_sys_part1_data1 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_1:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data1_reg_t; - -/** Type of rd_sys_part1_data2 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_2:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data2_reg_t; - -/** Type of rd_sys_part1_data3 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_3:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data3_reg_t; - -/** Type of rd_sys_part1_data4 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_4:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data4_reg_t; - -/** Type of rd_sys_part1_data5 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_5:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data5_reg_t; - -/** Type of rd_sys_part1_data6 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_6:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data6_reg_t; - -/** Type of rd_sys_part1_data7 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_7:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data7_reg_t; - -/** Type of rd_usr_data0 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data0:32; - }; - uint32_t val; -} efuse_rd_usr_data0_reg_t; - -/** Type of rd_usr_data1 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ - uint32_t usr_data1:32; - }; - uint32_t val; -} efuse_rd_usr_data1_reg_t; - -/** Type of rd_usr_data2 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ - uint32_t usr_data2:32; - }; - uint32_t val; -} efuse_rd_usr_data2_reg_t; - -/** Type of rd_usr_data3 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ - uint32_t usr_data3:32; - }; - uint32_t val; -} efuse_rd_usr_data3_reg_t; - -/** Type of rd_usr_data4 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data4:32; - }; - uint32_t val; -} efuse_rd_usr_data4_reg_t; - -/** Type of rd_usr_data5 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data5:32; - }; - uint32_t val; -} efuse_rd_usr_data5_reg_t; - -/** Type of rd_usr_data6 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data6:32; - }; - uint32_t val; -} efuse_rd_usr_data6_reg_t; - -/** Type of rd_usr_data7 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). - */ - uint32_t usr_data7:32; - }; - uint32_t val; -} efuse_rd_usr_data7_reg_t; - -/** Type of rd_key0_data0 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ - uint32_t key0_data0:32; - }; - uint32_t val; -} efuse_rd_key0_data0_reg_t; - -/** Type of rd_key0_data1 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. - */ - uint32_t key0_data1:32; - }; - uint32_t val; -} efuse_rd_key0_data1_reg_t; - -/** Type of rd_key0_data2 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ - uint32_t key0_data2:32; - }; - uint32_t val; -} efuse_rd_key0_data2_reg_t; - -/** Type of rd_key0_data3 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. - */ - uint32_t key0_data3:32; - }; - uint32_t val; -} efuse_rd_key0_data3_reg_t; - -/** Type of rd_key0_data4 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ - uint32_t key0_data4:32; - }; - uint32_t val; -} efuse_rd_key0_data4_reg_t; - -/** Type of rd_key0_data5 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. - */ - uint32_t key0_data5:32; - }; - uint32_t val; -} efuse_rd_key0_data5_reg_t; - -/** Type of rd_key0_data6 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ - uint32_t key0_data6:32; - }; - uint32_t val; -} efuse_rd_key0_data6_reg_t; - -/** Type of rd_key0_data7 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ - uint32_t key0_data7:32; - }; - uint32_t val; -} efuse_rd_key0_data7_reg_t; - -/** Type of rd_key1_data0 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ - uint32_t key1_data0:32; - }; - uint32_t val; -} efuse_rd_key1_data0_reg_t; - -/** Type of rd_key1_data1 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ - uint32_t key1_data1:32; - }; - uint32_t val; -} efuse_rd_key1_data1_reg_t; - -/** Type of rd_key1_data2 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ - uint32_t key1_data2:32; - }; - uint32_t val; -} efuse_rd_key1_data2_reg_t; - -/** Type of rd_key1_data3 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ - uint32_t key1_data3:32; - }; - uint32_t val; -} efuse_rd_key1_data3_reg_t; - -/** Type of rd_key1_data4 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ - uint32_t key1_data4:32; - }; - uint32_t val; -} efuse_rd_key1_data4_reg_t; - -/** Type of rd_key1_data5 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ - uint32_t key1_data5:32; - }; - uint32_t val; -} efuse_rd_key1_data5_reg_t; - -/** Type of rd_key1_data6 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ - uint32_t key1_data6:32; - }; - uint32_t val; -} efuse_rd_key1_data6_reg_t; - -/** Type of rd_key1_data7 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ - uint32_t key1_data7:32; - }; - uint32_t val; -} efuse_rd_key1_data7_reg_t; - -/** Type of rd_key2_data0 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ - uint32_t key2_data0:32; - }; - uint32_t val; -} efuse_rd_key2_data0_reg_t; - -/** Type of rd_key2_data1 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ - uint32_t key2_data1:32; - }; - uint32_t val; -} efuse_rd_key2_data1_reg_t; - -/** Type of rd_key2_data2 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ - uint32_t key2_data2:32; - }; - uint32_t val; -} efuse_rd_key2_data2_reg_t; - -/** Type of rd_key2_data3 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ - uint32_t key2_data3:32; - }; - uint32_t val; -} efuse_rd_key2_data3_reg_t; - -/** Type of rd_key2_data4 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ - uint32_t key2_data4:32; - }; - uint32_t val; -} efuse_rd_key2_data4_reg_t; - -/** Type of rd_key2_data5 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ - uint32_t key2_data5:32; - }; - uint32_t val; -} efuse_rd_key2_data5_reg_t; - -/** Type of rd_key2_data6 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ - uint32_t key2_data6:32; - }; - uint32_t val; -} efuse_rd_key2_data6_reg_t; - -/** Type of rd_key2_data7 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ - uint32_t key2_data7:32; - }; - uint32_t val; -} efuse_rd_key2_data7_reg_t; - -/** Type of rd_key3_data0 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ - uint32_t key3_data0:32; - }; - uint32_t val; -} efuse_rd_key3_data0_reg_t; - -/** Type of rd_key3_data1 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ - uint32_t key3_data1:32; - }; - uint32_t val; -} efuse_rd_key3_data1_reg_t; - -/** Type of rd_key3_data2 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ - uint32_t key3_data2:32; - }; - uint32_t val; -} efuse_rd_key3_data2_reg_t; - -/** Type of rd_key3_data3 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ - uint32_t key3_data3:32; - }; - uint32_t val; -} efuse_rd_key3_data3_reg_t; - -/** Type of rd_key3_data4 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ - uint32_t key3_data4:32; - }; - uint32_t val; -} efuse_rd_key3_data4_reg_t; - -/** Type of rd_key3_data5 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ - uint32_t key3_data5:32; - }; - uint32_t val; -} efuse_rd_key3_data5_reg_t; - -/** Type of rd_key3_data6 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ - uint32_t key3_data6:32; - }; - uint32_t val; -} efuse_rd_key3_data6_reg_t; - -/** Type of rd_key3_data7 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ - uint32_t key3_data7:32; - }; - uint32_t val; -} efuse_rd_key3_data7_reg_t; - -/** Type of rd_key4_data0 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ - uint32_t key4_data0:32; - }; - uint32_t val; -} efuse_rd_key4_data0_reg_t; - -/** Type of rd_key4_data1 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ - uint32_t key4_data1:32; - }; - uint32_t val; -} efuse_rd_key4_data1_reg_t; - -/** Type of rd_key4_data2 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ - uint32_t key4_data2:32; - }; - uint32_t val; -} efuse_rd_key4_data2_reg_t; - -/** Type of rd_key4_data3 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ - uint32_t key4_data3:32; - }; - uint32_t val; -} efuse_rd_key4_data3_reg_t; - -/** Type of rd_key4_data4 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ - uint32_t key4_data4:32; - }; - uint32_t val; -} efuse_rd_key4_data4_reg_t; - -/** Type of rd_key4_data5 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ - uint32_t key4_data5:32; - }; - uint32_t val; -} efuse_rd_key4_data5_reg_t; - -/** Type of rd_key4_data6 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ - uint32_t key4_data6:32; - }; - uint32_t val; -} efuse_rd_key4_data6_reg_t; - -/** Type of rd_key4_data7 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ - uint32_t key4_data7:32; - }; - uint32_t val; -} efuse_rd_key4_data7_reg_t; - -/** Type of rd_key5_data0 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ - uint32_t key5_data0:32; - }; - uint32_t val; -} efuse_rd_key5_data0_reg_t; - -/** Type of rd_key5_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ - uint32_t key5_data1:32; - }; - uint32_t val; -} efuse_rd_key5_data1_reg_t; - -/** Type of rd_key5_data2 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ - uint32_t key5_data2:32; - }; - uint32_t val; -} efuse_rd_key5_data2_reg_t; - -/** Type of rd_key5_data3 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ - uint32_t key5_data3:32; - }; - uint32_t val; -} efuse_rd_key5_data3_reg_t; - -/** Type of rd_key5_data4 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ - uint32_t key5_data4:32; - }; - uint32_t val; -} efuse_rd_key5_data4_reg_t; - -/** Type of rd_key5_data5 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ - uint32_t key5_data5:32; - }; - uint32_t val; -} efuse_rd_key5_data5_reg_t; - -/** Type of rd_key5_data6 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ - uint32_t key5_data6:32; - }; - uint32_t val; -} efuse_rd_key5_data6_reg_t; - -/** Type of rd_key5_data7 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ - uint32_t key5_data7:32; - }; - uint32_t val; -} efuse_rd_key5_data7_reg_t; - -/** Type of rd_sys_part2_data0 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_0:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data0_reg_t; - -/** Type of rd_sys_part2_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_1:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data1_reg_t; - -/** Type of rd_sys_part2_data2 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_2:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data2_reg_t; - -/** Type of rd_sys_part2_data3 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_3:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data3_reg_t; - -/** Type of rd_sys_part2_data4 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_4:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data4_reg_t; - -/** Type of rd_sys_part2_data5 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_5:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data5_reg_t; - -/** Type of rd_sys_part2_data6 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_6:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data6_reg_t; - -/** Type of rd_sys_part2_data7 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_7:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data7_reg_t; - -/** Type of rd_repeat_err0 register - * Programming error record register 0 of BLOCK0. - */ -typedef union { - struct { - /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. - */ - uint32_t rd_dis_err:7; - /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0; - * Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. - */ - uint32_t dis_usb_device_exchg_pins_err:1; - /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. - */ - uint32_t dis_usb_otg11_exchg_pins_err:1; - /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. - */ - uint32_t dis_usb_jtag_err:1; - /** powerglitch_en_err : RO; bitpos: [10]; default: 0; - * Indicates a programming error of POWERGLITCH_EN. - */ - uint32_t powerglitch_en_err:1; - uint32_t reserved_11:1; - /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. - */ - uint32_t dis_force_download_err:1; - /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. - */ - uint32_t spi_download_mspi_dis_err:1; - /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_TWAI. - */ - uint32_t dis_twai_err:1; - /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. - */ - uint32_t jtag_sel_enable_err:1; - /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. - */ - uint32_t soft_dis_jtag_err:3; - /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. - */ - uint32_t dis_pad_jtag_err:1; - /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ - uint32_t dis_download_manual_encrypt_err:1; - uint32_t reserved_21:4; - /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_PHY_SEL. - */ - uint32_t usb_phy_sel_err:1; - /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_LOW. - */ - uint32_t huk_gen_state_low_err:6; - }; - uint32_t val; -} efuse_rd_repeat_err0_reg_t; - -/** Type of rd_repeat_err1 register - * Programming error record register 1 of BLOCK0. - */ -typedef union { - struct { - /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_HIGH. - */ - uint32_t km_huk_gen_state_high_err:3; - /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0; - * Indicates a programming error of KM_RND_SWITCH_CYCLE. - */ - uint32_t km_rnd_switch_cycle_err:2; - /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0; - * Indicates a programming error of KM_DEPLOY_ONLY_ONCE. - */ - uint32_t km_deploy_only_once_err:4; - /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0; - * Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. - */ - uint32_t force_use_key_manager_key_err:4; - /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0; - * Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. - */ - uint32_t force_disable_sw_init_key_err:1; - /** xts_key_length_256_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of XTS_KEY_LENGTH_256. - */ - uint32_t xts_key_length_256_err:1; - uint32_t reserved_15:1; - /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. - */ - uint32_t wdt_delay_sel_err:2; - /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. - */ - uint32_t spi_boot_crypt_cnt_err:3; - /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. - */ - uint32_t secure_boot_key_revoke0_err:1; - /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. - */ - uint32_t secure_boot_key_revoke1_err:1; - /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. - */ - uint32_t secure_boot_key_revoke2_err:1; - /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. - */ - uint32_t key_purpose_0_err:4; - /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. - */ - uint32_t key_purpose_1_err:4; - }; - uint32_t val; -} efuse_rd_repeat_err1_reg_t; - -/** Type of rd_repeat_err2 register - * Programming error record register 2 of BLOCK0. - */ -typedef union { - struct { - /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. - */ - uint32_t key_purpose_2_err:4; - /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. - */ - uint32_t key_purpose_3_err:4; - /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. - */ - uint32_t key_purpose_4_err:4; - /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. - */ - uint32_t key_purpose_5_err:4; - /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. - */ - uint32_t sec_dpa_level_err:2; - /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0; - * Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. - */ - uint32_t ecdsa_enable_soft_k_err:1; - /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. - */ - uint32_t crypt_dpa_enable_err:1; - /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. - */ - uint32_t secure_boot_en_err:1; - /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. - */ - uint32_t secure_boot_aggressive_revoke_err:1; - uint32_t reserved_22:1; - /** flash_type_err : RO; bitpos: [23]; default: 0; - * Indicates a programming error of FLASH_TYPE. - */ - uint32_t flash_type_err:1; - /** flash_page_size_err : RO; bitpos: [25:24]; default: 0; - * Indicates a programming error of FLASH_PAGE_SIZE. - */ - uint32_t flash_page_size_err:2; - /** flash_ecc_en_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of FLASH_ECC_EN. - */ - uint32_t flash_ecc_en_err:1; - /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0; - * Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. - */ - uint32_t dis_usb_otg_download_mode_err:1; - /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. - */ - uint32_t flash_tpuw_err:4; - }; - uint32_t val; -} efuse_rd_repeat_err2_reg_t; - -/** Type of rd_repeat_err3 register - * Programming error record register 3 of BLOCK0. - */ -typedef union { - struct { - /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. - */ - uint32_t dis_download_mode_err:1; - /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. - */ - uint32_t dis_direct_boot_err:1; - /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. - */ - uint32_t dis_usb_serial_jtag_rom_print_err:1; - /** lock_km_key_err : RO; bitpos: [3]; default: 0; - * TBD - */ - uint32_t lock_km_key_err:1; - /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. - */ - uint32_t dis_usb_serial_jtag_download_mode_err:1; - /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. - */ - uint32_t enable_security_download_err:1; - /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. - */ - uint32_t uart_print_control_err:2; - /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. - */ - uint32_t force_send_resume_err:1; - /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. - */ - uint32_t secure_version_err:16; - /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. - */ - uint32_t secure_boot_disable_fast_wake_err:1; - /** hys_en_pad_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of HYS_EN_PAD. - */ - uint32_t hys_en_pad_err:1; - /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0; - * Indicates a programming error of DCDC_VSET. - */ - uint32_t dcdc_vset_err:5; - }; - uint32_t val; -} efuse_rd_repeat_err3_reg_t; - -/** Type of rd_repeat_err4 register - * Programming error record register 4 of BLOCK0. - */ -typedef union { - struct { - /** 0pxa_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_0. - */ - uint32_t rd_0pxa_tieh_sel_0_err:2; - /** 0pxa_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_1. - */ - uint32_t rd_0pxa_tieh_sel_1_err:2; - /** 0pxa_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_2. - */ - uint32_t rd_0pxa_tieh_sel_2_err:2; - /** 0pxa_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_3. - */ - uint32_t rd_0pxa_tieh_sel_3_err:2; - /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0; - * TBD. - */ - uint32_t km_disable_deploy_mode_err:4; - /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0; - * Indicates a programming error of USB_DEVICE_DREFL. - */ - uint32_t usb_device_drefl_err:2; - /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0; - * Indicates a programming error of USB_OTG11_DREFL. - */ - uint32_t usb_otg11_drefl_err:2; - uint32_t reserved_16:2; - /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0; - * Indicates a programming error of HP_PWR_SRC_SEL. - */ - uint32_t hp_pwr_src_sel_err:1; - /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DCDC_VSET_EN. - */ - uint32_t dcdc_vset_en_err:1; - /** dis_wdt_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_WDT. - */ - uint32_t dis_wdt_err:1; - /** dis_swd_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of DIS_SWD. - */ - uint32_t dis_swd_err:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} efuse_rd_repeat_err4_reg_t; - -/** Type of rd_rs_err0 register - * Programming error record register 0 of BLOCK1-10. - */ -typedef union { - struct { - /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t mac_sys_err_num:3; - /** mac_sys_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t mac_sys_fail:1; - /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t sys_part1_err_num:3; - /** sys_part1_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t sys_part1_fail:1; - /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t usr_data_err_num:3; - /** usr_data_fail : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ - uint32_t usr_data_fail:1; - /** key0_err_num : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key0_err_num:3; - /** key0_fail : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. - */ - uint32_t key0_fail:1; - /** key1_err_num : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key1_err_num:3; - /** key1_fail : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. - */ - uint32_t key1_fail:1; - /** key2_err_num : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key2_err_num:3; - /** key2_fail : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. - */ - uint32_t key2_fail:1; - /** key3_err_num : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key3_err_num:3; - /** key3_fail : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. - */ - uint32_t key3_fail:1; - /** key4_err_num : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key4_err_num:3; - /** key4_fail : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. - */ - uint32_t key4_fail:1; - }; - uint32_t val; -} efuse_rd_rs_err0_reg_t; - -/** Type of rd_rs_err1 register - * Programming error record register 1 of BLOCK1-10. - */ -typedef union { - struct { - /** key5_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key5_err_num:3; - /** key5_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. - */ - uint32_t key5_fail:1; - /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t sys_part2_err_num:3; - /** sys_part2_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t sys_part2_fail:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} efuse_rd_rs_err1_reg_t; - -/** Type of clk register - * eFuse clcok configuration register. - */ -typedef union { - struct { - /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ - uint32_t mem_force_pd:1; - /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ - uint32_t mem_clk_force_on:1; - /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ - uint32_t mem_force_pu:1; - uint32_t reserved_3:13; - /** clk_en : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. - */ - uint32_t clk_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} efuse_clk_reg_t; - -/** Type of conf register - * eFuse operation mode configuraiton register - */ -typedef union { - struct { - /** op_code : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. - */ - uint32_t op_code:16; - /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. - */ - uint32_t cfg_ecdsa_blk:4; - uint32_t reserved_20:12; - }; - uint32_t val; -} efuse_conf_reg_t; - -/** Type of status register - * eFuse status register. - */ -typedef union { - struct { - /** state : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - uint32_t state:4; - uint32_t reserved_4:6; - /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. - */ - uint32_t blk0_valid_bit_cnt:10; - /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. - */ - uint32_t cur_ecdsa_blk:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_status_reg_t; - -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - -/** Type of int_raw register - * eFuse raw interrupt register. - */ -typedef union { - struct { - /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - uint32_t read_done_int_raw:1; - /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_raw_reg_t; - -/** Type of int_st register - * eFuse interrupt status register. - */ -typedef union { - struct { - /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - uint32_t read_done_int_st:1; - /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_st_reg_t; - -/** Type of int_ena register - * eFuse interrupt enable register. - */ -typedef union { - struct { - /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - uint32_t read_done_int_ena:1; - /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_ena_reg_t; - -/** Type of int_clr register - * eFuse interrupt clear register. - */ -typedef union { - struct { - /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - uint32_t read_done_int_clr:1; - /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_clr_reg_t; - -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 15; - * Configures the waiting time of reading eFuse memory. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - - -/** Group: EFUSE Version Register */ -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 36720720; - * Stores eFuse version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Write Disable Data */ -/** Type of apb2otp_wr_dis register - * eFuse apb2otp block0 data register1. - */ -typedef union { - struct { - /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ - uint32_t apb2otp_block0_wr_dis:32; - }; - uint32_t val; -} efuse_apb2otp_wr_dis_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */ -/** Type of apb2otp_blk0_backup1_w1 register - * eFuse apb2otp block0 data register2. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ - uint32_t apb2otp_block0_backup1_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */ -/** Type of apb2otp_blk0_backup1_w2 register - * eFuse apb2otp block0 data register3. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ - uint32_t apb2otp_block0_backup1_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */ -/** Type of apb2otp_blk0_backup1_w3 register - * eFuse apb2otp block0 data register4. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ - uint32_t apb2otp_block0_backup1_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */ -/** Type of apb2otp_blk0_backup1_w4 register - * eFuse apb2otp block0 data register5. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ - uint32_t apb2otp_block0_backup1_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */ -/** Type of apb2otp_blk0_backup1_w5 register - * eFuse apb2otp block0 data register6. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ - uint32_t apb2otp_block0_backup1_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */ -/** Type of apb2otp_blk0_backup2_w1 register - * eFuse apb2otp block0 data register7. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ - uint32_t apb2otp_block0_backup2_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */ -/** Type of apb2otp_blk0_backup2_w2 register - * eFuse apb2otp block0 data register8. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ - uint32_t apb2otp_block0_backup2_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */ -/** Type of apb2otp_blk0_backup2_w3 register - * eFuse apb2otp block0 data register9. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ - uint32_t apb2otp_block0_backup2_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */ -/** Type of apb2otp_blk0_backup2_w4 register - * eFuse apb2otp block0 data register10. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ - uint32_t apb2otp_block0_backup2_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */ -/** Type of apb2otp_blk0_backup2_w5 register - * eFuse apb2otp block0 data register11. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ - uint32_t apb2otp_block0_backup2_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */ -/** Type of apb2otp_blk0_backup3_w1 register - * eFuse apb2otp block0 data register12. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ - uint32_t apb2otp_block0_backup3_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */ -/** Type of apb2otp_blk0_backup3_w2 register - * eFuse apb2otp block0 data register13. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ - uint32_t apb2otp_block0_backup3_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */ -/** Type of apb2otp_blk0_backup3_w3 register - * eFuse apb2otp block0 data register14. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ - uint32_t apb2otp_block0_backup3_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */ -/** Type of apb2otp_blk0_backup3_w4 register - * eFuse apb2otp block0 data register15. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ - uint32_t apb2otp_block0_backup3_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */ -/** Type of apb2otp_blk0_backup3_w5 register - * eFuse apb2otp block0 data register16. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ - uint32_t apb2otp_block0_backup3_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */ -/** Type of apb2otp_blk0_backup4_w1 register - * eFuse apb2otp block0 data register17. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ - uint32_t apb2otp_block0_backup4_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */ -/** Type of apb2otp_blk0_backup4_w2 register - * eFuse apb2otp block0 data register18. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ - uint32_t apb2otp_block0_backup4_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */ -/** Type of apb2otp_blk0_backup4_w3 register - * eFuse apb2otp block0 data register19. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ - uint32_t apb2otp_block0_backup4_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */ -/** Type of apb2otp_blk0_backup4_w4 register - * eFuse apb2otp block0 data register20. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ - uint32_t apb2otp_block0_backup4_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */ -/** Type of apb2otp_blk0_backup4_w5 register - * eFuse apb2otp block0 data register21. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ - uint32_t apb2otp_block0_backup4_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word1 Data */ -/** Type of apb2otp_blk1_w1 register - * eFuse apb2otp block1 data register1. - */ -typedef union { - struct { - /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ - uint32_t apb2otp_block1_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word2 Data */ -/** Type of apb2otp_blk1_w2 register - * eFuse apb2otp block1 data register2. - */ -typedef union { - struct { - /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ - uint32_t apb2otp_block1_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word3 Data */ -/** Type of apb2otp_blk1_w3 register - * eFuse apb2otp block1 data register3. - */ -typedef union { - struct { - /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ - uint32_t apb2otp_block1_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word4 Data */ -/** Type of apb2otp_blk1_w4 register - * eFuse apb2otp block1 data register4. - */ -typedef union { - struct { - /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ - uint32_t apb2otp_block1_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word5 Data */ -/** Type of apb2otp_blk1_w5 register - * eFuse apb2otp block1 data register5. - */ -typedef union { - struct { - /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ - uint32_t apb2otp_block1_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word6 Data */ -/** Type of apb2otp_blk1_w6 register - * eFuse apb2otp block1 data register6. - */ -typedef union { - struct { - /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ - uint32_t apb2otp_block1_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word7 Data */ -/** Type of apb2otp_blk1_w7 register - * eFuse apb2otp block1 data register7. - */ -typedef union { - struct { - /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ - uint32_t apb2otp_block1_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word8 Data */ -/** Type of apb2otp_blk1_w8 register - * eFuse apb2otp block1 data register8. - */ -typedef union { - struct { - /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ - uint32_t apb2otp_block1_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word9 Data */ -/** Type of apb2otp_blk1_w9 register - * eFuse apb2otp block1 data register9. - */ -typedef union { - struct { - /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ - uint32_t apb2otp_block1_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word1 Data */ -/** Type of apb2otp_blk2_w1 register - * eFuse apb2otp block2 data register1. - */ -typedef union { - struct { - /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ - uint32_t apb2otp_block2_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word2 Data */ -/** Type of apb2otp_blk2_w2 register - * eFuse apb2otp block2 data register2. - */ -typedef union { - struct { - /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ - uint32_t apb2otp_block2_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word3 Data */ -/** Type of apb2otp_blk2_w3 register - * eFuse apb2otp block2 data register3. - */ -typedef union { - struct { - /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ - uint32_t apb2otp_block2_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word4 Data */ -/** Type of apb2otp_blk2_w4 register - * eFuse apb2otp block2 data register4. - */ -typedef union { - struct { - /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ - uint32_t apb2otp_block2_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word5 Data */ -/** Type of apb2otp_blk2_w5 register - * eFuse apb2otp block2 data register5. - */ -typedef union { - struct { - /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ - uint32_t apb2otp_block2_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word6 Data */ -/** Type of apb2otp_blk2_w6 register - * eFuse apb2otp block2 data register6. - */ -typedef union { - struct { - /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ - uint32_t apb2otp_block2_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word7 Data */ -/** Type of apb2otp_blk2_w7 register - * eFuse apb2otp block2 data register7. - */ -typedef union { - struct { - /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ - uint32_t apb2otp_block2_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word8 Data */ -/** Type of apb2otp_blk2_w8 register - * eFuse apb2otp block2 data register8. - */ -typedef union { - struct { - /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ - uint32_t apb2otp_block2_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word9 Data */ -/** Type of apb2otp_blk2_w9 register - * eFuse apb2otp block2 data register9. - */ -typedef union { - struct { - /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ - uint32_t apb2otp_block2_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word10 Data */ -/** Type of apb2otp_blk2_w10 register - * eFuse apb2otp block2 data register10. - */ -typedef union { - struct { - /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ - uint32_t apb2otp_block2_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word11 Data */ -/** Type of apb2otp_blk2_w11 register - * eFuse apb2otp block2 data register11. - */ -typedef union { - struct { - /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ - uint32_t apb2otp_block2_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w11_reg_t; - -/** Type of apb2otp_blk10_w11 register - * eFuse apb2otp block10 data register11. - */ -typedef union { - struct { - /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t apb2otp_block10_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word1 Data */ -/** Type of apb2otp_blk3_w1 register - * eFuse apb2otp block3 data register1. - */ -typedef union { - struct { - /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ - uint32_t apb2otp_block3_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word2 Data */ -/** Type of apb2otp_blk3_w2 register - * eFuse apb2otp block3 data register2. - */ -typedef union { - struct { - /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ - uint32_t apb2otp_block3_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word3 Data */ -/** Type of apb2otp_blk3_w3 register - * eFuse apb2otp block3 data register3. - */ -typedef union { - struct { - /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ - uint32_t apb2otp_block3_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word4 Data */ -/** Type of apb2otp_blk3_w4 register - * eFuse apb2otp block3 data register4. - */ -typedef union { - struct { - /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ - uint32_t apb2otp_block3_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word5 Data */ -/** Type of apb2otp_blk3_w5 register - * eFuse apb2otp block3 data register5. - */ -typedef union { - struct { - /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ - uint32_t apb2otp_block3_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word6 Data */ -/** Type of apb2otp_blk3_w6 register - * eFuse apb2otp block3 data register6. - */ -typedef union { - struct { - /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ - uint32_t apb2otp_block3_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word7 Data */ -/** Type of apb2otp_blk3_w7 register - * eFuse apb2otp block3 data register7. - */ -typedef union { - struct { - /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ - uint32_t apb2otp_block3_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word8 Data */ -/** Type of apb2otp_blk3_w8 register - * eFuse apb2otp block3 data register8. - */ -typedef union { - struct { - /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ - uint32_t apb2otp_block3_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word9 Data */ -/** Type of apb2otp_blk3_w9 register - * eFuse apb2otp block3 data register9. - */ -typedef union { - struct { - /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ - uint32_t apb2otp_block3_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word10 Data */ -/** Type of apb2otp_blk3_w10 register - * eFuse apb2otp block3 data register10. - */ -typedef union { - struct { - /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ - uint32_t apb2otp_block3_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word11 Data */ -/** Type of apb2otp_blk3_w11 register - * eFuse apb2otp block3 data register11. - */ -typedef union { - struct { - /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ - uint32_t apb2otp_block3_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word1 Data */ -/** Type of apb2otp_blk4_w1 register - * eFuse apb2otp block4 data register1. - */ -typedef union { - struct { - /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ - uint32_t apb2otp_block4_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word2 Data */ -/** Type of apb2otp_blk4_w2 register - * eFuse apb2otp block4 data register2. - */ -typedef union { - struct { - /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ - uint32_t apb2otp_block4_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word3 Data */ -/** Type of apb2otp_blk4_w3 register - * eFuse apb2otp block4 data register3. - */ -typedef union { - struct { - /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ - uint32_t apb2otp_block4_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word4 Data */ -/** Type of apb2otp_blk4_w4 register - * eFuse apb2otp block4 data register4. - */ -typedef union { - struct { - /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ - uint32_t apb2otp_block4_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word5 Data */ -/** Type of apb2otp_blk4_w5 register - * eFuse apb2otp block4 data register5. - */ -typedef union { - struct { - /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ - uint32_t apb2otp_block4_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word6 Data */ -/** Type of apb2otp_blk4_w6 register - * eFuse apb2otp block4 data register6. - */ -typedef union { - struct { - /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ - uint32_t apb2otp_block4_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word7 Data */ -/** Type of apb2otp_blk4_w7 register - * eFuse apb2otp block4 data register7. - */ -typedef union { - struct { - /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ - uint32_t apb2otp_block4_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word8 Data */ -/** Type of apb2otp_blk4_w8 register - * eFuse apb2otp block4 data register8. - */ -typedef union { - struct { - /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ - uint32_t apb2otp_block4_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word9 Data */ -/** Type of apb2otp_blk4_w9 register - * eFuse apb2otp block4 data register9. - */ -typedef union { - struct { - /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ - uint32_t apb2otp_block4_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word10 Data */ -/** Type of apb2otp_blk4_w10 register - * eFuse apb2otp block4 data registe10. - */ -typedef union { - struct { - /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ - uint32_t apb2otp_block4_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word11 Data */ -/** Type of apb2otp_blk4_w11 register - * eFuse apb2otp block4 data register11. - */ -typedef union { - struct { - /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ - uint32_t apb2otp_block4_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word1 Data */ -/** Type of apb2otp_blk5_w1 register - * eFuse apb2otp block5 data register1. - */ -typedef union { - struct { - /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ - uint32_t apb2otp_block5_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word2 Data */ -/** Type of apb2otp_blk5_w2 register - * eFuse apb2otp block5 data register2. - */ -typedef union { - struct { - /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ - uint32_t apb2otp_block5_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word3 Data */ -/** Type of apb2otp_blk5_w3 register - * eFuse apb2otp block5 data register3. - */ -typedef union { - struct { - /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ - uint32_t apb2otp_block5_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word4 Data */ -/** Type of apb2otp_blk5_w4 register - * eFuse apb2otp block5 data register4. - */ -typedef union { - struct { - /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ - uint32_t apb2otp_block5_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word5 Data */ -/** Type of apb2otp_blk5_w5 register - * eFuse apb2otp block5 data register5. - */ -typedef union { - struct { - /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ - uint32_t apb2otp_block5_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word6 Data */ -/** Type of apb2otp_blk5_w6 register - * eFuse apb2otp block5 data register6. - */ -typedef union { - struct { - /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ - uint32_t apb2otp_block5_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word7 Data */ -/** Type of apb2otp_blk5_w7 register - * eFuse apb2otp block5 data register7. - */ -typedef union { - struct { - /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ - uint32_t apb2otp_block5_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word8 Data */ -/** Type of apb2otp_blk5_w8 register - * eFuse apb2otp block5 data register8. - */ -typedef union { - struct { - /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ - uint32_t apb2otp_block5_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word9 Data */ -/** Type of apb2otp_blk5_w9 register - * eFuse apb2otp block5 data register9. - */ -typedef union { - struct { - /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ - uint32_t apb2otp_block5_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word10 Data */ -/** Type of apb2otp_blk5_w10 register - * eFuse apb2otp block5 data register10. - */ -typedef union { - struct { - /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ - uint32_t apb2otp_block5_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word11 Data */ -/** Type of apb2otp_blk5_w11 register - * eFuse apb2otp block5 data register11. - */ -typedef union { - struct { - /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ - uint32_t apb2otp_block5_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word1 Data */ -/** Type of apb2otp_blk6_w1 register - * eFuse apb2otp block6 data register1. - */ -typedef union { - struct { - /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ - uint32_t apb2otp_block6_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word2 Data */ -/** Type of apb2otp_blk6_w2 register - * eFuse apb2otp block6 data register2. - */ -typedef union { - struct { - /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ - uint32_t apb2otp_block6_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word3 Data */ -/** Type of apb2otp_blk6_w3 register - * eFuse apb2otp block6 data register3. - */ -typedef union { - struct { - /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ - uint32_t apb2otp_block6_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word4 Data */ -/** Type of apb2otp_blk6_w4 register - * eFuse apb2otp block6 data register4. - */ -typedef union { - struct { - /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ - uint32_t apb2otp_block6_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word5 Data */ -/** Type of apb2otp_blk6_w5 register - * eFuse apb2otp block6 data register5. - */ -typedef union { - struct { - /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ - uint32_t apb2otp_block6_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word6 Data */ -/** Type of apb2otp_blk6_w6 register - * eFuse apb2otp block6 data register6. - */ -typedef union { - struct { - /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ - uint32_t apb2otp_block6_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word7 Data */ -/** Type of apb2otp_blk6_w7 register - * eFuse apb2otp block6 data register7. - */ -typedef union { - struct { - /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ - uint32_t apb2otp_block6_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word8 Data */ -/** Type of apb2otp_blk6_w8 register - * eFuse apb2otp block6 data register8. - */ -typedef union { - struct { - /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ - uint32_t apb2otp_block6_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word9 Data */ -/** Type of apb2otp_blk6_w9 register - * eFuse apb2otp block6 data register9. - */ -typedef union { - struct { - /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ - uint32_t apb2otp_block6_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word10 Data */ -/** Type of apb2otp_blk6_w10 register - * eFuse apb2otp block6 data register10. - */ -typedef union { - struct { - /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ - uint32_t apb2otp_block6_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word11 Data */ -/** Type of apb2otp_blk6_w11 register - * eFuse apb2otp block6 data register11. - */ -typedef union { - struct { - /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ - uint32_t apb2otp_block6_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word1 Data */ -/** Type of apb2otp_blk7_w1 register - * eFuse apb2otp block7 data register1. - */ -typedef union { - struct { - /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ - uint32_t apb2otp_block7_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word2 Data */ -/** Type of apb2otp_blk7_w2 register - * eFuse apb2otp block7 data register2. - */ -typedef union { - struct { - /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ - uint32_t apb2otp_block7_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word3 Data */ -/** Type of apb2otp_blk7_w3 register - * eFuse apb2otp block7 data register3. - */ -typedef union { - struct { - /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ - uint32_t apb2otp_block7_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word4 Data */ -/** Type of apb2otp_blk7_w4 register - * eFuse apb2otp block7 data register4. - */ -typedef union { - struct { - /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ - uint32_t apb2otp_block7_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word5 Data */ -/** Type of apb2otp_blk7_w5 register - * eFuse apb2otp block7 data register5. - */ -typedef union { - struct { - /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ - uint32_t apb2otp_block7_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word6 Data */ -/** Type of apb2otp_blk7_w6 register - * eFuse apb2otp block7 data register6. - */ -typedef union { - struct { - /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ - uint32_t apb2otp_block7_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word7 Data */ -/** Type of apb2otp_blk7_w7 register - * eFuse apb2otp block7 data register7. - */ -typedef union { - struct { - /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ - uint32_t apb2otp_block7_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word8 Data */ -/** Type of apb2otp_blk7_w8 register - * eFuse apb2otp block7 data register8. - */ -typedef union { - struct { - /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ - uint32_t apb2otp_block7_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word9 Data */ -/** Type of apb2otp_blk7_w9 register - * eFuse apb2otp block7 data register9. - */ -typedef union { - struct { - /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ - uint32_t apb2otp_block7_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word10 Data */ -/** Type of apb2otp_blk7_w10 register - * eFuse apb2otp block7 data register10. - */ -typedef union { - struct { - /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ - uint32_t apb2otp_block7_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word11 Data */ -/** Type of apb2otp_blk7_w11 register - * eFuse apb2otp block7 data register11. - */ -typedef union { - struct { - /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ - uint32_t apb2otp_block7_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word1 Data */ -/** Type of apb2otp_blk8_w1 register - * eFuse apb2otp block8 data register1. - */ -typedef union { - struct { - /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ - uint32_t apb2otp_block8_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word2 Data */ -/** Type of apb2otp_blk8_w2 register - * eFuse apb2otp block8 data register2. - */ -typedef union { - struct { - /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ - uint32_t apb2otp_block8_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word3 Data */ -/** Type of apb2otp_blk8_w3 register - * eFuse apb2otp block8 data register3. - */ -typedef union { - struct { - /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ - uint32_t apb2otp_block8_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word4 Data */ -/** Type of apb2otp_blk8_w4 register - * eFuse apb2otp block8 data register4. - */ -typedef union { - struct { - /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ - uint32_t apb2otp_block8_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word5 Data */ -/** Type of apb2otp_blk8_w5 register - * eFuse apb2otp block8 data register5. - */ -typedef union { - struct { - /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ - uint32_t apb2otp_block8_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word6 Data */ -/** Type of apb2otp_blk8_w6 register - * eFuse apb2otp block8 data register6. - */ -typedef union { - struct { - /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ - uint32_t apb2otp_block8_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word7 Data */ -/** Type of apb2otp_blk8_w7 register - * eFuse apb2otp block8 data register7. - */ -typedef union { - struct { - /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ - uint32_t apb2otp_block8_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word8 Data */ -/** Type of apb2otp_blk8_w8 register - * eFuse apb2otp block8 data register8. - */ -typedef union { - struct { - /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ - uint32_t apb2otp_block8_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word9 Data */ -/** Type of apb2otp_blk8_w9 register - * eFuse apb2otp block8 data register9. - */ -typedef union { - struct { - /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ - uint32_t apb2otp_block8_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word10 Data */ -/** Type of apb2otp_blk8_w10 register - * eFuse apb2otp block8 data register10. - */ -typedef union { - struct { - /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ - uint32_t apb2otp_block8_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word11 Data */ -/** Type of apb2otp_blk8_w11 register - * eFuse apb2otp block8 data register11. - */ -typedef union { - struct { - /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ - uint32_t apb2otp_block8_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word1 Data */ -/** Type of apb2otp_blk9_w1 register - * eFuse apb2otp block9 data register1. - */ -typedef union { - struct { - /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ - uint32_t apb2otp_block9_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word2 Data */ -/** Type of apb2otp_blk9_w2 register - * eFuse apb2otp block9 data register2. - */ -typedef union { - struct { - /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ - uint32_t apb2otp_block9_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word3 Data */ -/** Type of apb2otp_blk9_w3 register - * eFuse apb2otp block9 data register3. - */ -typedef union { - struct { - /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ - uint32_t apb2otp_block9_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word4 Data */ -/** Type of apb2otp_blk9_w4 register - * eFuse apb2otp block9 data register4. - */ -typedef union { - struct { - /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ - uint32_t apb2otp_block9_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word5 Data */ -/** Type of apb2otp_blk9_w5 register - * eFuse apb2otp block9 data register5. - */ -typedef union { - struct { - /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ - uint32_t apb2otp_block9_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word6 Data */ -/** Type of apb2otp_blk9_w6 register - * eFuse apb2otp block9 data register6. - */ -typedef union { - struct { - /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ - uint32_t apb2otp_block9_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word7 Data */ -/** Type of apb2otp_blk9_w7 register - * eFuse apb2otp block9 data register7. - */ -typedef union { - struct { - /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ - uint32_t apb2otp_block9_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word8 Data */ -/** Type of apb2otp_blk9_w8 register - * eFuse apb2otp block9 data register8. - */ -typedef union { - struct { - /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ - uint32_t apb2otp_block9_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word9 Data */ -/** Type of apb2otp_blk9_w9 register - * eFuse apb2otp block9 data register9. - */ -typedef union { - struct { - /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ - uint32_t apb2otp_block9_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word10 Data */ -/** Type of apb2otp_blk9_w10 register - * eFuse apb2otp block9 data register10. - */ -typedef union { - struct { - /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ - uint32_t apb2otp_block9_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word11 Data */ -/** Type of apb2otp_blk9_w11 register - * eFuse apb2otp block9 data register11. - */ -typedef union { - struct { - /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ - uint32_t apb2otp_block9_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word1 Data */ -/** Type of apb2otp_blk10_w1 register - * eFuse apb2otp block10 data register1. - */ -typedef union { - struct { - /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ - uint32_t apb2otp_block10_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word2 Data */ -/** Type of apb2otp_blk10_w2 register - * eFuse apb2otp block10 data register2. - */ -typedef union { - struct { - /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ - uint32_t apb2otp_block10_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word3 Data */ -/** Type of apb2otp_blk10_w3 register - * eFuse apb2otp block10 data register3. - */ -typedef union { - struct { - /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ - uint32_t apb2otp_block10_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word4 Data */ -/** Type of apb2otp_blk10_w4 register - * eFuse apb2otp block10 data register4. - */ -typedef union { - struct { - /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ - uint32_t apb2otp_block10_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word5 Data */ -/** Type of apb2otp_blk10_w5 register - * eFuse apb2otp block10 data register5. - */ -typedef union { - struct { - /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ - uint32_t apb2otp_block10_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word6 Data */ -/** Type of apb2otp_blk10_w6 register - * eFuse apb2otp block10 data register6. - */ -typedef union { - struct { - /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ - uint32_t apb2otp_block10_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word7 Data */ -/** Type of apb2otp_blk10_w7 register - * eFuse apb2otp block10 data register7. - */ -typedef union { - struct { - /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ - uint32_t apb2otp_block10_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word8 Data */ -/** Type of apb2otp_blk10_w8 register - * eFuse apb2otp block10 data register8. - */ -typedef union { - struct { - /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ - uint32_t apb2otp_block10_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word9 Data */ -/** Type of apb2otp_blk10_w9 register - * eFuse apb2otp block10 data register9. - */ -typedef union { - struct { - /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ - uint32_t apb2otp_block10_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word10 Data */ -/** Type of apb2otp_blk10_w10 register - * eFuse apb2otp block10 data register10. - */ -typedef union { - struct { - /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ - uint32_t apb2otp_block19_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Function Enable Singal */ -/** Type of apb2otp_en register - * eFuse apb2otp enable configuration register. - */ -typedef union { - struct { - /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0; - * Apb2otp mode enable signal. - */ - uint32_t apb2otp_apb2otp_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} efuse_apb2otp_en_reg_t; - - -typedef struct { - volatile efuse_pgm_data0_reg_t pgm_data0; - volatile efuse_pgm_data1_reg_t pgm_data1; - volatile efuse_pgm_data2_reg_t pgm_data2; - volatile efuse_pgm_data3_reg_t pgm_data3; - volatile efuse_pgm_data4_reg_t pgm_data4; - volatile efuse_pgm_data5_reg_t pgm_data5; - volatile efuse_pgm_data6_reg_t pgm_data6; - volatile efuse_pgm_data7_reg_t pgm_data7; - volatile efuse_pgm_check_value0_reg_t pgm_check_value0; - volatile efuse_pgm_check_value1_reg_t pgm_check_value1; - volatile efuse_pgm_check_value2_reg_t pgm_check_value2; - volatile efuse_rd_wr_dis_reg_t rd_wr_dis; - volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; - volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; - volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; - volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; - volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; - volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; - volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; - volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; - volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; - volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; - volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; - volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; - volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; - volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; - volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; - volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; - volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; - volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; - volatile efuse_rd_usr_data0_reg_t rd_usr_data0; - volatile efuse_rd_usr_data1_reg_t rd_usr_data1; - volatile efuse_rd_usr_data2_reg_t rd_usr_data2; - volatile efuse_rd_usr_data3_reg_t rd_usr_data3; - volatile efuse_rd_usr_data4_reg_t rd_usr_data4; - volatile efuse_rd_usr_data5_reg_t rd_usr_data5; - volatile efuse_rd_usr_data6_reg_t rd_usr_data6; - volatile efuse_rd_usr_data7_reg_t rd_usr_data7; - volatile efuse_rd_key0_data0_reg_t rd_key0_data0; - volatile efuse_rd_key0_data1_reg_t rd_key0_data1; - volatile efuse_rd_key0_data2_reg_t rd_key0_data2; - volatile efuse_rd_key0_data3_reg_t rd_key0_data3; - volatile efuse_rd_key0_data4_reg_t rd_key0_data4; - volatile efuse_rd_key0_data5_reg_t rd_key0_data5; - volatile efuse_rd_key0_data6_reg_t rd_key0_data6; - volatile efuse_rd_key0_data7_reg_t rd_key0_data7; - volatile efuse_rd_key1_data0_reg_t rd_key1_data0; - volatile efuse_rd_key1_data1_reg_t rd_key1_data1; - volatile efuse_rd_key1_data2_reg_t rd_key1_data2; - volatile efuse_rd_key1_data3_reg_t rd_key1_data3; - volatile efuse_rd_key1_data4_reg_t rd_key1_data4; - volatile efuse_rd_key1_data5_reg_t rd_key1_data5; - volatile efuse_rd_key1_data6_reg_t rd_key1_data6; - volatile efuse_rd_key1_data7_reg_t rd_key1_data7; - volatile efuse_rd_key2_data0_reg_t rd_key2_data0; - volatile efuse_rd_key2_data1_reg_t rd_key2_data1; - volatile efuse_rd_key2_data2_reg_t rd_key2_data2; - volatile efuse_rd_key2_data3_reg_t rd_key2_data3; - volatile efuse_rd_key2_data4_reg_t rd_key2_data4; - volatile efuse_rd_key2_data5_reg_t rd_key2_data5; - volatile efuse_rd_key2_data6_reg_t rd_key2_data6; - volatile efuse_rd_key2_data7_reg_t rd_key2_data7; - volatile efuse_rd_key3_data0_reg_t rd_key3_data0; - volatile efuse_rd_key3_data1_reg_t rd_key3_data1; - volatile efuse_rd_key3_data2_reg_t rd_key3_data2; - volatile efuse_rd_key3_data3_reg_t rd_key3_data3; - volatile efuse_rd_key3_data4_reg_t rd_key3_data4; - volatile efuse_rd_key3_data5_reg_t rd_key3_data5; - volatile efuse_rd_key3_data6_reg_t rd_key3_data6; - volatile efuse_rd_key3_data7_reg_t rd_key3_data7; - volatile efuse_rd_key4_data0_reg_t rd_key4_data0; - volatile efuse_rd_key4_data1_reg_t rd_key4_data1; - volatile efuse_rd_key4_data2_reg_t rd_key4_data2; - volatile efuse_rd_key4_data3_reg_t rd_key4_data3; - volatile efuse_rd_key4_data4_reg_t rd_key4_data4; - volatile efuse_rd_key4_data5_reg_t rd_key4_data5; - volatile efuse_rd_key4_data6_reg_t rd_key4_data6; - volatile efuse_rd_key4_data7_reg_t rd_key4_data7; - volatile efuse_rd_key5_data0_reg_t rd_key5_data0; - volatile efuse_rd_key5_data1_reg_t rd_key5_data1; - volatile efuse_rd_key5_data2_reg_t rd_key5_data2; - volatile efuse_rd_key5_data3_reg_t rd_key5_data3; - volatile efuse_rd_key5_data4_reg_t rd_key5_data4; - volatile efuse_rd_key5_data5_reg_t rd_key5_data5; - volatile efuse_rd_key5_data6_reg_t rd_key5_data6; - volatile efuse_rd_key5_data7_reg_t rd_key5_data7; - volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; - volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; - volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; - volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; - volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; - volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; - volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; - volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; - volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; - volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; - volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; - volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; - uint32_t reserved_190[12]; - volatile efuse_rd_rs_err0_reg_t rd_rs_err0; - volatile efuse_rd_rs_err1_reg_t rd_rs_err1; - volatile efuse_clk_reg_t clk; - volatile efuse_conf_reg_t conf; - volatile efuse_status_reg_t status; - volatile efuse_cmd_reg_t cmd; - volatile efuse_int_raw_reg_t int_raw; - volatile efuse_int_st_reg_t int_st; - volatile efuse_int_ena_reg_t int_ena; - volatile efuse_int_clr_reg_t int_clr; - volatile efuse_dac_conf_reg_t dac_conf; - volatile efuse_rd_tim_conf_reg_t rd_tim_conf; - volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; - volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; - volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; - volatile efuse_date_reg_t date; - uint32_t reserved_200[384]; - volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; - volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; - volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; - volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3; - volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4; - volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5; - volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1; - volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2; - volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3; - volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4; - volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5; - volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1; - volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2; - volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3; - volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4; - volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5; - volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1; - volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2; - volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3; - volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4; - volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5; - volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1; - volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2; - volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3; - volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4; - volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5; - volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6; - volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7; - volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8; - volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9; - volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1; - volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2; - volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3; - volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4; - volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5; - volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6; - volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7; - volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8; - volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9; - volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10; - volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11; - volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1; - volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2; - volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3; - volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4; - volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5; - volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6; - volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7; - volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8; - volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9; - volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10; - volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11; - volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1; - volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2; - volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3; - volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4; - volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5; - volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6; - volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7; - volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8; - volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9; - volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10; - volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11; - volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1; - volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2; - volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3; - volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4; - volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5; - volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6; - volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7; - volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8; - volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9; - volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10; - volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11; - volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1; - volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2; - volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3; - volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4; - volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5; - volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6; - volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7; - volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8; - volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9; - volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10; - volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11; - volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1; - volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2; - volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3; - volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4; - volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5; - volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6; - volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7; - volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8; - volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9; - volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10; - volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11; - volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1; - volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2; - volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3; - volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4; - volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5; - volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6; - volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7; - volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8; - volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9; - volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10; - volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11; - volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1; - volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2; - volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3; - volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4; - volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5; - volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6; - volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7; - volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8; - volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9; - volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10; - volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11; - volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1; - volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2; - volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3; - volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4; - volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5; - volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6; - volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7; - volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8; - volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9; - volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10; - volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; - uint32_t reserved_a04; - volatile efuse_apb2otp_en_reg_t apb2otp_en; -} efuse_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h index faed73b495..f095267388 100644 --- a/components/soc/esp32p4/include/soc/efuse_reg.h +++ b/components/soc/esp32p4/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,3079 +10,4133 @@ #ifdef __cplusplus extern "C" { #endif + #define EFUSE_READ_OP_CODE 0x5aa5 #define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 0th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_M ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S)) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF + +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 1st 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_M ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S)) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 2nd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_M ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S)) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC) -/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 3rd 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_3 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_M ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S)) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 4th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_4 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_M ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S)) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_4_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 5th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_5 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_M ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S)) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_5_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 6th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 7th 32-bit data to be programmed..*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 0th 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 1st 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Configures the 2nd 32-bit RS code to be programmed..*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2C) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Represents whether programming of individual eFuse memory bit is disabled or ena -bled. 1: Disabled. 0 Enabled..*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/* EFUSE_KM_HUK_GEN_STATE_LOW : RO ;bitpos:[31:26] ;default: 6'h0 ; */ -/*description: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, ev -en of 1 is valid..*/ -#define EFUSE_KM_HUK_GEN_STATE_LOW 0x0000003F -#define EFUSE_KM_HUK_GEN_STATE_LOW_M ((EFUSE_KM_HUK_GEN_STATE_LOW_V)<<(EFUSE_KM_HUK_GEN_STATE_LOW_S)) -#define EFUSE_KM_HUK_GEN_STATE_LOW_V 0x3F -#define EFUSE_KM_HUK_GEN_STATE_LOW_S 26 -/* EFUSE_USB_PHY_SEL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: TBD.*/ -#define EFUSE_USB_PHY_SEL (BIT(25)) -#define EFUSE_USB_PHY_SEL_M (BIT(25)) -#define EFUSE_USB_PHY_SEL_V 0x1 -#define EFUSE_USB_PHY_SEL_S 25 -/* EFUSE_USB_OTG11_DREFH : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80 -mV.*/ -#define EFUSE_USB_OTG11_DREFH 0x00000003 -#define EFUSE_USB_OTG11_DREFH_M ((EFUSE_USB_OTG11_DREFH_V)<<(EFUSE_USB_OTG11_DREFH_S)) -#define EFUSE_USB_OTG11_DREFH_V 0x3 -#define EFUSE_USB_OTG11_DREFH_S 23 -/* EFUSE_USB_DEVICE_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 8 -0mV.*/ -#define EFUSE_USB_DEVICE_DREFH 0x00000003 -#define EFUSE_USB_DEVICE_DREFH_M ((EFUSE_USB_DEVICE_DREFH_V)<<(EFUSE_USB_DEVICE_DREFH_S)) -#define EFUSE_USB_DEVICE_DREFH_V 0x3 -#define EFUSE_USB_DEVICE_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Represents whether flash encrypt function is disabled or enabled(except in SPI b -oot mode). 1: disabled. 0: enabled..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0 -: enabled..*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Represents whether JTAG is disabled in soft way. Odd number: disabled. Even numb -er: enabled..*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Represents whether the selection between usb_to_jtag and pad_to_jtag through str -apping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - is enabled or disabled. 1: enabled. 0: disabled..*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -..*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during b -oot_mode_download..*/ -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x1 -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Represents whether the function that forces chip into download mode is disabled -or enabled. 1: disabled. 0: enabled..*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_SERIAL_JTAG : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabl -ed..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_M (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 -/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Represents whether power glitch function is enabled. 1: enabled. 0: disabled..*/ -#define EFUSE_POWERGLITCH_EN (BIT(10)) -#define EFUSE_POWERGLITCH_EN_M (BIT(10)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 10 -/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Represents whether the function of usb switch to jtag is disabled or enabled. 1: - disabled. 0: enabled..*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_USB_OTG11_EXCHG_PINS : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Enable usb otg11 exchange pins of D+ and D-..*/ -#define EFUSE_USB_OTG11_EXCHG_PINS (BIT(8)) -#define EFUSE_USB_OTG11_EXCHG_PINS_M (BIT(8)) -#define EFUSE_USB_OTG11_EXCHG_PINS_V 0x1 -#define EFUSE_USB_OTG11_EXCHG_PINS_S 8 -/* EFUSE_USB_DEVICE_EXCHG_PINS : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Enable usb device exchange pins of D+ and D-..*/ -#define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(7)) -#define EFUSE_USB_DEVICE_EXCHG_PINS_M (BIT(7)) -#define EFUSE_USB_DEVICE_EXCHG_PINS_V 0x1 -#define EFUSE_USB_DEVICE_EXCHG_PINS_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Represents whether reading of individual eFuse block(block4~block10) is disabled - or enabled. 1: disabled. 0: enabled..*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0; + * Enable usb device exchange pins of D+ and D-. + */ +#define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(7)) +#define EFUSE_USB_DEVICE_EXCHG_PINS_M (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S) +#define EFUSE_USB_DEVICE_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_DEVICE_EXCHG_PINS_S 7 +/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0; + * Enable usb otg11 exchange pins of D+ and D-. + */ +#define EFUSE_USB_OTG11_EXCHG_PINS (BIT(8)) +#define EFUSE_USB_OTG11_EXCHG_PINS_M (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S) +#define EFUSE_USB_OTG11_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_OTG11_EXCHG_PINS_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + */ +#define EFUSE_POWERGLITCH_EN (BIT(10)) +#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) +#define EFUSE_POWERGLITCH_EN_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_S 10 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; + * Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during + * boot_mode_download. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; + * TBD + */ +#define EFUSE_USB_PHY_SEL (BIT(25)) +#define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) +#define EFUSE_USB_PHY_SEL_V 0x00000001U +#define EFUSE_USB_PHY_SEL_S 25 +/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0; + * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even + * of 1 is valid. + */ +#define EFUSE_KM_HUK_GEN_STATE_LOW 0x0000003FU +#define EFUSE_KM_HUK_GEN_STATE_LOW_M (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S) +#define EFUSE_KM_HUK_GEN_STATE_LOW_V 0x0000003FU +#define EFUSE_KM_HUK_GEN_STATE_LOW_S 26 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Represents the purpose of Key1..*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Represents the purpose of Key0..*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Represents whether revoking third secure boot key is enabled or disabled. 1: ena -bled. 0: disabled..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Represents whether revoking second secure boot key is enabled or disabled. 1: en -abled. 0: disabled..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Represents whether revoking first secure boot key is enabled or disabled. 1: ena -bled. 0: disabled..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number o -f 1: enabled. Even number of 1: disabled..*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Represents whether RTC watchdog timeout threshold is selected at startup. 1: sel -ected. 0: not selected..*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_XTS_KEY_LENGTH_256 : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to configure flash encryption use xts-128 key, else use xts-256 key -..*/ -#define EFUSE_XTS_KEY_LENGTH_256 (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_M (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_V 0x1 -#define EFUSE_XTS_KEY_LENGTH_256_S 14 -/* EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO ;bitpos:[13] ;default: 3'h0 ; */ -/*description: Set this bit to disable software written init key, and force use efuse_init_key..*/ -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(13)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (BIT(13)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x1 -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 13 -/* EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO ;bitpos:[12:9] ;default: 4'h0 ; */ -/*description: Set each bit to control whether corresponding key must come from key manager.. 1 - is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds..*/ -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000F -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M ((EFUSE_FORCE_USE_KEY_MANAGER_KEY_V)<<(EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)) -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0xF -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 9 -/* EFUSE_KM_DEPLOY_ONLY_ONCE : RO ;bitpos:[8:5] ;default: 4'h0 ; */ -/*description: Set each bit to control whether corresponding key can only be deployed once. 1 i -s true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds..*/ -#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000F -#define EFUSE_KM_DEPLOY_ONLY_ONCE_M ((EFUSE_KM_DEPLOY_ONLY_ONCE_V)<<(EFUSE_KM_DEPLOY_ONLY_ONCE_S)) -#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0xF -#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 5 -/* EFUSE_KM_RND_SWITCH_CYCLE : RO ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: Set bits to control key manager random number switch cycle. 0: control by regist -er. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles..*/ -#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003 -#define EFUSE_KM_RND_SWITCH_CYCLE_M ((EFUSE_KM_RND_SWITCH_CYCLE_V)<<(EFUSE_KM_RND_SWITCH_CYCLE_S)) -#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x3 -#define EFUSE_KM_RND_SWITCH_CYCLE_S 3 -/* EFUSE_KM_HUK_GEN_STATE_HIGH : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, ev -en of 1 is valid..*/ -#define EFUSE_KM_HUK_GEN_STATE_HIGH 0x00000007 -#define EFUSE_KM_HUK_GEN_STATE_HIGH_M ((EFUSE_KM_HUK_GEN_STATE_HIGH_V)<<(EFUSE_KM_HUK_GEN_STATE_HIGH_S)) -#define EFUSE_KM_HUK_GEN_STATE_HIGH_V 0x7 +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0; + * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even + * of 1 is valid. + */ +#define EFUSE_KM_HUK_GEN_STATE_HIGH 0x00000007U +#define EFUSE_KM_HUK_GEN_STATE_HIGH_M (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S) +#define EFUSE_KM_HUK_GEN_STATE_HIGH_V 0x00000007U #define EFUSE_KM_HUK_GEN_STATE_HIGH_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0; + * Set bits to control key manager random number switch cycle. 0: control by register. + * 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. + */ +#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_S 3 +/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0; + * Set each bit to control whether corresponding key can only be deployed once. 1 is + * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 5 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0; + * Set each bit to control whether corresponding key must come from key manager.. 1 is + * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 9 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0; + * Set this bit to disable software written init key, and force use efuse_init_key. + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(13)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 13 +/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0; + * Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. + */ +#define EFUSE_XTS_KEY_LENGTH_256 (BIT(14)) +#define EFUSE_XTS_KEY_LENGTH_256_M (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S) +#define EFUSE_XTS_KEY_LENGTH_256_V 0x00000001U +#define EFUSE_XTS_KEY_LENGTH_256_S 14 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Represents the flash waiting time after power-up, in unit of ms. When the value -less than 15, the waiting time is the programmed value. Otherwise, the waiting t -ime is 2 times the programmed value..*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to disable download via USB-OTG..*/ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(27)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (BIT(27)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 27 -/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable ecc for flash boot..*/ -#define EFUSE_FLASH_ECC_EN (BIT(26)) -#define EFUSE_FLASH_ECC_EN_M (BIT(26)) -#define EFUSE_FLASH_ECC_EN_V 0x1 -#define EFUSE_FLASH_ECC_EN_S 26 -/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: Set flash page size..*/ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) -#define EFUSE_FLASH_PAGE_SIZE_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_S 24 -/* EFUSE_FLASH_TYPE : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The type of interfaced flash. 0: four data lines, 1: eight data lines..*/ -#define EFUSE_FLASH_TYPE (BIT(23)) -#define EFUSE_FLASH_TYPE_M (BIT(23)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 23 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Represents whether revoking aggressive secure boot is enabled or disabled. 1: en -abled. 0: disabled..*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled..*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_CRYPT_DPA_ENABLE : RO ;bitpos:[19] ;default: 1'b1 ; */ -/*description: Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled..*/ -#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_M (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_V 0x1 -#define EFUSE_CRYPT_DPA_ENABLE_S 19 -/* EFUSE_ECDSA_ENABLE_SOFT_K : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Represents whether hardware random number k is forced used in ESDCA. 1: force us -ed. 0: not force used..*/ -#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_M (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x1 -#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 -/* EFUSE_SEC_DPA_LEVEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Represents the spa secure level by configuring the clock random divide mode..*/ -#define EFUSE_SEC_DPA_LEVEL 0x00000003 -#define EFUSE_SEC_DPA_LEVEL_M ((EFUSE_SEC_DPA_LEVEL_V)<<(EFUSE_SEC_DPA_LEVEL_S)) -#define EFUSE_SEC_DPA_LEVEL_V 0x3 -#define EFUSE_SEC_DPA_LEVEL_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Represents the purpose of Key5..*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Represents the purpose of Key4..*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Represents the purpose of Key3..*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Represents the purpose of Key2..*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ +#define EFUSE_SEC_DPA_LEVEL 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) +#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_S 16 +/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. + */ +#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) +#define EFUSE_ECDSA_ENABLE_SOFT_K_M (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S) +#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x00000001U +#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ +#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) +#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_S 19 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0; + * The type of interfaced flash. 0: four data lines, 1: eight data lines. + */ +#define EFUSE_FLASH_TYPE (BIT(23)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001U +#define EFUSE_FLASH_TYPE_S 23 +/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0; + * Set flash page size. + */ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) +#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_S 24 +/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0; + * Set this bit to enable ecc for flash boot. + */ +#define EFUSE_FLASH_ECC_EN (BIT(26)) +#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) +#define EFUSE_FLASH_ECC_EN_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_S 26 +/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0; + * Set this bit to disable download via USB-OTG. + */ +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(27)) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 27 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3C) -/* EFUSE_DCDC_VSET : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Set the dcdc voltage default..*/ -#define EFUSE_DCDC_VSET 0x0000001F -#define EFUSE_DCDC_VSET_M ((EFUSE_DCDC_VSET_V)<<(EFUSE_DCDC_VSET_S)) -#define EFUSE_DCDC_VSET_V 0x1F -#define EFUSE_DCDC_VSET_S 27 -/* EFUSE_HYS_EN_PAD : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Represents whether the hysteresis function of corresponding PAD is enabled. 1: e -nabled. 0:disabled..*/ -#define EFUSE_HYS_EN_PAD (BIT(26)) -#define EFUSE_HYS_EN_PAD_M (BIT(26)) -#define EFUSE_HYS_EN_PAD_V 0x1 -#define EFUSE_HYS_EN_PAD_S 26 -/* EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot i -s enabled. 1: disabled. 0: enabled..*/ -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x1 -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[24:9] ;default: 16'h0 ; */ -/*description: Represents the version used by ESP-IDF anti-rollback feature..*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 9 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Represents whether ROM code is forced to send a resume command during SPI boot. -1: forced. 0:not forced..*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Represents the type of UART printing. 00: force enable printing. 01: enable prin -ting when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset a -t high level. 11: force disable printing..*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Represents whether security download is enabled or disabled. 1: enabled. 0: disa -bled..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Represents whether the USB-Serial-JTAG download function is disabled or enabled. - 1: disabled. 0: enabled..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_LOCK_KM_KEY : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: TBD.*/ -#define EFUSE_LOCK_KM_KEY (BIT(3)) -#define EFUSE_LOCK_KM_KEY_M (BIT(3)) -#define EFUSE_LOCK_KM_KEY_V 0x1 -#define EFUSE_LOCK_KM_KEY_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disable -d. 0: enabled..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enab -led..*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -..*/ +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; + * TBD + */ +#define EFUSE_LOCK_KM_KEY (BIT(3)) +#define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) +#define EFUSE_LOCK_KM_KEY_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 8 +/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 +/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ +#define EFUSE_HYS_EN_PAD (BIT(26)) +#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) +#define EFUSE_HYS_EN_PAD_V 0x00000001U +#define EFUSE_HYS_EN_PAD_S 26 +/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0; + * Set the dcdc voltage default. + */ +#define EFUSE_DCDC_VSET 0x0000001FU +#define EFUSE_DCDC_VSET_M (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S) +#define EFUSE_DCDC_VSET_V 0x0000001FU +#define EFUSE_DCDC_VSET_S 27 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/* EFUSE_DIS_SWD : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to disable super-watchdog..*/ -#define EFUSE_DIS_SWD (BIT(21)) -#define EFUSE_DIS_SWD_M (BIT(21)) -#define EFUSE_DIS_SWD_V 0x1 -#define EFUSE_DIS_SWD_S 21 -/* EFUSE_DIS_WDT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable watch dog..*/ -#define EFUSE_DIS_WDT (BIT(20)) -#define EFUSE_DIS_WDT_M (BIT(20)) -#define EFUSE_DIS_WDT_V 0x1 -#define EFUSE_DIS_WDT_S 20 -/* EFUSE_DCDC_VSET_EN : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Select dcdc vset use efuse_dcdc_vset..*/ -#define EFUSE_DCDC_VSET_EN (BIT(19)) -#define EFUSE_DCDC_VSET_EN_M (BIT(19)) -#define EFUSE_DCDC_VSET_EN_V 0x1 -#define EFUSE_DCDC_VSET_EN_S 19 -/* EFUSE_HP_PWR_SRC_SEL : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: HP system power source select. 0:LDO. 1: DCDC..*/ -#define EFUSE_HP_PWR_SRC_SEL (BIT(18)) -#define EFUSE_HP_PWR_SRC_SEL_M (BIT(18)) -#define EFUSE_HP_PWR_SRC_SEL_V 0x1 -#define EFUSE_HP_PWR_SRC_SEL_S 18 -/* EFUSE_USB_OTG11_DREFL : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with ste -p of 80 mV..*/ -#define EFUSE_USB_OTG11_DREFL 0x00000003 -#define EFUSE_USB_OTG11_DREFL_M ((EFUSE_USB_OTG11_DREFL_V)<<(EFUSE_USB_OTG11_DREFL_S)) -#define EFUSE_USB_OTG11_DREFL_V 0x3 -#define EFUSE_USB_OTG11_DREFL_S 14 -/* EFUSE_USB_DEVICE_DREFL : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with st -ep of 80 mV..*/ -#define EFUSE_USB_DEVICE_DREFL 0x00000003 -#define EFUSE_USB_DEVICE_DREFL_M ((EFUSE_USB_DEVICE_DREFL_V)<<(EFUSE_USB_DEVICE_DREFL_S)) -#define EFUSE_USB_DEVICE_DREFL_V 0x3 -#define EFUSE_USB_DEVICE_DREFL_S 12 -/* EFUSE_KM_DISABLE_DEPLOY_MODE : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: TBD..*/ -#define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000F -#define EFUSE_KM_DISABLE_DEPLOY_MODE_M ((EFUSE_KM_DISABLE_DEPLOY_MODE_V)<<(EFUSE_KM_DISABLE_DEPLOY_MODE_S)) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0xF -#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8 -/* EFUSE_0PXA_TIEH_SEL_3 : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: TBD..*/ -#define EFUSE_0PXA_TIEH_SEL_3 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_3_M ((EFUSE_0PXA_TIEH_SEL_3_V)<<(EFUSE_0PXA_TIEH_SEL_3_S)) -#define EFUSE_0PXA_TIEH_SEL_3_V 0x3 -#define EFUSE_0PXA_TIEH_SEL_3_S 6 -/* EFUSE_0PXA_TIEH_SEL_2 : RO ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: TBD..*/ -#define EFUSE_0PXA_TIEH_SEL_2 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_2_M ((EFUSE_0PXA_TIEH_SEL_2_V)<<(EFUSE_0PXA_TIEH_SEL_2_S)) -#define EFUSE_0PXA_TIEH_SEL_2_V 0x3 -#define EFUSE_0PXA_TIEH_SEL_2_S 4 -/* EFUSE_0PXA_TIEH_SEL_1 : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: TBD..*/ -#define EFUSE_0PXA_TIEH_SEL_1 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_1_M ((EFUSE_0PXA_TIEH_SEL_1_V)<<(EFUSE_0PXA_TIEH_SEL_1_S)) -#define EFUSE_0PXA_TIEH_SEL_1_V 0x3 -#define EFUSE_0PXA_TIEH_SEL_1_S 2 -/* EFUSE_0PXA_TIEH_SEL_0 : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: TBD.*/ -#define EFUSE_0PXA_TIEH_SEL_0 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_0_M ((EFUSE_0PXA_TIEH_SEL_0_V)<<(EFUSE_0PXA_TIEH_SEL_0_S)) -#define EFUSE_0PXA_TIEH_SEL_0_V 0x3 +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_0PXA_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0; + * TBD + */ +#define EFUSE_0PXA_TIEH_SEL_0 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_0_M (EFUSE_0PXA_TIEH_SEL_0_V << EFUSE_0PXA_TIEH_SEL_0_S) +#define EFUSE_0PXA_TIEH_SEL_0_V 0x00000003U #define EFUSE_0PXA_TIEH_SEL_0_S 0 +/** EFUSE_0PXA_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0; + * TBD. + */ +#define EFUSE_0PXA_TIEH_SEL_1 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_1_M (EFUSE_0PXA_TIEH_SEL_1_V << EFUSE_0PXA_TIEH_SEL_1_S) +#define EFUSE_0PXA_TIEH_SEL_1_V 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_1_S 2 +/** EFUSE_0PXA_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0; + * TBD. + */ +#define EFUSE_0PXA_TIEH_SEL_2 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_2_M (EFUSE_0PXA_TIEH_SEL_2_V << EFUSE_0PXA_TIEH_SEL_2_S) +#define EFUSE_0PXA_TIEH_SEL_2_V 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_2_S 4 +/** EFUSE_0PXA_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0; + * TBD. + */ +#define EFUSE_0PXA_TIEH_SEL_3 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_3_M (EFUSE_0PXA_TIEH_SEL_3_V << EFUSE_0PXA_TIEH_SEL_3_S) +#define EFUSE_0PXA_TIEH_SEL_3_V 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_3_S 6 +/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0; + * TBD. + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8 +/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0; + * HP system power source select. 0:LDO. 1: DCDC. + */ +#define EFUSE_HP_PWR_SRC_SEL (BIT(18)) +#define EFUSE_HP_PWR_SRC_SEL_M (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S) +#define EFUSE_HP_PWR_SRC_SEL_V 0x00000001U +#define EFUSE_HP_PWR_SRC_SEL_S 18 +/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0; + * Select dcdc vset use efuse_dcdc_vset. + */ +#define EFUSE_DCDC_VSET_EN (BIT(19)) +#define EFUSE_DCDC_VSET_EN_M (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S) +#define EFUSE_DCDC_VSET_EN_V 0x00000001U +#define EFUSE_DCDC_VSET_EN_S 19 +/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0; + * Set this bit to disable watch dog. + */ +#define EFUSE_DIS_WDT (BIT(20)) +#define EFUSE_DIS_WDT_M (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S) +#define EFUSE_DIS_WDT_V 0x00000001U +#define EFUSE_DIS_WDT_S 20 +/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0; + * Set this bit to disable super-watchdog. + */ +#define EFUSE_DIS_SWD (BIT(21)) +#define EFUSE_DIS_SWD_M (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S) +#define EFUSE_DIS_SWD_V 0x00000001U +#define EFUSE_DIS_SWD_S 21 -#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address..*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SYS_0_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) -/* EFUSE_MAC_EXT : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the extended bits of MAC address..*/ -#define EFUSE_MAC_EXT 0x0000FFFF -#define EFUSE_MAC_EXT_M ((EFUSE_MAC_EXT_V)<<(EFUSE_MAC_EXT_S)) -#define EFUSE_MAC_EXT_V 0xFFFF -#define EFUSE_MAC_EXT_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address..*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF +/** EFUSE_RD_MAC_SYS_1_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 -#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4C) -/* EFUSE_MAC_RESERVED_0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */ -/*description: Reserved..*/ -#define EFUSE_MAC_RESERVED_0 0x0003FFFF -#define EFUSE_MAC_RESERVED_0_M ((EFUSE_MAC_RESERVED_0_V)<<(EFUSE_MAC_RESERVED_0_S)) -#define EFUSE_MAC_RESERVED_0_V 0x3FFFF -#define EFUSE_MAC_RESERVED_0_S 14 -/* EFUSE_MAC_RESERVED_1 : RO ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: Reserved..*/ -#define EFUSE_MAC_RESERVED_1 0x00003FFF -#define EFUSE_MAC_RESERVED_1_M ((EFUSE_MAC_RESERVED_1_V)<<(EFUSE_MAC_RESERVED_1_S)) -#define EFUSE_MAC_RESERVED_1_V 0x3FFF +/** EFUSE_RD_MAC_SYS_2_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU #define EFUSE_MAC_RESERVED_1_S 0 +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_0 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_S 14 -#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ -/*description: Stores the first 14 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 -/* EFUSE_MAC_RESERVED_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Reserved..*/ -#define EFUSE_MAC_RESERVED_2 0x0003FFFF -#define EFUSE_MAC_RESERVED_2_M ((EFUSE_MAC_RESERVED_2_V)<<(EFUSE_MAC_RESERVED_2_S)) -#define EFUSE_MAC_RESERVED_2_V 0x3FFFF +/** EFUSE_RD_MAC_SYS_3_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU #define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 -#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SYS_4_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_1_S 0 -#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +/** EFUSE_RD_MAC_SYS_5_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5C) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_0_S 0 -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_1_S 0 -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_3_S 0 -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6C) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_4_S 0 -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_5_S 0 -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_6_S 0 -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data..*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_7_S 0 -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7C) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA0_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA1_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA2_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA3_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8C) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA4_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA5_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA6_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU #define EFUSE_USR_DATA6_S 0 -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user)..*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_USR_DATA7_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU #define EFUSE_USR_DATA7_S 0 -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9C) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA0_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xA0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA1_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xA4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA2_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xA8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA3_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xAC) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA4_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xB0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA5_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xB4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA6_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xB8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0..*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY0_DATA7_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xBC) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA0_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xC0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA1_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xC4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA2_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xC8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA3_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xCC) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA4_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xD0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA5_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xD4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA6_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xD8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1..*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY1_DATA7_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xDC) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA0_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xE0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA1_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xE4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA2_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xE8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA3_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xEC) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA4_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xF0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA5_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xF4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA6_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xF8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2..*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY2_DATA7_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xFC) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA0_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_S 0 -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA1_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_S 0 -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA2_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_S 0 -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA3_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_S 0 -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA4_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_S 0 -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA5_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_S 0 -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA6_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_S 0 -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3..*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY3_DATA7_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_S 0 -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA0_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_S 0 -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA1_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_S 0 -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA2_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_S 0 -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA3_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_S 0 -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA4_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_S 0 -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA5_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_S 0 -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA6_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_S 0 -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4..*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY4_DATA7_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_S 0 -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA0_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_S 0 -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_S 0 -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA2_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_S 0 -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA3_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_S 0 -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA4_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_S 0 -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA5_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_S 0 -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA6_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_S 0 -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5..*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +/** EFUSE_RD_KEY5_DATA7_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data..*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) -/* EFUSE_HUK_GEN_STATE_LOW_ERR : RO ;bitpos:[31:26] ;default: 6'h0 ; */ -/*description: Indicates a programming error of HUK_GEN_STATE_LOW..*/ -#define EFUSE_HUK_GEN_STATE_LOW_ERR 0x0000003F -#define EFUSE_HUK_GEN_STATE_LOW_ERR_M ((EFUSE_HUK_GEN_STATE_LOW_ERR_V)<<(EFUSE_HUK_GEN_STATE_LOW_ERR_S)) -#define EFUSE_HUK_GEN_STATE_LOW_ERR_V 0x3F -#define EFUSE_HUK_GEN_STATE_LOW_ERR_S 26 -/* EFUSE_USB_PHY_SEL_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Indicates a programming error of USB_PHY_SEL..*/ -#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_M (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_V 0x1 -#define EFUSE_USB_PHY_SEL_ERR_S 25 -/* EFUSE_USB_OTG11_DREFH_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Indicates a programming error of USB_OTG11_DREFH..*/ -#define EFUSE_USB_OTG11_DREFH_ERR 0x00000003 -#define EFUSE_USB_OTG11_DREFH_ERR_M ((EFUSE_USB_OTG11_DREFH_ERR_V)<<(EFUSE_USB_OTG11_DREFH_ERR_S)) -#define EFUSE_USB_OTG11_DREFH_ERR_V 0x3 -#define EFUSE_USB_OTG11_DREFH_ERR_S 23 -/* EFUSE_USB_DEVICE_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Indicates a programming error of USB_DEVICE_DREFH..*/ -#define EFUSE_USB_DEVICE_DREFH_ERR 0x00000003 -#define EFUSE_USB_DEVICE_DREFH_ERR_M ((EFUSE_USB_DEVICE_DREFH_ERR_V)<<(EFUSE_USB_DEVICE_DREFH_ERR_S)) -#define EFUSE_USB_DEVICE_DREFH_ERR_V 0x3 -#define EFUSE_USB_DEVICE_DREFH_ERR_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT..*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_PAD_JTAG..*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Indicates a programming error of SOFT_DIS_JTAG..*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Indicates a programming error of JTAG_SEL_ENABLE..*/ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_TWAI..*/ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_V 0x1 -#define EFUSE_DIS_TWAI_ERR_S 14 -/* EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS..*/ -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x1 -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_FORCE_DOWNLOAD..*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 -/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Indicates a programming error of POWERGLITCH_EN..*/ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) -#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(10)) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x1 -#define EFUSE_POWERGLITCH_EN_ERR_S 10 -/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_JTAG..*/ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/* EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS..*/ -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR (BIT(8)) -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M (BIT(8)) -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S 8 -/* EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS..*/ -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR (BIT(7)) -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M (BIT(7)) -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Indicates a programming error of RD_DIS..*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + */ +#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR (BIT(7)) +#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S) +#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S 7 +/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + */ +#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR (BIT(8)) +#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S) +#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; + * Indicates a programming error of POWERGLITCH_EN. + */ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) +#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_ERR_S 10 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 +/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_TWAI. + */ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) +#define EFUSE_DIS_TWAI_ERR_V 0x00000001U +#define EFUSE_DIS_TWAI_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_PHY_SEL. + */ +#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) +#define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) +#define EFUSE_USB_PHY_SEL_ERR_V 0x00000001U +#define EFUSE_USB_PHY_SEL_ERR_S 25 +/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0; + * Indicates a programming error of HUK_GEN_STATE_LOW. + */ +#define EFUSE_HUK_GEN_STATE_LOW_ERR 0x0000003FU +#define EFUSE_HUK_GEN_STATE_LOW_ERR_M (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S) +#define EFUSE_HUK_GEN_STATE_LOW_ERR_V 0x0000003FU +#define EFUSE_HUK_GEN_STATE_LOW_ERR_S 26 -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KEY_PURPOSE_1..*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KEY_PURPOSE_0..*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE2..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE1..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE0..*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Indicates a programming error of SPI_BOOT_CRYPT_CNT..*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Indicates a programming error of WDT_DELAY_SEL..*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_XTS_KEY_LENGTH_256_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Indicates a programming error of XTS_KEY_LENGTH_256..*/ -#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x1 -#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 14 -/* EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO ;bitpos:[13] ;default: 3'h0 ; */ -/*description: Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY..*/ -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(13)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (BIT(13)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x1 -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 13 -/* EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO ;bitpos:[12:9] ;default: 4'h0 ; */ -/*description: Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY..*/ -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000F -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M ((EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V)<<(EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)) -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0xF -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 9 -/* EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO ;bitpos:[8:5] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KM_DEPLOY_ONLY_ONCE..*/ -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000F -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M ((EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V)<<(EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)) -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0xF -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 5 -/* EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: Indicates a programming error of KM_RND_SWITCH_CYCLE..*/ -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003 -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M ((EFUSE_KM_RND_SWITCH_CYCLE_ERR_V)<<(EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)) -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x3 -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 3 -/* EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: Indicates a programming error of HUK_GEN_STATE_HIGH..*/ -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR 0x00000007 -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M ((EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V)<<(EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)) -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V 0x7 +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0; + * Indicates a programming error of HUK_GEN_STATE_HIGH. + */ +#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR 0x00000007U +#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S) +#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V 0x00000007U #define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0; + * Indicates a programming error of KM_RND_SWITCH_CYCLE. + */ +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 3 +/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0; + * Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 5 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0; + * Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 9 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(13)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 13 +/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of XTS_KEY_LENGTH_256. + */ +#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(14)) +#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S) +#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x00000001U +#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 14 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Indicates a programming error of FLASH_TPUW..*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE..*/ -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR (BIT(27)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M (BIT(27)) -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S 27 -/* EFUSE_FLASH_ECC_EN_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Indicates a programming error of FLASH_ECC_EN..*/ -#define EFUSE_FLASH_ECC_EN_ERR (BIT(26)) -#define EFUSE_FLASH_ECC_EN_ERR_M (BIT(26)) -#define EFUSE_FLASH_ECC_EN_ERR_V 0x1 -#define EFUSE_FLASH_ECC_EN_ERR_S 26 -/* EFUSE_FLASH_PAGE_SIZE_ERR : RO ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: Indicates a programming error of FLASH_PAGE_SIZE..*/ -#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_ERR_M ((EFUSE_FLASH_PAGE_SIZE_ERR_V)<<(EFUSE_FLASH_PAGE_SIZE_ERR_S)) -#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_ERR_S 24 -/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Indicates a programming error of FLASH_TYPE..*/ -#define EFUSE_FLASH_TYPE_ERR (BIT(23)) -#define EFUSE_FLASH_TYPE_ERR_M (BIT(23)) -#define EFUSE_FLASH_TYPE_ERR_V 0x1 -#define EFUSE_FLASH_TYPE_ERR_S 23 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE..*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Indicates a programming error of SECURE_BOOT_EN..*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_CRYPT_DPA_ENABLE_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Indicates a programming error of CRYPT_DPA_ENABLE..*/ -#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x1 -#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 -/* EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K..*/ -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x1 -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 -/* EFUSE_SEC_DPA_LEVEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Indicates a programming error of SEC_DPA_LEVEL..*/ -#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003 -#define EFUSE_SEC_DPA_LEVEL_ERR_M ((EFUSE_SEC_DPA_LEVEL_ERR_V)<<(EFUSE_SEC_DPA_LEVEL_ERR_S)) -#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x3 -#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KEY_PURPOSE_5..*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KEY_PURPOSE_4..*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KEY_PURPOSE_3..*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates a programming error of KEY_PURPOSE_2..*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 +/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0; + * Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + */ +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S) +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x00000001U +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 +/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ +#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0; + * Indicates a programming error of FLASH_TYPE. + */ +#define EFUSE_FLASH_TYPE_ERR (BIT(23)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U +#define EFUSE_FLASH_TYPE_ERR_S 23 +/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0; + * Indicates a programming error of FLASH_PAGE_SIZE. + */ +#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) +#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U +#define EFUSE_FLASH_PAGE_SIZE_ERR_S 24 +/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of FLASH_ECC_EN. + */ +#define EFUSE_FLASH_ECC_EN_ERR (BIT(26)) +#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) +#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U +#define EFUSE_FLASH_ECC_EN_ERR_S 26 +/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0; + * Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR (BIT(27)) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S 27 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_DCDC_VSET_ERR : RO ;bitpos:[31:27] ;default: 5'h0 ; */ -/*description: Indicates a programming error of DCDC_VSET..*/ -#define EFUSE_DCDC_VSET_ERR 0x0000001F -#define EFUSE_DCDC_VSET_ERR_M ((EFUSE_DCDC_VSET_ERR_V)<<(EFUSE_DCDC_VSET_ERR_S)) -#define EFUSE_DCDC_VSET_ERR_V 0x1F -#define EFUSE_DCDC_VSET_ERR_S 27 -/* EFUSE_HYS_EN_PAD_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Indicates a programming error of HYS_EN_PAD..*/ -#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) -#define EFUSE_HYS_EN_PAD_ERR_M (BIT(26)) -#define EFUSE_HYS_EN_PAD_ERR_V 0x1 -#define EFUSE_HYS_EN_PAD_ERR_S 26 -/* EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE..*/ -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[24:9] ;default: 16'h0 ; */ -/*description: Indicates a programming error of SECURE VERSION..*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 9 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Indicates a programming error of FORCE_SEND_RESUME..*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Indicates a programming error of UART_PRINT_CONTROL..*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Indicates a programming error of ENABLE_SECURITY_DOWNLOAD..*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_LOCK_KM_KEY_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: TBD.*/ -#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) -#define EFUSE_LOCK_KM_KEY_ERR_M (BIT(3)) -#define EFUSE_LOCK_KM_KEY_ERR_V 0x1 -#define EFUSE_LOCK_KM_KEY_ERR_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR..*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_DIRECT_BOOT..*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_DOWNLOAD_MODE..*/ +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; + * TBD + */ +#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) +#define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) +#define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_ERR_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 +/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of HYS_EN_PAD. + */ +#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) +#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) +#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U +#define EFUSE_HYS_EN_PAD_ERR_S 26 +/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0; + * Indicates a programming error of DCDC_VSET. + */ +#define EFUSE_DCDC_VSET_ERR 0x0000001FU +#define EFUSE_DCDC_VSET_ERR_M (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S) +#define EFUSE_DCDC_VSET_ERR_V 0x0000001FU +#define EFUSE_DCDC_VSET_ERR_S 27 -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_DIS_SWD_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_SWD..*/ -#define EFUSE_DIS_SWD_ERR (BIT(21)) -#define EFUSE_DIS_SWD_ERR_M (BIT(21)) -#define EFUSE_DIS_SWD_ERR_V 0x1 -#define EFUSE_DIS_SWD_ERR_S 21 -/* EFUSE_DIS_WDT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DIS_WDT..*/ -#define EFUSE_DIS_WDT_ERR (BIT(20)) -#define EFUSE_DIS_WDT_ERR_M (BIT(20)) -#define EFUSE_DIS_WDT_ERR_V 0x1 -#define EFUSE_DIS_WDT_ERR_S 20 -/* EFUSE_DCDC_VSET_EN_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Indicates a programming error of DCDC_VSET_EN..*/ -#define EFUSE_DCDC_VSET_EN_ERR (BIT(19)) -#define EFUSE_DCDC_VSET_EN_ERR_M (BIT(19)) -#define EFUSE_DCDC_VSET_EN_ERR_V 0x1 -#define EFUSE_DCDC_VSET_EN_ERR_S 19 -/* EFUSE_HP_PWR_SRC_SEL_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Indicates a programming error of HP_PWR_SRC_SEL..*/ -#define EFUSE_HP_PWR_SRC_SEL_ERR (BIT(18)) -#define EFUSE_HP_PWR_SRC_SEL_ERR_M (BIT(18)) -#define EFUSE_HP_PWR_SRC_SEL_ERR_V 0x1 -#define EFUSE_HP_PWR_SRC_SEL_ERR_S 18 -/* EFUSE_USB_OTG11_DREFL_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Indicates a programming error of USB_OTG11_DREFL..*/ -#define EFUSE_USB_OTG11_DREFL_ERR 0x00000003 -#define EFUSE_USB_OTG11_DREFL_ERR_M ((EFUSE_USB_OTG11_DREFL_ERR_V)<<(EFUSE_USB_OTG11_DREFL_ERR_S)) -#define EFUSE_USB_OTG11_DREFL_ERR_V 0x3 -#define EFUSE_USB_OTG11_DREFL_ERR_S 14 -/* EFUSE_USB_DEVICE_DREFL_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Indicates a programming error of USB_DEVICE_DREFL..*/ -#define EFUSE_USB_DEVICE_DREFL_ERR 0x00000003 -#define EFUSE_USB_DEVICE_DREFL_ERR_M ((EFUSE_USB_DEVICE_DREFL_ERR_V)<<(EFUSE_USB_DEVICE_DREFL_ERR_S)) -#define EFUSE_USB_DEVICE_DREFL_ERR_V 0x3 -#define EFUSE_USB_DEVICE_DREFL_ERR_S 12 -/* EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: TBD..*/ -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000F -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M ((EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V)<<(EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0xF -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 8 -/* EFUSE_0PXA_TIEH_SEL_3_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Indicates a programming error of 0PXA_TIEH_SEL_3..*/ -#define EFUSE_0PXA_TIEH_SEL_3_ERR 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_3_ERR_M ((EFUSE_0PXA_TIEH_SEL_3_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_3_ERR_S)) -#define EFUSE_0PXA_TIEH_SEL_3_ERR_V 0x3 -#define EFUSE_0PXA_TIEH_SEL_3_ERR_S 6 -/* EFUSE_0PXA_TIEH_SEL_2_ERR : RO ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: Indicates a programming error of 0PXA_TIEH_SEL_2..*/ -#define EFUSE_0PXA_TIEH_SEL_2_ERR 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_2_ERR_M ((EFUSE_0PXA_TIEH_SEL_2_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_2_ERR_S)) -#define EFUSE_0PXA_TIEH_SEL_2_ERR_V 0x3 -#define EFUSE_0PXA_TIEH_SEL_2_ERR_S 4 -/* EFUSE_0PXA_TIEH_SEL_1_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: Indicates a programming error of 0PXA_TIEH_SEL_1..*/ -#define EFUSE_0PXA_TIEH_SEL_1_ERR 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_1_ERR_M ((EFUSE_0PXA_TIEH_SEL_1_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_1_ERR_S)) -#define EFUSE_0PXA_TIEH_SEL_1_ERR_V 0x3 -#define EFUSE_0PXA_TIEH_SEL_1_ERR_S 2 -/* EFUSE_0PXA_TIEH_SEL_0_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: Indicates a programming error of 0PXA_TIEH_SEL_0..*/ -#define EFUSE_0PXA_TIEH_SEL_0_ERR 0x00000003 -#define EFUSE_0PXA_TIEH_SEL_0_ERR_M ((EFUSE_0PXA_TIEH_SEL_0_ERR_V)<<(EFUSE_0PXA_TIEH_SEL_0_ERR_S)) -#define EFUSE_0PXA_TIEH_SEL_0_ERR_V 0x3 +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +/** EFUSE_0PXA_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_0. + */ +#define EFUSE_0PXA_TIEH_SEL_0_ERR 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_0_ERR_M (EFUSE_0PXA_TIEH_SEL_0_ERR_V << EFUSE_0PXA_TIEH_SEL_0_ERR_S) +#define EFUSE_0PXA_TIEH_SEL_0_ERR_V 0x00000003U #define EFUSE_0PXA_TIEH_SEL_0_ERR_S 0 +/** EFUSE_0PXA_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_1. + */ +#define EFUSE_0PXA_TIEH_SEL_1_ERR 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_1_ERR_M (EFUSE_0PXA_TIEH_SEL_1_ERR_V << EFUSE_0PXA_TIEH_SEL_1_ERR_S) +#define EFUSE_0PXA_TIEH_SEL_1_ERR_V 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_1_ERR_S 2 +/** EFUSE_0PXA_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_2. + */ +#define EFUSE_0PXA_TIEH_SEL_2_ERR 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_2_ERR_M (EFUSE_0PXA_TIEH_SEL_2_ERR_V << EFUSE_0PXA_TIEH_SEL_2_ERR_S) +#define EFUSE_0PXA_TIEH_SEL_2_ERR_V 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_2_ERR_S 4 +/** EFUSE_0PXA_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_3. + */ +#define EFUSE_0PXA_TIEH_SEL_3_ERR 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_3_ERR_M (EFUSE_0PXA_TIEH_SEL_3_ERR_V << EFUSE_0PXA_TIEH_SEL_3_ERR_S) +#define EFUSE_0PXA_TIEH_SEL_3_ERR_V 0x00000003U +#define EFUSE_0PXA_TIEH_SEL_3_ERR_S 6 +/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0; + * TBD. + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 8 +/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0; + * Indicates a programming error of USB_DEVICE_DREFL. + */ +#define EFUSE_USB_DEVICE_DREFL_ERR 0x00000003U +#define EFUSE_USB_DEVICE_DREFL_ERR_M (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S) +#define EFUSE_USB_DEVICE_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DEVICE_DREFL_ERR_S 12 +/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0; + * Indicates a programming error of USB_OTG11_DREFL. + */ +#define EFUSE_USB_OTG11_DREFL_ERR 0x00000003U +#define EFUSE_USB_OTG11_DREFL_ERR_M (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S) +#define EFUSE_USB_OTG11_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_OTG11_DREFL_ERR_S 14 +/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0; + * Indicates a programming error of HP_PWR_SRC_SEL. + */ +#define EFUSE_HP_PWR_SRC_SEL_ERR (BIT(18)) +#define EFUSE_HP_PWR_SRC_SEL_ERR_M (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S) +#define EFUSE_HP_PWR_SRC_SEL_ERR_V 0x00000001U +#define EFUSE_HP_PWR_SRC_SEL_ERR_S 18 +/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DCDC_VSET_EN. + */ +#define EFUSE_DCDC_VSET_EN_ERR (BIT(19)) +#define EFUSE_DCDC_VSET_EN_ERR_M (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S) +#define EFUSE_DCDC_VSET_EN_ERR_V 0x00000001U +#define EFUSE_DCDC_VSET_EN_ERR_S 19 +/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_WDT. + */ +#define EFUSE_DIS_WDT_ERR (BIT(20)) +#define EFUSE_DIS_WDT_ERR_M (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S) +#define EFUSE_DIS_WDT_ERR_V 0x00000001U +#define EFUSE_DIS_WDT_ERR_S 20 +/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of DIS_SWD. + */ +#define EFUSE_DIS_SWD_ERR (BIT(21)) +#define EFUSE_DIS_SWD_ERR_M (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S) +#define EFUSE_DIS_SWD_ERR_V 0x00000001U +#define EFUSE_DIS_SWD_ERR_S 21 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) -/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key4 is reliable 1: Means that programm -ing key4 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (BIT(31)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key3 is reliable 1: Means that programm -ing key3 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (BIT(27)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key2 is reliable 1: Means that programm -ing key2 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (BIT(23)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key1 is reliable 1: Means that programm -ing key1 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (BIT(19)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key0 is reliable 1: Means that programm -ing key0 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (BIT(15)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the user data is reliable 1: Means that programming - user data failed and the number of error bytes is over 6..*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable 1: Means that -programming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 7 -/* EFUSE_SYS_PART1_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_SYS_PART1_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART1_ERR_NUM_M ((EFUSE_SYS_PART1_ERR_NUM_V)<<(EFUSE_SYS_PART1_ERR_NUM_S)) -#define EFUSE_SYS_PART1_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART1_ERR_NUM_S 4 -/* EFUSE_MAC_SYS_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that pr -ogramming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_MAC_SYS_FAIL_M (BIT(3)) -#define EFUSE_MAC_SYS_FAIL_V 0x1 -#define EFUSE_MAC_SYS_FAIL_S 3 -/* EFUSE_MAC_SYS_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_MAC_SYS_ERR_NUM 0x00000007 -#define EFUSE_MAC_SYS_ERR_NUM_M ((EFUSE_MAC_SYS_ERR_NUM_V)<<(EFUSE_MAC_SYS_ERR_NUM_S)) -#define EFUSE_MAC_SYS_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_MAC_SYS_ERR_NUM_M (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S) +#define EFUSE_MAC_SYS_ERR_NUM_V 0x00000007U #define EFUSE_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_MAC_SYS_FAIL_M (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S) +#define EFUSE_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_MAC_SYS_FAIL_S 3 +/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART1_ERR_NUM_M (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S) +#define EFUSE_SYS_PART1_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_ERR_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) -/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable 1: Means that -programming user data failed and the number of error bytes is over 6..*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_V 0x1 -#define EFUSE_SYS_PART2_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key5 is reliable 1: Means that programm -ing key5 failed and the number of error bytes is over 6..*/ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (BIT(3)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes..*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U #define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to force enable eFuse register configuration clock signal..*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode..*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 -#define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode..*/ +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ #define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) -/* EFUSE_CFG_ECDSA_BLK : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Configures which block to use for ECDSA key output..*/ -#define EFUSE_CFG_ECDSA_BLK 0x0000000F -#define EFUSE_CFG_ECDSA_BLK_M ((EFUSE_CFG_ECDSA_BLK_V)<<(EFUSE_CFG_ECDSA_BLK_S)) -#define EFUSE_CFG_ECDSA_BLK_V 0xF -#define EFUSE_CFG_ECDSA_BLK_S 16 -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: programming operation command 0x5AA5: read operation command..*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) -/* EFUSE_CUR_ECDSA_BLK : RO ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: Indicates which block is used for ECDSA key output..*/ -#define EFUSE_CUR_ECDSA_BLK 0x0000000F -#define EFUSE_CUR_ECDSA_BLK_M ((EFUSE_CUR_ECDSA_BLK_V)<<(EFUSE_CUR_ECDSA_BLK_S)) -#define EFUSE_CUR_ECDSA_BLK_V 0xF -#define EFUSE_CUR_ECDSA_BLK_S 20 -/* EFUSE_BLK0_VALID_BIT_CNT : RO ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: Indicates the number of block valid bit..*/ -#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FF -#define EFUSE_BLK0_VALID_BIT_CNT_M ((EFUSE_BLK0_VALID_BIT_CNT_V)<<(EFUSE_BLK0_VALID_BIT_CNT_S)) -#define EFUSE_BLK0_VALID_BIT_CNT_V 0x3FF -#define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW..*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW..*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW..*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW..*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2..*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW..*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine..*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds to block - number 0-10, respectively..*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command..*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command..*/ +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ #define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt..*/ +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt..*/ +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt..*/ +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) -/* EFUSE_PGM_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt..*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt..*/ +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage..*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage..*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care..*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd23 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage..*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU #define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'hf ; */ -/*description: Configures the waiting time of reading eFuse memory..*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF -#define EFUSE_READ_INIT_NUM_S 24 -/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ -/*description: Configures the read setup time..*/ -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S)) -#define EFUSE_TSUR_A_V 0xFF -#define EFUSE_TSUR_A_S 16 -/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: Configures the read time..*/ -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S)) -#define EFUSE_TRD_V 0xFF -#define EFUSE_TRD_S 8 -/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the read hold time..*/ -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S)) -#define EFUSE_THR_A_V 0xFF +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_THP_A : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ -/*description: Configures the programming hold time..*/ -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S)) -#define EFUSE_THP_A_V 0xFF -#define EFUSE_THP_A_S 24 -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2667 ; */ -/*description: Configures the power up time for VDDQ..*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF -#define EFUSE_PWR_ON_NUM_S 8 -/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the programming setup time..*/ -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S)) -#define EFUSE_TSUP_A_V 0xFF +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'ha0 ; */ -/*description: Configures the active programming time..*/ -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S)) -#define EFUSE_TPGM_V 0xFFFF -#define EFUSE_TPGM_S 16 -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h140 ; */ -/*description: Configures the power outage time for VDDQ..*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 -#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1F8) -/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[20:13] ;default: 8'h1 ; */ -/*description: Configures the inactive programming time..*/ -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S)) -#define EFUSE_TPGM_INACTIVE_V 0xFF -#define EFUSE_TPGM_INACTIVE_S 13 -/* EFUSE_UPDATE : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to update multi-bit register signals..*/ -#define EFUSE_UPDATE (BIT(12)) -#define EFUSE_UPDATE_M (BIT(12)) -#define EFUSE_UPDATE_V 0x1 -#define EFUSE_UPDATE_S 12 -/* EFUSE_BYPASS_RS_BLK_NUM : R/W ;bitpos:[11:1] ;default: 11'h0 ; */ -/*description: Configures block number of programming twice operation..*/ -#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FF -#define EFUSE_BYPASS_RS_BLK_NUM_M ((EFUSE_BYPASS_RS_BLK_NUM_V)<<(EFUSE_BYPASS_RS_BLK_NUM_S)) -#define EFUSE_BYPASS_RS_BLK_NUM_V 0x7FF -#define EFUSE_BYPASS_RS_BLK_NUM_S 1 -/* EFUSE_BYPASS_RS_CORRECTION : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to bypass reed solomon correction step..*/ +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) -#define EFUSE_BYPASS_RS_CORRECTION_M (BIT(0)) -#define EFUSE_BYPASS_RS_CORRECTION_V 0x1 +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U #define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2305050 ; */ -/*description: Stores eFuse version..*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU #define EFUSE_DATE_S 0 -#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800) -/* EFUSE_APB2OTP_BLOCK0_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 write disable data..*/ -#define EFUSE_APB2OTP_BLOCK0_WR_DIS 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M ((EFUSE_APB2OTP_BLOCK0_WR_DIS_V)<<(EFUSE_APB2OTP_BLOCK0_WR_DIS_S)) -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V 0xFFFFFFFF +/** EFUSE_APB2OTP_WR_DIS_REG register + * eFuse apb2otp block0 data register1. + */ +#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800) +/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ +#define EFUSE_APB2OTP_BLOCK0_WR_DIS 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S) +#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_WR_DIS_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804) -/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup1 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register + * eFuse apb2otp block0 data register2. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808) -/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup1 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register + * eFuse apb2otp block0 data register3. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80C) -/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup1 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register + * eFuse apb2otp block0 data register4. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810) -/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup1 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register + * eFuse apb2otp block0 data register5. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814) -/* EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup1 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M ((EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register + * eFuse apb2otp block0 data register6. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814) +/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818) -/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup2 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register + * eFuse apb2otp block0 data register7. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81C) -/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup2 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register + * eFuse apb2otp block0 data register8. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820) -/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup2 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register + * eFuse apb2otp block0 data register9. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824) -/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup2 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register + * eFuse apb2otp block0 data register10. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828) -/* EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup2 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M ((EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register + * eFuse apb2otp block0 data register11. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828) +/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82C) -/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup3 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register + * eFuse apb2otp block0 data register12. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830) -/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup3 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register + * eFuse apb2otp block0 data register13. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834) -/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup3 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register + * eFuse apb2otp block0 data register14. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838) -/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup3 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register + * eFuse apb2otp block0 data register15. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83C) -/* EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup3 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M ((EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register + * eFuse apb2otp block0 data register16. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840) -/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup4 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register + * eFuse apb2otp block0 data register17. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844) -/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup4 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register + * eFuse apb2otp block0 data register18. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848) -/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup4 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register + * eFuse apb2otp block0 data register19. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84C) -/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup4 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register + * eFuse apb2otp block0 data register20. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S 0 -#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850) -/* EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block0 backup4 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M ((EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V)<<(EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register + * eFuse apb2otp block0 data register21. + */ +#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850) +/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S) +#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S 0 -#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854) -/* EFUSE_APB2OTP_BLOCK1_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W1_M ((EFUSE_APB2OTP_BLOCK1_W1_V)<<(EFUSE_APB2OTP_BLOCK1_W1_S)) -#define EFUSE_APB2OTP_BLOCK1_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W1_REG register + * eFuse apb2otp block1 data register1. + */ +#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854) +/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W1_M (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S) +#define EFUSE_APB2OTP_BLOCK1_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W1_S 0 -#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858) -/* EFUSE_APB2OTP_BLOCK1_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W2_M ((EFUSE_APB2OTP_BLOCK1_W2_V)<<(EFUSE_APB2OTP_BLOCK1_W2_S)) -#define EFUSE_APB2OTP_BLOCK1_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W2_REG register + * eFuse apb2otp block1 data register2. + */ +#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858) +/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W2_M (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S) +#define EFUSE_APB2OTP_BLOCK1_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W2_S 0 -#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85C) -/* EFUSE_APB2OTP_BLOCK1_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W3_M ((EFUSE_APB2OTP_BLOCK1_W3_V)<<(EFUSE_APB2OTP_BLOCK1_W3_S)) -#define EFUSE_APB2OTP_BLOCK1_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W3_REG register + * eFuse apb2otp block1 data register3. + */ +#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c) +/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W3_M (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S) +#define EFUSE_APB2OTP_BLOCK1_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W3_S 0 -#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860) -/* EFUSE_APB2OTP_BLOCK1_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W4_M ((EFUSE_APB2OTP_BLOCK1_W4_V)<<(EFUSE_APB2OTP_BLOCK1_W4_S)) -#define EFUSE_APB2OTP_BLOCK1_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W4_REG register + * eFuse apb2otp block1 data register4. + */ +#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860) +/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W4_M (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S) +#define EFUSE_APB2OTP_BLOCK1_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W4_S 0 -#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864) -/* EFUSE_APB2OTP_BLOCK1_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W5_M ((EFUSE_APB2OTP_BLOCK1_W5_V)<<(EFUSE_APB2OTP_BLOCK1_W5_S)) -#define EFUSE_APB2OTP_BLOCK1_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W5_REG register + * eFuse apb2otp block1 data register5. + */ +#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864) +/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W5_M (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S) +#define EFUSE_APB2OTP_BLOCK1_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W5_S 0 -#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868) -/* EFUSE_APB2OTP_BLOCK1_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W6_M ((EFUSE_APB2OTP_BLOCK1_W6_V)<<(EFUSE_APB2OTP_BLOCK1_W6_S)) -#define EFUSE_APB2OTP_BLOCK1_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W6_REG register + * eFuse apb2otp block1 data register6. + */ +#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868) +/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W6_M (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S) +#define EFUSE_APB2OTP_BLOCK1_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W6_S 0 -#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86C) -/* EFUSE_APB2OTP_BLOCK1_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W7_M ((EFUSE_APB2OTP_BLOCK1_W7_V)<<(EFUSE_APB2OTP_BLOCK1_W7_S)) -#define EFUSE_APB2OTP_BLOCK1_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W7_REG register + * eFuse apb2otp block1 data register7. + */ +#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c) +/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W7_M (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S) +#define EFUSE_APB2OTP_BLOCK1_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W7_S 0 -#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870) -/* EFUSE_APB2OTP_BLOCK1_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W8_M ((EFUSE_APB2OTP_BLOCK1_W8_V)<<(EFUSE_APB2OTP_BLOCK1_W8_S)) -#define EFUSE_APB2OTP_BLOCK1_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W8_REG register + * eFuse apb2otp block1 data register8. + */ +#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870) +/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W8_M (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S) +#define EFUSE_APB2OTP_BLOCK1_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W8_S 0 -#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874) -/* EFUSE_APB2OTP_BLOCK1_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block1 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK1_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK1_W9_M ((EFUSE_APB2OTP_BLOCK1_W9_V)<<(EFUSE_APB2OTP_BLOCK1_W9_S)) -#define EFUSE_APB2OTP_BLOCK1_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK1_W9_REG register + * eFuse apb2otp block1 data register9. + */ +#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874) +/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK1_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK1_W9_M (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S) +#define EFUSE_APB2OTP_BLOCK1_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK1_W9_S 0 -#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878) -/* EFUSE_APB2OTP_BLOCK2_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W1_M ((EFUSE_APB2OTP_BLOCK2_W1_V)<<(EFUSE_APB2OTP_BLOCK2_W1_S)) -#define EFUSE_APB2OTP_BLOCK2_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W1_REG register + * eFuse apb2otp block2 data register1. + */ +#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878) +/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W1_M (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S) +#define EFUSE_APB2OTP_BLOCK2_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W1_S 0 -#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87C) -/* EFUSE_APB2OTP_BLOCK2_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W2_M ((EFUSE_APB2OTP_BLOCK2_W2_V)<<(EFUSE_APB2OTP_BLOCK2_W2_S)) -#define EFUSE_APB2OTP_BLOCK2_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W2_REG register + * eFuse apb2otp block2 data register2. + */ +#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c) +/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W2_M (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S) +#define EFUSE_APB2OTP_BLOCK2_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W2_S 0 -#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880) -/* EFUSE_APB2OTP_BLOCK2_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W3_M ((EFUSE_APB2OTP_BLOCK2_W3_V)<<(EFUSE_APB2OTP_BLOCK2_W3_S)) -#define EFUSE_APB2OTP_BLOCK2_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W3_REG register + * eFuse apb2otp block2 data register3. + */ +#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880) +/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W3_M (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S) +#define EFUSE_APB2OTP_BLOCK2_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W3_S 0 -#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884) -/* EFUSE_APB2OTP_BLOCK2_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W4_M ((EFUSE_APB2OTP_BLOCK2_W4_V)<<(EFUSE_APB2OTP_BLOCK2_W4_S)) -#define EFUSE_APB2OTP_BLOCK2_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W4_REG register + * eFuse apb2otp block2 data register4. + */ +#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884) +/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W4_M (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S) +#define EFUSE_APB2OTP_BLOCK2_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W4_S 0 -#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888) -/* EFUSE_APB2OTP_BLOCK2_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W5_M ((EFUSE_APB2OTP_BLOCK2_W5_V)<<(EFUSE_APB2OTP_BLOCK2_W5_S)) -#define EFUSE_APB2OTP_BLOCK2_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W5_REG register + * eFuse apb2otp block2 data register5. + */ +#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888) +/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W5_M (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S) +#define EFUSE_APB2OTP_BLOCK2_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W5_S 0 -#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88C) -/* EFUSE_APB2OTP_BLOCK2_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W6_M ((EFUSE_APB2OTP_BLOCK2_W6_V)<<(EFUSE_APB2OTP_BLOCK2_W6_S)) -#define EFUSE_APB2OTP_BLOCK2_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W6_REG register + * eFuse apb2otp block2 data register6. + */ +#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c) +/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W6_M (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S) +#define EFUSE_APB2OTP_BLOCK2_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W6_S 0 -#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890) -/* EFUSE_APB2OTP_BLOCK2_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W7_M ((EFUSE_APB2OTP_BLOCK2_W7_V)<<(EFUSE_APB2OTP_BLOCK2_W7_S)) -#define EFUSE_APB2OTP_BLOCK2_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W7_REG register + * eFuse apb2otp block2 data register7. + */ +#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890) +/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W7_M (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S) +#define EFUSE_APB2OTP_BLOCK2_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W7_S 0 -#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894) -/* EFUSE_APB2OTP_BLOCK2_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W8_M ((EFUSE_APB2OTP_BLOCK2_W8_V)<<(EFUSE_APB2OTP_BLOCK2_W8_S)) -#define EFUSE_APB2OTP_BLOCK2_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W8_REG register + * eFuse apb2otp block2 data register8. + */ +#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894) +/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W8_M (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S) +#define EFUSE_APB2OTP_BLOCK2_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W8_S 0 -#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898) -/* EFUSE_APB2OTP_BLOCK2_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W9_M ((EFUSE_APB2OTP_BLOCK2_W9_V)<<(EFUSE_APB2OTP_BLOCK2_W9_S)) -#define EFUSE_APB2OTP_BLOCK2_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W9_REG register + * eFuse apb2otp block2 data register9. + */ +#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898) +/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W9_M (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S) +#define EFUSE_APB2OTP_BLOCK2_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W9_S 0 -#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89C) -/* EFUSE_APB2OTP_BLOCK2_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W10_M ((EFUSE_APB2OTP_BLOCK2_W10_V)<<(EFUSE_APB2OTP_BLOCK2_W10_S)) -#define EFUSE_APB2OTP_BLOCK2_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W10_REG register + * eFuse apb2otp block2 data register10. + */ +#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c) +/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W10_M (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S) +#define EFUSE_APB2OTP_BLOCK2_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W10_S 0 -#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8A0) -/* EFUSE_APB2OTP_BLOCK2_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block2 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK2_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK2_W11_M ((EFUSE_APB2OTP_BLOCK2_W11_V)<<(EFUSE_APB2OTP_BLOCK2_W11_S)) -#define EFUSE_APB2OTP_BLOCK2_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK2_W11_REG register + * eFuse apb2otp block2 data register11. + */ +#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0) +/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK2_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK2_W11_M (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S) +#define EFUSE_APB2OTP_BLOCK2_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK2_W11_S 0 -#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8A4) -/* EFUSE_APB2OTP_BLOCK3_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W1_M ((EFUSE_APB2OTP_BLOCK3_W1_V)<<(EFUSE_APB2OTP_BLOCK3_W1_S)) -#define EFUSE_APB2OTP_BLOCK3_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W1_REG register + * eFuse apb2otp block3 data register1. + */ +#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4) +/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W1_M (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S) +#define EFUSE_APB2OTP_BLOCK3_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W1_S 0 -#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8A8) -/* EFUSE_APB2OTP_BLOCK3_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W2_M ((EFUSE_APB2OTP_BLOCK3_W2_V)<<(EFUSE_APB2OTP_BLOCK3_W2_S)) -#define EFUSE_APB2OTP_BLOCK3_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W2_REG register + * eFuse apb2otp block3 data register2. + */ +#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8) +/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W2_M (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S) +#define EFUSE_APB2OTP_BLOCK3_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W2_S 0 -#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8AC) -/* EFUSE_APB2OTP_BLOCK3_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W3_M ((EFUSE_APB2OTP_BLOCK3_W3_V)<<(EFUSE_APB2OTP_BLOCK3_W3_S)) -#define EFUSE_APB2OTP_BLOCK3_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W3_REG register + * eFuse apb2otp block3 data register3. + */ +#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac) +/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W3_M (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S) +#define EFUSE_APB2OTP_BLOCK3_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W3_S 0 -#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8B0) -/* EFUSE_APB2OTP_BLOCK3_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W4_M ((EFUSE_APB2OTP_BLOCK3_W4_V)<<(EFUSE_APB2OTP_BLOCK3_W4_S)) -#define EFUSE_APB2OTP_BLOCK3_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W4_REG register + * eFuse apb2otp block3 data register4. + */ +#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0) +/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W4_M (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S) +#define EFUSE_APB2OTP_BLOCK3_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W4_S 0 -#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8B4) -/* EFUSE_APB2OTP_BLOCK3_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W5_M ((EFUSE_APB2OTP_BLOCK3_W5_V)<<(EFUSE_APB2OTP_BLOCK3_W5_S)) -#define EFUSE_APB2OTP_BLOCK3_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W5_REG register + * eFuse apb2otp block3 data register5. + */ +#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4) +/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W5_M (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S) +#define EFUSE_APB2OTP_BLOCK3_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W5_S 0 -#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8B8) -/* EFUSE_APB2OTP_BLOCK3_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W6_M ((EFUSE_APB2OTP_BLOCK3_W6_V)<<(EFUSE_APB2OTP_BLOCK3_W6_S)) -#define EFUSE_APB2OTP_BLOCK3_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W6_REG register + * eFuse apb2otp block3 data register6. + */ +#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8) +/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W6_M (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S) +#define EFUSE_APB2OTP_BLOCK3_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W6_S 0 -#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8BC) -/* EFUSE_APB2OTP_BLOCK3_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W7_M ((EFUSE_APB2OTP_BLOCK3_W7_V)<<(EFUSE_APB2OTP_BLOCK3_W7_S)) -#define EFUSE_APB2OTP_BLOCK3_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W7_REG register + * eFuse apb2otp block3 data register7. + */ +#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc) +/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W7_M (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S) +#define EFUSE_APB2OTP_BLOCK3_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W7_S 0 -#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8C0) -/* EFUSE_APB2OTP_BLOCK3_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W8_M ((EFUSE_APB2OTP_BLOCK3_W8_V)<<(EFUSE_APB2OTP_BLOCK3_W8_S)) -#define EFUSE_APB2OTP_BLOCK3_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W8_REG register + * eFuse apb2otp block3 data register8. + */ +#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0) +/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W8_M (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S) +#define EFUSE_APB2OTP_BLOCK3_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W8_S 0 -#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8C4) -/* EFUSE_APB2OTP_BLOCK3_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W9_M ((EFUSE_APB2OTP_BLOCK3_W9_V)<<(EFUSE_APB2OTP_BLOCK3_W9_S)) -#define EFUSE_APB2OTP_BLOCK3_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W9_REG register + * eFuse apb2otp block3 data register9. + */ +#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4) +/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W9_M (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S) +#define EFUSE_APB2OTP_BLOCK3_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W9_S 0 -#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8C8) -/* EFUSE_APB2OTP_BLOCK3_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W10_M ((EFUSE_APB2OTP_BLOCK3_W10_V)<<(EFUSE_APB2OTP_BLOCK3_W10_S)) -#define EFUSE_APB2OTP_BLOCK3_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W10_REG register + * eFuse apb2otp block3 data register10. + */ +#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8) +/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W10_M (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S) +#define EFUSE_APB2OTP_BLOCK3_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W10_S 0 -#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8CC) -/* EFUSE_APB2OTP_BLOCK3_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block3 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK3_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK3_W11_M ((EFUSE_APB2OTP_BLOCK3_W11_V)<<(EFUSE_APB2OTP_BLOCK3_W11_S)) -#define EFUSE_APB2OTP_BLOCK3_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK3_W11_REG register + * eFuse apb2otp block3 data register11. + */ +#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc) +/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK3_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK3_W11_M (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S) +#define EFUSE_APB2OTP_BLOCK3_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK3_W11_S 0 -#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8D0) -/* EFUSE_APB2OTP_BLOCK4_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W1_M ((EFUSE_APB2OTP_BLOCK4_W1_V)<<(EFUSE_APB2OTP_BLOCK4_W1_S)) -#define EFUSE_APB2OTP_BLOCK4_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W1_REG register + * eFuse apb2otp block4 data register1. + */ +#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0) +/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W1_M (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S) +#define EFUSE_APB2OTP_BLOCK4_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W1_S 0 -#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8D4) -/* EFUSE_APB2OTP_BLOCK4_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W2_M ((EFUSE_APB2OTP_BLOCK4_W2_V)<<(EFUSE_APB2OTP_BLOCK4_W2_S)) -#define EFUSE_APB2OTP_BLOCK4_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W2_REG register + * eFuse apb2otp block4 data register2. + */ +#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4) +/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W2_M (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S) +#define EFUSE_APB2OTP_BLOCK4_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W2_S 0 -#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8D8) -/* EFUSE_APB2OTP_BLOCK4_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W3_M ((EFUSE_APB2OTP_BLOCK4_W3_V)<<(EFUSE_APB2OTP_BLOCK4_W3_S)) -#define EFUSE_APB2OTP_BLOCK4_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W3_REG register + * eFuse apb2otp block4 data register3. + */ +#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8) +/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W3_M (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S) +#define EFUSE_APB2OTP_BLOCK4_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W3_S 0 -#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8DC) -/* EFUSE_APB2OTP_BLOCK4_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W4_M ((EFUSE_APB2OTP_BLOCK4_W4_V)<<(EFUSE_APB2OTP_BLOCK4_W4_S)) -#define EFUSE_APB2OTP_BLOCK4_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W4_REG register + * eFuse apb2otp block4 data register4. + */ +#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc) +/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W4_M (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S) +#define EFUSE_APB2OTP_BLOCK4_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W4_S 0 -#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8E0) -/* EFUSE_APB2OTP_BLOCK4_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W5_M ((EFUSE_APB2OTP_BLOCK4_W5_V)<<(EFUSE_APB2OTP_BLOCK4_W5_S)) -#define EFUSE_APB2OTP_BLOCK4_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W5_REG register + * eFuse apb2otp block4 data register5. + */ +#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0) +/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W5_M (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S) +#define EFUSE_APB2OTP_BLOCK4_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W5_S 0 -#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8E4) -/* EFUSE_APB2OTP_BLOCK4_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W6_M ((EFUSE_APB2OTP_BLOCK4_W6_V)<<(EFUSE_APB2OTP_BLOCK4_W6_S)) -#define EFUSE_APB2OTP_BLOCK4_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W6_REG register + * eFuse apb2otp block4 data register6. + */ +#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4) +/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W6_M (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S) +#define EFUSE_APB2OTP_BLOCK4_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W6_S 0 -#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8E8) -/* EFUSE_APB2OTP_BLOCK4_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W7_M ((EFUSE_APB2OTP_BLOCK4_W7_V)<<(EFUSE_APB2OTP_BLOCK4_W7_S)) -#define EFUSE_APB2OTP_BLOCK4_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W7_REG register + * eFuse apb2otp block4 data register7. + */ +#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8) +/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W7_M (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S) +#define EFUSE_APB2OTP_BLOCK4_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W7_S 0 -#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8EC) -/* EFUSE_APB2OTP_BLOCK4_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W8_M ((EFUSE_APB2OTP_BLOCK4_W8_V)<<(EFUSE_APB2OTP_BLOCK4_W8_S)) -#define EFUSE_APB2OTP_BLOCK4_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W8_REG register + * eFuse apb2otp block4 data register8. + */ +#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec) +/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W8_M (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S) +#define EFUSE_APB2OTP_BLOCK4_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W8_S 0 -#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8F0) -/* EFUSE_APB2OTP_BLOCK4_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W9_M ((EFUSE_APB2OTP_BLOCK4_W9_V)<<(EFUSE_APB2OTP_BLOCK4_W9_S)) -#define EFUSE_APB2OTP_BLOCK4_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W9_REG register + * eFuse apb2otp block4 data register9. + */ +#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0) +/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W9_M (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S) +#define EFUSE_APB2OTP_BLOCK4_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W9_S 0 -#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8F4) -/* EFUSE_APB2OTP_BLOCK4_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W10_M ((EFUSE_APB2OTP_BLOCK4_W10_V)<<(EFUSE_APB2OTP_BLOCK4_W10_S)) -#define EFUSE_APB2OTP_BLOCK4_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W10_REG register + * eFuse apb2otp block4 data registe10. + */ +#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4) +/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W10_M (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S) +#define EFUSE_APB2OTP_BLOCK4_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W10_S 0 -#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8F8) -/* EFUSE_APB2OTP_BLOCK4_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block4 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK4_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK4_W11_M ((EFUSE_APB2OTP_BLOCK4_W11_V)<<(EFUSE_APB2OTP_BLOCK4_W11_S)) -#define EFUSE_APB2OTP_BLOCK4_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK4_W11_REG register + * eFuse apb2otp block4 data register11. + */ +#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8) +/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK4_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK4_W11_M (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S) +#define EFUSE_APB2OTP_BLOCK4_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK4_W11_S 0 -#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8FC) -/* EFUSE_APB2OTP_BLOCK5_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W1_M ((EFUSE_APB2OTP_BLOCK5_W1_V)<<(EFUSE_APB2OTP_BLOCK5_W1_S)) -#define EFUSE_APB2OTP_BLOCK5_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W1_REG register + * eFuse apb2otp block5 data register1. + */ +#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc) +/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W1_M (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S) +#define EFUSE_APB2OTP_BLOCK5_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W1_S 0 -#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900) -/* EFUSE_APB2OTP_BLOCK5_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W2_M ((EFUSE_APB2OTP_BLOCK5_W2_V)<<(EFUSE_APB2OTP_BLOCK5_W2_S)) -#define EFUSE_APB2OTP_BLOCK5_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W2_REG register + * eFuse apb2otp block5 data register2. + */ +#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900) +/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W2_M (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S) +#define EFUSE_APB2OTP_BLOCK5_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W2_S 0 -#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904) -/* EFUSE_APB2OTP_BLOCK5_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W3_M ((EFUSE_APB2OTP_BLOCK5_W3_V)<<(EFUSE_APB2OTP_BLOCK5_W3_S)) -#define EFUSE_APB2OTP_BLOCK5_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W3_REG register + * eFuse apb2otp block5 data register3. + */ +#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904) +/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W3_M (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S) +#define EFUSE_APB2OTP_BLOCK5_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W3_S 0 -#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908) -/* EFUSE_APB2OTP_BLOCK5_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W4_M ((EFUSE_APB2OTP_BLOCK5_W4_V)<<(EFUSE_APB2OTP_BLOCK5_W4_S)) -#define EFUSE_APB2OTP_BLOCK5_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W4_REG register + * eFuse apb2otp block5 data register4. + */ +#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908) +/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W4_M (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S) +#define EFUSE_APB2OTP_BLOCK5_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W4_S 0 -#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90C) -/* EFUSE_APB2OTP_BLOCK5_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W5_M ((EFUSE_APB2OTP_BLOCK5_W5_V)<<(EFUSE_APB2OTP_BLOCK5_W5_S)) -#define EFUSE_APB2OTP_BLOCK5_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W5_REG register + * eFuse apb2otp block5 data register5. + */ +#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c) +/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W5_M (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S) +#define EFUSE_APB2OTP_BLOCK5_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W5_S 0 -#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910) -/* EFUSE_APB2OTP_BLOCK5_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W6_M ((EFUSE_APB2OTP_BLOCK5_W6_V)<<(EFUSE_APB2OTP_BLOCK5_W6_S)) -#define EFUSE_APB2OTP_BLOCK5_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W6_REG register + * eFuse apb2otp block5 data register6. + */ +#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910) +/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W6_M (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S) +#define EFUSE_APB2OTP_BLOCK5_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W6_S 0 -#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914) -/* EFUSE_APB2OTP_BLOCK5_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W7_M ((EFUSE_APB2OTP_BLOCK5_W7_V)<<(EFUSE_APB2OTP_BLOCK5_W7_S)) -#define EFUSE_APB2OTP_BLOCK5_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W7_REG register + * eFuse apb2otp block5 data register7. + */ +#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914) +/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W7_M (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S) +#define EFUSE_APB2OTP_BLOCK5_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W7_S 0 -#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918) -/* EFUSE_APB2OTP_BLOCK5_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W8_M ((EFUSE_APB2OTP_BLOCK5_W8_V)<<(EFUSE_APB2OTP_BLOCK5_W8_S)) -#define EFUSE_APB2OTP_BLOCK5_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W8_REG register + * eFuse apb2otp block5 data register8. + */ +#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918) +/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W8_M (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S) +#define EFUSE_APB2OTP_BLOCK5_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W8_S 0 -#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91C) -/* EFUSE_APB2OTP_BLOCK5_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W9_M ((EFUSE_APB2OTP_BLOCK5_W9_V)<<(EFUSE_APB2OTP_BLOCK5_W9_S)) -#define EFUSE_APB2OTP_BLOCK5_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W9_REG register + * eFuse apb2otp block5 data register9. + */ +#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c) +/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W9_M (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S) +#define EFUSE_APB2OTP_BLOCK5_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W9_S 0 -#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920) -/* EFUSE_APB2OTP_BLOCK5_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W10_M ((EFUSE_APB2OTP_BLOCK5_W10_V)<<(EFUSE_APB2OTP_BLOCK5_W10_S)) -#define EFUSE_APB2OTP_BLOCK5_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W10_REG register + * eFuse apb2otp block5 data register10. + */ +#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920) +/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W10_M (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S) +#define EFUSE_APB2OTP_BLOCK5_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W10_S 0 -#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924) -/* EFUSE_APB2OTP_BLOCK5_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block5 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK5_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK5_W11_M ((EFUSE_APB2OTP_BLOCK5_W11_V)<<(EFUSE_APB2OTP_BLOCK5_W11_S)) -#define EFUSE_APB2OTP_BLOCK5_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK5_W11_REG register + * eFuse apb2otp block5 data register11. + */ +#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924) +/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK5_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK5_W11_M (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S) +#define EFUSE_APB2OTP_BLOCK5_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK5_W11_S 0 -#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928) -/* EFUSE_APB2OTP_BLOCK6_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W1_M ((EFUSE_APB2OTP_BLOCK6_W1_V)<<(EFUSE_APB2OTP_BLOCK6_W1_S)) -#define EFUSE_APB2OTP_BLOCK6_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W1_REG register + * eFuse apb2otp block6 data register1. + */ +#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928) +/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W1_M (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S) +#define EFUSE_APB2OTP_BLOCK6_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W1_S 0 -#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92C) -/* EFUSE_APB2OTP_BLOCK6_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W2_M ((EFUSE_APB2OTP_BLOCK6_W2_V)<<(EFUSE_APB2OTP_BLOCK6_W2_S)) -#define EFUSE_APB2OTP_BLOCK6_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W2_REG register + * eFuse apb2otp block6 data register2. + */ +#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c) +/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W2_M (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S) +#define EFUSE_APB2OTP_BLOCK6_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W2_S 0 -#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930) -/* EFUSE_APB2OTP_BLOCK6_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W3_M ((EFUSE_APB2OTP_BLOCK6_W3_V)<<(EFUSE_APB2OTP_BLOCK6_W3_S)) -#define EFUSE_APB2OTP_BLOCK6_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W3_REG register + * eFuse apb2otp block6 data register3. + */ +#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930) +/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W3_M (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S) +#define EFUSE_APB2OTP_BLOCK6_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W3_S 0 -#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934) -/* EFUSE_APB2OTP_BLOCK6_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W4_M ((EFUSE_APB2OTP_BLOCK6_W4_V)<<(EFUSE_APB2OTP_BLOCK6_W4_S)) -#define EFUSE_APB2OTP_BLOCK6_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W4_REG register + * eFuse apb2otp block6 data register4. + */ +#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934) +/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W4_M (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S) +#define EFUSE_APB2OTP_BLOCK6_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W4_S 0 -#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938) -/* EFUSE_APB2OTP_BLOCK6_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W5_M ((EFUSE_APB2OTP_BLOCK6_W5_V)<<(EFUSE_APB2OTP_BLOCK6_W5_S)) -#define EFUSE_APB2OTP_BLOCK6_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W5_REG register + * eFuse apb2otp block6 data register5. + */ +#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938) +/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W5_M (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S) +#define EFUSE_APB2OTP_BLOCK6_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W5_S 0 -#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93C) -/* EFUSE_APB2OTP_BLOCK6_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W6_M ((EFUSE_APB2OTP_BLOCK6_W6_V)<<(EFUSE_APB2OTP_BLOCK6_W6_S)) -#define EFUSE_APB2OTP_BLOCK6_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W6_REG register + * eFuse apb2otp block6 data register6. + */ +#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c) +/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W6_M (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S) +#define EFUSE_APB2OTP_BLOCK6_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W6_S 0 -#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940) -/* EFUSE_APB2OTP_BLOCK6_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W7_M ((EFUSE_APB2OTP_BLOCK6_W7_V)<<(EFUSE_APB2OTP_BLOCK6_W7_S)) -#define EFUSE_APB2OTP_BLOCK6_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W7_REG register + * eFuse apb2otp block6 data register7. + */ +#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940) +/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W7_M (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S) +#define EFUSE_APB2OTP_BLOCK6_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W7_S 0 -#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944) -/* EFUSE_APB2OTP_BLOCK6_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W8_M ((EFUSE_APB2OTP_BLOCK6_W8_V)<<(EFUSE_APB2OTP_BLOCK6_W8_S)) -#define EFUSE_APB2OTP_BLOCK6_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W8_REG register + * eFuse apb2otp block6 data register8. + */ +#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944) +/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W8_M (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S) +#define EFUSE_APB2OTP_BLOCK6_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W8_S 0 -#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948) -/* EFUSE_APB2OTP_BLOCK6_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W9_M ((EFUSE_APB2OTP_BLOCK6_W9_V)<<(EFUSE_APB2OTP_BLOCK6_W9_S)) -#define EFUSE_APB2OTP_BLOCK6_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W9_REG register + * eFuse apb2otp block6 data register9. + */ +#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948) +/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W9_M (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S) +#define EFUSE_APB2OTP_BLOCK6_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W9_S 0 -#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94C) -/* EFUSE_APB2OTP_BLOCK6_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W10_M ((EFUSE_APB2OTP_BLOCK6_W10_V)<<(EFUSE_APB2OTP_BLOCK6_W10_S)) -#define EFUSE_APB2OTP_BLOCK6_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W10_REG register + * eFuse apb2otp block6 data register10. + */ +#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c) +/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W10_M (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S) +#define EFUSE_APB2OTP_BLOCK6_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W10_S 0 -#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950) -/* EFUSE_APB2OTP_BLOCK6_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block6 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK6_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK6_W11_M ((EFUSE_APB2OTP_BLOCK6_W11_V)<<(EFUSE_APB2OTP_BLOCK6_W11_S)) -#define EFUSE_APB2OTP_BLOCK6_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK6_W11_REG register + * eFuse apb2otp block6 data register11. + */ +#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950) +/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK6_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK6_W11_M (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S) +#define EFUSE_APB2OTP_BLOCK6_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK6_W11_S 0 -#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954) -/* EFUSE_APB2OTP_BLOCK7_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W1_M ((EFUSE_APB2OTP_BLOCK7_W1_V)<<(EFUSE_APB2OTP_BLOCK7_W1_S)) -#define EFUSE_APB2OTP_BLOCK7_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W1_REG register + * eFuse apb2otp block7 data register1. + */ +#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954) +/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W1_M (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S) +#define EFUSE_APB2OTP_BLOCK7_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W1_S 0 -#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958) -/* EFUSE_APB2OTP_BLOCK7_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W2_M ((EFUSE_APB2OTP_BLOCK7_W2_V)<<(EFUSE_APB2OTP_BLOCK7_W2_S)) -#define EFUSE_APB2OTP_BLOCK7_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W2_REG register + * eFuse apb2otp block7 data register2. + */ +#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958) +/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W2_M (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S) +#define EFUSE_APB2OTP_BLOCK7_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W2_S 0 -#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95C) -/* EFUSE_APB2OTP_BLOCK7_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W3_M ((EFUSE_APB2OTP_BLOCK7_W3_V)<<(EFUSE_APB2OTP_BLOCK7_W3_S)) -#define EFUSE_APB2OTP_BLOCK7_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W3_REG register + * eFuse apb2otp block7 data register3. + */ +#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c) +/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W3_M (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S) +#define EFUSE_APB2OTP_BLOCK7_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W3_S 0 -#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960) -/* EFUSE_APB2OTP_BLOCK7_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W4_M ((EFUSE_APB2OTP_BLOCK7_W4_V)<<(EFUSE_APB2OTP_BLOCK7_W4_S)) -#define EFUSE_APB2OTP_BLOCK7_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W4_REG register + * eFuse apb2otp block7 data register4. + */ +#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960) +/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W4_M (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S) +#define EFUSE_APB2OTP_BLOCK7_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W4_S 0 -#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964) -/* EFUSE_APB2OTP_BLOCK7_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W5_M ((EFUSE_APB2OTP_BLOCK7_W5_V)<<(EFUSE_APB2OTP_BLOCK7_W5_S)) -#define EFUSE_APB2OTP_BLOCK7_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W5_REG register + * eFuse apb2otp block7 data register5. + */ +#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964) +/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W5_M (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S) +#define EFUSE_APB2OTP_BLOCK7_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W5_S 0 -#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968) -/* EFUSE_APB2OTP_BLOCK7_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W6_M ((EFUSE_APB2OTP_BLOCK7_W6_V)<<(EFUSE_APB2OTP_BLOCK7_W6_S)) -#define EFUSE_APB2OTP_BLOCK7_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W6_REG register + * eFuse apb2otp block7 data register6. + */ +#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968) +/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W6_M (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S) +#define EFUSE_APB2OTP_BLOCK7_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W6_S 0 -#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96C) -/* EFUSE_APB2OTP_BLOCK7_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W7_M ((EFUSE_APB2OTP_BLOCK7_W7_V)<<(EFUSE_APB2OTP_BLOCK7_W7_S)) -#define EFUSE_APB2OTP_BLOCK7_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W7_REG register + * eFuse apb2otp block7 data register7. + */ +#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c) +/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W7_M (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S) +#define EFUSE_APB2OTP_BLOCK7_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W7_S 0 -#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970) -/* EFUSE_APB2OTP_BLOCK7_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W8_M ((EFUSE_APB2OTP_BLOCK7_W8_V)<<(EFUSE_APB2OTP_BLOCK7_W8_S)) -#define EFUSE_APB2OTP_BLOCK7_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W8_REG register + * eFuse apb2otp block7 data register8. + */ +#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970) +/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W8_M (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S) +#define EFUSE_APB2OTP_BLOCK7_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W8_S 0 -#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974) -/* EFUSE_APB2OTP_BLOCK7_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W9_M ((EFUSE_APB2OTP_BLOCK7_W9_V)<<(EFUSE_APB2OTP_BLOCK7_W9_S)) -#define EFUSE_APB2OTP_BLOCK7_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W9_REG register + * eFuse apb2otp block7 data register9. + */ +#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974) +/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W9_M (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S) +#define EFUSE_APB2OTP_BLOCK7_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W9_S 0 -#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978) -/* EFUSE_APB2OTP_BLOCK7_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W10_M ((EFUSE_APB2OTP_BLOCK7_W10_V)<<(EFUSE_APB2OTP_BLOCK7_W10_S)) -#define EFUSE_APB2OTP_BLOCK7_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W10_REG register + * eFuse apb2otp block7 data register10. + */ +#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978) +/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W10_M (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S) +#define EFUSE_APB2OTP_BLOCK7_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W10_S 0 -#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97C) -/* EFUSE_APB2OTP_BLOCK7_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block7 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK7_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK7_W11_M ((EFUSE_APB2OTP_BLOCK7_W11_V)<<(EFUSE_APB2OTP_BLOCK7_W11_S)) -#define EFUSE_APB2OTP_BLOCK7_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK7_W11_REG register + * eFuse apb2otp block7 data register11. + */ +#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c) +/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK7_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK7_W11_M (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S) +#define EFUSE_APB2OTP_BLOCK7_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK7_W11_S 0 -#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980) -/* EFUSE_APB2OTP_BLOCK8_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W1_M ((EFUSE_APB2OTP_BLOCK8_W1_V)<<(EFUSE_APB2OTP_BLOCK8_W1_S)) -#define EFUSE_APB2OTP_BLOCK8_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W1_REG register + * eFuse apb2otp block8 data register1. + */ +#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980) +/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W1_M (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S) +#define EFUSE_APB2OTP_BLOCK8_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W1_S 0 -#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984) -/* EFUSE_APB2OTP_BLOCK8_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W2_M ((EFUSE_APB2OTP_BLOCK8_W2_V)<<(EFUSE_APB2OTP_BLOCK8_W2_S)) -#define EFUSE_APB2OTP_BLOCK8_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W2_REG register + * eFuse apb2otp block8 data register2. + */ +#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984) +/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W2_M (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S) +#define EFUSE_APB2OTP_BLOCK8_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W2_S 0 -#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988) -/* EFUSE_APB2OTP_BLOCK8_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W3_M ((EFUSE_APB2OTP_BLOCK8_W3_V)<<(EFUSE_APB2OTP_BLOCK8_W3_S)) -#define EFUSE_APB2OTP_BLOCK8_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W3_REG register + * eFuse apb2otp block8 data register3. + */ +#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988) +/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W3_M (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S) +#define EFUSE_APB2OTP_BLOCK8_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W3_S 0 -#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98C) -/* EFUSE_APB2OTP_BLOCK8_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W4_M ((EFUSE_APB2OTP_BLOCK8_W4_V)<<(EFUSE_APB2OTP_BLOCK8_W4_S)) -#define EFUSE_APB2OTP_BLOCK8_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W4_REG register + * eFuse apb2otp block8 data register4. + */ +#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c) +/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W4_M (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S) +#define EFUSE_APB2OTP_BLOCK8_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W4_S 0 -#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990) -/* EFUSE_APB2OTP_BLOCK8_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W5_M ((EFUSE_APB2OTP_BLOCK8_W5_V)<<(EFUSE_APB2OTP_BLOCK8_W5_S)) -#define EFUSE_APB2OTP_BLOCK8_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W5_REG register + * eFuse apb2otp block8 data register5. + */ +#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990) +/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W5_M (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S) +#define EFUSE_APB2OTP_BLOCK8_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W5_S 0 -#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994) -/* EFUSE_APB2OTP_BLOCK8_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W6_M ((EFUSE_APB2OTP_BLOCK8_W6_V)<<(EFUSE_APB2OTP_BLOCK8_W6_S)) -#define EFUSE_APB2OTP_BLOCK8_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W6_REG register + * eFuse apb2otp block8 data register6. + */ +#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994) +/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W6_M (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S) +#define EFUSE_APB2OTP_BLOCK8_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W6_S 0 -#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998) -/* EFUSE_APB2OTP_BLOCK8_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W7_M ((EFUSE_APB2OTP_BLOCK8_W7_V)<<(EFUSE_APB2OTP_BLOCK8_W7_S)) -#define EFUSE_APB2OTP_BLOCK8_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W7_REG register + * eFuse apb2otp block8 data register7. + */ +#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998) +/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W7_M (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S) +#define EFUSE_APB2OTP_BLOCK8_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W7_S 0 -#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99C) -/* EFUSE_APB2OTP_BLOCK8_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W8_M ((EFUSE_APB2OTP_BLOCK8_W8_V)<<(EFUSE_APB2OTP_BLOCK8_W8_S)) -#define EFUSE_APB2OTP_BLOCK8_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W8_REG register + * eFuse apb2otp block8 data register8. + */ +#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c) +/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W8_M (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S) +#define EFUSE_APB2OTP_BLOCK8_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W8_S 0 -#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9A0) -/* EFUSE_APB2OTP_BLOCK8_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W9_M ((EFUSE_APB2OTP_BLOCK8_W9_V)<<(EFUSE_APB2OTP_BLOCK8_W9_S)) -#define EFUSE_APB2OTP_BLOCK8_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W9_REG register + * eFuse apb2otp block8 data register9. + */ +#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0) +/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W9_M (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S) +#define EFUSE_APB2OTP_BLOCK8_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W9_S 0 -#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9A4) -/* EFUSE_APB2OTP_BLOCK8_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W10_M ((EFUSE_APB2OTP_BLOCK8_W10_V)<<(EFUSE_APB2OTP_BLOCK8_W10_S)) -#define EFUSE_APB2OTP_BLOCK8_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W10_REG register + * eFuse apb2otp block8 data register10. + */ +#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4) +/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W10_M (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S) +#define EFUSE_APB2OTP_BLOCK8_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W10_S 0 -#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9A8) -/* EFUSE_APB2OTP_BLOCK8_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block8 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK8_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK8_W11_M ((EFUSE_APB2OTP_BLOCK8_W11_V)<<(EFUSE_APB2OTP_BLOCK8_W11_S)) -#define EFUSE_APB2OTP_BLOCK8_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK8_W11_REG register + * eFuse apb2otp block8 data register11. + */ +#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8) +/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK8_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK8_W11_M (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S) +#define EFUSE_APB2OTP_BLOCK8_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK8_W11_S 0 -#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9AC) -/* EFUSE_APB2OTP_BLOCK9_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W1_M ((EFUSE_APB2OTP_BLOCK9_W1_V)<<(EFUSE_APB2OTP_BLOCK9_W1_S)) -#define EFUSE_APB2OTP_BLOCK9_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W1_REG register + * eFuse apb2otp block9 data register1. + */ +#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac) +/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W1_M (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S) +#define EFUSE_APB2OTP_BLOCK9_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W1_S 0 -#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9B0) -/* EFUSE_APB2OTP_BLOCK9_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W2_M ((EFUSE_APB2OTP_BLOCK9_W2_V)<<(EFUSE_APB2OTP_BLOCK9_W2_S)) -#define EFUSE_APB2OTP_BLOCK9_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W2_REG register + * eFuse apb2otp block9 data register2. + */ +#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0) +/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W2_M (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S) +#define EFUSE_APB2OTP_BLOCK9_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W2_S 0 -#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9B4) -/* EFUSE_APB2OTP_BLOCK9_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W3_M ((EFUSE_APB2OTP_BLOCK9_W3_V)<<(EFUSE_APB2OTP_BLOCK9_W3_S)) -#define EFUSE_APB2OTP_BLOCK9_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W3_REG register + * eFuse apb2otp block9 data register3. + */ +#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4) +/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W3_M (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S) +#define EFUSE_APB2OTP_BLOCK9_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W3_S 0 -#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9B8) -/* EFUSE_APB2OTP_BLOCK9_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W4_M ((EFUSE_APB2OTP_BLOCK9_W4_V)<<(EFUSE_APB2OTP_BLOCK9_W4_S)) -#define EFUSE_APB2OTP_BLOCK9_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W4_REG register + * eFuse apb2otp block9 data register4. + */ +#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8) +/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W4_M (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S) +#define EFUSE_APB2OTP_BLOCK9_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W4_S 0 -#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9BC) -/* EFUSE_APB2OTP_BLOCK9_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W5_M ((EFUSE_APB2OTP_BLOCK9_W5_V)<<(EFUSE_APB2OTP_BLOCK9_W5_S)) -#define EFUSE_APB2OTP_BLOCK9_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W5_REG register + * eFuse apb2otp block9 data register5. + */ +#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc) +/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W5_M (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S) +#define EFUSE_APB2OTP_BLOCK9_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W5_S 0 -#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9C0) -/* EFUSE_APB2OTP_BLOCK9_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W6_M ((EFUSE_APB2OTP_BLOCK9_W6_V)<<(EFUSE_APB2OTP_BLOCK9_W6_S)) -#define EFUSE_APB2OTP_BLOCK9_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W6_REG register + * eFuse apb2otp block9 data register6. + */ +#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0) +/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W6_M (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S) +#define EFUSE_APB2OTP_BLOCK9_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W6_S 0 -#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9C4) -/* EFUSE_APB2OTP_BLOCK9_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W7_M ((EFUSE_APB2OTP_BLOCK9_W7_V)<<(EFUSE_APB2OTP_BLOCK9_W7_S)) -#define EFUSE_APB2OTP_BLOCK9_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W7_REG register + * eFuse apb2otp block9 data register7. + */ +#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4) +/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W7_M (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S) +#define EFUSE_APB2OTP_BLOCK9_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W7_S 0 -#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9C8) -/* EFUSE_APB2OTP_BLOCK9_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W8_M ((EFUSE_APB2OTP_BLOCK9_W8_V)<<(EFUSE_APB2OTP_BLOCK9_W8_S)) -#define EFUSE_APB2OTP_BLOCK9_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W8_REG register + * eFuse apb2otp block9 data register8. + */ +#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8) +/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W8_M (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S) +#define EFUSE_APB2OTP_BLOCK9_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W8_S 0 -#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9CC) -/* EFUSE_APB2OTP_BLOCK9_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W9_M ((EFUSE_APB2OTP_BLOCK9_W9_V)<<(EFUSE_APB2OTP_BLOCK9_W9_S)) -#define EFUSE_APB2OTP_BLOCK9_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W9_REG register + * eFuse apb2otp block9 data register9. + */ +#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc) +/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W9_M (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S) +#define EFUSE_APB2OTP_BLOCK9_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W9_S 0 -#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9D0) -/* EFUSE_APB2OTP_BLOCK9_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W10_M ((EFUSE_APB2OTP_BLOCK9_W10_V)<<(EFUSE_APB2OTP_BLOCK9_W10_S)) -#define EFUSE_APB2OTP_BLOCK9_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W10_REG register + * eFuse apb2otp block9 data register10. + */ +#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0) +/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W10_M (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S) +#define EFUSE_APB2OTP_BLOCK9_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W10_S 0 -#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9D4) -/* EFUSE_APB2OTP_BLOCK9_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block9 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK9_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK9_W11_M ((EFUSE_APB2OTP_BLOCK9_W11_V)<<(EFUSE_APB2OTP_BLOCK9_W11_S)) -#define EFUSE_APB2OTP_BLOCK9_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK9_W11_REG register + * eFuse apb2otp block9 data register11. + */ +#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4) +/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK9_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK9_W11_M (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S) +#define EFUSE_APB2OTP_BLOCK9_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK9_W11_S 0 -#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9D8) -/* EFUSE_APB2OTP_BLOCK10_W1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word1 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W1 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W1_M ((EFUSE_APB2OTP_BLOCK10_W1_V)<<(EFUSE_APB2OTP_BLOCK10_W1_S)) -#define EFUSE_APB2OTP_BLOCK10_W1_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W1_REG register + * eFuse apb2otp block10 data register1. + */ +#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8) +/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W1 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W1_M (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S) +#define EFUSE_APB2OTP_BLOCK10_W1_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W1_S 0 -#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9DC) -/* EFUSE_APB2OTP_BLOCK10_W2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word2 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W2 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W2_M ((EFUSE_APB2OTP_BLOCK10_W2_V)<<(EFUSE_APB2OTP_BLOCK10_W2_S)) -#define EFUSE_APB2OTP_BLOCK10_W2_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W2_REG register + * eFuse apb2otp block10 data register2. + */ +#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc) +/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W2 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W2_M (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S) +#define EFUSE_APB2OTP_BLOCK10_W2_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W2_S 0 -#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9E0) -/* EFUSE_APB2OTP_BLOCK10_W3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word3 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W3 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W3_M ((EFUSE_APB2OTP_BLOCK10_W3_V)<<(EFUSE_APB2OTP_BLOCK10_W3_S)) -#define EFUSE_APB2OTP_BLOCK10_W3_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W3_REG register + * eFuse apb2otp block10 data register3. + */ +#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0) +/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W3 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W3_M (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S) +#define EFUSE_APB2OTP_BLOCK10_W3_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W3_S 0 -#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9E4) -/* EFUSE_APB2OTP_BLOCK10_W4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word4 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W4 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W4_M ((EFUSE_APB2OTP_BLOCK10_W4_V)<<(EFUSE_APB2OTP_BLOCK10_W4_S)) -#define EFUSE_APB2OTP_BLOCK10_W4_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W4_REG register + * eFuse apb2otp block10 data register4. + */ +#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4) +/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W4 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W4_M (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S) +#define EFUSE_APB2OTP_BLOCK10_W4_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W4_S 0 -#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9E8) -/* EFUSE_APB2OTP_BLOCK10_W5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word5 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W5 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W5_M ((EFUSE_APB2OTP_BLOCK10_W5_V)<<(EFUSE_APB2OTP_BLOCK10_W5_S)) -#define EFUSE_APB2OTP_BLOCK10_W5_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W5_REG register + * eFuse apb2otp block10 data register5. + */ +#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8) +/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W5 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W5_M (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S) +#define EFUSE_APB2OTP_BLOCK10_W5_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W5_S 0 -#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9EC) -/* EFUSE_APB2OTP_BLOCK10_W6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word6 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W6 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W6_M ((EFUSE_APB2OTP_BLOCK10_W6_V)<<(EFUSE_APB2OTP_BLOCK10_W6_S)) -#define EFUSE_APB2OTP_BLOCK10_W6_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W6_REG register + * eFuse apb2otp block10 data register6. + */ +#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec) +/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W6 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W6_M (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S) +#define EFUSE_APB2OTP_BLOCK10_W6_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W6_S 0 -#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9F0) -/* EFUSE_APB2OTP_BLOCK10_W7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word7 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W7 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W7_M ((EFUSE_APB2OTP_BLOCK10_W7_V)<<(EFUSE_APB2OTP_BLOCK10_W7_S)) -#define EFUSE_APB2OTP_BLOCK10_W7_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W7_REG register + * eFuse apb2otp block10 data register7. + */ +#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0) +/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W7 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W7_M (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S) +#define EFUSE_APB2OTP_BLOCK10_W7_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W7_S 0 -#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9F4) -/* EFUSE_APB2OTP_BLOCK10_W8 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word8 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W8 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W8_M ((EFUSE_APB2OTP_BLOCK10_W8_V)<<(EFUSE_APB2OTP_BLOCK10_W8_S)) -#define EFUSE_APB2OTP_BLOCK10_W8_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W8_REG register + * eFuse apb2otp block10 data register8. + */ +#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4) +/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W8 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W8_M (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S) +#define EFUSE_APB2OTP_BLOCK10_W8_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W8_S 0 -#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9F8) -/* EFUSE_APB2OTP_BLOCK10_W9 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word9 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W9 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W9_M ((EFUSE_APB2OTP_BLOCK10_W9_V)<<(EFUSE_APB2OTP_BLOCK10_W9_S)) -#define EFUSE_APB2OTP_BLOCK10_W9_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W9_REG register + * eFuse apb2otp block10 data register9. + */ +#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8) +/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W9 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W9_M (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S) +#define EFUSE_APB2OTP_BLOCK10_W9_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W9_S 0 -#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9FC) -/* EFUSE_APB2OTP_BLOCK19_W10 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word10 data..*/ -#define EFUSE_APB2OTP_BLOCK19_W10 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK19_W10_M ((EFUSE_APB2OTP_BLOCK19_W10_V)<<(EFUSE_APB2OTP_BLOCK19_W10_S)) -#define EFUSE_APB2OTP_BLOCK19_W10_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W10_REG register + * eFuse apb2otp block10 data register10. + */ +#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc) +/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ +#define EFUSE_APB2OTP_BLOCK19_W10 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK19_W10_M (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S) +#define EFUSE_APB2OTP_BLOCK19_W10_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK19_W10_S 0 -#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xA00) -/* EFUSE_APB2OTP_BLOCK10_W11 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Otp block10 word11 data..*/ -#define EFUSE_APB2OTP_BLOCK10_W11 0xFFFFFFFF -#define EFUSE_APB2OTP_BLOCK10_W11_M ((EFUSE_APB2OTP_BLOCK10_W11_V)<<(EFUSE_APB2OTP_BLOCK10_W11_S)) -#define EFUSE_APB2OTP_BLOCK10_W11_V 0xFFFFFFFF +/** EFUSE_APB2OTP_BLK10_W11_REG register + * eFuse apb2otp block10 data register11. + */ +#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00) +/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ +#define EFUSE_APB2OTP_BLOCK10_W11 0xFFFFFFFFU +#define EFUSE_APB2OTP_BLOCK10_W11_M (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S) +#define EFUSE_APB2OTP_BLOCK10_W11_V 0xFFFFFFFFU #define EFUSE_APB2OTP_BLOCK10_W11_S 0 -#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xA08) -/* EFUSE_APB2OTP_APB2OTP_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Apb2otp mode enable signal..*/ +/** EFUSE_APB2OTP_EN_REG register + * eFuse apb2otp enable configuration register. + */ +#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08) +/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0; + * Apb2otp mode enable signal. + */ #define EFUSE_APB2OTP_APB2OTP_EN (BIT(0)) -#define EFUSE_APB2OTP_APB2OTP_EN_M (BIT(0)) -#define EFUSE_APB2OTP_APB2OTP_EN_V 0x1 +#define EFUSE_APB2OTP_APB2OTP_EN_M (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S) +#define EFUSE_APB2OTP_APB2OTP_EN_V 0x00000001U #define EFUSE_APB2OTP_APB2OTP_EN_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h index ffa54c2a0e..1ed1b20ab8 100644 --- a/components/soc/esp32p4/include/soc/efuse_struct.h +++ b/components/soc/esp32p4/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,1002 +10,4441 @@ extern "C" { #endif -typedef volatile struct { - uint32_t pgm_data0; - uint32_t pgm_data1; - uint32_t pgm_data2; - uint32_t pgm_data3; - uint32_t pgm_data4; - uint32_t pgm_data5; - uint32_t pgm_data6; - uint32_t pgm_data7; - uint32_t pgm_check_value0; - uint32_t pgm_check_value1; - uint32_t pgm_check_value2; - uint32_t rd_wr_dis; - union { - struct { - uint32_t rd_dis : 7; /*Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t usb_device_exchg_pins : 1; /*Enable usb device exchange pins of D+ and D-.*/ - uint32_t usb_otg11_exchg_pins : 1; /*Enable usb otg11 exchange pins of D+ and D-.*/ - uint32_t dis_usb_jtag : 1; /*Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t powerglitch_en : 1; /*Represents whether power glitch function is enabled. 1: enabled. 0: disabled.*/ - uint32_t dis_usb_serial_jtag : 1; /*Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t dis_force_download : 1; /*Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t spi_download_mspi_dis : 1; /*Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download.*/ - uint32_t dis_twai : 1; /*Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t jtag_sel_enable : 1; /*Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t soft_dis_jtag : 3; /*Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled.*/ - uint32_t dis_pad_jtag : 1; /*Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled.*/ - uint32_t dis_download_manual_encrypt: 1; /*Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled.*/ - uint32_t usb_device_drefh : 2; /*USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV*/ - uint32_t usb_otg11_drefh : 2; /*USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV*/ - uint32_t usb_phy_sel : 1; /*TBD*/ - uint32_t huk_gen_state_low : 6; /*Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t huk_gen_state_high : 3; /*Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid.*/ - uint32_t km_rnd_switch_cycle : 2; /*Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.*/ - uint32_t km_deploy_only_once : 4; /*Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.*/ - uint32_t force_use_key_manager_key : 4; /*Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.*/ - uint32_t force_disable_sw_init_key : 1; /*Set this bit to disable software written init key, and force use efuse_init_key.*/ - uint32_t xts_key_length_256 : 1; /*Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.*/ - uint32_t reserved15 : 1; /*Reserved.*/ - uint32_t wdt_delay_sel : 2; /*Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected.*/ - uint32_t spi_boot_crypt_cnt : 3; /*Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled.*/ - uint32_t secure_boot_key_revoke0 : 1; /*Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t secure_boot_key_revoke1 : 1; /*Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t secure_boot_key_revoke2 : 1; /*Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t key_purpose_0 : 4; /*Represents the purpose of Key0.*/ - uint32_t key_purpose_1 : 4; /*Represents the purpose of Key1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t key_purpose_2 : 4; /*Represents the purpose of Key2.*/ - uint32_t key_purpose_3 : 4; /*Represents the purpose of Key3.*/ - uint32_t key_purpose_4 : 4; /*Represents the purpose of Key4.*/ - uint32_t key_purpose_5 : 4; /*Represents the purpose of Key5.*/ - uint32_t sec_dpa_level : 2; /*Represents the spa secure level by configuring the clock random divide mode.*/ - uint32_t ecdsa_enable_soft_k : 1; /*Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used.*/ - uint32_t crypt_dpa_enable : 1; /*Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.*/ - uint32_t secure_boot_en : 1; /*Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t reserved22 : 1; /*Reserved.*/ - uint32_t flash_type : 1; /*The type of interfaced flash. 0: four data lines, 1: eight data lines.*/ - uint32_t flash_page_size : 2; /*Set flash page size.*/ - uint32_t flash_ecc_en : 1; /*Set this bit to enable ecc for flash boot.*/ - uint32_t dis_usb_otg_download_mode : 1; /*Set this bit to disable download via USB-OTG.*/ - uint32_t flash_tpuw : 4; /*Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t dis_download_mode : 1; /*Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t dis_direct_boot : 1; /*Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t dis_usb_serial_jtag_rom_print: 1; /*Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t lock_km_key : 1; /*TBD*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled.*/ - uint32_t enable_security_download : 1; /*Represents whether security download is enabled or disabled. 1: enabled. 0: disabled.*/ - uint32_t uart_print_control : 2; /*Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. */ - uint32_t force_send_resume : 1; /*Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced.*/ - uint32_t secure_version : 16; /*Represents the version used by ESP-IDF anti-rollback feature.*/ - uint32_t secure_boot_disable_fast_wake: 1; /*Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled.*/ - uint32_t hys_en_pad : 1; /*Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled.*/ - uint32_t dcdc_vset : 5; /*Set the dcdc voltage default.*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t _0pxa_tieh_sel_0 : 2; /*TBD*/ - uint32_t _0pxa_tieh_sel_1 : 2; /*TBD.*/ - uint32_t _0pxa_tieh_sel_2 : 2; /*TBD.*/ - uint32_t _0pxa_tieh_sel_3 : 2; /*TBD.*/ - uint32_t km_disable_deploy_mode : 4; /*TBD*/ - uint32_t usb_device_drefl : 2; /*Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV.*/ - uint32_t usb_otg11_drefl : 2; /*Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV.*/ - uint32_t reserved16 : 2; /*Reserved.*/ - uint32_t hp_pwr_src_sel : 1; /*HP system power source select. 0:LDO. 1: DCDC.*/ - uint32_t dcdc_vset_en : 1; /*Select dcdc vset use efuse_dcdc_vset.*/ - uint32_t dis_wdt : 1; /*Set this bit to disable watch dog.*/ - uint32_t dis_swd : 1; /*Set this bit to disable super-watchdog.*/ - uint32_t reserved22 : 2; /*Reserved.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_sys_0; - union { - struct { - uint32_t mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t mac_ext : 16; /*Stores the extended bits of MAC address.*/ - }; - uint32_t val; - } rd_mac_sys_1; - union { - struct { - uint32_t mac_reserved_1 : 14; /*Reserved.*/ - uint32_t mac_reserved_0 : 18; /*Reserved.*/ - }; - uint32_t val; - } rd_mac_sys_2; - union { - struct { - uint32_t mac_reserved_2 : 18; /*Reserved.*/ - uint32_t sys_data_part0_0 : 14; /*Stores the first 14 bits of the zeroth part of system data.*/ - }; - uint32_t val; - } rd_mac_sys_3; - uint32_t rd_mac_sys_4; - uint32_t rd_mac_sys_5; - uint32_t rd_sys_part1_data0; - uint32_t rd_sys_part1_data1; - uint32_t rd_sys_part1_data2; - uint32_t rd_sys_part1_data3; - uint32_t rd_sys_part1_data4; - uint32_t rd_sys_part1_data5; - uint32_t rd_sys_part1_data6; - uint32_t rd_sys_part1_data7; - uint32_t rd_usr_data0; - uint32_t rd_usr_data1; - uint32_t rd_usr_data2; - uint32_t rd_usr_data3; - uint32_t rd_usr_data4; - uint32_t rd_usr_data5; - uint32_t rd_usr_data6; - uint32_t rd_usr_data7; - uint32_t rd_key0_data0; - uint32_t rd_key0_data1; - uint32_t rd_key0_data2; - uint32_t rd_key0_data3; - uint32_t rd_key0_data4; - uint32_t rd_key0_data5; - uint32_t rd_key0_data6; - uint32_t rd_key0_data7; - uint32_t rd_key1_data0; - uint32_t rd_key1_data1; - uint32_t rd_key1_data2; - uint32_t rd_key1_data3; - uint32_t rd_key1_data4; - uint32_t rd_key1_data5; - uint32_t rd_key1_data6; - uint32_t rd_key1_data7; - uint32_t rd_key2_data0; - uint32_t rd_key2_data1; - uint32_t rd_key2_data2; - uint32_t rd_key2_data3; - uint32_t rd_key2_data4; - uint32_t rd_key2_data5; - uint32_t rd_key2_data6; - uint32_t rd_key2_data7; - uint32_t rd_key3_data0; - uint32_t rd_key3_data1; - uint32_t rd_key3_data2; - uint32_t rd_key3_data3; - uint32_t rd_key3_data4; - uint32_t rd_key3_data5; - uint32_t rd_key3_data6; - uint32_t rd_key3_data7; - uint32_t rd_key4_data0; - uint32_t rd_key4_data1; - uint32_t rd_key4_data2; - uint32_t rd_key4_data3; - uint32_t rd_key4_data4; - uint32_t rd_key4_data5; - uint32_t rd_key4_data6; - uint32_t rd_key4_data7; - uint32_t rd_key5_data0; - uint32_t rd_key5_data1; - uint32_t rd_key5_data2; - uint32_t rd_key5_data3; - uint32_t rd_key5_data4; - uint32_t rd_key5_data5; - uint32_t rd_key5_data6; - uint32_t rd_key5_data7; - uint32_t rd_sys_part2_data0; - uint32_t rd_sys_part2_data1; - uint32_t rd_sys_part2_data2; - uint32_t rd_sys_part2_data3; - uint32_t rd_sys_part2_data4; - uint32_t rd_sys_part2_data5; - uint32_t rd_sys_part2_data6; - uint32_t rd_sys_part2_data7; - union { - struct { - uint32_t rd_dis_err : 7; /*Indicates a programming error of RD_DIS.*/ - uint32_t usb_device_exchg_pins_err : 1; /*Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.*/ - uint32_t usb_otg11_exchg_pins_err : 1; /*Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.*/ - uint32_t dis_usb_jtag_err : 1; /*Indicates a programming error of DIS_USB_JTAG.*/ - uint32_t powerglitch_en_err : 1; /*Indicates a programming error of POWERGLITCH_EN.*/ - uint32_t dis_usb_serial_jtag_err : 1; /*Indicates a programming error of DIS_USB_SERIAL_JTAG.*/ - uint32_t dis_force_download_err : 1; /*Indicates a programming error of DIS_FORCE_DOWNLOAD.*/ - uint32_t spi_download_mspi_dis_err : 1; /*Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.*/ - uint32_t dis_twai_err : 1; /*Indicates a programming error of DIS_TWAI.*/ - uint32_t jtag_sel_enable_err : 1; /*Indicates a programming error of JTAG_SEL_ENABLE.*/ - uint32_t soft_dis_jtag_err : 3; /*Indicates a programming error of SOFT_DIS_JTAG.*/ - uint32_t dis_pad_jtag_err : 1; /*Indicates a programming error of DIS_PAD_JTAG.*/ - uint32_t dis_download_manual_encrypt_err: 1; /*Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ - uint32_t usb_device_drefh_err : 2; /*Indicates a programming error of USB_DEVICE_DREFH.*/ - uint32_t usb_otg11_drefh_err : 2; /*Indicates a programming error of USB_OTG11_DREFH.*/ - uint32_t usb_phy_sel_err : 1; /*Indicates a programming error of USB_PHY_SEL.*/ - uint32_t huk_gen_state_low_err : 6; /*Indicates a programming error of HUK_GEN_STATE_LOW.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t huk_gen_state_high_err : 3; /*Indicates a programming error of HUK_GEN_STATE_HIGH.*/ - uint32_t km_rnd_switch_cycle_err : 2; /*Indicates a programming error of KM_RND_SWITCH_CYCLE.*/ - uint32_t km_deploy_only_once_err : 4; /*Indicates a programming error of KM_DEPLOY_ONLY_ONCE.*/ - uint32_t force_use_key_manager_key_err: 4; /*Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.*/ - uint32_t force_disable_sw_init_key_err: 1; /*Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.*/ - uint32_t xts_key_length_256_err : 1; /*Indicates a programming error of XTS_KEY_LENGTH_256.*/ - uint32_t reserved15 : 1; /*Reserved.*/ - uint32_t wdt_delay_sel_err : 2; /*Indicates a programming error of WDT_DELAY_SEL.*/ - uint32_t spi_boot_crypt_cnt_err : 3; /*Indicates a programming error of SPI_BOOT_CRYPT_CNT.*/ - uint32_t secure_boot_key_revoke0_err: 1; /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.*/ - uint32_t secure_boot_key_revoke1_err: 1; /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.*/ - uint32_t secure_boot_key_revoke2_err: 1; /*Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.*/ - uint32_t key_purpose_0_err : 4; /*Indicates a programming error of KEY_PURPOSE_0.*/ - uint32_t key_purpose_1_err : 4; /*Indicates a programming error of KEY_PURPOSE_1.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t key_purpose_2_err : 4; /*Indicates a programming error of KEY_PURPOSE_2.*/ - uint32_t key_purpose_3_err : 4; /*Indicates a programming error of KEY_PURPOSE_3.*/ - uint32_t key_purpose_4_err : 4; /*Indicates a programming error of KEY_PURPOSE_4.*/ - uint32_t key_purpose_5_err : 4; /*Indicates a programming error of KEY_PURPOSE_5.*/ - uint32_t sec_dpa_level_err : 2; /*Indicates a programming error of SEC_DPA_LEVEL.*/ - uint32_t ecdsa_enable_soft_k_err : 1; /*Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.*/ - uint32_t crypt_dpa_enable_err : 1; /*Indicates a programming error of CRYPT_DPA_ENABLE.*/ - uint32_t secure_boot_en_err : 1; /*Indicates a programming error of SECURE_BOOT_EN.*/ - uint32_t secure_boot_aggressive_revoke_err: 1; /*Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ - uint32_t reserved22 : 1; /*Reserved.*/ - uint32_t flash_type_err : 1; /*Indicates a programming error of FLASH_TYPE.*/ - uint32_t flash_page_size_err : 2; /*Indicates a programming error of FLASH_PAGE_SIZE.*/ - uint32_t flash_ecc_en_err : 1; /*Indicates a programming error of FLASH_ECC_EN.*/ - uint32_t dis_usb_otg_download_mode_err: 1; /*Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.*/ - uint32_t flash_tpuw_err : 4; /*Indicates a programming error of FLASH_TPUW.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t dis_download_mode_err : 1; /*Indicates a programming error of DIS_DOWNLOAD_MODE.*/ - uint32_t dis_direct_boot_err : 1; /*Indicates a programming error of DIS_DIRECT_BOOT.*/ - uint32_t dis_usb_serial_jtag_rom_print_err: 1; /*Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.*/ - uint32_t lock_km_key_err : 1; /*TBD*/ - uint32_t dis_usb_serial_jtag_download_mode_err: 1; /*Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ - uint32_t enable_security_download_err: 1; /*Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.*/ - uint32_t uart_print_control_err : 2; /*Indicates a programming error of UART_PRINT_CONTROL.*/ - uint32_t force_send_resume_err : 1; /*Indicates a programming error of FORCE_SEND_RESUME.*/ - uint32_t secure_version_err : 16; /*Indicates a programming error of SECURE VERSION.*/ - uint32_t secure_boot_disable_fast_wake_err: 1; /*Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.*/ - uint32_t hys_en_pad_err : 1; /*Indicates a programming error of HYS_EN_PAD.*/ - uint32_t dcdc_vset_err : 5; /*Indicates a programming error of DCDC_VSET.*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t _0pxa_tieh_sel_0_err : 2; /*Indicates a programming error of 0PXA_TIEH_SEL_0.*/ - uint32_t _0pxa_tieh_sel_1_err : 2; /*Indicates a programming error of 0PXA_TIEH_SEL_1.*/ - uint32_t _0pxa_tieh_sel_2_err : 2; /*Indicates a programming error of 0PXA_TIEH_SEL_2.*/ - uint32_t _0pxa_tieh_sel_3_err : 2; /*Indicates a programming error of 0PXA_TIEH_SEL_3.*/ - uint32_t km_disable_deploy_mode_err: 4; /*TBD.*/ - uint32_t usb_device_drefl_err : 2; /*Indicates a programming error of USB_DEVICE_DREFL.*/ - uint32_t usb_otg11_drefl_err : 2; /*Indicates a programming error of USB_OTG11_DREFL.*/ - uint32_t reserved16 : 2; /*Reserved.*/ - uint32_t hp_pwr_src_sel_err : 1; /*Indicates a programming error of HP_PWR_SRC_SEL.*/ - uint32_t dcdc_vset_en_err : 1; /*Indicates a programming error of DCDC_VSET_EN.*/ - uint32_t dis_wdt_err : 1; /*Indicates a programming error of DIS_WDT.*/ - uint32_t dis_swd_err : 1; /*Indicates a programming error of DIS_SWD.*/ - uint32_t reserved22 : 2; /*Reserved.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t mac_sys_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t mac_sys_fail : 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t sys_part1_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t sys_part1_fail : 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t usr_data_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t usr_data_fail : 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t key0_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key0_fail : 1; /*0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.*/ - uint32_t key1_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key1_fail : 1; /*0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.*/ - uint32_t key2_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key2_fail : 1; /*0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.*/ - uint32_t key3_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key3_fail : 1; /*0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.*/ - uint32_t key4_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key4_fail : 1; /*0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t key5_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key5_fail : 1; /*0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6.*/ - uint32_t sys_part2_err_num : 3; /*The value of this signal means the number of error bytes.*/ - uint32_t sys_part2_fail : 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t reserved8 : 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t efuse_mem_force_pd : 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t efuse_mem_clk_force_on : 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t efuse_mem_force_pu : 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3 : 13; /*Reserved.*/ - uint32_t clk_en : 1; /*Set this bit to force enable eFuse register configuration clock signal.*/ - uint32_t reserved17 : 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code : 16; /*0x5A5A: programming operation command 0x5AA5: read operation command.*/ - uint32_t cfg_ecdsa_blk : 4; /*Configures which block to use for ECDSA key output.*/ - uint32_t reserved20 : 12; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state : 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw : 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2 : 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw : 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw : 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw : 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw : 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t blk0_valid_bit_cnt : 10; /*Indicates the number of block valid bit.*/ - uint32_t cur_ecdsa_blk : 4; /*Indicates which block is used for ECDSA key output.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd : 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd : 1; /*Set this bit to send programming command.*/ - uint32_t blk_num : 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.*/ - uint32_t reserved6 : 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done_int_raw : 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done_int_raw : 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done_int_st : 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done_int_st : 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done_int_ena : 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done_int_ena : 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done_int_clr : 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done_int_clr : 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2 : 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div : 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel : 1; /*Don't care.*/ - uint32_t dac_num : 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr : 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18 : 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t thr_a : 8; /*Configures the read hold time.*/ - uint32_t trd : 8; /*Configures the read time.*/ - uint32_t tsur_a : 8; /*Configures the read setup time.*/ - uint32_t read_init_num : 8; /*Configures the waiting time of reading eFuse memory.*/ - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t tsup_a : 8; /*Configures the programming setup time.*/ - uint32_t pwr_on_num : 16; /*Configures the power up time for VDDQ.*/ - uint32_t thp_a : 8; /*Configures the programming hold time.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num : 16; /*Configures the power outage time for VDDQ.*/ - uint32_t tpgm : 16; /*Configures the active programming time.*/ - }; - uint32_t val; - } wr_tim_conf2; - union { - struct { - uint32_t bypass_rs_correction : 1; /*Set this bit to bypass reed solomon correction step.*/ - uint32_t bypass_rs_blk_num : 11; /*Configures block number of programming twice operation.*/ - uint32_t update : 1; /*Set this bit to update multi-bit register signals.*/ - uint32_t tpgm_inactive : 8; /*Configures the inactive programming time.*/ - uint32_t reserved21 : 11; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf0_rs_bypass; - union { - struct { - uint32_t date : 28; /*Stores eFuse version.*/ - uint32_t reserved28 : 4; /*Reserved.*/ - }; - uint32_t val; - } date; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t reserved_400; - uint32_t reserved_404; - uint32_t reserved_408; - uint32_t reserved_40c; - uint32_t reserved_410; - uint32_t reserved_414; - uint32_t reserved_418; - uint32_t reserved_41c; - uint32_t reserved_420; - uint32_t reserved_424; - uint32_t reserved_428; - uint32_t reserved_42c; - uint32_t reserved_430; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - uint32_t reserved_47c; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t reserved_500; - uint32_t reserved_504; - uint32_t reserved_508; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t reserved_540; - uint32_t reserved_544; - uint32_t reserved_548; - uint32_t reserved_54c; - uint32_t reserved_550; - uint32_t reserved_554; - uint32_t reserved_558; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t reserved_580; - uint32_t reserved_584; - uint32_t reserved_588; - uint32_t reserved_58c; - uint32_t reserved_590; - uint32_t reserved_594; - uint32_t reserved_598; - uint32_t reserved_59c; - uint32_t reserved_5a0; - uint32_t reserved_5a4; - uint32_t reserved_5a8; - uint32_t reserved_5ac; - uint32_t reserved_5b0; - uint32_t reserved_5b4; - uint32_t reserved_5b8; - uint32_t reserved_5bc; - uint32_t reserved_5c0; - uint32_t reserved_5c4; - uint32_t reserved_5c8; - uint32_t reserved_5cc; - uint32_t reserved_5d0; - uint32_t reserved_5d4; - uint32_t reserved_5d8; - uint32_t reserved_5dc; - uint32_t reserved_5e0; - uint32_t reserved_5e4; - uint32_t reserved_5e8; - uint32_t reserved_5ec; - uint32_t reserved_5f0; - uint32_t reserved_5f4; - uint32_t reserved_5f8; - uint32_t reserved_5fc; - uint32_t reserved_600; - uint32_t reserved_604; - uint32_t reserved_608; - uint32_t reserved_60c; - uint32_t reserved_610; - uint32_t reserved_614; - uint32_t reserved_618; - uint32_t reserved_61c; - uint32_t reserved_620; - uint32_t reserved_624; - uint32_t reserved_628; - uint32_t reserved_62c; - uint32_t reserved_630; - uint32_t reserved_634; - uint32_t reserved_638; - uint32_t reserved_63c; - uint32_t reserved_640; - uint32_t reserved_644; - uint32_t reserved_648; - uint32_t reserved_64c; - uint32_t reserved_650; - uint32_t reserved_654; - uint32_t reserved_658; - uint32_t reserved_65c; - uint32_t reserved_660; - uint32_t reserved_664; - uint32_t reserved_668; - uint32_t reserved_66c; - uint32_t reserved_670; - uint32_t reserved_674; - uint32_t reserved_678; - uint32_t reserved_67c; - uint32_t reserved_680; - uint32_t reserved_684; - uint32_t reserved_688; - uint32_t reserved_68c; - uint32_t reserved_690; - uint32_t reserved_694; - uint32_t reserved_698; - uint32_t reserved_69c; - uint32_t reserved_6a0; - uint32_t reserved_6a4; - uint32_t reserved_6a8; - uint32_t reserved_6ac; - uint32_t reserved_6b0; - uint32_t reserved_6b4; - uint32_t reserved_6b8; - uint32_t reserved_6bc; - uint32_t reserved_6c0; - uint32_t reserved_6c4; - uint32_t reserved_6c8; - uint32_t reserved_6cc; - uint32_t reserved_6d0; - uint32_t reserved_6d4; - uint32_t reserved_6d8; - uint32_t reserved_6dc; - uint32_t reserved_6e0; - uint32_t reserved_6e4; - uint32_t reserved_6e8; - uint32_t reserved_6ec; - uint32_t reserved_6f0; - uint32_t reserved_6f4; - uint32_t reserved_6f8; - uint32_t reserved_6fc; - uint32_t reserved_700; - uint32_t reserved_704; - uint32_t reserved_708; - uint32_t reserved_70c; - uint32_t reserved_710; - uint32_t reserved_714; - uint32_t reserved_718; - uint32_t reserved_71c; - uint32_t reserved_720; - uint32_t reserved_724; - uint32_t reserved_728; - uint32_t reserved_72c; - uint32_t reserved_730; - uint32_t reserved_734; - uint32_t reserved_738; - uint32_t reserved_73c; - uint32_t reserved_740; - uint32_t reserved_744; - uint32_t reserved_748; - uint32_t reserved_74c; - uint32_t reserved_750; - uint32_t reserved_754; - uint32_t reserved_758; - uint32_t reserved_75c; - uint32_t reserved_760; - uint32_t reserved_764; - uint32_t reserved_768; - uint32_t reserved_76c; - uint32_t reserved_770; - uint32_t reserved_774; - uint32_t reserved_778; - uint32_t reserved_77c; - uint32_t reserved_780; - uint32_t reserved_784; - uint32_t reserved_788; - uint32_t reserved_78c; - uint32_t reserved_790; - uint32_t reserved_794; - uint32_t reserved_798; - uint32_t reserved_79c; - uint32_t reserved_7a0; - uint32_t reserved_7a4; - uint32_t reserved_7a8; - uint32_t reserved_7ac; - uint32_t reserved_7b0; - uint32_t reserved_7b4; - uint32_t reserved_7b8; - uint32_t reserved_7bc; - uint32_t reserved_7c0; - uint32_t reserved_7c4; - uint32_t reserved_7c8; - uint32_t reserved_7cc; - uint32_t reserved_7d0; - uint32_t reserved_7d4; - uint32_t reserved_7d8; - uint32_t reserved_7dc; - uint32_t reserved_7e0; - uint32_t reserved_7e4; - uint32_t reserved_7e8; - uint32_t reserved_7ec; - uint32_t reserved_7f0; - uint32_t reserved_7f4; - uint32_t reserved_7f8; - uint32_t reserved_7fc; - uint32_t apb2otp_wr_dis; - uint32_t apb2otp_blk0_backup1_w1; - uint32_t apb2otp_blk0_backup1_w2; - uint32_t apb2otp_blk0_backup1_w3; - uint32_t apb2otp_blk0_backup1_w4; - uint32_t apb2otp_blk0_backup1_w5; - uint32_t apb2otp_blk0_backup2_w1; - uint32_t apb2otp_blk0_backup2_w2; - uint32_t apb2otp_blk0_backup2_w3; - uint32_t apb2otp_blk0_backup2_w4; - uint32_t apb2otp_blk0_backup2_w5; - uint32_t apb2otp_blk0_backup3_w1; - uint32_t apb2otp_blk0_backup3_w2; - uint32_t apb2otp_blk0_backup3_w3; - uint32_t apb2otp_blk0_backup3_w4; - uint32_t apb2otp_blk0_backup3_w5; - uint32_t apb2otp_blk0_backup4_w1; - uint32_t apb2otp_blk0_backup4_w2; - uint32_t apb2otp_blk0_backup4_w3; - uint32_t apb2otp_blk0_backup4_w4; - uint32_t apb2otp_blk0_backup4_w5; - uint32_t apb2otp_blk1_w1; - uint32_t apb2otp_blk1_w2; - uint32_t apb2otp_blk1_w3; - uint32_t apb2otp_blk1_w4; - uint32_t apb2otp_blk1_w5; - uint32_t apb2otp_blk1_w6; - uint32_t apb2otp_blk1_w7; - uint32_t apb2otp_blk1_w8; - uint32_t apb2otp_blk1_w9; - uint32_t apb2otp_blk2_w1; - uint32_t apb2otp_blk2_w2; - uint32_t apb2otp_blk2_w3; - uint32_t apb2otp_blk2_w4; - uint32_t apb2otp_blk2_w5; - uint32_t apb2otp_blk2_w6; - uint32_t apb2otp_blk2_w7; - uint32_t apb2otp_blk2_w8; - uint32_t apb2otp_blk2_w9; - uint32_t apb2otp_blk2_w10; - uint32_t apb2otp_blk2_w11; - uint32_t apb2otp_blk3_w1; - uint32_t apb2otp_blk3_w2; - uint32_t apb2otp_blk3_w3; - uint32_t apb2otp_blk3_w4; - uint32_t apb2otp_blk3_w5; - uint32_t apb2otp_blk3_w6; - uint32_t apb2otp_blk3_w7; - uint32_t apb2otp_blk3_w8; - uint32_t apb2otp_blk3_w9; - uint32_t apb2otp_blk3_w10; - uint32_t apb2otp_blk3_w11; - uint32_t apb2otp_blk4_w1; - uint32_t apb2otp_blk4_w2; - uint32_t apb2otp_blk4_w3; - uint32_t apb2otp_blk4_w4; - uint32_t apb2otp_blk4_w5; - uint32_t apb2otp_blk4_w6; - uint32_t apb2otp_blk4_w7; - uint32_t apb2otp_blk4_w8; - uint32_t apb2otp_blk4_w9; - uint32_t apb2otp_blk4_w10; - uint32_t apb2otp_blk4_w11; - uint32_t apb2otp_blk5_w1; - uint32_t apb2otp_blk5_w2; - uint32_t apb2otp_blk5_w3; - uint32_t apb2otp_blk5_w4; - uint32_t apb2otp_blk5_w5; - uint32_t apb2otp_blk5_w6; - uint32_t apb2otp_blk5_w7; - uint32_t apb2otp_blk5_w8; - uint32_t apb2otp_blk5_w9; - uint32_t apb2otp_blk5_w10; - uint32_t apb2otp_blk5_w11; - uint32_t apb2otp_blk6_w1; - uint32_t apb2otp_blk6_w2; - uint32_t apb2otp_blk6_w3; - uint32_t apb2otp_blk6_w4; - uint32_t apb2otp_blk6_w5; - uint32_t apb2otp_blk6_w6; - uint32_t apb2otp_blk6_w7; - uint32_t apb2otp_blk6_w8; - uint32_t apb2otp_blk6_w9; - uint32_t apb2otp_blk6_w10; - uint32_t apb2otp_blk6_w11; - uint32_t apb2otp_blk7_w1; - uint32_t apb2otp_blk7_w2; - uint32_t apb2otp_blk7_w3; - uint32_t apb2otp_blk7_w4; - uint32_t apb2otp_blk7_w5; - uint32_t apb2otp_blk7_w6; - uint32_t apb2otp_blk7_w7; - uint32_t apb2otp_blk7_w8; - uint32_t apb2otp_blk7_w9; - uint32_t apb2otp_blk7_w10; - uint32_t apb2otp_blk7_w11; - uint32_t apb2otp_blk8_w1; - uint32_t apb2otp_blk8_w2; - uint32_t apb2otp_blk8_w3; - uint32_t apb2otp_blk8_w4; - uint32_t apb2otp_blk8_w5; - uint32_t apb2otp_blk8_w6; - uint32_t apb2otp_blk8_w7; - uint32_t apb2otp_blk8_w8; - uint32_t apb2otp_blk8_w9; - uint32_t apb2otp_blk8_w10; - uint32_t apb2otp_blk8_w11; - uint32_t apb2otp_blk9_w1; - uint32_t apb2otp_blk9_w2; - uint32_t apb2otp_blk9_w3; - uint32_t apb2otp_blk9_w4; - uint32_t apb2otp_blk9_w5; - uint32_t apb2otp_blk9_w6; - uint32_t apb2otp_blk9_w7; - uint32_t apb2otp_blk9_w8; - uint32_t apb2otp_blk9_w9; - uint32_t apb2otp_blk9_w10; - uint32_t apb2otp_blk9_w11; - uint32_t apb2otp_blk10_w1; - uint32_t apb2otp_blk10_w2; - uint32_t apb2otp_blk10_w3; - uint32_t apb2otp_blk10_w4; - uint32_t apb2otp_blk10_w5; - uint32_t apb2otp_blk10_w6; - uint32_t apb2otp_blk10_w7; - uint32_t apb2otp_blk10_w8; - uint32_t apb2otp_blk10_w9; - uint32_t apb2otp_blk10_w10; - uint32_t apb2otp_blk10_w11; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: ******** Registers */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t rd_dis:7; + /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0; + * Enable usb device exchange pins of D+ and D-. + */ + uint32_t usb_device_exchg_pins:1; + /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0; + * Enable usb otg11 exchange pins of D+ and D-. + */ + uint32_t usb_otg11_exchg_pins:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_jtag:1; + /** powerglitch_en : RO; bitpos: [10]; default: 0; + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + */ + uint32_t powerglitch_en:1; + uint32_t reserved_11:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; + * Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during + * boot_mode_download. + */ + uint32_t spi_download_mspi_dis:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_twai:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ + uint32_t dis_download_manual_encrypt:1; + uint32_t reserved_21:4; + /** usb_phy_sel : RO; bitpos: [25]; default: 0; + * TBD + */ + uint32_t usb_phy_sel:1; + /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0; + * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even + * of 1 is valid. + */ + uint32_t km_huk_gen_state_low:6; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0; + * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even + * of 1 is valid. + */ + uint32_t km_huk_gen_state_high:3; + /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0; + * Set bits to control key manager random number switch cycle. 0: control by register. + * 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. + */ + uint32_t km_rnd_switch_cycle:2; + /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0; + * Set each bit to control whether corresponding key can only be deployed once. 1 is + * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + */ + uint32_t km_deploy_only_once:4; + /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0; + * Set each bit to control whether corresponding key must come from key manager.. 1 is + * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + */ + uint32_t force_use_key_manager_key:4; + /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0; + * Set this bit to disable software written init key, and force use efuse_init_key. + */ + uint32_t force_disable_sw_init_key:1; + /** xts_key_length_256 : RO; bitpos: [14]; default: 0; + * Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. + */ + uint32_t xts_key_length_256:1; + uint32_t reserved_15:1; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t sec_dpa_level:2; + /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. + */ + uint32_t ecdsa_enable_soft_k:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ + uint32_t crypt_dpa_enable:1; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_aggressive_revoke:1; + uint32_t reserved_22:1; + /** flash_type : RO; bitpos: [23]; default: 0; + * The type of interfaced flash. 0: four data lines, 1: eight data lines. + */ + uint32_t flash_type:1; + /** flash_page_size : RO; bitpos: [25:24]; default: 0; + * Set flash page size. + */ + uint32_t flash_page_size:2; + /** flash_ecc_en : RO; bitpos: [26]; default: 0; + * Set this bit to enable ecc for flash boot. + */ + uint32_t flash_ecc_en:1; + /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0; + * Set this bit to disable download via USB-OTG. + */ + uint32_t dis_usb_otg_download_mode:1; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** lock_km_key : RO; bitpos: [3]; default: 0; + * TBD + */ + uint32_t lock_km_key:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ + uint32_t hys_en_pad:1; + /** dcdc_vset : RO; bitpos: [31:27]; default: 0; + * Set the dcdc voltage default. + */ + uint32_t dcdc_vset:5; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** 0pxa_tieh_sel_0 : RO; bitpos: [1:0]; default: 0; + * TBD + */ + uint32_t rd_0pxa_tieh_sel_0:2; + /** 0pxa_tieh_sel_1 : RO; bitpos: [3:2]; default: 0; + * TBD. + */ + uint32_t rd_0pxa_tieh_sel_1:2; + /** 0pxa_tieh_sel_2 : RO; bitpos: [5:4]; default: 0; + * TBD. + */ + uint32_t rd_0pxa_tieh_sel_2:2; + /** 0pxa_tieh_sel_3 : RO; bitpos: [7:6]; default: 0; + * TBD. + */ + uint32_t rd_0pxa_tieh_sel_3:2; + /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0; + * TBD. + */ + uint32_t km_disable_deploy_mode:4; + uint32_t reserved_12:6; + /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0; + * HP system power source select. 0:LDO. 1: DCDC. + */ + uint32_t hp_pwr_src_sel:1; + /** dcdc_vset_en : RO; bitpos: [19]; default: 0; + * Select dcdc vset use efuse_dcdc_vset. + */ + uint32_t dcdc_vset_en:1; + /** dis_wdt : RO; bitpos: [20]; default: 0; + * Set this bit to disable watch dog. + */ + uint32_t dis_wdt:1; + /** dis_swd : RO; bitpos: [21]; default: 0; + * Set this bit to disable super-watchdog. + */ + uint32_t dis_swd:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_sys_0 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys_0_reg_t; + +/** Type of rd_mac_sys_1 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys_1_reg_t; + +/** Type of rd_mac_sys_2 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_1:14; + /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_0:18; + }; + uint32_t val; +} efuse_rd_mac_sys_2_reg_t; + +/** Type of rd_mac_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys_3_reg_t; + +/** Type of rd_mac_sys_4 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys_4_reg_t; + +/** Type of rd_mac_sys_5 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_0:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data6:32; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ + uint32_t usr_data7:32; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ + uint32_t rd_dis_err:7; + /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + */ + uint32_t dis_usb_device_exchg_pins_err:1; + /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + */ + uint32_t dis_usb_otg11_exchg_pins_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ + uint32_t dis_usb_jtag_err:1; + /** powerglitch_en_err : RO; bitpos: [10]; default: 0; + * Indicates a programming error of POWERGLITCH_EN. + */ + uint32_t powerglitch_en_err:1; + uint32_t reserved_11:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ + uint32_t spi_download_mspi_dis_err:1; + /** dis_twai_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_TWAI. + */ + uint32_t dis_twai_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + uint32_t reserved_21:4; + /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_PHY_SEL. + */ + uint32_t usb_phy_sel_err:1; + /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0; + * Indicates a programming error of HUK_GEN_STATE_LOW. + */ + uint32_t huk_gen_state_low_err:6; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0; + * Indicates a programming error of HUK_GEN_STATE_HIGH. + */ + uint32_t km_huk_gen_state_high_err:3; + /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0; + * Indicates a programming error of KM_RND_SWITCH_CYCLE. + */ + uint32_t km_rnd_switch_cycle_err:2; + /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0; + * Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + */ + uint32_t km_deploy_only_once_err:4; + /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0; + * Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + */ + uint32_t force_use_key_manager_key_err:4; + /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + */ + uint32_t force_disable_sw_init_key_err:1; + /** xts_key_length_256_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of XTS_KEY_LENGTH_256. + */ + uint32_t xts_key_length_256_err:1; + uint32_t reserved_15:1; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_level_err:2; + /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0; + * Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + */ + uint32_t ecdsa_enable_soft_k_err:1; + /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ + uint32_t crypt_dpa_enable_err:1; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + uint32_t reserved_22:1; + /** flash_type_err : RO; bitpos: [23]; default: 0; + * Indicates a programming error of FLASH_TYPE. + */ + uint32_t flash_type_err:1; + /** flash_page_size_err : RO; bitpos: [25:24]; default: 0; + * Indicates a programming error of FLASH_PAGE_SIZE. + */ + uint32_t flash_page_size_err:2; + /** flash_ecc_en_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of FLASH_ECC_EN. + */ + uint32_t flash_ecc_en_err:1; + /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0; + * Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + */ + uint32_t dis_usb_otg_download_mode_err:1; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ + uint32_t dis_direct_boot_err:1; + /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + */ + uint32_t dis_usb_serial_jtag_rom_print_err:1; + /** lock_km_key_err : RO; bitpos: [3]; default: 0; + * TBD + */ + uint32_t lock_km_key_err:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ + uint32_t secure_version_err:16; + /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ + uint32_t secure_boot_disable_fast_wake_err:1; + /** hys_en_pad_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of HYS_EN_PAD. + */ + uint32_t hys_en_pad_err:1; + /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0; + * Indicates a programming error of DCDC_VSET. + */ + uint32_t dcdc_vset_err:5; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** 0pxa_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_0. + */ + uint32_t rd_0pxa_tieh_sel_0_err:2; + /** 0pxa_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_1. + */ + uint32_t rd_0pxa_tieh_sel_1_err:2; + /** 0pxa_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_2. + */ + uint32_t rd_0pxa_tieh_sel_2_err:2; + /** 0pxa_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of 0PXA_TIEH_SEL_3. + */ + uint32_t rd_0pxa_tieh_sel_3_err:2; + /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0; + * TBD. + */ + uint32_t km_disable_deploy_mode_err:4; + /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0; + * Indicates a programming error of USB_DEVICE_DREFL. + */ + uint32_t usb_device_drefl_err:2; + /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0; + * Indicates a programming error of USB_OTG11_DREFL. + */ + uint32_t usb_otg11_drefl_err:2; + uint32_t reserved_16:2; + /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0; + * Indicates a programming error of HP_PWR_SRC_SEL. + */ + uint32_t hp_pwr_src_sel_err:1; + /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DCDC_VSET_EN. + */ + uint32_t dcdc_vset_en_err:1; + /** dis_wdt_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_WDT. + */ + uint32_t dis_wdt_err:1; + /** dis_swd_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of DIS_SWD. + */ + uint32_t dis_swd_err:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_sys_err_num:3; + /** mac_sys_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_sys_fail:1; + /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_err_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ + uint32_t op_code:16; + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + uint32_t reserved_4:6; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + + +/** Group: EFUSE Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720720; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Write Disable Data */ +/** Type of apb2otp_wr_dis register + * eFuse apb2otp block0 data register1. + */ +typedef union { + struct { + /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ + uint32_t apb2otp_block0_wr_dis:32; + }; + uint32_t val; +} efuse_apb2otp_wr_dis_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */ +/** Type of apb2otp_blk0_backup1_w1 register + * eFuse apb2otp block0 data register2. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ + uint32_t apb2otp_block0_backup1_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */ +/** Type of apb2otp_blk0_backup1_w2 register + * eFuse apb2otp block0 data register3. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ + uint32_t apb2otp_block0_backup1_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */ +/** Type of apb2otp_blk0_backup1_w3 register + * eFuse apb2otp block0 data register4. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ + uint32_t apb2otp_block0_backup1_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */ +/** Type of apb2otp_blk0_backup1_w4 register + * eFuse apb2otp block0 data register5. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ + uint32_t apb2otp_block0_backup1_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */ +/** Type of apb2otp_blk0_backup1_w5 register + * eFuse apb2otp block0 data register6. + */ +typedef union { + struct { + /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ + uint32_t apb2otp_block0_backup1_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup1_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */ +/** Type of apb2otp_blk0_backup2_w1 register + * eFuse apb2otp block0 data register7. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ + uint32_t apb2otp_block0_backup2_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */ +/** Type of apb2otp_blk0_backup2_w2 register + * eFuse apb2otp block0 data register8. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ + uint32_t apb2otp_block0_backup2_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */ +/** Type of apb2otp_blk0_backup2_w3 register + * eFuse apb2otp block0 data register9. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ + uint32_t apb2otp_block0_backup2_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */ +/** Type of apb2otp_blk0_backup2_w4 register + * eFuse apb2otp block0 data register10. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ + uint32_t apb2otp_block0_backup2_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */ +/** Type of apb2otp_blk0_backup2_w5 register + * eFuse apb2otp block0 data register11. + */ +typedef union { + struct { + /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ + uint32_t apb2otp_block0_backup2_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup2_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */ +/** Type of apb2otp_blk0_backup3_w1 register + * eFuse apb2otp block0 data register12. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ + uint32_t apb2otp_block0_backup3_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */ +/** Type of apb2otp_blk0_backup3_w2 register + * eFuse apb2otp block0 data register13. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ + uint32_t apb2otp_block0_backup3_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */ +/** Type of apb2otp_blk0_backup3_w3 register + * eFuse apb2otp block0 data register14. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ + uint32_t apb2otp_block0_backup3_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */ +/** Type of apb2otp_blk0_backup3_w4 register + * eFuse apb2otp block0 data register15. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ + uint32_t apb2otp_block0_backup3_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */ +/** Type of apb2otp_blk0_backup3_w5 register + * eFuse apb2otp block0 data register16. + */ +typedef union { + struct { + /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ + uint32_t apb2otp_block0_backup3_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup3_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */ +/** Type of apb2otp_blk0_backup4_w1 register + * eFuse apb2otp block0 data register17. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ + uint32_t apb2otp_block0_backup4_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */ +/** Type of apb2otp_blk0_backup4_w2 register + * eFuse apb2otp block0 data register18. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ + uint32_t apb2otp_block0_backup4_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */ +/** Type of apb2otp_blk0_backup4_w3 register + * eFuse apb2otp block0 data register19. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ + uint32_t apb2otp_block0_backup4_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */ +/** Type of apb2otp_blk0_backup4_w4 register + * eFuse apb2otp block0 data register20. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ + uint32_t apb2otp_block0_backup4_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */ +/** Type of apb2otp_blk0_backup4_w5 register + * eFuse apb2otp block0 data register21. + */ +typedef union { + struct { + /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ + uint32_t apb2otp_block0_backup4_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk0_backup4_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word1 Data */ +/** Type of apb2otp_blk1_w1 register + * eFuse apb2otp block1 data register1. + */ +typedef union { + struct { + /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ + uint32_t apb2otp_block1_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word2 Data */ +/** Type of apb2otp_blk1_w2 register + * eFuse apb2otp block1 data register2. + */ +typedef union { + struct { + /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ + uint32_t apb2otp_block1_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word3 Data */ +/** Type of apb2otp_blk1_w3 register + * eFuse apb2otp block1 data register3. + */ +typedef union { + struct { + /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ + uint32_t apb2otp_block1_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word4 Data */ +/** Type of apb2otp_blk1_w4 register + * eFuse apb2otp block1 data register4. + */ +typedef union { + struct { + /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ + uint32_t apb2otp_block1_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word5 Data */ +/** Type of apb2otp_blk1_w5 register + * eFuse apb2otp block1 data register5. + */ +typedef union { + struct { + /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ + uint32_t apb2otp_block1_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word6 Data */ +/** Type of apb2otp_blk1_w6 register + * eFuse apb2otp block1 data register6. + */ +typedef union { + struct { + /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ + uint32_t apb2otp_block1_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word7 Data */ +/** Type of apb2otp_blk1_w7 register + * eFuse apb2otp block1 data register7. + */ +typedef union { + struct { + /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ + uint32_t apb2otp_block1_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word8 Data */ +/** Type of apb2otp_blk1_w8 register + * eFuse apb2otp block1 data register8. + */ +typedef union { + struct { + /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ + uint32_t apb2otp_block1_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block1 Word9 Data */ +/** Type of apb2otp_blk1_w9 register + * eFuse apb2otp block1 data register9. + */ +typedef union { + struct { + /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ + uint32_t apb2otp_block1_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk1_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word1 Data */ +/** Type of apb2otp_blk2_w1 register + * eFuse apb2otp block2 data register1. + */ +typedef union { + struct { + /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ + uint32_t apb2otp_block2_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word2 Data */ +/** Type of apb2otp_blk2_w2 register + * eFuse apb2otp block2 data register2. + */ +typedef union { + struct { + /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ + uint32_t apb2otp_block2_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word3 Data */ +/** Type of apb2otp_blk2_w3 register + * eFuse apb2otp block2 data register3. + */ +typedef union { + struct { + /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ + uint32_t apb2otp_block2_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word4 Data */ +/** Type of apb2otp_blk2_w4 register + * eFuse apb2otp block2 data register4. + */ +typedef union { + struct { + /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ + uint32_t apb2otp_block2_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word5 Data */ +/** Type of apb2otp_blk2_w5 register + * eFuse apb2otp block2 data register5. + */ +typedef union { + struct { + /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ + uint32_t apb2otp_block2_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word6 Data */ +/** Type of apb2otp_blk2_w6 register + * eFuse apb2otp block2 data register6. + */ +typedef union { + struct { + /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ + uint32_t apb2otp_block2_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word7 Data */ +/** Type of apb2otp_blk2_w7 register + * eFuse apb2otp block2 data register7. + */ +typedef union { + struct { + /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ + uint32_t apb2otp_block2_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word8 Data */ +/** Type of apb2otp_blk2_w8 register + * eFuse apb2otp block2 data register8. + */ +typedef union { + struct { + /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ + uint32_t apb2otp_block2_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word9 Data */ +/** Type of apb2otp_blk2_w9 register + * eFuse apb2otp block2 data register9. + */ +typedef union { + struct { + /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ + uint32_t apb2otp_block2_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word10 Data */ +/** Type of apb2otp_blk2_w10 register + * eFuse apb2otp block2 data register10. + */ +typedef union { + struct { + /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ + uint32_t apb2otp_block2_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block2 Word11 Data */ +/** Type of apb2otp_blk2_w11 register + * eFuse apb2otp block2 data register11. + */ +typedef union { + struct { + /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ + uint32_t apb2otp_block2_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk2_w11_reg_t; + +/** Type of apb2otp_blk10_w11 register + * eFuse apb2otp block10 data register11. + */ +typedef union { + struct { + /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t apb2otp_block10_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word1 Data */ +/** Type of apb2otp_blk3_w1 register + * eFuse apb2otp block3 data register1. + */ +typedef union { + struct { + /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ + uint32_t apb2otp_block3_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word2 Data */ +/** Type of apb2otp_blk3_w2 register + * eFuse apb2otp block3 data register2. + */ +typedef union { + struct { + /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ + uint32_t apb2otp_block3_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word3 Data */ +/** Type of apb2otp_blk3_w3 register + * eFuse apb2otp block3 data register3. + */ +typedef union { + struct { + /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ + uint32_t apb2otp_block3_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word4 Data */ +/** Type of apb2otp_blk3_w4 register + * eFuse apb2otp block3 data register4. + */ +typedef union { + struct { + /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ + uint32_t apb2otp_block3_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word5 Data */ +/** Type of apb2otp_blk3_w5 register + * eFuse apb2otp block3 data register5. + */ +typedef union { + struct { + /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ + uint32_t apb2otp_block3_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word6 Data */ +/** Type of apb2otp_blk3_w6 register + * eFuse apb2otp block3 data register6. + */ +typedef union { + struct { + /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ + uint32_t apb2otp_block3_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word7 Data */ +/** Type of apb2otp_blk3_w7 register + * eFuse apb2otp block3 data register7. + */ +typedef union { + struct { + /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ + uint32_t apb2otp_block3_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word8 Data */ +/** Type of apb2otp_blk3_w8 register + * eFuse apb2otp block3 data register8. + */ +typedef union { + struct { + /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ + uint32_t apb2otp_block3_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word9 Data */ +/** Type of apb2otp_blk3_w9 register + * eFuse apb2otp block3 data register9. + */ +typedef union { + struct { + /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ + uint32_t apb2otp_block3_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word10 Data */ +/** Type of apb2otp_blk3_w10 register + * eFuse apb2otp block3 data register10. + */ +typedef union { + struct { + /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ + uint32_t apb2otp_block3_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block3 Word11 Data */ +/** Type of apb2otp_blk3_w11 register + * eFuse apb2otp block3 data register11. + */ +typedef union { + struct { + /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ + uint32_t apb2otp_block3_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk3_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word1 Data */ +/** Type of apb2otp_blk4_w1 register + * eFuse apb2otp block4 data register1. + */ +typedef union { + struct { + /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ + uint32_t apb2otp_block4_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word2 Data */ +/** Type of apb2otp_blk4_w2 register + * eFuse apb2otp block4 data register2. + */ +typedef union { + struct { + /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ + uint32_t apb2otp_block4_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word3 Data */ +/** Type of apb2otp_blk4_w3 register + * eFuse apb2otp block4 data register3. + */ +typedef union { + struct { + /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ + uint32_t apb2otp_block4_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word4 Data */ +/** Type of apb2otp_blk4_w4 register + * eFuse apb2otp block4 data register4. + */ +typedef union { + struct { + /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ + uint32_t apb2otp_block4_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word5 Data */ +/** Type of apb2otp_blk4_w5 register + * eFuse apb2otp block4 data register5. + */ +typedef union { + struct { + /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ + uint32_t apb2otp_block4_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word6 Data */ +/** Type of apb2otp_blk4_w6 register + * eFuse apb2otp block4 data register6. + */ +typedef union { + struct { + /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ + uint32_t apb2otp_block4_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word7 Data */ +/** Type of apb2otp_blk4_w7 register + * eFuse apb2otp block4 data register7. + */ +typedef union { + struct { + /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ + uint32_t apb2otp_block4_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word8 Data */ +/** Type of apb2otp_blk4_w8 register + * eFuse apb2otp block4 data register8. + */ +typedef union { + struct { + /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ + uint32_t apb2otp_block4_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word9 Data */ +/** Type of apb2otp_blk4_w9 register + * eFuse apb2otp block4 data register9. + */ +typedef union { + struct { + /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ + uint32_t apb2otp_block4_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word10 Data */ +/** Type of apb2otp_blk4_w10 register + * eFuse apb2otp block4 data registe10. + */ +typedef union { + struct { + /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ + uint32_t apb2otp_block4_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block4 Word11 Data */ +/** Type of apb2otp_blk4_w11 register + * eFuse apb2otp block4 data register11. + */ +typedef union { + struct { + /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ + uint32_t apb2otp_block4_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk4_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word1 Data */ +/** Type of apb2otp_blk5_w1 register + * eFuse apb2otp block5 data register1. + */ +typedef union { + struct { + /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ + uint32_t apb2otp_block5_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word2 Data */ +/** Type of apb2otp_blk5_w2 register + * eFuse apb2otp block5 data register2. + */ +typedef union { + struct { + /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ + uint32_t apb2otp_block5_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word3 Data */ +/** Type of apb2otp_blk5_w3 register + * eFuse apb2otp block5 data register3. + */ +typedef union { + struct { + /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ + uint32_t apb2otp_block5_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word4 Data */ +/** Type of apb2otp_blk5_w4 register + * eFuse apb2otp block5 data register4. + */ +typedef union { + struct { + /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ + uint32_t apb2otp_block5_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word5 Data */ +/** Type of apb2otp_blk5_w5 register + * eFuse apb2otp block5 data register5. + */ +typedef union { + struct { + /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ + uint32_t apb2otp_block5_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word6 Data */ +/** Type of apb2otp_blk5_w6 register + * eFuse apb2otp block5 data register6. + */ +typedef union { + struct { + /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ + uint32_t apb2otp_block5_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word7 Data */ +/** Type of apb2otp_blk5_w7 register + * eFuse apb2otp block5 data register7. + */ +typedef union { + struct { + /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ + uint32_t apb2otp_block5_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word8 Data */ +/** Type of apb2otp_blk5_w8 register + * eFuse apb2otp block5 data register8. + */ +typedef union { + struct { + /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ + uint32_t apb2otp_block5_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word9 Data */ +/** Type of apb2otp_blk5_w9 register + * eFuse apb2otp block5 data register9. + */ +typedef union { + struct { + /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ + uint32_t apb2otp_block5_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word10 Data */ +/** Type of apb2otp_blk5_w10 register + * eFuse apb2otp block5 data register10. + */ +typedef union { + struct { + /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ + uint32_t apb2otp_block5_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block5 Word11 Data */ +/** Type of apb2otp_blk5_w11 register + * eFuse apb2otp block5 data register11. + */ +typedef union { + struct { + /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ + uint32_t apb2otp_block5_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk5_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word1 Data */ +/** Type of apb2otp_blk6_w1 register + * eFuse apb2otp block6 data register1. + */ +typedef union { + struct { + /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ + uint32_t apb2otp_block6_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word2 Data */ +/** Type of apb2otp_blk6_w2 register + * eFuse apb2otp block6 data register2. + */ +typedef union { + struct { + /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ + uint32_t apb2otp_block6_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word3 Data */ +/** Type of apb2otp_blk6_w3 register + * eFuse apb2otp block6 data register3. + */ +typedef union { + struct { + /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ + uint32_t apb2otp_block6_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word4 Data */ +/** Type of apb2otp_blk6_w4 register + * eFuse apb2otp block6 data register4. + */ +typedef union { + struct { + /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ + uint32_t apb2otp_block6_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word5 Data */ +/** Type of apb2otp_blk6_w5 register + * eFuse apb2otp block6 data register5. + */ +typedef union { + struct { + /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ + uint32_t apb2otp_block6_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word6 Data */ +/** Type of apb2otp_blk6_w6 register + * eFuse apb2otp block6 data register6. + */ +typedef union { + struct { + /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ + uint32_t apb2otp_block6_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word7 Data */ +/** Type of apb2otp_blk6_w7 register + * eFuse apb2otp block6 data register7. + */ +typedef union { + struct { + /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ + uint32_t apb2otp_block6_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word8 Data */ +/** Type of apb2otp_blk6_w8 register + * eFuse apb2otp block6 data register8. + */ +typedef union { + struct { + /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ + uint32_t apb2otp_block6_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word9 Data */ +/** Type of apb2otp_blk6_w9 register + * eFuse apb2otp block6 data register9. + */ +typedef union { + struct { + /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ + uint32_t apb2otp_block6_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word10 Data */ +/** Type of apb2otp_blk6_w10 register + * eFuse apb2otp block6 data register10. + */ +typedef union { + struct { + /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ + uint32_t apb2otp_block6_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block6 Word11 Data */ +/** Type of apb2otp_blk6_w11 register + * eFuse apb2otp block6 data register11. + */ +typedef union { + struct { + /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ + uint32_t apb2otp_block6_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk6_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word1 Data */ +/** Type of apb2otp_blk7_w1 register + * eFuse apb2otp block7 data register1. + */ +typedef union { + struct { + /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ + uint32_t apb2otp_block7_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word2 Data */ +/** Type of apb2otp_blk7_w2 register + * eFuse apb2otp block7 data register2. + */ +typedef union { + struct { + /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ + uint32_t apb2otp_block7_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word3 Data */ +/** Type of apb2otp_blk7_w3 register + * eFuse apb2otp block7 data register3. + */ +typedef union { + struct { + /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ + uint32_t apb2otp_block7_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word4 Data */ +/** Type of apb2otp_blk7_w4 register + * eFuse apb2otp block7 data register4. + */ +typedef union { + struct { + /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ + uint32_t apb2otp_block7_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word5 Data */ +/** Type of apb2otp_blk7_w5 register + * eFuse apb2otp block7 data register5. + */ +typedef union { + struct { + /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ + uint32_t apb2otp_block7_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word6 Data */ +/** Type of apb2otp_blk7_w6 register + * eFuse apb2otp block7 data register6. + */ +typedef union { + struct { + /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ + uint32_t apb2otp_block7_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word7 Data */ +/** Type of apb2otp_blk7_w7 register + * eFuse apb2otp block7 data register7. + */ +typedef union { + struct { + /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ + uint32_t apb2otp_block7_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word8 Data */ +/** Type of apb2otp_blk7_w8 register + * eFuse apb2otp block7 data register8. + */ +typedef union { + struct { + /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ + uint32_t apb2otp_block7_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word9 Data */ +/** Type of apb2otp_blk7_w9 register + * eFuse apb2otp block7 data register9. + */ +typedef union { + struct { + /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ + uint32_t apb2otp_block7_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word10 Data */ +/** Type of apb2otp_blk7_w10 register + * eFuse apb2otp block7 data register10. + */ +typedef union { + struct { + /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ + uint32_t apb2otp_block7_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block7 Word11 Data */ +/** Type of apb2otp_blk7_w11 register + * eFuse apb2otp block7 data register11. + */ +typedef union { + struct { + /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ + uint32_t apb2otp_block7_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk7_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word1 Data */ +/** Type of apb2otp_blk8_w1 register + * eFuse apb2otp block8 data register1. + */ +typedef union { + struct { + /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ + uint32_t apb2otp_block8_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word2 Data */ +/** Type of apb2otp_blk8_w2 register + * eFuse apb2otp block8 data register2. + */ +typedef union { + struct { + /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ + uint32_t apb2otp_block8_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word3 Data */ +/** Type of apb2otp_blk8_w3 register + * eFuse apb2otp block8 data register3. + */ +typedef union { + struct { + /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ + uint32_t apb2otp_block8_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word4 Data */ +/** Type of apb2otp_blk8_w4 register + * eFuse apb2otp block8 data register4. + */ +typedef union { + struct { + /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ + uint32_t apb2otp_block8_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word5 Data */ +/** Type of apb2otp_blk8_w5 register + * eFuse apb2otp block8 data register5. + */ +typedef union { + struct { + /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ + uint32_t apb2otp_block8_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word6 Data */ +/** Type of apb2otp_blk8_w6 register + * eFuse apb2otp block8 data register6. + */ +typedef union { + struct { + /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ + uint32_t apb2otp_block8_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word7 Data */ +/** Type of apb2otp_blk8_w7 register + * eFuse apb2otp block8 data register7. + */ +typedef union { + struct { + /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ + uint32_t apb2otp_block8_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word8 Data */ +/** Type of apb2otp_blk8_w8 register + * eFuse apb2otp block8 data register8. + */ +typedef union { + struct { + /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ + uint32_t apb2otp_block8_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word9 Data */ +/** Type of apb2otp_blk8_w9 register + * eFuse apb2otp block8 data register9. + */ +typedef union { + struct { + /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ + uint32_t apb2otp_block8_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word10 Data */ +/** Type of apb2otp_blk8_w10 register + * eFuse apb2otp block8 data register10. + */ +typedef union { + struct { + /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ + uint32_t apb2otp_block8_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block8 Word11 Data */ +/** Type of apb2otp_blk8_w11 register + * eFuse apb2otp block8 data register11. + */ +typedef union { + struct { + /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ + uint32_t apb2otp_block8_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk8_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word1 Data */ +/** Type of apb2otp_blk9_w1 register + * eFuse apb2otp block9 data register1. + */ +typedef union { + struct { + /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ + uint32_t apb2otp_block9_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word2 Data */ +/** Type of apb2otp_blk9_w2 register + * eFuse apb2otp block9 data register2. + */ +typedef union { + struct { + /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ + uint32_t apb2otp_block9_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word3 Data */ +/** Type of apb2otp_blk9_w3 register + * eFuse apb2otp block9 data register3. + */ +typedef union { + struct { + /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ + uint32_t apb2otp_block9_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word4 Data */ +/** Type of apb2otp_blk9_w4 register + * eFuse apb2otp block9 data register4. + */ +typedef union { + struct { + /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ + uint32_t apb2otp_block9_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word5 Data */ +/** Type of apb2otp_blk9_w5 register + * eFuse apb2otp block9 data register5. + */ +typedef union { + struct { + /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ + uint32_t apb2otp_block9_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word6 Data */ +/** Type of apb2otp_blk9_w6 register + * eFuse apb2otp block9 data register6. + */ +typedef union { + struct { + /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ + uint32_t apb2otp_block9_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word7 Data */ +/** Type of apb2otp_blk9_w7 register + * eFuse apb2otp block9 data register7. + */ +typedef union { + struct { + /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ + uint32_t apb2otp_block9_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word8 Data */ +/** Type of apb2otp_blk9_w8 register + * eFuse apb2otp block9 data register8. + */ +typedef union { + struct { + /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ + uint32_t apb2otp_block9_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word9 Data */ +/** Type of apb2otp_blk9_w9 register + * eFuse apb2otp block9 data register9. + */ +typedef union { + struct { + /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ + uint32_t apb2otp_block9_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word10 Data */ +/** Type of apb2otp_blk9_w10 register + * eFuse apb2otp block9 data register10. + */ +typedef union { + struct { + /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ + uint32_t apb2otp_block9_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Block9 Word11 Data */ +/** Type of apb2otp_blk9_w11 register + * eFuse apb2otp block9 data register11. + */ +typedef union { + struct { + /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ + uint32_t apb2otp_block9_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk9_w11_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word1 Data */ +/** Type of apb2otp_blk10_w1 register + * eFuse apb2otp block10 data register1. + */ +typedef union { + struct { + /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ + uint32_t apb2otp_block10_w1:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w1_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word2 Data */ +/** Type of apb2otp_blk10_w2 register + * eFuse apb2otp block10 data register2. + */ +typedef union { + struct { + /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ + uint32_t apb2otp_block10_w2:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w2_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word3 Data */ +/** Type of apb2otp_blk10_w3 register + * eFuse apb2otp block10 data register3. + */ +typedef union { + struct { + /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ + uint32_t apb2otp_block10_w3:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w3_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word4 Data */ +/** Type of apb2otp_blk10_w4 register + * eFuse apb2otp block10 data register4. + */ +typedef union { + struct { + /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ + uint32_t apb2otp_block10_w4:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w4_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word5 Data */ +/** Type of apb2otp_blk10_w5 register + * eFuse apb2otp block10 data register5. + */ +typedef union { + struct { + /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ + uint32_t apb2otp_block10_w5:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w5_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word6 Data */ +/** Type of apb2otp_blk10_w6 register + * eFuse apb2otp block10 data register6. + */ +typedef union { + struct { + /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ + uint32_t apb2otp_block10_w6:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w6_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word7 Data */ +/** Type of apb2otp_blk10_w7 register + * eFuse apb2otp block10 data register7. + */ +typedef union { + struct { + /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ + uint32_t apb2otp_block10_w7:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w7_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word8 Data */ +/** Type of apb2otp_blk10_w8 register + * eFuse apb2otp block10 data register8. + */ +typedef union { + struct { + /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ + uint32_t apb2otp_block10_w8:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w8_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word9 Data */ +/** Type of apb2otp_blk10_w9 register + * eFuse apb2otp block10 data register9. + */ +typedef union { + struct { + /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ + uint32_t apb2otp_block10_w9:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w9_reg_t; + + +/** Group: EFUSE_APB2OTP Block10 Word10 Data */ +/** Type of apb2otp_blk10_w10 register + * eFuse apb2otp block10 data register10. + */ +typedef union { + struct { + /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ + uint32_t apb2otp_block19_w10:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w10_reg_t; + + +/** Group: EFUSE_APB2OTP Function Enable Singal */ +/** Type of apb2otp_en register + * eFuse apb2otp enable configuration register. + */ +typedef union { + struct { + /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0; + * Apb2otp mode enable signal. + */ + uint32_t apb2otp_apb2otp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} efuse_apb2otp_en_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_190[12]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; + uint32_t reserved_200[384]; + volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; + volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; + volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; + volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3; + volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4; + volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5; + volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1; + volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2; + volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3; + volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4; + volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5; + volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1; + volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2; + volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3; + volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4; + volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5; + volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1; + volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2; + volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3; + volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4; + volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5; + volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1; + volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2; + volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3; + volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4; + volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5; + volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6; + volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7; + volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8; + volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9; + volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1; + volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2; + volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3; + volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4; + volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5; + volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6; + volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7; + volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8; + volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9; + volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10; + volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11; + volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1; + volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2; + volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3; + volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4; + volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5; + volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6; + volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7; + volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8; + volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9; + volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10; + volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11; + volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1; + volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2; + volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3; + volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4; + volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5; + volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6; + volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7; + volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8; + volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9; + volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10; + volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11; + volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1; + volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2; + volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3; + volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4; + volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5; + volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6; + volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7; + volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8; + volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9; + volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10; + volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11; + volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1; + volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2; + volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3; + volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4; + volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5; + volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6; + volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7; + volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8; + volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9; + volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10; + volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11; + volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1; + volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2; + volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3; + volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4; + volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5; + volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6; + volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7; + volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8; + volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9; + volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10; + volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11; + volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1; + volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2; + volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3; + volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4; + volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5; + volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6; + volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7; + volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8; + volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9; + volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10; + volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11; + volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1; + volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2; + volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3; + volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4; + volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5; + volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6; + volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7; + volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8; + volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9; + volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10; + volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11; + volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1; + volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2; + volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3; + volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4; + volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5; + volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6; + volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7; + volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8; + volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9; + volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10; + volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; uint32_t reserved_a04; - union { - struct { - uint32_t apb2otp_enable : 1; /*Apb2otp mode enable signal.*/ - uint32_t reserved1 : 31; /*Reserved.*/ - }; - uint32_t val; - } apb2otp_en; + volatile efuse_apb2otp_en_reg_t apb2otp_en; } efuse_dev_t; extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure"); +#endif + #ifdef __cplusplus } #endif