diff --git a/components/esp_hw_support/hw_random.c b/components/esp_hw_support/hw_random.c
index 0f1f193ced..0c9c1e82bf 100644
--- a/components/esp_hw_support/hw_random.c
+++ b/components/esp_hw_support/hw_random.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,11 +13,17 @@
 #include "esp_cpu.h"
 #include "soc/wdev_reg.h"
 #include "esp_private/esp_clk.h"
+#include "esp_private/startup_internal.h"
+#include "soc/soc_caps.h"
 
 #if SOC_LP_TIMER_SUPPORTED
 #include "hal/lp_timer_hal.h"
 #endif
 
+#if SOC_RNG_CLOCK_IS_INDEPENDENT
+#include "hal/lp_clkrst_ll.h"
+#endif
+
 #if defined CONFIG_IDF_TARGET_ESP32S3
 #define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz*/
                                   /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
@@ -103,3 +109,11 @@ void esp_fill_random(void *buf, size_t len)
         len -= to_copy;
     }
 }
+
+#if SOC_RNG_CLOCK_IS_INDEPENDENT
+ESP_SYSTEM_INIT_FN(init_rng_clock, SECONDARY, BIT(0), 102)
+{
+    _lp_clkrst_ll_enable_rng_clock(true);
+    return ESP_OK;
+}
+#endif
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index 9fa7406d45..89356b07ae 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -26,6 +26,7 @@
 #include "hal/i2c_ll.h"
 #include "hal/rmt_ll.h"
 #include "hal/ledc_ll.h"
+#include "hal/lp_clkrst_ll.h"
 #include "hal/timer_ll.h"
 #include "hal/twai_ll.h"
 #include "hal/i2s_ll.h"
@@ -291,9 +292,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         _lp_i2c_ll_enable_bus_clock(0, false);
         _lp_uart_ll_enable_bus_clock(0, false);
         lp_core_ll_enable_bus_clock(false);
+        _lp_clkrst_ll_enable_rng_clock(false);
 
         CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
-        CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
         CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
         CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
         WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index 81dcd8be42..c153830dab 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -28,6 +28,7 @@
 #include "hal/i2c_ll.h"
 #include "hal/rmt_ll.h"
 #include "hal/ledc_ll.h"
+#include "hal/lp_clkrst_ll.h"
 #include "hal/timer_ll.h"
 #include "hal/twai_ll.h"
 #include "hal/i2s_ll.h"
@@ -279,8 +280,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
 
     if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
             || rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) {
+        _lp_clkrst_ll_enable_rng_clock(false);
         CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
-        CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
         CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
         CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
         WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt
index beb3c458df..5a2abd8cc1 100644
--- a/components/esp_system/system_init_fn.txt
+++ b/components/esp_system/system_init_fn.txt
@@ -67,6 +67,9 @@ SECONDARY: 100: esp_timer_init_os in components/esp_timer/src/esp_timer.c on ESP
 # HW stack guard via assist-debug module.
 SECONDARY: 101: esp_hw_stack_guard_init in components/esp_system/hw_stack_guard.c on ESP_SYSTEM_INIT_ALL_CORES
 
+# RNG module clock was disabled in `esp_perip_clk_init`, if hw_random is used, need to re-ebnabled it in startup
+SECONDARY: 102: init_rng_clock in components/esp_hw_support/hw_random.c on BIT(0)
+
 # esp_sleep doesn't have init dependencies
 SECONDARY: 105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0)
 SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/sleep_clock.c on BIT(0)
diff --git a/components/hal/esp32c6/include/hal/lp_clkrst_ll.h b/components/hal/esp32c6/include/hal/lp_clkrst_ll.h
new file mode 100644
index 0000000000..43b94076be
--- /dev/null
+++ b/components/hal/esp32c6/include/hal/lp_clkrst_ll.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-C6 LP_CLKRST & LP PERI register operations
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "soc/soc.h"
+#include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    LPPERI.clk_en.rng_ck_en = en;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32h2/include/hal/lp_clkrst_ll.h b/components/hal/esp32h2/include/hal/lp_clkrst_ll.h
index a91f01a857..bffe712ba4 100644
--- a/components/hal/esp32h2/include/hal/lp_clkrst_ll.h
+++ b/components/hal/esp32h2/include/hal/lp_clkrst_ll.h
@@ -1,10 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// The LL layer for ESP32-H2 LP CLKRST register operations
+// The LL layer for ESP32-H2 LP CLKRST & LP PERI register operations
 
 #pragma once
 
@@ -12,6 +12,7 @@
 #include <stdlib.h>
 #include "soc/soc.h"
 #include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -59,6 +60,15 @@ static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *h
     hw->lpperi.lp_bletimer_32k_sel = src;
 }
 
+__attribute__((always_inline))
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    LPPERI.clk_en.rng_ck_en = en;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index cca1adfdb4..ca4a8f5cec 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -1351,6 +1351,10 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
     bool
     default y
 
+config SOC_RNG_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
 config SOC_WIFI_HW_TSF
     bool
     default y
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index c51e1c40dd..fb75998b07 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -541,6 +541,9 @@
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                    (1)
 
+/*--------------------------------- RNG CAPS --------------------------------------------*/
+#define SOC_RNG_CLOCK_IS_INDEPENDENT                          (1)
+
 /*------------------------------------ WI-FI CAPS ------------------------------------*/
 #define SOC_WIFI_HW_TSF                     (1)    /*!< Support hardware TSF */
 #define SOC_WIFI_FTM_SUPPORT                (0)    /*!< Support FTM */
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 6ef786e8f5..a062bd1c23 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -1315,6 +1315,10 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
     bool
     default y
 
+config SOC_RNG_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
 config SOC_BLE_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index 858b218ccb..a5ce9810bc 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -520,6 +520,9 @@
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                    (1)
 
+/*--------------------------------- RNG CAPS --------------------------------------------*/
+#define SOC_RNG_CLOCK_IS_INDEPENDENT                          (1)
+
 /*---------------------------------- Bluetooth CAPS ----------------------------------*/
 #define SOC_BLE_SUPPORTED               (1)    /*!< Support Bluetooth Low Energy hardware */
 #define SOC_BLE_MESH_SUPPORTED          (1)    /*!< Support BLE MESH */