diff --git a/components/hal/esp32p4/include/ahb_dma_ll.h b/components/hal/esp32p4/include/ahb_dma_ll.h
new file mode 100644
index 0000000000..2f4d880821
--- /dev/null
+++ b/components/hal/esp32p4/include/ahb_dma_ll.h
@@ -0,0 +1,505 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "hal/gdma_types.h"
+#include "hal/gdma_ll.h"
+#include "soc/ahb_dma_struct.h"
+#include "soc/ahb_dma_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
+
+// any "dummy" peripheral ID can be used for M2M mode
+#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFAC2)
+#define AHB_DMA_LL_INVALID_PERIPH_ID       (0x3F)
+
+///////////////////////////////////// Common /////////////////////////////////////////
+/**
+ * @brief Force enable register clock
+ */
+static inline void ahb_dma_ll_force_enable_reg_clock(ahb_dma_dev_t *dev, bool enable)
+{
+    dev->misc_conf.clk_en = enable;
+}
+
+/**
+ * @brief Disable priority arbitration
+ *
+ * @param dev DMA register base address
+ * @param dis True to disable, false to enable
+ */
+static inline void ahb_dma_ll_disable_prio_arb(ahb_dma_dev_t *dev, bool dis)
+{
+    dev->misc_conf.arb_pri_dis = dis;
+}
+
+/**
+ * @brief Reset DMA FSM
+ *
+ * @param dev DMA register base address
+ */
+static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
+{
+    dev->misc_conf.ahbm_rst_inter = 1;
+    dev->misc_conf.ahbm_rst_inter = 0;
+}
+
+///////////////////////////////////// RX /////////////////////////////////////////
+/**
+ * @brief Get DMA RX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->in_intr[channel].st.val;
+}
+
+/**
+ * @brief Enable DMA RX channel interrupt
+ */
+static inline void ahb_dma_ll_rx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->in_intr[channel].ena.val |= mask;
+    } else {
+        dev->in_intr[channel].ena.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Clear DMA RX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_rx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->in_intr[channel].clr.val = mask;
+}
+
+/**
+ * @brief Get DMA RX channel interrupt status register address
+ */
+static inline volatile void *ahb_dma_ll_rx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->in_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void ahb_dma_ll_rx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf1.in_check_owner_chn = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading data, disabled by default
+ */
+static inline void ahb_dma_ll_rx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_data_burst_en_chn = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
+ */
+static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
+}
+
+/**
+ * @brief Reset DMA RX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_rx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_conf0.in_rst_chn = 1;
+    dev->channel[channel].in.in_conf0.in_rst_chn = 0;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool ahb_dma_ll_rx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool ahb_dma_ll_rx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes remained in the L1 RX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t ahb_dma_ll_rx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.infifo_cnt_chn;
+}
+
+/**
+ * @brief Pop data from DMA RX FIFO
+ */
+static inline uint32_t ahb_dma_ll_rx_pop_data(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_pop.infifo_pop_chn = 1;
+    return dev->channel[channel].in.in_pop.infifo_rdata_chn;
+}
+
+/**
+ * @brief Set the descriptor link base address for RX channel
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_rx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->in_link_addr[channel].inlink_addr_chn = addr;
+}
+
+/**
+ * @brief Start dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_rx_start(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_start_chn = 1;
+}
+
+/**
+ * @brief Stop dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_rx_stop(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_stop_chn = 1;
+}
+
+/**
+ * @brief Restart a new inlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_rx_restart(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_restart_chn = 1;
+}
+
+/**
+ * @brief Enable DMA RX to return the address of current descriptor when receives error
+ */
+static inline void ahb_dma_ll_rx_enable_auto_return(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_link.inlink_auto_ret_chn = enable;
+}
+
+/**
+ * @brief Check if DMA RX FSM is in IDLE state
+ */
+static inline bool ahb_dma_ll_rx_is_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_link.inlink_park_chn;
+}
+
+/**
+ * @brief Get RX success EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_rx_get_success_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_suc_eof_des_addr.val;
+}
+
+/**
+ * @brief Get RX error EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_rx_get_error_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_err_eof_des_addr.val;
+}
+
+/**
+ * @brief Get the pre-fetched RX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_rx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA RX channel
+ */
+static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].in.in_pri.rx_pri_chn = prio;
+}
+
+/**
+ * @brief Connect DMA RX channel to a given peripheral
+ */
+static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
+{
+    dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
+    dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
+}
+
+/**
+ * @brief Disconnect DMA RX channel from peripheral
+ */
+static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for RX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_etm_en_chn = enable;
+}
+
+///////////////////////////////////// TX /////////////////////////////////////////
+/**
+ * @brief Get DMA TX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->out_intr[channel].st.val;
+}
+
+/**
+ * @brief Enable DMA TX channel interrupt
+ */
+static inline void ahb_dma_ll_tx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->out_intr[channel].ena.val |= mask;
+    } else {
+        dev->out_intr[channel].ena.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Clear DMA TX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_tx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->out_intr[channel].clr.val = mask;
+}
+
+/**
+ * @brief Get DMA TX channel interrupt status register address
+ */
+static inline volatile void *ahb_dma_ll_tx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->out_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void ahb_dma_ll_tx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf1.out_check_owner_chn = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst sending data, disabled by default
+ */
+static inline void ahb_dma_ll_tx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_data_burst_en_chn = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst reading descriptor link, disabled by default
+ */
+static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
+}
+
+/**
+ * @brief Set TX channel EOF mode
+ */
+static inline void ahb_dma_ll_tx_set_eof_mode(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mode)
+{
+    dev->channel[channel].out.out_conf0.out_eof_mode_chn = mode;
+}
+
+/**
+ * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
+ */
+static inline void ahb_dma_ll_tx_enable_auto_write_back(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable;
+}
+
+/**
+ * @brief Reset DMA TX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_tx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_conf0.out_rst_chn = 1;
+    dev->channel[channel].out.out_conf0.out_rst_chn = 0;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool ahb_dma_ll_tx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool ahb_dma_ll_tx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in TX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t ahb_dma_ll_tx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.outfifo_cnt_chn;
+}
+
+/**
+ * @brief Push data into DMA TX FIFO
+ */
+static inline void ahb_dma_ll_tx_push_data(ahb_dma_dev_t *dev, uint32_t channel, uint32_t data)
+{
+    dev->channel[channel].out.out_push.outfifo_wdata_chn = data;
+    dev->channel[channel].out.out_push.outfifo_push_chn = 1;
+}
+
+/**
+ * @brief Set the descriptor link base address for TX channel
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_tx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->out_link_addr[channel].outlink_addr_chn = addr;
+}
+
+/**
+ * @brief Start dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_tx_start(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_start_chn = 1;
+}
+
+/**
+ * @brief Stop dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_tx_stop(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_stop_chn = 1;
+}
+
+/**
+ * @brief Restart a new outlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void ahb_dma_ll_tx_restart(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_restart_chn = 1;
+}
+
+/**
+ * @brief Check if DMA TX FSM is in IDLE state
+ */
+static inline bool ahb_dma_ll_tx_is_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_link.outlink_park_chn;
+}
+
+/**
+ * @brief Get TX EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_tx_get_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_eof_des_addr.val;
+}
+
+/**
+ * @brief Get the pre-fetched TX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t ahb_dma_ll_tx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA TX channel
+ */
+static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].out.out_pri.tx_pri_chn = prio;
+}
+
+/**
+ * @brief Connect DMA TX channel to a given peripheral
+ */
+static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
+{
+    (void)periph;
+    dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
+}
+
+/**
+ * @brief Disconnect DMA TX channel from peripheral
+ */
+static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for TX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32p4/include/axi_dma_ll.h b/components/hal/esp32p4/include/axi_dma_ll.h
new file mode 100644
index 0000000000..2219725c0d
--- /dev/null
+++ b/components/hal/esp32p4/include/axi_dma_ll.h
@@ -0,0 +1,453 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "hal/gdma_types.h"
+#include "hal/gdma_ll.h"
+#include "soc/axi_dma_struct.h"
+#include "soc/axi_dma_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AXI_DMA_LL_GET_HW(id) (((id) == 0) ? (&AXI_DMA) : NULL)
+
+// any "dummy" peripheral ID can be used for M2M mode
+#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
+#define AXI_DMA_LL_INVALID_PERIPH_ID       (0x3F)
+
+///////////////////////////////////// Common /////////////////////////////////////////
+/**
+ * @brief Force enable register clock
+ */
+static inline void axi_dma_ll_force_enable_reg_clock(axi_dma_dev_t *dev, bool enable)
+{
+    dev->misc_conf.clk_en = enable;
+}
+
+/**
+ * @brief Disable priority arbitration
+ *
+ * @param dev DMA register base address
+ * @param dis True to disable, false to enable
+ */
+static inline void axi_dma_ll_disable_prio_arb(axi_dma_dev_t *dev, bool dis)
+{
+    dev->misc_conf.arb_pri_dis = dis;
+}
+
+/**
+ * @brief Reset DMA FSM (Read and Write)
+ *
+ * @param dev DMA register base address
+ */
+static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
+{
+    dev->misc_conf.axim_rst_rd_inter = 1;
+    dev->misc_conf.axim_rst_rd_inter = 0;
+    dev->misc_conf.axim_rst_wr_inter = 1;
+    dev->misc_conf.axim_rst_wr_inter = 0;
+}
+
+///////////////////////////////////// RX /////////////////////////////////////////
+/**
+ * @brief Get DMA RX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->in[channel].intr.st.val;
+}
+
+/**
+ * @brief Enable DMA RX channel interrupt
+ */
+static inline void axi_dma_ll_rx_enable_interrupt(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->in[channel].intr.ena.val |= mask;
+    } else {
+        dev->in[channel].intr.ena.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Clear DMA RX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_rx_clear_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->in[channel].intr.clr.val = mask;
+}
+
+/**
+ * @brief Get DMA RX channel interrupt status register address
+ */
+static inline volatile void *axi_dma_ll_rx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->in[channel].intr.st);
+}
+
+/**
+ * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->in[channel].conf.in_conf1.in_check_owner_chn = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading data, disabled by default
+ */
+static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    // TODO: IDF-6504
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
+ */
+static inline void axi_dma_ll_rx_enable_descriptor_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->in[channel].conf.in_conf0.indscr_burst_en_chn = enable;
+}
+
+/**
+ * @brief Reset DMA RX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_rx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->in[channel].conf.in_conf0.in_rst_chn = 1;
+    dev->in[channel].conf.in_conf0.in_rst_chn = 0;
+}
+
+/**
+ * @brief Pop data from DMA RX FIFO
+ */
+static inline uint32_t axi_dma_ll_rx_pop_data(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->in[channel].conf.in_pop.infifo_pop_chn = 1;
+    return dev->in[channel].conf.in_pop.infifo_rdata_chn;
+}
+
+/**
+ * @brief Set the descriptor link base address for RX channel
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_rx_set_desc_addr(axi_dma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->in[channel].conf.in_link2.inlink_addr_chn = addr;
+}
+
+/**
+ * @brief Start dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_rx_start(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->in[channel].conf.in_link1.inlink_start_chn = 1;
+}
+
+/**
+ * @brief Stop dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_rx_stop(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->in[channel].conf.in_link1.inlink_stop_chn = 1;
+}
+
+/**
+ * @brief Restart a new inlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_rx_restart(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->in[channel].conf.in_link1.inlink_restart_chn = 1;
+}
+
+/**
+ * @brief Enable DMA RX to return the address of current descriptor when receives error
+ */
+static inline void axi_dma_ll_rx_enable_auto_return(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->in[channel].conf.in_link1.inlink_auto_ret_chn = enable;
+}
+
+/**
+ * @brief Check if DMA RX FSM is in IDLE state
+ */
+static inline bool axi_dma_ll_rx_is_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->in[channel].conf.in_link1.inlink_park_chn;
+}
+
+/**
+ * @brief Get RX success EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_rx_get_success_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->in[channel].conf.in_suc_eof_des_addr.val;
+}
+
+/**
+ * @brief Get RX error EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_rx_get_error_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->in[channel].conf.in_err_eof_des_addr.val;
+}
+
+/**
+ * @brief Get the pre-fetched RX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_rx_get_prefetched_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->in[channel].conf.in_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA RX channel
+ */
+static inline void axi_dma_ll_rx_set_priority(axi_dma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->in[channel].conf.in_pri.rx_pri_chn = prio;
+}
+
+/**
+ * @brief Connect DMA RX channel to a given peripheral
+ */
+static inline void axi_dma_ll_rx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
+{
+    dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = periph_id;
+    dev->in[channel].conf.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
+}
+
+/**
+ * @brief Disconnect DMA RX channel from peripheral
+ */
+static inline void axi_dma_ll_rx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for RX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->in[channel].conf.in_conf0.in_etm_en_chn = enable;
+}
+
+///////////////////////////////////// TX /////////////////////////////////////////
+/**
+ * @brief Get DMA TX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->out[channel].intr.st.val;
+}
+
+/**
+ * @brief Enable DMA TX channel interrupt
+ */
+static inline void axi_dma_ll_tx_enable_interrupt(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->out[channel].intr.ena.val |= mask;
+    } else {
+        dev->out[channel].intr.ena.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Clear DMA TX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_tx_clear_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->out[channel].intr.clr.val = mask;
+}
+
+/**
+ * @brief Get DMA TX channel interrupt status register address
+ */
+static inline volatile void *axi_dma_ll_tx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->out[channel].intr.st);
+}
+
+/**
+ * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->out[channel].conf.out_conf1.out_check_owner_chn = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst sending data, disabled by default
+ */
+static inline void axi_dma_ll_tx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    // TODO: IDF-6504
+}
+
+/**
+ * @brief Enable DMA TX channel burst reading descriptor link, disabled by default
+ */
+static inline void axi_dma_ll_tx_enable_descriptor_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->out[channel].conf.out_conf0.outdscr_burst_en_chn = enable;
+}
+
+/**
+ * @brief Set TX channel EOF mode
+ */
+static inline void axi_dma_ll_tx_set_eof_mode(axi_dma_dev_t *dev, uint32_t channel, uint32_t mode)
+{
+    dev->out[channel].conf.out_conf0.out_eof_mode_chn = mode;
+}
+
+/**
+ * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
+ */
+static inline void axi_dma_ll_tx_enable_auto_write_back(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->out[channel].conf.out_conf0.out_auto_wrback_chn = enable;
+}
+
+/**
+ * @brief Reset DMA TX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_tx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->out[channel].conf.out_conf0.out_rst_chn = 1;
+    dev->out[channel].conf.out_conf0.out_rst_chn = 0;
+}
+
+/**
+ * @brief Push data into DMA TX FIFO
+ */
+static inline void axi_dma_ll_tx_push_data(axi_dma_dev_t *dev, uint32_t channel, uint32_t data)
+{
+    dev->out[channel].conf.out_push.outfifo_wdata_chn = data;
+    dev->out[channel].conf.out_push.outfifo_push_chn = 1;
+}
+
+/**
+ * @brief Set the descriptor link base address for TX channel
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_tx_set_desc_addr(axi_dma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->out[channel].conf.out_link2.outlink_addr_chn = addr;
+}
+
+/**
+ * @brief Start dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_tx_start(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->out[channel].conf.out_link1.outlink_start_chn = 1;
+}
+
+/**
+ * @brief Stop dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_tx_stop(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->out[channel].conf.out_link1.outlink_stop_chn = 1;
+}
+
+/**
+ * @brief Restart a new outlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void axi_dma_ll_tx_restart(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->out[channel].conf.out_link1.outlink_restart_chn = 1;
+}
+
+/**
+ * @brief Check if DMA TX FSM is in IDLE state
+ */
+static inline bool axi_dma_ll_tx_is_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->out[channel].conf.out_link1.outlink_park_chn;
+}
+
+/**
+ * @brief Get TX EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_tx_get_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->out[channel].conf.out_eof_des_addr.val;
+}
+
+/**
+ * @brief Get the pre-fetched TX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t axi_dma_ll_tx_get_prefetched_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
+{
+    return dev->out[channel].conf.out_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA TX channel
+ */
+static inline void axi_dma_ll_tx_set_priority(axi_dma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->out[channel].conf.out_pri.tx_pri_chn = prio;
+}
+
+/**
+ * @brief Connect DMA TX channel to a given peripheral
+ */
+static inline void axi_dma_ll_tx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
+{
+    (void)periph;
+    dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = periph_id;
+}
+
+/**
+ * @brief Disconnect DMA TX channel from peripheral
+ */
+static inline void axi_dma_ll_tx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
+{
+    dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for TX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->out[channel].conf.out_conf0.out_etm_en_chn = enable;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32p4/include/gdma_ll.h b/components/hal/esp32p4/include/gdma_ll.h
new file mode 100644
index 0000000000..7bad6c03f5
--- /dev/null
+++ b/components/hal/esp32p4/include/gdma_ll.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief The contents defined in this file are common for both AXI-DMA and AHB-DMA
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
+
+#define GDMA_LL_RX_EVENT_MASK       (0x1F)
+#define GDMA_LL_TX_EVENT_MASK       (0x0F)
+
+#define GDMA_LL_EVENT_TX_TOTAL_EOF  (1<<3)
+#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
+#define GDMA_LL_EVENT_TX_EOF        (1<<1)
+#define GDMA_LL_EVENT_TX_DONE       (1<<0)
+
+#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
+#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
+#define GDMA_LL_EVENT_RX_ERR_EOF    (1<<2)
+#define GDMA_LL_EVENT_RX_SUC_EOF    (1<<1)
+#define GDMA_LL_EVENT_RX_DONE       (1<<0)
+
+#define GDMA_LL_AHB_GROUP_START_ID    0 // AHB GDMA group ID starts from 0
+#define GDMA_LL_AHB_NUM_GROUPS        1 // Number of AHB GDMA groups
+#define GDMA_LL_AHB_PAIRS_PER_GROUP   3 // Number of GDMA pairs in each AHB group
+
+#define GDMA_LL_AXI_GROUP_START_ID    1 // AXI GDMA group ID starts from 1
+#define GDMA_LL_AXI_NUM_GROUPS        1 // Number of AXI GDMA groups
+#define GDMA_LL_AXI_PAIRS_PER_GROUP   3 // Number of GDMA pairs in each AXI group
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/gdma_hal_ahb_v2.c b/components/hal/gdma_hal_ahb_v2.c
new file mode 100644
index 0000000000..2c2678e052
--- /dev/null
+++ b/components/hal/gdma_hal_ahb_v2.c
@@ -0,0 +1,167 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc_caps.h"
+#include "hal/assert.h"
+#include "hal/gdma_hal_ahb.h"
+#include "hal/ahb_dma_ll.h"
+
+static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
+    .m2m_free_periph_mask = AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
+};
+
+void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_set_desc_addr(hal->ahb_dma_dev, chan_id, desc_base_addr);
+        ahb_dma_ll_rx_start(hal->ahb_dma_dev, chan_id);
+    } else {
+        ahb_dma_ll_tx_set_desc_addr(hal->ahb_dma_dev, chan_id, desc_base_addr);
+        ahb_dma_ll_tx_start(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+void gdma_ahb_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_stop(hal->ahb_dma_dev, chan_id);
+    } else {
+        ahb_dma_ll_tx_stop(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+void gdma_ahb_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_restart(hal->ahb_dma_dev, chan_id);
+    } else {
+        ahb_dma_ll_tx_restart(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+void gdma_ahb_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id);
+    } else {
+        ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_set_priority(hal->ahb_dma_dev, chan_id, priority);
+    } else {
+        ahb_dma_ll_tx_set_priority(hal->ahb_dma_dev, chan_id, priority);
+    }
+}
+
+void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
+        ahb_dma_ll_rx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
+    } else {
+        ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
+        ahb_dma_ll_tx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
+    }
+}
+
+void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
+    } else {
+        ahb_dma_ll_tx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_enable_data_burst(hal->ahb_dma_dev, chan_id, en_data_burst);
+        ahb_dma_ll_rx_enable_descriptor_burst(hal->ahb_dma_dev, chan_id, en_desc_burst);
+    } else {
+        ahb_dma_ll_tx_enable_data_burst(hal->ahb_dma_dev, chan_id, en_data_burst);
+        ahb_dma_ll_tx_enable_descriptor_burst(hal->ahb_dma_dev, chan_id, en_desc_burst);
+    }
+}
+
+void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
+    } else {
+        ahb_dma_ll_tx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
+        ahb_dma_ll_tx_enable_auto_write_back(hal->ahb_dma_dev, chan_id, en_desc_write_back);
+    }
+}
+
+void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_enable_interrupt(hal->ahb_dma_dev, chan_id, intr_event_mask, en_or_dis);
+    } else {
+        ahb_dma_ll_tx_enable_interrupt(hal->ahb_dma_dev, chan_id, intr_event_mask, en_or_dis);
+    }
+}
+
+void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_clear_interrupt_status(hal->ahb_dma_dev, chan_id, intr_event_mask);
+    } else {
+        ahb_dma_ll_tx_clear_interrupt_status(hal->ahb_dma_dev, chan_id, intr_event_mask);
+    }
+}
+
+uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id);
+    } else {
+        return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+uint32_t gdma_ahb_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        return (uint32_t)ahb_dma_ll_rx_get_interrupt_status_reg(hal->ahb_dma_dev, chan_id);
+    } else {
+        return (uint32_t)ahb_dma_ll_tx_get_interrupt_status_reg(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+uint32_t gdma_ahb_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        return ahb_dma_ll_rx_get_success_eof_desc_addr(hal->ahb_dma_dev, chan_id);
+    } else {
+        return ahb_dma_ll_tx_get_eof_desc_addr(hal->ahb_dma_dev, chan_id);
+    }
+}
+
+void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
+{
+    hal->ahb_dma_dev = AHB_DMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID);
+    hal->start_with_desc = gdma_ahb_hal_start_with_desc;
+    hal->stop = gdma_ahb_hal_stop;
+    hal->append = gdma_ahb_hal_append;
+    hal->reset = gdma_ahb_hal_reset;
+    hal->set_priority = gdma_ahb_hal_set_priority;
+    hal->connect_peri = gdma_ahb_hal_connect_peri;
+    hal->disconnect_peri = gdma_ahb_hal_disconnect_peri;
+    hal->enable_burst = gdma_ahb_hal_enable_burst;
+    hal->set_strategy = gdma_ahb_hal_set_strategy;
+    hal->enable_intr = gdma_ahb_hal_enable_intr;
+    hal->clear_intr = gdma_ahb_hal_clear_intr;
+    hal->read_intr_status = gdma_ahb_hal_read_intr_status;
+    hal->get_intr_status_reg = gdma_ahb_hal_get_intr_status_reg;
+    hal->get_eof_desc_addr = gdma_ahb_hal_get_eof_desc_addr;
+    hal->priv_data = &gdma_ahb_hal_priv_data;
+}
diff --git a/components/hal/gdma_hal_axi.c b/components/hal/gdma_hal_axi.c
new file mode 100644
index 0000000000..c84d7693cc
--- /dev/null
+++ b/components/hal/gdma_hal_axi.c
@@ -0,0 +1,167 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc_caps.h"
+#include "hal/assert.h"
+#include "hal/gdma_hal_axi.h"
+#include "hal/axi_dma_ll.h"
+
+static gdma_hal_priv_data_t gdma_axi_hal_priv_data = {
+    .m2m_free_periph_mask = AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
+};
+
+void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_set_desc_addr(hal->axi_dma_dev, chan_id, desc_base_addr);
+        axi_dma_ll_rx_start(hal->axi_dma_dev, chan_id);
+    } else {
+        axi_dma_ll_tx_set_desc_addr(hal->axi_dma_dev, chan_id, desc_base_addr);
+        axi_dma_ll_tx_start(hal->axi_dma_dev, chan_id);
+    }
+}
+
+void gdma_axi_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_stop(hal->axi_dma_dev, chan_id);
+    } else {
+        axi_dma_ll_tx_stop(hal->axi_dma_dev, chan_id);
+    }
+}
+
+void gdma_axi_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_restart(hal->axi_dma_dev, chan_id);
+    } else {
+        axi_dma_ll_tx_restart(hal->axi_dma_dev, chan_id);
+    }
+}
+
+void gdma_axi_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_reset_channel(hal->axi_dma_dev, chan_id);
+    } else {
+        axi_dma_ll_tx_reset_channel(hal->axi_dma_dev, chan_id);
+    }
+}
+
+void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_set_priority(hal->axi_dma_dev, chan_id, priority);
+    } else {
+        axi_dma_ll_tx_set_priority(hal->axi_dma_dev, chan_id, priority);
+    }
+}
+
+void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_reset_channel(hal->axi_dma_dev, chan_id); // reset channel
+        axi_dma_ll_rx_connect_to_periph(hal->axi_dma_dev, chan_id, periph, periph_sub_id);
+    } else {
+        axi_dma_ll_tx_reset_channel(hal->axi_dma_dev, chan_id); // reset channel
+        axi_dma_ll_tx_connect_to_periph(hal->axi_dma_dev, chan_id, periph, periph_sub_id);
+    }
+}
+
+void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_disconnect_from_periph(hal->axi_dma_dev, chan_id);
+    } else {
+        axi_dma_ll_tx_disconnect_from_periph(hal->axi_dma_dev, chan_id);
+    }
+}
+
+void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_enable_data_burst(hal->axi_dma_dev, chan_id, en_data_burst);
+        axi_dma_ll_rx_enable_descriptor_burst(hal->axi_dma_dev, chan_id, en_desc_burst);
+    } else {
+        axi_dma_ll_tx_enable_data_burst(hal->axi_dma_dev, chan_id, en_data_burst);
+        axi_dma_ll_tx_enable_descriptor_burst(hal->axi_dma_dev, chan_id, en_desc_burst);
+    }
+}
+
+void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_enable_owner_check(hal->axi_dma_dev, chan_id, en_owner_check);
+    } else {
+        axi_dma_ll_tx_enable_owner_check(hal->axi_dma_dev, chan_id, en_owner_check);
+        axi_dma_ll_tx_enable_auto_write_back(hal->axi_dma_dev, chan_id, en_desc_write_back);
+    }
+}
+
+void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_enable_interrupt(hal->axi_dma_dev, chan_id, intr_event_mask, en_or_dis);
+    } else {
+        axi_dma_ll_tx_enable_interrupt(hal->axi_dma_dev, chan_id, intr_event_mask, en_or_dis);
+    }
+}
+
+void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_clear_interrupt_status(hal->axi_dma_dev, chan_id, intr_event_mask);
+    } else {
+        axi_dma_ll_tx_clear_interrupt_status(hal->axi_dma_dev, chan_id, intr_event_mask);
+    }
+}
+
+uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        return axi_dma_ll_rx_get_interrupt_status(hal->axi_dma_dev, chan_id);
+    } else {
+        return axi_dma_ll_tx_get_interrupt_status(hal->axi_dma_dev, chan_id);
+    }
+}
+
+uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        return (uint32_t)axi_dma_ll_rx_get_interrupt_status_reg(hal->axi_dma_dev, chan_id);
+    } else {
+        return (uint32_t)axi_dma_ll_tx_get_interrupt_status_reg(hal->axi_dma_dev, chan_id);
+    }
+}
+
+uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        return axi_dma_ll_rx_get_success_eof_desc_addr(hal->axi_dma_dev, chan_id);
+    } else {
+        return axi_dma_ll_tx_get_eof_desc_addr(hal->axi_dma_dev, chan_id);
+    }
+}
+
+void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
+{
+    hal->axi_dma_dev = AXI_DMA_LL_GET_HW(config->group_id - GDMA_LL_AXI_GROUP_START_ID);
+    hal->start_with_desc = gdma_axi_hal_start_with_desc;
+    hal->stop = gdma_axi_hal_stop;
+    hal->append = gdma_axi_hal_append;
+    hal->reset = gdma_axi_hal_reset;
+    hal->set_priority = gdma_axi_hal_set_priority;
+    hal->connect_peri = gdma_axi_hal_connect_peri;
+    hal->disconnect_peri = gdma_axi_hal_disconnect_peri;
+    hal->enable_burst = gdma_axi_hal_enable_burst;
+    hal->set_strategy = gdma_axi_hal_set_strategy;
+    hal->enable_intr = gdma_axi_hal_enable_intr;
+    hal->clear_intr = gdma_axi_hal_clear_intr;
+    hal->read_intr_status = gdma_axi_hal_read_intr_status;
+    hal->get_intr_status_reg = gdma_axi_hal_get_intr_status_reg;
+    hal->get_eof_desc_addr = gdma_axi_hal_get_eof_desc_addr;
+    hal->priv_data = &gdma_axi_hal_priv_data;
+}
diff --git a/components/hal/include/hal/gdma_hal_axi.h b/components/hal/include/hal/gdma_hal_axi.h
new file mode 100644
index 0000000000..a10ee22c03
--- /dev/null
+++ b/components/hal/include/hal/gdma_hal_axi.h
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "hal/gdma_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr);
+
+void gdma_axi_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+void gdma_axi_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+void gdma_axi_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
+
+void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id);
+
+void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
+
+void gdma_axi_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align);
+
+void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back);
+
+void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis);
+
+void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask);
+
+uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
+
+void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/include/hal/gdma_types.h b/components/hal/include/hal/gdma_types.h
index 4a889bbf35..9ad63adee5 100644
--- a/components/hal/include/hal/gdma_types.h
+++ b/components/hal/include/hal/gdma_types.h
@@ -27,6 +27,7 @@ typedef enum {
     GDMA_TRIG_PERIPH_CAM,  /*!< GDMA trigger peripheral: CAM */
     GDMA_TRIG_PERIPH_RMT,  /*!< GDMA trigger peripheral: RMT */
     GDMA_TRIG_PERIPH_PARLIO, /*!< GDMA trigger peripheral: PARLIO */
+    GDMA_TRIG_PERIPH_I3C,  /*!< GDMA trigger peripheral: I3C */
 } gdma_trigger_peripheral_t;
 
 /**
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index cf0f176453..2325fb761e 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -195,17 +195,21 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US
     int
     default 1100
 
-config SOC_GDMA_GROUPS
+config SOC_AHB_GDMA_VERSION
     int
-    default 1
+    default 2
 
-config SOC_GDMA_PAIRS_PER_GROUP
+config SOC_GDMA_NUM_GROUPS_MAX
+    int
+    default 2
+
+config SOC_GDMA_PAIRS_PER_GROUP_MAX
     int
     default 3
 
 config SOC_GDMA_SUPPORT_ETM
     bool
-    default n
+    default y
 
 config SOC_ETM_GROUPS
     int
diff --git a/components/soc/esp32p4/include/soc/ahb_dma_struct.h b/components/soc/esp32p4/include/soc/ahb_dma_struct.h
index 2d15e193b1..cc642d6ad4 100644
--- a/components/soc/esp32p4/include/soc/ahb_dma_struct.h
+++ b/components/soc/esp32p4/include/soc/ahb_dma_struct.h
@@ -20,42 +20,42 @@ typedef union {
          *  The raw interrupt bit turns to high level when the last data pointed by one inlink
          *  descriptor has been received for Rx channel 0.
          */
-        uint32_t in_done_chn_int_raw:1;
+        uint32_t in_done_chn_int_raw: 1;
         /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
          *  The raw interrupt bit turns to high level when the last data pointed by one inlink
          *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
          *  turns to high level when the last data pointed by one inlink descriptor has been
          *  received and no data error is detected for Rx channel 0.
          */
-        uint32_t in_suc_eof_chn_int_raw:1;
+        uint32_t in_suc_eof_chn_int_raw: 1;
         /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
          *  The raw interrupt bit turns to high level when data error is detected only in the
          *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
          *  interrupt is reserved.
          */
-        uint32_t in_err_eof_chn_int_raw:1;
+        uint32_t in_err_eof_chn_int_raw: 1;
         /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
          *  The raw interrupt bit turns to high level when detecting inlink descriptor error
          *  including owner error and the second and third word error of inlink descriptor for
          *  Rx channel 0.
          */
-        uint32_t in_dscr_err_chn_int_raw:1;
+        uint32_t in_dscr_err_chn_int_raw: 1;
         /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
          *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
          *  and receiving data is not completed but there is no more inlink for Rx channel 0.
          */
-        uint32_t in_dscr_empty_chn_int_raw:1;
+        uint32_t in_dscr_empty_chn_int_raw: 1;
         /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  overflow.
          */
-        uint32_t infifo_ovf_chn_int_raw:1;
+        uint32_t infifo_ovf_chn_int_raw: 1;
         /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  underflow.
          */
-        uint32_t infifo_udf_chn_int_raw:1;
-        uint32_t reserved_7:25;
+        uint32_t infifo_udf_chn_int_raw: 1;
+        uint32_t reserved_7: 25;
     };
     uint32_t val;
 } ahb_dma_in_int_raw_chn_reg_t;
@@ -68,32 +68,32 @@ typedef union {
         /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
          *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t in_done_chn_int_st:1;
+        uint32_t in_done_chn_int_st: 1;
         /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
          *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_suc_eof_chn_int_st:1;
+        uint32_t in_suc_eof_chn_int_st: 1;
         /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
          *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_err_eof_chn_int_st:1;
+        uint32_t in_err_eof_chn_int_st: 1;
         /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
          *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_dscr_err_chn_int_st:1;
+        uint32_t in_dscr_err_chn_int_st: 1;
         /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
          *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
          */
-        uint32_t in_dscr_empty_chn_int_st:1;
+        uint32_t in_dscr_empty_chn_int_st: 1;
         /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
          *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_ovf_chn_int_st:1;
+        uint32_t infifo_ovf_chn_int_st: 1;
         /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0;
          *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_udf_chn_int_st:1;
-        uint32_t reserved_7:25;
+        uint32_t infifo_udf_chn_int_st: 1;
+        uint32_t reserved_7: 25;
     };
     uint32_t val;
 } ahb_dma_in_int_st_chn_reg_t;
@@ -106,32 +106,32 @@ typedef union {
         /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
          *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t in_done_chn_int_ena:1;
+        uint32_t in_done_chn_int_ena: 1;
         /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
          *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_suc_eof_chn_int_ena:1;
+        uint32_t in_suc_eof_chn_int_ena: 1;
         /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
          *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_err_eof_chn_int_ena:1;
+        uint32_t in_err_eof_chn_int_ena: 1;
         /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
          *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_dscr_err_chn_int_ena:1;
+        uint32_t in_dscr_err_chn_int_ena: 1;
         /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
          *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
          */
-        uint32_t in_dscr_empty_chn_int_ena:1;
+        uint32_t in_dscr_empty_chn_int_ena: 1;
         /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
          *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_ovf_chn_int_ena:1;
+        uint32_t infifo_ovf_chn_int_ena: 1;
         /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
          *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_udf_chn_int_ena:1;
-        uint32_t reserved_7:25;
+        uint32_t infifo_udf_chn_int_ena: 1;
+        uint32_t reserved_7: 25;
     };
     uint32_t val;
 } ahb_dma_in_int_ena_chn_reg_t;
@@ -144,32 +144,32 @@ typedef union {
         /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
          *  Set this bit to clear the IN_DONE_CH_INT interrupt.
          */
-        uint32_t in_done_chn_int_clr:1;
+        uint32_t in_done_chn_int_clr: 1;
         /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
          *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_suc_eof_chn_int_clr:1;
+        uint32_t in_suc_eof_chn_int_clr: 1;
         /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
          *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_err_eof_chn_int_clr:1;
+        uint32_t in_err_eof_chn_int_clr: 1;
         /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
          *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_dscr_err_chn_int_clr:1;
+        uint32_t in_dscr_err_chn_int_clr: 1;
         /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
          *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
          */
-        uint32_t in_dscr_empty_chn_int_clr:1;
+        uint32_t in_dscr_empty_chn_int_clr: 1;
         /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
          *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_ovf_chn_int_clr:1;
+        uint32_t infifo_ovf_chn_int_clr: 1;
         /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
          *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_udf_chn_int_clr:1;
-        uint32_t reserved_7:25;
+        uint32_t infifo_udf_chn_int_clr: 1;
+        uint32_t reserved_7: 25;
     };
     uint32_t val;
 } ahb_dma_in_int_clr_chn_reg_t;
@@ -183,35 +183,35 @@ typedef union {
          *  The raw interrupt bit turns to high level when the last data pointed by one outlink
          *  descriptor has been transmitted to peripherals for Tx channel 0.
          */
-        uint32_t out_done_chn_int_raw:1;
+        uint32_t out_done_chn_int_raw: 1;
         /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
          *  The raw interrupt bit turns to high level when the last data pointed by one outlink
          *  descriptor has been read from memory for Tx channel 0.
          */
-        uint32_t out_eof_chn_int_raw:1;
+        uint32_t out_eof_chn_int_raw: 1;
         /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
          *  The raw interrupt bit turns to high level when detecting outlink descriptor error
          *  including owner error and the second and third word error of outlink descriptor for
          *  Tx channel 0.
          */
-        uint32_t out_dscr_err_chn_int_raw:1;
+        uint32_t out_dscr_err_chn_int_raw: 1;
         /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
          *  The raw interrupt bit turns to high level when data corresponding a outlink
          *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
          *  channel 0.
          */
-        uint32_t out_total_eof_chn_int_raw:1;
+        uint32_t out_total_eof_chn_int_raw: 1;
         /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
          *  overflow.
          */
-        uint32_t outfifo_ovf_chn_int_raw:1;
+        uint32_t outfifo_ovf_chn_int_raw: 1;
         /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
          *  underflow.
          */
-        uint32_t outfifo_udf_chn_int_raw:1;
-        uint32_t reserved_6:26;
+        uint32_t outfifo_udf_chn_int_raw: 1;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_out_int_raw_chn_reg_t;
@@ -224,28 +224,28 @@ typedef union {
         /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
          *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t out_done_chn_int_st:1;
+        uint32_t out_done_chn_int_st: 1;
         /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
          *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t out_eof_chn_int_st:1;
+        uint32_t out_eof_chn_int_st: 1;
         /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
          *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t out_dscr_err_chn_int_st:1;
+        uint32_t out_dscr_err_chn_int_st: 1;
         /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
          *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t out_total_eof_chn_int_st:1;
+        uint32_t out_total_eof_chn_int_st: 1;
         /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_ovf_chn_int_st:1;
+        uint32_t outfifo_ovf_chn_int_st: 1;
         /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_udf_chn_int_st:1;
-        uint32_t reserved_6:26;
+        uint32_t outfifo_udf_chn_int_st: 1;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_out_int_st_chn_reg_t;
@@ -258,28 +258,28 @@ typedef union {
         /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
          *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t out_done_chn_int_ena:1;
+        uint32_t out_done_chn_int_ena: 1;
         /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
          *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t out_eof_chn_int_ena:1;
+        uint32_t out_eof_chn_int_ena: 1;
         /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
          *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t out_dscr_err_chn_int_ena:1;
+        uint32_t out_dscr_err_chn_int_ena: 1;
         /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
          *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t out_total_eof_chn_int_ena:1;
+        uint32_t out_total_eof_chn_int_ena: 1;
         /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_ovf_chn_int_ena:1;
+        uint32_t outfifo_ovf_chn_int_ena: 1;
         /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_udf_chn_int_ena:1;
-        uint32_t reserved_6:26;
+        uint32_t outfifo_udf_chn_int_ena: 1;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_out_int_ena_chn_reg_t;
@@ -292,33 +292,32 @@ typedef union {
         /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
          *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t out_done_chn_int_clr:1;
+        uint32_t out_done_chn_int_clr: 1;
         /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
          *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t out_eof_chn_int_clr:1;
+        uint32_t out_eof_chn_int_clr: 1;
         /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
          *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t out_dscr_err_chn_int_clr:1;
+        uint32_t out_dscr_err_chn_int_clr: 1;
         /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
          *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t out_total_eof_chn_int_clr:1;
+        uint32_t out_total_eof_chn_int_clr: 1;
         /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
          *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_ovf_chn_int_clr:1;
+        uint32_t outfifo_ovf_chn_int_clr: 1;
         /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
          *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_udf_chn_int_clr:1;
-        uint32_t reserved_6:26;
+        uint32_t outfifo_udf_chn_int_clr: 1;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_out_int_clr_chn_reg_t;
 
-
 /** Group: Debug Registers */
 /** Type of ahb_test register
  *  reserved
@@ -328,18 +327,17 @@ typedef union {
         /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
          *  reserved
          */
-        uint32_t ahb_testmode:3;
-        uint32_t reserved_3:1;
+        uint32_t ahb_testmode: 3;
+        uint32_t reserved_3: 1;
         /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
          *  reserved
          */
-        uint32_t ahb_testaddr:2;
-        uint32_t reserved_6:26;
+        uint32_t ahb_testaddr: 2;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_ahb_test_reg_t;
 
-
 /** Group: Configuration Registers */
 /** Type of misc_conf register
  *  MISC register
@@ -349,18 +347,18 @@ typedef union {
         /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
          *  Set this bit then clear this bit to reset the internal ahb FSM.
          */
-        uint32_t ahbm_rst_inter:1;
-        uint32_t reserved_1:1;
+        uint32_t ahbm_rst_inter: 1;
+        uint32_t reserved_1: 1;
         /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
          *  Set this bit to disable priority arbitration function.
          */
-        uint32_t arb_pri_dis:1;
+        uint32_t arb_pri_dis: 1;
         /** clk_en : R/W; bitpos: [3]; default: 0;
          *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
          *  registers.
          */
-        uint32_t clk_en:1;
-        uint32_t reserved_4:28;
+        uint32_t clk_en: 1;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } ahb_dma_misc_conf_reg_t;
@@ -373,32 +371,32 @@ typedef union {
         /** in_rst_chn : R/W; bitpos: [0]; default: 0;
          *  This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer.
          */
-        uint32_t in_rst_chn:1;
+        uint32_t in_rst_chn: 1;
         /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t in_loop_test_chn:1;
+        uint32_t in_loop_test_chn: 1;
         /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
          *  descriptor when accessing internal SRAM.
          */
-        uint32_t indscr_burst_en_chn:1;
+        uint32_t indscr_burst_en_chn: 1;
         /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
          *  when accessing internal SRAM.
          */
-        uint32_t in_data_burst_en_chn:1;
+        uint32_t in_data_burst_en_chn: 1;
         /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0;
          *  Set this bit 1 to enable automatic transmitting data from memory to memory via
          *  AHB_DMA.
          */
-        uint32_t mem_trans_en_chn:1;
+        uint32_t mem_trans_en_chn: 1;
         /** in_etm_en_chn : R/W; bitpos: [5]; default: 0;
          *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
          *  task.
          */
-        uint32_t in_etm_en_chn:1;
-        uint32_t reserved_6:26;
+        uint32_t in_etm_en_chn: 1;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_in_conf0_chn_reg_t;
@@ -408,12 +406,12 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:12;
+        uint32_t reserved_0: 12;
         /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
          *  Set this bit to enable checking the owner attribute of the link descriptor.
          */
-        uint32_t in_check_owner_chn:1;
-        uint32_t reserved_13:19;
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
     };
     uint32_t val;
 } ahb_dma_in_conf1_chn_reg_t;
@@ -426,12 +424,12 @@ typedef union {
         /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
          *  This register stores the data popping from AHB_DMA FIFO.
          */
-        uint32_t infifo_rdata_chn:12;
+        uint32_t infifo_rdata_chn: 12;
         /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
          *  Set this bit to pop data from AHB_DMA FIFO.
          */
-        uint32_t infifo_pop_chn:1;
-        uint32_t reserved_13:19;
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
     };
     uint32_t val;
 } ahb_dma_in_pop_chn_reg_t;
@@ -445,25 +443,25 @@ typedef union {
          *  Set this bit to return to current inlink descriptor's address when there are some
          *  errors in current receiving data.
          */
-        uint32_t inlink_auto_ret_chn:1;
+        uint32_t inlink_auto_ret_chn: 1;
         /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
          *  Set this bit to stop dealing with the inlink descriptors.
          */
-        uint32_t inlink_stop_chn:1;
+        uint32_t inlink_stop_chn: 1;
         /** inlink_start_chn : WT; bitpos: [2]; default: 0;
          *  Set this bit to start dealing with the inlink descriptors.
          */
-        uint32_t inlink_start_chn:1;
+        uint32_t inlink_start_chn: 1;
         /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
          *  Set this bit to mount a new inlink descriptor.
          */
-        uint32_t inlink_restart_chn:1;
+        uint32_t inlink_restart_chn: 1;
         /** inlink_park_chn : RO; bitpos: [4]; default: 1;
          *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
          *  working.
          */
-        uint32_t inlink_park_chn:1;
-        uint32_t reserved_5:27;
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
     };
     uint32_t val;
 } ahb_dma_in_link_chn_reg_t;
@@ -473,12 +471,12 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:12;
+        uint32_t reserved_0: 12;
         /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
          *  Set this bit to enable checking the owner attribute of the link descriptor.
          */
-        uint32_t out_check_owner_chn:1;
-        uint32_t reserved_13:19;
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
     };
     uint32_t val;
 } ahb_dma_out_conf1_chn_reg_t;
@@ -491,12 +489,12 @@ typedef union {
         /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
          *  This register stores the data that need to be pushed into AHB_DMA FIFO.
          */
-        uint32_t outfifo_wdata_chn:9;
+        uint32_t outfifo_wdata_chn: 9;
         /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
          *  Set this bit to push data into AHB_DMA FIFO.
          */
-        uint32_t outfifo_push_chn:1;
-        uint32_t reserved_10:22;
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } ahb_dma_out_push_chn_reg_t;
@@ -509,21 +507,21 @@ typedef union {
         /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
          *  Set this bit to stop dealing with the outlink descriptors.
          */
-        uint32_t outlink_stop_chn:1;
+        uint32_t outlink_stop_chn: 1;
         /** outlink_start_chn : WT; bitpos: [1]; default: 0;
          *  Set this bit to start dealing with the outlink descriptors.
          */
-        uint32_t outlink_start_chn:1;
+        uint32_t outlink_start_chn: 1;
         /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
          *  Set this bit to restart a new outlink from the last address.
          */
-        uint32_t outlink_restart_chn:1;
+        uint32_t outlink_restart_chn: 1;
         /** outlink_park_chn : RO; bitpos: [3]; default: 1;
          *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
          *  is working.
          */
-        uint32_t outlink_park_chn:1;
-        uint32_t reserved_4:28;
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } ahb_dma_out_link_chn_reg_t;
@@ -536,37 +534,37 @@ typedef union {
         /** out_rst_chn : R/W; bitpos: [0]; default: 0;
          *  This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer.
          */
-        uint32_t out_rst_chn:1;
+        uint32_t out_rst_chn: 1;
         /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t out_loop_test_chn:1;
+        uint32_t out_loop_test_chn: 1;
         /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
          *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
          *  has been transmitted.
          */
-        uint32_t out_auto_wrback_chn:1;
+        uint32_t out_auto_wrback_chn: 1;
         /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
          *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
          *  generated when data need to transmit has been popped from FIFO in AHB_DMA
          */
-        uint32_t out_eof_mode_chn:1;
+        uint32_t out_eof_mode_chn: 1;
         /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
          *  descriptor when accessing internal SRAM.
          */
-        uint32_t outdscr_burst_en_chn:1;
+        uint32_t outdscr_burst_en_chn: 1;
         /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
          *  when accessing internal SRAM.
          */
-        uint32_t out_data_burst_en_chn:1;
+        uint32_t out_data_burst_en_chn: 1;
         /** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
          *  Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm
          *  task.
          */
-        uint32_t out_etm_en_chn:1;
-        uint32_t reserved_7:25;
+        uint32_t out_etm_en_chn: 1;
+        uint32_t reserved_7: 25;
     };
     uint32_t val;
 } ahb_dma_out_conf0_chn_reg_t;
@@ -579,7 +577,7 @@ typedef union {
         /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
          *  This register is used to config ch0 of tx crc initial value
          */
-        uint32_t out_crc_init_data_chn:32;
+        uint32_t out_crc_init_data_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_crc_init_data_chn_reg_t;
@@ -594,12 +592,12 @@ typedef union {
         /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_width_chn:2;
+        uint32_t tx_crc_width_chn: 2;
         /** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_lautch_flga_chn:1;
-        uint32_t reserved_3:29;
+        uint32_t tx_crc_lautch_flga_chn: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } ahb_dma_tx_crc_width_chn_reg_t;
@@ -612,8 +610,8 @@ typedef union {
         /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
          *  This register is used to clear ch0 of tx crc result
          */
-        uint32_t out_crc_clear_chn_reg:1;
-        uint32_t reserved_1:31;
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } ahb_dma_out_crc_clear_chn_reg_t;
@@ -626,7 +624,7 @@ typedef union {
         /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
          *  This register is used to store result ch0 of tx
          */
-        uint32_t out_crc_final_result_chn:32;
+        uint32_t out_crc_final_result_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_crc_final_result_chn_reg_t;
@@ -639,7 +637,7 @@ typedef union {
         /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
          *  This register is used to enable tx ch0 crc 32bit on/off
          */
-        uint32_t tx_crc_en_wr_data_chn:32;
+        uint32_t tx_crc_en_wr_data_chn: 32;
     };
     uint32_t val;
 } ahb_dma_tx_crc_en_wr_data_chn_reg_t;
@@ -652,7 +650,7 @@ typedef union {
         /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_en_addr_chn:32;
+        uint32_t tx_crc_en_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_tx_crc_en_addr_chn_reg_t;
@@ -665,8 +663,8 @@ typedef union {
         /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_data_en_wr_data_chn:8;
-        uint32_t reserved_8:24;
+        uint32_t tx_crc_data_en_wr_data_chn: 8;
+        uint32_t reserved_8: 24;
     };
     uint32_t val;
 } ahb_dma_tx_crc_data_en_wr_data_chn_reg_t;
@@ -679,7 +677,7 @@ typedef union {
         /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_data_en_addr_chn:32;
+        uint32_t tx_crc_data_en_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_tx_crc_data_en_addr_chn_reg_t;
@@ -692,8 +690,8 @@ typedef union {
         /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_ch_arb_weigh_chn:4;
-        uint32_t reserved_4:28;
+        uint32_t tx_ch_arb_weigh_chn: 4;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } ahb_dma_tx_ch_arb_weigh_chn_reg_t;
@@ -706,8 +704,8 @@ typedef union {
         /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
          *  reserved
          */
-        uint32_t tx_arb_weigh_opt_dir_chn:1;
-        uint32_t reserved_1:31;
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
@@ -720,7 +718,7 @@ typedef union {
         /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
          *  This register is used to config ch0 of rx crc initial value
          */
-        uint32_t in_crc_init_data_chn:32;
+        uint32_t in_crc_init_data_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_crc_init_data_chn_reg_t;
@@ -735,12 +733,12 @@ typedef union {
         /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_width_chn:2;
+        uint32_t rx_crc_width_chn: 2;
         /** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_lautch_flga_chn:1;
-        uint32_t reserved_3:29;
+        uint32_t rx_crc_lautch_flga_chn: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } ahb_dma_rx_crc_width_chn_reg_t;
@@ -753,8 +751,8 @@ typedef union {
         /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
          *  This register is used to clear ch0 of rx crc result
          */
-        uint32_t in_crc_clear_chn_reg:1;
-        uint32_t reserved_1:31;
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } ahb_dma_in_crc_clear_chn_reg_t;
@@ -767,7 +765,7 @@ typedef union {
         /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
          *  This register is used to store result ch0 of rx
          */
-        uint32_t in_crc_final_result_chn:32;
+        uint32_t in_crc_final_result_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_crc_final_result_chn_reg_t;
@@ -780,7 +778,7 @@ typedef union {
         /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
          *  This register is used to enable rx ch0 crc 32bit on/off
          */
-        uint32_t rx_crc_en_wr_data_chn:32;
+        uint32_t rx_crc_en_wr_data_chn: 32;
     };
     uint32_t val;
 } ahb_dma_rx_crc_en_wr_data_chn_reg_t;
@@ -793,7 +791,7 @@ typedef union {
         /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_en_addr_chn:32;
+        uint32_t rx_crc_en_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_rx_crc_en_addr_chn_reg_t;
@@ -806,8 +804,8 @@ typedef union {
         /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_data_en_wr_data_chn:8;
-        uint32_t reserved_8:24;
+        uint32_t rx_crc_data_en_wr_data_chn: 8;
+        uint32_t reserved_8: 24;
     };
     uint32_t val;
 } ahb_dma_rx_crc_data_en_wr_data_chn_reg_t;
@@ -820,7 +818,7 @@ typedef union {
         /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_data_en_addr_chn:32;
+        uint32_t rx_crc_data_en_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_rx_crc_data_en_addr_chn_reg_t;
@@ -833,8 +831,8 @@ typedef union {
         /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_ch_arb_weigh_chn:4;
-        uint32_t reserved_4:28;
+        uint32_t rx_ch_arb_weigh_chn: 4;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } ahb_dma_rx_ch_arb_weigh_chn_reg_t;
@@ -847,8 +845,8 @@ typedef union {
         /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
          *  reserved
          */
-        uint32_t rx_arb_weigh_opt_dir_chn:1;
-        uint32_t reserved_1:31;
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
@@ -862,7 +860,7 @@ typedef union {
          *  This register stores the 32 least significant bits of the first inlink descriptor's
          *  address.
          */
-        uint32_t inlink_addr_chn:32;
+        uint32_t inlink_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_link_addr_chn_reg_t;
@@ -876,7 +874,7 @@ typedef union {
          *  This register stores the 32 least significant bits of the first outlink
          *  descriptor's address.
          */
-        uint32_t outlink_addr_chn:32;
+        uint32_t outlink_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_link_addr_chn_reg_t;
@@ -889,7 +887,7 @@ typedef union {
         /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
          *  The start address of accessible address space.
          */
-        uint32_t access_intr_mem_start_addr:32;
+        uint32_t access_intr_mem_start_addr: 32;
     };
     uint32_t val;
 } ahb_dma_intr_mem_start_addr_reg_t;
@@ -904,7 +902,7 @@ typedef union {
          *  The end address of accessible address space. The access address beyond this range
          *  would lead to descriptor error.
          */
-        uint32_t access_intr_mem_end_addr:32;
+        uint32_t access_intr_mem_end_addr: 32;
     };
     uint32_t val;
 } ahb_dma_intr_mem_end_addr_reg_t;
@@ -917,8 +915,8 @@ typedef union {
         /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
          *  This register is used to config arbiter time out value
          */
-        uint32_t arb_timeout_tx:16;
-        uint32_t reserved_16:16;
+        uint32_t arb_timeout_tx: 16;
+        uint32_t reserved_16: 16;
     };
     uint32_t val;
 } ahb_dma_arb_timeout_tx_reg_t;
@@ -931,8 +929,8 @@ typedef union {
         /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0;
          *  This register is used to config arbiter time out value
          */
-        uint32_t arb_timeout_rx:16;
-        uint32_t reserved_16:16;
+        uint32_t arb_timeout_rx: 16;
+        uint32_t reserved_16: 16;
     };
     uint32_t val;
 } ahb_dma_arb_timeout_rx_reg_t;
@@ -945,8 +943,8 @@ typedef union {
         /** weight_en_tx : R/W; bitpos: [0]; default: 0;
          *  This register is used to config arbiter weight function  off/on
          */
-        uint32_t weight_en_tx:1;
-        uint32_t reserved_1:31;
+        uint32_t weight_en_tx: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } ahb_dma_weight_en_tx_reg_t;
@@ -959,13 +957,12 @@ typedef union {
         /** weight_en_rx : R/W; bitpos: [0]; default: 0;
          *  This register is used to config arbiter weight function  off/on
          */
-        uint32_t weight_en_rx:1;
-        uint32_t reserved_1:31;
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } ahb_dma_weight_en_rx_reg_t;
 
-
 /** Group: Version Registers */
 /** Type of date register
  *  Version control register
@@ -975,12 +972,11 @@ typedef union {
         /** date : R/W; bitpos: [31:0]; default: 36712768;
          *  register version.
          */
-        uint32_t date:32;
+        uint32_t date: 32;
     };
     uint32_t val;
 } ahb_dma_date_reg_t;
 
-
 /** Group: Status Registers */
 /** Type of infifo_status_chn register
  *  Receive FIFO status of Rx channel 0
@@ -990,37 +986,37 @@ typedef union {
         /** infifo_full_chn : RO; bitpos: [0]; default: 1;
          *  L1 Rx FIFO full signal for Rx channel 0.
          */
-        uint32_t infifo_full_chn:1;
+        uint32_t infifo_full_chn: 1;
         /** infifo_empty_chn : RO; bitpos: [1]; default: 1;
          *  L1 Rx FIFO empty signal for Rx channel 0.
          */
-        uint32_t infifo_empty_chn:1;
+        uint32_t infifo_empty_chn: 1;
         /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
          *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
          */
-        uint32_t infifo_cnt_chn:6;
-        uint32_t reserved_8:15;
+        uint32_t infifo_cnt_chn: 6;
+        uint32_t reserved_8: 15;
         /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
          *  reserved
          */
-        uint32_t in_remain_under_1b_chn:1;
+        uint32_t in_remain_under_1b_chn: 1;
         /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
          *  reserved
          */
-        uint32_t in_remain_under_2b_chn:1;
+        uint32_t in_remain_under_2b_chn: 1;
         /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
          *  reserved
          */
-        uint32_t in_remain_under_3b_chn:1;
+        uint32_t in_remain_under_3b_chn: 1;
         /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
          *  reserved
          */
-        uint32_t in_remain_under_4b_chn:1;
+        uint32_t in_remain_under_4b_chn: 1;
         /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0;
          *  reserved
          */
-        uint32_t in_buf_hungry_chn:1;
-        uint32_t reserved_28:4;
+        uint32_t in_buf_hungry_chn: 1;
+        uint32_t reserved_28: 4;
     };
     uint32_t val;
 } ahb_dma_infifo_status_chn_reg_t;
@@ -1033,16 +1029,16 @@ typedef union {
         /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
          *  This register stores the current inlink descriptor's address.
          */
-        uint32_t inlink_dscr_addr_chn:18;
+        uint32_t inlink_dscr_addr_chn: 18;
         /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
          *  reserved
          */
-        uint32_t in_dscr_state_chn:2;
+        uint32_t in_dscr_state_chn: 2;
         /** in_state_chn : RO; bitpos: [22:20]; default: 0;
          *  reserved
          */
-        uint32_t in_state_chn:3;
-        uint32_t reserved_23:9;
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
     };
     uint32_t val;
 } ahb_dma_in_state_chn_reg_t;
@@ -1056,7 +1052,7 @@ typedef union {
          *  This register stores the address of the inlink descriptor when the EOF bit in this
          *  descriptor is 1.
          */
-        uint32_t in_suc_eof_des_addr_chn:32;
+        uint32_t in_suc_eof_des_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_suc_eof_des_addr_chn_reg_t;
@@ -1070,7 +1066,7 @@ typedef union {
          *  This register stores the address of the inlink descriptor when there are some
          *  errors in current receiving data. Only used when peripheral is UHCI0.
          */
-        uint32_t in_err_eof_des_addr_chn:32;
+        uint32_t in_err_eof_des_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_err_eof_des_addr_chn_reg_t;
@@ -1083,7 +1079,7 @@ typedef union {
         /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the current inlink descriptor x.
          */
-        uint32_t inlink_dscr_chn:32;
+        uint32_t inlink_dscr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_dscr_chn_reg_t;
@@ -1096,7 +1092,7 @@ typedef union {
         /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the last inlink descriptor x-1.
          */
-        uint32_t inlink_dscr_bf0_chn:32;
+        uint32_t inlink_dscr_bf0_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_dscr_bf0_chn_reg_t;
@@ -1109,7 +1105,7 @@ typedef union {
         /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the second-to-last inlink descriptor x-2.
          */
-        uint32_t inlink_dscr_bf1_chn:32;
+        uint32_t inlink_dscr_bf1_chn: 32;
     };
     uint32_t val;
 } ahb_dma_in_dscr_bf1_chn_reg_t;
@@ -1122,33 +1118,33 @@ typedef union {
         /** outfifo_full_chn : RO; bitpos: [0]; default: 0;
          *  L1 Tx FIFO full signal for Tx channel 0.
          */
-        uint32_t outfifo_full_chn:1;
+        uint32_t outfifo_full_chn: 1;
         /** outfifo_empty_chn : RO; bitpos: [1]; default: 1;
          *  L1 Tx FIFO empty signal for Tx channel 0.
          */
-        uint32_t outfifo_empty_chn:1;
+        uint32_t outfifo_empty_chn: 1;
         /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
          *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
          */
-        uint32_t outfifo_cnt_chn:6;
-        uint32_t reserved_8:15;
+        uint32_t outfifo_cnt_chn: 6;
+        uint32_t reserved_8: 15;
         /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_1b_chn:1;
+        uint32_t out_remain_under_1b_chn: 1;
         /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_2b_chn:1;
+        uint32_t out_remain_under_2b_chn: 1;
         /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_3b_chn:1;
+        uint32_t out_remain_under_3b_chn: 1;
         /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_4b_chn:1;
-        uint32_t reserved_27:5;
+        uint32_t out_remain_under_4b_chn: 1;
+        uint32_t reserved_27: 5;
     };
     uint32_t val;
 } ahb_dma_outfifo_status_chn_reg_t;
@@ -1161,16 +1157,16 @@ typedef union {
         /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
          *  This register stores the current outlink descriptor's address.
          */
-        uint32_t outlink_dscr_addr_chn:18;
+        uint32_t outlink_dscr_addr_chn: 18;
         /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
          *  reserved
          */
-        uint32_t out_dscr_state_chn:2;
+        uint32_t out_dscr_state_chn: 2;
         /** out_state_chn : RO; bitpos: [22:20]; default: 0;
          *  reserved
          */
-        uint32_t out_state_chn:3;
-        uint32_t reserved_23:9;
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
     };
     uint32_t val;
 } ahb_dma_out_state_chn_reg_t;
@@ -1184,7 +1180,7 @@ typedef union {
          *  This register stores the address of the outlink descriptor when the EOF bit in this
          *  descriptor is 1.
          */
-        uint32_t out_eof_des_addr_chn:32;
+        uint32_t out_eof_des_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_eof_des_addr_chn_reg_t;
@@ -1198,7 +1194,7 @@ typedef union {
          *  This register stores the address of the outlink descriptor before the last outlink
          *  descriptor.
          */
-        uint32_t out_eof_bfr_des_addr_chn:32;
+        uint32_t out_eof_bfr_des_addr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
@@ -1211,7 +1207,7 @@ typedef union {
         /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the current outlink descriptor y.
          */
-        uint32_t outlink_dscr_chn:32;
+        uint32_t outlink_dscr_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_dscr_chn_reg_t;
@@ -1224,7 +1220,7 @@ typedef union {
         /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the last outlink descriptor y-1.
          */
-        uint32_t outlink_dscr_bf0_chn:32;
+        uint32_t outlink_dscr_bf0_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_dscr_bf0_chn_reg_t;
@@ -1237,12 +1233,11 @@ typedef union {
         /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the second-to-last inlink descriptor x-2.
          */
-        uint32_t outlink_dscr_bf1_chn:32;
+        uint32_t outlink_dscr_bf1_chn: 32;
     };
     uint32_t val;
 } ahb_dma_out_dscr_bf1_chn_reg_t;
 
-
 /** Group: Priority Registers */
 /** Type of in_pri_chn register
  *  Priority register of Rx channel 0
@@ -1252,8 +1247,8 @@ typedef union {
         /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
          *  The priority of Rx channel 0. The larger of the value the higher of the priority.
          */
-        uint32_t rx_pri_chn:4;
-        uint32_t reserved_4:28;
+        uint32_t rx_pri_chn: 4;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } ahb_dma_in_pri_chn_reg_t;
@@ -1266,13 +1261,12 @@ typedef union {
         /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
          *  The priority of Tx channel 0. The larger of the value the higher of the priority.
          */
-        uint32_t tx_pri_chn:4;
-        uint32_t reserved_4:28;
+        uint32_t tx_pri_chn: 4;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } ahb_dma_out_pri_chn_reg_t;
 
-
 /** Group: Peripheral Select Registers */
 /** Type of in_peri_sel_chn register
  *  Peripheral selection of Rx channel 0
@@ -1284,8 +1278,8 @@ typedef union {
          *  UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
          *  RMT,11~15: Dummy
          */
-        uint32_t peri_in_sel_chn:6;
-        uint32_t reserved_6:26;
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_in_peri_sel_chn_reg_t;
@@ -1300,26 +1294,24 @@ typedef union {
          *  UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
          *  RMT,11~15: Dummy
          */
-        uint32_t peri_out_sel_chn:6;
-        uint32_t reserved_6:26;
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } ahb_dma_out_peri_sel_chn_reg_t;
 
-
-
 typedef struct {
-    volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw;
-    volatile ahb_dma_in_int_st_chn_reg_t in_int_st;
-    volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena;
-    volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr;
+    volatile ahb_dma_in_int_raw_chn_reg_t raw;
+    volatile ahb_dma_in_int_st_chn_reg_t st;
+    volatile ahb_dma_in_int_ena_chn_reg_t ena;
+    volatile ahb_dma_in_int_clr_chn_reg_t clr;
 } ahb_dma_in_int_chn_reg_t;
 
 typedef struct {
-    volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw;
-    volatile ahb_dma_out_int_st_chn_reg_t out_int_st;
-    volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena;
-    volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr;
+    volatile ahb_dma_out_int_raw_chn_reg_t raw;
+    volatile ahb_dma_out_int_st_chn_reg_t st;
+    volatile ahb_dma_out_int_ena_chn_reg_t ena;
+    volatile ahb_dma_out_int_clr_chn_reg_t clr;
 } ahb_dma_out_int_chn_reg_t;
 
 typedef struct {
@@ -1410,7 +1402,6 @@ typedef struct {
 
 extern ahb_dma_dev_t AHB_DMA;
 
-
 #ifndef __cplusplus
 _Static_assert(sizeof(ahb_dma_dev_t) == 0x3DC, "Invalid size of ahb_dma_dev_t structure");
 #endif
diff --git a/components/soc/esp32p4/include/soc/axi_dma_struct.h b/components/soc/esp32p4/include/soc/axi_dma_struct.h
index da0d436759..52e73e65fa 100644
--- a/components/soc/esp32p4/include/soc/axi_dma_struct.h
+++ b/components/soc/esp32p4/include/soc/axi_dma_struct.h
@@ -20,62 +20,62 @@ typedef union {
          *  The raw interrupt bit turns to high level when the last data pointed by one inlink
          *  descriptor has been received for Rx channel 0.
          */
-        uint32_t in_done_chn_int_raw:1;
+        uint32_t in_done_chn_int_raw: 1;
         /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
          *  The raw interrupt bit turns to high level when the last data pointed by one inlink
          *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
          *  turns to high level when the last data pointed by one inlink descriptor has been
          *  received and no data error is detected for Rx channel 0.
          */
-        uint32_t in_suc_eof_chn_int_raw:1;
+        uint32_t in_suc_eof_chn_int_raw: 1;
         /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
          *  The raw interrupt bit turns to high level when data error is detected only in the
          *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
          *  interrupt is reserved.
          */
-        uint32_t in_err_eof_chn_int_raw:1;
+        uint32_t in_err_eof_chn_int_raw: 1;
         /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
          *  The raw interrupt bit turns to high level when detecting inlink descriptor error
          *  including owner error and the second and third word error of inlink descriptor for
          *  Rx channel 0.
          */
-        uint32_t in_dscr_err_chn_int_raw:1;
+        uint32_t in_dscr_err_chn_int_raw: 1;
         /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
          *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
          *  and receiving data is not completed but there is no more inlink for Rx channel 0.
          */
-        uint32_t in_dscr_empty_chn_int_raw:1;
+        uint32_t in_dscr_empty_chn_int_raw: 1;
         /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  overflow.
          */
-        uint32_t infifo_l1_ovf_chn_int_raw:1;
+        uint32_t infifo_l1_ovf_chn_int_raw: 1;
         /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  underflow.
          */
-        uint32_t infifo_l1_udf_chn_int_raw:1;
+        uint32_t infifo_l1_udf_chn_int_raw: 1;
         /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  overflow.
          */
-        uint32_t infifo_l2_ovf_chn_int_raw:1;
+        uint32_t infifo_l2_ovf_chn_int_raw: 1;
         /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  underflow.
          */
-        uint32_t infifo_l2_udf_chn_int_raw:1;
+        uint32_t infifo_l2_udf_chn_int_raw: 1;
         /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  overflow.
          */
-        uint32_t infifo_l3_ovf_chn_int_raw:1;
+        uint32_t infifo_l3_ovf_chn_int_raw: 1;
         /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
          *  underflow.
          */
-        uint32_t infifo_l3_udf_chn_int_raw:1;
-        uint32_t reserved_11:21;
+        uint32_t infifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
 } axi_dma_in_int_raw_chn_reg_t;
@@ -88,48 +88,48 @@ typedef union {
         /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
          *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t in_done_chn_int_st:1;
+        uint32_t in_done_chn_int_st: 1;
         /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
          *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_suc_eof_chn_int_st:1;
+        uint32_t in_suc_eof_chn_int_st: 1;
         /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
          *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_err_eof_chn_int_st:1;
+        uint32_t in_err_eof_chn_int_st: 1;
         /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
          *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_dscr_err_chn_int_st:1;
+        uint32_t in_dscr_err_chn_int_st: 1;
         /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
          *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
          */
-        uint32_t in_dscr_empty_chn_int_st:1;
+        uint32_t in_dscr_empty_chn_int_st: 1;
         /** infifo_l1_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
          *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_l1_ovf_chn_int_st:1;
+        uint32_t infifo_l1_ovf_chn_int_st: 1;
         /** infifo_l1_udf_chn_int_st : RO; bitpos: [6]; default: 0;
          *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_l1_udf_chn_int_st:1;
+        uint32_t infifo_l1_udf_chn_int_st: 1;
         /** infifo_l2_ovf_chn_int_st : RO; bitpos: [7]; default: 0;
          *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t infifo_l2_ovf_chn_int_st:1;
+        uint32_t infifo_l2_ovf_chn_int_st: 1;
         /** infifo_l2_udf_chn_int_st : RO; bitpos: [8]; default: 0;
          *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t infifo_l2_udf_chn_int_st:1;
+        uint32_t infifo_l2_udf_chn_int_st: 1;
         /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0;
          *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
          */
-        uint32_t infifo_l3_ovf_chn_int_st:1;
+        uint32_t infifo_l3_ovf_chn_int_st: 1;
         /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0;
          *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
          */
-        uint32_t infifo_l3_udf_chn_int_st:1;
-        uint32_t reserved_11:21;
+        uint32_t infifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
 } axi_dma_in_int_st_chn_reg_t;
@@ -142,48 +142,48 @@ typedef union {
         /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
          *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t in_done_chn_int_ena:1;
+        uint32_t in_done_chn_int_ena: 1;
         /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
          *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_suc_eof_chn_int_ena:1;
+        uint32_t in_suc_eof_chn_int_ena: 1;
         /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
          *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_err_eof_chn_int_ena:1;
+        uint32_t in_err_eof_chn_int_ena: 1;
         /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
          *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_dscr_err_chn_int_ena:1;
+        uint32_t in_dscr_err_chn_int_ena: 1;
         /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
          *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
          */
-        uint32_t in_dscr_empty_chn_int_ena:1;
+        uint32_t in_dscr_empty_chn_int_ena: 1;
         /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
          *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_l1_ovf_chn_int_ena:1;
+        uint32_t infifo_l1_ovf_chn_int_ena: 1;
         /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
          *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_l1_udf_chn_int_ena:1;
+        uint32_t infifo_l1_udf_chn_int_ena: 1;
         /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0;
          *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t infifo_l2_ovf_chn_int_ena:1;
+        uint32_t infifo_l2_ovf_chn_int_ena: 1;
         /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0;
          *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t infifo_l2_udf_chn_int_ena:1;
+        uint32_t infifo_l2_udf_chn_int_ena: 1;
         /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0;
          *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
          */
-        uint32_t infifo_l3_ovf_chn_int_ena:1;
+        uint32_t infifo_l3_ovf_chn_int_ena: 1;
         /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0;
          *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
          */
-        uint32_t infifo_l3_udf_chn_int_ena:1;
-        uint32_t reserved_11:21;
+        uint32_t infifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
 } axi_dma_in_int_ena_chn_reg_t;
@@ -196,48 +196,48 @@ typedef union {
         /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
          *  Set this bit to clear the IN_DONE_CH_INT interrupt.
          */
-        uint32_t in_done_chn_int_clr:1;
+        uint32_t in_done_chn_int_clr: 1;
         /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
          *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_suc_eof_chn_int_clr:1;
+        uint32_t in_suc_eof_chn_int_clr: 1;
         /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
          *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_err_eof_chn_int_clr:1;
+        uint32_t in_err_eof_chn_int_clr: 1;
         /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
          *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_dscr_err_chn_int_clr:1;
+        uint32_t in_dscr_err_chn_int_clr: 1;
         /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
          *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
          */
-        uint32_t in_dscr_empty_chn_int_clr:1;
+        uint32_t in_dscr_empty_chn_int_clr: 1;
         /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
          *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_l1_ovf_chn_int_clr:1;
+        uint32_t infifo_l1_ovf_chn_int_clr: 1;
         /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
          *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t infifo_l1_udf_chn_int_clr:1;
+        uint32_t infifo_l1_udf_chn_int_clr: 1;
         /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0;
          *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t infifo_l2_ovf_chn_int_clr:1;
+        uint32_t infifo_l2_ovf_chn_int_clr: 1;
         /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0;
          *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t infifo_l2_udf_chn_int_clr:1;
+        uint32_t infifo_l2_udf_chn_int_clr: 1;
         /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0;
          *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
          */
-        uint32_t infifo_l3_ovf_chn_int_clr:1;
+        uint32_t infifo_l3_ovf_chn_int_clr: 1;
         /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0;
          *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
          */
-        uint32_t infifo_l3_udf_chn_int_clr:1;
-        uint32_t reserved_11:21;
+        uint32_t infifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
 } axi_dma_in_int_clr_chn_reg_t;
@@ -250,39 +250,39 @@ typedef union {
         /** in_rst_chn : R/W; bitpos: [0]; default: 0;
          *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
          */
-        uint32_t in_rst_chn:1;
+        uint32_t in_rst_chn: 1;
         /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t in_loop_test_chn:1;
+        uint32_t in_loop_test_chn: 1;
         /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0;
          *  Set this bit 1 to enable automatic transmitting data from memory to memory via
          *  AXI_DMA.
          */
-        uint32_t mem_trans_en_chn:1;
+        uint32_t mem_trans_en_chn: 1;
         /** in_etm_en_chn : R/W; bitpos: [3]; default: 0;
          *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
          *  task.
          */
-        uint32_t in_etm_en_chn:1;
+        uint32_t in_etm_en_chn: 1;
         /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0;
          *  3'b000-3'b100:burst length 8byte~128byte
          */
-        uint32_t in_burst_size_sel_chn:3;
+        uint32_t in_burst_size_sel_chn: 3;
         /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0;
          *  1:mean disable cmd of this ch0
          */
-        uint32_t in_cmd_disable_chn:1;
+        uint32_t in_cmd_disable_chn: 1;
         /** in_ecc_aec_en_chn : R/W; bitpos: [8]; default: 0;
          *  1: mean access ecc or aes domain,0: mean not
          */
-        uint32_t in_ecc_aec_en_chn:1;
+        uint32_t in_ecc_aec_en_chn: 1;
         /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
          *  descriptor when accessing internal SRAM.
          */
-        uint32_t indscr_burst_en_chn:1;
-        uint32_t reserved_10:22;
+        uint32_t indscr_burst_en_chn: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_in_conf0_chn_reg_t;
@@ -292,12 +292,12 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:12;
+        uint32_t reserved_0: 12;
         /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
          *  Set this bit to enable checking the owner attribute of the link descriptor.
          */
-        uint32_t in_check_owner_chn:1;
-        uint32_t reserved_13:19;
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
     };
     uint32_t val;
 } axi_dma_in_conf1_chn_reg_t;
@@ -310,92 +310,92 @@ typedef union {
         /** infifo_l3_full_chn : RO; bitpos: [0]; default: 1;
          *  L3 Rx FIFO full signal for Rx channel 0.
          */
-        uint32_t infifo_l3_full_chn:1;
+        uint32_t infifo_l3_full_chn: 1;
         /** infifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
          *  L3 Rx FIFO empty signal for Rx channel 0.
          */
-        uint32_t infifo_l3_empty_chn:1;
+        uint32_t infifo_l3_empty_chn: 1;
         /** infifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
          *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
          */
-        uint32_t infifo_l3_cnt_chn:6;
+        uint32_t infifo_l3_cnt_chn: 6;
         /** infifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
          *  L3 Rx FIFO under flow signal for Rx channel 0.
          */
-        uint32_t infifo_l3_udf_chn:1;
+        uint32_t infifo_l3_udf_chn: 1;
         /** infifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
          *  L3 Rx FIFO over flow signal for Rx channel 0.
          */
-        uint32_t infifo_l3_ovf_chn:1;
+        uint32_t infifo_l3_ovf_chn: 1;
         /** infifo_l1_full_chn : RO; bitpos: [10]; default: 0;
          *  L1 Rx FIFO full signal for Rx channel 0.
          */
-        uint32_t infifo_l1_full_chn:1;
+        uint32_t infifo_l1_full_chn: 1;
         /** infifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
          *  L1 Rx FIFO empty signal for Rx channel 0.
          */
-        uint32_t infifo_l1_empty_chn:1;
+        uint32_t infifo_l1_empty_chn: 1;
         /** infifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
          *  L1 Rx FIFO under flow signal for Rx channel 0.
          */
-        uint32_t infifo_l1_udf_chn:1;
+        uint32_t infifo_l1_udf_chn: 1;
         /** infifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
          *  L1 Rx FIFO over flow signal for Rx channel 0.
          */
-        uint32_t infifo_l1_ovf_chn:1;
+        uint32_t infifo_l1_ovf_chn: 1;
         /** infifo_l2_full_chn : RO; bitpos: [14]; default: 0;
          *  L2 Rx RAM full signal for Rx channel 0.
          */
-        uint32_t infifo_l2_full_chn:1;
+        uint32_t infifo_l2_full_chn: 1;
         /** infifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
          *  L2 Rx RAM empty signal for Rx channel 0.
          */
-        uint32_t infifo_l2_empty_chn:1;
+        uint32_t infifo_l2_empty_chn: 1;
         /** infifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
          *  L2 Rx FIFO under flow signal for Rx channel 0.
          */
-        uint32_t infifo_l2_udf_chn:1;
+        uint32_t infifo_l2_udf_chn: 1;
         /** infifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
          *  L2 Rx FIFO over flow signal for Rx channel 0.
          */
-        uint32_t infifo_l2_ovf_chn:1;
-        uint32_t reserved_18:5;
+        uint32_t infifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
         /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_1b_chn:1;
+        uint32_t in_remain_under_1b_chn: 1;
         /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_2b_chn:1;
+        uint32_t in_remain_under_2b_chn: 1;
         /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_3b_chn:1;
+        uint32_t in_remain_under_3b_chn: 1;
         /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_4b_chn:1;
+        uint32_t in_remain_under_4b_chn: 1;
         /** in_remain_under_5b_chn : RO; bitpos: [27]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_5b_chn:1;
+        uint32_t in_remain_under_5b_chn: 1;
         /** in_remain_under_6b_chn : RO; bitpos: [28]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_6b_chn:1;
+        uint32_t in_remain_under_6b_chn: 1;
         /** in_remain_under_7b_chn : RO; bitpos: [29]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_7b_chn:1;
+        uint32_t in_remain_under_7b_chn: 1;
         /** in_remain_under_8b_chn : RO; bitpos: [30]; default: 0;
          *  reserved
          */
-        uint32_t in_remain_under_8b_chn:1;
+        uint32_t in_remain_under_8b_chn: 1;
         /** in_buf_hungry_chn : RO; bitpos: [31]; default: 0;
          *  reserved
          */
-        uint32_t in_buf_hungry_chn:1;
+        uint32_t in_buf_hungry_chn: 1;
     };
     uint32_t val;
 } axi_dma_infifo_status_chn_reg_t;
@@ -408,12 +408,12 @@ typedef union {
         /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
          *  This register stores the data popping from AXI_DMA FIFO.
          */
-        uint32_t infifo_rdata_chn:12;
+        uint32_t infifo_rdata_chn: 12;
         /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
          *  Set this bit to pop data from AXI_DMA FIFO.
          */
-        uint32_t infifo_pop_chn:1;
-        uint32_t reserved_13:19;
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
     };
     uint32_t val;
 } axi_dma_in_pop_chn_reg_t;
@@ -427,25 +427,25 @@ typedef union {
          *  Set this bit to return to current inlink descriptor's address when there are some
          *  errors in current receiving data.
          */
-        uint32_t inlink_auto_ret_chn:1;
+        uint32_t inlink_auto_ret_chn: 1;
         /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
          *  Set this bit to stop dealing with the inlink descriptors.
          */
-        uint32_t inlink_stop_chn:1;
+        uint32_t inlink_stop_chn: 1;
         /** inlink_start_chn : WT; bitpos: [2]; default: 0;
          *  Set this bit to start dealing with the inlink descriptors.
          */
-        uint32_t inlink_start_chn:1;
+        uint32_t inlink_start_chn: 1;
         /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
          *  Set this bit to mount a new inlink descriptor.
          */
-        uint32_t inlink_restart_chn:1;
+        uint32_t inlink_restart_chn: 1;
         /** inlink_park_chn : RO; bitpos: [4]; default: 1;
          *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
          *  working.
          */
-        uint32_t inlink_park_chn:1;
-        uint32_t reserved_5:27;
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
     };
     uint32_t val;
 } axi_dma_in_link1_chn_reg_t;
@@ -459,7 +459,7 @@ typedef union {
          *  This register stores the 20 least significant bits of the first inlink descriptor's
          *  address.
          */
-        uint32_t inlink_addr_chn:32;
+        uint32_t inlink_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_link2_chn_reg_t;
@@ -472,16 +472,16 @@ typedef union {
         /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
          *  This register stores the current inlink descriptor's address.
          */
-        uint32_t inlink_dscr_addr_chn:18;
+        uint32_t inlink_dscr_addr_chn: 18;
         /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
          *  reserved
          */
-        uint32_t in_dscr_state_chn:2;
+        uint32_t in_dscr_state_chn: 2;
         /** in_state_chn : RO; bitpos: [22:20]; default: 0;
          *  reserved
          */
-        uint32_t in_state_chn:3;
-        uint32_t reserved_23:9;
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
     };
     uint32_t val;
 } axi_dma_in_state_chn_reg_t;
@@ -495,7 +495,7 @@ typedef union {
          *  This register stores the address of the inlink descriptor when the EOF bit in this
          *  descriptor is 1.
          */
-        uint32_t in_suc_eof_des_addr_chn:32;
+        uint32_t in_suc_eof_des_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_suc_eof_des_addr_chn_reg_t;
@@ -509,7 +509,7 @@ typedef union {
          *  This register stores the address of the inlink descriptor when there are some
          *  errors in current receiving data. Only used when peripheral is UHCI0.
          */
-        uint32_t in_err_eof_des_addr_chn:32;
+        uint32_t in_err_eof_des_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_err_eof_des_addr_chn_reg_t;
@@ -522,7 +522,7 @@ typedef union {
         /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the current inlink descriptor x.
          */
-        uint32_t inlink_dscr_chn:32;
+        uint32_t inlink_dscr_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_dscr_chn_reg_t;
@@ -535,7 +535,7 @@ typedef union {
         /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the last inlink descriptor x-1.
          */
-        uint32_t inlink_dscr_bf0_chn:32;
+        uint32_t inlink_dscr_bf0_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_dscr_bf0_chn_reg_t;
@@ -548,7 +548,7 @@ typedef union {
         /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the second-to-last inlink descriptor x-2.
          */
-        uint32_t inlink_dscr_bf1_chn:32;
+        uint32_t inlink_dscr_bf1_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_dscr_bf1_chn_reg_t;
@@ -561,16 +561,16 @@ typedef union {
         /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
          *  The priority of Rx channel 0. The larger of the value the higher of the priority.
          */
-        uint32_t rx_pri_chn:4;
+        uint32_t rx_pri_chn: 4;
         /** rx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
          *  The weight of Rx channel 0
          */
-        uint32_t rx_ch_arb_weigh_chn:4;
+        uint32_t rx_ch_arb_weigh_chn: 4;
         /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
          *  0: mean not optimazation weight function ,1: mean optimazation
          */
-        uint32_t rx_arb_weigh_opt_dir_chn:1;
-        uint32_t reserved_9:23;
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
     };
     uint32_t val;
 } axi_dma_in_pri_chn_reg_t;
@@ -584,8 +584,8 @@ typedef union {
          *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
          *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
          */
-        uint32_t peri_in_sel_chn:6;
-        uint32_t reserved_6:26;
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } axi_dma_in_peri_sel_chn_reg_t;
@@ -598,7 +598,7 @@ typedef union {
         /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
          *  This register is used to config ch0 of rx crc initial value
          */
-        uint32_t in_crc_init_data_chn:32;
+        uint32_t in_crc_init_data_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_crc_init_data_chn_reg_t;
@@ -613,12 +613,12 @@ typedef union {
         /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_width_chn:2;
+        uint32_t rx_crc_width_chn: 2;
         /** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_lautch_flga_chn:1;
-        uint32_t reserved_3:29;
+        uint32_t rx_crc_lautch_flga_chn: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } axi_dma_rx_crc_width_chn_reg_t;
@@ -631,8 +631,8 @@ typedef union {
         /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
          *  This register is used to clear ch0 of rx crc result
          */
-        uint32_t in_crc_clear_chn_reg:1;
-        uint32_t reserved_1:31;
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } axi_dma_in_crc_clear_chn_reg_t;
@@ -645,7 +645,7 @@ typedef union {
         /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
          *  This register is used to store result ch0 of rx
          */
-        uint32_t in_crc_final_result_chn:32;
+        uint32_t in_crc_final_result_chn: 32;
     };
     uint32_t val;
 } axi_dma_in_crc_final_result_chn_reg_t;
@@ -658,7 +658,7 @@ typedef union {
         /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
          *  This register is used to enable rx ch0 crc 32bit on/off
          */
-        uint32_t rx_crc_en_wr_data_chn:32;
+        uint32_t rx_crc_en_wr_data_chn: 32;
     };
     uint32_t val;
 } axi_dma_rx_crc_en_wr_data_chn_reg_t;
@@ -671,7 +671,7 @@ typedef union {
         /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_en_addr_chn:32;
+        uint32_t rx_crc_en_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_rx_crc_en_addr_chn_reg_t;
@@ -684,8 +684,8 @@ typedef union {
         /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_data_en_wr_data_chn:16;
-        uint32_t reserved_16:16;
+        uint32_t rx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
     };
     uint32_t val;
 } axi_dma_rx_crc_data_en_wr_data_chn_reg_t;
@@ -698,12 +698,11 @@ typedef union {
         /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t rx_crc_data_en_addr_chn:32;
+        uint32_t rx_crc_data_en_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_rx_crc_data_en_addr_chn_reg_t;
 
-
 /** Group: out */
 /** Type of out_int_raw_chn register
  *  Raw status interrupt of channel0
@@ -714,55 +713,55 @@ typedef union {
          *  The raw interrupt bit turns to high level when the last data pointed by one outlink
          *  descriptor has been transmitted to peripherals for Tx channel0.
          */
-        uint32_t out_done_chn_int_raw:1;
+        uint32_t out_done_chn_int_raw: 1;
         /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
          *  The raw interrupt bit turns to high level when the last data pointed by one outlink
          *  descriptor has been read from memory for Tx channel0.
          */
-        uint32_t out_eof_chn_int_raw:1;
+        uint32_t out_eof_chn_int_raw: 1;
         /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
          *  The raw interrupt bit turns to high level when detecting outlink descriptor error
          *  including owner error and the second and third word error of outlink descriptor for
          *  Tx channel0.
          */
-        uint32_t out_dscr_err_chn_int_raw:1;
+        uint32_t out_dscr_err_chn_int_raw: 1;
         /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
          *  The raw interrupt bit turns to high level when data corresponding a outlink
          *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
          *  channel0.
          */
-        uint32_t out_total_eof_chn_int_raw:1;
+        uint32_t out_total_eof_chn_int_raw: 1;
         /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
          *  overflow.
          */
-        uint32_t outfifo_l1_ovf_chn_int_raw:1;
+        uint32_t outfifo_l1_ovf_chn_int_raw: 1;
         /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
          *  underflow.
          */
-        uint32_t outfifo_l1_udf_chn_int_raw:1;
+        uint32_t outfifo_l1_udf_chn_int_raw: 1;
         /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
          *  overflow.
          */
-        uint32_t outfifo_l2_ovf_chn_int_raw:1;
+        uint32_t outfifo_l2_ovf_chn_int_raw: 1;
         /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
          *  underflow.
          */
-        uint32_t outfifo_l2_udf_chn_int_raw:1;
+        uint32_t outfifo_l2_udf_chn_int_raw: 1;
         /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
          *  overflow.
          */
-        uint32_t outfifo_l3_ovf_chn_int_raw:1;
+        uint32_t outfifo_l3_ovf_chn_int_raw: 1;
         /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
          *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
          *  underflow.
          */
-        uint32_t outfifo_l3_udf_chn_int_raw:1;
-        uint32_t reserved_10:22;
+        uint32_t outfifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_out_int_raw_chn_reg_t;
@@ -775,44 +774,44 @@ typedef union {
         /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
          *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t out_done_chn_int_st:1;
+        uint32_t out_done_chn_int_st: 1;
         /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
          *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t out_eof_chn_int_st:1;
+        uint32_t out_eof_chn_int_st: 1;
         /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
          *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t out_dscr_err_chn_int_st:1;
+        uint32_t out_dscr_err_chn_int_st: 1;
         /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
          *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t out_total_eof_chn_int_st:1;
+        uint32_t out_total_eof_chn_int_st: 1;
         /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_l1_ovf_chn_int_st:1;
+        uint32_t outfifo_l1_ovf_chn_int_st: 1;
         /** outfifo_l1_udf_chn_int_st : RO; bitpos: [5]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_l1_udf_chn_int_st:1;
+        uint32_t outfifo_l1_udf_chn_int_st: 1;
         /** outfifo_l2_ovf_chn_int_st : RO; bitpos: [6]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t outfifo_l2_ovf_chn_int_st:1;
+        uint32_t outfifo_l2_ovf_chn_int_st: 1;
         /** outfifo_l2_udf_chn_int_st : RO; bitpos: [7]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t outfifo_l2_udf_chn_int_st:1;
+        uint32_t outfifo_l2_udf_chn_int_st: 1;
         /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
          */
-        uint32_t outfifo_l3_ovf_chn_int_st:1;
+        uint32_t outfifo_l3_ovf_chn_int_st: 1;
         /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0;
          *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
          */
-        uint32_t outfifo_l3_udf_chn_int_st:1;
-        uint32_t reserved_10:22;
+        uint32_t outfifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_out_int_st_chn_reg_t;
@@ -825,44 +824,44 @@ typedef union {
         /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
          *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t out_done_chn_int_ena:1;
+        uint32_t out_done_chn_int_ena: 1;
         /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
          *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t out_eof_chn_int_ena:1;
+        uint32_t out_eof_chn_int_ena: 1;
         /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
          *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t out_dscr_err_chn_int_ena:1;
+        uint32_t out_dscr_err_chn_int_ena: 1;
         /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
          *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t out_total_eof_chn_int_ena:1;
+        uint32_t out_total_eof_chn_int_ena: 1;
         /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_l1_ovf_chn_int_ena:1;
+        uint32_t outfifo_l1_ovf_chn_int_ena: 1;
         /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_l1_udf_chn_int_ena:1;
+        uint32_t outfifo_l1_udf_chn_int_ena: 1;
         /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t outfifo_l2_ovf_chn_int_ena:1;
+        uint32_t outfifo_l2_ovf_chn_int_ena: 1;
         /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t outfifo_l2_udf_chn_int_ena:1;
+        uint32_t outfifo_l2_udf_chn_int_ena: 1;
         /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
          */
-        uint32_t outfifo_l3_ovf_chn_int_ena:1;
+        uint32_t outfifo_l3_ovf_chn_int_ena: 1;
         /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0;
          *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
          */
-        uint32_t outfifo_l3_udf_chn_int_ena:1;
-        uint32_t reserved_10:22;
+        uint32_t outfifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_out_int_ena_chn_reg_t;
@@ -875,109 +874,109 @@ typedef union {
         /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
          *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t out_done_chn_int_clr:1;
+        uint32_t out_done_chn_int_clr: 1;
         /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
          *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t out_eof_chn_int_clr:1;
+        uint32_t out_eof_chn_int_clr: 1;
         /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
          *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t out_dscr_err_chn_int_clr:1;
+        uint32_t out_dscr_err_chn_int_clr: 1;
         /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
          *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t out_total_eof_chn_int_clr:1;
+        uint32_t out_total_eof_chn_int_clr: 1;
         /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
          *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_l1_ovf_chn_int_clr:1;
+        uint32_t outfifo_l1_ovf_chn_int_clr: 1;
         /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
          *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t outfifo_l1_udf_chn_int_clr:1;
+        uint32_t outfifo_l1_udf_chn_int_clr: 1;
         /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0;
          *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t outfifo_l2_ovf_chn_int_clr:1;
+        uint32_t outfifo_l2_ovf_chn_int_clr: 1;
         /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0;
          *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t outfifo_l2_udf_chn_int_clr:1;
+        uint32_t outfifo_l2_udf_chn_int_clr: 1;
         /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0;
          *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
          */
-        uint32_t outfifo_l3_ovf_chn_int_clr:1;
+        uint32_t outfifo_l3_ovf_chn_int_clr: 1;
         /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0;
          *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
          */
-        uint32_t outfifo_l3_udf_chn_int_clr:1;
-        uint32_t reserved_10:22;
+        uint32_t outfifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_out_int_clr_chn_reg_t;
 
-/** Type of out_conf0_ch0 register
- *  Configure 0 register of Tx channel0
+/** Type of out_conf0_chn register
+ *  Configure 0 register of Tx channelN
  */
 typedef union {
     struct {
-        /** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
          *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
          */
-        uint32_t out_rst_ch0:1;
-        /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+        uint32_t out_rst_chn: 1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t out_loop_test_ch0:1;
-        /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
+        uint32_t out_loop_test_chn: 1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
          *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
          *  has been transmitted.
          */
-        uint32_t out_auto_wrback_ch0:1;
-        /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
+        uint32_t out_auto_wrback_chn: 1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
          *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
          *  generated when data need to transmit has been popped from FIFO in AXI_DMA
          */
-        uint32_t out_eof_mode_ch0:1;
-        /** out_etm_en_ch0 : R/W; bitpos: [4]; default: 0;
+        uint32_t out_eof_mode_chn: 1;
+        /** out_etm_en_chn : R/W; bitpos: [4]; default: 0;
          *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
          *  task.
          */
-        uint32_t out_etm_en_ch0:1;
-        /** out_burst_size_sel_ch0 : R/W; bitpos: [7:5]; default: 0;
+        uint32_t out_etm_en_chn: 1;
+        /** out_burst_size_sel_chn : R/W; bitpos: [7:5]; default: 0;
          *  3'b000-3'b100:burst length 8byte~128byte
          */
-        uint32_t out_burst_size_sel_ch0:3;
-        /** out_cmd_disable_ch0 : R/W; bitpos: [8]; default: 0;
-         *  1:mean disable cmd of this ch0
+        uint32_t out_burst_size_sel_chn: 3;
+        /** out_cmd_disable_chn : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this chn
          */
-        uint32_t out_cmd_disable_ch0:1;
-        /** out_ecc_aec_en_ch0 : R/W; bitpos: [9]; default: 0;
+        uint32_t out_cmd_disable_chn: 1;
+        /** out_ecc_aec_en_chn : R/W; bitpos: [9]; default: 0;
          *  1: mean access ecc or aes domain,0: mean not
          */
-        uint32_t out_ecc_aec_en_ch0:1;
-        /** outdscr_burst_en_ch0 : R/W; bitpos: [10]; default: 0;
+        uint32_t out_ecc_aec_en_chn: 1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [10]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
          *  descriptor when accessing internal SRAM.
          */
-        uint32_t outdscr_burst_en_ch0:1;
-        uint32_t reserved_11:21;
+        uint32_t outdscr_burst_en_chn: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
-} axi_dma_out_conf0_ch0_reg_t;
+} axi_dma_out_conf0_chn_reg_t;
 
 /** Type of out_conf1_chn register
  *  Configure 1 register of Tx channel0
  */
 typedef union {
     struct {
-        uint32_t reserved_0:12;
+        uint32_t reserved_0: 12;
         /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
          *  Set this bit to enable checking the owner attribute of the link descriptor.
          */
-        uint32_t out_check_owner_chn:1;
-        uint32_t reserved_13:19;
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
     };
     uint32_t val;
 } axi_dma_out_conf1_chn_reg_t;
@@ -990,89 +989,89 @@ typedef union {
         /** outfifo_l3_full_chn : RO; bitpos: [0]; default: 0;
          *  L3 Tx FIFO full signal for Tx channel0.
          */
-        uint32_t outfifo_l3_full_chn:1;
+        uint32_t outfifo_l3_full_chn: 1;
         /** outfifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
          *  L3 Tx FIFO empty signal for Tx channel0.
          */
-        uint32_t outfifo_l3_empty_chn:1;
+        uint32_t outfifo_l3_empty_chn: 1;
         /** outfifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
          *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
          */
-        uint32_t outfifo_l3_cnt_chn:6;
+        uint32_t outfifo_l3_cnt_chn: 6;
         /** outfifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
          *  L3 Tx FIFO under flow signal for Tx channel0.
          */
-        uint32_t outfifo_l3_udf_chn:1;
+        uint32_t outfifo_l3_udf_chn: 1;
         /** outfifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
          *  L3 Tx FIFO over flow signal for Tx channel0.
          */
-        uint32_t outfifo_l3_ovf_chn:1;
+        uint32_t outfifo_l3_ovf_chn: 1;
         /** outfifo_l1_full_chn : RO; bitpos: [10]; default: 0;
          *  L1 Tx FIFO full signal for Tx channel0.
          */
-        uint32_t outfifo_l1_full_chn:1;
+        uint32_t outfifo_l1_full_chn: 1;
         /** outfifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
          *  L1 Tx FIFO empty signal for Tx channel0.
          */
-        uint32_t outfifo_l1_empty_chn:1;
+        uint32_t outfifo_l1_empty_chn: 1;
         /** outfifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
          *  L1 Tx FIFO under flow signal for Tx channel0.
          */
-        uint32_t outfifo_l1_udf_chn:1;
+        uint32_t outfifo_l1_udf_chn: 1;
         /** outfifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
          *  L1 Tx FIFO over flow signal for Tx channel0.
          */
-        uint32_t outfifo_l1_ovf_chn:1;
+        uint32_t outfifo_l1_ovf_chn: 1;
         /** outfifo_l2_full_chn : RO; bitpos: [14]; default: 0;
          *  L2 Tx RAM full signal for Tx channel0.
          */
-        uint32_t outfifo_l2_full_chn:1;
+        uint32_t outfifo_l2_full_chn: 1;
         /** outfifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
          *  L2 Tx RAM empty signal for Tx channel0.
          */
-        uint32_t outfifo_l2_empty_chn:1;
+        uint32_t outfifo_l2_empty_chn: 1;
         /** outfifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
          *  L2 Tx FIFO under flow signal for Tx channel0.
          */
-        uint32_t outfifo_l2_udf_chn:1;
+        uint32_t outfifo_l2_udf_chn: 1;
         /** outfifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
          *  L2 Tx FIFO over flow signal for Tx channel0.
          */
-        uint32_t outfifo_l2_ovf_chn:1;
-        uint32_t reserved_18:5;
+        uint32_t outfifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
         /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_1b_chn:1;
+        uint32_t out_remain_under_1b_chn: 1;
         /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_2b_chn:1;
+        uint32_t out_remain_under_2b_chn: 1;
         /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_3b_chn:1;
+        uint32_t out_remain_under_3b_chn: 1;
         /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_4b_chn:1;
+        uint32_t out_remain_under_4b_chn: 1;
         /** out_remain_under_5b_chn : RO; bitpos: [27]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_5b_chn:1;
+        uint32_t out_remain_under_5b_chn: 1;
         /** out_remain_under_6b_chn : RO; bitpos: [28]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_6b_chn:1;
+        uint32_t out_remain_under_6b_chn: 1;
         /** out_remain_under_7b_chn : RO; bitpos: [29]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_7b_chn:1;
+        uint32_t out_remain_under_7b_chn: 1;
         /** out_remain_under_8b_chn : RO; bitpos: [30]; default: 1;
          *  reserved
          */
-        uint32_t out_remain_under_8b_chn:1;
-        uint32_t reserved_31:1;
+        uint32_t out_remain_under_8b_chn: 1;
+        uint32_t reserved_31: 1;
     };
     uint32_t val;
 } axi_dma_outfifo_status_chn_reg_t;
@@ -1085,12 +1084,12 @@ typedef union {
         /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
          *  This register stores the data that need to be pushed into AXI_DMA FIFO.
          */
-        uint32_t outfifo_wdata_chn:9;
+        uint32_t outfifo_wdata_chn: 9;
         /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
          *  Set this bit to push data into AXI_DMA FIFO.
          */
-        uint32_t outfifo_push_chn:1;
-        uint32_t reserved_10:22;
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_out_push_chn_reg_t;
@@ -1103,21 +1102,21 @@ typedef union {
         /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
          *  Set this bit to stop dealing with the outlink descriptors.
          */
-        uint32_t outlink_stop_chn:1;
+        uint32_t outlink_stop_chn: 1;
         /** outlink_start_chn : WT; bitpos: [1]; default: 0;
          *  Set this bit to start dealing with the outlink descriptors.
          */
-        uint32_t outlink_start_chn:1;
+        uint32_t outlink_start_chn: 1;
         /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
          *  Set this bit to restart a new outlink from the last address.
          */
-        uint32_t outlink_restart_chn:1;
+        uint32_t outlink_restart_chn: 1;
         /** outlink_park_chn : RO; bitpos: [3]; default: 1;
          *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
          *  is working.
          */
-        uint32_t outlink_park_chn:1;
-        uint32_t reserved_4:28;
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } axi_dma_out_link1_chn_reg_t;
@@ -1131,7 +1130,7 @@ typedef union {
          *  This register stores the 32 least significant bits of the first outlink
          *  descriptor's address.
          */
-        uint32_t outlink_addr_chn:32;
+        uint32_t outlink_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_link2_chn_reg_t;
@@ -1144,16 +1143,16 @@ typedef union {
         /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
          *  This register stores the current outlink descriptor's address.
          */
-        uint32_t outlink_dscr_addr_chn:18;
+        uint32_t outlink_dscr_addr_chn: 18;
         /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
          *  reserved
          */
-        uint32_t out_dscr_state_chn:2;
+        uint32_t out_dscr_state_chn: 2;
         /** out_state_chn : RO; bitpos: [22:20]; default: 0;
          *  reserved
          */
-        uint32_t out_state_chn:3;
-        uint32_t reserved_23:9;
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
     };
     uint32_t val;
 } axi_dma_out_state_chn_reg_t;
@@ -1167,7 +1166,7 @@ typedef union {
          *  This register stores the address of the outlink descriptor when the EOF bit in this
          *  descriptor is 1.
          */
-        uint32_t out_eof_des_addr_chn:32;
+        uint32_t out_eof_des_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_eof_des_addr_chn_reg_t;
@@ -1181,7 +1180,7 @@ typedef union {
          *  This register stores the address of the outlink descriptor before the last outlink
          *  descriptor.
          */
-        uint32_t out_eof_bfr_des_addr_chn:32;
+        uint32_t out_eof_bfr_des_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_eof_bfr_des_addr_chn_reg_t;
@@ -1194,7 +1193,7 @@ typedef union {
         /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the current outlink descriptor y.
          */
-        uint32_t outlink_dscr_chn:32;
+        uint32_t outlink_dscr_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_dscr_chn_reg_t;
@@ -1207,7 +1206,7 @@ typedef union {
         /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the last outlink descriptor y-1.
          */
-        uint32_t outlink_dscr_bf0_chn:32;
+        uint32_t outlink_dscr_bf0_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_dscr_bf0_chn_reg_t;
@@ -1220,7 +1219,7 @@ typedef union {
         /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
          *  The address of the second-to-last outlink descriptor x-2.
          */
-        uint32_t outlink_dscr_bf1_chn:32;
+        uint32_t outlink_dscr_bf1_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_dscr_bf1_chn_reg_t;
@@ -1233,16 +1232,16 @@ typedef union {
         /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
          *  The priority of Tx channel0. The larger of the value the higher of the priority.
          */
-        uint32_t tx_pri_chn:4;
+        uint32_t tx_pri_chn: 4;
         /** tx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
          *  The weight of Tx channel0
          */
-        uint32_t tx_ch_arb_weigh_chn:4;
+        uint32_t tx_ch_arb_weigh_chn: 4;
         /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
          *  0: mean not optimazation weight function ,1: mean optimazation
          */
-        uint32_t tx_arb_weigh_opt_dir_chn:1;
-        uint32_t reserved_9:23;
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
     };
     uint32_t val;
 } axi_dma_out_pri_chn_reg_t;
@@ -1256,8 +1255,8 @@ typedef union {
          *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
          *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
          */
-        uint32_t peri_out_sel_chn:6;
-        uint32_t reserved_6:26;
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } axi_dma_out_peri_sel_chn_reg_t;
@@ -1270,7 +1269,7 @@ typedef union {
         /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
          *  This register is used to config ch0 of tx crc initial value
          */
-        uint32_t out_crc_init_data_chn:32;
+        uint32_t out_crc_init_data_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_crc_init_data_chn_reg_t;
@@ -1285,12 +1284,12 @@ typedef union {
         /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_width_chn:2;
+        uint32_t tx_crc_width_chn: 2;
         /** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_lautch_flga_chn:1;
-        uint32_t reserved_3:29;
+        uint32_t tx_crc_lautch_flga_chn: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } axi_dma_tx_crc_width_chn_reg_t;
@@ -1303,8 +1302,8 @@ typedef union {
         /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
          *  This register is used to clear ch0 of tx crc result
          */
-        uint32_t out_crc_clear_chn_reg:1;
-        uint32_t reserved_1:31;
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } axi_dma_out_crc_clear_chn_reg_t;
@@ -1317,7 +1316,7 @@ typedef union {
         /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
          *  This register is used to store result ch0 of tx
          */
-        uint32_t out_crc_final_result_chn:32;
+        uint32_t out_crc_final_result_chn: 32;
     };
     uint32_t val;
 } axi_dma_out_crc_final_result_chn_reg_t;
@@ -1330,7 +1329,7 @@ typedef union {
         /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
          *  This register is used to enable tx ch0 crc 32bit on/off
          */
-        uint32_t tx_crc_en_wr_data_chn:32;
+        uint32_t tx_crc_en_wr_data_chn: 32;
     };
     uint32_t val;
 } axi_dma_tx_crc_en_wr_data_chn_reg_t;
@@ -1343,7 +1342,7 @@ typedef union {
         /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_en_addr_chn:32;
+        uint32_t tx_crc_en_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_tx_crc_en_addr_chn_reg_t;
@@ -1356,8 +1355,8 @@ typedef union {
         /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_data_en_wr_data_chn:16;
-        uint32_t reserved_16:16;
+        uint32_t tx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
     };
     uint32_t val;
 } axi_dma_tx_crc_data_en_wr_data_chn_reg_t;
@@ -1370,7 +1369,7 @@ typedef union {
         /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
          *  reserved
          */
-        uint32_t tx_crc_data_en_addr_chn:32;
+        uint32_t tx_crc_data_en_addr_chn: 32;
     };
     uint32_t val;
 } axi_dma_tx_crc_data_en_addr_chn_reg_t;
@@ -1383,44 +1382,44 @@ typedef union {
         /** out_rst_ch1 : R/W; bitpos: [0]; default: 0;
          *  This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer.
          */
-        uint32_t out_rst_ch1:1;
+        uint32_t out_rst_ch1: 1;
         /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t out_loop_test_ch1:1;
+        uint32_t out_loop_test_ch1: 1;
         /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0;
          *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
          *  has been transmitted.
          */
-        uint32_t out_auto_wrback_ch1:1;
+        uint32_t out_auto_wrback_ch1: 1;
         /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1;
          *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is
          *  generated when data need to transmit has been popped from FIFO in AXI_DMA
          */
-        uint32_t out_eof_mode_ch1:1;
+        uint32_t out_eof_mode_ch1: 1;
         /** out_etm_en_ch1 : R/W; bitpos: [4]; default: 0;
          *  Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm
          *  task.
          */
-        uint32_t out_etm_en_ch1:1;
+        uint32_t out_etm_en_ch1: 1;
         /** out_burst_size_sel_ch1 : R/W; bitpos: [7:5]; default: 0;
          *  3'b000-3'b100:burst length 8byte~128byte
          */
-        uint32_t out_burst_size_sel_ch1:3;
+        uint32_t out_burst_size_sel_ch1: 3;
         /** out_cmd_disable_ch1 : R/W; bitpos: [8]; default: 0;
          *  1:mean disable cmd of this ch1
          */
-        uint32_t out_cmd_disable_ch1:1;
+        uint32_t out_cmd_disable_ch1: 1;
         /** out_ecc_aec_en_ch1 : R/W; bitpos: [9]; default: 0;
          *  1: mean access ecc or aes domain,0: mean not
          */
-        uint32_t out_ecc_aec_en_ch1:1;
+        uint32_t out_ecc_aec_en_ch1: 1;
         /** outdscr_burst_en_ch1 : R/W; bitpos: [10]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link
          *  descriptor when accessing internal SRAM.
          */
-        uint32_t outdscr_burst_en_ch1:1;
-        uint32_t reserved_11:21;
+        uint32_t outdscr_burst_en_ch1: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
 } axi_dma_out_conf0_ch1_reg_t;
@@ -1433,49 +1432,48 @@ typedef union {
         /** out_rst_ch2 : R/W; bitpos: [0]; default: 0;
          *  This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer.
          */
-        uint32_t out_rst_ch2:1;
+        uint32_t out_rst_ch2: 1;
         /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t out_loop_test_ch2:1;
+        uint32_t out_loop_test_ch2: 1;
         /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0;
          *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
          *  has been transmitted.
          */
-        uint32_t out_auto_wrback_ch2:1;
+        uint32_t out_auto_wrback_ch2: 1;
         /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1;
          *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is
          *  generated when data need to transmit has been popped from FIFO in AXI_DMA
          */
-        uint32_t out_eof_mode_ch2:1;
+        uint32_t out_eof_mode_ch2: 1;
         /** out_etm_en_ch2 : R/W; bitpos: [4]; default: 0;
          *  Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm
          *  task.
          */
-        uint32_t out_etm_en_ch2:1;
+        uint32_t out_etm_en_ch2: 1;
         /** out_burst_size_sel_ch2 : R/W; bitpos: [7:5]; default: 0;
          *  3'b000-3'b100:burst length 8byte~128byte
          */
-        uint32_t out_burst_size_sel_ch2:3;
+        uint32_t out_burst_size_sel_ch2: 3;
         /** out_cmd_disable_ch2 : R/W; bitpos: [8]; default: 0;
          *  1:mean disable cmd of this ch2
          */
-        uint32_t out_cmd_disable_ch2:1;
+        uint32_t out_cmd_disable_ch2: 1;
         /** out_ecc_aec_en_ch2 : R/W; bitpos: [9]; default: 0;
          *  1: mean access ecc or aes domain,0: mean not
          */
-        uint32_t out_ecc_aec_en_ch2:1;
+        uint32_t out_ecc_aec_en_ch2: 1;
         /** outdscr_burst_en_ch2 : R/W; bitpos: [10]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link
          *  descriptor when accessing internal SRAM.
          */
-        uint32_t outdscr_burst_en_ch2:1;
-        uint32_t reserved_11:21;
+        uint32_t outdscr_burst_en_ch2: 1;
+        uint32_t reserved_11: 21;
     };
     uint32_t val;
 } axi_dma_out_conf0_ch2_reg_t;
 
-
 /** Group: Configuration Registers */
 /** Type of arb_timeout register
  *  This retister is used to config arbiter time slice
@@ -1485,11 +1483,11 @@ typedef union {
         /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
          *  This register is used to config tx arbiter time out value
          */
-        uint32_t arb_timeout_tx:16;
+        uint32_t arb_timeout_tx: 16;
         /** arb_timeout_rx : R/W; bitpos: [31:16]; default: 0;
          *  This register is used to config rx arbiter time out value
          */
-        uint32_t arb_timeout_rx:16;
+        uint32_t arb_timeout_rx: 16;
     };
     uint32_t val;
 } axi_dma_arb_timeout_reg_t;
@@ -1502,12 +1500,12 @@ typedef union {
         /** weight_en_tx : R/W; bitpos: [0]; default: 0;
          *  This register is used to config tx arbiter weight function  off/on
          */
-        uint32_t weight_en_tx:1;
+        uint32_t weight_en_tx: 1;
         /** weight_en_rx : R/W; bitpos: [1]; default: 0;
          *  This register is used to config rx arbiter weight function  off/on
          */
-        uint32_t weight_en_rx:1;
-        uint32_t reserved_2:30;
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_2: 30;
     };
     uint32_t val;
 } axi_dma_weight_en_reg_t;
@@ -1521,29 +1519,29 @@ typedef union {
          *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
          *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
          */
-        uint32_t in_mem_clk_force_en:1;
+        uint32_t in_mem_clk_force_en: 1;
         /** in_mem_force_pu : R/W; bitpos: [1]; default: 0;
          *  Force power up ram
          */
-        uint32_t in_mem_force_pu:1;
+        uint32_t in_mem_force_pu: 1;
         /** in_mem_force_pd : R/W; bitpos: [2]; default: 0;
          *  Force power down ram
          */
-        uint32_t in_mem_force_pd:1;
+        uint32_t in_mem_force_pd: 1;
         /** out_mem_clk_force_en : R/W; bitpos: [3]; default: 0;
          *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
          *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
          */
-        uint32_t out_mem_clk_force_en:1;
+        uint32_t out_mem_clk_force_en: 1;
         /** out_mem_force_pu : R/W; bitpos: [4]; default: 0;
          *  Force power up ram
          */
-        uint32_t out_mem_force_pu:1;
+        uint32_t out_mem_force_pu: 1;
         /** out_mem_force_pd : R/W; bitpos: [5]; default: 0;
          *  Force power down ram
          */
-        uint32_t out_mem_force_pd:1;
-        uint32_t reserved_6:26;
+        uint32_t out_mem_force_pd: 1;
+        uint32_t reserved_6: 26;
     };
     uint32_t val;
 } axi_dma_in_mem_conf_reg_t;
@@ -1556,7 +1554,7 @@ typedef union {
         /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
          *  The start address of accessible address space.
          */
-        uint32_t access_intr_mem_start_addr:32;
+        uint32_t access_intr_mem_start_addr: 32;
     };
     uint32_t val;
 } axi_dma_intr_mem_start_addr_reg_t;
@@ -1571,7 +1569,7 @@ typedef union {
          *  The end address of accessible address space. The access address beyond this range
          *  would lead to descriptor error.
          */
-        uint32_t access_intr_mem_end_addr:32;
+        uint32_t access_intr_mem_end_addr: 32;
     };
     uint32_t val;
 } axi_dma_intr_mem_end_addr_reg_t;
@@ -1584,7 +1582,7 @@ typedef union {
         /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
          *  The start address of accessible address space.
          */
-        uint32_t access_extr_mem_start_addr:32;
+        uint32_t access_extr_mem_start_addr: 32;
     };
     uint32_t val;
 } axi_dma_extr_mem_start_addr_reg_t;
@@ -1599,7 +1597,7 @@ typedef union {
          *  The end address of accessible address space. The access address beyond this range
          *  would lead to descriptor error.
          */
-        uint32_t access_extr_mem_end_addr:32;
+        uint32_t access_extr_mem_end_addr: 32;
     };
     uint32_t val;
 } axi_dma_extr_mem_end_addr_reg_t;
@@ -1612,8 +1610,8 @@ typedef union {
         /** in_reset_avail_chn : RO; bitpos: [0]; default: 1;
          *  rx chan0 reset valid reg.
          */
-        uint32_t in_reset_avail_chn:1;
-        uint32_t reserved_1:31;
+        uint32_t in_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } axi_dma_in_reset_avail_chn_reg_t;
@@ -1626,8 +1624,8 @@ typedef union {
         /** out_reset_avail_chn : RO; bitpos: [0]; default: 1;
          *  tx chan0 reset valid reg.
          */
-        uint32_t out_reset_avail_chn:1;
-        uint32_t reserved_1:31;
+        uint32_t out_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } axi_dma_out_reset_avail_chn_reg_t;
@@ -1640,27 +1638,26 @@ typedef union {
         /** axim_rst_wr_inter : R/W; bitpos: [0]; default: 0;
          *  Set this bit then clear this bit to reset the internal axi_wr FSM.
          */
-        uint32_t axim_rst_wr_inter:1;
+        uint32_t axim_rst_wr_inter: 1;
         /** axim_rst_rd_inter : R/W; bitpos: [1]; default: 0;
          *  Set this bit then clear this bit to reset the internal axi_rd FSM.
          */
-        uint32_t axim_rst_rd_inter:1;
-        uint32_t reserved_2:1;
+        uint32_t axim_rst_rd_inter: 1;
+        uint32_t reserved_2: 1;
         /** arb_pri_dis : R/W; bitpos: [3]; default: 0;
          *  Set this bit to disable priority arbitration function.
          */
-        uint32_t arb_pri_dis:1;
+        uint32_t arb_pri_dis: 1;
         /** clk_en : R/W; bitpos: [4]; default: 0;
          *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
          *  registers.
          */
-        uint32_t clk_en:1;
-        uint32_t reserved_5:27;
+        uint32_t clk_en: 1;
+        uint32_t reserved_5: 27;
     };
     uint32_t val;
 } axi_dma_misc_conf_reg_t;
 
-
 /** Group: Debug Registers */
 /** Type of rdn_result register
  *  reserved
@@ -1670,12 +1667,12 @@ typedef union {
         /** rdn_ena : R/W; bitpos: [0]; default: 0;
          *  reserved
          */
-        uint32_t rdn_ena:1;
+        uint32_t rdn_ena: 1;
         /** rdn_result : RO; bitpos: [1]; default: 0;
          *  reserved
          */
-        uint32_t rdn_result:1;
-        uint32_t reserved_2:30;
+        uint32_t rdn_result: 1;
+        uint32_t reserved_2: 30;
     };
     uint32_t val;
 } axi_dma_rdn_result_reg_t;
@@ -1688,7 +1685,7 @@ typedef union {
         /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
          *  The start address of accessible address space.
          */
-        uint32_t rdn_eco_high:32;
+        uint32_t rdn_eco_high: 32;
     };
     uint32_t val;
 } axi_dma_rdn_eco_high_reg_t;
@@ -1701,12 +1698,11 @@ typedef union {
         /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
          *  The start address of accessible address space.
          */
-        uint32_t rdn_eco_low:32;
+        uint32_t rdn_eco_low: 32;
     };
     uint32_t val;
 } axi_dma_rdn_eco_low_reg_t;
 
-
 /** Group: Status Registers */
 /** Type of wresp_cnt register
  *  AXI wr responce cnt register.
@@ -1716,8 +1712,8 @@ typedef union {
         /** wresp_cnt : RO; bitpos: [3:0]; default: 0;
          *  axi wr responce cnt reg.
          */
-        uint32_t wresp_cnt:4;
-        uint32_t reserved_4:28;
+        uint32_t wresp_cnt: 4;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } axi_dma_wresp_cnt_reg_t;
@@ -1730,8 +1726,8 @@ typedef union {
         /** rresp_cnt : RO; bitpos: [3:0]; default: 0;
          *  axi rd responce cnt reg.
          */
-        uint32_t rresp_cnt:4;
-        uint32_t reserved_4:28;
+        uint32_t rresp_cnt: 4;
+        uint32_t reserved_4: 28;
     };
     uint32_t val;
 } axi_dma_rresp_cnt_reg_t;
@@ -1744,12 +1740,12 @@ typedef union {
         /** l1infifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
          *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
          */
-        uint32_t l1infifo_cnt_chn:6;
+        uint32_t l1infifo_cnt_chn: 6;
         /** l2infifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
          *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
          */
-        uint32_t l2infifo_cnt_chn:4;
-        uint32_t reserved_10:22;
+        uint32_t l2infifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_infifo_status1_chn_reg_t;
@@ -1762,17 +1758,16 @@ typedef union {
         /** l1outfifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
          *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
          */
-        uint32_t l1outfifo_cnt_chn:6;
+        uint32_t l1outfifo_cnt_chn: 6;
         /** l2outfifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
          *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
          */
-        uint32_t l2outfifo_cnt_chn:4;
-        uint32_t reserved_10:22;
+        uint32_t l2outfifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
     };
     uint32_t val;
 } axi_dma_outfifo_status1_chn_reg_t;
 
-
 /** Group: Version Registers */
 /** Type of date register
  *  Version control register
@@ -1782,16 +1777,16 @@ typedef union {
         /** date : R/W; bitpos: [31:0]; default: 36712768;
          *  register version.
          */
-        uint32_t date:32;
+        uint32_t date: 32;
     };
     uint32_t val;
 } axi_dma_date_reg_t;
 
 typedef struct {
-    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw;
-    volatile axi_dma_in_int_st_chn_reg_t in_int_st;
-    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena;
-    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr;
+    volatile axi_dma_in_int_raw_chn_reg_t raw;
+    volatile axi_dma_in_int_st_chn_reg_t st;
+    volatile axi_dma_in_int_ena_chn_reg_t ena;
+    volatile axi_dma_in_int_clr_chn_reg_t clr;
 } axi_dma_in_int_chn_reg_t;
 
 typedef struct {
@@ -1823,20 +1818,20 @@ typedef struct {
 } axi_dma_in_crc_chn_reg_t;
 
 typedef struct {
-    volatile axi_dma_in_int_chn_reg_t in_intr;
-    volatile axi_dma_in_conf_chn_reg_t in_conf;
-    volatile axi_dma_in_crc_chn_reg_t in_crc;
+    volatile axi_dma_in_int_chn_reg_t intr;
+    volatile axi_dma_in_conf_chn_reg_t conf;
+    volatile axi_dma_in_crc_chn_reg_t crc;
 } axi_dma_in_reg_t;
 
 typedef struct {
-    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw;
-    volatile axi_dma_out_int_st_chn_reg_t out_int_st;
-    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena;
-    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr;
+    volatile axi_dma_out_int_raw_chn_reg_t raw;
+    volatile axi_dma_out_int_st_chn_reg_t st;
+    volatile axi_dma_out_int_ena_chn_reg_t ena;
+    volatile axi_dma_out_int_clr_chn_reg_t clr;
 } axi_dma_out_int_chn_reg_t;
 
 typedef struct {
-    volatile axi_dma_out_conf0_ch0_reg_t out_conf0;
+    volatile axi_dma_out_conf0_chn_reg_t out_conf0;
     volatile axi_dma_out_conf1_chn_reg_t out_conf1;
     volatile axi_dma_outfifo_status_chn_reg_t outfifo_status;
     volatile axi_dma_out_push_chn_reg_t out_push;
@@ -1864,9 +1859,9 @@ typedef struct {
 } axi_dma_out_crc_chn_reg_t;
 
 typedef struct {
-    volatile axi_dma_out_int_chn_reg_t in_intr;
-    volatile axi_dma_out_conf_chn_reg_t in_conf;
-    volatile axi_dma_out_crc_chn_reg_t in_crc;
+    volatile axi_dma_out_int_chn_reg_t intr;
+    volatile axi_dma_out_conf_chn_reg_t conf;
+    volatile axi_dma_out_crc_chn_reg_t crc;
 } axi_dma_out_reg_t;
 
 typedef struct {
@@ -1893,6 +1888,7 @@ typedef struct {
     volatile axi_dma_date_reg_t date;
 } axi_dma_dev_t;
 
+extern axi_dma_dev_t AXI_DMA;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(axi_dma_dev_t) == 0x2dc, "Invalid size of axi_dma_dev_t structure");
diff --git a/components/soc/esp32p4/include/soc/gdma_channel.h b/components/soc/esp32p4/include/soc/gdma_channel.h
index d2aa55b41e..bdd6bd8725 100644
--- a/components/soc/esp32p4/include/soc/gdma_channel.h
+++ b/components/soc/esp32p4/include/soc/gdma_channel.h
@@ -5,3 +5,41 @@
  */
 
 #pragma once
+
+// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
+#define SOC_GDMA_TRIG_PERIPH_M2M0     -1
+#define SOC_GDMA_TRIG_PERIPH_I3C0     0
+#define SOC_GDMA_TRIG_PERIPH_UHCI0    2
+#define SOC_GDMA_TRIG_PERIPH_I2S0     3
+#define SOC_GDMA_TRIG_PERIPH_I2S1     4
+#define SOC_GDMA_TRIG_PERIPH_I2S2     5
+#define SOC_GDMA_TRIG_PERIPH_ADC0     8
+#define SOC_GDMA_TRIG_PERIPH_RMT0     10
+#define SOC_GDMA_TRIG_PERIPH_LCD0     0
+#define SOC_GDMA_TRIG_PERIPH_CAM0     0
+#define SOC_GDMA_TRIG_PERIPH_SPI2     1
+#define SOC_GDMA_TRIG_PERIPH_SPI3     2
+#define SOC_GDMA_TRIG_PERIPH_PARLIO0  3
+#define SOC_GDMA_TRIG_PERIPH_AES0     4
+#define SOC_GDMA_TRIG_PERIPH_SHA0     5
+
+// On which system bus is the DMA instance of the peripheral connection mounted
+#define SOC_GDMA_BUS_ANY -1
+#define SOC_GDMA_BUS_AHB 0
+#define SOC_GDMA_BUS_AXI 1
+
+#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS     SOC_GDMA_BUS_ANY
+#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS    SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS     SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_I2S1_BUS     SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_I2S2_BUS     SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS     SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_RMT0_BUS     SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_I3C0_BUS     SOC_GDMA_BUS_AHB
+#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS     SOC_GDMA_BUS_AXI
+#define SOC_GDMA_TRIG_PERIPH_SPI3_BUS     SOC_GDMA_BUS_AXI
+#define SOC_GDMA_TRIG_PERIPH_LCD0_BUS     SOC_GDMA_BUS_AXI
+#define SOC_GDMA_TRIG_PERIPH_CAM0_BUS     SOC_GDMA_BUS_AXI
+#define SOC_GDMA_TRIG_PERIPH_AES0_BUS     SOC_GDMA_BUS_AXI
+#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS     SOC_GDMA_BUS_AXI
+#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS  SOC_GDMA_BUS_AXI
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index 21a3346f60..a4e61a6ba2 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -30,6 +30,8 @@
 // #define SOC_DEDICATED_GPIO_SUPPORTED    1  //TODO: IDF-7552
 #define SOC_UART_SUPPORTED              1
 // #define SOC_GDMA_SUPPORTED              1  //TODO: IDF-6504
+// #define SOC_AHB_GDMA_SUPPORTED          1
+// #define SOC_AXI_GDMA_SUPPORTED          1
 // #define SOC_GPTIMER_SUPPORTED           1  //TODO: IDF-6515
 // #define SOC_PCNT_SUPPORTED              1  //TODO: IDF-7475
 // #define SOC_MCPWM_SUPPORTED             1  //TODO: IDF-7493
@@ -154,9 +156,10 @@
 #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
 
 /*-------------------------- GDMA CAPS -------------------------------------*/
-#define SOC_GDMA_GROUPS                 (1U) // Number of GDMA groups
-#define SOC_GDMA_PAIRS_PER_GROUP        (3)  // Number of GDMA pairs in each group
-#define SOC_GDMA_SUPPORT_ETM            (0)  // Support ETM submodule
+#define SOC_AHB_GDMA_VERSION            2
+#define SOC_GDMA_NUM_GROUPS_MAX         2
+#define SOC_GDMA_PAIRS_PER_GROUP_MAX    3
+#define SOC_GDMA_SUPPORT_ETM            1  // Both AHB-DMA and AXI-DMA supports ETM
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
@@ -421,7 +424,6 @@
 
 /*-------------------------- MEMPROT CAPS ------------------------------------*/
 
-
 /*-------------------------- UART CAPS ---------------------------------------*/
 // ESP32-P4 has 2 UARTs
 #define SOC_UART_NUM                    (2)