diff --git a/components/soc/esp32h21/include/soc/gpio_sig_map.h b/components/soc/esp32h21/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..e6e4080df8 --- /dev/null +++ b/components/soc/esp32h21/include/soc/gpio_sig_map.h @@ -0,0 +1,262 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define USB_JTAG_TDO_BRIDGE_IDX 19 +#define USB_JTAG_TRST_IDX 19 +#define CPU_TESTBUS0_IDX 20 +#define CPU_TESTBUS1_IDX 21 +#define CPU_TESTBUS2_IDX 22 +#define CPU_TESTBUS3_IDX 23 +#define CPU_TESTBUS4_IDX 24 +#define CPU_TESTBUS5_IDX 25 +#define CPU_TESTBUS6_IDX 26 +#define CPU_TESTBUS7_IDX 27 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define USB_JTAG_TCK_IDX 36 +#define USB_JTAG_TMS_IDX 37 +#define USB_JTAG_TDI_IDX 38 +#define USB_JTAG_TDO_IDX 39 +#define USB_EXTPHY_VP_IDX 40 +#define USB_EXTPHY_OEN_IDX 40 +#define USB_EXTPHY_VM_IDX 41 +#define USB_EXTPHY_SPEED_IDX 41 +#define USB_EXTPHY_RCV_IDX 42 +#define USB_EXTPHY_VPO_IDX 42 +#define USB_EXTPHY_VMO_IDX 43 +#define USB_EXTPHY_SUSPND_IDX 44 +#define I2CEXT0_SCL_IN_IDX 45 +#define I2CEXT0_SCL_OUT_IDX 45 +#define I2CEXT0_SDA_IN_IDX 46 +#define I2CEXT0_SDA_OUT_IDX 46 +#define PARL_RX_DATA0_IDX 47 +#define PARL_TX_DATA0_IDX 47 +#define PARL_RX_DATA1_IDX 48 +#define PARL_TX_DATA1_IDX 48 +#define PARL_RX_DATA2_IDX 49 +#define PARL_TX_DATA2_IDX 49 +#define PARL_RX_DATA3_IDX 50 +#define PARL_TX_DATA3_IDX 50 +#define PARL_RX_DATA4_IDX 51 +#define PARL_TX_DATA4_IDX 51 +#define PARL_RX_DATA5_IDX 52 +#define PARL_TX_DATA5_IDX 52 +#define PARL_RX_DATA6_IDX 53 +#define PARL_TX_DATA6_IDX 53 +#define PARL_RX_DATA7_IDX 54 +#define PARL_TX_DATA7_IDX 54 +#define I2CEXT1_SCL_IN_IDX 55 +#define I2CEXT1_SCL_OUT_IDX 55 +#define I2CEXT1_SDA_IN_IDX 56 +#define I2CEXT1_SDA_OUT_IDX 56 +#define CTE_ANT0_IDX 57 +#define CTE_ANT1_IDX 58 +#define CTE_ANT2_IDX 59 +#define CTE_ANT3_IDX 60 +#define CTE_ANT4_IDX 61 +#define CTE_ANT5_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define PARL_RX_CLK_IN_IDX 69 +#define PARL_RX_CLK_OUT_IDX 69 +#define PARL_TX_CLK_IN_IDX 70 +#define PARL_TX_CLK_OUT_IDX 70 +#define RMT_SIG_IN0_IDX 71 +#define RMT_SIG_OUT0_IDX 71 +#define RMT_SIG_IN1_IDX 72 +#define RMT_SIG_OUT1_IDX 72 +#define TWAI0_RX_IDX 73 +#define TWAI0_TX_IDX 73 +#define TWAI0_BUS_OFF_ON_IDX 74 +#define TWAI0_CLKOUT_IDX 75 +#define TWAI0_STANDBY_IDX 76 +#define PCNT_RST_IN0_IDX 77 +#define CTE_ANT6_IDX 77 +#define PCNT_RST_IN1_IDX 78 +#define CTE_ANT7_IDX 78 +#define PCNT_RST_IN2_IDX 79 +#define CTE_ANT8_IDX 79 +#define PCNT_RST_IN3_IDX 80 +#define CTE_ANT9_IDX 80 +#define EXTERN_PRIORITY_I_IDX 81 +#define EXTERN_PRIORITY_O_IDX 81 +#define EXTERN_ACTIVE_I_IDX 82 +#define EXTERN_ACTIVE_O_IDX 82 +#define GPIO_SD0_OUT_IDX 83 +#define GPIO_SD1_OUT_IDX 84 +#define GPIO_SD2_OUT_IDX 85 +#define GPIO_SD3_OUT_IDX 86 +#define PWM0_SYNC0_IN_IDX 87 +#define PWM0_OUT0A_IDX 87 +#define PWM0_SYNC1_IN_IDX 88 +#define PWM0_OUT0B_IDX 88 +#define PWM0_SYNC2_IN_IDX 89 +#define PWM0_OUT1A_IDX 89 +#define PWM0_F0_IN_IDX 90 +#define PWM0_OUT1B_IDX 90 +#define PWM0_F1_IN_IDX 91 +#define PWM0_OUT2A_IDX 91 +#define PWM0_F2_IN_IDX 92 +#define PWM0_OUT2B_IDX 92 +#define PWM0_CAP0_IN_IDX 93 +#define ANT_SEL0_IDX 93 +#define PWM0_CAP1_IN_IDX 94 +#define ANT_SEL1_IDX 94 +#define PWM0_CAP2_IN_IDX 95 +#define ANT_SEL2_IDX 95 +#define ANT_SEL3_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 101 +#define FSPICS1_OUT_IDX 101 +#define PCNT_SIG_CH1_IN0_IDX 102 +#define FSPICS2_OUT_IDX 102 +#define PCNT_CTRL_CH0_IN0_IDX 103 +#define FSPICS3_OUT_IDX 103 +#define PCNT_CTRL_CH1_IN0_IDX 104 +#define FSPICS4_OUT_IDX 104 +#define PCNT_SIG_CH0_IN1_IDX 105 +#define FSPICS5_OUT_IDX 105 +#define PCNT_SIG_CH1_IN1_IDX 106 +#define CTE_ANT10_IDX 106 +#define PCNT_CTRL_CH0_IN1_IDX 107 +#define CTE_ANT11_IDX 107 +#define PCNT_CTRL_CH1_IN1_IDX 108 +#define CTE_ANT12_IDX 108 +#define PCNT_SIG_CH0_IN2_IDX 109 +#define CTE_ANT13_IDX 109 +#define PCNT_SIG_CH1_IN2_IDX 110 +#define CTE_ANT14_IDX 110 +#define PCNT_CTRL_CH0_IN2_IDX 111 +#define CTE_ANT15_IDX 111 +#define PCNT_CTRL_CH1_IN2_IDX 112 +#define USB_JTAG_SRST_IDX 112 +#define PCNT_SIG_CH0_IN3_IDX 113 +#define PCNT_SIG_CH1_IN3_IDX 114 +#define SPICLK_OUT_IDX 114 +#define PCNT_CTRL_CH0_IN3_IDX 115 +#define SPICS0_OUT_IDX 115 +#define PCNT_CTRL_CH1_IN3_IDX 116 +#define SPICS1_OUT_IDX 116 +#define GPIO_EVENT_MATRIX_IN0_IDX 117 +#define GPIO_TASK_MATRIX_OUT0_IDX 117 +#define GPIO_EVENT_MATRIX_IN1_IDX 118 +#define GPIO_TASK_MATRIX_OUT1_IDX 118 +#define GPIO_EVENT_MATRIX_IN2_IDX 119 +#define GPIO_TASK_MATRIX_OUT2_IDX 119 +#define GPIO_EVENT_MATRIX_IN3_IDX 120 +#define GPIO_TASK_MATRIX_OUT3_IDX 120 +#define SPIQ_IN_IDX 121 +#define SPIQ_OUT_IDX 121 +#define SPID_IN_IDX 122 +#define SPID_OUT_IDX 122 +#define SPIHD_IN_IDX 123 +#define SPIHD_OUT_IDX 123 +#define SPIWP_IN_IDX 124 +#define SPIWP_OUT_IDX 124 +#define CLK_OUT_OUT1_IDX 125 +#define CLK_OUT_OUT2_IDX 126 +#define CLK_OUT_OUT3_IDX 127 +#define MODEM_DIAG0_IDX 128 +#define MODEM_DIAG1_IDX 129 +#define MODEM_DIAG2_IDX 130 +#define MODEM_DIAG3_IDX 131 +#define MODEM_DIAG4_IDX 132 +#define MODEM_DIAG5_IDX 133 +#define MODEM_DIAG6_IDX 134 +#define MODEM_DIAG7_IDX 135 +#define MODEM_DIAG8_IDX 136 +#define MODEM_DIAG9_IDX 137 +#define MODEM_DIAG10_IDX 138 +#define MODEM_DIAG11_IDX 139 +#define MODEM_DIAG12_IDX 140 +#define MODEM_DIAG13_IDX 141 +#define MODEM_DIAG14_IDX 142 +#define MODEM_DIAG15_IDX 143 +#define MODEM_DIAG16_IDX 144 +#define MODEM_DIAG17_IDX 145 +#define MODEM_DIAG18_IDX 146 +#define MODEM_DIAG19_IDX 147 +#define MODEM_DIAG20_IDX 148 +#define MODEM_DIAG21_IDX 149 +#define MODEM_DIAG22_IDX 150 +#define MODEM_DIAG23_IDX 151 +#define MODEM_DIAG24_IDX 152 +#define MODEM_DIAG25_IDX 153 +#define MODEM_DIAG26_IDX 154 +#define MODEM_DIAG27_IDX 155 +#define MODEM_DIAG28_IDX 156 +#define MODEM_DIAG29_IDX 157 +#define MODEM_DIAG30_IDX 158 +#define MODEM_DIAG31_IDX 159 +#define COEX_PA_PWR_SWITCH_PIN0_IDX 160 +#define COEX_PA_PWR_SWITCH_PIN1_IDX 161 +// version date 2409110 +#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32h21/include/soc/interrupts.h b/components/soc/esp32h21/include/soc/interrupts.h new file mode 100644 index 0000000000..9f28a1ab24 --- /dev/null +++ b/components/soc/esp32h21/include/soc/interrupts.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_BLE_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, + ETS_ASSIST_DEBUG_INTR_SOURCE, + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, + ETS_GPIO_INTERRUPT_PRO_NMI_SOURCE, + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_TWAI0_INTR_SOURCE, + ETS_USB_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C_EXT0_INTR_SOURCE, + ETS_I2C_EXT1_INTR_SOURCE, + ETS_TG0_T0_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, + ETS_TG1_T0_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_APB_ADC_INTR_SOURCE, + ETS_PWM_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, + ETS_DMA_IN_CH1_INTR_SOURCE, + ETS_DMA_IN_CH2_INTR_SOURCE, + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH2_INTR_SOURCE, + ETS_GPSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_RSA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/pmu_icg_mapping.h b/components/soc/esp32h21/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..972e2d6d09 --- /dev/null +++ b/components/soc/esp32h21/include/soc/pmu_icg_mapping.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_I2C0 13 +#define PMU_ICG_APB_ENA_I2C1 13 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_APB_ENA_TWAI0 18 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#define PMU_ICG_FUNC_ENA_HPMEM 15 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_I2C0 29 +#define PMU_ICG_FUNC_ENA_I2C1 29 +#define PMU_ICG_FUNC_ENA_TWAI0 31 diff --git a/components/soc/esp32h21/include/soc/soc_etm_source.h b/components/soc/esp32h21/include/soc/soc_etm_source.h new file mode 100644 index 0000000000..3c75bcff21 --- /dev/null +++ b/components/soc/esp32h21/include/soc/soc_etm_source.h @@ -0,0 +1,338 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define LEDC_EVT_DUTY_CHNG_END_CH0 25 +#define LEDC_EVT_DUTY_CHNG_END_CH1 26 +#define LEDC_EVT_DUTY_CHNG_END_CH2 27 +#define LEDC_EVT_DUTY_CHNG_END_CH3 28 +#define LEDC_EVT_DUTY_CHNG_END_CH4 29 +#define LEDC_EVT_DUTY_CHNG_END_CH5 30 +#define LEDC_EVT_OVF_CNT_PLS_CH0 31 +#define LEDC_EVT_OVF_CNT_PLS_CH1 32 +#define LEDC_EVT_OVF_CNT_PLS_CH2 33 +#define LEDC_EVT_OVF_CNT_PLS_CH3 34 +#define LEDC_EVT_OVF_CNT_PLS_CH4 35 +#define LEDC_EVT_OVF_CNT_PLS_CH5 36 +#define LEDC_EVT_TIME_OVF_TIMER0 37 +#define LEDC_EVT_TIME_OVF_TIMER1 38 +#define LEDC_EVT_TIME_OVF_TIMER2 39 +#define LEDC_EVT_TIME_OVF_TIMER3 40 +#define LEDC_EVT_TIMER0_CMP 41 +#define LEDC_EVT_TIMER1_CMP 42 +#define LEDC_EVT_TIMER2_CMP 43 +#define LEDC_EVT_TIMER3_CMP 44 +#define PCNT_EVT_CNT_EQ_THRESH 45 +#define PCNT_EVT_CNT_EQ_LMT 46 +#define PCNT_EVT_CNT_EQ_ZERO 47 +#define TIMER0_EVT_CNT_CMP_TIMER0 48 +#define TIMER1_EVT_CNT_CMP_TIMER0 49 +#define SYSTIMER_EVT_CNT_CMP0 50 +#define SYSTIMER_EVT_CNT_CMP1 51 +#define SYSTIMER_EVT_CNT_CMP2 52 +#define RMT_EVT_TX_END 53 +#define RMT_EVT_TX_LOOP 54 +#define RMT_EVT_RX_END 55 +#define RMT_EVT_TX_THRESH 56 +#define RMT_EVT_RX_THRESH 57 +#define MCPWM_EVT_TIMER0_STOP 58 +#define MCPWM_EVT_TIMER1_STOP 59 +#define MCPWM_EVT_TIMER2_STOP 60 +#define MCPWM_EVT_TIMER0_TEZ 61 +#define MCPWM_EVT_TIMER1_TEZ 62 +#define MCPWM_EVT_TIMER2_TEZ 63 +#define MCPWM_EVT_TIMER0_TEP 64 +#define MCPWM_EVT_TIMER1_TEP 65 +#define MCPWM_EVT_TIMER2_TEP 66 +#define MCPWM_EVT_OP0_TEA 67 +#define MCPWM_EVT_OP1_TEA 68 +#define MCPWM_EVT_OP2_TEA 69 +#define MCPWM_EVT_OP0_TEB 70 +#define MCPWM_EVT_OP1_TEB 71 +#define MCPWM_EVT_OP2_TEB 72 +#define MCPWM_EVT_F0 73 +#define MCPWM_EVT_F1 74 +#define MCPWM_EVT_F2 75 +#define MCPWM_EVT_F0_CLR 76 +#define MCPWM_EVT_F1_CLR 77 +#define MCPWM_EVT_F2_CLR 78 +#define MCPWM_EVT_TZ0_CBC 79 +#define MCPWM_EVT_TZ1_CBC 80 +#define MCPWM_EVT_TZ2_CBC 81 +#define MCPWM_EVT_TZ0_OST 82 +#define MCPWM_EVT_TZ1_OST 83 +#define MCPWM_EVT_TZ2_OST 84 +#define MCPWM_EVT_CAP0 85 +#define MCPWM_EVT_CAP1 86 +#define MCPWM_EVT_CAP2 87 +#define ADC_EVT_CONV_CMPLT0 88 +#define ADC_EVT_EQ_ABOVE_THRESH0 89 +#define ADC_EVT_EQ_ABOVE_THRESH1 90 +#define ADC_EVT_EQ_BELOW_THRESH0 91 +#define ADC_EVT_EQ_BELOW_THRESH1 92 +#define ADC_EVT_RESULT_DONE0 93 +#define ADC_EVT_STOPPED0 94 +#define ADC_EVT_STARTED0 95 +#define REGDMA_EVT_DONE0 96 +#define REGDMA_EVT_DONE1 97 +#define REGDMA_EVT_DONE2 98 +#define REGDMA_EVT_DONE3 99 +#define REGDMA_EVT_ERR0 100 +#define REGDMA_EVT_ERR1 101 +#define REGDMA_EVT_ERR2 102 +#define REGDMA_EVT_ERR3 103 +#define PDMA_EVT_TX_DONE 104 +#define PDMA_EVT_OUT_EOF 105 +#define PDMA_EVT_IN_SUC_EOF 106 +#define PDMA_EVT_FULL_OR_EMPTY 107 +#define PDMA_EVT_ALL_DONE 108 +#define PDMA_EVT_RX_DONE 109 +#define TMPSNSR_EVT_OVER_LIMIT 110 +#define UART_EVT_REC_DATA_OVF0 111 +#define UART_EVT_REC_DATA_OVF1 112 +#define UART_EVT_TX_DONE0 113 +#define UART_EVT_TX_DONE1 114 +#define UART_EVT_TIMEOUT0 115 +#define UART_EVT_TIMEOUT1 116 +#define UART_EVT_ERR0 117 +#define UART_EVT_ERR1 118 +#define UART_EVT_CTS0 119 +#define UART_EVT_CTS1 120 +#define UART_EVT_TX_EMPTY0 121 +#define UART_EVT_TX_EMPTY1 122 +#define UART_EVT_AT_PATTERNS0 123 +#define UART_EVT_AT_PATTERNS1 124 +#define SPI_EVT_STOPPED 125 +#define I2S_EVT_RX_DONE 126 +#define I2S_EVT_TX_DONE 127 +#define I2S_EVT_X_WORDS_RECEIVED 128 +#define I2S_EVT_X_WORDS_SENT 129 +#define I2C_EVT_TRANS_DONE 130 +#define LCDCAM_EVT_TRANS_DONE 131 +#define TWAI_EVT_TRANS_DONE 132 +#define ULP_EVT_ERR_INTR 133 +#define ULP_EVT_START_INTR 134 +#define RTC_EVT_TICK 135 +#define RTC_EVT_OVF 136 +#define RTC_EVT_CMP 137 +#define GDMA_EVT_IN_DONE_CH0 138 +#define GDMA_EVT_IN_DONE_CH1 139 +#define GDMA_EVT_IN_DONE_CH2 140 +#define GDMA_EVT_IN_SUC_EOF_CH0 141 +#define GDMA_EVT_IN_SUC_EOF_CH1 142 +#define GDMA_EVT_IN_SUC_EOF_CH2 143 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 144 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 145 +#define GDMA_EVT_IN_FIFO_EMPTY_CH2 146 +#define GDMA_EVT_IN_FIFO_FULL_CH0 147 +#define GDMA_EVT_IN_FIFO_FULL_CH1 148 +#define GDMA_EVT_IN_FIFO_FULL_CH2 149 +#define GDMA_EVT_OUT_DONE_CH0 150 +#define GDMA_EVT_OUT_DONE_CH1 151 +#define GDMA_EVT_OUT_DONE_CH2 152 +#define GDMA_EVT_OUT_EOF_CH0 153 +#define GDMA_EVT_OUT_EOF_CH1 154 +#define GDMA_EVT_OUT_EOF_CH2 155 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 156 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 157 +#define GDMA_EVT_OUT_TOTAL_EOF_CH2 158 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 159 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 160 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 161 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 162 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 163 +#define GDMA_EVT_OUT_FIFO_FULL_CH2 164 +#define PMU_EVT_SLEEP_WEEKUP 165 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_RESERVED0 29 +#define LEDC_TASK_RESERVED1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36 +#define LEDC_TASK_TIMER0_CAP 37 +#define LEDC_TASK_TIMER1_CAP 38 +#define LEDC_TASK_TIMER2_CAP 39 +#define LEDC_TASK_TIMER3_CAP 40 +#define LEDC_TASK_SIG_OUT_DIS_CH0 41 +#define LEDC_TASK_SIG_OUT_DIS_CH1 42 +#define LEDC_TASK_SIG_OUT_DIS_CH2 43 +#define LEDC_TASK_SIG_OUT_DIS_CH3 44 +#define LEDC_TASK_SIG_OUT_DIS_CH4 45 +#define LEDC_TASK_SIG_OUT_DIS_CH5 46 +#define LEDC_TASK_OVF_CNT_RST_CH0 47 +#define LEDC_TASK_OVF_CNT_RST_CH1 48 +#define LEDC_TASK_OVF_CNT_RST_CH2 49 +#define LEDC_TASK_OVF_CNT_RST_CH3 50 +#define LEDC_TASK_OVF_CNT_RST_CH4 51 +#define LEDC_TASK_OVF_CNT_RST_CH5 52 +#define LEDC_TASK_TIMER0_RST 53 +#define LEDC_TASK_TIMER1_RST 54 +#define LEDC_TASK_TIMER2_RST 55 +#define LEDC_TASK_TIMER3_RST 56 +#define LEDC_TASK_TIMER0_RESUME 57 +#define LEDC_TASK_TIMER1_RESUME 58 +#define LEDC_TASK_TIMER2_RESUME 59 +#define LEDC_TASK_TIMER3_RESUME 60 +#define LEDC_TASK_TIMER0_PAUSE 61 +#define LEDC_TASK_TIMER1_PAUSE 62 +#define LEDC_TASK_TIMER2_PAUSE 63 +#define LEDC_TASK_TIMER3_PAUSE 64 +#define LEDC_TASK_GAMMA_RESTART_CH0 65 +#define LEDC_TASK_GAMMA_RESTART_CH1 66 +#define LEDC_TASK_GAMMA_RESTART_CH2 67 +#define LEDC_TASK_GAMMA_RESTART_CH3 68 +#define LEDC_TASK_GAMMA_RESTART_CH4 69 +#define LEDC_TASK_GAMMA_RESTART_CH5 70 +#define LEDC_TASK_GAMMA_PAUSE_CH0 71 +#define LEDC_TASK_GAMMA_PAUSE_CH1 72 +#define LEDC_TASK_GAMMA_PAUSE_CH2 73 +#define LEDC_TASK_GAMMA_PAUSE_CH3 74 +#define LEDC_TASK_GAMMA_PAUSE_CH4 75 +#define LEDC_TASK_GAMMA_PAUSE_CH5 76 +#define LEDC_TASK_GAMMA_RESUME_CH0 77 +#define LEDC_TASK_GAMMA_RESUME_CH1 78 +#define LEDC_TASK_GAMMA_RESUME_CH2 79 +#define LEDC_TASK_GAMMA_RESUME_CH3 80 +#define LEDC_TASK_GAMMA_RESUME_CH4 81 +#define LEDC_TASK_GAMMA_RESUME_CH5 82 +#define PCNT_TASK_START 83 +#define PCNT_TASK_STOP 84 +#define PCNT_TASK_CNT_INC 85 +#define PCNT_TASK_CNT_DEC 86 +#define PCNT_TASK_CNT_RST 87 +#define TIMER0_TASK_CNT_START_TIMER0 88 +#define TIMER1_TASK_CNT_START_TIMER0 89 +#define TIMER0_TASK_ALARM_START_TIMER0 90 +#define TIMER1_TASK_ALARM_START_TIMER0 91 +#define TIMER0_TASK_CNT_STOP_TIMER0 92 +#define TIMER1_TASK_CNT_STOP_TIMER0 93 +#define TIMER0_TASK_CNT_RELOAD_TIMER0 94 +#define TIMER1_TASK_CNT_RELOAD_TIMER0 95 +#define TIMER0_TASK_CNT_CAP_TIMER0 96 +#define TIMER1_TASK_CNT_CAP_TIMER0 97 +#define RMT_TASK_TX_START 98 +#define RMT_TASK_TX_STOP 99 +#define RMT_TASK_RX_DONE 100 +#define RMT_TASK_RX_START 101 +#define MCPWM_TASK_CMPR0_A_UP 102 +#define MCPWM_TASK_CMPR1_A_UP 103 +#define MCPWM_TASK_CMPR2_A_UP 104 +#define MCPWM_TASK_CMPR0_B_UP 105 +#define MCPWM_TASK_CMPR1_B_UP 106 +#define MCPWM_TASK_CMPR2_B_UP 107 +#define MCPWM_TASK_GEN_STOP 108 +#define MCPWM_TASK_TIMER0_SYN 109 +#define MCPWM_TASK_TIMER1_SYN 110 +#define MCPWM_TASK_TIMER2_SYN 111 +#define MCPWM_TASK_TIMER0_PERIOD_UP 112 +#define MCPWM_TASK_TIMER1_PERIOD_UP 113 +#define MCPWM_TASK_TIMER2_PERIOD_UP 114 +#define MCPWM_TASK_TZ0_OST 115 +#define MCPWM_TASK_TZ1_OST 116 +#define MCPWM_TASK_TZ2_OST 117 +#define MCPWM_TASK_CLR0_OST 118 +#define MCPWM_TASK_CLR1_OST 119 +#define MCPWM_TASK_CLR2_OST 120 +#define MCPWM_TASK_CAP0 121 +#define MCPWM_TASK_CAP1 122 +#define MCPWM_TASK_CAP2 123 +#define ADC_TASK_SAMPLE0 124 +#define ADC_TASK_SAMPLE1 125 +#define ADC_TASK_START0 126 +#define ADC_TASK_STOP0 127 +#define REGDMA_TASK_START0 128 +#define REGDMA_TASK_START1 129 +#define REGDMA_TASK_START2 130 +#define REGDMA_TASK_START3 131 +#define PDMA_TASK_START_TX 132 +#define PDMA_TASK_START_RX 133 +#define PDMA_TASK_STOP 134 +#define TMPSNSR_TASK_START_SAMPLE 135 +#define TMPSNSR_TASK_STOP_SAMPLE 136 +#define UART_TASK_TX_START0 137 +#define UART_TASK_TX_START1 138 +#define UART_TASK_TX_STOP0 139 +#define UART_TASK_TX_STOP1 140 +#define UART_TASK_RX_START0 141 +#define UART_TASK_RX_START1 142 +#define UART_TASK_RX_STOP0 143 +#define UART_TASK_RX_STOP1 144 +#define SPI_TASK_TX_START 145 +#define SPI_TASK_SLAVE_HD 146 +#define SPI_TASK_STOP 147 +#define I2S_TASK_START_RX 148 +#define I2S_TASK_START_TX 149 +#define I2S_TASK_STOP_RX 150 +#define I2S_TASK_STOP_TX 151 +#define I2C_TASK_START_TRANS 152 +#define TWAI_TASK_TRANS_START 153 +#define ULP_TASK_WAKEUP_CPU 154 +#define RTC_TASK_START 155 +#define RTC_TASK_STOP 156 +#define RTC_TASK_CLR 157 +#define RTC_TASK_TRIGGERFLW 158 +#define GDMA_TASK_IN_START_CH0 159 +#define GDMA_TASK_IN_START_CH1 160 +#define GDMA_TASK_IN_START_CH2 161 +#define GDMA_TASK_OUT_START_CH0 162 +#define GDMA_TASK_OUT_START_CH1 163 +#define GDMA_TASK_OUT_START_CH2 164 +#define PMU_TASK_SLEEP_REQ 165 diff --git a/components/soc/esp32h21/interrupts.c b/components/soc/esp32h21/interrupts.c index e69de29bb2..5ebe02a84e 100644 --- a/components/soc/esp32h21/interrupts.c +++ b/components/soc/esp32h21/interrupts.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "PMU", + [1] = "EFUSE", + [2] = "LP_RTC_TIMER", + [3] = "LP_BLE_TIMER", + [4] = "LP_WDT", + [5] = "LP_PERI_TIMEOUT", + [6] = "LP_APM_M0", + [7] = "CPU_FROM_CPU_0", + [8] = "CPU_FROM_CPU_1", + [9] = "CPU_FROM_CPU_2", + [10] = "CPU_FROM_CPU_3", + [11] = "ASSIST_DEBUG", + [12] = "TRACE", + [13] = "CACHE", + [14] = "CPU_PERI_TIMEOUT", + [15] = "BT_MAC", + [16] = "BT_BB", + [17] = "BT_BB_NMI", + [18] = "COEX", + [19] = "BLE_TIMER", + [20] = "BLE_SEC", + [21] = "ZB_MAC", + [22] = "GPIO_INTERRUPT_PRO", + [23] = "GPIO_INTERRUPT_PRO_NMI", + [24] = "PAU", + [25] = "HP_PERI_TIMEOUT", + [26] = "HP_APM_M0", + [27] = "HP_APM_M1", + [28] = "HP_APM_M2", + [29] = "HP_APM_M3", + [30] = "MSPI", + [31] = "I2S1", + [32] = "UHCI0", + [33] = "UART0", + [34] = "UART1", + [35] = "LEDC", + [36] = "TWAI0", + [37] = "USB", + [38] = "RMT", + [39] = "I2C_EXT0", + [40] = "I2C_EXT1", + [41] = "TG0_T0", + [42] = "TG0_WDT", + [43] = "TG1_T0", + [44] = "TG1_WDT", + [45] = "SYSTIMER_TARGET0", + [46] = "SYSTIMER_TARGET1", + [47] = "SYSTIMER_TARGET2", + [48] = "APB_ADC", + [49] = "PWM", + [50] = "PCNT", + [51] = "PARL_IO_TX", + [52] = "PARL_IO_RX", + [53] = "DMA_IN_CH0", + [54] = "DMA_IN_CH1", + [55] = "DMA_IN_CH2", + [56] = "DMA_OUT_CH0", + [57] = "DMA_OUT_CH1", + [58] = "DMA_OUT_CH2", + [59] = "GPSPI2", + [60] = "AES", + [61] = "SHA", + [62] = "RSA", + [63] = "ECC", + [64] = "ECDSA", +}; diff --git a/components/soc/esp32h21/ld/esp32h21.peripherals.ld b/components/soc/esp32h21/ld/esp32h21.peripherals.ld new file mode 100644 index 0000000000..1dc197c8fb --- /dev/null +++ b/components/soc/esp32h21/ld/esp32h21.peripherals.ld @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C0 = 0x60004000 ); +PROVIDE ( I2C1 = 0x60005000 ); +PROVIDE ( UHCI0 = 0x60006000 ); +PROVIDE ( RMT = 0x60007000 ); +PROVIDE ( LEDC = 0x60008000 ); +PROVIDE ( TIMERG0 = 0x60009000 ); +PROVIDE ( TIMERG1 = 0x6000A000 ); +PROVIDE ( SYSTIMER = 0x6000B000 ); +PROVIDE ( TWAI = 0x6000C000 ); +PROVIDE ( I2S0 = 0x6000D000 ); +PROVIDE ( APB_SARADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( PCNT = 0x60012000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( MCPWM0 = 0x60014000 ); +PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( PVT = 0x60019000 ); +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); +PROVIDE ( AES = 0x60088000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( RSA = 0x6008A000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( DS = 0x6008C000 ); +PROVIDE ( HMAC = 0x6008D000 ); +PROVIDE ( ECDSA = 0x6008E000 ); +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091E00 ); +PROVIDE ( MEM_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( LP_APM0 = 0x60099800 ); +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( LPPERI = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_TIMER = 0x600B3000 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( EFUSE = 0x600B4000 ); diff --git a/components/soc/esp32h21/register/soc/lp_analog_peri_reg.h b/components/soc/esp32h21/register/soc/lp_analog_peri_reg.h new file mode 100644 index 0000000000..8ab77f212f --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_analog_peri_reg.h @@ -0,0 +1,469 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_VDD_SOURCE_CNTL_REG register + * need_des + */ +#define LP_ANA_VDD_SOURCE_CNTL_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_ANA_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_ANA_DETMODE_SEL 0x000000FFU +#define LP_ANA_DETMODE_SEL_M (LP_ANA_DETMODE_SEL_V << LP_ANA_DETMODE_SEL_S) +#define LP_ANA_DETMODE_SEL_V 0x000000FFU +#define LP_ANA_DETMODE_SEL_S 0 +/** LP_ANA_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define LP_ANA_VGOOD_EVENT_RECORD 0x000000FFU +#define LP_ANA_VGOOD_EVENT_RECORD_M (LP_ANA_VGOOD_EVENT_RECORD_V << LP_ANA_VGOOD_EVENT_RECORD_S) +#define LP_ANA_VGOOD_EVENT_RECORD_V 0x000000FFU +#define LP_ANA_VGOOD_EVENT_RECORD_S 8 +/** LP_ANA_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_ANA_VBAT_EVENT_RECORD_CLR 0x000000FFU +#define LP_ANA_VBAT_EVENT_RECORD_CLR_M (LP_ANA_VBAT_EVENT_RECORD_CLR_V << LP_ANA_VBAT_EVENT_RECORD_CLR_S) +#define LP_ANA_VBAT_EVENT_RECORD_CLR_V 0x000000FFU +#define LP_ANA_VBAT_EVENT_RECORD_CLR_S 16 +/** LP_ANA_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4; + * need_des + */ +#define LP_ANA_BOD_SOURCE_ENA 0x000000FFU +#define LP_ANA_BOD_SOURCE_ENA_M (LP_ANA_BOD_SOURCE_ENA_V << LP_ANA_BOD_SOURCE_ENA_S) +#define LP_ANA_BOD_SOURCE_ENA_V 0x000000FFU +#define LP_ANA_BOD_SOURCE_ENA_S 24 + +/** LP_ANA_VDDBAT_BOD_CNTL_REG register + * need_des + */ +#define LP_ANA_VDDBAT_BOD_CNTL_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANA_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGER (BIT(10)) +#define LP_ANA_VDDBAT_CHARGER_M (LP_ANA_VDDBAT_CHARGER_V << LP_ANA_VDDBAT_CHARGER_S) +#define LP_ANA_VDDBAT_CHARGER_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGER_S 10 +/** LP_ANA_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CNT_CLR (BIT(11)) +#define LP_ANA_VDDBAT_CNT_CLR_M (LP_ANA_VDDBAT_CNT_CLR_V << LP_ANA_VDDBAT_CNT_CLR_S) +#define LP_ANA_VDDBAT_CNT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CNT_CLR_S 11 +/** LP_ANA_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S 12 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANA_VDDBAT_CHARGE_CNTL_REG register + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANA_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CHARGER (BIT(10)) +#define LP_ANA_VDDBAT_CHARGE_CHARGER_M (LP_ANA_VDDBAT_CHARGE_CHARGER_V << LP_ANA_VDDBAT_CHARGE_CHARGER_S) +#define LP_ANA_VDDBAT_CHARGE_CHARGER_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_CHARGER_S 10 +/** LP_ANA_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR (BIT(11)) +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_M (LP_ANA_VDDBAT_CHARGE_CNT_CLR_V << LP_ANA_VDDBAT_CHARGE_CNT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_S 11 +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S 12 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANA_PG_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_PG_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define LP_ANA_POWER_GLITCH_RESET_ENA 0x0000003FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_M (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S) +#define LP_ANA_POWER_GLITCH_RESET_ENA_V 0x0000003FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_S 26 + +/** LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define LP_ANA_ANA_FIB_ENA 0x000000FFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0x000000FFU +#define LP_ANA_ANA_FIB_ENA_S 24 + +#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) + +/** LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S 30 +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S 30 +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S 30 +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S 30 +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANA_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37765696; + * need_des + */ +#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 0 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_analog_peri_struct.h b/components/soc/esp32h21/register/soc/lp_analog_peri_struct.h new file mode 100644 index 0000000000..668408f504 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_analog_peri_struct.h @@ -0,0 +1,420 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of ana_bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** ana_bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_close_flash_ena:1; + /** ana_bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_pd_rf_ena:1; + /** ana_bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t ana_bod_mode0_intr_wait:10; + /** ana_bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t ana_bod_mode0_reset_wait:10; + /** ana_bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_cnt_clr:1; + /** ana_bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_intr_ena:1; + /** ana_bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_reset_sel:1; + /** ana_bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of ana_bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ana_vdd_source_cntl register + * need_des + */ +typedef union { + struct { + /** ana_detmode_sel : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t ana_detmode_sel:8; + /** ana_vgood_event_record : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t ana_vgood_event_record:8; + /** ana_vbat_event_record_clr : WT; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t ana_vbat_event_record_clr:8; + /** ana_bod_source_ena : R/W; bitpos: [31:24]; default: 4; + * need_des + */ + uint32_t ana_bod_source_ena:8; + }; + uint32_t val; +} lp_ana_vdd_source_cntl_reg_t; + +/** Type of ana_vddbat_bod_cntl register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_flag:1; + uint32_t reserved_1:9; + /** ana_vddbat_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charger:1; + /** ana_vddbat_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t ana_vddbat_cnt_clr:1; + /** ana_vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_target:10; + /** ana_vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t ana_vddbat_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_bod_cntl_reg_t; + +/** Type of ana_vddbat_charge_cntl register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_flag:1; + uint32_t reserved_1:9; + /** ana_vddbat_charge_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_charger:1; + /** ana_vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_cnt_clr:1; + /** ana_vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_target:10; + /** ana_vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_charge_cntl_reg_t; + +/** Type of ana_ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of ana_pg_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** ana_power_glitch_reset_ena : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t ana_power_glitch_reset_ena:6; + }; + uint32_t val; +} lp_ana_pg_glitch_cntl_reg_t; + +/** Type of ana_fib_enable register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** ana_ana_fib_ena : R/W; bitpos: [31:24]; default: 255; + * need_des + */ + uint32_t ana_ana_fib_ena:8; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of ana_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_raw:1; + /** ana_vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_raw:1; + /** ana_vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_raw:1; + /** ana_vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_raw:1; + /** ana_bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of ana_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_st:1; + /** ana_vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_st:1; + /** ana_vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_st:1; + /** ana_vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_st:1; + /** ana_bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of ana_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_ena:1; + /** ana_vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_ena:1; + /** ana_vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_ena:1; + /** ana_vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_ena:1; + /** ana_bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of ana_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_clr:1; + /** ana_vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_clr:1; + /** ana_vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_clr:1; + /** ana_vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_clr:1; + /** ana_bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of ana_lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of ana_lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of ana_lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of ana_lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of ana_date register + * need_des + */ +typedef union { + struct { + /** ana_lp_ana_date : R/W; bitpos: [30:0]; default: 37765696; + * need_des + */ + uint32_t ana_lp_ana_date:31; + /** ana_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t ana_bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t ana_bod_mode1_cntl; + volatile lp_ana_vdd_source_cntl_reg_t ana_vdd_source_cntl; + volatile lp_ana_vddbat_bod_cntl_reg_t ana_vddbat_bod_cntl; + volatile lp_ana_vddbat_charge_cntl_reg_t ana_vddbat_charge_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ana_ck_glitch_cntl; + volatile lp_ana_pg_glitch_cntl_reg_t ana_pg_glitch_cntl; + volatile lp_ana_fib_enable_reg_t ana_fib_enable; + volatile lp_ana_int_raw_reg_t ana_int_raw; + volatile lp_ana_int_st_reg_t ana_int_st; + volatile lp_ana_int_ena_reg_t ana_int_ena; + volatile lp_ana_int_clr_reg_t ana_int_clr; + volatile lp_ana_lp_int_raw_reg_t ana_lp_int_raw; + volatile lp_ana_lp_int_st_reg_t ana_lp_int_st; + volatile lp_ana_lp_int_ena_reg_t ana_lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t ana_lp_int_clr; + uint32_t reserved_040[239]; + volatile lp_ana_date_reg_t ana_date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_aon_reg.h b/components/soc/esp32h21/register/soc/lp_aon_reg.h new file mode 100644 index 0000000000..726e391d7e --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_aon_reg.h @@ -0,0 +1,470 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_ANA_FIB_SWD_ENABLE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_SWD_ENABLE (BIT(0)) +#define LP_AON_ANA_FIB_SWD_ENABLE_M (LP_AON_ANA_FIB_SWD_ENABLE_V << LP_AON_ANA_FIB_SWD_ENABLE_S) +#define LP_AON_ANA_FIB_SWD_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_SWD_ENABLE_S 0 +/** LP_AON_ANA_FIB_CK_GLITCH_ENABLE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE (BIT(1)) +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_M (LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V << LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S) +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S 1 +/** LP_AON_ANA_FIB_BOD_ENABLE : RO; bitpos: [2]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_BOD_ENABLE (BIT(2)) +#define LP_AON_ANA_FIB_BOD_ENABLE_M (LP_AON_ANA_FIB_BOD_ENABLE_V << LP_AON_ANA_FIB_BOD_ENABLE_S) +#define LP_AON_ANA_FIB_BOD_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_BOD_ENABLE_S 2 +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_PULL_LDO 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_M (LP_AON_IO_MUX_PULL_LDO_V << LP_AON_IO_MUX_PULL_LDO_S) +#define LP_AON_IO_MUX_PULL_LDO_V 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_S 28 +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_SDIO_ACTIVE_REG register + * need_des + */ +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des + */ +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_JTAG_SEL_REG register + * need_des + */ +#define LP_AON_JTAG_SEL_REG (DR_REG_LP_AON_BASE + 0x58) +/** LP_AON_JTAG_SEL_SOFT : R/W; bitpos: [31]; default: 1; + * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or + * usb_jtag is disabled by efuse, this field determines which one jtag between + * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + */ +#define LP_AON_JTAG_SEL_SOFT (BIT(31)) +#define LP_AON_JTAG_SEL_SOFT_M (LP_AON_JTAG_SEL_SOFT_V << LP_AON_JTAG_SEL_SOFT_S) +#define LP_AON_JTAG_SEL_SOFT_V 0x00000001U +#define LP_AON_JTAG_SEL_SOFT_S 31 + +/** LP_AON_BACKUP_DMA_CFG0_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG0_REG (DR_REG_LP_AON_BASE + 0x70) +/** LP_AON_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10; + * Set this field to configure max value of burst in single transfer. + */ +#define LP_AON_BURST_LIMIT_AON 0x0000001FU +#define LP_AON_BURST_LIMIT_AON_M (LP_AON_BURST_LIMIT_AON_V << LP_AON_BURST_LIMIT_AON_S) +#define LP_AON_BURST_LIMIT_AON_V 0x0000001FU +#define LP_AON_BURST_LIMIT_AON_S 0 +/** LP_AON_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10; + * Set this field to configure read registers' interval time in reading mode. + */ +#define LP_AON_READ_INTERVAL_AON 0x0000007FU +#define LP_AON_READ_INTERVAL_AON_M (LP_AON_READ_INTERVAL_AON_V << LP_AON_READ_INTERVAL_AON_S) +#define LP_AON_READ_INTERVAL_AON_V 0x0000007FU +#define LP_AON_READ_INTERVAL_AON_S 5 +/** LP_AON_BRANCH_LINK_LENGTH_AON : R/W; bitpos: [15:12]; default: 0; + * Set this field to configure link address. + */ +#define LP_AON_BRANCH_LINK_LENGTH_AON 0x0000000FU +#define LP_AON_BRANCH_LINK_LENGTH_AON_M (LP_AON_BRANCH_LINK_LENGTH_AON_V << LP_AON_BRANCH_LINK_LENGTH_AON_S) +#define LP_AON_BRANCH_LINK_LENGTH_AON_V 0x0000000FU +#define LP_AON_BRANCH_LINK_LENGTH_AON_S 12 + +/** LP_AON_BACKUP_DMA_CFG1_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG1_REG (DR_REG_LP_AON_BASE + 0x74) +/** LP_AON_LINK_WAIT_TOUT_THRES_AON : R/W; bitpos: [9:0]; default: 100; + * Set this field to configure the number of consecutive links of link list. + */ +#define LP_AON_LINK_WAIT_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_M (LP_AON_LINK_WAIT_TOUT_THRES_AON_V << LP_AON_LINK_WAIT_TOUT_THRES_AON_S) +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_S 0 +/** LP_AON_LINK_WORK_TOUT_THRES_AON : R/W; bitpos: [19:10]; default: 100; + * Set this field to configure maximum waiting time in waiting mode. + */ +#define LP_AON_LINK_WORK_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_WORK_TOUT_THRES_AON_M (LP_AON_LINK_WORK_TOUT_THRES_AON_V << LP_AON_LINK_WORK_TOUT_THRES_AON_S) +#define LP_AON_LINK_WORK_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_WORK_TOUT_THRES_AON_S 10 +/** LP_AON_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [29:20]; default: 100; + * Set this field to configure maximum waiting time in backup mode. + */ +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_M (LP_AON_LINK_BACKUP_TOUT_THRES_AON_V << LP_AON_LINK_BACKUP_TOUT_THRES_AON_S) +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20 + +/** LP_AON_BACKUP_DMA_CFG2_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG2_REG (DR_REG_LP_AON_BASE + 0x78) +/** LP_AON_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0; + * Set this field to configure link address. + */ +#define LP_AON_LINK_ADDR_AON 0xFFFFFFFFU +#define LP_AON_LINK_ADDR_AON_M (LP_AON_LINK_ADDR_AON_V << LP_AON_LINK_ADDR_AON_S) +#define LP_AON_LINK_ADDR_AON_V 0xFFFFFFFFU +#define LP_AON_LINK_ADDR_AON_S 0 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37781648; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_aon_struct.h b/components/soc/esp32h21/register/soc/lp_aon_struct.h new file mode 100644 index 0000000000..951d8cfc5d --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_aon_struct.h @@ -0,0 +1,487 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of aon_store0 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store0:32; + }; + uint32_t val; +} lp_aon_store0_reg_t; + +/** Type of aon_store1 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store1:32; + }; + uint32_t val; +} lp_aon_store1_reg_t; + +/** Type of aon_store2 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store2:32; + }; + uint32_t val; +} lp_aon_store2_reg_t; + +/** Type of aon_store3 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store3:32; + }; + uint32_t val; +} lp_aon_store3_reg_t; + +/** Type of aon_store4 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store4:32; + }; + uint32_t val; +} lp_aon_store4_reg_t; + +/** Type of aon_store5 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store5:32; + }; + uint32_t val; +} lp_aon_store5_reg_t; + +/** Type of aon_store6 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store6:32; + }; + uint32_t val; +} lp_aon_store6_reg_t; + +/** Type of aon_store7 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store7:32; + }; + uint32_t val; +} lp_aon_store7_reg_t; + +/** Type of aon_store8 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store8:32; + }; + uint32_t val; +} lp_aon_store8_reg_t; + +/** Type of aon_store9 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store9:32; + }; + uint32_t val; +} lp_aon_store9_reg_t; + +/** Type of aon_gpio_mux register + * need_des + */ +typedef union { + struct { + /** aon_gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t aon_gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of aon_gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of aon_gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** aon_gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of aon_sys_cfg register + * need_des + */ +typedef union { + struct { + /** aon_ana_fib_swd_enable : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t aon_ana_fib_swd_enable:1; + /** aon_ana_fib_ck_glitch_enable : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t aon_ana_fib_ck_glitch_enable:1; + /** aon_ana_fib_bod_enable : RO; bitpos: [2]; default: 1; + * need_des + */ + uint32_t aon_ana_fib_bod_enable:1; + uint32_t reserved_3:27; + /** aon_force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t aon_force_download_boot:1; + /** aon_hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of aon_cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** aon_cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** aon_cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_sw_reset:1; + /** aon_cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_ocd_halt_on_reset:1; + /** aon_cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t aon_cpu_core0_stat_vector_sel:1; + /** aon_cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of aon_io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t aon_io_mux_pull_ldo:3; + /** aon_io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of aon_ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** aon_ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_status:8; + uint32_t reserved_8:6; + /** aon_ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_status_clr:1; + /** aon_ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_sel:8; + /** aon_ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_lv:8; + /** aon_ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of aon_usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** aon_usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of aon_sdio_active register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** aon_sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des + */ + uint32_t aon_sdio_act_dnum:10; + }; + uint32_t val; +} lp_aon_sdio_active_reg_t; + +/** Type of aon_lpcore register + * need_des + */ +typedef union { + struct { + /** aon_lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t aon_lpcore_etm_wakeup_flag_clr:1; + /** aon_lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t aon_lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** aon_lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of aon_sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** aon_sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t aon_sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of aon_jtag_sel register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** aon_jtag_sel_soft : R/W; bitpos: [31]; default: 1; + * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or + * usb_jtag is disabled by efuse, this field determines which one jtag between + * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + */ + uint32_t aon_jtag_sel_soft:1; + }; + uint32_t val; +} lp_aon_jtag_sel_reg_t; + +/** Type of aon_backup_dma_cfg0 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_burst_limit_aon : R/W; bitpos: [4:0]; default: 10; + * Set this field to configure max value of burst in single transfer. + */ + uint32_t aon_burst_limit_aon:5; + /** aon_read_interval_aon : R/W; bitpos: [11:5]; default: 10; + * Set this field to configure read registers' interval time in reading mode. + */ + uint32_t aon_read_interval_aon:7; + /** aon_branch_link_length_aon : R/W; bitpos: [15:12]; default: 0; + * Set this field to configure link address. + */ + uint32_t aon_branch_link_length_aon:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_aon_backup_dma_cfg0_reg_t; + +/** Type of aon_backup_dma_cfg1 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_link_wait_tout_thres_aon : R/W; bitpos: [9:0]; default: 100; + * Set this field to configure the number of consecutive links of link list. + */ + uint32_t aon_link_wait_tout_thres_aon:10; + /** aon_link_work_tout_thres_aon : R/W; bitpos: [19:10]; default: 100; + * Set this field to configure maximum waiting time in waiting mode. + */ + uint32_t aon_link_work_tout_thres_aon:10; + /** aon_link_backup_tout_thres_aon : R/W; bitpos: [29:20]; default: 100; + * Set this field to configure maximum waiting time in backup mode. + */ + uint32_t aon_link_backup_tout_thres_aon:10; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_aon_backup_dma_cfg1_reg_t; + +/** Type of aon_backup_dma_cfg2 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_link_addr_aon : R/W; bitpos: [31:0]; default: 0; + * Set this field to configure link address. + */ + uint32_t aon_link_addr_aon:32; + }; + uint32_t val; +} lp_aon_backup_dma_cfg2_reg_t; + +/** Type of aon_date register + * need_des + */ +typedef union { + struct { + /** aon_date : R/W; bitpos: [30:0]; default: 37781648; + * need_des + */ + uint32_t aon_date:31; + /** aon_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +typedef struct { + volatile lp_aon_store0_reg_t store0; + volatile lp_aon_store1_reg_t store1; + volatile lp_aon_store2_reg_t store2; + volatile lp_aon_store3_reg_t store3; + volatile lp_aon_store4_reg_t store4; + volatile lp_aon_store5_reg_t store5; + volatile lp_aon_store6_reg_t store6; + volatile lp_aon_store7_reg_t store7; + volatile lp_aon_store8_reg_t store8; + volatile lp_aon_store9_reg_t store9; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + uint32_t reserved_048; + volatile lp_aon_sdio_active_reg_t sdio_active; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + volatile lp_aon_jtag_sel_reg_t _jtag_sel; + uint32_t reserved_05c[5]; + volatile lp_aon_backup_dma_cfg0_reg_t backup_dma_cfg0; + volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1; + volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2; + uint32_t reserved_07c[224]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm0_reg.h b/components/soc/esp32h21/register/soc/lp_apm0_reg.h new file mode 100644 index 0000000000..17220e50a9 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm0_reg.h @@ -0,0 +1,506 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM0_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0) +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) +#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_S 0 + +/** LP_APM0_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4) +/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) +#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_S 0 + +/** LP_APM0_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8) +/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) +#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_S 0 + +/** LP_APM0_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc) +/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) +#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_X_S 0 +/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) +#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_W_S 1 +/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) +#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_R_S 2 +/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) +#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_X_S 4 +/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) +#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_W_S 5 +/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) +#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_R_S 6 +/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) +#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_X_S 8 +/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) +#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_W_S 9 +/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) +#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_R_S 10 + +/** LP_APM0_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10) +/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) +#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_S 0 + +/** LP_APM0_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14) +/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) +#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_S 0 + +/** LP_APM0_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18) +/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) +#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_X_S 0 +/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) +#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_W_S 1 +/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) +#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_R_S 2 +/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) +#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_X_S 4 +/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) +#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_W_S 5 +/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) +#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_R_S 6 +/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) +#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_X_S 8 +/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) +#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_W_S 9 +/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) +#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_R_S 10 + +/** LP_APM0_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_BASE + 0x1c) +/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) +#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_S 0 + +/** LP_APM0_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_BASE + 0x20) +/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) +#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_S 0 + +/** LP_APM0_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_BASE + 0x24) +/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) +#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_X_S 0 +/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) +#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_W_S 1 +/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) +#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_R_S 2 +/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) +#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_X_S 4 +/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) +#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_W_S 5 +/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) +#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_R_S 6 +/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) +#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_X_S 8 +/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) +#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_W_S 9 +/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) +#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_R_S 10 + +/** LP_APM0_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_BASE + 0x28) +/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) +#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_S 0 + +/** LP_APM0_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_BASE + 0x2c) +/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) +#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_S 0 + +/** LP_APM0_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_BASE + 0x30) +/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) +#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_X_S 0 +/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) +#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_W_S 1 +/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) +#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_R_S 2 +/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) +#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_X_S 4 +/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) +#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_W_S 5 +/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) +#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_R_S 6 +/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) +#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_X_S 8 +/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) +#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_W_S 9 +/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) +#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_R_S 10 + +/** LP_APM0_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4) +/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) +#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM0_M0_PMS_FUNC_EN_S 0 + +/** LP_APM0_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8) +/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) +#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM0_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc) +/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) +#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM0_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM0_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0) +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) +#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_S 0 +/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) +#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_S 16 +/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) +#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_S 18 + +/** LP_APM0_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4) +/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) +#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM0_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM0_INT_EN_REG (DR_REG_LP_BASE + 0xd8) +/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM0_M0_APM_INT_EN (BIT(0)) +#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) +#define LP_APM0_M0_APM_INT_EN_V 0x00000001U +#define LP_APM0_M0_APM_INT_EN_S 0 + +/** LP_APM0_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xdc) +/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM0_CLK_EN (BIT(0)) +#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) +#define LP_APM0_CLK_EN_V 0x00000001U +#define LP_APM0_CLK_EN_S 0 + +/** LP_APM0_DATE_REG register + * Version register + */ +#define LP_APM0_DATE_REG (DR_REG_LP_BASE + 0x7fc) +/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define LP_APM0_DATE 0x0FFFFFFFU +#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) +#define LP_APM0_DATE_V 0x0FFFFFFFU +#define LP_APM0_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm0_struct.h b/components/soc/esp32h21/register/soc/lp_apm0_struct.h new file mode 100644 index 0000000000..48258e4a57 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm0_struct.h @@ -0,0 +1,499 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of apm0_region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** apm0_region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t apm0_region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm0_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of apm0_region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t apm0_region0_addr_start:32; + }; + uint32_t val; +} lp_apm0_region0_addr_start_reg_t; + +/** Type of apm0_region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t apm0_region0_addr_end:32; + }; + uint32_t val; +} lp_apm0_region0_addr_end_reg_t; + +/** Type of apm0_region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t apm0_region1_addr_start:32; + }; + uint32_t val; +} lp_apm0_region1_addr_start_reg_t; + +/** Type of apm0_region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t apm0_region1_addr_end:32; + }; + uint32_t val; +} lp_apm0_region1_addr_end_reg_t; + +/** Type of apm0_region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t apm0_region2_addr_start:32; + }; + uint32_t val; +} lp_apm0_region2_addr_start_reg_t; + +/** Type of apm0_region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t apm0_region2_addr_end:32; + }; + uint32_t val; +} lp_apm0_region2_addr_end_reg_t; + +/** Type of apm0_region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t apm0_region3_addr_start:32; + }; + uint32_t val; +} lp_apm0_region3_addr_start_reg_t; + +/** Type of apm0_region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t apm0_region3_addr_end:32; + }; + uint32_t val; +} lp_apm0_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of apm0_region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region0_r0_pms_x:1; + /** apm0_region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region0_r0_pms_w:1; + /** apm0_region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region0_r1_pms_x:1; + /** apm0_region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region0_r1_pms_w:1; + /** apm0_region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region0_r2_pms_x:1; + /** apm0_region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region0_r2_pms_w:1; + /** apm0_region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region0_pms_attr_reg_t; + +/** Type of apm0_region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region1_r0_pms_x:1; + /** apm0_region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region1_r0_pms_w:1; + /** apm0_region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region1_r1_pms_x:1; + /** apm0_region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region1_r1_pms_w:1; + /** apm0_region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region1_r2_pms_x:1; + /** apm0_region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region1_r2_pms_w:1; + /** apm0_region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region1_pms_attr_reg_t; + +/** Type of apm0_region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region2_r0_pms_x:1; + /** apm0_region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region2_r0_pms_w:1; + /** apm0_region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region2_r1_pms_x:1; + /** apm0_region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region2_r1_pms_w:1; + /** apm0_region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region2_r2_pms_x:1; + /** apm0_region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region2_r2_pms_w:1; + /** apm0_region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region2_pms_attr_reg_t; + +/** Type of apm0_region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region3_r0_pms_x:1; + /** apm0_region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region3_r0_pms_w:1; + /** apm0_region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region3_r1_pms_x:1; + /** apm0_region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region3_r1_pms_w:1; + /** apm0_region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region3_r2_pms_x:1; + /** apm0_region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region3_r2_pms_w:1; + /** apm0_region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of apm0_func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** apm0_m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t apm0_m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of apm0_m0_status register + * M0 status register + */ +typedef union { + struct { + /** apm0_m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t apm0_m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm0_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of apm0_m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** apm0_m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t apm0_m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of apm0_m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** apm0_m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t apm0_m0_exception_region:4; + uint32_t reserved_4:12; + /** apm0_m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t apm0_m0_exception_mode:2; + /** apm0_m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t apm0_m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm0_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of apm0_m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** apm0_m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t apm0_m0_exception_addr:32; + }; + uint32_t val; +} lp_apm0_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of apm0_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** apm0_m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t apm0_m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of apm0_clock_gate register + * clock gating register + */ +typedef union { + struct { + /** apm0_clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t apm0_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of apm0_date register + * Version register + */ +typedef union { + struct { + /** apm0_date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t apm0_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm0_date_reg_t; + + +typedef struct { + volatile lp_apm0_region_filter_en_reg_t apm0_region_filter_en; + volatile lp_apm0_region0_addr_start_reg_t apm0_region0_addr_start; + volatile lp_apm0_region0_addr_end_reg_t apm0_region0_addr_end; + volatile lp_apm0_region0_pms_attr_reg_t apm0_region0_pms_attr; + volatile lp_apm0_region1_addr_start_reg_t apm0_region1_addr_start; + volatile lp_apm0_region1_addr_end_reg_t apm0_region1_addr_end; + volatile lp_apm0_region1_pms_attr_reg_t apm0_region1_pms_attr; + volatile lp_apm0_region2_addr_start_reg_t apm0_region2_addr_start; + volatile lp_apm0_region2_addr_end_reg_t apm0_region2_addr_end; + volatile lp_apm0_region2_pms_attr_reg_t apm0_region2_pms_attr; + volatile lp_apm0_region3_addr_start_reg_t apm0_region3_addr_start; + volatile lp_apm0_region3_addr_end_reg_t apm0_region3_addr_end; + volatile lp_apm0_region3_pms_attr_reg_t apm0_region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm0_func_ctrl_reg_t apm0_func_ctrl; + volatile lp_apm0_m0_status_reg_t apm0_m0_status; + volatile lp_apm0_m0_status_clr_reg_t apm0_m0_status_clr; + volatile lp_apm0_m0_exception_info0_reg_t apm0_m0_exception_info0; + volatile lp_apm0_m0_exception_info1_reg_t apm0_m0_exception_info1; + volatile lp_apm0_int_en_reg_t apm0_int_en; + volatile lp_apm0_clock_gate_reg_t apm0_clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm0_date_reg_t apm0_date; +} lp_apm0_dev_t; + +extern lp_apm0_dev_t LP_APM0; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm_reg.h b/components/soc/esp32h21/register/soc/lp_apm_reg.h new file mode 100644 index 0000000000..6e433906e1 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm_reg.h @@ -0,0 +1,322 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [1:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x00000003U +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x00000003U +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [1:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x00000003U +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x00000003U +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35680864; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm_struct.h b/components/soc/esp32h21/register/soc/lp_apm_struct.h new file mode 100644 index 0000000000..974b642d00 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm_struct.h @@ -0,0 +1,346 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of apm_region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** apm_region_filter_en : R/W; bitpos: [1:0]; default: 1; + * Region filter enable + */ + uint32_t apm_region_filter_en:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of apm_region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm_region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t apm_region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of apm_region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm_region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t apm_region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of apm_region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm_region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t apm_region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of apm_region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm_region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t apm_region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of apm_region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm_region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm_region0_r0_pms_x:1; + /** apm_region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm_region0_r0_pms_w:1; + /** apm_region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm_region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm_region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm_region0_r1_pms_x:1; + /** apm_region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm_region0_r1_pms_w:1; + /** apm_region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm_region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm_region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm_region0_r2_pms_x:1; + /** apm_region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm_region0_r2_pms_w:1; + /** apm_region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm_region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of apm_region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm_region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm_region1_r0_pms_x:1; + /** apm_region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm_region1_r0_pms_w:1; + /** apm_region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm_region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm_region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm_region1_r1_pms_x:1; + /** apm_region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm_region1_r1_pms_w:1; + /** apm_region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm_region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm_region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm_region1_r2_pms_x:1; + /** apm_region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm_region1_r2_pms_w:1; + /** apm_region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm_region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of apm_func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** apm_m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t apm_m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of apm_m0_status register + * M0 status register + */ +typedef union { + struct { + /** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t apm_m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of apm_m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** apm_m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t apm_m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of apm_m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** apm_m0_exception_region : RO; bitpos: [1:0]; default: 0; + * Exception region + */ + uint32_t apm_m0_exception_region:2; + uint32_t reserved_2:14; + /** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t apm_m0_exception_mode:2; + /** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t apm_m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of apm_m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t apm_m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of apm_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t apm_m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of apm_clock_gate register + * clock gating register + */ +typedef union { + struct { + /** apm_clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t apm_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of apm_date register + * Version register + */ +typedef union { + struct { + /** apm_date : R/W; bitpos: [27:0]; default: 35680864; + * reg_date + */ + uint32_t apm_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct { + volatile lp_apm_region_filter_en_reg_t apm_region_filter_en; + volatile lp_apm_region0_addr_start_reg_t apm_region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t apm_region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t apm_region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t apm_region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t apm_region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t apm_region1_pms_attr; + uint32_t reserved_01c[42]; + volatile lp_apm_func_ctrl_reg_t apm_func_ctrl; + volatile lp_apm_m0_status_reg_t apm_m0_status; + volatile lp_apm_m0_status_clr_reg_t apm_m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t apm_m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t apm_m0_exception_info1; + uint32_t reserved_0d8[4]; + volatile lp_apm_int_en_reg_t apm_int_en; + volatile lp_apm_clock_gate_reg_t apm_clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t apm_date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_clkrst_reg.h b/components/soc/esp32h21/register/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..a1c3f6dfe5 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_clkrst_reg.h @@ -0,0 +1,431 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * need_des + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * need_des + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * need_des + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 600; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 650; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_LP_BLETIMER_DIV_NUM : R/W; bitpos: [23:12]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_DIV_NUM 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_M (LP_CLKRST_LP_BLETIMER_DIV_NUM_V << LP_CLKRST_LP_BLETIMER_DIV_NUM_S) +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_V 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_S 12 +/** LP_CLKRST_LP_BLETIMER_32K_SEL : R/W; bitpos: [25:24]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_32K_SEL 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_M (LP_CLKRST_LP_BLETIMER_32K_SEL_V << LP_CLKRST_LP_BLETIMER_32K_SEL_S) +#define LP_CLKRST_LP_BLETIMER_32K_SEL_V 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_S 24 +/** LP_CLKRST_LP_SEL_OSC_SLOW : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_SLOW (BIT(26)) +#define LP_CLKRST_LP_SEL_OSC_SLOW_M (LP_CLKRST_LP_SEL_OSC_SLOW_V << LP_CLKRST_LP_SEL_OSC_SLOW_S) +#define LP_CLKRST_LP_SEL_OSC_SLOW_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_SLOW_S 26 +/** LP_CLKRST_LP_SEL_OSC_FAST : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_FAST (BIT(27)) +#define LP_CLKRST_LP_SEL_OSC_FAST_M (LP_CLKRST_LP_SEL_OSC_FAST_V << LP_CLKRST_LP_SEL_OSC_FAST_S) +#define LP_CLKRST_LP_SEL_OSC_FAST_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_FAST_S 27 +/** LP_CLKRST_LP_SEL_XTAL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL (BIT(28)) +#define LP_CLKRST_LP_SEL_XTAL_M (LP_CLKRST_LP_SEL_XTAL_V << LP_CLKRST_LP_SEL_XTAL_S) +#define LP_CLKRST_LP_SEL_XTAL_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL_S 28 +/** LP_CLKRST_LP_SEL_XTAL32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL32K (BIT(29)) +#define LP_CLKRST_LP_SEL_XTAL32K_M (LP_CLKRST_LP_SEL_XTAL32K_V << LP_CLKRST_LP_SEL_XTAL32K_S) +#define LP_CLKRST_LP_SEL_XTAL32K_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL32K_S 29 +/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) +#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) +#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 +/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) +#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) +#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_UART_CLK_SEL_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_RTC_SEL_POWER_XTAL32K : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K (BIT(21)) +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_M (LP_CLKRST_RTC_SEL_POWER_XTAL32K_V << LP_CLKRST_RTC_SEL_POWER_XTAL32K_S) +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_V 0x00000001U +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_S 21 +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 37782064; + * need_des + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_clkrst_struct.h b/components/soc/esp32h21/register/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..4e5754ae46 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_clkrst_struct.h @@ -0,0 +1,369 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clkrst_lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** clkrst_slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t clkrst_slow_clk_sel:2; + /** clkrst_fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * need_des + */ + uint32_t clkrst_fast_clk_sel:2; + /** clkrst_lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; + * need_des + */ + uint32_t clkrst_lp_peri_div_num:8; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of clkrst_lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** clkrst_aon_slow_oen : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t clkrst_aon_slow_oen:1; + /** clkrst_aon_fast_oen : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t clkrst_aon_fast_oen:1; + /** clkrst_sosc_oen : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t clkrst_sosc_oen:1; + /** clkrst_fosc_oen : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t clkrst_fosc_oen:1; + /** clkrst_osc32k_oen : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t clkrst_osc32k_oen:1; + /** clkrst_xtal32k_oen : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t clkrst_xtal32k_oen:1; + /** clkrst_core_efuse_oen : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t clkrst_core_efuse_oen:1; + /** clkrst_slow_oen : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t clkrst_slow_oen:1; + /** clkrst_fast_oen : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t clkrst_fast_oen:1; + /** clkrst_rng_oen : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t clkrst_rng_oen:1; + /** clkrst_lpbus_oen : R/W; bitpos: [10]; default: 1; + * need_des + */ + uint32_t clkrst_lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of clkrst_lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clkrst_fast_ori_gate : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of clkrst_lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** clkrst_aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t clkrst_aon_efuse_core_reset_en:1; + /** clkrst_lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t clkrst_lp_timer_reset_en:1; + /** clkrst_wdt_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t clkrst_wdt_reset_en:1; + /** clkrst_ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of clkrst_reset_cause register + * need_des + */ +typedef union { + struct { + /** clkrst_reset_cause : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t clkrst_reset_cause:5; + /** clkrst_core0_reset_flag : RO; bitpos: [5]; default: 1; + * need_des + */ + uint32_t clkrst_core0_reset_flag:1; + uint32_t reserved_6:23; + /** clkrst_core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t clkrst_core0_reset_cause_clr:1; + /** clkrst_core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t clkrst_core0_reset_flag_set:1; + /** clkrst_core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of clkrst_cpu_reset register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** clkrst_rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * need_des + */ + uint32_t clkrst_rtc_wdt_cpu_reset_length:3; + /** clkrst_rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t clkrst_rtc_wdt_cpu_reset_en:1; + /** clkrst_cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * need_des + */ + uint32_t clkrst_cpu_stall_wait:5; + /** clkrst_cpu_stall_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of clkrst_fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** clkrst_fosc_dfreq : R/W; bitpos: [31:22]; default: 600; + * need_des + */ + uint32_t clkrst_fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of clkrst_rc32k_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** clkrst_rc32k_dfreq : R/W; bitpos: [31:22]; default: 650; + * need_des + */ + uint32_t clkrst_rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clkrst_clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** clkrst_icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_xtal32k:1; + /** clkrst_icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_sosc:1; + /** clkrst_icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_osc32k:1; + /** clkrst_icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of clkrst_lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clkrst_lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of clkrst_lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** clkrst_lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0; + * need_des + */ + uint32_t clkrst_lp_bletimer_div_num:12; + /** clkrst_lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0; + * need_des + */ + uint32_t clkrst_lp_bletimer_32k_sel:2; + /** clkrst_lp_sel_osc_slow : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_osc_slow:1; + /** clkrst_lp_sel_osc_fast : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_osc_fast:1; + /** clkrst_lp_sel_xtal : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_xtal:1; + /** clkrst_lp_sel_xtal32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_xtal32k:1; + /** clkrst_lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t clkrst_lp_i2c_clk_sel:1; + /** clkrst_lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_lp_uart_clk_sel:1; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of clkrst_xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** clkrst_rtc_sel_power_xtal32k : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t clkrst_rtc_sel_power_xtal32k:1; + /** clkrst_dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t clkrst_dres_xtal32k:3; + /** clkrst_dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t clkrst_dgm_xtal32k:3; + /** clkrst_dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t clkrst_dbuf_xtal32k:1; + /** clkrst_dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t clkrst_dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of clkrst_date register + * need_des + */ +typedef union { + struct { + /** clkrst_clkrst_date : R/W; bitpos: [30:0]; default: 37782064; + * need_des + */ + uint32_t clkrst_clkrst_date:31; + /** clkrst_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_lpperi_reg_t lpperi; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_peri_reg.h b/components/soc/esp32h21/register/soc/lp_peri_reg.h new file mode 100644 index 0000000000..593e87e2e1 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_peri_reg.h @@ -0,0 +1,388 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24)) +#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S) +#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U +#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; + * need des + */ +#define LPPERI_RTC_TIMER_EN 0x00000003U +#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S) +#define LPPERI_RTC_TIMER_EN_V 0x00000003U +#define LPPERI_RTC_TIMER_EN_S 10 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DEBUG_SEL0_REG register + * need des + */ +#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL0 0x0000007FU +#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S) +#define LPPERI_DEBUG_SEL0_V 0x0000007FU +#define LPPERI_DEBUG_SEL0_S 0 +/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL1 0x0000007FU +#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S) +#define LPPERI_DEBUG_SEL1_V 0x0000007FU +#define LPPERI_DEBUG_SEL1_S 7 +/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL2 0x0000007FU +#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S) +#define LPPERI_DEBUG_SEL2_V 0x0000007FU +#define LPPERI_DEBUG_SEL2_S 14 +/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL3 0x0000007FU +#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S) +#define LPPERI_DEBUG_SEL3_V 0x0000007FU +#define LPPERI_DEBUG_SEL3_S 21 + +/** LPPERI_DEBUG_SEL1_REG register + * need des + */ +#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x2c) +/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL4 0x0000007FU +#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S) +#define LPPERI_DEBUG_SEL4_V 0x0000007FU +#define LPPERI_DEBUG_SEL4_S 0 + +/** LPPERI_RNG_DATA_SYNC_REG register + * rng result sync register + */ +#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x30) +/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ +#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S) +#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_peri_struct.h b/components/soc/esp32h21/register/soc/lp_peri_struct.h new file mode 100644 index 0000000000..4ccec691b9 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_peri_struct.h @@ -0,0 +1,352 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; + * need des + */ + uint32_t rtc_timer_en:2; + uint32_t reserved_12:12; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_debug_sel1_reg_t; + +/** Type of rng_data_sync register + * rng result sync register + */ +typedef union { + struct { + /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ + uint32_t rnd_sync_data:32; + }; + uint32_t val; +} lpperi_rng_data_sync_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_cfg_reg_t rng_cfg; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_debug_sel0_reg_t debug_sel0; + volatile lpperi_debug_sel1_reg_t debug_sel1; + volatile lpperi_rng_data_sync_reg_t rng_data_sync; + uint32_t reserved_034[242]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_wdt_reg.h b/components/soc/esp32h21/register/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..d2b4cf0022 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_wdt_reg.h @@ -0,0 +1,350 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_CONFIG5_REG register + * need_des + */ +#define LP_WDT_CONFIG5_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_CHIP_RESET_TARGET : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_WDT_CHIP_RESET_TARGET 0x000000FFU +#define LP_WDT_CHIP_RESET_TARGET_M (LP_WDT_CHIP_RESET_TARGET_V << LP_WDT_CHIP_RESET_TARGET_S) +#define LP_WDT_CHIP_RESET_TARGET_V 0x000000FFU +#define LP_WDT_CHIP_RESET_TARGET_S 0 +/** LP_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_WDT_CHIP_RESET_EN (BIT(8)) +#define LP_WDT_CHIP_RESET_EN_M (LP_WDT_CHIP_RESET_EN_V << LP_WDT_CHIP_RESET_EN_S) +#define LP_WDT_CHIP_RESET_EN_V 0x00000001U +#define LP_WDT_CHIP_RESET_EN_S 8 +/** LP_WDT_CHIP_RESET_KEY : R/W; bitpos: [16:9]; default: 0; + * need_des + */ +#define LP_WDT_CHIP_RESET_KEY 0x000000FFU +#define LP_WDT_CHIP_RESET_KEY_M (LP_WDT_CHIP_RESET_KEY_V << LP_WDT_CHIP_RESET_KEY_S) +#define LP_WDT_CHIP_RESET_KEY_V 0x000000FFU +#define LP_WDT_CHIP_RESET_KEY_S 9 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x34) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_wdt_struct.h b/components/soc/esp32h21/register/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..4c010e18e9 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_wdt_struct.h @@ -0,0 +1,333 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of wdt_config0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_wdt_pause_in_slp:1; + /** wdt_wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_wdt_appcpu_reset_en:1; + /** wdt_wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_wdt_procpu_reset_en:1; + /** wdt_wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_wdt_flashboot_mod_en:1; + /** wdt_wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_wdt_sys_reset_length:3; + /** wdt_wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_wdt_cpu_reset_length:3; + /** wdt_wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg3:3; + /** wdt_wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg2:3; + /** wdt_wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg1:3; + /** wdt_wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg0:3; + /** wdt_wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of wdt_config1 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of wdt_config2 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of wdt_config3 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of wdt_config4 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of wdt_config5 register + * need_des + */ +typedef union { + struct { + /** wdt_chip_reset_target : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t wdt_chip_reset_target:8; + /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_en:1; + /** wdt_chip_reset_key : R/W; bitpos: [16:9]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_key:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_wdt_config5_reg_t; + +/** Type of wdt_feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** wdt_rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wdt_wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of wdt_swd_config register + * need_des + */ +typedef union { + struct { + /** wdt_swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t wdt_swd_reset_flag:1; + uint32_t reserved_1:17; + /** wdt_swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t wdt_swd_auto_feed_en:1; + /** wdt_swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t wdt_swd_rst_flag_clr:1; + /** wdt_swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t wdt_swd_signal_width:10; + /** wdt_swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_swd_disable:1; + /** wdt_swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of wdt_swd_wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of wdt_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_raw:1; + /** wdt_lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of wdt_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_st:1; + /** wdt_lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of wdt_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_ena:1; + /** wdt_lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of wdt_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_clr:1; + /** wdt_lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of wdt_date register + * need_des + */ +typedef union { + struct { + /** wdt_lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ + uint32_t wdt_lp_wdt_date:31; + /** wdt_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct { + volatile lp_wdt_config0_reg_t wdt_config0; + volatile lp_wdt_config1_reg_t wdt_config1; + volatile lp_wdt_config2_reg_t wdt_config2; + volatile lp_wdt_config3_reg_t wdt_config3; + volatile lp_wdt_config4_reg_t wdt_config4; + volatile lp_wdt_config5_reg_t wdt_config5; + volatile lp_wdt_feed_reg_t wdt_feed; + volatile lp_wdt_wprotect_reg_t wdt_wprotect; + volatile lp_wdt_swd_config_reg_t wdt_swd_config; + volatile lp_wdt_swd_wprotect_reg_t wdt_swd_wprotect; + volatile lp_wdt_int_raw_reg_t wdt_int_raw; + volatile lp_wdt_int_st_reg_t wdt_int_st; + volatile lp_wdt_int_ena_reg_t wdt_int_ena; + volatile lp_wdt_int_clr_reg_t wdt_int_clr; + uint32_t reserved_038[241]; + volatile lp_wdt_date_reg_t wdt_date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/reg_base.h b/components/soc/esp32h21/register/soc/reg_base.h new file mode 100644 index 0000000000..9a3a45bb95 --- /dev/null +++ b/components/soc/esp32h21/register/soc/reg_base.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DR_REG_UART0_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_SPIMEM0_BASE 0x60002000 +#define DR_REG_SPIMEM1_BASE 0x60003000 +#define DR_REG_I2C0_BASE 0x60004000 +#define DR_REG_I2C1_BASE 0x60005000 +#define DR_REG_UHCI0_BASE 0x60006000 +#define DR_REG_RMT_BASE 0x60007000 +#define DR_REG_LEDC_BASE 0x60008000 +#define DR_REG_TIMERG0_BASE 0x60009000 +#define DR_REG_TIMERG1_BASE 0x6000A000 +#define DR_REG_SYSTIMER_BASE 0x6000B000 +#define DR_REG_TWAI_BASE 0x6000C000 +#define DR_REG_I2S0_BASE 0x6000D000 +#define DR_REG_APB_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_PCNT_BASE 0x60012000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_MCPWM0_BASE 0x60014000 +#define DR_REG_PARL_IO_BASE 0x60015000 +#define DR_REG_PVT_BASE 0x60019000 +#define DR_REG_GDMA_BASE 0x60080000 +#define DR_REG_GPSPI2_BASE 0x60081000 +#define DR_REG_AES_BASE 0x60088000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_RSA_BASE 0x6008A000 +#define DR_REG_ECC_BASE 0x6008B000 +#define DR_REG_DS_BASE 0x6008C000 +#define DR_REG_HMAC_BASE 0x6008D000 +#define DR_REG_ECDSA_BASE 0x6008E000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_GPIO_EXT_BASE 0x60091e00 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_BASE 0x60098000 +#define DR_REG_HP_APM_BASE 0x60099000 +#define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00 +#define DR_REG_LP_TIMER_BASE 0x600B3000 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_EFUSE_BASE 0x600B4000