From c8c137f2b78e5019f79bd5086857221d51ccfb09 Mon Sep 17 00:00:00 2001 From: songruojing Date: Thu, 30 Dec 2021 20:31:38 +0800 Subject: [PATCH] esp32h2: support GPIO peripheral, IO_MUX, GPIO matrix. Generic GPIO example is supported as well. --- components/driver/gpio.c | 5 +- components/driver/test/test_gpio.c | 25 +- .../port/esp32h2/rtc_clk_init.c | 1 - components/hal/CMakeLists.txt | 8 + components/hal/esp32/include/hal/gpio_ll.h | 8 +- components/hal/esp32c2/include/hal/gpio_ll.h | 20 +- components/hal/esp32c3/include/hal/gpio_ll.h | 20 +- .../hal/esp32h2/include/rev1/hal/gpio_ll.h | 597 + .../esp32h2/include/{ => rev2}/hal/gpio_ll.h | 90 +- components/hal/esp32s2/include/hal/gpio_ll.h | 18 +- components/hal/esp32s3/include/hal/gpio_ll.h | 18 +- components/hal/include/hal/gpio_hal.h | 13 +- components/hal/include/hal/gpio_types.h | 93 +- components/soc/esp32h2/gpio_periph.c | 114 +- .../soc/esp32h2/include/rev1/soc/gpio_reg.h | 13119 +++++++++------- .../esp32h2/include/rev1/soc/gpio_struct.h | 609 + .../soc/esp32h2/include/rev1/soc/io_mux_reg.h | 161 +- .../include/rev1/soc/usb_serial_jtag_reg.h | 40 +- .../soc/esp32h2/include/rev2/soc/gpio_reg.h | 10524 +++++++------ .../esp32h2/include/rev2/soc/gpio_struct.h | 420 + .../soc/esp32h2/include/rev2/soc/io_mux_reg.h | 8 +- .../include/rev2/soc/usb_serial_jtag_reg.h | 42 +- .../esp32h2/include/soc/Kconfig.soc_caps.in | 2 +- .../soc/esp32h2/include/soc/gpio_struct.h | 437 - components/soc/esp32h2/include/soc/reg_base.h | 2 +- components/soc/esp32h2/include/soc/soc_caps.h | 33 +- components/soc/esp32s3/include/soc/reg_base.h | 2 +- .../soc/esp32s3/include/soc/usb_device_reg.h | 737 - .../esp32s3/include/soc/usb_serial_jtag_reg.h | 65 +- components/spi_flash/esp_flash_spi_init.c | 15 +- .../system/deep_sleep/main/Kconfig.projbuild | 10 +- tools/ci/check_copyright_ignore.txt | 3 - 32 files changed, 15881 insertions(+), 11378 deletions(-) create mode 100644 components/hal/esp32h2/include/rev1/hal/gpio_ll.h rename components/hal/esp32h2/include/{ => rev2}/hal/gpio_ll.h (87%) create mode 100644 components/soc/esp32h2/include/rev1/soc/gpio_struct.h create mode 100644 components/soc/esp32h2/include/rev2/soc/gpio_struct.h delete mode 100644 components/soc/esp32h2/include/soc/gpio_struct.h delete mode 100644 components/soc/esp32s3/include/soc/usb_device_reg.h diff --git a/components/driver/gpio.c b/components/driver/gpio.c index fc918f4f2e..9b3dbae6e9 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -561,7 +561,8 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) } #endif portENTER_CRITICAL(&gpio_context.gpio_spinlock); - gpio_hal_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type); + gpio_hal_set_intr_type(gpio_context.gpio_hal, gpio_num, intr_type); + gpio_hal_wakeup_enable(gpio_context.gpio_hal, gpio_num); #if SOC_GPIO_SUPPORT_SLP_SWITCH && CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num); #endif @@ -696,7 +697,7 @@ esp_err_t gpio_force_hold_all() rtc_gpio_force_hold_all(); #endif portENTER_CRITICAL(&gpio_context.gpio_spinlock); - gpio_hal_force_hold_all(gpio_context.gpio_hal); + gpio_hal_force_hold_all(); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c index b3d6183a92..5f73b2ebb8 100644 --- a/components/driver/test/test_gpio.c +++ b/components/driver/test/test_gpio.c @@ -70,6 +70,15 @@ #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX #define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 10 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1 +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 +#define TEST_GPIO_EXT_OUT_IO 6 // default output GPIO +#define TEST_GPIO_EXT_IN_IO 7 // default input GPIO +#define TEST_GPIO_OUTPUT_PIN 1 +#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX +#define TEST_GPIO_USB_DM_IO 24 // USB D- GPIO +#define TEST_GPIO_USB_DP_IO 25 // USB D+ GPIO +#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 9 +#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1 #endif // If there is any input-only pin, enable input-only pin part of some tests. @@ -113,7 +122,7 @@ __attribute__((unused)) static void gpio_isr_edge_handler(void *arg) edge_intr_times++; } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) //No runners // level interrupt event with "gpio_intr_disable" static void gpio_isr_level_handler(void *arg) @@ -138,7 +147,7 @@ static void gpio_isr_level_handler2(void *arg) esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", TEST_GPIO_EXT_OUT_IO, gpio_get_level(TEST_GPIO_EXT_OUT_IO), level_intr_times); esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) #if !WAKE_UP_IGNORE // get result of waking up or not @@ -223,7 +232,7 @@ TEST_CASE("GPIO config parameters test", "[gpio]") #endif // SOC_HAS_INPUT_ONLY_PIN } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) //No runners TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]") { @@ -415,7 +424,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO] TEST_ASSERT(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void *) TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE); TEST_ASSERT(gpio_isr_handler_remove(TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE); } -#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) +#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) #if !CONFIG_FREERTOS_UNICORE static void install_isr_service_task(void *arg) @@ -527,7 +536,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]") TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), 0, "gpio_pullup_dis error, it can pull up"); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) //No runners TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]") { @@ -601,7 +610,7 @@ TEST_CASE("GPIO repeate call service and isr has no memory leak test", "[gpio][t } TEST_ASSERT_INT32_WITHIN(size, esp_get_free_heap_size(), 100); } -#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) +#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) #if !WAKE_UP_IGNORE //this function development is not completed yet, set it ignored @@ -848,7 +857,7 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]") TEST_ASSERT((io9_param.isr_cnt == 1) && (io10_param.isr_cnt == 1)); } -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#if SOC_USB_SERIAL_JTAG_SUPPORTED TEST_CASE("GPIO input and output of USB pins test", "[gpio]") { const int test_pins[] = {TEST_GPIO_USB_DP_IO, TEST_GPIO_USB_DM_IO}; @@ -885,4 +894,4 @@ TEST_CASE("GPIO input and output of USB pins test", "[gpio]") TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!"); } } -#endif //CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#endif //SOC_USB_SERIAL_JTAG_SUPPORTED diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c index 77fa166ea9..fe88b95c66 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c @@ -21,7 +21,6 @@ #include "hal/cpu_hal.h" #include "regi2c_ctrl.h" #include "soc_log.h" -#include "sdkconfig.h" #include "rtc_clk_common.h" #include "esp_rom_uart.h" #include "soc/efuse_reg.h" diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 95fb28a874..48c74b8246 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -8,6 +8,14 @@ set(srcs "wdt_hal_iram.c" set(includes "${target}/include" "include" "platform_port/include") +if(target STREQUAL "esp32h2") + if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1) + list(APPEND includes "${target}/include/rev1") + elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2) + list(APPEND includes "${target}/include/rev2") + endif() +endif() + if(NOT BOOTLOADER_BUILD) list(APPEND srcs "rtc_io_hal.c" diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index fcff6a22bd..8e5237ae85 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -338,7 +338,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { if (gpio_num < 32) { hw->enable_w1ts = (0x1 << gpio_num); @@ -397,7 +397,7 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->pin[gpio_num].pad_driver = 0; } @@ -463,11 +463,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_type = intr_type; hw->pin[gpio_num].wakeup_enable = 0x1; } diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h index 9e7cbb7e7d..35c23774b2 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/hal/esp32c2/include/hal/gpio_ll.h @@ -7,7 +7,7 @@ /******************************************************************************* * NOTICE * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * See readme.md in hal/include/hal/readme.md ******************************************************************************/ // The LL layer for ESP32-C2 GPIO register operations @@ -198,7 +198,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); } @@ -209,7 +209,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->pin[gpio_num].pad_driver = 0; } @@ -263,11 +263,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_type = intr_type; hw->pin[gpio_num].wakeup_enable = 0x1; } @@ -397,13 +395,21 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } -static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); } +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ static inline void gpio_ll_force_unhold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index c8dac5a34b..907d1a35fe 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -7,7 +7,7 @@ /******************************************************************************* * NOTICE * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * See readme.md in hal/include/hal/readme.md ******************************************************************************/ // The LL layer for ESP32-C3 GPIO register operations @@ -200,7 +200,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); } @@ -211,7 +211,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->pin[gpio_num].pad_driver = 0; } @@ -265,11 +265,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_type = intr_type; hw->pin[gpio_num].wakeup_enable = 0x1; } @@ -403,13 +401,21 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } -static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); } +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ static inline void gpio_ll_force_unhold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); diff --git a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h new file mode 100644 index 0000000000..054a31fa94 --- /dev/null +++ b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h @@ -0,0 +1,597 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-H2 GPIO register operations + +#pragma once + +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/gpio_struct.h" +#include "soc/usb_serial_jtag_reg.h" +#include "hal/gpio_types.h" +#include "hal/assert.h" +#include "stdlib.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get GPIO hardware instance with giving gpio num +#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) + +#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) +/** + * @brief Enable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Disable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Enable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief Disable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief GPIO set interrupt trigger type + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].pin_int_type = intr_type; +} + +/** + * @brief Get GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status + */ +static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = hw->pcpu_int.procpu_int; +} + +/** + * @brief Get GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status high + */ +static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = hw->pcpu_int1.procpu_int1; +} + +/** + * @brief Clear GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status clear mask + */ +static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) +{ + hw->status_w1tc.status_w1tc = mask; +} + +/** + * @brief Clear GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status high clear mask + */ +static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) +{ + hw->status1_w1tc.status1_w1tc = mask; +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id Interrupt enabled CPU to corresponding ID + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num) +{ + HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); + GPIO.pin[gpio_num].pin_int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pin_int_ena = 0; //disable GPIO intr +} + +/** + * @brief Disable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); + } else { + hw->enable1_w1tc.enable1_w1tc = (0x1 << (gpio_num - 32)); + } + // Ensure no other output signal is routed via GPIO matrix to this pin + REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), + SIG_GPIO_OUT_IDX); +} + +/** + * @brief Enable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); + } else { + hw->enable1_w1ts.enable1_w1ts = (0x1 << (gpio_num - 32)); + } +} + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pin_pad_driver = 0; +} + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pin_pad_driver = 1; +} + +/** + * @brief GPIO set output level + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level) +{ + if (level) { + if (gpio_num < 32) { + hw->out_w1ts.out_w1ts = (1 << gpio_num); + } else { + hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32)); + } + } else { + if (gpio_num < 32) { + hw->out_w1tc.out_w1tc = (1 << gpio_num); + } else { + hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32)); + } + } +} + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num < 32) { + return (hw->in.in_data_next >> gpio_num) & 0x1; + } else { + return (hw->in1.in1_data_next >> (gpio_num - 32)) & 0x1; + } +} + +/** + * @brief Enable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + */ +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pin_wakeup_enable = 0x1; +} + +/** + * @brief Disable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + hw->pin[gpio_num].pin_wakeup_enable = 0; +} + +/** + * @brief Set GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength) +{ + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); +} + +/** + * @brief Get GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength) +{ + *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); +} + +/** + * @brief Enable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Disable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) +{ + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); +} + +/** + * @brief Enable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num <= GPIO_NUM_5) { + REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); + } else if (gpio_num <= GPIO_NUM_31) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); + } else { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); + } +} + +/** + * @brief Disable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + if (gpio_num <= GPIO_NUM_5) { + REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); + } else if (gpio_num <= GPIO_NUM_31) { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); + } +} + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) +{ + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); +} + +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function + if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(pin_name, func); +} + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) +{ + hw->func_out_sel_cfg[gpio_num].func_oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].func_oen_inv_sel = oen_inv; + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); +} + +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); +} + +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_unhold_all(void) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); +} + +/** + * @brief Enable GPIO pin used for wakeup from sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pin used for wakeup from sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO deep-sleep wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); + + REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); + REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); + SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); + uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG); + reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3))); + reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3)); + REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg); +} + +/** + * @brief Disable GPIO deep-sleep wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +{ + HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); + + CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); + CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h similarity index 87% rename from components/hal/esp32h2/include/hal/gpio_ll.h rename to components/hal/esp32h2/include/rev2/hal/gpio_ll.h index f38cf9c5d4..c1b07b109a 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h @@ -7,7 +7,7 @@ /******************************************************************************* * NOTICE * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * See readme.md in hal/include/hal/readme.md ******************************************************************************/ // The LL layer for ESP32-H2 GPIO register operations @@ -18,24 +18,15 @@ #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" #include "soc/gpio_struct.h" +#include "soc/usb_serial_jtag_reg.h" #include "hal/gpio_types.h" +#include "hal/assert.h" #include "stdlib.h" #ifdef __cplusplus extern "C" { #endif -/* - * The following defines are used to disable USB JTAG when pins 18 and pins 19 - * are set to be used as GPIO. - * See gpio_pad_select_gpio() below. - * - * TODO: Delete these definitions once the USB device registers definition is - * merged. - */ -#define USB_DEVICE_CONF0_REG (0x60043018) -#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -94,7 +85,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) */ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) { - hw->pin[gpio_num].int_type = intr_type; + hw->pin[gpio_num].pin_int_type = intr_type; } /** @@ -106,7 +97,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gp */ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) { - *status = hw->pcpu_int.intr; + *status = hw->pcpu_int.procpu_int; } /** @@ -118,7 +109,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin */ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) { - *status = 0; // Less than 32 GPIOs in ESP32-H2 + *status = 0; // Less than 32 GPIOs in ESP32-H2Beta2 } /** @@ -140,7 +131,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) */ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) { - // Not supported on C3 + // Less than 32 GPIOs in ESP32-H2Beta2. Do nothing. } /** @@ -152,11 +143,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) */ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num) { - if (core_id == 0) { - GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr - } else { - // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr - } + HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); + GPIO.pin[gpio_num].pin_int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr } /** @@ -167,7 +155,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, */ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_ena = 0; //disable GPIO intr + hw->pin[gpio_num].pin_int_ena = 0; //disable GPIO intr } /** @@ -212,7 +200,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); } @@ -223,9 +211,9 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].pad_driver = 0; + hw->pin[gpio_num].pin_pad_driver = 0; } /** @@ -236,7 +224,7 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) */ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].pad_driver = 1; + hw->pin[gpio_num].pin_pad_driver = 1; } /** @@ -269,7 +257,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32 */ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) { - return (hw->in.data >> gpio_num) & 0x1; + return (hw->in.in_data_next >> gpio_num) & 0x1; } /** @@ -277,12 +265,10 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_type = intr_type; - hw->pin[gpio_num].wakeup_enable = 0x1; + hw->pin[gpio_num].pin_wakeup_enable = 0x1; } /** @@ -293,7 +279,7 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gp */ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].wakeup_enable = 0; + hw->pin[gpio_num].pin_wakeup_enable = 0; } /** @@ -327,6 +313,7 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_ */ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } @@ -348,8 +335,8 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) */ static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num) { - if (gpio_num <= GPIO_NUM_5) { - REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); + if (gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) { + REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } else { SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } @@ -363,8 +350,8 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num) */ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num) { - if (gpio_num <= GPIO_NUM_5) { - REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); + if (gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) { + REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } @@ -391,8 +378,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign */ static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) { - if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { - CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE); + // Disable USB Serial JTAG if pin 24 or pin 25 needs to select an IOMUX function + if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(pin_name, func); } @@ -408,18 +396,26 @@ static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_ */ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) { - hw->func_out_sel_cfg[gpio_num].oen_sel = 0; - hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + hw->func_out_sel_cfg[gpio_num].func_oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].func_oen_inv_sel = oen_inv; gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } -static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); } +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ static inline void gpio_ll_force_unhold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); @@ -547,9 +543,9 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n */ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) { - if (gpio_num > GPIO_NUM_5) { - abort(); // gpio lager than 5 doesn't support. - } + HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) && + "only gpio7~12 support deep sleep wake-up function"); + REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); @@ -567,9 +563,9 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gp */ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { - if (gpio_num > GPIO_NUM_5) { - abort(); // gpio lager than 5 doesn't support. - } + HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) && + "only gpio7~12 support deep sleep wake-up function"); + CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3); } diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index 2c122cfdb5..7d8249d78e 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -205,7 +205,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { if (gpio_num < 32) { hw->enable_w1ts = (0x1 << gpio_num); @@ -220,7 +220,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->pin[gpio_num].pad_driver = 0; } @@ -286,11 +286,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_type = intr_type; hw->pin[gpio_num].wakeup_enable = 0x1; } @@ -411,12 +409,20 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } -static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); } +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ static inline void gpio_ll_force_unhold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index 6a5b7b1b85..c5e26aef50 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -210,7 +210,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { if (gpio_num < 32) { hw->enable_w1ts = (0x1 << gpio_num); @@ -225,7 +225,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ -static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) +static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->pin[gpio_num].pad_driver = 0; } @@ -291,11 +291,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type) +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - hw->pin[gpio_num].int_type = intr_type; hw->pin[gpio_num].wakeup_enable = 0x1; } @@ -419,12 +417,20 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); } -static inline void gpio_ll_force_hold_all(gpio_dev_t *hw) +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); } +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ static inline void gpio_ll_force_unhold_all(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index f31a355cbe..a532562b59 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -203,9 +203,8 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num); * * @param hal Context of the HAL layer * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. */ -#define gpio_hal_wakeup_enable(hal, gpio_num, intr_type) gpio_ll_wakeup_enable((hal)->dev, gpio_num, intr_type) +#define gpio_hal_wakeup_enable(hal, gpio_num) gpio_ll_wakeup_enable((hal)->dev, gpio_num) /** * @brief Disable GPIO wake-up function. @@ -312,17 +311,13 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num); /** * @brief Force hold digital and rtc gpio pad. * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. - * - * @param hal Context of the HAL layer - * */ -#define gpio_hal_force_hold_all(hal) gpio_ll_force_hold_all((hal)->dev) + */ +#define gpio_hal_force_hold_all() gpio_ll_force_hold_all() /** * @brief Force unhold digital and rtc gpio pad. * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. - * - * @param hal Context of the HAL layer - * */ + */ #define gpio_hal_force_unhold_all() gpio_ll_force_unhold_all() #endif diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index 67c992c483..dbc2208a07 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -19,62 +19,6 @@ typedef enum { GPIO_PORT_MAX, } gpio_port_t; -#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ -#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ -#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */ -#define GPIO_SEL_3 (BIT(3)) /*!< Pin 3 selected */ -#define GPIO_SEL_4 (BIT(4)) /*!< Pin 4 selected */ -#define GPIO_SEL_5 (BIT(5)) /*!< Pin 5 selected */ -#define GPIO_SEL_6 (BIT(6)) /*!< Pin 6 selected */ -#define GPIO_SEL_7 (BIT(7)) /*!< Pin 7 selected */ -#define GPIO_SEL_8 (BIT(8)) /*!< Pin 8 selected */ -#define GPIO_SEL_9 (BIT(9)) /*!< Pin 9 selected */ -#define GPIO_SEL_10 (BIT(10)) /*!< Pin 10 selected */ -#define GPIO_SEL_11 (BIT(11)) /*!< Pin 11 selected */ -#define GPIO_SEL_12 (BIT(12)) /*!< Pin 12 selected */ -#define GPIO_SEL_13 (BIT(13)) /*!< Pin 13 selected */ -#define GPIO_SEL_14 (BIT(14)) /*!< Pin 14 selected */ -#define GPIO_SEL_15 (BIT(15)) /*!< Pin 15 selected */ -#define GPIO_SEL_16 (BIT(16)) /*!< Pin 16 selected */ -#define GPIO_SEL_17 (BIT(17)) /*!< Pin 17 selected */ -#define GPIO_SEL_18 (BIT(18)) /*!< Pin 18 selected */ -#define GPIO_SEL_19 (BIT(19)) /*!< Pin 19 selected */ -#define GPIO_SEL_20 (BIT(20)) /*!< Pin 20 selected */ -#define GPIO_SEL_21 (BIT(21)) /*!< Pin 21 selected */ -#if CONFIG_IDF_TARGET_ESP32 -#define GPIO_SEL_22 (BIT(22)) /*!< Pin 22 selected */ -#define GPIO_SEL_23 (BIT(23)) /*!< Pin 23 selected */ - -#define GPIO_SEL_25 (BIT(25)) /*!< Pin 25 selected */ -#endif -#define GPIO_SEL_26 (BIT(26)) /*!< Pin 26 selected */ -#define GPIO_SEL_27 (BIT(27)) /*!< Pin 27 selected */ -#define GPIO_SEL_28 (BIT(28)) /*!< Pin 28 selected */ -#define GPIO_SEL_29 (BIT(29)) /*!< Pin 29 selected */ -#define GPIO_SEL_30 (BIT(30)) /*!< Pin 30 selected */ -#define GPIO_SEL_31 (BIT(31)) /*!< Pin 31 selected */ -#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /*!< Pin 32 selected */ -#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /*!< Pin 33 selected */ -#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /*!< Pin 34 selected */ -#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /*!< Pin 35 selected */ -#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /*!< Pin 36 selected */ -#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /*!< Pin 37 selected */ -#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */ -#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */ -#if SOC_GPIO_PIN_COUNT > 40 -#define GPIO_SEL_40 ((uint64_t)(((uint64_t)1)<<40)) /*!< Pin 40 selected */ -#define GPIO_SEL_41 ((uint64_t)(((uint64_t)1)<<41)) /*!< Pin 41 selected */ -#define GPIO_SEL_42 ((uint64_t)(((uint64_t)1)<<42)) /*!< Pin 42 selected */ -#define GPIO_SEL_43 ((uint64_t)(((uint64_t)1)<<43)) /*!< Pin 43 selected */ -#define GPIO_SEL_44 ((uint64_t)(((uint64_t)1)<<44)) /*!< Pin 44 selected */ -#define GPIO_SEL_45 ((uint64_t)(((uint64_t)1)<<45)) /*!< Pin 45 selected */ -#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */ -#if CONFIG_IDF_TARGET_ESP32S3 -#define GPIO_SEL_47 ((uint64_t)(((uint64_t)1)<<47)) /*!< Pin 47 selected */ -#define GPIO_SEL_48 ((uint64_t)(((uint64_t)1)<<48)) /*!< Pin 48 selected */ -#endif -#endif - #define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG #define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG #define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG @@ -298,7 +242,7 @@ typedef enum { GPIO_NUM_MAX, /** @endcond */ } gpio_num_t; -#elif CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 typedef enum { GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ @@ -324,6 +268,9 @@ typedef enum { GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ @@ -342,6 +289,38 @@ typedef enum { GPIO_NUM_MAX, /** @endcond */ } gpio_num_t; +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_MAX, +/** @endcond */ +} gpio_num_t; #elif CONFIG_IDF_TARGET_ESP32C2 typedef enum { GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ diff --git a/components/soc/esp32h2/gpio_periph.c b/components/soc/esp32h2/gpio_periph.c index 475f279b1c..02df23128c 100644 --- a/components/soc/esp32h2/gpio_periph.c +++ b/components/soc/esp32h2/gpio_periph.c @@ -6,7 +6,6 @@ #include "soc/gpio_periph.h" -// ESP32H2-TODO: IDF-3439 const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { IO_MUX_GPIO0_REG, IO_MUX_GPIO1_REG, @@ -30,29 +29,98 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { IO_MUX_GPIO19_REG, IO_MUX_GPIO20_REG, IO_MUX_GPIO21_REG, + IO_MUX_GPIO22_REG, + IO_MUX_GPIO23_REG, + IO_MUX_GPIO24_REG, + IO_MUX_GPIO25_REG, +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG, + IO_MUX_GPIO28_REG, + IO_MUX_GPIO29_REG, + IO_MUX_GPIO30_REG, + IO_MUX_GPIO31_REG, + IO_MUX_GPIO32_REG, + IO_MUX_GPIO33_REG, + IO_MUX_GPIO34_REG, + IO_MUX_GPIO35_REG, + IO_MUX_GPIO36_REG, + IO_MUX_GPIO37_REG, + IO_MUX_GPIO38_REG, + IO_MUX_GPIO39_REG, + IO_MUX_GPIO40_REG, +#endif }; const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { - BIT(0), //GPIO0 - BIT(1), //GPIO1 - BIT(2), //GPIO2 - BIT(3), //GPIO3 - BIT(4), //GPIO4 - BIT(5), //GPIO5 - BIT(5), //GPIO6 - BIT(6), //GPIO7 - BIT(3), //GPIO8 - BIT(4), //GPIO9 - BIT(0), //GPIO10 - BIT(15), //GPIO11 - BIT(10), //GPIO12 - BIT(12), //GPIO13 - BIT(8), //GPIO14 - BIT(7), //GPIO15 - BIT(9), //GPIO16 - BIT(11), //GPIO17 - BIT(1), //GPIO18 - BIT(2), //GPIO19 - BIT(13), //GPIO20 - BIT(14), //GPIO21 +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 + BIT(0), //GPIO0 + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(7), //GPIO7 + BIT(8), //GPIO8 + BIT(9), //GPIO9 + BIT(10), //GPIO10 + BIT(11), //GPIO11 + BIT(12), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(16), //GPIO16 + BIT(17), //GPIO17 + BIT(18), //GPIO18 + BIT(19), //GPIO19 + BIT(20), //GPIO20 + BIT(21), //GPIO21 + BIT(22), //GPIO22 + BIT(23), //GPIO23 + BIT(24), //GPIO24 + BIT(25), //GPIO25 + BIT(26), //GPIO26 + BIT(27), //GPIO27 + BIT(28), //GPIO28 + BIT(29), //GPIO29 + BIT(30), //GPIO30 + BIT(31), //GPIO31 + BIT(0), //GPIO32 + BIT(1), //GPIO33 + BIT(2), //GPIO34 + BIT(3), //GPIO35 + BIT(4), //GPIO36 + BIT(5), //GPIO37 + BIT(6), //GPIO38 + BIT(7), //GPIO39 + BIT(8), //GPIO40 +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 + BIT(0), //GPIO0 + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(0), //GPIO7 + BIT(1), //GPIO8 + BIT(2), //GPIO9 + BIT(4), //GPIO10 + BIT(3), //GPIO11 + BIT(5), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(16), //GPIO16 + BIT(17), //GPIO17 + BIT(18), //GPIO18 + BIT(19), //GPIO19 + BIT(20), //GPIO20 + BIT(21), //GPIO21 + BIT(22), //GPIO22 + BIT(23), //GPIO23 + BIT(24), //GPIO24 + BIT(25), //GPIO25 +#endif }; diff --git a/components/soc/esp32h2/include/rev1/soc/gpio_reg.h b/components/soc/esp32h2/include/rev1/soc/gpio_reg.h index f7aa79dd4f..d5d7b74f61 100644 --- a/components/soc/esp32h2/include/rev1/soc/gpio_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/gpio_reg.h @@ -39,5984 +39,8135 @@ extern "C" { #define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) #define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) -#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) -/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_BT_SEL 0xFFFFFFFF -#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) -#define GPIO_BT_SEL_V 0xFFFFFFFF +/** GPIO_BT_SELECT_REG register + * GPIO bit select register + */ +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ +#define GPIO_BT_SEL 0xFFFFFFFFU +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFFU #define GPIO_BT_SEL_S 0 -#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_OUT_DATA 0xFFFFFFFF -#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) -#define GPIO_OUT_DATA_V 0xFFFFFFFF -#define GPIO_OUT_DATA_S 0 +/** GPIO_OUT_REG register + * GPIO output register for GPIO0-31 + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/WS/WC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 + */ +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 -#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/* GPIO_OUT_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_OUT_W1TS 0xFFFFFFFF -#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) -#define GPIO_OUT_W1TS_V 0xFFFFFFFF +/** GPIO_OUT_W1TS_REG register + * GPIO output set register for GPIO0-31 + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 + */ +#define GPIO_OUT_W1TS 0xFFFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0xFFFFFFFFU #define GPIO_OUT_W1TS_S 0 -#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xC) -/* GPIO_OUT_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_OUT_W1TC 0xFFFFFFFF -#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) -#define GPIO_OUT_W1TC_V 0xFFFFFFFF +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register for GPIO0-31 + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 + */ +#define GPIO_OUT_W1TC 0xFFFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0xFFFFFFFFU #define GPIO_OUT_W1TC_S 0 -#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) -/* GPIO_OUT1_DATA : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_OUT1_DATA 0x00001FFF -#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) -#define GPIO_OUT1_DATA_V 0x1FFF -#define GPIO_OUT1_DATA_S 0 +/** GPIO_OUT1_REG register + * GPIO output register for GPIO32-44 + */ +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) +/** GPIO_OUT1_DATA_ORIG : R/W/WS/WC; bitpos: [12:0]; default: 0; + * GPIO output register for GPIO32-44 + */ +#define GPIO_OUT1_DATA_ORIG 0x00001FFFU +#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) +#define GPIO_OUT1_DATA_ORIG_V 0x00001FFFU +#define GPIO_OUT1_DATA_ORIG_S 0 -#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) -/* GPIO_OUT1_W1TS : WO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_OUT1_W1TS 0x00001FFF -#define GPIO_OUT1_W1TS_M ((GPIO_OUT1_W1TS_V)<<(GPIO_OUT1_W1TS_S)) -#define GPIO_OUT1_W1TS_V 0x1FFF +/** GPIO_OUT1_W1TS_REG register + * GPIO output set register for GPIO32-44 + */ +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) +/** GPIO_OUT1_W1TS : WT; bitpos: [12:0]; default: 0; + * GPIO output set register for GPIO32-44 + */ +#define GPIO_OUT1_W1TS 0x00001FFFU +#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) +#define GPIO_OUT1_W1TS_V 0x00001FFFU #define GPIO_OUT1_W1TS_S 0 -#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) -/* GPIO_OUT1_W1TC : WO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_OUT1_W1TC 0x00001FFF -#define GPIO_OUT1_W1TC_M ((GPIO_OUT1_W1TC_V)<<(GPIO_OUT1_W1TC_S)) -#define GPIO_OUT1_W1TC_V 0x1FFF +/** GPIO_OUT1_W1TC_REG register + * GPIO output clear register for GPIO32-44 + */ +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) +/** GPIO_OUT1_W1TC : WT; bitpos: [12:0]; default: 0; + * GPIO output clear register for GPIO32-44 + */ +#define GPIO_OUT1_W1TC 0x00001FFFU +#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) +#define GPIO_OUT1_W1TC_V 0x00001FFFU #define GPIO_OUT1_W1TC_S 0 -#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1C) -/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SDIO_SEL 0x000000FF -#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) -#define GPIO_SDIO_SEL_V 0xFF +/** GPIO_SDIO_SELECT_REG register + * GPIO sdio select register + */ +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) +/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ +#define GPIO_SDIO_SEL 0x000000FFU +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FFU #define GPIO_SDIO_SEL_S 0 -#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) -/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_ENABLE_DATA 0xFFFFFFFF -#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) -#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +/** GPIO_ENABLE_REG register + * GPIO output enable register for GPIO0-31 + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/** GPIO_ENABLE_DATA : R/W/SS; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ +#define GPIO_ENABLE_DATA 0xFFFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFFU #define GPIO_ENABLE_DATA_S 0 -#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) -/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_ENABLE_W1TS 0xFFFFFFFF -#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) -#define GPIO_ENABLE_W1TS_V 0xFFFFFFFF +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TS 0xFFFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU #define GPIO_ENABLE_W1TS_S 0 -#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) -/* GPIO_ENABLE_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_ENABLE_W1TC 0xFFFFFFFF -#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) -#define GPIO_ENABLE_W1TC_V 0xFFFFFFFF +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TC 0xFFFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU #define GPIO_ENABLE_W1TC_S 0 -#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2C) -/* GPIO_ENABLE1_DATA : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_ENABLE1_DATA 0x00001FFF -#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) -#define GPIO_ENABLE1_DATA_V 0x1FFF +/** GPIO_ENABLE1_REG register + * GPIO output enable register for GPIO32-44 + */ +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c) +/** GPIO_ENABLE1_DATA : R/W/SS; bitpos: [12:0]; default: 0; + * GPIO output enable register for GPIO32-44 + */ +#define GPIO_ENABLE1_DATA 0x00001FFFU +#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) +#define GPIO_ENABLE1_DATA_V 0x00001FFFU #define GPIO_ENABLE1_DATA_S 0 -#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) -/* GPIO_ENABLE1_W1TS : WO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_ENABLE1_W1TS 0x00001FFF -#define GPIO_ENABLE1_W1TS_M ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S)) -#define GPIO_ENABLE1_W1TS_V 0x1FFF +/** GPIO_ENABLE1_W1TS_REG register + * GPIO output enable set register for GPIO32-44 + */ +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) +/** GPIO_ENABLE1_W1TS : WT; bitpos: [12:0]; default: 0; + * GPIO output enable set register for GPIO32-44 + */ +#define GPIO_ENABLE1_W1TS 0x00001FFFU +#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) +#define GPIO_ENABLE1_W1TS_V 0x00001FFFU #define GPIO_ENABLE1_W1TS_S 0 -#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) -/* GPIO_ENABLE1_W1TC : WO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_ENABLE1_W1TC 0x00001FFF -#define GPIO_ENABLE1_W1TC_M ((GPIO_ENABLE1_W1TC_V)<<(GPIO_ENABLE1_W1TC_S)) -#define GPIO_ENABLE1_W1TC_V 0x1FFF +/** GPIO_ENABLE1_W1TC_REG register + * GPIO output enable clear register for GPIO32-44 + */ +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) +/** GPIO_ENABLE1_W1TC : WT; bitpos: [12:0]; default: 0; + * GPIO output enable clear register for GPIO32-44 + */ +#define GPIO_ENABLE1_W1TC 0x00001FFFU +#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) +#define GPIO_ENABLE1_W1TC_V 0x00001FFFU #define GPIO_ENABLE1_W1TC_S 0 -#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) -/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ -/*description: */ -#define GPIO_STRAPPING 0x0000FFFF -#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) -#define GPIO_STRAPPING_V 0xFFFF +/** GPIO_STRAP_REG register + * pad strapping register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU #define GPIO_STRAPPING_S 0 -#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3C) -/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ -/*description: */ -#define GPIO_IN_DATA 0xFFFFFFFF -#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) -#define GPIO_IN_DATA_V 0xFFFFFFFF -#define GPIO_IN_DATA_S 0 +/** GPIO_IN_REG register + * GPIO input register for GPIO0-31 + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ +#define GPIO_IN_DATA_NEXT 0xFFFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 -#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) -/* GPIO_IN1_DATA : RO ;bitpos:[12:0] ;default: ; */ -/*description: */ -#define GPIO_IN1_DATA 0x00001FFF -#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) -#define GPIO_IN1_DATA_V 0x1FFF -#define GPIO_IN1_DATA_S 0 +/** GPIO_IN1_REG register + * GPIO input register for GPIO32-44 + */ +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) +/** GPIO_IN1_DATA_NEXT : RO; bitpos: [12:0]; default: 0; + * GPIO input register for GPIO32-44 + */ +#define GPIO_IN1_DATA_NEXT 0x00001FFFU +#define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) +#define GPIO_IN1_DATA_NEXT_V 0x00001FFFU +#define GPIO_IN1_DATA_NEXT_S 0 -#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) -/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_STATUS_INT 0xFFFFFFFF -#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) -#define GPIO_STATUS_INT_V 0xFFFFFFFF -#define GPIO_STATUS_INT_S 0 +/** GPIO_STATUS_REG register + * GPIO interrupt status register for GPIO0-31 + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_STATUS_INTERRUPT : R/W/SS; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 -#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) -/* GPIO_STATUS_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_STATUS_W1TS 0xFFFFFFFF -#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) -#define GPIO_STATUS_W1TS_V 0xFFFFFFFF +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register for GPIO0-31 + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 + */ +#define GPIO_STATUS_W1TS 0xFFFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0xFFFFFFFFU #define GPIO_STATUS_W1TS_S 0 -#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4C) -/* GPIO_STATUS_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_STATUS_W1TC 0xFFFFFFFF -#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) -#define GPIO_STATUS_W1TC_V 0xFFFFFFFF +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register for GPIO0-31 + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) +/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 + */ +#define GPIO_STATUS_W1TC 0xFFFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0xFFFFFFFFU #define GPIO_STATUS_W1TC_S 0 -#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) -/* GPIO_STATUS1_INT : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_STATUS1_INT 0x00001FFF -#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) -#define GPIO_STATUS1_INT_V 0x1FFF -#define GPIO_STATUS1_INT_S 0 +/** GPIO_STATUS1_REG register + * GPIO interrupt status register for GPIO32-44 + */ +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) +/** GPIO_STATUS1_INTERRUPT : R/W/SS; bitpos: [12:0]; default: 0; + * GPIO interrupt status register for GPIO32-44 + */ +#define GPIO_STATUS1_INTERRUPT 0x00001FFFU +#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) +#define GPIO_STATUS1_INTERRUPT_V 0x00001FFFU +#define GPIO_STATUS1_INTERRUPT_S 0 -#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) -/* GPIO_STATUS1_W1TS : WO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_STATUS1_W1TS 0x00001FFF -#define GPIO_STATUS1_W1TS_M ((GPIO_STATUS1_W1TS_V)<<(GPIO_STATUS1_W1TS_S)) -#define GPIO_STATUS1_W1TS_V 0x1FFF +/** GPIO_STATUS1_W1TS_REG register + * GPIO interrupt status set register for GPIO32-44 + */ +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) +/** GPIO_STATUS1_W1TS : WT; bitpos: [12:0]; default: 0; + * GPIO interrupt status set register for GPIO32-44 + */ +#define GPIO_STATUS1_W1TS 0x00001FFFU +#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) +#define GPIO_STATUS1_W1TS_V 0x00001FFFU #define GPIO_STATUS1_W1TS_S 0 -#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) -/* GPIO_STATUS1_W1TC : WO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_STATUS1_W1TC 0x00001FFF -#define GPIO_STATUS1_W1TC_M ((GPIO_STATUS1_W1TC_V)<<(GPIO_STATUS1_W1TC_S)) -#define GPIO_STATUS1_W1TC_V 0x1FFF +/** GPIO_STATUS1_W1TC_REG register + * GPIO interrupt status clear register for GPIO32-44 + */ +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) +/** GPIO_STATUS1_W1TC : WT; bitpos: [12:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-44 + */ +#define GPIO_STATUS1_W1TC 0x00001FFFU +#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) +#define GPIO_STATUS1_W1TC_V 0x00001FFFU #define GPIO_STATUS1_W1TC_S 0 -#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) -/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_PROCPU_INT 0xFFFFFFFF -#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) -#define GPIO_PROCPU_INT_V 0xFFFFFFFF +/** GPIO_PCPU_INT_REG register + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) +/** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +#define GPIO_PROCPU_INT 0xFFFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0xFFFFFFFFU #define GPIO_PROCPU_INT_S 0 -#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) -/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF -#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) -#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +/** GPIO_PCPU_NMI_INT_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/** GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFFU +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFFU #define GPIO_PROCPU_NMI_INT_S 0 -#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) -/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_SDIO_INT 0xFFFFFFFF -#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) -#define GPIO_SDIO_INT_V 0xFFFFFFFF +/** GPIO_CPUSDIO_INT_REG register + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT 0xFFFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFFU #define GPIO_SDIO_INT_S 0 -#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) -/* GPIO_PROCPU_INT_H : RO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_PROCPU_INT_H 0x00001FFF -#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) -#define GPIO_PROCPU_INT_H_V 0x1FFF -#define GPIO_PROCPU_INT_H_S 0 +/** GPIO_PCPU_INT1_REG register + * GPIO PRO_CPU interrupt status register for GPIO32-44 + */ +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) +/** GPIO_PROCPU_INT1 : RO; bitpos: [12:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO32-44 + */ +#define GPIO_PROCPU_INT1 0x00001FFFU +#define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) +#define GPIO_PROCPU_INT1_V 0x00001FFFU +#define GPIO_PROCPU_INT1_S 0 -#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6C) -/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_PROCPU_NMI_INT_H 0x00001FFF -#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) -#define GPIO_PROCPU_NMI_INT_H_V 0x1FFF -#define GPIO_PROCPU_NMI_INT_H_S 0 +/** GPIO_PCPU_NMI_INT1_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 + */ +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6c) +/** GPIO_PROCPU_NMI_INT1 : RO; bitpos: [12:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 + */ +#define GPIO_PROCPU_NMI_INT1 0x00001FFFU +#define GPIO_PROCPU_NMI_INT1_M (GPIO_PROCPU_NMI_INT1_V << GPIO_PROCPU_NMI_INT1_S) +#define GPIO_PROCPU_NMI_INT1_V 0x00001FFFU +#define GPIO_PROCPU_NMI_INT1_S 0 -#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) -/* GPIO_SDIO_INT_H : RO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_SDIO_INT_H 0x00001FFF -#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) -#define GPIO_SDIO_INT_H_V 0x1FFF -#define GPIO_SDIO_INT_H_S 0 +/** GPIO_CPUSDIO_INT1_REG register + * GPIO CPUSDIO interrupt status register for GPIO32-44 + */ +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) +/** GPIO_SDIO_INT1 : RO; bitpos: [12:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO32-44 + */ +#define GPIO_SDIO_INT1 0x00001FFFU +#define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) +#define GPIO_SDIO_INT1_V 0x00001FFFU +#define GPIO_SDIO_INT1_S 0 -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) -/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN0_INT_ENA 0x0000001F -#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) -#define GPIO_PIN0_INT_ENA_V 0x1F -#define GPIO_PIN0_INT_ENA_S 13 -/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN0_CONFIG 0x00000003 -#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) -#define GPIO_PIN0_CONFIG_V 0x3 -#define GPIO_PIN0_CONFIG_S 11 -/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN0_WAKEUP_ENABLE_S 10 -/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN0_INT_TYPE 0x00000007 -#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) -#define GPIO_PIN0_INT_TYPE_V 0x7 -#define GPIO_PIN0_INT_TYPE_S 7 -/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) -#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN0_SYNC1_BYPASS_S 3 -/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_V 0x1 -#define GPIO_PIN0_PAD_DRIVER_S 2 -/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) -#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN0_CONFIG 0x00000003U +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003U +#define GPIO_PIN0_CONFIG_S 11 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) -/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN1_INT_ENA 0x0000001F -#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) -#define GPIO_PIN1_INT_ENA_V 0x1F -#define GPIO_PIN1_INT_ENA_S 13 -/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN1_CONFIG 0x00000003 -#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) -#define GPIO_PIN1_CONFIG_V 0x3 -#define GPIO_PIN1_CONFIG_S 11 -/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN1_WAKEUP_ENABLE_S 10 -/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN1_INT_TYPE 0x00000007 -#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) -#define GPIO_PIN1_INT_TYPE_V 0x7 -#define GPIO_PIN1_INT_TYPE_S 7 -/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) -#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN1_SYNC1_BYPASS_S 3 -/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_V 0x1 -#define GPIO_PIN1_PAD_DRIVER_S 2 -/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) -#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN1_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN1_CONFIG 0x00000003U +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003U +#define GPIO_PIN1_CONFIG_S 11 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7C) -/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN2_INT_ENA 0x0000001F -#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) -#define GPIO_PIN2_INT_ENA_V 0x1F -#define GPIO_PIN2_INT_ENA_S 13 -/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN2_CONFIG 0x00000003 -#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) -#define GPIO_PIN2_CONFIG_V 0x3 -#define GPIO_PIN2_CONFIG_S 11 -/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN2_WAKEUP_ENABLE_S 10 -/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN2_INT_TYPE 0x00000007 -#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) -#define GPIO_PIN2_INT_TYPE_V 0x7 -#define GPIO_PIN2_INT_TYPE_S 7 -/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) -#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN2_SYNC1_BYPASS_S 3 -/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_V 0x1 -#define GPIO_PIN2_PAD_DRIVER_S 2 -/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) -#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN2_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN2_CONFIG 0x00000003U +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003U +#define GPIO_PIN2_CONFIG_S 11 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) -/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN3_INT_ENA 0x0000001F -#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) -#define GPIO_PIN3_INT_ENA_V 0x1F -#define GPIO_PIN3_INT_ENA_S 13 -/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN3_CONFIG 0x00000003 -#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) -#define GPIO_PIN3_CONFIG_V 0x3 -#define GPIO_PIN3_CONFIG_S 11 -/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN3_WAKEUP_ENABLE_S 10 -/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN3_INT_TYPE 0x00000007 -#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) -#define GPIO_PIN3_INT_TYPE_V 0x7 -#define GPIO_PIN3_INT_TYPE_S 7 -/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) -#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN3_SYNC1_BYPASS_S 3 -/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_V 0x1 -#define GPIO_PIN3_PAD_DRIVER_S 2 -/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) -#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN3_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN3_CONFIG 0x00000003U +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003U +#define GPIO_PIN3_CONFIG_S 11 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) -/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN4_INT_ENA 0x0000001F -#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) -#define GPIO_PIN4_INT_ENA_V 0x1F -#define GPIO_PIN4_INT_ENA_S 13 -/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN4_CONFIG 0x00000003 -#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) -#define GPIO_PIN4_CONFIG_V 0x3 -#define GPIO_PIN4_CONFIG_S 11 -/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN4_WAKEUP_ENABLE_S 10 -/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN4_INT_TYPE 0x00000007 -#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) -#define GPIO_PIN4_INT_TYPE_V 0x7 -#define GPIO_PIN4_INT_TYPE_S 7 -/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) -#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN4_SYNC1_BYPASS_S 3 -/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_V 0x1 -#define GPIO_PIN4_PAD_DRIVER_S 2 -/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) -#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN4_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN4_CONFIG 0x00000003U +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003U +#define GPIO_PIN4_CONFIG_S 11 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) -/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN5_INT_ENA 0x0000001F -#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) -#define GPIO_PIN5_INT_ENA_V 0x1F -#define GPIO_PIN5_INT_ENA_S 13 -/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN5_CONFIG 0x00000003 -#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) -#define GPIO_PIN5_CONFIG_V 0x3 -#define GPIO_PIN5_CONFIG_S 11 -/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN5_WAKEUP_ENABLE_S 10 -/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN5_INT_TYPE 0x00000007 -#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) -#define GPIO_PIN5_INT_TYPE_V 0x7 -#define GPIO_PIN5_INT_TYPE_S 7 -/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) -#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN5_SYNC1_BYPASS_S 3 -/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_V 0x1 -#define GPIO_PIN5_PAD_DRIVER_S 2 -/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) -#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN5_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN5_CONFIG 0x00000003U +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003U +#define GPIO_PIN5_CONFIG_S 11 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8C) -/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN6_INT_ENA 0x0000001F -#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) -#define GPIO_PIN6_INT_ENA_V 0x1F -#define GPIO_PIN6_INT_ENA_S 13 -/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN6_CONFIG 0x00000003 -#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) -#define GPIO_PIN6_CONFIG_V 0x3 -#define GPIO_PIN6_CONFIG_S 11 -/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN6_WAKEUP_ENABLE_S 10 -/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN6_INT_TYPE 0x00000007 -#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) -#define GPIO_PIN6_INT_TYPE_V 0x7 -#define GPIO_PIN6_INT_TYPE_S 7 -/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) -#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN6_SYNC1_BYPASS_S 3 -/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_V 0x1 -#define GPIO_PIN6_PAD_DRIVER_S 2 -/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) -#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN6_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN6_CONFIG 0x00000003U +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003U +#define GPIO_PIN6_CONFIG_S 11 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) -/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN7_INT_ENA 0x0000001F -#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) -#define GPIO_PIN7_INT_ENA_V 0x1F -#define GPIO_PIN7_INT_ENA_S 13 -/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN7_CONFIG 0x00000003 -#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) -#define GPIO_PIN7_CONFIG_V 0x3 -#define GPIO_PIN7_CONFIG_S 11 -/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN7_WAKEUP_ENABLE_S 10 -/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN7_INT_TYPE 0x00000007 -#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) -#define GPIO_PIN7_INT_TYPE_V 0x7 -#define GPIO_PIN7_INT_TYPE_S 7 -/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) -#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN7_SYNC1_BYPASS_S 3 -/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_V 0x1 -#define GPIO_PIN7_PAD_DRIVER_S 2 -/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) -#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN7_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN7_CONFIG 0x00000003U +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003U +#define GPIO_PIN7_CONFIG_S 11 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) -/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN8_INT_ENA 0x0000001F -#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) -#define GPIO_PIN8_INT_ENA_V 0x1F -#define GPIO_PIN8_INT_ENA_S 13 -/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN8_CONFIG 0x00000003 -#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) -#define GPIO_PIN8_CONFIG_V 0x3 -#define GPIO_PIN8_CONFIG_S 11 -/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN8_WAKEUP_ENABLE_S 10 -/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN8_INT_TYPE 0x00000007 -#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) -#define GPIO_PIN8_INT_TYPE_V 0x7 -#define GPIO_PIN8_INT_TYPE_S 7 -/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) -#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN8_SYNC1_BYPASS_S 3 -/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_V 0x1 -#define GPIO_PIN8_PAD_DRIVER_S 2 -/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) -#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN8_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN8_CONFIG 0x00000003U +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003U +#define GPIO_PIN8_CONFIG_S 11 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) -/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN9_INT_ENA 0x0000001F -#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) -#define GPIO_PIN9_INT_ENA_V 0x1F -#define GPIO_PIN9_INT_ENA_S 13 -/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN9_CONFIG 0x00000003 -#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) -#define GPIO_PIN9_CONFIG_V 0x3 -#define GPIO_PIN9_CONFIG_S 11 -/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN9_WAKEUP_ENABLE_S 10 -/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN9_INT_TYPE 0x00000007 -#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) -#define GPIO_PIN9_INT_TYPE_V 0x7 -#define GPIO_PIN9_INT_TYPE_S 7 -/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) -#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN9_SYNC1_BYPASS_S 3 -/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_V 0x1 -#define GPIO_PIN9_PAD_DRIVER_S 2 -/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) -#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN9_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN9_CONFIG 0x00000003U +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003U +#define GPIO_PIN9_CONFIG_S 11 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9C) -/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN10_INT_ENA 0x0000001F -#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) -#define GPIO_PIN10_INT_ENA_V 0x1F -#define GPIO_PIN10_INT_ENA_S 13 -/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN10_CONFIG 0x00000003 -#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) -#define GPIO_PIN10_CONFIG_V 0x3 -#define GPIO_PIN10_CONFIG_S 11 -/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN10_WAKEUP_ENABLE_S 10 -/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN10_INT_TYPE 0x00000007 -#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) -#define GPIO_PIN10_INT_TYPE_V 0x7 -#define GPIO_PIN10_INT_TYPE_S 7 -/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) -#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN10_SYNC1_BYPASS_S 3 -/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_V 0x1 -#define GPIO_PIN10_PAD_DRIVER_S 2 -/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) -#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN10_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN10_CONFIG 0x00000003U +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003U +#define GPIO_PIN10_CONFIG_S 11 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xA0) -/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN11_INT_ENA 0x0000001F -#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) -#define GPIO_PIN11_INT_ENA_V 0x1F -#define GPIO_PIN11_INT_ENA_S 13 -/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN11_CONFIG 0x00000003 -#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) -#define GPIO_PIN11_CONFIG_V 0x3 -#define GPIO_PIN11_CONFIG_S 11 -/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN11_WAKEUP_ENABLE_S 10 -/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN11_INT_TYPE 0x00000007 -#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) -#define GPIO_PIN11_INT_TYPE_V 0x7 -#define GPIO_PIN11_INT_TYPE_S 7 -/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) -#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN11_SYNC1_BYPASS_S 3 -/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_V 0x1 -#define GPIO_PIN11_PAD_DRIVER_S 2 -/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) -#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN11_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN11_CONFIG 0x00000003U +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003U +#define GPIO_PIN11_CONFIG_S 11 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xA4) -/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN12_INT_ENA 0x0000001F -#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) -#define GPIO_PIN12_INT_ENA_V 0x1F -#define GPIO_PIN12_INT_ENA_S 13 -/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN12_CONFIG 0x00000003 -#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) -#define GPIO_PIN12_CONFIG_V 0x3 -#define GPIO_PIN12_CONFIG_S 11 -/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN12_WAKEUP_ENABLE_S 10 -/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN12_INT_TYPE 0x00000007 -#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) -#define GPIO_PIN12_INT_TYPE_V 0x7 -#define GPIO_PIN12_INT_TYPE_S 7 -/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) -#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN12_SYNC1_BYPASS_S 3 -/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_V 0x1 -#define GPIO_PIN12_PAD_DRIVER_S 2 -/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) -#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN12_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN12_CONFIG 0x00000003U +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003U +#define GPIO_PIN12_CONFIG_S 11 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xA8) -/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN13_INT_ENA 0x0000001F -#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) -#define GPIO_PIN13_INT_ENA_V 0x1F -#define GPIO_PIN13_INT_ENA_S 13 -/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN13_CONFIG 0x00000003 -#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) -#define GPIO_PIN13_CONFIG_V 0x3 -#define GPIO_PIN13_CONFIG_S 11 -/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN13_WAKEUP_ENABLE_S 10 -/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN13_INT_TYPE 0x00000007 -#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) -#define GPIO_PIN13_INT_TYPE_V 0x7 -#define GPIO_PIN13_INT_TYPE_S 7 -/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) -#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN13_SYNC1_BYPASS_S 3 -/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_V 0x1 -#define GPIO_PIN13_PAD_DRIVER_S 2 -/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) -#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN13_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN13_CONFIG 0x00000003U +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003U +#define GPIO_PIN13_CONFIG_S 11 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xAC) -/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN14_INT_ENA 0x0000001F -#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) -#define GPIO_PIN14_INT_ENA_V 0x1F -#define GPIO_PIN14_INT_ENA_S 13 -/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN14_CONFIG 0x00000003 -#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) -#define GPIO_PIN14_CONFIG_V 0x3 -#define GPIO_PIN14_CONFIG_S 11 -/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN14_WAKEUP_ENABLE_S 10 -/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN14_INT_TYPE 0x00000007 -#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) -#define GPIO_PIN14_INT_TYPE_V 0x7 -#define GPIO_PIN14_INT_TYPE_S 7 -/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) -#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN14_SYNC1_BYPASS_S 3 -/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_V 0x1 -#define GPIO_PIN14_PAD_DRIVER_S 2 -/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) -#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN14_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN14_CONFIG 0x00000003U +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003U +#define GPIO_PIN14_CONFIG_S 11 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xB0) -/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN15_INT_ENA 0x0000001F -#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) -#define GPIO_PIN15_INT_ENA_V 0x1F -#define GPIO_PIN15_INT_ENA_S 13 -/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN15_CONFIG 0x00000003 -#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) -#define GPIO_PIN15_CONFIG_V 0x3 -#define GPIO_PIN15_CONFIG_S 11 -/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN15_WAKEUP_ENABLE_S 10 -/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN15_INT_TYPE 0x00000007 -#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) -#define GPIO_PIN15_INT_TYPE_V 0x7 -#define GPIO_PIN15_INT_TYPE_S 7 -/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) -#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN15_SYNC1_BYPASS_S 3 -/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_V 0x1 -#define GPIO_PIN15_PAD_DRIVER_S 2 -/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) -#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN15_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN15_CONFIG 0x00000003U +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003U +#define GPIO_PIN15_CONFIG_S 11 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xB4) -/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN16_INT_ENA 0x0000001F -#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) -#define GPIO_PIN16_INT_ENA_V 0x1F -#define GPIO_PIN16_INT_ENA_S 13 -/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN16_CONFIG 0x00000003 -#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) -#define GPIO_PIN16_CONFIG_V 0x3 -#define GPIO_PIN16_CONFIG_S 11 -/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN16_WAKEUP_ENABLE_S 10 -/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN16_INT_TYPE 0x00000007 -#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) -#define GPIO_PIN16_INT_TYPE_V 0x7 -#define GPIO_PIN16_INT_TYPE_S 7 -/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) -#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN16_SYNC1_BYPASS_S 3 -/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_V 0x1 -#define GPIO_PIN16_PAD_DRIVER_S 2 -/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) -#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN16_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN16_CONFIG 0x00000003U +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003U +#define GPIO_PIN16_CONFIG_S 11 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xB8) -/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN17_INT_ENA 0x0000001F -#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) -#define GPIO_PIN17_INT_ENA_V 0x1F -#define GPIO_PIN17_INT_ENA_S 13 -/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN17_CONFIG 0x00000003 -#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) -#define GPIO_PIN17_CONFIG_V 0x3 -#define GPIO_PIN17_CONFIG_S 11 -/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN17_WAKEUP_ENABLE_S 10 -/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN17_INT_TYPE 0x00000007 -#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) -#define GPIO_PIN17_INT_TYPE_V 0x7 -#define GPIO_PIN17_INT_TYPE_S 7 -/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) -#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN17_SYNC1_BYPASS_S 3 -/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_V 0x1 -#define GPIO_PIN17_PAD_DRIVER_S 2 -/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) -#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN17_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN17_CONFIG 0x00000003U +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003U +#define GPIO_PIN17_CONFIG_S 11 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xBC) -/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN18_INT_ENA 0x0000001F -#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) -#define GPIO_PIN18_INT_ENA_V 0x1F -#define GPIO_PIN18_INT_ENA_S 13 -/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN18_CONFIG 0x00000003 -#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) -#define GPIO_PIN18_CONFIG_V 0x3 -#define GPIO_PIN18_CONFIG_S 11 -/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN18_WAKEUP_ENABLE_S 10 -/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN18_INT_TYPE 0x00000007 -#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) -#define GPIO_PIN18_INT_TYPE_V 0x7 -#define GPIO_PIN18_INT_TYPE_S 7 -/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) -#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN18_SYNC1_BYPASS_S 3 -/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN18_PAD_DRIVER (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_V 0x1 -#define GPIO_PIN18_PAD_DRIVER_S 2 -/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) -#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN18_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN18_CONFIG 0x00000003U +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003U +#define GPIO_PIN18_CONFIG_S 11 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xC0) -/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN19_INT_ENA 0x0000001F -#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) -#define GPIO_PIN19_INT_ENA_V 0x1F -#define GPIO_PIN19_INT_ENA_S 13 -/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN19_CONFIG 0x00000003 -#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) -#define GPIO_PIN19_CONFIG_V 0x3 -#define GPIO_PIN19_CONFIG_S 11 -/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN19_WAKEUP_ENABLE_S 10 -/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN19_INT_TYPE 0x00000007 -#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) -#define GPIO_PIN19_INT_TYPE_V 0x7 -#define GPIO_PIN19_INT_TYPE_S 7 -/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) -#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN19_SYNC1_BYPASS_S 3 -/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN19_PAD_DRIVER (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_V 0x1 -#define GPIO_PIN19_PAD_DRIVER_S 2 -/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) -#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN19_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN19_CONFIG 0x00000003U +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003U +#define GPIO_PIN19_CONFIG_S 11 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xC4) -/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN20_INT_ENA 0x0000001F -#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) -#define GPIO_PIN20_INT_ENA_V 0x1F -#define GPIO_PIN20_INT_ENA_S 13 -/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN20_CONFIG 0x00000003 -#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) -#define GPIO_PIN20_CONFIG_V 0x3 -#define GPIO_PIN20_CONFIG_S 11 -/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN20_WAKEUP_ENABLE_S 10 -/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN20_INT_TYPE 0x00000007 -#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) -#define GPIO_PIN20_INT_TYPE_V 0x7 -#define GPIO_PIN20_INT_TYPE_S 7 -/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) -#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN20_SYNC1_BYPASS_S 3 -/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN20_PAD_DRIVER (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_V 0x1 -#define GPIO_PIN20_PAD_DRIVER_S 2 -/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) -#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN20_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN20_CONFIG 0x00000003U +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003U +#define GPIO_PIN20_CONFIG_S 11 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xC8) -/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN21_INT_ENA 0x0000001F -#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) -#define GPIO_PIN21_INT_ENA_V 0x1F -#define GPIO_PIN21_INT_ENA_S 13 -/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN21_CONFIG 0x00000003 -#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) -#define GPIO_PIN21_CONFIG_V 0x3 -#define GPIO_PIN21_CONFIG_S 11 -/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN21_WAKEUP_ENABLE_S 10 -/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN21_INT_TYPE 0x00000007 -#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) -#define GPIO_PIN21_INT_TYPE_V 0x7 -#define GPIO_PIN21_INT_TYPE_S 7 -/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) -#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN21_SYNC1_BYPASS_S 3 -/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN21_PAD_DRIVER (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_V 0x1 -#define GPIO_PIN21_PAD_DRIVER_S 2 -/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) -#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN21_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN21_CONFIG 0x00000003U +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003U +#define GPIO_PIN21_CONFIG_S 11 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xCC) -/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN22_INT_ENA 0x0000001F -#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) -#define GPIO_PIN22_INT_ENA_V 0x1F -#define GPIO_PIN22_INT_ENA_S 13 -/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN22_CONFIG 0x00000003 -#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) -#define GPIO_PIN22_CONFIG_V 0x3 -#define GPIO_PIN22_CONFIG_S 11 -/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN22_WAKEUP_ENABLE_S 10 -/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN22_INT_TYPE 0x00000007 -#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) -#define GPIO_PIN22_INT_TYPE_V 0x7 -#define GPIO_PIN22_INT_TYPE_S 7 -/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) -#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN22_SYNC1_BYPASS_S 3 -/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN22_PAD_DRIVER (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_V 0x1 -#define GPIO_PIN22_PAD_DRIVER_S 2 -/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) -#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN22_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN22_CONFIG 0x00000003U +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003U +#define GPIO_PIN22_CONFIG_S 11 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xD0) -/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN23_INT_ENA 0x0000001F -#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) -#define GPIO_PIN23_INT_ENA_V 0x1F -#define GPIO_PIN23_INT_ENA_S 13 -/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN23_CONFIG 0x00000003 -#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) -#define GPIO_PIN23_CONFIG_V 0x3 -#define GPIO_PIN23_CONFIG_S 11 -/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN23_WAKEUP_ENABLE_S 10 -/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN23_INT_TYPE 0x00000007 -#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) -#define GPIO_PIN23_INT_TYPE_V 0x7 -#define GPIO_PIN23_INT_TYPE_S 7 -/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) -#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN23_SYNC1_BYPASS_S 3 -/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN23_PAD_DRIVER (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_V 0x1 -#define GPIO_PIN23_PAD_DRIVER_S 2 -/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) -#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN23_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN23_CONFIG 0x00000003U +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003U +#define GPIO_PIN23_CONFIG_S 11 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xD4) -/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN24_INT_ENA 0x0000001F -#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) -#define GPIO_PIN24_INT_ENA_V 0x1F -#define GPIO_PIN24_INT_ENA_S 13 -/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN24_CONFIG 0x00000003 -#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) -#define GPIO_PIN24_CONFIG_V 0x3 -#define GPIO_PIN24_CONFIG_S 11 -/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN24_WAKEUP_ENABLE_S 10 -/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN24_INT_TYPE 0x00000007 -#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) -#define GPIO_PIN24_INT_TYPE_V 0x7 -#define GPIO_PIN24_INT_TYPE_S 7 -/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) -#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN24_SYNC1_BYPASS_S 3 -/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN24_PAD_DRIVER (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_V 0x1 -#define GPIO_PIN24_PAD_DRIVER_S 2 -/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) -#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN24_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN24_CONFIG 0x00000003U +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003U +#define GPIO_PIN24_CONFIG_S 11 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 -#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xD8) -/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN25_INT_ENA 0x0000001F -#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) -#define GPIO_PIN25_INT_ENA_V 0x1F -#define GPIO_PIN25_INT_ENA_S 13 -/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN25_CONFIG 0x00000003 -#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) -#define GPIO_PIN25_CONFIG_V 0x3 -#define GPIO_PIN25_CONFIG_S 11 -/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN25_WAKEUP_ENABLE_S 10 -/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN25_INT_TYPE 0x00000007 -#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) -#define GPIO_PIN25_INT_TYPE_V 0x7 -#define GPIO_PIN25_INT_TYPE_S 7 -/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) -#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN25_SYNC1_BYPASS_S 3 -/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN25_PAD_DRIVER (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_V 0x1 -#define GPIO_PIN25_PAD_DRIVER_S 2 -/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) -#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN25_CONFIG 0x00000003U +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003U +#define GPIO_PIN25_CONFIG_S 11 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 -#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xDC) -/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN26_INT_ENA 0x0000001F -#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) -#define GPIO_PIN26_INT_ENA_V 0x1F -#define GPIO_PIN26_INT_ENA_S 13 -/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN26_CONFIG 0x00000003 -#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) -#define GPIO_PIN26_CONFIG_V 0x3 -#define GPIO_PIN26_CONFIG_S 11 -/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN26_WAKEUP_ENABLE_S 10 -/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN26_INT_TYPE 0x00000007 -#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) -#define GPIO_PIN26_INT_TYPE_V 0x7 -#define GPIO_PIN26_INT_TYPE_S 7 -/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN26_SYNC1_BYPASS_M ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S)) -#define GPIO_PIN26_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN26_SYNC1_BYPASS_S 3 -/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN26_PAD_DRIVER (BIT(2)) -#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN26_PAD_DRIVER_V 0x1 -#define GPIO_PIN26_PAD_DRIVER_S 2 -/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN26_SYNC2_BYPASS_M ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S)) -#define GPIO_PIN26_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN26_CONFIG 0x00000003U +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003U +#define GPIO_PIN26_CONFIG_S 11 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 -#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xE0) -/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN27_INT_ENA 0x0000001F -#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) -#define GPIO_PIN27_INT_ENA_V 0x1F -#define GPIO_PIN27_INT_ENA_S 13 -/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN27_CONFIG 0x00000003 -#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) -#define GPIO_PIN27_CONFIG_V 0x3 -#define GPIO_PIN27_CONFIG_S 11 -/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN27_WAKEUP_ENABLE_S 10 -/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN27_INT_TYPE 0x00000007 -#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) -#define GPIO_PIN27_INT_TYPE_V 0x7 -#define GPIO_PIN27_INT_TYPE_S 7 -/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN27_SYNC1_BYPASS_M ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S)) -#define GPIO_PIN27_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN27_SYNC1_BYPASS_S 3 -/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN27_PAD_DRIVER (BIT(2)) -#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN27_PAD_DRIVER_V 0x1 -#define GPIO_PIN27_PAD_DRIVER_S 2 -/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN27_SYNC2_BYPASS_M ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S)) -#define GPIO_PIN27_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN27_CONFIG 0x00000003U +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003U +#define GPIO_PIN27_CONFIG_S 11 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 -#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xE4) -/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN28_INT_ENA 0x0000001F -#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) -#define GPIO_PIN28_INT_ENA_V 0x1F -#define GPIO_PIN28_INT_ENA_S 13 -/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN28_CONFIG 0x00000003 -#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) -#define GPIO_PIN28_CONFIG_V 0x3 -#define GPIO_PIN28_CONFIG_S 11 -/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN28_WAKEUP_ENABLE_S 10 -/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN28_INT_TYPE 0x00000007 -#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) -#define GPIO_PIN28_INT_TYPE_V 0x7 -#define GPIO_PIN28_INT_TYPE_S 7 -/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN28_SYNC1_BYPASS_M ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S)) -#define GPIO_PIN28_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN28_SYNC1_BYPASS_S 3 -/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN28_PAD_DRIVER (BIT(2)) -#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN28_PAD_DRIVER_V 0x1 -#define GPIO_PIN28_PAD_DRIVER_S 2 -/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN28_SYNC2_BYPASS_M ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S)) -#define GPIO_PIN28_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN28_CONFIG 0x00000003U +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003U +#define GPIO_PIN28_CONFIG_S 11 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 -#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xE8) -/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN29_INT_ENA 0x0000001F -#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) -#define GPIO_PIN29_INT_ENA_V 0x1F -#define GPIO_PIN29_INT_ENA_S 13 -/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN29_CONFIG 0x00000003 -#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) -#define GPIO_PIN29_CONFIG_V 0x3 -#define GPIO_PIN29_CONFIG_S 11 -/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN29_WAKEUP_ENABLE_S 10 -/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN29_INT_TYPE 0x00000007 -#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) -#define GPIO_PIN29_INT_TYPE_V 0x7 -#define GPIO_PIN29_INT_TYPE_S 7 -/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN29_SYNC1_BYPASS_M ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S)) -#define GPIO_PIN29_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN29_SYNC1_BYPASS_S 3 -/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN29_PAD_DRIVER (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_V 0x1 -#define GPIO_PIN29_PAD_DRIVER_S 2 -/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN29_SYNC2_BYPASS_M ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S)) -#define GPIO_PIN29_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN29_CONFIG 0x00000003U +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003U +#define GPIO_PIN29_CONFIG_S 11 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 -#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xEC) -/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN30_INT_ENA 0x0000001F -#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) -#define GPIO_PIN30_INT_ENA_V 0x1F -#define GPIO_PIN30_INT_ENA_S 13 -/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN30_CONFIG 0x00000003 -#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) -#define GPIO_PIN30_CONFIG_V 0x3 -#define GPIO_PIN30_CONFIG_S 11 -/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN30_WAKEUP_ENABLE_S 10 -/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN30_INT_TYPE 0x00000007 -#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) -#define GPIO_PIN30_INT_TYPE_V 0x7 -#define GPIO_PIN30_INT_TYPE_S 7 -/* GPIO_PIN30_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN30_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN30_SYNC1_BYPASS_M ((GPIO_PIN30_SYNC1_BYPASS_V)<<(GPIO_PIN30_SYNC1_BYPASS_S)) -#define GPIO_PIN30_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN30_SYNC1_BYPASS_S 3 -/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN30_PAD_DRIVER (BIT(2)) -#define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN30_PAD_DRIVER_V 0x1 -#define GPIO_PIN30_PAD_DRIVER_S 2 -/* GPIO_PIN30_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN30_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN30_SYNC2_BYPASS_M ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S)) -#define GPIO_PIN30_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN30_CONFIG 0x00000003U +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003U +#define GPIO_PIN30_CONFIG_S 11 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 -#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xF0) -/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN31_INT_ENA 0x0000001F -#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) -#define GPIO_PIN31_INT_ENA_V 0x1F -#define GPIO_PIN31_INT_ENA_S 13 -/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN31_CONFIG 0x00000003 -#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) -#define GPIO_PIN31_CONFIG_V 0x3 -#define GPIO_PIN31_CONFIG_S 11 -/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN31_WAKEUP_ENABLE_S 10 -/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN31_INT_TYPE 0x00000007 -#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) -#define GPIO_PIN31_INT_TYPE_V 0x7 -#define GPIO_PIN31_INT_TYPE_S 7 -/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN31_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN31_SYNC1_BYPASS_M ((GPIO_PIN31_SYNC1_BYPASS_V)<<(GPIO_PIN31_SYNC1_BYPASS_S)) -#define GPIO_PIN31_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN31_SYNC1_BYPASS_S 3 -/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN31_PAD_DRIVER (BIT(2)) -#define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN31_PAD_DRIVER_V 0x1 -#define GPIO_PIN31_PAD_DRIVER_S 2 -/* GPIO_PIN31_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN31_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN31_SYNC2_BYPASS_M ((GPIO_PIN31_SYNC2_BYPASS_V)<<(GPIO_PIN31_SYNC2_BYPASS_S)) -#define GPIO_PIN31_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN31_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) +/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN31_SYNC2_BYPASS_S 0 +/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN31_PAD_DRIVER_S 2 +/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN31_INT_TYPE 0x00000007U +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007U +#define GPIO_PIN31_INT_TYPE_S 7 +/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN31_CONFIG 0x00000003U +#define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) +#define GPIO_PIN31_CONFIG_V 0x00000003U +#define GPIO_PIN31_CONFIG_S 11 +/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN31_INT_ENA 0x0000001FU +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001FU +#define GPIO_PIN31_INT_ENA_S 13 -#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xF4) -/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN32_INT_ENA 0x0000001F -#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) -#define GPIO_PIN32_INT_ENA_V 0x1F -#define GPIO_PIN32_INT_ENA_S 13 -/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN32_CONFIG 0x00000003 -#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) -#define GPIO_PIN32_CONFIG_V 0x3 -#define GPIO_PIN32_CONFIG_S 11 -/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN32_WAKEUP_ENABLE_S 10 -/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN32_INT_TYPE 0x00000007 -#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) -#define GPIO_PIN32_INT_TYPE_V 0x7 -#define GPIO_PIN32_INT_TYPE_S 7 -/* GPIO_PIN32_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN32_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN32_SYNC1_BYPASS_M ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S)) -#define GPIO_PIN32_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN32_SYNC1_BYPASS_S 3 -/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN32_PAD_DRIVER (BIT(2)) -#define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN32_PAD_DRIVER_V 0x1 -#define GPIO_PIN32_PAD_DRIVER_S 2 -/* GPIO_PIN32_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN32_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN32_SYNC2_BYPASS_M ((GPIO_PIN32_SYNC2_BYPASS_V)<<(GPIO_PIN32_SYNC2_BYPASS_S)) -#define GPIO_PIN32_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN32_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4) +/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN32_SYNC2_BYPASS_S 0 +/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) +#define GPIO_PIN32_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN32_PAD_DRIVER_S 2 +/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_S 3 +/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN32_INT_TYPE 0x00000007U +#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) +#define GPIO_PIN32_INT_TYPE_V 0x00000007U +#define GPIO_PIN32_INT_TYPE_S 7 +/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN32_CONFIG 0x00000003U +#define GPIO_PIN32_CONFIG_M (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S) +#define GPIO_PIN32_CONFIG_V 0x00000003U +#define GPIO_PIN32_CONFIG_S 11 +/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN32_INT_ENA 0x0000001FU +#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) +#define GPIO_PIN32_INT_ENA_V 0x0000001FU +#define GPIO_PIN32_INT_ENA_S 13 -#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xF8) -/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN33_INT_ENA 0x0000001F -#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) -#define GPIO_PIN33_INT_ENA_V 0x1F -#define GPIO_PIN33_INT_ENA_S 13 -/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN33_CONFIG 0x00000003 -#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) -#define GPIO_PIN33_CONFIG_V 0x3 -#define GPIO_PIN33_CONFIG_S 11 -/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN33_WAKEUP_ENABLE_S 10 -/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN33_INT_TYPE 0x00000007 -#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) -#define GPIO_PIN33_INT_TYPE_V 0x7 -#define GPIO_PIN33_INT_TYPE_S 7 -/* GPIO_PIN33_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN33_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN33_SYNC1_BYPASS_M ((GPIO_PIN33_SYNC1_BYPASS_V)<<(GPIO_PIN33_SYNC1_BYPASS_S)) -#define GPIO_PIN33_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN33_SYNC1_BYPASS_S 3 -/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN33_PAD_DRIVER (BIT(2)) -#define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN33_PAD_DRIVER_V 0x1 -#define GPIO_PIN33_PAD_DRIVER_S 2 -/* GPIO_PIN33_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN33_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN33_SYNC2_BYPASS_M ((GPIO_PIN33_SYNC2_BYPASS_V)<<(GPIO_PIN33_SYNC2_BYPASS_S)) -#define GPIO_PIN33_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN33_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8) +/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN33_SYNC2_BYPASS_S 0 +/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) +#define GPIO_PIN33_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN33_PAD_DRIVER_S 2 +/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_S 3 +/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN33_INT_TYPE 0x00000007U +#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) +#define GPIO_PIN33_INT_TYPE_V 0x00000007U +#define GPIO_PIN33_INT_TYPE_S 7 +/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN33_CONFIG 0x00000003U +#define GPIO_PIN33_CONFIG_M (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S) +#define GPIO_PIN33_CONFIG_V 0x00000003U +#define GPIO_PIN33_CONFIG_S 11 +/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN33_INT_ENA 0x0000001FU +#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) +#define GPIO_PIN33_INT_ENA_V 0x0000001FU +#define GPIO_PIN33_INT_ENA_S 13 -#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xFC) -/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN34_INT_ENA 0x0000001F -#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) -#define GPIO_PIN34_INT_ENA_V 0x1F -#define GPIO_PIN34_INT_ENA_S 13 -/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN34_CONFIG 0x00000003 -#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) -#define GPIO_PIN34_CONFIG_V 0x3 -#define GPIO_PIN34_CONFIG_S 11 -/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN34_WAKEUP_ENABLE_S 10 -/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN34_INT_TYPE 0x00000007 -#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) -#define GPIO_PIN34_INT_TYPE_V 0x7 -#define GPIO_PIN34_INT_TYPE_S 7 -/* GPIO_PIN34_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN34_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN34_SYNC1_BYPASS_M ((GPIO_PIN34_SYNC1_BYPASS_V)<<(GPIO_PIN34_SYNC1_BYPASS_S)) -#define GPIO_PIN34_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN34_SYNC1_BYPASS_S 3 -/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN34_PAD_DRIVER (BIT(2)) -#define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN34_PAD_DRIVER_V 0x1 -#define GPIO_PIN34_PAD_DRIVER_S 2 -/* GPIO_PIN34_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN34_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN34_SYNC2_BYPASS_M ((GPIO_PIN34_SYNC2_BYPASS_V)<<(GPIO_PIN34_SYNC2_BYPASS_S)) -#define GPIO_PIN34_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN34_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc) +/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN34_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN34_SYNC2_BYPASS_M (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S) +#define GPIO_PIN34_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN34_SYNC2_BYPASS_S 0 +/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S) +#define GPIO_PIN34_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN34_PAD_DRIVER_S 2 +/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN34_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN34_SYNC1_BYPASS_M (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S) +#define GPIO_PIN34_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN34_SYNC1_BYPASS_S 3 +/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN34_INT_TYPE 0x00000007U +#define GPIO_PIN34_INT_TYPE_M (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S) +#define GPIO_PIN34_INT_TYPE_V 0x00000007U +#define GPIO_PIN34_INT_TYPE_S 7 +/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 +/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN34_CONFIG 0x00000003U +#define GPIO_PIN34_CONFIG_M (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S) +#define GPIO_PIN34_CONFIG_V 0x00000003U +#define GPIO_PIN34_CONFIG_S 11 +/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN34_INT_ENA 0x0000001FU +#define GPIO_PIN34_INT_ENA_M (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S) +#define GPIO_PIN34_INT_ENA_V 0x0000001FU +#define GPIO_PIN34_INT_ENA_S 13 -#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) -/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN35_INT_ENA 0x0000001F -#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) -#define GPIO_PIN35_INT_ENA_V 0x1F -#define GPIO_PIN35_INT_ENA_S 13 -/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN35_CONFIG 0x00000003 -#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) -#define GPIO_PIN35_CONFIG_V 0x3 -#define GPIO_PIN35_CONFIG_S 11 -/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN35_WAKEUP_ENABLE_S 10 -/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN35_INT_TYPE 0x00000007 -#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) -#define GPIO_PIN35_INT_TYPE_V 0x7 -#define GPIO_PIN35_INT_TYPE_S 7 -/* GPIO_PIN35_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN35_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN35_SYNC1_BYPASS_M ((GPIO_PIN35_SYNC1_BYPASS_V)<<(GPIO_PIN35_SYNC1_BYPASS_S)) -#define GPIO_PIN35_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN35_SYNC1_BYPASS_S 3 -/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN35_PAD_DRIVER (BIT(2)) -#define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN35_PAD_DRIVER_V 0x1 -#define GPIO_PIN35_PAD_DRIVER_S 2 -/* GPIO_PIN35_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN35_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN35_SYNC2_BYPASS_M ((GPIO_PIN35_SYNC2_BYPASS_V)<<(GPIO_PIN35_SYNC2_BYPASS_S)) -#define GPIO_PIN35_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN35_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) +/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN35_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN35_SYNC2_BYPASS_M (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S) +#define GPIO_PIN35_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN35_SYNC2_BYPASS_S 0 +/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S) +#define GPIO_PIN35_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN35_PAD_DRIVER_S 2 +/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN35_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN35_SYNC1_BYPASS_M (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S) +#define GPIO_PIN35_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN35_SYNC1_BYPASS_S 3 +/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN35_INT_TYPE 0x00000007U +#define GPIO_PIN35_INT_TYPE_M (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S) +#define GPIO_PIN35_INT_TYPE_V 0x00000007U +#define GPIO_PIN35_INT_TYPE_S 7 +/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 +/** GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN35_CONFIG 0x00000003U +#define GPIO_PIN35_CONFIG_M (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S) +#define GPIO_PIN35_CONFIG_V 0x00000003U +#define GPIO_PIN35_CONFIG_S 11 +/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN35_INT_ENA 0x0000001FU +#define GPIO_PIN35_INT_ENA_M (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S) +#define GPIO_PIN35_INT_ENA_V 0x0000001FU +#define GPIO_PIN35_INT_ENA_S 13 -#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) -/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN36_INT_ENA 0x0000001F -#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) -#define GPIO_PIN36_INT_ENA_V 0x1F -#define GPIO_PIN36_INT_ENA_S 13 -/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN36_CONFIG 0x00000003 -#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) -#define GPIO_PIN36_CONFIG_V 0x3 -#define GPIO_PIN36_CONFIG_S 11 -/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN36_WAKEUP_ENABLE_S 10 -/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN36_INT_TYPE 0x00000007 -#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) -#define GPIO_PIN36_INT_TYPE_V 0x7 -#define GPIO_PIN36_INT_TYPE_S 7 -/* GPIO_PIN36_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN36_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN36_SYNC1_BYPASS_M ((GPIO_PIN36_SYNC1_BYPASS_V)<<(GPIO_PIN36_SYNC1_BYPASS_S)) -#define GPIO_PIN36_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN36_SYNC1_BYPASS_S 3 -/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN36_PAD_DRIVER (BIT(2)) -#define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN36_PAD_DRIVER_V 0x1 -#define GPIO_PIN36_PAD_DRIVER_S 2 -/* GPIO_PIN36_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN36_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN36_SYNC2_BYPASS_M ((GPIO_PIN36_SYNC2_BYPASS_V)<<(GPIO_PIN36_SYNC2_BYPASS_S)) -#define GPIO_PIN36_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN36_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) +/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN36_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN36_SYNC2_BYPASS_M (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S) +#define GPIO_PIN36_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN36_SYNC2_BYPASS_S 0 +/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S) +#define GPIO_PIN36_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN36_PAD_DRIVER_S 2 +/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN36_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN36_SYNC1_BYPASS_M (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S) +#define GPIO_PIN36_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN36_SYNC1_BYPASS_S 3 +/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN36_INT_TYPE 0x00000007U +#define GPIO_PIN36_INT_TYPE_M (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S) +#define GPIO_PIN36_INT_TYPE_V 0x00000007U +#define GPIO_PIN36_INT_TYPE_S 7 +/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 +/** GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN36_CONFIG 0x00000003U +#define GPIO_PIN36_CONFIG_M (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S) +#define GPIO_PIN36_CONFIG_V 0x00000003U +#define GPIO_PIN36_CONFIG_S 11 +/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN36_INT_ENA 0x0000001FU +#define GPIO_PIN36_INT_ENA_M (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S) +#define GPIO_PIN36_INT_ENA_V 0x0000001FU +#define GPIO_PIN36_INT_ENA_S 13 -#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) -/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN37_INT_ENA 0x0000001F -#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) -#define GPIO_PIN37_INT_ENA_V 0x1F -#define GPIO_PIN37_INT_ENA_S 13 -/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN37_CONFIG 0x00000003 -#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) -#define GPIO_PIN37_CONFIG_V 0x3 -#define GPIO_PIN37_CONFIG_S 11 -/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN37_WAKEUP_ENABLE_S 10 -/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN37_INT_TYPE 0x00000007 -#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) -#define GPIO_PIN37_INT_TYPE_V 0x7 -#define GPIO_PIN37_INT_TYPE_S 7 -/* GPIO_PIN37_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN37_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN37_SYNC1_BYPASS_M ((GPIO_PIN37_SYNC1_BYPASS_V)<<(GPIO_PIN37_SYNC1_BYPASS_S)) -#define GPIO_PIN37_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN37_SYNC1_BYPASS_S 3 -/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN37_PAD_DRIVER (BIT(2)) -#define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN37_PAD_DRIVER_V 0x1 -#define GPIO_PIN37_PAD_DRIVER_S 2 -/* GPIO_PIN37_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN37_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN37_SYNC2_BYPASS_M ((GPIO_PIN37_SYNC2_BYPASS_V)<<(GPIO_PIN37_SYNC2_BYPASS_S)) -#define GPIO_PIN37_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN37_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) +/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN37_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN37_SYNC2_BYPASS_M (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S) +#define GPIO_PIN37_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN37_SYNC2_BYPASS_S 0 +/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S) +#define GPIO_PIN37_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN37_PAD_DRIVER_S 2 +/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN37_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN37_SYNC1_BYPASS_M (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S) +#define GPIO_PIN37_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN37_SYNC1_BYPASS_S 3 +/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN37_INT_TYPE 0x00000007U +#define GPIO_PIN37_INT_TYPE_M (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S) +#define GPIO_PIN37_INT_TYPE_V 0x00000007U +#define GPIO_PIN37_INT_TYPE_S 7 +/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 +/** GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN37_CONFIG 0x00000003U +#define GPIO_PIN37_CONFIG_M (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S) +#define GPIO_PIN37_CONFIG_V 0x00000003U +#define GPIO_PIN37_CONFIG_S 11 +/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN37_INT_ENA 0x0000001FU +#define GPIO_PIN37_INT_ENA_M (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S) +#define GPIO_PIN37_INT_ENA_V 0x0000001FU +#define GPIO_PIN37_INT_ENA_S 13 -#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10C) -/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN38_INT_ENA 0x0000001F -#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) -#define GPIO_PIN38_INT_ENA_V 0x1F -#define GPIO_PIN38_INT_ENA_S 13 -/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN38_CONFIG 0x00000003 -#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) -#define GPIO_PIN38_CONFIG_V 0x3 -#define GPIO_PIN38_CONFIG_S 11 -/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN38_WAKEUP_ENABLE_S 10 -/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN38_INT_TYPE 0x00000007 -#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) -#define GPIO_PIN38_INT_TYPE_V 0x7 -#define GPIO_PIN38_INT_TYPE_S 7 -/* GPIO_PIN38_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN38_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN38_SYNC1_BYPASS_M ((GPIO_PIN38_SYNC1_BYPASS_V)<<(GPIO_PIN38_SYNC1_BYPASS_S)) -#define GPIO_PIN38_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN38_SYNC1_BYPASS_S 3 -/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN38_PAD_DRIVER (BIT(2)) -#define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN38_PAD_DRIVER_V 0x1 -#define GPIO_PIN38_PAD_DRIVER_S 2 -/* GPIO_PIN38_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN38_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN38_SYNC2_BYPASS_M ((GPIO_PIN38_SYNC2_BYPASS_V)<<(GPIO_PIN38_SYNC2_BYPASS_S)) -#define GPIO_PIN38_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN38_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c) +/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN38_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN38_SYNC2_BYPASS_M (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S) +#define GPIO_PIN38_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN38_SYNC2_BYPASS_S 0 +/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S) +#define GPIO_PIN38_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN38_PAD_DRIVER_S 2 +/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN38_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN38_SYNC1_BYPASS_M (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S) +#define GPIO_PIN38_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN38_SYNC1_BYPASS_S 3 +/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN38_INT_TYPE 0x00000007U +#define GPIO_PIN38_INT_TYPE_M (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S) +#define GPIO_PIN38_INT_TYPE_V 0x00000007U +#define GPIO_PIN38_INT_TYPE_S 7 +/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 +/** GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN38_CONFIG 0x00000003U +#define GPIO_PIN38_CONFIG_M (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S) +#define GPIO_PIN38_CONFIG_V 0x00000003U +#define GPIO_PIN38_CONFIG_S 11 +/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN38_INT_ENA 0x0000001FU +#define GPIO_PIN38_INT_ENA_M (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S) +#define GPIO_PIN38_INT_ENA_V 0x0000001FU +#define GPIO_PIN38_INT_ENA_S 13 -#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) -/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN39_INT_ENA 0x0000001F -#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) -#define GPIO_PIN39_INT_ENA_V 0x1F -#define GPIO_PIN39_INT_ENA_S 13 -/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN39_CONFIG 0x00000003 -#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) -#define GPIO_PIN39_CONFIG_V 0x3 -#define GPIO_PIN39_CONFIG_S 11 -/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN39_WAKEUP_ENABLE_S 10 -/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN39_INT_TYPE 0x00000007 -#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) -#define GPIO_PIN39_INT_TYPE_V 0x7 -#define GPIO_PIN39_INT_TYPE_S 7 -/* GPIO_PIN39_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN39_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN39_SYNC1_BYPASS_M ((GPIO_PIN39_SYNC1_BYPASS_V)<<(GPIO_PIN39_SYNC1_BYPASS_S)) -#define GPIO_PIN39_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN39_SYNC1_BYPASS_S 3 -/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN39_PAD_DRIVER (BIT(2)) -#define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN39_PAD_DRIVER_V 0x1 -#define GPIO_PIN39_PAD_DRIVER_S 2 -/* GPIO_PIN39_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN39_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN39_SYNC2_BYPASS_M ((GPIO_PIN39_SYNC2_BYPASS_V)<<(GPIO_PIN39_SYNC2_BYPASS_S)) -#define GPIO_PIN39_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN39_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) +/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN39_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN39_SYNC2_BYPASS_M (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S) +#define GPIO_PIN39_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN39_SYNC2_BYPASS_S 0 +/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S) +#define GPIO_PIN39_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN39_PAD_DRIVER_S 2 +/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN39_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN39_SYNC1_BYPASS_M (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S) +#define GPIO_PIN39_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN39_SYNC1_BYPASS_S 3 +/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN39_INT_TYPE 0x00000007U +#define GPIO_PIN39_INT_TYPE_M (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S) +#define GPIO_PIN39_INT_TYPE_V 0x00000007U +#define GPIO_PIN39_INT_TYPE_S 7 +/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 +/** GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN39_CONFIG 0x00000003U +#define GPIO_PIN39_CONFIG_M (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S) +#define GPIO_PIN39_CONFIG_V 0x00000003U +#define GPIO_PIN39_CONFIG_S 11 +/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN39_INT_ENA 0x0000001FU +#define GPIO_PIN39_INT_ENA_M (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S) +#define GPIO_PIN39_INT_ENA_V 0x0000001FU +#define GPIO_PIN39_INT_ENA_S 13 -#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) -/* GPIO_PIN40_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN40_INT_ENA 0x0000001F -#define GPIO_PIN40_INT_ENA_M ((GPIO_PIN40_INT_ENA_V)<<(GPIO_PIN40_INT_ENA_S)) -#define GPIO_PIN40_INT_ENA_V 0x1F -#define GPIO_PIN40_INT_ENA_S 13 -/* GPIO_PIN40_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN40_CONFIG 0x00000003 -#define GPIO_PIN40_CONFIG_M ((GPIO_PIN40_CONFIG_V)<<(GPIO_PIN40_CONFIG_S)) -#define GPIO_PIN40_CONFIG_V 0x3 -#define GPIO_PIN40_CONFIG_S 11 -/* GPIO_PIN40_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN40_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN40_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN40_WAKEUP_ENABLE_S 10 -/* GPIO_PIN40_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN40_INT_TYPE 0x00000007 -#define GPIO_PIN40_INT_TYPE_M ((GPIO_PIN40_INT_TYPE_V)<<(GPIO_PIN40_INT_TYPE_S)) -#define GPIO_PIN40_INT_TYPE_V 0x7 -#define GPIO_PIN40_INT_TYPE_S 7 -/* GPIO_PIN40_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN40_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN40_SYNC1_BYPASS_M ((GPIO_PIN40_SYNC1_BYPASS_V)<<(GPIO_PIN40_SYNC1_BYPASS_S)) -#define GPIO_PIN40_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN40_SYNC1_BYPASS_S 3 -/* GPIO_PIN40_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN40_PAD_DRIVER (BIT(2)) -#define GPIO_PIN40_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN40_PAD_DRIVER_V 0x1 -#define GPIO_PIN40_PAD_DRIVER_S 2 -/* GPIO_PIN40_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN40_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN40_SYNC2_BYPASS_M ((GPIO_PIN40_SYNC2_BYPASS_V)<<(GPIO_PIN40_SYNC2_BYPASS_S)) -#define GPIO_PIN40_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN40_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) +/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN40_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN40_SYNC2_BYPASS_M (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S) +#define GPIO_PIN40_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN40_SYNC2_BYPASS_S 0 +/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN40_PAD_DRIVER (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_M (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S) +#define GPIO_PIN40_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN40_PAD_DRIVER_S 2 +/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN40_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN40_SYNC1_BYPASS_M (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S) +#define GPIO_PIN40_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN40_SYNC1_BYPASS_S 3 +/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN40_INT_TYPE 0x00000007U +#define GPIO_PIN40_INT_TYPE_M (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S) +#define GPIO_PIN40_INT_TYPE_V 0x00000007U +#define GPIO_PIN40_INT_TYPE_S 7 +/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_M (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S) +#define GPIO_PIN40_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN40_WAKEUP_ENABLE_S 10 +/** GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN40_CONFIG 0x00000003U +#define GPIO_PIN40_CONFIG_M (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S) +#define GPIO_PIN40_CONFIG_V 0x00000003U +#define GPIO_PIN40_CONFIG_S 11 +/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN40_INT_ENA 0x0000001FU +#define GPIO_PIN40_INT_ENA_M (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S) +#define GPIO_PIN40_INT_ENA_V 0x0000001FU +#define GPIO_PIN40_INT_ENA_S 13 -#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) -/* GPIO_PIN41_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN41_INT_ENA 0x0000001F -#define GPIO_PIN41_INT_ENA_M ((GPIO_PIN41_INT_ENA_V)<<(GPIO_PIN41_INT_ENA_S)) -#define GPIO_PIN41_INT_ENA_V 0x1F -#define GPIO_PIN41_INT_ENA_S 13 -/* GPIO_PIN41_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN41_CONFIG 0x00000003 -#define GPIO_PIN41_CONFIG_M ((GPIO_PIN41_CONFIG_V)<<(GPIO_PIN41_CONFIG_S)) -#define GPIO_PIN41_CONFIG_V 0x3 -#define GPIO_PIN41_CONFIG_S 11 -/* GPIO_PIN41_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN41_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN41_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN41_WAKEUP_ENABLE_S 10 -/* GPIO_PIN41_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN41_INT_TYPE 0x00000007 -#define GPIO_PIN41_INT_TYPE_M ((GPIO_PIN41_INT_TYPE_V)<<(GPIO_PIN41_INT_TYPE_S)) -#define GPIO_PIN41_INT_TYPE_V 0x7 -#define GPIO_PIN41_INT_TYPE_S 7 -/* GPIO_PIN41_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN41_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN41_SYNC1_BYPASS_M ((GPIO_PIN41_SYNC1_BYPASS_V)<<(GPIO_PIN41_SYNC1_BYPASS_S)) -#define GPIO_PIN41_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN41_SYNC1_BYPASS_S 3 -/* GPIO_PIN41_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN41_PAD_DRIVER (BIT(2)) -#define GPIO_PIN41_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN41_PAD_DRIVER_V 0x1 -#define GPIO_PIN41_PAD_DRIVER_S 2 -/* GPIO_PIN41_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN41_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN41_SYNC2_BYPASS_M ((GPIO_PIN41_SYNC2_BYPASS_V)<<(GPIO_PIN41_SYNC2_BYPASS_S)) -#define GPIO_PIN41_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN41_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) +/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN41_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN41_SYNC2_BYPASS_M (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S) +#define GPIO_PIN41_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN41_SYNC2_BYPASS_S 0 +/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN41_PAD_DRIVER (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_M (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S) +#define GPIO_PIN41_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN41_PAD_DRIVER_S 2 +/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN41_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN41_SYNC1_BYPASS_M (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S) +#define GPIO_PIN41_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN41_SYNC1_BYPASS_S 3 +/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN41_INT_TYPE 0x00000007U +#define GPIO_PIN41_INT_TYPE_M (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S) +#define GPIO_PIN41_INT_TYPE_V 0x00000007U +#define GPIO_PIN41_INT_TYPE_S 7 +/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_M (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S) +#define GPIO_PIN41_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN41_WAKEUP_ENABLE_S 10 +/** GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN41_CONFIG 0x00000003U +#define GPIO_PIN41_CONFIG_M (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S) +#define GPIO_PIN41_CONFIG_V 0x00000003U +#define GPIO_PIN41_CONFIG_S 11 +/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN41_INT_ENA 0x0000001FU +#define GPIO_PIN41_INT_ENA_M (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S) +#define GPIO_PIN41_INT_ENA_V 0x0000001FU +#define GPIO_PIN41_INT_ENA_S 13 -#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11C) -/* GPIO_PIN42_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN42_INT_ENA 0x0000001F -#define GPIO_PIN42_INT_ENA_M ((GPIO_PIN42_INT_ENA_V)<<(GPIO_PIN42_INT_ENA_S)) -#define GPIO_PIN42_INT_ENA_V 0x1F -#define GPIO_PIN42_INT_ENA_S 13 -/* GPIO_PIN42_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN42_CONFIG 0x00000003 -#define GPIO_PIN42_CONFIG_M ((GPIO_PIN42_CONFIG_V)<<(GPIO_PIN42_CONFIG_S)) -#define GPIO_PIN42_CONFIG_V 0x3 -#define GPIO_PIN42_CONFIG_S 11 -/* GPIO_PIN42_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN42_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN42_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN42_WAKEUP_ENABLE_S 10 -/* GPIO_PIN42_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN42_INT_TYPE 0x00000007 -#define GPIO_PIN42_INT_TYPE_M ((GPIO_PIN42_INT_TYPE_V)<<(GPIO_PIN42_INT_TYPE_S)) -#define GPIO_PIN42_INT_TYPE_V 0x7 -#define GPIO_PIN42_INT_TYPE_S 7 -/* GPIO_PIN42_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN42_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN42_SYNC1_BYPASS_M ((GPIO_PIN42_SYNC1_BYPASS_V)<<(GPIO_PIN42_SYNC1_BYPASS_S)) -#define GPIO_PIN42_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN42_SYNC1_BYPASS_S 3 -/* GPIO_PIN42_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN42_PAD_DRIVER (BIT(2)) -#define GPIO_PIN42_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN42_PAD_DRIVER_V 0x1 -#define GPIO_PIN42_PAD_DRIVER_S 2 -/* GPIO_PIN42_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN42_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN42_SYNC2_BYPASS_M ((GPIO_PIN42_SYNC2_BYPASS_V)<<(GPIO_PIN42_SYNC2_BYPASS_S)) -#define GPIO_PIN42_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN42_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c) +/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN42_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN42_SYNC2_BYPASS_M (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S) +#define GPIO_PIN42_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN42_SYNC2_BYPASS_S 0 +/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN42_PAD_DRIVER (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_M (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S) +#define GPIO_PIN42_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN42_PAD_DRIVER_S 2 +/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN42_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN42_SYNC1_BYPASS_M (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S) +#define GPIO_PIN42_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN42_SYNC1_BYPASS_S 3 +/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN42_INT_TYPE 0x00000007U +#define GPIO_PIN42_INT_TYPE_M (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S) +#define GPIO_PIN42_INT_TYPE_V 0x00000007U +#define GPIO_PIN42_INT_TYPE_S 7 +/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_M (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S) +#define GPIO_PIN42_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN42_WAKEUP_ENABLE_S 10 +/** GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN42_CONFIG 0x00000003U +#define GPIO_PIN42_CONFIG_M (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S) +#define GPIO_PIN42_CONFIG_V 0x00000003U +#define GPIO_PIN42_CONFIG_S 11 +/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN42_INT_ENA 0x0000001FU +#define GPIO_PIN42_INT_ENA_M (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S) +#define GPIO_PIN42_INT_ENA_V 0x0000001FU +#define GPIO_PIN42_INT_ENA_S 13 -#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) -/* GPIO_PIN43_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN43_INT_ENA 0x0000001F -#define GPIO_PIN43_INT_ENA_M ((GPIO_PIN43_INT_ENA_V)<<(GPIO_PIN43_INT_ENA_S)) -#define GPIO_PIN43_INT_ENA_V 0x1F -#define GPIO_PIN43_INT_ENA_S 13 -/* GPIO_PIN43_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN43_CONFIG 0x00000003 -#define GPIO_PIN43_CONFIG_M ((GPIO_PIN43_CONFIG_V)<<(GPIO_PIN43_CONFIG_S)) -#define GPIO_PIN43_CONFIG_V 0x3 -#define GPIO_PIN43_CONFIG_S 11 -/* GPIO_PIN43_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN43_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN43_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN43_WAKEUP_ENABLE_S 10 -/* GPIO_PIN43_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN43_INT_TYPE 0x00000007 -#define GPIO_PIN43_INT_TYPE_M ((GPIO_PIN43_INT_TYPE_V)<<(GPIO_PIN43_INT_TYPE_S)) -#define GPIO_PIN43_INT_TYPE_V 0x7 -#define GPIO_PIN43_INT_TYPE_S 7 -/* GPIO_PIN43_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN43_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN43_SYNC1_BYPASS_M ((GPIO_PIN43_SYNC1_BYPASS_V)<<(GPIO_PIN43_SYNC1_BYPASS_S)) -#define GPIO_PIN43_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN43_SYNC1_BYPASS_S 3 -/* GPIO_PIN43_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN43_PAD_DRIVER (BIT(2)) -#define GPIO_PIN43_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN43_PAD_DRIVER_V 0x1 -#define GPIO_PIN43_PAD_DRIVER_S 2 -/* GPIO_PIN43_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN43_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN43_SYNC2_BYPASS_M ((GPIO_PIN43_SYNC2_BYPASS_V)<<(GPIO_PIN43_SYNC2_BYPASS_S)) -#define GPIO_PIN43_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN43_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) +/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN43_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN43_SYNC2_BYPASS_M (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S) +#define GPIO_PIN43_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN43_SYNC2_BYPASS_S 0 +/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN43_PAD_DRIVER (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_M (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S) +#define GPIO_PIN43_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN43_PAD_DRIVER_S 2 +/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN43_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN43_SYNC1_BYPASS_M (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S) +#define GPIO_PIN43_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN43_SYNC1_BYPASS_S 3 +/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN43_INT_TYPE 0x00000007U +#define GPIO_PIN43_INT_TYPE_M (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S) +#define GPIO_PIN43_INT_TYPE_V 0x00000007U +#define GPIO_PIN43_INT_TYPE_S 7 +/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_M (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S) +#define GPIO_PIN43_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN43_WAKEUP_ENABLE_S 10 +/** GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN43_CONFIG 0x00000003U +#define GPIO_PIN43_CONFIG_M (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S) +#define GPIO_PIN43_CONFIG_V 0x00000003U +#define GPIO_PIN43_CONFIG_S 11 +/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN43_INT_ENA 0x0000001FU +#define GPIO_PIN43_INT_ENA_M (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S) +#define GPIO_PIN43_INT_ENA_V 0x0000001FU +#define GPIO_PIN43_INT_ENA_S 13 -#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) -/* GPIO_PIN44_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: */ -#define GPIO_PIN44_INT_ENA 0x0000001F -#define GPIO_PIN44_INT_ENA_M ((GPIO_PIN44_INT_ENA_V)<<(GPIO_PIN44_INT_ENA_S)) -#define GPIO_PIN44_INT_ENA_V 0x1F -#define GPIO_PIN44_INT_ENA_S 13 -/* GPIO_PIN44_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN44_CONFIG 0x00000003 -#define GPIO_PIN44_CONFIG_M ((GPIO_PIN44_CONFIG_V)<<(GPIO_PIN44_CONFIG_S)) -#define GPIO_PIN44_CONFIG_V 0x3 -#define GPIO_PIN44_CONFIG_S 11 -/* GPIO_PIN44_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN44_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN44_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN44_WAKEUP_ENABLE_S 10 -/* GPIO_PIN44_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: */ -#define GPIO_PIN44_INT_TYPE 0x00000007 -#define GPIO_PIN44_INT_TYPE_M ((GPIO_PIN44_INT_TYPE_V)<<(GPIO_PIN44_INT_TYPE_S)) -#define GPIO_PIN44_INT_TYPE_V 0x7 -#define GPIO_PIN44_INT_TYPE_S 7 -/* GPIO_PIN44_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN44_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN44_SYNC1_BYPASS_M ((GPIO_PIN44_SYNC1_BYPASS_V)<<(GPIO_PIN44_SYNC1_BYPASS_S)) -#define GPIO_PIN44_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN44_SYNC1_BYPASS_S 3 -/* GPIO_PIN44_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_PIN44_PAD_DRIVER (BIT(2)) -#define GPIO_PIN44_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN44_PAD_DRIVER_V 0x1 -#define GPIO_PIN44_PAD_DRIVER_S 2 -/* GPIO_PIN44_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: */ -#define GPIO_PIN44_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN44_SYNC2_BYPASS_M ((GPIO_PIN44_SYNC2_BYPASS_V)<<(GPIO_PIN44_SYNC2_BYPASS_S)) -#define GPIO_PIN44_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN44_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) +/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN44_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN44_SYNC2_BYPASS_M (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S) +#define GPIO_PIN44_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN44_SYNC2_BYPASS_S 0 +/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN44_PAD_DRIVER (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_M (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S) +#define GPIO_PIN44_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN44_PAD_DRIVER_S 2 +/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN44_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN44_SYNC1_BYPASS_M (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S) +#define GPIO_PIN44_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN44_SYNC1_BYPASS_S 3 +/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN44_INT_TYPE 0x00000007U +#define GPIO_PIN44_INT_TYPE_M (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S) +#define GPIO_PIN44_INT_TYPE_V 0x00000007U +#define GPIO_PIN44_INT_TYPE_S 7 +/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_M (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S) +#define GPIO_PIN44_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN44_WAKEUP_ENABLE_S 10 +/** GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN44_CONFIG 0x00000003U +#define GPIO_PIN44_CONFIG_M (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S) +#define GPIO_PIN44_CONFIG_V 0x00000003U +#define GPIO_PIN44_CONFIG_S 11 +/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN44_INT_ENA 0x0000001FU +#define GPIO_PIN44_INT_ENA_M (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S) +#define GPIO_PIN44_INT_ENA_V 0x0000001FU +#define GPIO_PIN44_INT_ENA_S 13 -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) -/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFF -#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFF +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_S 0 -#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) -/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[12:0] ;default: 13'h0 ; */ -/*description: */ -#define GPIO_STATUS_INTERRUPT_NEXT1 0x00001FFF -#define GPIO_STATUS_INTERRUPT_NEXT1_M ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S)) -#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x1FFF +/** GPIO_STATUS_NEXT1_REG register + * GPIO interrupt source register for GPIO32-44 + */ +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) +/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [12:0]; default: 0; + * GPIO interrupt source register for GPIO32-44 + */ +#define GPIO_STATUS_INTERRUPT_NEXT1 0x00001FFFU +#define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) +#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x00001FFFU #define GPIO_STATUS_INTERRUPT_NEXT1_S 0 -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) -/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG0_IN_SEL (BIT(7)) -#define GPIO_SIG0_IN_SEL_M (BIT(7)) -#define GPIO_SIG0_IN_SEL_V 0x1 -#define GPIO_SIG0_IN_SEL_S 7 -/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC0_IN_INV_SEL_V 0x1 -#define GPIO_FUNC0_IN_INV_SEL_S 6 -/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC0_IN_SEL 0x0000003F -#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) -#define GPIO_FUNC0_IN_SEL_V 0x3F +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003FU #define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 7 -#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) -/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG1_IN_SEL (BIT(7)) -#define GPIO_SIG1_IN_SEL_M (BIT(7)) -#define GPIO_SIG1_IN_SEL_V 0x1 -#define GPIO_SIG1_IN_SEL_S 7 -/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC1_IN_INV_SEL_V 0x1 -#define GPIO_FUNC1_IN_INV_SEL_S 6 -/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC1_IN_SEL 0x0000003F -#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) -#define GPIO_FUNC1_IN_SEL_V 0x3F +/** GPIO_FUNC1_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) +/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC1_IN_SEL 0x0000003FU +#define GPIO_FUNC1_IN_SEL_M (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S) +#define GPIO_FUNC1_IN_SEL_V 0x0000003FU #define GPIO_FUNC1_IN_SEL_S 0 +/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S) +#define GPIO_FUNC1_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_IN_INV_SEL_S 6 +/** GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S) +#define GPIO_SIG1_IN_SEL_V 0x00000001U +#define GPIO_SIG1_IN_SEL_S 7 -#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15C) -/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG2_IN_SEL (BIT(7)) -#define GPIO_SIG2_IN_SEL_M (BIT(7)) -#define GPIO_SIG2_IN_SEL_V 0x1 -#define GPIO_SIG2_IN_SEL_S 7 -/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC2_IN_INV_SEL_V 0x1 -#define GPIO_FUNC2_IN_INV_SEL_S 6 -/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC2_IN_SEL 0x0000003F -#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) -#define GPIO_FUNC2_IN_SEL_V 0x3F +/** GPIO_FUNC2_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) +/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC2_IN_SEL 0x0000003FU +#define GPIO_FUNC2_IN_SEL_M (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S) +#define GPIO_FUNC2_IN_SEL_V 0x0000003FU #define GPIO_FUNC2_IN_SEL_S 0 +/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S) +#define GPIO_FUNC2_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_IN_INV_SEL_S 6 +/** GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S) +#define GPIO_SIG2_IN_SEL_V 0x00000001U +#define GPIO_SIG2_IN_SEL_S 7 -#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) -/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG3_IN_SEL (BIT(7)) -#define GPIO_SIG3_IN_SEL_M (BIT(7)) -#define GPIO_SIG3_IN_SEL_V 0x1 -#define GPIO_SIG3_IN_SEL_S 7 -/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC3_IN_INV_SEL_V 0x1 -#define GPIO_FUNC3_IN_INV_SEL_S 6 -/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC3_IN_SEL 0x0000003F -#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) -#define GPIO_FUNC3_IN_SEL_V 0x3F +/** GPIO_FUNC3_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) +/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC3_IN_SEL 0x0000003FU +#define GPIO_FUNC3_IN_SEL_M (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S) +#define GPIO_FUNC3_IN_SEL_V 0x0000003FU #define GPIO_FUNC3_IN_SEL_S 0 +/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S) +#define GPIO_FUNC3_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_IN_INV_SEL_S 6 +/** GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S) +#define GPIO_SIG3_IN_SEL_V 0x00000001U +#define GPIO_SIG3_IN_SEL_S 7 -#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) -/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG4_IN_SEL (BIT(7)) -#define GPIO_SIG4_IN_SEL_M (BIT(7)) -#define GPIO_SIG4_IN_SEL_V 0x1 -#define GPIO_SIG4_IN_SEL_S 7 -/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC4_IN_INV_SEL_V 0x1 -#define GPIO_FUNC4_IN_INV_SEL_S 6 -/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC4_IN_SEL 0x0000003F -#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) -#define GPIO_FUNC4_IN_SEL_V 0x3F +/** GPIO_FUNC4_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) +/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC4_IN_SEL 0x0000003FU +#define GPIO_FUNC4_IN_SEL_M (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S) +#define GPIO_FUNC4_IN_SEL_V 0x0000003FU #define GPIO_FUNC4_IN_SEL_S 0 +/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S) +#define GPIO_FUNC4_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_IN_INV_SEL_S 6 +/** GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S) +#define GPIO_SIG4_IN_SEL_V 0x00000001U +#define GPIO_SIG4_IN_SEL_S 7 -#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) -/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG5_IN_SEL (BIT(7)) -#define GPIO_SIG5_IN_SEL_M (BIT(7)) -#define GPIO_SIG5_IN_SEL_V 0x1 -#define GPIO_SIG5_IN_SEL_S 7 -/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC5_IN_INV_SEL_V 0x1 -#define GPIO_FUNC5_IN_INV_SEL_S 6 -/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC5_IN_SEL 0x0000003F -#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) -#define GPIO_FUNC5_IN_SEL_V 0x3F +/** GPIO_FUNC5_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) +/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC5_IN_SEL 0x0000003FU +#define GPIO_FUNC5_IN_SEL_M (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S) +#define GPIO_FUNC5_IN_SEL_V 0x0000003FU #define GPIO_FUNC5_IN_SEL_S 0 +/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S) +#define GPIO_FUNC5_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_IN_INV_SEL_S 6 +/** GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S) +#define GPIO_SIG5_IN_SEL_V 0x00000001U +#define GPIO_SIG5_IN_SEL_S 7 -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16C) -/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG6_IN_SEL (BIT(7)) -#define GPIO_SIG6_IN_SEL_M (BIT(7)) -#define GPIO_SIG6_IN_SEL_V 0x1 -#define GPIO_SIG6_IN_SEL_S 7 -/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC6_IN_INV_SEL_V 0x1 -#define GPIO_FUNC6_IN_INV_SEL_S 6 -/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC6_IN_SEL 0x0000003F -#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) -#define GPIO_FUNC6_IN_SEL_V 0x3F +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003FU #define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 7 -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) -/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG7_IN_SEL (BIT(7)) -#define GPIO_SIG7_IN_SEL_M (BIT(7)) -#define GPIO_SIG7_IN_SEL_V 0x1 -#define GPIO_SIG7_IN_SEL_S 7 -/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC7_IN_INV_SEL_V 0x1 -#define GPIO_FUNC7_IN_INV_SEL_S 6 -/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC7_IN_SEL 0x0000003F -#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) -#define GPIO_FUNC7_IN_SEL_V 0x3F +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003FU #define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 7 -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) -/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG8_IN_SEL (BIT(7)) -#define GPIO_SIG8_IN_SEL_M (BIT(7)) -#define GPIO_SIG8_IN_SEL_V 0x1 -#define GPIO_SIG8_IN_SEL_S 7 -/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC8_IN_INV_SEL_V 0x1 -#define GPIO_FUNC8_IN_INV_SEL_S 6 -/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC8_IN_SEL 0x0000003F -#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) -#define GPIO_FUNC8_IN_SEL_V 0x3F +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003FU #define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 7 -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) -/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG9_IN_SEL (BIT(7)) -#define GPIO_SIG9_IN_SEL_M (BIT(7)) -#define GPIO_SIG9_IN_SEL_V 0x1 -#define GPIO_SIG9_IN_SEL_S 7 -/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC9_IN_INV_SEL_V 0x1 -#define GPIO_FUNC9_IN_INV_SEL_S 6 -/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC9_IN_SEL 0x0000003F -#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) -#define GPIO_FUNC9_IN_SEL_V 0x3F +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003FU #define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 7 -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17C) -/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG10_IN_SEL (BIT(7)) -#define GPIO_SIG10_IN_SEL_M (BIT(7)) -#define GPIO_SIG10_IN_SEL_V 0x1 -#define GPIO_SIG10_IN_SEL_S 7 -/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC10_IN_INV_SEL_V 0x1 -#define GPIO_FUNC10_IN_INV_SEL_S 6 -/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC10_IN_SEL 0x0000003F -#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) -#define GPIO_FUNC10_IN_SEL_V 0x3F +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003FU #define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 7 -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) -/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG11_IN_SEL (BIT(7)) -#define GPIO_SIG11_IN_SEL_M (BIT(7)) -#define GPIO_SIG11_IN_SEL_V 0x1 -#define GPIO_SIG11_IN_SEL_S 7 -/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC11_IN_INV_SEL_V 0x1 -#define GPIO_FUNC11_IN_INV_SEL_S 6 -/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC11_IN_SEL 0x0000003F -#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) -#define GPIO_FUNC11_IN_SEL_V 0x3F +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003FU #define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 7 -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) -/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG12_IN_SEL (BIT(7)) -#define GPIO_SIG12_IN_SEL_M (BIT(7)) -#define GPIO_SIG12_IN_SEL_V 0x1 -#define GPIO_SIG12_IN_SEL_S 7 -/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC12_IN_INV_SEL_V 0x1 -#define GPIO_FUNC12_IN_INV_SEL_S 6 -/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC12_IN_SEL 0x0000003F -#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) -#define GPIO_FUNC12_IN_SEL_V 0x3F +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003FU #define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 7 -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) -/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG13_IN_SEL (BIT(7)) -#define GPIO_SIG13_IN_SEL_M (BIT(7)) -#define GPIO_SIG13_IN_SEL_V 0x1 -#define GPIO_SIG13_IN_SEL_S 7 -/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC13_IN_INV_SEL_V 0x1 -#define GPIO_FUNC13_IN_INV_SEL_S 6 -/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC13_IN_SEL 0x0000003F -#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) -#define GPIO_FUNC13_IN_SEL_V 0x3F +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003FU #define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 7 -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18C) -/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG14_IN_SEL (BIT(7)) -#define GPIO_SIG14_IN_SEL_M (BIT(7)) -#define GPIO_SIG14_IN_SEL_V 0x1 -#define GPIO_SIG14_IN_SEL_S 7 -/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC14_IN_INV_SEL_V 0x1 -#define GPIO_FUNC14_IN_INV_SEL_S 6 -/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC14_IN_SEL 0x0000003F -#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) -#define GPIO_FUNC14_IN_SEL_V 0x3F +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003FU #define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 7 -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) -/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG15_IN_SEL (BIT(7)) -#define GPIO_SIG15_IN_SEL_M (BIT(7)) -#define GPIO_SIG15_IN_SEL_V 0x1 -#define GPIO_SIG15_IN_SEL_S 7 -/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC15_IN_INV_SEL_V 0x1 -#define GPIO_FUNC15_IN_INV_SEL_S 6 -/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC15_IN_SEL 0x0000003F -#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) -#define GPIO_FUNC15_IN_SEL_V 0x3F +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003FU #define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 7 -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) -/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG16_IN_SEL (BIT(7)) -#define GPIO_SIG16_IN_SEL_M (BIT(7)) -#define GPIO_SIG16_IN_SEL_V 0x1 -#define GPIO_SIG16_IN_SEL_S 7 -/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC16_IN_INV_SEL_V 0x1 -#define GPIO_FUNC16_IN_INV_SEL_S 6 -/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC16_IN_SEL 0x0000003F -#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) -#define GPIO_FUNC16_IN_SEL_V 0x3F +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003FU #define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 7 -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) -/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG17_IN_SEL (BIT(7)) -#define GPIO_SIG17_IN_SEL_M (BIT(7)) -#define GPIO_SIG17_IN_SEL_V 0x1 -#define GPIO_SIG17_IN_SEL_S 7 -/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC17_IN_INV_SEL_V 0x1 -#define GPIO_FUNC17_IN_INV_SEL_S 6 -/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC17_IN_SEL 0x0000003F -#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) -#define GPIO_FUNC17_IN_SEL_V 0x3F +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003FU #define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 7 -#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19C) -/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG18_IN_SEL (BIT(7)) -#define GPIO_SIG18_IN_SEL_M (BIT(7)) -#define GPIO_SIG18_IN_SEL_V 0x1 -#define GPIO_SIG18_IN_SEL_S 7 -/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC18_IN_INV_SEL_V 0x1 -#define GPIO_FUNC18_IN_INV_SEL_S 6 -/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC18_IN_SEL 0x0000003F -#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) -#define GPIO_FUNC18_IN_SEL_V 0x3F +/** GPIO_FUNC18_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) +/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC18_IN_SEL 0x0000003FU +#define GPIO_FUNC18_IN_SEL_M (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S) +#define GPIO_FUNC18_IN_SEL_V 0x0000003FU #define GPIO_FUNC18_IN_SEL_S 0 +/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S) +#define GPIO_FUNC18_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_IN_INV_SEL_S 6 +/** GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S) +#define GPIO_SIG18_IN_SEL_V 0x00000001U +#define GPIO_SIG18_IN_SEL_S 7 -#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A0) -/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG19_IN_SEL (BIT(7)) -#define GPIO_SIG19_IN_SEL_M (BIT(7)) -#define GPIO_SIG19_IN_SEL_V 0x1 -#define GPIO_SIG19_IN_SEL_S 7 -/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC19_IN_INV_SEL_V 0x1 -#define GPIO_FUNC19_IN_INV_SEL_S 6 -/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC19_IN_SEL 0x0000003F -#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) -#define GPIO_FUNC19_IN_SEL_V 0x3F +/** GPIO_FUNC19_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) +/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC19_IN_SEL 0x0000003FU +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003FU #define GPIO_FUNC19_IN_SEL_S 0 +/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001U +#define GPIO_SIG19_IN_SEL_S 7 -#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A4) -/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG20_IN_SEL (BIT(7)) -#define GPIO_SIG20_IN_SEL_M (BIT(7)) -#define GPIO_SIG20_IN_SEL_V 0x1 -#define GPIO_SIG20_IN_SEL_S 7 -/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC20_IN_INV_SEL_V 0x1 -#define GPIO_FUNC20_IN_INV_SEL_S 6 -/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC20_IN_SEL 0x0000003F -#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) -#define GPIO_FUNC20_IN_SEL_V 0x3F +/** GPIO_FUNC20_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) +/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC20_IN_SEL 0x0000003FU +#define GPIO_FUNC20_IN_SEL_M (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S) +#define GPIO_FUNC20_IN_SEL_V 0x0000003FU #define GPIO_FUNC20_IN_SEL_S 0 +/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S) +#define GPIO_FUNC20_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_IN_INV_SEL_S 6 +/** GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S) +#define GPIO_SIG20_IN_SEL_V 0x00000001U +#define GPIO_SIG20_IN_SEL_S 7 -#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A8) -/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG21_IN_SEL (BIT(7)) -#define GPIO_SIG21_IN_SEL_M (BIT(7)) -#define GPIO_SIG21_IN_SEL_V 0x1 -#define GPIO_SIG21_IN_SEL_S 7 -/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC21_IN_INV_SEL_V 0x1 -#define GPIO_FUNC21_IN_INV_SEL_S 6 -/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC21_IN_SEL 0x0000003F -#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) -#define GPIO_FUNC21_IN_SEL_V 0x3F +/** GPIO_FUNC21_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) +/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC21_IN_SEL 0x0000003FU +#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) +#define GPIO_FUNC21_IN_SEL_V 0x0000003FU #define GPIO_FUNC21_IN_SEL_S 0 +/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) +#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) +#define GPIO_SIG21_IN_SEL_V 0x00000001U +#define GPIO_SIG21_IN_SEL_S 7 -#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1AC) -/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG22_IN_SEL (BIT(7)) -#define GPIO_SIG22_IN_SEL_M (BIT(7)) -#define GPIO_SIG22_IN_SEL_V 0x1 -#define GPIO_SIG22_IN_SEL_S 7 -/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC22_IN_INV_SEL_V 0x1 -#define GPIO_FUNC22_IN_INV_SEL_S 6 -/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC22_IN_SEL 0x0000003F -#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) -#define GPIO_FUNC22_IN_SEL_V 0x3F +/** GPIO_FUNC22_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) +/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC22_IN_SEL 0x0000003FU +#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) +#define GPIO_FUNC22_IN_SEL_V 0x0000003FU #define GPIO_FUNC22_IN_SEL_S 0 +/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) +#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) +#define GPIO_SIG22_IN_SEL_V 0x00000001U +#define GPIO_SIG22_IN_SEL_S 7 -#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B0) -/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG23_IN_SEL (BIT(7)) -#define GPIO_SIG23_IN_SEL_M (BIT(7)) -#define GPIO_SIG23_IN_SEL_V 0x1 -#define GPIO_SIG23_IN_SEL_S 7 -/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC23_IN_INV_SEL_V 0x1 -#define GPIO_FUNC23_IN_INV_SEL_S 6 -/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC23_IN_SEL 0x0000003F -#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) -#define GPIO_FUNC23_IN_SEL_V 0x3F +/** GPIO_FUNC23_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) +/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC23_IN_SEL 0x0000003FU +#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) +#define GPIO_FUNC23_IN_SEL_V 0x0000003FU #define GPIO_FUNC23_IN_SEL_S 0 +/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) +#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) +#define GPIO_SIG23_IN_SEL_V 0x00000001U +#define GPIO_SIG23_IN_SEL_S 7 -#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B4) -/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG24_IN_SEL (BIT(7)) -#define GPIO_SIG24_IN_SEL_M (BIT(7)) -#define GPIO_SIG24_IN_SEL_V 0x1 -#define GPIO_SIG24_IN_SEL_S 7 -/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC24_IN_INV_SEL_V 0x1 -#define GPIO_FUNC24_IN_INV_SEL_S 6 -/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC24_IN_SEL 0x0000003F -#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) -#define GPIO_FUNC24_IN_SEL_V 0x3F +/** GPIO_FUNC24_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) +/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC24_IN_SEL 0x0000003FU +#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) +#define GPIO_FUNC24_IN_SEL_V 0x0000003FU #define GPIO_FUNC24_IN_SEL_S 0 +/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) +#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) +#define GPIO_SIG24_IN_SEL_V 0x00000001U +#define GPIO_SIG24_IN_SEL_S 7 -#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B8) -/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG25_IN_SEL (BIT(7)) -#define GPIO_SIG25_IN_SEL_M (BIT(7)) -#define GPIO_SIG25_IN_SEL_V 0x1 -#define GPIO_SIG25_IN_SEL_S 7 -/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC25_IN_INV_SEL_V 0x1 -#define GPIO_FUNC25_IN_INV_SEL_S 6 -/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC25_IN_SEL 0x0000003F -#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) -#define GPIO_FUNC25_IN_SEL_V 0x3F +/** GPIO_FUNC25_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) +/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC25_IN_SEL 0x0000003FU +#define GPIO_FUNC25_IN_SEL_M (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S) +#define GPIO_FUNC25_IN_SEL_V 0x0000003FU #define GPIO_FUNC25_IN_SEL_S 0 +/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S) +#define GPIO_FUNC25_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_IN_INV_SEL_S 6 +/** GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S) +#define GPIO_SIG25_IN_SEL_V 0x00000001U +#define GPIO_SIG25_IN_SEL_S 7 -#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1BC) -/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG26_IN_SEL (BIT(7)) -#define GPIO_SIG26_IN_SEL_M (BIT(7)) -#define GPIO_SIG26_IN_SEL_V 0x1 -#define GPIO_SIG26_IN_SEL_S 7 -/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC26_IN_INV_SEL_V 0x1 -#define GPIO_FUNC26_IN_INV_SEL_S 6 -/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC26_IN_SEL 0x0000003F -#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) -#define GPIO_FUNC26_IN_SEL_V 0x3F +/** GPIO_FUNC26_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) +/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC26_IN_SEL 0x0000003FU +#define GPIO_FUNC26_IN_SEL_M (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S) +#define GPIO_FUNC26_IN_SEL_V 0x0000003FU #define GPIO_FUNC26_IN_SEL_S 0 +/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S) +#define GPIO_FUNC26_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_IN_INV_SEL_S 6 +/** GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S) +#define GPIO_SIG26_IN_SEL_V 0x00000001U +#define GPIO_SIG26_IN_SEL_S 7 -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C0) -/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG27_IN_SEL (BIT(7)) -#define GPIO_SIG27_IN_SEL_M (BIT(7)) -#define GPIO_SIG27_IN_SEL_V 0x1 -#define GPIO_SIG27_IN_SEL_S 7 -/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC27_IN_INV_SEL_V 0x1 -#define GPIO_FUNC27_IN_INV_SEL_S 6 -/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC27_IN_SEL 0x0000003F -#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) -#define GPIO_FUNC27_IN_SEL_V 0x3F +/** GPIO_FUNC27_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) +/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC27_IN_SEL 0x0000003FU +#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) +#define GPIO_FUNC27_IN_SEL_V 0x0000003FU #define GPIO_FUNC27_IN_SEL_S 0 +/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) +#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_IN_INV_SEL_S 6 +/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) +#define GPIO_SIG27_IN_SEL_V 0x00000001U +#define GPIO_SIG27_IN_SEL_S 7 -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C4) -/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG28_IN_SEL (BIT(7)) -#define GPIO_SIG28_IN_SEL_M (BIT(7)) -#define GPIO_SIG28_IN_SEL_V 0x1 -#define GPIO_SIG28_IN_SEL_S 7 -/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC28_IN_INV_SEL_V 0x1 -#define GPIO_FUNC28_IN_INV_SEL_S 6 -/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC28_IN_SEL 0x0000003F -#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) -#define GPIO_FUNC28_IN_SEL_V 0x3F +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003FU #define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 7 -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C8) -/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG29_IN_SEL (BIT(7)) -#define GPIO_SIG29_IN_SEL_M (BIT(7)) -#define GPIO_SIG29_IN_SEL_V 0x1 -#define GPIO_SIG29_IN_SEL_S 7 -/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC29_IN_INV_SEL_V 0x1 -#define GPIO_FUNC29_IN_INV_SEL_S 6 -/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC29_IN_SEL 0x0000003F -#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) -#define GPIO_FUNC29_IN_SEL_V 0x3F +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003FU #define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 7 -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1CC) -/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG30_IN_SEL (BIT(7)) -#define GPIO_SIG30_IN_SEL_M (BIT(7)) -#define GPIO_SIG30_IN_SEL_V 0x1 -#define GPIO_SIG30_IN_SEL_S 7 -/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC30_IN_INV_SEL_V 0x1 -#define GPIO_FUNC30_IN_INV_SEL_S 6 -/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC30_IN_SEL 0x0000003F -#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) -#define GPIO_FUNC30_IN_SEL_V 0x3F +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003FU #define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 7 -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D0) -/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG31_IN_SEL (BIT(7)) -#define GPIO_SIG31_IN_SEL_M (BIT(7)) -#define GPIO_SIG31_IN_SEL_V 0x1 -#define GPIO_SIG31_IN_SEL_S 7 -/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC31_IN_INV_SEL_V 0x1 -#define GPIO_FUNC31_IN_INV_SEL_S 6 -/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC31_IN_SEL 0x0000003F -#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) -#define GPIO_FUNC31_IN_SEL_V 0x3F +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003FU #define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 7 -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D4) -/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG32_IN_SEL (BIT(7)) -#define GPIO_SIG32_IN_SEL_M (BIT(7)) -#define GPIO_SIG32_IN_SEL_V 0x1 -#define GPIO_SIG32_IN_SEL_S 7 -/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC32_IN_INV_SEL_V 0x1 -#define GPIO_FUNC32_IN_INV_SEL_S 6 -/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC32_IN_SEL 0x0000003F -#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) -#define GPIO_FUNC32_IN_SEL_V 0x3F +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003FU #define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 7 -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D8) -/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG33_IN_SEL (BIT(7)) -#define GPIO_SIG33_IN_SEL_M (BIT(7)) -#define GPIO_SIG33_IN_SEL_V 0x1 -#define GPIO_SIG33_IN_SEL_S 7 -/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC33_IN_INV_SEL_V 0x1 -#define GPIO_FUNC33_IN_INV_SEL_S 6 -/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC33_IN_SEL 0x0000003F -#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) -#define GPIO_FUNC33_IN_SEL_V 0x3F +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003FU #define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 7 -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1DC) -/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG34_IN_SEL (BIT(7)) -#define GPIO_SIG34_IN_SEL_M (BIT(7)) -#define GPIO_SIG34_IN_SEL_V 0x1 -#define GPIO_SIG34_IN_SEL_S 7 -/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC34_IN_INV_SEL_V 0x1 -#define GPIO_FUNC34_IN_INV_SEL_S 6 -/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC34_IN_SEL 0x0000003F -#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) -#define GPIO_FUNC34_IN_SEL_V 0x3F +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003FU #define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 7 -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E0) -/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG35_IN_SEL (BIT(7)) -#define GPIO_SIG35_IN_SEL_M (BIT(7)) -#define GPIO_SIG35_IN_SEL_V 0x1 -#define GPIO_SIG35_IN_SEL_S 7 -/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC35_IN_INV_SEL_V 0x1 -#define GPIO_FUNC35_IN_INV_SEL_S 6 -/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC35_IN_SEL 0x0000003F -#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) -#define GPIO_FUNC35_IN_SEL_V 0x3F +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003FU #define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 7 -#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E4) -/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG36_IN_SEL (BIT(7)) -#define GPIO_SIG36_IN_SEL_M (BIT(7)) -#define GPIO_SIG36_IN_SEL_V 0x1 -#define GPIO_SIG36_IN_SEL_S 7 -/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC36_IN_INV_SEL_V 0x1 -#define GPIO_FUNC36_IN_INV_SEL_S 6 -/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC36_IN_SEL 0x0000003F -#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) -#define GPIO_FUNC36_IN_SEL_V 0x3F +/** GPIO_FUNC36_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) +/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC36_IN_SEL 0x0000003FU +#define GPIO_FUNC36_IN_SEL_M (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S) +#define GPIO_FUNC36_IN_SEL_V 0x0000003FU #define GPIO_FUNC36_IN_SEL_S 0 +/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S) +#define GPIO_FUNC36_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC36_IN_INV_SEL_S 6 +/** GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S) +#define GPIO_SIG36_IN_SEL_V 0x00000001U +#define GPIO_SIG36_IN_SEL_S 7 -#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E8) -/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG37_IN_SEL (BIT(7)) -#define GPIO_SIG37_IN_SEL_M (BIT(7)) -#define GPIO_SIG37_IN_SEL_V 0x1 -#define GPIO_SIG37_IN_SEL_S 7 -/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC37_IN_INV_SEL_V 0x1 -#define GPIO_FUNC37_IN_INV_SEL_S 6 -/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC37_IN_SEL 0x0000003F -#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) -#define GPIO_FUNC37_IN_SEL_V 0x3F +/** GPIO_FUNC37_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) +/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC37_IN_SEL 0x0000003FU +#define GPIO_FUNC37_IN_SEL_M (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S) +#define GPIO_FUNC37_IN_SEL_V 0x0000003FU #define GPIO_FUNC37_IN_SEL_S 0 +/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S) +#define GPIO_FUNC37_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC37_IN_INV_SEL_S 6 +/** GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S) +#define GPIO_SIG37_IN_SEL_V 0x00000001U +#define GPIO_SIG37_IN_SEL_S 7 -#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1EC) -/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG38_IN_SEL (BIT(7)) -#define GPIO_SIG38_IN_SEL_M (BIT(7)) -#define GPIO_SIG38_IN_SEL_V 0x1 -#define GPIO_SIG38_IN_SEL_S 7 -/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC38_IN_INV_SEL_V 0x1 -#define GPIO_FUNC38_IN_INV_SEL_S 6 -/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC38_IN_SEL 0x0000003F -#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) -#define GPIO_FUNC38_IN_SEL_V 0x3F +/** GPIO_FUNC38_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) +/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC38_IN_SEL 0x0000003FU +#define GPIO_FUNC38_IN_SEL_M (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S) +#define GPIO_FUNC38_IN_SEL_V 0x0000003FU #define GPIO_FUNC38_IN_SEL_S 0 +/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S) +#define GPIO_FUNC38_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC38_IN_INV_SEL_S 6 +/** GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S) +#define GPIO_SIG38_IN_SEL_V 0x00000001U +#define GPIO_SIG38_IN_SEL_S 7 -#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F0) -/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG39_IN_SEL (BIT(7)) -#define GPIO_SIG39_IN_SEL_M (BIT(7)) -#define GPIO_SIG39_IN_SEL_V 0x1 -#define GPIO_SIG39_IN_SEL_S 7 -/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC39_IN_INV_SEL_V 0x1 -#define GPIO_FUNC39_IN_INV_SEL_S 6 -/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC39_IN_SEL 0x0000003F -#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) -#define GPIO_FUNC39_IN_SEL_V 0x3F +/** GPIO_FUNC39_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) +/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC39_IN_SEL 0x0000003FU +#define GPIO_FUNC39_IN_SEL_M (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S) +#define GPIO_FUNC39_IN_SEL_V 0x0000003FU #define GPIO_FUNC39_IN_SEL_S 0 +/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S) +#define GPIO_FUNC39_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC39_IN_INV_SEL_S 6 +/** GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S) +#define GPIO_SIG39_IN_SEL_V 0x00000001U +#define GPIO_SIG39_IN_SEL_S 7 -#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F4) -/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG40_IN_SEL (BIT(7)) -#define GPIO_SIG40_IN_SEL_M (BIT(7)) -#define GPIO_SIG40_IN_SEL_V 0x1 -#define GPIO_SIG40_IN_SEL_S 7 -/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC40_IN_INV_SEL_V 0x1 -#define GPIO_FUNC40_IN_INV_SEL_S 6 -/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC40_IN_SEL 0x0000003F -#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) -#define GPIO_FUNC40_IN_SEL_V 0x3F +/** GPIO_FUNC40_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) +/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC40_IN_SEL 0x0000003FU +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003FU #define GPIO_FUNC40_IN_SEL_S 0 +/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001U +#define GPIO_SIG40_IN_SEL_S 7 -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F8) -/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG41_IN_SEL (BIT(7)) -#define GPIO_SIG41_IN_SEL_M (BIT(7)) -#define GPIO_SIG41_IN_SEL_V 0x1 -#define GPIO_SIG41_IN_SEL_S 7 -/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC41_IN_INV_SEL_V 0x1 -#define GPIO_FUNC41_IN_INV_SEL_S 6 -/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC41_IN_SEL 0x0000003F -#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) -#define GPIO_FUNC41_IN_SEL_V 0x3F +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003FU #define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 7 -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1FC) -/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG42_IN_SEL (BIT(7)) -#define GPIO_SIG42_IN_SEL_M (BIT(7)) -#define GPIO_SIG42_IN_SEL_V 0x1 -#define GPIO_SIG42_IN_SEL_S 7 -/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC42_IN_INV_SEL_V 0x1 -#define GPIO_FUNC42_IN_INV_SEL_S 6 -/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC42_IN_SEL 0x0000003F -#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) -#define GPIO_FUNC42_IN_SEL_V 0x3F +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003FU #define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 7 -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) -/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG43_IN_SEL (BIT(7)) -#define GPIO_SIG43_IN_SEL_M (BIT(7)) -#define GPIO_SIG43_IN_SEL_V 0x1 -#define GPIO_SIG43_IN_SEL_S 7 -/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC43_IN_INV_SEL_V 0x1 -#define GPIO_FUNC43_IN_INV_SEL_S 6 -/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC43_IN_SEL 0x0000003F -#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) -#define GPIO_FUNC43_IN_SEL_V 0x3F +/** GPIO_FUNC43_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) +/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC43_IN_SEL 0x0000003FU +#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) +#define GPIO_FUNC43_IN_SEL_V 0x0000003FU #define GPIO_FUNC43_IN_SEL_S 0 +/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) +#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC43_IN_INV_SEL_S 6 +/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) +#define GPIO_SIG43_IN_SEL_V 0x00000001U +#define GPIO_SIG43_IN_SEL_S 7 -#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) -/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG44_IN_SEL (BIT(7)) -#define GPIO_SIG44_IN_SEL_M (BIT(7)) -#define GPIO_SIG44_IN_SEL_V 0x1 -#define GPIO_SIG44_IN_SEL_S 7 -/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC44_IN_INV_SEL_V 0x1 -#define GPIO_FUNC44_IN_INV_SEL_S 6 -/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC44_IN_SEL 0x0000003F -#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) -#define GPIO_FUNC44_IN_SEL_V 0x3F +/** GPIO_FUNC44_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) +/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC44_IN_SEL 0x0000003FU +#define GPIO_FUNC44_IN_SEL_M (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S) +#define GPIO_FUNC44_IN_SEL_V 0x0000003FU #define GPIO_FUNC44_IN_SEL_S 0 +/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S) +#define GPIO_FUNC44_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC44_IN_INV_SEL_S 6 +/** GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S) +#define GPIO_SIG44_IN_SEL_V 0x00000001U +#define GPIO_SIG44_IN_SEL_S 7 -#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) -/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG45_IN_SEL (BIT(7)) -#define GPIO_SIG45_IN_SEL_M (BIT(7)) -#define GPIO_SIG45_IN_SEL_V 0x1 -#define GPIO_SIG45_IN_SEL_S 7 -/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC45_IN_INV_SEL_V 0x1 -#define GPIO_FUNC45_IN_INV_SEL_S 6 -/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC45_IN_SEL 0x0000003F -#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) -#define GPIO_FUNC45_IN_SEL_V 0x3F +/** GPIO_FUNC45_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC45_IN_SEL 0x0000003FU +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003FU #define GPIO_FUNC45_IN_SEL_S 0 +/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001U +#define GPIO_SIG45_IN_SEL_S 7 -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20C) -/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG46_IN_SEL (BIT(7)) -#define GPIO_SIG46_IN_SEL_M (BIT(7)) -#define GPIO_SIG46_IN_SEL_V 0x1 -#define GPIO_SIG46_IN_SEL_S 7 -/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC46_IN_INV_SEL_V 0x1 -#define GPIO_FUNC46_IN_INV_SEL_S 6 -/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC46_IN_SEL 0x0000003F -#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) -#define GPIO_FUNC46_IN_SEL_V 0x3F +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003FU #define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 7 -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) -/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG47_IN_SEL (BIT(7)) -#define GPIO_SIG47_IN_SEL_M (BIT(7)) -#define GPIO_SIG47_IN_SEL_V 0x1 -#define GPIO_SIG47_IN_SEL_S 7 -/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC47_IN_INV_SEL_V 0x1 -#define GPIO_FUNC47_IN_INV_SEL_S 6 -/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC47_IN_SEL 0x0000003F -#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) -#define GPIO_FUNC47_IN_SEL_V 0x3F +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003FU #define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 7 -#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) -/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG48_IN_SEL (BIT(7)) -#define GPIO_SIG48_IN_SEL_M (BIT(7)) -#define GPIO_SIG48_IN_SEL_V 0x1 -#define GPIO_SIG48_IN_SEL_S 7 -/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC48_IN_INV_SEL_V 0x1 -#define GPIO_FUNC48_IN_INV_SEL_S 6 -/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC48_IN_SEL 0x0000003F -#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) -#define GPIO_FUNC48_IN_SEL_V 0x3F +/** GPIO_FUNC48_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC48_IN_SEL 0x0000003FU +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003FU #define GPIO_FUNC48_IN_SEL_S 0 +/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001U +#define GPIO_SIG48_IN_SEL_S 7 -#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) -/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG49_IN_SEL (BIT(7)) -#define GPIO_SIG49_IN_SEL_M (BIT(7)) -#define GPIO_SIG49_IN_SEL_V 0x1 -#define GPIO_SIG49_IN_SEL_S 7 -/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC49_IN_INV_SEL_V 0x1 -#define GPIO_FUNC49_IN_INV_SEL_S 6 -/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC49_IN_SEL 0x0000003F -#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) -#define GPIO_FUNC49_IN_SEL_V 0x3F +/** GPIO_FUNC49_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC49_IN_SEL 0x0000003FU +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003FU #define GPIO_FUNC49_IN_SEL_S 0 +/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001U +#define GPIO_SIG49_IN_SEL_S 7 -#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21C) -/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG50_IN_SEL (BIT(7)) -#define GPIO_SIG50_IN_SEL_M (BIT(7)) -#define GPIO_SIG50_IN_SEL_V 0x1 -#define GPIO_SIG50_IN_SEL_S 7 -/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC50_IN_INV_SEL_V 0x1 -#define GPIO_FUNC50_IN_INV_SEL_S 6 -/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC50_IN_SEL 0x0000003F -#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) -#define GPIO_FUNC50_IN_SEL_V 0x3F +/** GPIO_FUNC50_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) +/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC50_IN_SEL 0x0000003FU +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003FU #define GPIO_FUNC50_IN_SEL_S 0 +/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001U +#define GPIO_SIG50_IN_SEL_S 7 -#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) -/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG51_IN_SEL (BIT(7)) -#define GPIO_SIG51_IN_SEL_M (BIT(7)) -#define GPIO_SIG51_IN_SEL_V 0x1 -#define GPIO_SIG51_IN_SEL_S 7 -/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC51_IN_INV_SEL_V 0x1 -#define GPIO_FUNC51_IN_INV_SEL_S 6 -/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC51_IN_SEL 0x0000003F -#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) -#define GPIO_FUNC51_IN_SEL_V 0x3F +/** GPIO_FUNC51_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC51_IN_SEL 0x0000003FU +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003FU #define GPIO_FUNC51_IN_SEL_S 0 +/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001U +#define GPIO_SIG51_IN_SEL_S 7 -#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) -/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG52_IN_SEL (BIT(7)) -#define GPIO_SIG52_IN_SEL_M (BIT(7)) -#define GPIO_SIG52_IN_SEL_V 0x1 -#define GPIO_SIG52_IN_SEL_S 7 -/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC52_IN_INV_SEL_V 0x1 -#define GPIO_FUNC52_IN_INV_SEL_S 6 -/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC52_IN_SEL 0x0000003F -#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) -#define GPIO_FUNC52_IN_SEL_V 0x3F +/** GPIO_FUNC52_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC52_IN_SEL 0x0000003FU +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003FU #define GPIO_FUNC52_IN_SEL_S 0 +/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001U +#define GPIO_SIG52_IN_SEL_S 7 -#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) -/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG53_IN_SEL (BIT(7)) -#define GPIO_SIG53_IN_SEL_M (BIT(7)) -#define GPIO_SIG53_IN_SEL_V 0x1 -#define GPIO_SIG53_IN_SEL_S 7 -/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC53_IN_INV_SEL_V 0x1 -#define GPIO_FUNC53_IN_INV_SEL_S 6 -/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC53_IN_SEL 0x0000003F -#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) -#define GPIO_FUNC53_IN_SEL_V 0x3F +/** GPIO_FUNC53_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC53_IN_SEL 0x0000003FU +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003FU #define GPIO_FUNC53_IN_SEL_S 0 +/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001U +#define GPIO_SIG53_IN_SEL_S 7 -#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22C) -/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG54_IN_SEL (BIT(7)) -#define GPIO_SIG54_IN_SEL_M (BIT(7)) -#define GPIO_SIG54_IN_SEL_V 0x1 -#define GPIO_SIG54_IN_SEL_S 7 -/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC54_IN_INV_SEL_V 0x1 -#define GPIO_FUNC54_IN_INV_SEL_S 6 -/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC54_IN_SEL 0x0000003F -#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) -#define GPIO_FUNC54_IN_SEL_V 0x3F +/** GPIO_FUNC54_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) +/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC54_IN_SEL 0x0000003FU +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003FU #define GPIO_FUNC54_IN_SEL_S 0 +/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001U +#define GPIO_SIG54_IN_SEL_S 7 -#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) -/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG55_IN_SEL (BIT(7)) -#define GPIO_SIG55_IN_SEL_M (BIT(7)) -#define GPIO_SIG55_IN_SEL_V 0x1 -#define GPIO_SIG55_IN_SEL_S 7 -/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC55_IN_INV_SEL_V 0x1 -#define GPIO_FUNC55_IN_INV_SEL_S 6 -/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC55_IN_SEL 0x0000003F -#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) -#define GPIO_FUNC55_IN_SEL_V 0x3F +/** GPIO_FUNC55_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC55_IN_SEL 0x0000003FU +#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) +#define GPIO_FUNC55_IN_SEL_V 0x0000003FU #define GPIO_FUNC55_IN_SEL_S 0 +/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) +#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) +#define GPIO_SIG55_IN_SEL_V 0x00000001U +#define GPIO_SIG55_IN_SEL_S 7 -#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) -/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG56_IN_SEL (BIT(7)) -#define GPIO_SIG56_IN_SEL_M (BIT(7)) -#define GPIO_SIG56_IN_SEL_V 0x1 -#define GPIO_SIG56_IN_SEL_S 7 -/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC56_IN_INV_SEL_V 0x1 -#define GPIO_FUNC56_IN_INV_SEL_S 6 -/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC56_IN_SEL 0x0000003F -#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) -#define GPIO_FUNC56_IN_SEL_V 0x3F +/** GPIO_FUNC56_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC56_IN_SEL 0x0000003FU +#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) +#define GPIO_FUNC56_IN_SEL_V 0x0000003FU #define GPIO_FUNC56_IN_SEL_S 0 +/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) +#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) +#define GPIO_SIG56_IN_SEL_V 0x00000001U +#define GPIO_SIG56_IN_SEL_S 7 -#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) -/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG57_IN_SEL (BIT(7)) -#define GPIO_SIG57_IN_SEL_M (BIT(7)) -#define GPIO_SIG57_IN_SEL_V 0x1 -#define GPIO_SIG57_IN_SEL_S 7 -/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC57_IN_INV_SEL_V 0x1 -#define GPIO_FUNC57_IN_INV_SEL_S 6 -/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC57_IN_SEL 0x0000003F -#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) -#define GPIO_FUNC57_IN_SEL_V 0x3F +/** GPIO_FUNC57_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) +/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC57_IN_SEL 0x0000003FU +#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) +#define GPIO_FUNC57_IN_SEL_V 0x0000003FU #define GPIO_FUNC57_IN_SEL_S 0 +/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) +#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC57_IN_INV_SEL_S 6 +/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) +#define GPIO_SIG57_IN_SEL_V 0x00000001U +#define GPIO_SIG57_IN_SEL_S 7 -#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23C) -/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG58_IN_SEL (BIT(7)) -#define GPIO_SIG58_IN_SEL_M (BIT(7)) -#define GPIO_SIG58_IN_SEL_V 0x1 -#define GPIO_SIG58_IN_SEL_S 7 -/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC58_IN_INV_SEL_V 0x1 -#define GPIO_FUNC58_IN_INV_SEL_S 6 -/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC58_IN_SEL 0x0000003F -#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) -#define GPIO_FUNC58_IN_SEL_V 0x3F +/** GPIO_FUNC58_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) +/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC58_IN_SEL 0x0000003FU +#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) +#define GPIO_FUNC58_IN_SEL_V 0x0000003FU #define GPIO_FUNC58_IN_SEL_S 0 +/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) +#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC58_IN_INV_SEL_S 6 +/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) +#define GPIO_SIG58_IN_SEL_V 0x00000001U +#define GPIO_SIG58_IN_SEL_S 7 -#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) -/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG59_IN_SEL (BIT(7)) -#define GPIO_SIG59_IN_SEL_M (BIT(7)) -#define GPIO_SIG59_IN_SEL_V 0x1 -#define GPIO_SIG59_IN_SEL_S 7 -/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC59_IN_INV_SEL_V 0x1 -#define GPIO_FUNC59_IN_INV_SEL_S 6 -/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC59_IN_SEL 0x0000003F -#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) -#define GPIO_FUNC59_IN_SEL_V 0x3F +/** GPIO_FUNC59_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) +/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC59_IN_SEL 0x0000003FU +#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) +#define GPIO_FUNC59_IN_SEL_V 0x0000003FU #define GPIO_FUNC59_IN_SEL_S 0 +/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) +#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC59_IN_INV_SEL_S 6 +/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) +#define GPIO_SIG59_IN_SEL_V 0x00000001U +#define GPIO_SIG59_IN_SEL_S 7 -#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) -/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG60_IN_SEL (BIT(7)) -#define GPIO_SIG60_IN_SEL_M (BIT(7)) -#define GPIO_SIG60_IN_SEL_V 0x1 -#define GPIO_SIG60_IN_SEL_S 7 -/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC60_IN_INV_SEL_V 0x1 -#define GPIO_FUNC60_IN_INV_SEL_S 6 -/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC60_IN_SEL 0x0000003F -#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) -#define GPIO_FUNC60_IN_SEL_V 0x3F +/** GPIO_FUNC60_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) +/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC60_IN_SEL 0x0000003FU +#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) +#define GPIO_FUNC60_IN_SEL_V 0x0000003FU #define GPIO_FUNC60_IN_SEL_S 0 +/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) +#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC60_IN_INV_SEL_S 6 +/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) +#define GPIO_SIG60_IN_SEL_V 0x00000001U +#define GPIO_SIG60_IN_SEL_S 7 -#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) -/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG61_IN_SEL (BIT(7)) -#define GPIO_SIG61_IN_SEL_M (BIT(7)) -#define GPIO_SIG61_IN_SEL_V 0x1 -#define GPIO_SIG61_IN_SEL_S 7 -/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC61_IN_INV_SEL_V 0x1 -#define GPIO_FUNC61_IN_INV_SEL_S 6 -/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC61_IN_SEL 0x0000003F -#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) -#define GPIO_FUNC61_IN_SEL_V 0x3F +/** GPIO_FUNC61_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) +/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC61_IN_SEL 0x0000003FU +#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) +#define GPIO_FUNC61_IN_SEL_V 0x0000003FU #define GPIO_FUNC61_IN_SEL_S 0 +/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) +#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC61_IN_INV_SEL_S 6 +/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) +#define GPIO_SIG61_IN_SEL_V 0x00000001U +#define GPIO_SIG61_IN_SEL_S 7 -#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24C) -/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG62_IN_SEL (BIT(7)) -#define GPIO_SIG62_IN_SEL_M (BIT(7)) -#define GPIO_SIG62_IN_SEL_V 0x1 -#define GPIO_SIG62_IN_SEL_S 7 -/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC62_IN_INV_SEL_V 0x1 -#define GPIO_FUNC62_IN_INV_SEL_S 6 -/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC62_IN_SEL 0x0000003F -#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) -#define GPIO_FUNC62_IN_SEL_V 0x3F +/** GPIO_FUNC62_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) +/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC62_IN_SEL 0x0000003FU +#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) +#define GPIO_FUNC62_IN_SEL_V 0x0000003FU #define GPIO_FUNC62_IN_SEL_S 0 +/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) +#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC62_IN_INV_SEL_S 6 +/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) +#define GPIO_SIG62_IN_SEL_V 0x00000001U +#define GPIO_SIG62_IN_SEL_S 7 -#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) -/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG63_IN_SEL (BIT(7)) -#define GPIO_SIG63_IN_SEL_M (BIT(7)) -#define GPIO_SIG63_IN_SEL_V 0x1 -#define GPIO_SIG63_IN_SEL_S 7 -/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC63_IN_INV_SEL_V 0x1 -#define GPIO_FUNC63_IN_INV_SEL_S 6 -/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC63_IN_SEL 0x0000003F -#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) -#define GPIO_FUNC63_IN_SEL_V 0x3F +/** GPIO_FUNC63_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC63_IN_SEL 0x0000003FU +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003FU #define GPIO_FUNC63_IN_SEL_S 0 +/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001U +#define GPIO_SIG63_IN_SEL_S 7 -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) -/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG64_IN_SEL (BIT(7)) -#define GPIO_SIG64_IN_SEL_M (BIT(7)) -#define GPIO_SIG64_IN_SEL_V 0x1 -#define GPIO_SIG64_IN_SEL_S 7 -/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC64_IN_INV_SEL_V 0x1 -#define GPIO_FUNC64_IN_INV_SEL_S 6 -/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC64_IN_SEL 0x0000003F -#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) -#define GPIO_FUNC64_IN_SEL_V 0x3F +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003FU #define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 7 -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) -/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG65_IN_SEL (BIT(7)) -#define GPIO_SIG65_IN_SEL_M (BIT(7)) -#define GPIO_SIG65_IN_SEL_V 0x1 -#define GPIO_SIG65_IN_SEL_S 7 -/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC65_IN_INV_SEL_V 0x1 -#define GPIO_FUNC65_IN_INV_SEL_S 6 -/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC65_IN_SEL 0x0000003F -#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) -#define GPIO_FUNC65_IN_SEL_V 0x3F +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003FU #define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 7 -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25C) -/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG66_IN_SEL (BIT(7)) -#define GPIO_SIG66_IN_SEL_M (BIT(7)) -#define GPIO_SIG66_IN_SEL_V 0x1 -#define GPIO_SIG66_IN_SEL_S 7 -/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC66_IN_INV_SEL_V 0x1 -#define GPIO_FUNC66_IN_INV_SEL_S 6 -/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC66_IN_SEL 0x0000003F -#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) -#define GPIO_FUNC66_IN_SEL_V 0x3F +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003FU #define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 7 -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) -/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG67_IN_SEL (BIT(7)) -#define GPIO_SIG67_IN_SEL_M (BIT(7)) -#define GPIO_SIG67_IN_SEL_V 0x1 -#define GPIO_SIG67_IN_SEL_S 7 -/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC67_IN_INV_SEL_V 0x1 -#define GPIO_FUNC67_IN_INV_SEL_S 6 -/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC67_IN_SEL 0x0000003F -#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) -#define GPIO_FUNC67_IN_SEL_V 0x3F +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003FU #define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 7 -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) -/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG68_IN_SEL (BIT(7)) -#define GPIO_SIG68_IN_SEL_M (BIT(7)) -#define GPIO_SIG68_IN_SEL_V 0x1 -#define GPIO_SIG68_IN_SEL_S 7 -/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC68_IN_INV_SEL_V 0x1 -#define GPIO_FUNC68_IN_INV_SEL_S 6 -/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC68_IN_SEL 0x0000003F -#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) -#define GPIO_FUNC68_IN_SEL_V 0x3F +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003FU #define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 7 -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) -/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG69_IN_SEL (BIT(7)) -#define GPIO_SIG69_IN_SEL_M (BIT(7)) -#define GPIO_SIG69_IN_SEL_V 0x1 -#define GPIO_SIG69_IN_SEL_S 7 -/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC69_IN_INV_SEL_V 0x1 -#define GPIO_FUNC69_IN_INV_SEL_S 6 -/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC69_IN_SEL 0x0000003F -#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) -#define GPIO_FUNC69_IN_SEL_V 0x3F +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003FU #define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 7 -#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26C) -/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG70_IN_SEL (BIT(7)) -#define GPIO_SIG70_IN_SEL_M (BIT(7)) -#define GPIO_SIG70_IN_SEL_V 0x1 -#define GPIO_SIG70_IN_SEL_S 7 -/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC70_IN_INV_SEL_V 0x1 -#define GPIO_FUNC70_IN_INV_SEL_S 6 -/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC70_IN_SEL 0x0000003F -#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) -#define GPIO_FUNC70_IN_SEL_V 0x3F +/** GPIO_FUNC70_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) +/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC70_IN_SEL 0x0000003FU +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003FU #define GPIO_FUNC70_IN_SEL_S 0 +/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001U +#define GPIO_SIG70_IN_SEL_S 7 -#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) -/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG71_IN_SEL (BIT(7)) -#define GPIO_SIG71_IN_SEL_M (BIT(7)) -#define GPIO_SIG71_IN_SEL_V 0x1 -#define GPIO_SIG71_IN_SEL_S 7 -/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC71_IN_INV_SEL_V 0x1 -#define GPIO_FUNC71_IN_INV_SEL_S 6 -/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC71_IN_SEL 0x0000003F -#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) -#define GPIO_FUNC71_IN_SEL_V 0x3F +/** GPIO_FUNC71_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC71_IN_SEL 0x0000003FU +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003FU #define GPIO_FUNC71_IN_SEL_S 0 +/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001U +#define GPIO_SIG71_IN_SEL_S 7 -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) -/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG72_IN_SEL (BIT(7)) -#define GPIO_SIG72_IN_SEL_M (BIT(7)) -#define GPIO_SIG72_IN_SEL_V 0x1 -#define GPIO_SIG72_IN_SEL_S 7 -/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC72_IN_INV_SEL_V 0x1 -#define GPIO_FUNC72_IN_INV_SEL_S 6 -/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC72_IN_SEL 0x0000003F -#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) -#define GPIO_FUNC72_IN_SEL_V 0x3F +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003FU #define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 7 -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) -/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG73_IN_SEL (BIT(7)) -#define GPIO_SIG73_IN_SEL_M (BIT(7)) -#define GPIO_SIG73_IN_SEL_V 0x1 -#define GPIO_SIG73_IN_SEL_S 7 -/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC73_IN_INV_SEL_V 0x1 -#define GPIO_FUNC73_IN_INV_SEL_S 6 -/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC73_IN_SEL 0x0000003F -#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) -#define GPIO_FUNC73_IN_SEL_V 0x3F +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003FU #define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 7 -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27C) -/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG74_IN_SEL (BIT(7)) -#define GPIO_SIG74_IN_SEL_M (BIT(7)) -#define GPIO_SIG74_IN_SEL_V 0x1 -#define GPIO_SIG74_IN_SEL_S 7 -/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC74_IN_INV_SEL_V 0x1 -#define GPIO_FUNC74_IN_INV_SEL_S 6 -/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC74_IN_SEL 0x0000003F -#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) -#define GPIO_FUNC74_IN_SEL_V 0x3F +/** GPIO_FUNC74_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) +/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC74_IN_SEL 0x0000003FU +#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) +#define GPIO_FUNC74_IN_SEL_V 0x0000003FU #define GPIO_FUNC74_IN_SEL_S 0 +/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) +#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC74_IN_INV_SEL_S 6 +/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) +#define GPIO_SIG74_IN_SEL_V 0x00000001U +#define GPIO_SIG74_IN_SEL_S 7 -#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) -/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG75_IN_SEL (BIT(7)) -#define GPIO_SIG75_IN_SEL_M (BIT(7)) -#define GPIO_SIG75_IN_SEL_V 0x1 -#define GPIO_SIG75_IN_SEL_S 7 -/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC75_IN_INV_SEL_V 0x1 -#define GPIO_FUNC75_IN_INV_SEL_S 6 -/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC75_IN_SEL 0x0000003F -#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) -#define GPIO_FUNC75_IN_SEL_V 0x3F +/** GPIO_FUNC75_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) +/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC75_IN_SEL 0x0000003FU +#define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) +#define GPIO_FUNC75_IN_SEL_V 0x0000003FU #define GPIO_FUNC75_IN_SEL_S 0 +/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) +#define GPIO_FUNC75_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC75_IN_INV_SEL_S 6 +/** GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) +#define GPIO_SIG75_IN_SEL_V 0x00000001U +#define GPIO_SIG75_IN_SEL_S 7 -#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) -/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG76_IN_SEL (BIT(7)) -#define GPIO_SIG76_IN_SEL_M (BIT(7)) -#define GPIO_SIG76_IN_SEL_V 0x1 -#define GPIO_SIG76_IN_SEL_S 7 -/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC76_IN_INV_SEL_V 0x1 -#define GPIO_FUNC76_IN_INV_SEL_S 6 -/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC76_IN_SEL 0x0000003F -#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) -#define GPIO_FUNC76_IN_SEL_V 0x3F +/** GPIO_FUNC76_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) +/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC76_IN_SEL 0x0000003FU +#define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) +#define GPIO_FUNC76_IN_SEL_V 0x0000003FU #define GPIO_FUNC76_IN_SEL_S 0 +/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) +#define GPIO_FUNC76_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC76_IN_INV_SEL_S 6 +/** GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) +#define GPIO_SIG76_IN_SEL_V 0x00000001U +#define GPIO_SIG76_IN_SEL_S 7 -#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) -/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG77_IN_SEL (BIT(7)) -#define GPIO_SIG77_IN_SEL_M (BIT(7)) -#define GPIO_SIG77_IN_SEL_V 0x1 -#define GPIO_SIG77_IN_SEL_S 7 -/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC77_IN_INV_SEL_V 0x1 -#define GPIO_FUNC77_IN_INV_SEL_S 6 -/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC77_IN_SEL 0x0000003F -#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) -#define GPIO_FUNC77_IN_SEL_V 0x3F +/** GPIO_FUNC77_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC77_IN_SEL 0x0000003FU +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000003FU #define GPIO_FUNC77_IN_SEL_S 0 +/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001U +#define GPIO_SIG77_IN_SEL_S 7 -#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28C) -/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG78_IN_SEL (BIT(7)) -#define GPIO_SIG78_IN_SEL_M (BIT(7)) -#define GPIO_SIG78_IN_SEL_V 0x1 -#define GPIO_SIG78_IN_SEL_S 7 -/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC78_IN_INV_SEL_V 0x1 -#define GPIO_FUNC78_IN_INV_SEL_S 6 -/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC78_IN_SEL 0x0000003F -#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) -#define GPIO_FUNC78_IN_SEL_V 0x3F +/** GPIO_FUNC78_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) +/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC78_IN_SEL 0x0000003FU +#define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) +#define GPIO_FUNC78_IN_SEL_V 0x0000003FU #define GPIO_FUNC78_IN_SEL_S 0 +/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) +#define GPIO_FUNC78_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC78_IN_INV_SEL_S 6 +/** GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) +#define GPIO_SIG78_IN_SEL_V 0x00000001U +#define GPIO_SIG78_IN_SEL_S 7 -#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) -/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG79_IN_SEL (BIT(7)) -#define GPIO_SIG79_IN_SEL_M (BIT(7)) -#define GPIO_SIG79_IN_SEL_V 0x1 -#define GPIO_SIG79_IN_SEL_S 7 -/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC79_IN_INV_SEL_V 0x1 -#define GPIO_FUNC79_IN_INV_SEL_S 6 -/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC79_IN_SEL 0x0000003F -#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) -#define GPIO_FUNC79_IN_SEL_V 0x3F +/** GPIO_FUNC79_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) +/** GPIO_FUNC79_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC79_IN_SEL 0x0000003FU +#define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) +#define GPIO_FUNC79_IN_SEL_V 0x0000003FU #define GPIO_FUNC79_IN_SEL_S 0 +/** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) +#define GPIO_FUNC79_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC79_IN_INV_SEL_S 6 +/** GPIO_SIG79_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) +#define GPIO_SIG79_IN_SEL_V 0x00000001U +#define GPIO_SIG79_IN_SEL_S 7 -#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) -/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG80_IN_SEL (BIT(7)) -#define GPIO_SIG80_IN_SEL_M (BIT(7)) -#define GPIO_SIG80_IN_SEL_V 0x1 -#define GPIO_SIG80_IN_SEL_S 7 -/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC80_IN_INV_SEL_V 0x1 -#define GPIO_FUNC80_IN_INV_SEL_S 6 -/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC80_IN_SEL 0x0000003F -#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) -#define GPIO_FUNC80_IN_SEL_V 0x3F +/** GPIO_FUNC80_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) +/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC80_IN_SEL 0x0000003FU +#define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) +#define GPIO_FUNC80_IN_SEL_V 0x0000003FU #define GPIO_FUNC80_IN_SEL_S 0 +/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) +#define GPIO_FUNC80_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC80_IN_INV_SEL_S 6 +/** GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) +#define GPIO_SIG80_IN_SEL_V 0x00000001U +#define GPIO_SIG80_IN_SEL_S 7 -#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) -/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG81_IN_SEL (BIT(7)) -#define GPIO_SIG81_IN_SEL_M (BIT(7)) -#define GPIO_SIG81_IN_SEL_V 0x1 -#define GPIO_SIG81_IN_SEL_S 7 -/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC81_IN_INV_SEL_V 0x1 -#define GPIO_FUNC81_IN_INV_SEL_S 6 -/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC81_IN_SEL 0x0000003F -#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) -#define GPIO_FUNC81_IN_SEL_V 0x3F +/** GPIO_FUNC81_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC81_IN_SEL 0x0000003FU +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003FU #define GPIO_FUNC81_IN_SEL_S 0 +/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001U +#define GPIO_SIG81_IN_SEL_S 7 -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29C) -/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG82_IN_SEL (BIT(7)) -#define GPIO_SIG82_IN_SEL_M (BIT(7)) -#define GPIO_SIG82_IN_SEL_V 0x1 -#define GPIO_SIG82_IN_SEL_S 7 -/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC82_IN_INV_SEL_V 0x1 -#define GPIO_FUNC82_IN_INV_SEL_S 6 -/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC82_IN_SEL 0x0000003F -#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) -#define GPIO_FUNC82_IN_SEL_V 0x3F +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003FU #define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 7 -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A0) -/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG83_IN_SEL (BIT(7)) -#define GPIO_SIG83_IN_SEL_M (BIT(7)) -#define GPIO_SIG83_IN_SEL_V 0x1 -#define GPIO_SIG83_IN_SEL_S 7 -/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC83_IN_INV_SEL_V 0x1 -#define GPIO_FUNC83_IN_INV_SEL_S 6 -/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC83_IN_SEL 0x0000003F -#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) -#define GPIO_FUNC83_IN_SEL_V 0x3F +/** GPIO_FUNC83_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC83_IN_SEL 0x0000003FU +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000003FU #define GPIO_FUNC83_IN_SEL_S 0 +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001U +#define GPIO_SIG83_IN_SEL_S 7 -#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A4) -/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG84_IN_SEL (BIT(7)) -#define GPIO_SIG84_IN_SEL_M (BIT(7)) -#define GPIO_SIG84_IN_SEL_V 0x1 -#define GPIO_SIG84_IN_SEL_S 7 -/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC84_IN_INV_SEL_V 0x1 -#define GPIO_FUNC84_IN_INV_SEL_S 6 -/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC84_IN_SEL 0x0000003F -#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) -#define GPIO_FUNC84_IN_SEL_V 0x3F +/** GPIO_FUNC84_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) +/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC84_IN_SEL 0x0000003FU +#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) +#define GPIO_FUNC84_IN_SEL_V 0x0000003FU #define GPIO_FUNC84_IN_SEL_S 0 +/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) +#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/** GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) +#define GPIO_SIG84_IN_SEL_V 0x00000001U +#define GPIO_SIG84_IN_SEL_S 7 -#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A8) -/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG85_IN_SEL (BIT(7)) -#define GPIO_SIG85_IN_SEL_M (BIT(7)) -#define GPIO_SIG85_IN_SEL_V 0x1 -#define GPIO_SIG85_IN_SEL_S 7 -/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC85_IN_INV_SEL_V 0x1 -#define GPIO_FUNC85_IN_INV_SEL_S 6 -/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC85_IN_SEL 0x0000003F -#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) -#define GPIO_FUNC85_IN_SEL_V 0x3F +/** GPIO_FUNC85_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) +/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC85_IN_SEL 0x0000003FU +#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) +#define GPIO_FUNC85_IN_SEL_V 0x0000003FU #define GPIO_FUNC85_IN_SEL_S 0 +/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) +#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/** GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) +#define GPIO_SIG85_IN_SEL_V 0x00000001U +#define GPIO_SIG85_IN_SEL_S 7 -#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2AC) -/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG86_IN_SEL (BIT(7)) -#define GPIO_SIG86_IN_SEL_M (BIT(7)) -#define GPIO_SIG86_IN_SEL_V 0x1 -#define GPIO_SIG86_IN_SEL_S 7 -/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC86_IN_INV_SEL_V 0x1 -#define GPIO_FUNC86_IN_INV_SEL_S 6 -/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC86_IN_SEL 0x0000003F -#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) -#define GPIO_FUNC86_IN_SEL_V 0x3F +/** GPIO_FUNC86_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) +/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC86_IN_SEL 0x0000003FU +#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) +#define GPIO_FUNC86_IN_SEL_V 0x0000003FU #define GPIO_FUNC86_IN_SEL_S 0 +/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) +#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) +#define GPIO_SIG86_IN_SEL_V 0x00000001U +#define GPIO_SIG86_IN_SEL_S 7 -#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B0) -/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG87_IN_SEL (BIT(7)) -#define GPIO_SIG87_IN_SEL_M (BIT(7)) -#define GPIO_SIG87_IN_SEL_V 0x1 -#define GPIO_SIG87_IN_SEL_S 7 -/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC87_IN_INV_SEL_V 0x1 -#define GPIO_FUNC87_IN_INV_SEL_S 6 -/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC87_IN_SEL 0x0000003F -#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) -#define GPIO_FUNC87_IN_SEL_V 0x3F +/** GPIO_FUNC87_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) +/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC87_IN_SEL 0x0000003FU +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003FU #define GPIO_FUNC87_IN_SEL_S 0 +/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001U +#define GPIO_SIG87_IN_SEL_S 7 -#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B4) -/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG88_IN_SEL (BIT(7)) -#define GPIO_SIG88_IN_SEL_M (BIT(7)) -#define GPIO_SIG88_IN_SEL_V 0x1 -#define GPIO_SIG88_IN_SEL_S 7 -/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC88_IN_INV_SEL_V 0x1 -#define GPIO_FUNC88_IN_INV_SEL_S 6 -/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC88_IN_SEL 0x0000003F -#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) -#define GPIO_FUNC88_IN_SEL_V 0x3F +/** GPIO_FUNC88_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) +/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC88_IN_SEL 0x0000003FU +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003FU #define GPIO_FUNC88_IN_SEL_S 0 +/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001U +#define GPIO_SIG88_IN_SEL_S 7 -#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B8) -/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG89_IN_SEL (BIT(7)) -#define GPIO_SIG89_IN_SEL_M (BIT(7)) -#define GPIO_SIG89_IN_SEL_V 0x1 -#define GPIO_SIG89_IN_SEL_S 7 -/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC89_IN_INV_SEL_V 0x1 -#define GPIO_FUNC89_IN_INV_SEL_S 6 -/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC89_IN_SEL 0x0000003F -#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) -#define GPIO_FUNC89_IN_SEL_V 0x3F +/** GPIO_FUNC89_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) +/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC89_IN_SEL 0x0000003FU +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003FU #define GPIO_FUNC89_IN_SEL_S 0 +/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001U +#define GPIO_SIG89_IN_SEL_S 7 -#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2BC) -/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG90_IN_SEL (BIT(7)) -#define GPIO_SIG90_IN_SEL_M (BIT(7)) -#define GPIO_SIG90_IN_SEL_V 0x1 -#define GPIO_SIG90_IN_SEL_S 7 -/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC90_IN_INV_SEL_V 0x1 -#define GPIO_FUNC90_IN_INV_SEL_S 6 -/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC90_IN_SEL 0x0000003F -#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) -#define GPIO_FUNC90_IN_SEL_V 0x3F +/** GPIO_FUNC90_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) +/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC90_IN_SEL 0x0000003FU +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003FU #define GPIO_FUNC90_IN_SEL_S 0 +/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001U +#define GPIO_SIG90_IN_SEL_S 7 -#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C0) -/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG91_IN_SEL (BIT(7)) -#define GPIO_SIG91_IN_SEL_M (BIT(7)) -#define GPIO_SIG91_IN_SEL_V 0x1 -#define GPIO_SIG91_IN_SEL_S 7 -/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC91_IN_INV_SEL_V 0x1 -#define GPIO_FUNC91_IN_INV_SEL_S 6 -/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC91_IN_SEL 0x0000003F -#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) -#define GPIO_FUNC91_IN_SEL_V 0x3F +/** GPIO_FUNC91_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) +/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC91_IN_SEL 0x0000003FU +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003FU #define GPIO_FUNC91_IN_SEL_S 0 +/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001U +#define GPIO_SIG91_IN_SEL_S 7 -#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C4) -/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG92_IN_SEL (BIT(7)) -#define GPIO_SIG92_IN_SEL_M (BIT(7)) -#define GPIO_SIG92_IN_SEL_V 0x1 -#define GPIO_SIG92_IN_SEL_S 7 -/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC92_IN_INV_SEL_V 0x1 -#define GPIO_FUNC92_IN_INV_SEL_S 6 -/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC92_IN_SEL 0x0000003F -#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) -#define GPIO_FUNC92_IN_SEL_V 0x3F +/** GPIO_FUNC92_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC92_IN_SEL 0x0000003FU +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003FU #define GPIO_FUNC92_IN_SEL_S 0 +/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001U +#define GPIO_SIG92_IN_SEL_S 7 -#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C8) -/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG93_IN_SEL (BIT(7)) -#define GPIO_SIG93_IN_SEL_M (BIT(7)) -#define GPIO_SIG93_IN_SEL_V 0x1 -#define GPIO_SIG93_IN_SEL_S 7 -/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC93_IN_INV_SEL_V 0x1 -#define GPIO_FUNC93_IN_INV_SEL_S 6 -/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC93_IN_SEL 0x0000003F -#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) -#define GPIO_FUNC93_IN_SEL_V 0x3F +/** GPIO_FUNC93_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) +/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC93_IN_SEL 0x0000003FU +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003FU #define GPIO_FUNC93_IN_SEL_S 0 +/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001U +#define GPIO_SIG93_IN_SEL_S 7 -#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2CC) -/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG94_IN_SEL (BIT(7)) -#define GPIO_SIG94_IN_SEL_M (BIT(7)) -#define GPIO_SIG94_IN_SEL_V 0x1 -#define GPIO_SIG94_IN_SEL_S 7 -/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC94_IN_INV_SEL_V 0x1 -#define GPIO_FUNC94_IN_INV_SEL_S 6 -/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC94_IN_SEL 0x0000003F -#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) -#define GPIO_FUNC94_IN_SEL_V 0x3F +/** GPIO_FUNC94_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) +/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC94_IN_SEL 0x0000003FU +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003FU #define GPIO_FUNC94_IN_SEL_S 0 +/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001U +#define GPIO_SIG94_IN_SEL_S 7 -#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D0) -/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG95_IN_SEL (BIT(7)) -#define GPIO_SIG95_IN_SEL_M (BIT(7)) -#define GPIO_SIG95_IN_SEL_V 0x1 -#define GPIO_SIG95_IN_SEL_S 7 -/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC95_IN_INV_SEL_V 0x1 -#define GPIO_FUNC95_IN_INV_SEL_S 6 -/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC95_IN_SEL 0x0000003F -#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) -#define GPIO_FUNC95_IN_SEL_V 0x3F +/** GPIO_FUNC95_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) +/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC95_IN_SEL 0x0000003FU +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003FU #define GPIO_FUNC95_IN_SEL_S 0 +/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001U +#define GPIO_SIG95_IN_SEL_S 7 -#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D4) -/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG96_IN_SEL (BIT(7)) -#define GPIO_SIG96_IN_SEL_M (BIT(7)) -#define GPIO_SIG96_IN_SEL_V 0x1 -#define GPIO_SIG96_IN_SEL_S 7 -/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC96_IN_INV_SEL_V 0x1 -#define GPIO_FUNC96_IN_INV_SEL_S 6 -/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC96_IN_SEL 0x0000003F -#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) -#define GPIO_FUNC96_IN_SEL_V 0x3F +/** GPIO_FUNC96_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) +/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC96_IN_SEL 0x0000003FU +#define GPIO_FUNC96_IN_SEL_M (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S) +#define GPIO_FUNC96_IN_SEL_V 0x0000003FU #define GPIO_FUNC96_IN_SEL_S 0 +/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S) +#define GPIO_FUNC96_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC96_IN_INV_SEL_S 6 +/** GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S) +#define GPIO_SIG96_IN_SEL_V 0x00000001U +#define GPIO_SIG96_IN_SEL_S 7 -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D8) -/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG97_IN_SEL (BIT(7)) -#define GPIO_SIG97_IN_SEL_M (BIT(7)) -#define GPIO_SIG97_IN_SEL_V 0x1 -#define GPIO_SIG97_IN_SEL_S 7 -/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC97_IN_INV_SEL_V 0x1 -#define GPIO_FUNC97_IN_INV_SEL_S 6 -/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC97_IN_SEL 0x0000003F -#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) -#define GPIO_FUNC97_IN_SEL_V 0x3F +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003FU #define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 7 -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2DC) -/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG98_IN_SEL (BIT(7)) -#define GPIO_SIG98_IN_SEL_M (BIT(7)) -#define GPIO_SIG98_IN_SEL_V 0x1 -#define GPIO_SIG98_IN_SEL_S 7 -/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC98_IN_INV_SEL_V 0x1 -#define GPIO_FUNC98_IN_INV_SEL_S 6 -/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC98_IN_SEL 0x0000003F -#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) -#define GPIO_FUNC98_IN_SEL_V 0x3F +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003FU #define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 7 -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E0) -/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG99_IN_SEL (BIT(7)) -#define GPIO_SIG99_IN_SEL_M (BIT(7)) -#define GPIO_SIG99_IN_SEL_V 0x1 -#define GPIO_SIG99_IN_SEL_S 7 -/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC99_IN_INV_SEL_V 0x1 -#define GPIO_FUNC99_IN_INV_SEL_S 6 -/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC99_IN_SEL 0x0000003F -#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) -#define GPIO_FUNC99_IN_SEL_V 0x3F +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003FU #define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 7 -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E4) -/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG100_IN_SEL (BIT(7)) -#define GPIO_SIG100_IN_SEL_M (BIT(7)) -#define GPIO_SIG100_IN_SEL_V 0x1 -#define GPIO_SIG100_IN_SEL_S 7 -/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC100_IN_INV_SEL_V 0x1 -#define GPIO_FUNC100_IN_INV_SEL_S 6 -/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC100_IN_SEL 0x0000003F -#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) -#define GPIO_FUNC100_IN_SEL_V 0x3F +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003FU #define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 7 -#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E8) -/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG101_IN_SEL (BIT(7)) -#define GPIO_SIG101_IN_SEL_M (BIT(7)) -#define GPIO_SIG101_IN_SEL_V 0x1 -#define GPIO_SIG101_IN_SEL_S 7 -/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC101_IN_INV_SEL_V 0x1 -#define GPIO_FUNC101_IN_INV_SEL_S 6 -/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC101_IN_SEL 0x0000003F -#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) -#define GPIO_FUNC101_IN_SEL_V 0x3F +/** GPIO_FUNC101_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC101_IN_SEL 0x0000003FU +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003FU #define GPIO_FUNC101_IN_SEL_S 0 +/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001U +#define GPIO_SIG101_IN_SEL_S 7 -#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2EC) -/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG102_IN_SEL (BIT(7)) -#define GPIO_SIG102_IN_SEL_M (BIT(7)) -#define GPIO_SIG102_IN_SEL_V 0x1 -#define GPIO_SIG102_IN_SEL_S 7 -/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC102_IN_INV_SEL_V 0x1 -#define GPIO_FUNC102_IN_INV_SEL_S 6 -/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC102_IN_SEL 0x0000003F -#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) -#define GPIO_FUNC102_IN_SEL_V 0x3F +/** GPIO_FUNC102_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC102_IN_SEL 0x0000003FU +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003FU #define GPIO_FUNC102_IN_SEL_S 0 +/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001U +#define GPIO_SIG102_IN_SEL_S 7 -#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F0) -/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG103_IN_SEL (BIT(7)) -#define GPIO_SIG103_IN_SEL_M (BIT(7)) -#define GPIO_SIG103_IN_SEL_V 0x1 -#define GPIO_SIG103_IN_SEL_S 7 -/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC103_IN_INV_SEL_V 0x1 -#define GPIO_FUNC103_IN_INV_SEL_S 6 -/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC103_IN_SEL 0x0000003F -#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) -#define GPIO_FUNC103_IN_SEL_V 0x3F +/** GPIO_FUNC103_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC103_IN_SEL 0x0000003FU +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003FU #define GPIO_FUNC103_IN_SEL_S 0 +/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001U +#define GPIO_SIG103_IN_SEL_S 7 -#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F4) -/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG104_IN_SEL (BIT(7)) -#define GPIO_SIG104_IN_SEL_M (BIT(7)) -#define GPIO_SIG104_IN_SEL_V 0x1 -#define GPIO_SIG104_IN_SEL_S 7 -/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC104_IN_INV_SEL_V 0x1 -#define GPIO_FUNC104_IN_INV_SEL_S 6 -/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC104_IN_SEL 0x0000003F -#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) -#define GPIO_FUNC104_IN_SEL_V 0x3F +/** GPIO_FUNC104_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC104_IN_SEL 0x0000003FU +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003FU #define GPIO_FUNC104_IN_SEL_S 0 +/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001U +#define GPIO_SIG104_IN_SEL_S 7 -#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F8) -/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG105_IN_SEL (BIT(7)) -#define GPIO_SIG105_IN_SEL_M (BIT(7)) -#define GPIO_SIG105_IN_SEL_V 0x1 -#define GPIO_SIG105_IN_SEL_S 7 -/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC105_IN_INV_SEL_V 0x1 -#define GPIO_FUNC105_IN_INV_SEL_S 6 -/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC105_IN_SEL 0x0000003F -#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) -#define GPIO_FUNC105_IN_SEL_V 0x3F +/** GPIO_FUNC105_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC105_IN_SEL 0x0000003FU +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003FU #define GPIO_FUNC105_IN_SEL_S 0 +/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001U +#define GPIO_SIG105_IN_SEL_S 7 -#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2FC) -/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG106_IN_SEL (BIT(7)) -#define GPIO_SIG106_IN_SEL_M (BIT(7)) -#define GPIO_SIG106_IN_SEL_V 0x1 -#define GPIO_SIG106_IN_SEL_S 7 -/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC106_IN_INV_SEL_V 0x1 -#define GPIO_FUNC106_IN_INV_SEL_S 6 -/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC106_IN_SEL 0x0000003F -#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) -#define GPIO_FUNC106_IN_SEL_V 0x3F +/** GPIO_FUNC106_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC106_IN_SEL 0x0000003FU +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003FU #define GPIO_FUNC106_IN_SEL_S 0 +/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001U +#define GPIO_SIG106_IN_SEL_S 7 -#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG107_IN_SEL (BIT(7)) -#define GPIO_SIG107_IN_SEL_M (BIT(7)) -#define GPIO_SIG107_IN_SEL_V 0x1 -#define GPIO_SIG107_IN_SEL_S 7 -/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC107_IN_INV_SEL_V 0x1 -#define GPIO_FUNC107_IN_INV_SEL_S 6 -/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC107_IN_SEL 0x0000003F -#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) -#define GPIO_FUNC107_IN_SEL_V 0x3F +/** GPIO_FUNC107_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC107_IN_SEL 0x0000003FU +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003FU #define GPIO_FUNC107_IN_SEL_S 0 +/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001U +#define GPIO_SIG107_IN_SEL_S 7 -#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG108_IN_SEL (BIT(7)) -#define GPIO_SIG108_IN_SEL_M (BIT(7)) -#define GPIO_SIG108_IN_SEL_V 0x1 -#define GPIO_SIG108_IN_SEL_S 7 -/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC108_IN_INV_SEL_V 0x1 -#define GPIO_FUNC108_IN_INV_SEL_S 6 -/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC108_IN_SEL 0x0000003F -#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) -#define GPIO_FUNC108_IN_SEL_V 0x3F +/** GPIO_FUNC108_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC108_IN_SEL 0x0000003FU +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003FU #define GPIO_FUNC108_IN_SEL_S 0 +/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001U +#define GPIO_SIG108_IN_SEL_S 7 -#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG109_IN_SEL (BIT(7)) -#define GPIO_SIG109_IN_SEL_M (BIT(7)) -#define GPIO_SIG109_IN_SEL_V 0x1 -#define GPIO_SIG109_IN_SEL_S 7 -/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC109_IN_INV_SEL_V 0x1 -#define GPIO_FUNC109_IN_INV_SEL_S 6 -/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC109_IN_SEL 0x0000003F -#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) -#define GPIO_FUNC109_IN_SEL_V 0x3F +/** GPIO_FUNC109_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC109_IN_SEL 0x0000003FU +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003FU #define GPIO_FUNC109_IN_SEL_S 0 +/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001U +#define GPIO_SIG109_IN_SEL_S 7 -#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30C) -/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG110_IN_SEL (BIT(7)) -#define GPIO_SIG110_IN_SEL_M (BIT(7)) -#define GPIO_SIG110_IN_SEL_V 0x1 -#define GPIO_SIG110_IN_SEL_S 7 -/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC110_IN_INV_SEL_V 0x1 -#define GPIO_FUNC110_IN_INV_SEL_S 6 -/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC110_IN_SEL 0x0000003F -#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) -#define GPIO_FUNC110_IN_SEL_V 0x3F +/** GPIO_FUNC110_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC110_IN_SEL 0x0000003FU +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003FU #define GPIO_FUNC110_IN_SEL_S 0 +/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001U +#define GPIO_SIG110_IN_SEL_S 7 -#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) -/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG111_IN_SEL (BIT(7)) -#define GPIO_SIG111_IN_SEL_M (BIT(7)) -#define GPIO_SIG111_IN_SEL_V 0x1 -#define GPIO_SIG111_IN_SEL_S 7 -/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC111_IN_INV_SEL_V 0x1 -#define GPIO_FUNC111_IN_INV_SEL_S 6 -/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC111_IN_SEL 0x0000003F -#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) -#define GPIO_FUNC111_IN_SEL_V 0x3F +/** GPIO_FUNC111_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC111_IN_SEL 0x0000003FU +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003FU #define GPIO_FUNC111_IN_SEL_S 0 +/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001U +#define GPIO_SIG111_IN_SEL_S 7 -#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) -/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG112_IN_SEL (BIT(7)) -#define GPIO_SIG112_IN_SEL_M (BIT(7)) -#define GPIO_SIG112_IN_SEL_V 0x1 -#define GPIO_SIG112_IN_SEL_S 7 -/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC112_IN_INV_SEL_V 0x1 -#define GPIO_FUNC112_IN_INV_SEL_S 6 -/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC112_IN_SEL 0x0000003F -#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) -#define GPIO_FUNC112_IN_SEL_V 0x3F +/** GPIO_FUNC112_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC112_IN_SEL 0x0000003FU +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003FU #define GPIO_FUNC112_IN_SEL_S 0 +/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001U +#define GPIO_SIG112_IN_SEL_S 7 -#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) -/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG113_IN_SEL (BIT(7)) -#define GPIO_SIG113_IN_SEL_M (BIT(7)) -#define GPIO_SIG113_IN_SEL_V 0x1 -#define GPIO_SIG113_IN_SEL_S 7 -/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC113_IN_INV_SEL_V 0x1 -#define GPIO_FUNC113_IN_INV_SEL_S 6 -/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC113_IN_SEL 0x0000003F -#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) -#define GPIO_FUNC113_IN_SEL_V 0x3F +/** GPIO_FUNC113_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC113_IN_SEL 0x0000003FU +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003FU #define GPIO_FUNC113_IN_SEL_S 0 +/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001U +#define GPIO_SIG113_IN_SEL_S 7 -#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31C) -/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG114_IN_SEL (BIT(7)) -#define GPIO_SIG114_IN_SEL_M (BIT(7)) -#define GPIO_SIG114_IN_SEL_V 0x1 -#define GPIO_SIG114_IN_SEL_S 7 -/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC114_IN_INV_SEL_V 0x1 -#define GPIO_FUNC114_IN_INV_SEL_S 6 -/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC114_IN_SEL 0x0000003F -#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) -#define GPIO_FUNC114_IN_SEL_V 0x3F +/** GPIO_FUNC114_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) +/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC114_IN_SEL 0x0000003FU +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003FU #define GPIO_FUNC114_IN_SEL_S 0 +/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001U +#define GPIO_SIG114_IN_SEL_S 7 -#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) -/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG115_IN_SEL (BIT(7)) -#define GPIO_SIG115_IN_SEL_M (BIT(7)) -#define GPIO_SIG115_IN_SEL_V 0x1 -#define GPIO_SIG115_IN_SEL_S 7 -/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC115_IN_INV_SEL_V 0x1 -#define GPIO_FUNC115_IN_INV_SEL_S 6 -/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC115_IN_SEL 0x0000003F -#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) -#define GPIO_FUNC115_IN_SEL_V 0x3F +/** GPIO_FUNC115_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC115_IN_SEL 0x0000003FU +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003FU #define GPIO_FUNC115_IN_SEL_S 0 +/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001U +#define GPIO_SIG115_IN_SEL_S 7 -#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) -/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG116_IN_SEL (BIT(7)) -#define GPIO_SIG116_IN_SEL_M (BIT(7)) -#define GPIO_SIG116_IN_SEL_V 0x1 -#define GPIO_SIG116_IN_SEL_S 7 -/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC116_IN_INV_SEL_V 0x1 -#define GPIO_FUNC116_IN_INV_SEL_S 6 -/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC116_IN_SEL 0x0000003F -#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) -#define GPIO_FUNC116_IN_SEL_V 0x3F +/** GPIO_FUNC116_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC116_IN_SEL 0x0000003FU +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003FU #define GPIO_FUNC116_IN_SEL_S 0 +/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001U +#define GPIO_SIG116_IN_SEL_S 7 -#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) -/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG117_IN_SEL (BIT(7)) -#define GPIO_SIG117_IN_SEL_M (BIT(7)) -#define GPIO_SIG117_IN_SEL_V 0x1 -#define GPIO_SIG117_IN_SEL_S 7 -/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC117_IN_INV_SEL_V 0x1 -#define GPIO_FUNC117_IN_INV_SEL_S 6 -/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC117_IN_SEL 0x0000003F -#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) -#define GPIO_FUNC117_IN_SEL_V 0x3F +/** GPIO_FUNC117_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC117_IN_SEL 0x0000003FU +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003FU #define GPIO_FUNC117_IN_SEL_S 0 +/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001U +#define GPIO_SIG117_IN_SEL_S 7 -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32C) -/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG118_IN_SEL (BIT(7)) -#define GPIO_SIG118_IN_SEL_M (BIT(7)) -#define GPIO_SIG118_IN_SEL_V 0x1 -#define GPIO_SIG118_IN_SEL_S 7 -/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC118_IN_INV_SEL_V 0x1 -#define GPIO_FUNC118_IN_INV_SEL_S 6 -/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC118_IN_SEL 0x0000003F -#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) -#define GPIO_FUNC118_IN_SEL_V 0x3F +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003FU #define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 7 -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG119_IN_SEL (BIT(7)) -#define GPIO_SIG119_IN_SEL_M (BIT(7)) -#define GPIO_SIG119_IN_SEL_V 0x1 -#define GPIO_SIG119_IN_SEL_S 7 -/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC119_IN_INV_SEL_V 0x1 -#define GPIO_FUNC119_IN_INV_SEL_S 6 -/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC119_IN_SEL 0x0000003F -#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) -#define GPIO_FUNC119_IN_SEL_V 0x3F +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003FU #define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 7 -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG120_IN_SEL (BIT(7)) -#define GPIO_SIG120_IN_SEL_M (BIT(7)) -#define GPIO_SIG120_IN_SEL_V 0x1 -#define GPIO_SIG120_IN_SEL_S 7 -/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC120_IN_INV_SEL_V 0x1 -#define GPIO_FUNC120_IN_INV_SEL_S 6 -/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC120_IN_SEL 0x0000003F -#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) -#define GPIO_FUNC120_IN_SEL_V 0x3F +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003FU #define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 7 -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG121_IN_SEL (BIT(7)) -#define GPIO_SIG121_IN_SEL_M (BIT(7)) -#define GPIO_SIG121_IN_SEL_V 0x1 -#define GPIO_SIG121_IN_SEL_S 7 -/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC121_IN_INV_SEL_V 0x1 -#define GPIO_FUNC121_IN_INV_SEL_S 6 -/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC121_IN_SEL 0x0000003F -#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) -#define GPIO_FUNC121_IN_SEL_V 0x3F +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003FU #define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 7 -#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33C) -/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG122_IN_SEL (BIT(7)) -#define GPIO_SIG122_IN_SEL_M (BIT(7)) -#define GPIO_SIG122_IN_SEL_V 0x1 -#define GPIO_SIG122_IN_SEL_S 7 -/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC122_IN_INV_SEL_V 0x1 -#define GPIO_FUNC122_IN_INV_SEL_S 6 -/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC122_IN_SEL 0x0000003F -#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) -#define GPIO_FUNC122_IN_SEL_V 0x3F +/** GPIO_FUNC122_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC122_IN_SEL 0x0000003FU +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003FU #define GPIO_FUNC122_IN_SEL_S 0 +/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001U +#define GPIO_SIG122_IN_SEL_S 7 -#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG123_IN_SEL (BIT(7)) -#define GPIO_SIG123_IN_SEL_M (BIT(7)) -#define GPIO_SIG123_IN_SEL_V 0x1 -#define GPIO_SIG123_IN_SEL_S 7 -/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC123_IN_INV_SEL_V 0x1 -#define GPIO_FUNC123_IN_INV_SEL_S 6 -/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC123_IN_SEL 0x0000003F -#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) -#define GPIO_FUNC123_IN_SEL_V 0x3F +/** GPIO_FUNC123_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC123_IN_SEL 0x0000003FU +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003FU #define GPIO_FUNC123_IN_SEL_S 0 +/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001U +#define GPIO_SIG123_IN_SEL_S 7 -#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG124_IN_SEL (BIT(7)) -#define GPIO_SIG124_IN_SEL_M (BIT(7)) -#define GPIO_SIG124_IN_SEL_V 0x1 -#define GPIO_SIG124_IN_SEL_S 7 -/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC124_IN_INV_SEL_V 0x1 -#define GPIO_FUNC124_IN_INV_SEL_S 6 -/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC124_IN_SEL 0x0000003F -#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) -#define GPIO_FUNC124_IN_SEL_V 0x3F +/** GPIO_FUNC124_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC124_IN_SEL 0x0000003FU +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003FU #define GPIO_FUNC124_IN_SEL_S 0 +/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001U +#define GPIO_SIG124_IN_SEL_S 7 -#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG125_IN_SEL (BIT(7)) -#define GPIO_SIG125_IN_SEL_M (BIT(7)) -#define GPIO_SIG125_IN_SEL_V 0x1 -#define GPIO_SIG125_IN_SEL_S 7 -/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC125_IN_INV_SEL_V 0x1 -#define GPIO_FUNC125_IN_INV_SEL_S 6 -/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC125_IN_SEL 0x0000003F -#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) -#define GPIO_FUNC125_IN_SEL_V 0x3F +/** GPIO_FUNC125_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/** GPIO_FUNC125_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC125_IN_SEL 0x0000003FU +#define GPIO_FUNC125_IN_SEL_M (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S) +#define GPIO_FUNC125_IN_SEL_V 0x0000003FU #define GPIO_FUNC125_IN_SEL_S 0 +/** GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S) +#define GPIO_FUNC125_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC125_IN_INV_SEL_S 6 +/** GPIO_SIG125_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S) +#define GPIO_SIG125_IN_SEL_V 0x00000001U +#define GPIO_SIG125_IN_SEL_S 7 -#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34C) -/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG126_IN_SEL (BIT(7)) -#define GPIO_SIG126_IN_SEL_M (BIT(7)) -#define GPIO_SIG126_IN_SEL_V 0x1 -#define GPIO_SIG126_IN_SEL_S 7 -/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC126_IN_INV_SEL_V 0x1 -#define GPIO_FUNC126_IN_INV_SEL_S 6 -/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC126_IN_SEL 0x0000003F -#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) -#define GPIO_FUNC126_IN_SEL_V 0x3F +/** GPIO_FUNC126_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) +/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC126_IN_SEL 0x0000003FU +#define GPIO_FUNC126_IN_SEL_M (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S) +#define GPIO_FUNC126_IN_SEL_V 0x0000003FU #define GPIO_FUNC126_IN_SEL_S 0 +/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S) +#define GPIO_FUNC126_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC126_IN_INV_SEL_S 6 +/** GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S) +#define GPIO_SIG126_IN_SEL_V 0x00000001U +#define GPIO_SIG126_IN_SEL_S 7 -#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SIG127_IN_SEL (BIT(7)) -#define GPIO_SIG127_IN_SEL_M (BIT(7)) -#define GPIO_SIG127_IN_SEL_V 0x1 -#define GPIO_SIG127_IN_SEL_S 7 -/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) -#define GPIO_FUNC127_IN_INV_SEL_V 0x1 -#define GPIO_FUNC127_IN_INV_SEL_S 6 -/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define GPIO_FUNC127_IN_SEL 0x0000003F -#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) -#define GPIO_FUNC127_IN_SEL_V 0x3F +/** GPIO_FUNC127_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC127_IN_SEL 0x0000003FU +#define GPIO_FUNC127_IN_SEL_M (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S) +#define GPIO_FUNC127_IN_SEL_V 0x0000003FU #define GPIO_FUNC127_IN_SEL_S 0 +/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S) +#define GPIO_FUNC127_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC127_IN_INV_SEL_S 6 +/** GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S) +#define GPIO_SIG127_IN_SEL_V 0x00000001U +#define GPIO_SIG127_IN_SEL_S 7 -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) -/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC0_OEN_INV_SEL_S 10 -/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC0_OEN_SEL (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_V 0x1 -#define GPIO_FUNC0_OEN_SEL_S 9 -/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC0_OUT_INV_SEL_S 8 -/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC0_OUT_SEL 0x000000FF -#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) -#define GPIO_FUNC0_OUT_SEL_V 0xFF +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/** GPIO_FUNC0_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC0_OUT_SEL 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU #define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_SEL_S 9 +/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_INV_SEL_S 10 -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) -/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC1_OEN_INV_SEL_S 10 -/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC1_OEN_SEL (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_V 0x1 -#define GPIO_FUNC1_OEN_SEL_S 9 -/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC1_OUT_INV_SEL_S 8 -/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC1_OUT_SEL 0x000000FF -#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) -#define GPIO_FUNC1_OUT_SEL_V 0xFF +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/** GPIO_FUNC1_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC1_OUT_SEL 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU #define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_SEL_S 9 +/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_INV_SEL_S 10 -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55C) -/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC2_OEN_INV_SEL_S 10 -/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC2_OEN_SEL (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_V 0x1 -#define GPIO_FUNC2_OEN_SEL_S 9 -/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC2_OUT_INV_SEL_S 8 -/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC2_OUT_SEL 0x000000FF -#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) -#define GPIO_FUNC2_OUT_SEL_V 0xFF +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) +/** GPIO_FUNC2_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC2_OUT_SEL 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU #define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_SEL_S 9 +/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_INV_SEL_S 10 -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) -/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC3_OEN_INV_SEL_S 10 -/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC3_OEN_SEL (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_V 0x1 -#define GPIO_FUNC3_OEN_SEL_S 9 -/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC3_OUT_INV_SEL_S 8 -/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC3_OUT_SEL 0x000000FF -#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) -#define GPIO_FUNC3_OUT_SEL_V 0xFF +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/** GPIO_FUNC3_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC3_OUT_SEL 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU #define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_SEL_S 9 +/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_INV_SEL_S 10 -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) -/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC4_OEN_INV_SEL_S 10 -/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC4_OEN_SEL (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_V 0x1 -#define GPIO_FUNC4_OEN_SEL_S 9 -/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC4_OUT_INV_SEL_S 8 -/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC4_OUT_SEL 0x000000FF -#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) -#define GPIO_FUNC4_OUT_SEL_V 0xFF +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/** GPIO_FUNC4_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC4_OUT_SEL 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU #define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_SEL_S 9 +/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_INV_SEL_S 10 -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) -/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC5_OEN_INV_SEL_S 10 -/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC5_OEN_SEL (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_V 0x1 -#define GPIO_FUNC5_OEN_SEL_S 9 -/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC5_OUT_INV_SEL_S 8 -/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC5_OUT_SEL 0x000000FF -#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) -#define GPIO_FUNC5_OUT_SEL_V 0xFF +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/** GPIO_FUNC5_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC5_OUT_SEL 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU #define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_SEL_S 9 +/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_INV_SEL_S 10 -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56C) -/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC6_OEN_INV_SEL_S 10 -/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC6_OEN_SEL (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_V 0x1 -#define GPIO_FUNC6_OEN_SEL_S 9 -/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC6_OUT_INV_SEL_S 8 -/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC6_OUT_SEL 0x000000FF -#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) -#define GPIO_FUNC6_OUT_SEL_V 0xFF +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) +/** GPIO_FUNC6_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC6_OUT_SEL 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU #define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_SEL_S 9 +/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_INV_SEL_S 10 -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) -/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC7_OEN_INV_SEL_S 10 -/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC7_OEN_SEL (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_V 0x1 -#define GPIO_FUNC7_OEN_SEL_S 9 -/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC7_OUT_INV_SEL_S 8 -/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC7_OUT_SEL 0x000000FF -#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) -#define GPIO_FUNC7_OUT_SEL_V 0xFF +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/** GPIO_FUNC7_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC7_OUT_SEL 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU #define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_SEL_S 9 +/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_INV_SEL_S 10 -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) -/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC8_OEN_INV_SEL_S 10 -/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC8_OEN_SEL (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_V 0x1 -#define GPIO_FUNC8_OEN_SEL_S 9 -/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC8_OUT_INV_SEL_S 8 -/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC8_OUT_SEL 0x000000FF -#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) -#define GPIO_FUNC8_OUT_SEL_V 0xFF +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/** GPIO_FUNC8_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC8_OUT_SEL 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU #define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_SEL_S 9 +/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_INV_SEL_S 10 -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) -/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC9_OEN_INV_SEL_S 10 -/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC9_OEN_SEL (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_V 0x1 -#define GPIO_FUNC9_OEN_SEL_S 9 -/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC9_OUT_INV_SEL_S 8 -/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC9_OUT_SEL 0x000000FF -#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) -#define GPIO_FUNC9_OUT_SEL_V 0xFF +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/** GPIO_FUNC9_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC9_OUT_SEL 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU #define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_SEL_S 9 +/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_INV_SEL_S 10 -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57C) -/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC10_OEN_INV_SEL_S 10 -/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC10_OEN_SEL (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_V 0x1 -#define GPIO_FUNC10_OEN_SEL_S 9 -/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC10_OUT_INV_SEL_S 8 -/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC10_OUT_SEL 0x000000FF -#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) -#define GPIO_FUNC10_OUT_SEL_V 0xFF +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) +/** GPIO_FUNC10_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC10_OUT_SEL 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU #define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_SEL_S 9 +/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_INV_SEL_S 10 -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) -/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC11_OEN_INV_SEL_S 10 -/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC11_OEN_SEL (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_V 0x1 -#define GPIO_FUNC11_OEN_SEL_S 9 -/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC11_OUT_INV_SEL_S 8 -/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC11_OUT_SEL 0x000000FF -#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) -#define GPIO_FUNC11_OUT_SEL_V 0xFF +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/** GPIO_FUNC11_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC11_OUT_SEL 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU #define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_SEL_S 9 +/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_INV_SEL_S 10 -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) -/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC12_OEN_INV_SEL_S 10 -/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC12_OEN_SEL (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_V 0x1 -#define GPIO_FUNC12_OEN_SEL_S 9 -/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC12_OUT_INV_SEL_S 8 -/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC12_OUT_SEL 0x000000FF -#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) -#define GPIO_FUNC12_OUT_SEL_V 0xFF +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/** GPIO_FUNC12_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC12_OUT_SEL 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU #define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_SEL_S 9 +/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_INV_SEL_S 10 -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) -/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC13_OEN_INV_SEL_S 10 -/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC13_OEN_SEL (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_V 0x1 -#define GPIO_FUNC13_OEN_SEL_S 9 -/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC13_OUT_INV_SEL_S 8 -/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC13_OUT_SEL 0x000000FF -#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) -#define GPIO_FUNC13_OUT_SEL_V 0xFF +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/** GPIO_FUNC13_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC13_OUT_SEL 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU #define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_SEL_S 9 +/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_INV_SEL_S 10 -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58C) -/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC14_OEN_INV_SEL_S 10 -/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC14_OEN_SEL (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_V 0x1 -#define GPIO_FUNC14_OEN_SEL_S 9 -/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC14_OUT_INV_SEL_S 8 -/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC14_OUT_SEL 0x000000FF -#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) -#define GPIO_FUNC14_OUT_SEL_V 0xFF +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) +/** GPIO_FUNC14_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC14_OUT_SEL 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU #define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_SEL_S 9 +/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_INV_SEL_S 10 -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) -/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC15_OEN_INV_SEL_S 10 -/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC15_OEN_SEL (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_V 0x1 -#define GPIO_FUNC15_OEN_SEL_S 9 -/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC15_OUT_INV_SEL_S 8 -/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC15_OUT_SEL 0x000000FF -#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) -#define GPIO_FUNC15_OUT_SEL_V 0xFF +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/** GPIO_FUNC15_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC15_OUT_SEL 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU #define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_SEL_S 9 +/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_INV_SEL_S 10 -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) -/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC16_OEN_INV_SEL_S 10 -/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC16_OEN_SEL (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_V 0x1 -#define GPIO_FUNC16_OEN_SEL_S 9 -/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC16_OUT_INV_SEL_S 8 -/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC16_OUT_SEL 0x000000FF -#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) -#define GPIO_FUNC16_OUT_SEL_V 0xFF +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/** GPIO_FUNC16_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC16_OUT_SEL 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU #define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_SEL_S 9 +/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_INV_SEL_S 10 -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) -/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC17_OEN_INV_SEL_S 10 -/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC17_OEN_SEL (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_V 0x1 -#define GPIO_FUNC17_OEN_SEL_S 9 -/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC17_OUT_INV_SEL_S 8 -/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC17_OUT_SEL 0x000000FF -#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) -#define GPIO_FUNC17_OUT_SEL_V 0xFF +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/** GPIO_FUNC17_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC17_OUT_SEL 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU #define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_SEL_S 9 +/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_INV_SEL_S 10 -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59C) -/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC18_OEN_INV_SEL_S 10 -/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC18_OEN_SEL (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_V 0x1 -#define GPIO_FUNC18_OEN_SEL_S 9 -/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC18_OUT_INV_SEL_S 8 -/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC18_OUT_SEL 0x000000FF -#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) -#define GPIO_FUNC18_OUT_SEL_V 0xFF +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) +/** GPIO_FUNC18_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC18_OUT_SEL 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU #define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_SEL_S 9 +/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_INV_SEL_S 10 -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A0) -/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC19_OEN_INV_SEL_S 10 -/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC19_OEN_SEL (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_V 0x1 -#define GPIO_FUNC19_OEN_SEL_S 9 -/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC19_OUT_INV_SEL_S 8 -/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC19_OUT_SEL 0x000000FF -#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) -#define GPIO_FUNC19_OUT_SEL_V 0xFF +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) +/** GPIO_FUNC19_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC19_OUT_SEL 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU #define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_SEL_S 9 +/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_INV_SEL_S 10 -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A4) -/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC20_OEN_INV_SEL_S 10 -/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC20_OEN_SEL (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_V 0x1 -#define GPIO_FUNC20_OEN_SEL_S 9 -/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC20_OUT_INV_SEL_S 8 -/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC20_OUT_SEL 0x000000FF -#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) -#define GPIO_FUNC20_OUT_SEL_V 0xFF +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) +/** GPIO_FUNC20_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC20_OUT_SEL 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU #define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_SEL_S 9 +/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_INV_SEL_S 10 -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A8) -/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC21_OEN_INV_SEL_S 10 -/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC21_OEN_SEL (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_V 0x1 -#define GPIO_FUNC21_OEN_SEL_S 9 -/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC21_OUT_INV_SEL_S 8 -/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC21_OUT_SEL 0x000000FF -#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) -#define GPIO_FUNC21_OUT_SEL_V 0xFF +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) +/** GPIO_FUNC21_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC21_OUT_SEL 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU #define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_SEL_S 9 +/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_INV_SEL_S 10 -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5AC) -/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC22_OEN_INV_SEL_S 10 -/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC22_OEN_SEL (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_V 0x1 -#define GPIO_FUNC22_OEN_SEL_S 9 -/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC22_OUT_INV_SEL_S 8 -/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC22_OUT_SEL 0x000000FF -#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) -#define GPIO_FUNC22_OUT_SEL_V 0xFF +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) +/** GPIO_FUNC22_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC22_OUT_SEL 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU #define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_SEL_S 9 +/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_INV_SEL_S 10 -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B0) -/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC23_OEN_INV_SEL_S 10 -/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC23_OEN_SEL (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_V 0x1 -#define GPIO_FUNC23_OEN_SEL_S 9 -/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC23_OUT_INV_SEL_S 8 -/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC23_OUT_SEL 0x000000FF -#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) -#define GPIO_FUNC23_OUT_SEL_V 0xFF +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) +/** GPIO_FUNC23_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC23_OUT_SEL 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU #define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_SEL_S 9 +/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_INV_SEL_S 10 -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B4) -/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC24_OEN_INV_SEL_S 10 -/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC24_OEN_SEL (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_V 0x1 -#define GPIO_FUNC24_OEN_SEL_S 9 -/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC24_OUT_INV_SEL_S 8 -/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC24_OUT_SEL 0x000000FF -#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) -#define GPIO_FUNC24_OUT_SEL_V 0xFF +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) +/** GPIO_FUNC24_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC24_OUT_SEL 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU #define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_SEL_S 9 +/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_INV_SEL_S 10 -#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B8) -/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC25_OEN_INV_SEL_S 10 -/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC25_OEN_SEL (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_V 0x1 -#define GPIO_FUNC25_OEN_SEL_S 9 -/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC25_OUT_INV_SEL_S 8 -/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC25_OUT_SEL 0x000000FF -#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) -#define GPIO_FUNC25_OUT_SEL_V 0xFF +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) +/** GPIO_FUNC25_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU #define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_SEL_S 9 +/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_INV_SEL_S 10 -#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5BC) -/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC26_OEN_INV_SEL_S 10 -/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC26_OEN_SEL (BIT(9)) -#define GPIO_FUNC26_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC26_OEN_SEL_V 0x1 -#define GPIO_FUNC26_OEN_SEL_S 9 -/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC26_OUT_INV_SEL_S 8 -/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC26_OUT_SEL 0x000000FF -#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) -#define GPIO_FUNC26_OUT_SEL_V 0xFF +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) +/** GPIO_FUNC26_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU #define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_SEL_S 9 +/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_INV_SEL_S 10 -#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C0) -/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC27_OEN_INV_SEL_S 10 -/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC27_OEN_SEL (BIT(9)) -#define GPIO_FUNC27_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC27_OEN_SEL_V 0x1 -#define GPIO_FUNC27_OEN_SEL_S 9 -/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC27_OUT_INV_SEL_S 8 -/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC27_OUT_SEL 0x000000FF -#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) -#define GPIO_FUNC27_OUT_SEL_V 0xFF +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) +/** GPIO_FUNC27_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU #define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_SEL_S 9 +/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_INV_SEL_S 10 -#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C4) -/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC28_OEN_INV_SEL_S 10 -/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC28_OEN_SEL (BIT(9)) -#define GPIO_FUNC28_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC28_OEN_SEL_V 0x1 -#define GPIO_FUNC28_OEN_SEL_S 9 -/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC28_OUT_INV_SEL_S 8 -/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC28_OUT_SEL 0x000000FF -#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) -#define GPIO_FUNC28_OUT_SEL_V 0xFF +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) +/** GPIO_FUNC28_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU #define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_SEL_S 9 +/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_INV_SEL_S 10 -#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C8) -/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC29_OEN_INV_SEL_S 10 -/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC29_OEN_SEL (BIT(9)) -#define GPIO_FUNC29_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC29_OEN_SEL_V 0x1 -#define GPIO_FUNC29_OEN_SEL_S 9 -/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC29_OUT_INV_SEL_S 8 -/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC29_OUT_SEL 0x000000FF -#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) -#define GPIO_FUNC29_OUT_SEL_V 0xFF +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) +/** GPIO_FUNC29_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU #define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_SEL_S 9 +/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_INV_SEL_S 10 -#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5CC) -/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC30_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC30_OEN_INV_SEL_S 10 -/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC30_OEN_SEL (BIT(9)) -#define GPIO_FUNC30_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC30_OEN_SEL_V 0x1 -#define GPIO_FUNC30_OEN_SEL_S 9 -/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC30_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC30_OUT_INV_SEL_S 8 -/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC30_OUT_SEL 0x000000FF -#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) -#define GPIO_FUNC30_OUT_SEL_V 0xFF +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) +/** GPIO_FUNC30_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000000FFU #define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 8 +/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OEN_SEL (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_SEL_S 9 +/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_INV_SEL_S 10 -#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D0) -/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC31_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC31_OEN_INV_SEL_S 10 -/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC31_OEN_SEL (BIT(9)) -#define GPIO_FUNC31_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC31_OEN_SEL_V 0x1 -#define GPIO_FUNC31_OEN_SEL_S 9 -/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC31_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC31_OUT_INV_SEL_S 8 -/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC31_OUT_SEL 0x000000FF -#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) -#define GPIO_FUNC31_OUT_SEL_V 0xFF +/** GPIO_FUNC31_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) +/** GPIO_FUNC31_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC31_OUT_SEL 0x000000FFU +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000000FFU #define GPIO_FUNC31_OUT_SEL_S 0 +/** GPIO_FUNC31_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OUT_INV_SEL_S 8 +/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC31_OEN_SEL (BIT(9)) +#define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) +#define GPIO_FUNC31_OEN_SEL_V 0x00000001U +#define GPIO_FUNC31_OEN_SEL_S 9 +/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OEN_INV_SEL_S 10 -#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D4) -/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC32_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC32_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC32_OEN_INV_SEL_S 10 -/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC32_OEN_SEL (BIT(9)) -#define GPIO_FUNC32_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC32_OEN_SEL_V 0x1 -#define GPIO_FUNC32_OEN_SEL_S 9 -/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC32_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC32_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC32_OUT_INV_SEL_S 8 -/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC32_OUT_SEL 0x000000FF -#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) -#define GPIO_FUNC32_OUT_SEL_V 0xFF +/** GPIO_FUNC32_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4) +/** GPIO_FUNC32_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC32_OUT_SEL 0x000000FFU +#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) +#define GPIO_FUNC32_OUT_SEL_V 0x000000FFU #define GPIO_FUNC32_OUT_SEL_S 0 +/** GPIO_FUNC32_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OUT_INV_SEL_S 8 +/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC32_OEN_SEL (BIT(9)) +#define GPIO_FUNC32_OEN_SEL_M (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S) +#define GPIO_FUNC32_OEN_SEL_V 0x00000001U +#define GPIO_FUNC32_OEN_SEL_S 9 +/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_INV_SEL_M (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OEN_INV_SEL_S 10 -#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D8) -/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC33_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC33_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC33_OEN_INV_SEL_S 10 -/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC33_OEN_SEL (BIT(9)) -#define GPIO_FUNC33_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC33_OEN_SEL_V 0x1 -#define GPIO_FUNC33_OEN_SEL_S 9 -/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC33_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC33_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC33_OUT_INV_SEL_S 8 -/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC33_OUT_SEL 0x000000FF -#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) -#define GPIO_FUNC33_OUT_SEL_V 0xFF +/** GPIO_FUNC33_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8) +/** GPIO_FUNC33_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC33_OUT_SEL 0x000000FFU +#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) +#define GPIO_FUNC33_OUT_SEL_V 0x000000FFU #define GPIO_FUNC33_OUT_SEL_S 0 +/** GPIO_FUNC33_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OUT_INV_SEL_S 8 +/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC33_OEN_SEL (BIT(9)) +#define GPIO_FUNC33_OEN_SEL_M (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S) +#define GPIO_FUNC33_OEN_SEL_V 0x00000001U +#define GPIO_FUNC33_OEN_SEL_S 9 +/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_INV_SEL_M (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OEN_INV_SEL_S 10 -#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5DC) -/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC34_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC34_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC34_OEN_INV_SEL_S 10 -/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC34_OEN_SEL (BIT(9)) -#define GPIO_FUNC34_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC34_OEN_SEL_V 0x1 -#define GPIO_FUNC34_OEN_SEL_S 9 -/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC34_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC34_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC34_OUT_INV_SEL_S 8 -/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC34_OUT_SEL 0x000000FF -#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) -#define GPIO_FUNC34_OUT_SEL_V 0xFF +/** GPIO_FUNC34_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc) +/** GPIO_FUNC34_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC34_OUT_SEL 0x000000FFU +#define GPIO_FUNC34_OUT_SEL_M (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S) +#define GPIO_FUNC34_OUT_SEL_V 0x000000FFU #define GPIO_FUNC34_OUT_SEL_S 0 +/** GPIO_FUNC34_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC34_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC34_OUT_INV_SEL_M (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_OUT_INV_SEL_S 8 +/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC34_OEN_SEL (BIT(9)) +#define GPIO_FUNC34_OEN_SEL_M (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S) +#define GPIO_FUNC34_OEN_SEL_V 0x00000001U +#define GPIO_FUNC34_OEN_SEL_S 9 +/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC34_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_INV_SEL_M (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_OEN_INV_SEL_S 10 -#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E0) -/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC35_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC35_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC35_OEN_INV_SEL_S 10 -/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC35_OEN_SEL (BIT(9)) -#define GPIO_FUNC35_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC35_OEN_SEL_V 0x1 -#define GPIO_FUNC35_OEN_SEL_S 9 -/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC35_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC35_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC35_OUT_INV_SEL_S 8 -/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC35_OUT_SEL 0x000000FF -#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) -#define GPIO_FUNC35_OUT_SEL_V 0xFF +/** GPIO_FUNC35_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0) +/** GPIO_FUNC35_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC35_OUT_SEL 0x000000FFU +#define GPIO_FUNC35_OUT_SEL_M (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S) +#define GPIO_FUNC35_OUT_SEL_V 0x000000FFU #define GPIO_FUNC35_OUT_SEL_S 0 +/** GPIO_FUNC35_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC35_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC35_OUT_INV_SEL_M (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_OUT_INV_SEL_S 8 +/** GPIO_FUNC35_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC35_OEN_SEL (BIT(9)) +#define GPIO_FUNC35_OEN_SEL_M (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S) +#define GPIO_FUNC35_OEN_SEL_V 0x00000001U +#define GPIO_FUNC35_OEN_SEL_S 9 +/** GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC35_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_INV_SEL_M (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_OEN_INV_SEL_S 10 -#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E4) -/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC36_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC36_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC36_OEN_INV_SEL_S 10 -/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC36_OEN_SEL (BIT(9)) -#define GPIO_FUNC36_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC36_OEN_SEL_V 0x1 -#define GPIO_FUNC36_OEN_SEL_S 9 -/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC36_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC36_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC36_OUT_INV_SEL_S 8 -/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC36_OUT_SEL 0x000000FF -#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) -#define GPIO_FUNC36_OUT_SEL_V 0xFF +/** GPIO_FUNC36_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4) +/** GPIO_FUNC36_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC36_OUT_SEL 0x000000FFU +#define GPIO_FUNC36_OUT_SEL_M (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S) +#define GPIO_FUNC36_OUT_SEL_V 0x000000FFU #define GPIO_FUNC36_OUT_SEL_S 0 +/** GPIO_FUNC36_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC36_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC36_OUT_INV_SEL_M (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC36_OUT_INV_SEL_S 8 +/** GPIO_FUNC36_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC36_OEN_SEL (BIT(9)) +#define GPIO_FUNC36_OEN_SEL_M (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S) +#define GPIO_FUNC36_OEN_SEL_V 0x00000001U +#define GPIO_FUNC36_OEN_SEL_S 9 +/** GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC36_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_INV_SEL_M (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC36_OEN_INV_SEL_S 10 -#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E8) -/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC37_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC37_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC37_OEN_INV_SEL_S 10 -/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC37_OEN_SEL (BIT(9)) -#define GPIO_FUNC37_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC37_OEN_SEL_V 0x1 -#define GPIO_FUNC37_OEN_SEL_S 9 -/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC37_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC37_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC37_OUT_INV_SEL_S 8 -/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC37_OUT_SEL 0x000000FF -#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) -#define GPIO_FUNC37_OUT_SEL_V 0xFF +/** GPIO_FUNC37_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8) +/** GPIO_FUNC37_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC37_OUT_SEL 0x000000FFU +#define GPIO_FUNC37_OUT_SEL_M (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S) +#define GPIO_FUNC37_OUT_SEL_V 0x000000FFU #define GPIO_FUNC37_OUT_SEL_S 0 +/** GPIO_FUNC37_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC37_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC37_OUT_INV_SEL_M (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC37_OUT_INV_SEL_S 8 +/** GPIO_FUNC37_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC37_OEN_SEL (BIT(9)) +#define GPIO_FUNC37_OEN_SEL_M (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S) +#define GPIO_FUNC37_OEN_SEL_V 0x00000001U +#define GPIO_FUNC37_OEN_SEL_S 9 +/** GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC37_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_INV_SEL_M (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC37_OEN_INV_SEL_S 10 -#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5EC) -/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC38_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC38_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC38_OEN_INV_SEL_S 10 -/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC38_OEN_SEL (BIT(9)) -#define GPIO_FUNC38_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC38_OEN_SEL_V 0x1 -#define GPIO_FUNC38_OEN_SEL_S 9 -/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC38_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC38_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC38_OUT_INV_SEL_S 8 -/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC38_OUT_SEL 0x000000FF -#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) -#define GPIO_FUNC38_OUT_SEL_V 0xFF +/** GPIO_FUNC38_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec) +/** GPIO_FUNC38_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC38_OUT_SEL 0x000000FFU +#define GPIO_FUNC38_OUT_SEL_M (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S) +#define GPIO_FUNC38_OUT_SEL_V 0x000000FFU #define GPIO_FUNC38_OUT_SEL_S 0 +/** GPIO_FUNC38_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC38_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC38_OUT_INV_SEL_M (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC38_OUT_INV_SEL_S 8 +/** GPIO_FUNC38_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC38_OEN_SEL (BIT(9)) +#define GPIO_FUNC38_OEN_SEL_M (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S) +#define GPIO_FUNC38_OEN_SEL_V 0x00000001U +#define GPIO_FUNC38_OEN_SEL_S 9 +/** GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC38_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_INV_SEL_M (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC38_OEN_INV_SEL_S 10 -#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F0) -/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC39_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC39_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC39_OEN_INV_SEL_S 10 -/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC39_OEN_SEL (BIT(9)) -#define GPIO_FUNC39_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC39_OEN_SEL_V 0x1 -#define GPIO_FUNC39_OEN_SEL_S 9 -/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC39_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC39_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC39_OUT_INV_SEL_S 8 -/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC39_OUT_SEL 0x000000FF -#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) -#define GPIO_FUNC39_OUT_SEL_V 0xFF +/** GPIO_FUNC39_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0) +/** GPIO_FUNC39_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC39_OUT_SEL 0x000000FFU +#define GPIO_FUNC39_OUT_SEL_M (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S) +#define GPIO_FUNC39_OUT_SEL_V 0x000000FFU #define GPIO_FUNC39_OUT_SEL_S 0 +/** GPIO_FUNC39_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC39_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC39_OUT_INV_SEL_M (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC39_OUT_INV_SEL_S 8 +/** GPIO_FUNC39_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC39_OEN_SEL (BIT(9)) +#define GPIO_FUNC39_OEN_SEL_M (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S) +#define GPIO_FUNC39_OEN_SEL_V 0x00000001U +#define GPIO_FUNC39_OEN_SEL_S 9 +/** GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC39_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_INV_SEL_M (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC39_OEN_INV_SEL_S 10 -#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F4) -/* GPIO_FUNC40_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC40_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC40_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC40_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC40_OEN_INV_SEL_S 10 -/* GPIO_FUNC40_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC40_OEN_SEL (BIT(9)) -#define GPIO_FUNC40_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC40_OEN_SEL_V 0x1 -#define GPIO_FUNC40_OEN_SEL_S 9 -/* GPIO_FUNC40_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC40_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC40_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC40_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC40_OUT_INV_SEL_S 8 -/* GPIO_FUNC40_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC40_OUT_SEL 0x000000FF -#define GPIO_FUNC40_OUT_SEL_M ((GPIO_FUNC40_OUT_SEL_V)<<(GPIO_FUNC40_OUT_SEL_S)) -#define GPIO_FUNC40_OUT_SEL_V 0xFF +/** GPIO_FUNC40_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4) +/** GPIO_FUNC40_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC40_OUT_SEL 0x000000FFU +#define GPIO_FUNC40_OUT_SEL_M (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S) +#define GPIO_FUNC40_OUT_SEL_V 0x000000FFU #define GPIO_FUNC40_OUT_SEL_S 0 +/** GPIO_FUNC40_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC40_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC40_OUT_INV_SEL_M (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S) +#define GPIO_FUNC40_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_OUT_INV_SEL_S 8 +/** GPIO_FUNC40_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC40_OEN_SEL (BIT(9)) +#define GPIO_FUNC40_OEN_SEL_M (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S) +#define GPIO_FUNC40_OEN_SEL_V 0x00000001U +#define GPIO_FUNC40_OEN_SEL_S 9 +/** GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC40_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC40_OEN_INV_SEL_M (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S) +#define GPIO_FUNC40_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_OEN_INV_SEL_S 10 -#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F8) -/* GPIO_FUNC41_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC41_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC41_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC41_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC41_OEN_INV_SEL_S 10 -/* GPIO_FUNC41_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC41_OEN_SEL (BIT(9)) -#define GPIO_FUNC41_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC41_OEN_SEL_V 0x1 -#define GPIO_FUNC41_OEN_SEL_S 9 -/* GPIO_FUNC41_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC41_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC41_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC41_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC41_OUT_INV_SEL_S 8 -/* GPIO_FUNC41_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC41_OUT_SEL 0x000000FF -#define GPIO_FUNC41_OUT_SEL_M ((GPIO_FUNC41_OUT_SEL_V)<<(GPIO_FUNC41_OUT_SEL_S)) -#define GPIO_FUNC41_OUT_SEL_V 0xFF +/** GPIO_FUNC41_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8) +/** GPIO_FUNC41_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC41_OUT_SEL 0x000000FFU +#define GPIO_FUNC41_OUT_SEL_M (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S) +#define GPIO_FUNC41_OUT_SEL_V 0x000000FFU #define GPIO_FUNC41_OUT_SEL_S 0 +/** GPIO_FUNC41_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC41_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC41_OUT_INV_SEL_M (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S) +#define GPIO_FUNC41_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_OUT_INV_SEL_S 8 +/** GPIO_FUNC41_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC41_OEN_SEL (BIT(9)) +#define GPIO_FUNC41_OEN_SEL_M (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S) +#define GPIO_FUNC41_OEN_SEL_V 0x00000001U +#define GPIO_FUNC41_OEN_SEL_S 9 +/** GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC41_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC41_OEN_INV_SEL_M (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S) +#define GPIO_FUNC41_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_OEN_INV_SEL_S 10 -#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5FC) -/* GPIO_FUNC42_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC42_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC42_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC42_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC42_OEN_INV_SEL_S 10 -/* GPIO_FUNC42_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC42_OEN_SEL (BIT(9)) -#define GPIO_FUNC42_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC42_OEN_SEL_V 0x1 -#define GPIO_FUNC42_OEN_SEL_S 9 -/* GPIO_FUNC42_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC42_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC42_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC42_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC42_OUT_INV_SEL_S 8 -/* GPIO_FUNC42_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC42_OUT_SEL 0x000000FF -#define GPIO_FUNC42_OUT_SEL_M ((GPIO_FUNC42_OUT_SEL_V)<<(GPIO_FUNC42_OUT_SEL_S)) -#define GPIO_FUNC42_OUT_SEL_V 0xFF +/** GPIO_FUNC42_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc) +/** GPIO_FUNC42_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC42_OUT_SEL 0x000000FFU +#define GPIO_FUNC42_OUT_SEL_M (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S) +#define GPIO_FUNC42_OUT_SEL_V 0x000000FFU #define GPIO_FUNC42_OUT_SEL_S 0 +/** GPIO_FUNC42_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC42_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC42_OUT_INV_SEL_M (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S) +#define GPIO_FUNC42_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_OUT_INV_SEL_S 8 +/** GPIO_FUNC42_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC42_OEN_SEL (BIT(9)) +#define GPIO_FUNC42_OEN_SEL_M (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S) +#define GPIO_FUNC42_OEN_SEL_V 0x00000001U +#define GPIO_FUNC42_OEN_SEL_S 9 +/** GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC42_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC42_OEN_INV_SEL_M (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S) +#define GPIO_FUNC42_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_OEN_INV_SEL_S 10 -#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) -/* GPIO_FUNC43_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC43_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC43_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC43_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC43_OEN_INV_SEL_S 10 -/* GPIO_FUNC43_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC43_OEN_SEL (BIT(9)) -#define GPIO_FUNC43_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC43_OEN_SEL_V 0x1 -#define GPIO_FUNC43_OEN_SEL_S 9 -/* GPIO_FUNC43_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC43_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC43_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC43_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC43_OUT_INV_SEL_S 8 -/* GPIO_FUNC43_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC43_OUT_SEL 0x000000FF -#define GPIO_FUNC43_OUT_SEL_M ((GPIO_FUNC43_OUT_SEL_V)<<(GPIO_FUNC43_OUT_SEL_S)) -#define GPIO_FUNC43_OUT_SEL_V 0xFF +/** GPIO_FUNC43_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) +/** GPIO_FUNC43_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC43_OUT_SEL 0x000000FFU +#define GPIO_FUNC43_OUT_SEL_M (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S) +#define GPIO_FUNC43_OUT_SEL_V 0x000000FFU #define GPIO_FUNC43_OUT_SEL_S 0 +/** GPIO_FUNC43_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC43_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC43_OUT_INV_SEL_M (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S) +#define GPIO_FUNC43_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC43_OUT_INV_SEL_S 8 +/** GPIO_FUNC43_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC43_OEN_SEL (BIT(9)) +#define GPIO_FUNC43_OEN_SEL_M (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S) +#define GPIO_FUNC43_OEN_SEL_V 0x00000001U +#define GPIO_FUNC43_OEN_SEL_S 9 +/** GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC43_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC43_OEN_INV_SEL_M (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S) +#define GPIO_FUNC43_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC43_OEN_INV_SEL_S 10 -#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) -/* GPIO_FUNC44_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC44_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC44_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC44_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC44_OEN_INV_SEL_S 10 -/* GPIO_FUNC44_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC44_OEN_SEL (BIT(9)) -#define GPIO_FUNC44_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC44_OEN_SEL_V 0x1 -#define GPIO_FUNC44_OEN_SEL_S 9 -/* GPIO_FUNC44_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_FUNC44_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC44_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC44_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC44_OUT_INV_SEL_S 8 -/* GPIO_FUNC44_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: */ -#define GPIO_FUNC44_OUT_SEL 0x000000FF -#define GPIO_FUNC44_OUT_SEL_M ((GPIO_FUNC44_OUT_SEL_V)<<(GPIO_FUNC44_OUT_SEL_S)) -#define GPIO_FUNC44_OUT_SEL_V 0xFF +/** GPIO_FUNC44_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) +/** GPIO_FUNC44_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC44_OUT_SEL 0x000000FFU +#define GPIO_FUNC44_OUT_SEL_M (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S) +#define GPIO_FUNC44_OUT_SEL_V 0x000000FFU #define GPIO_FUNC44_OUT_SEL_S 0 +/** GPIO_FUNC44_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC44_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC44_OUT_INV_SEL_M (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S) +#define GPIO_FUNC44_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC44_OUT_INV_SEL_S 8 +/** GPIO_FUNC44_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC44_OEN_SEL (BIT(9)) +#define GPIO_FUNC44_OEN_SEL_M (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S) +#define GPIO_FUNC44_OEN_SEL_V 0x00000001U +#define GPIO_FUNC44_OEN_SEL_S 9 +/** GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC44_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC44_OEN_INV_SEL_M (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S) +#define GPIO_FUNC44_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC44_OEN_INV_SEL_S 10 -#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62C) -/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define GPIO_CLK_EN (BIT(0)) -#define GPIO_CLK_EN_M (BIT(0)) -#define GPIO_CLK_EN_V 0x1 +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U #define GPIO_CLK_EN_S 0 -#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) -/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */ -/*description: */ -#define GPIO_DATE 0x0FFFFFFF -#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) -#define GPIO_DATE_V 0xFFFFFFF -#define GPIO_DATE_S 0 +/** GPIO_REG_DATE_REG register + * GPIO version register + */ +#define GPIO_REG_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) +/** GPIO_REG_DATE : R/W; bitpos: [27:0]; default: 33628944; + * version register + */ +#define GPIO_REG_DATE 0x0FFFFFFFU +#define GPIO_REG_DATE_M (GPIO_REG_DATE_V << GPIO_REG_DATE_S) +#define GPIO_REG_DATE_V 0x0FFFFFFFU +#define GPIO_REG_DATE_S 0 #ifdef __cplusplus } #endif - - #endif /*_SOC_GPIO_REG_H_ */ diff --git a/components/soc/esp32h2/include/rev1/soc/gpio_struct.h b/components/soc/esp32h2/include/rev1/soc/gpio_struct.h new file mode 100644 index 0000000000..87cd70a6c3 --- /dev/null +++ b/components/soc/esp32h2/include/rev1/soc/gpio_struct.h @@ -0,0 +1,609 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration register */ +/** Type of bt_select register + * GPIO bit select register + */ +typedef union { + struct { + /** bt_sel : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ + uint32_t bt_sel:32; + }; + uint32_t val; +} gpio_bt_select_reg_t; + +/** Type of out register + * GPIO output register for GPIO0-31 + */ +typedef union { + struct { + /** out_data_orig : R/W/WS/WC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 + */ + uint32_t out_data_orig:32; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register for GPIO0-31 + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 + */ + uint32_t out_w1ts:32; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register for GPIO0-31 + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 + */ + uint32_t out_w1tc:32; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of out1 register + * GPIO output register for GPIO32-44 + */ +typedef union { + struct { + /** out1_data_orig : R/W/WS/WC; bitpos: [12:0]; default: 0; + * GPIO output register for GPIO32-44 + */ + uint32_t out1_data_orig:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_out1_reg_t; + +/** Type of out1_w1ts register + * GPIO output set register for GPIO32-44 + */ +typedef union { + struct { + /** out1_w1ts : WT; bitpos: [12:0]; default: 0; + * GPIO output set register for GPIO32-44 + */ + uint32_t out1_w1ts:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_out1_w1ts_reg_t; + +/** Type of out1_w1tc register + * GPIO output clear register for GPIO32-44 + */ +typedef union { + struct { + /** out1_w1tc : WT; bitpos: [12:0]; default: 0; + * GPIO output clear register for GPIO32-44 + */ + uint32_t out1_w1tc:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_out1_w1tc_reg_t; + +/** Type of sdio_select register + * GPIO sdio select register + */ +typedef union { + struct { + /** sdio_sel : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ + uint32_t sdio_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_sdio_select_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-31 + */ +typedef union { + struct { + /** enable_data : R/W/SS; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ + uint32_t enable_data:32; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register for GPIO0-31 + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 + */ + uint32_t enable_w1ts:32; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register for GPIO0-31 + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 + */ + uint32_t enable_w1tc:32; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of enable1 register + * GPIO output enable register for GPIO32-44 + */ +typedef union { + struct { + /** enable1_data : R/W/SS; bitpos: [12:0]; default: 0; + * GPIO output enable register for GPIO32-44 + */ + uint32_t enable1_data:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_enable1_reg_t; + +/** Type of enable1_w1ts register + * GPIO output enable set register for GPIO32-44 + */ +typedef union { + struct { + /** enable1_w1ts : WT; bitpos: [12:0]; default: 0; + * GPIO output enable set register for GPIO32-44 + */ + uint32_t enable1_w1ts:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_enable1_w1ts_reg_t; + +/** Type of enable1_w1tc register + * GPIO output enable clear register for GPIO32-44 + */ +typedef union { + struct { + /** enable1_w1tc : WT; bitpos: [12:0]; default: 0; + * GPIO output enable clear register for GPIO32-44 + */ + uint32_t enable1_w1tc:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_enable1_w1tc_reg_t; + +/** Type of strap register + * pad strapping register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-31 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ + uint32_t in_data_next:32; + }; + uint32_t val; +} gpio_in_reg_t; + +/** Type of in1 register + * GPIO input register for GPIO32-44 + */ +typedef union { + struct { + /** in1_data_next : RO; bitpos: [12:0]; default: 0; + * GPIO input register for GPIO32-44 + */ + uint32_t in1_data_next:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_in1_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt : R/W/SS; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ + uint32_t status_interrupt:32; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register for GPIO0-31 + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 + */ + uint32_t status_w1ts:32; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register for GPIO0-31 + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 + */ + uint32_t status_w1tc:32; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of status1 register + * GPIO interrupt status register for GPIO32-44 + */ +typedef union { + struct { + /** status1_interrupt : R/W/SS; bitpos: [12:0]; default: 0; + * GPIO interrupt status register for GPIO32-44 + */ + uint32_t status1_interrupt:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_status1_reg_t; + +/** Type of status1_w1ts register + * GPIO interrupt status set register for GPIO32-44 + */ +typedef union { + struct { + /** status1_w1ts : WT; bitpos: [12:0]; default: 0; + * GPIO interrupt status set register for GPIO32-44 + */ + uint32_t status1_w1ts:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_status1_w1ts_reg_t; + +/** Type of status1_w1tc register + * GPIO interrupt status clear register for GPIO32-44 + */ +typedef union { + struct { + /** status1_w1tc : WT; bitpos: [12:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-44 + */ + uint32_t status1_w1tc:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_status1_w1tc_reg_t; + +/** Type of pcpu_int register + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ + uint32_t procpu_int:32; + }; + uint32_t val; +} gpio_pcpu_int_reg_t; + +/** Type of pcpu_nmi_int register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_nmi_int : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ + uint32_t procpu_nmi_int:32; + }; + uint32_t val; +} gpio_pcpu_nmi_int_reg_t; + +/** Type of cpusdio_int register + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [31:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ + uint32_t sdio_int:32; + }; + uint32_t val; +} gpio_cpusdio_int_reg_t; + +/** Type of pcpu_int1 register + * GPIO PRO_CPU interrupt status register for GPIO32-44 + */ +typedef union { + struct { + /** procpu_int1 : RO; bitpos: [12:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO32-44 + */ + uint32_t procpu_int1:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_pcpu_int1_reg_t; + +/** Type of pcpu_nmi_int1 register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 + */ +typedef union { + struct { + /** procpu_nmi_int1 : RO; bitpos: [12:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 + */ + uint32_t procpu_nmi_int1:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_pcpu_nmi_int1_reg_t; + +/** Type of cpusdio_int1 register + * GPIO CPUSDIO interrupt status register for GPIO32-44 + */ +typedef union { + struct { + /** sdio_int1 : RO; bitpos: [12:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO32-44 + */ + uint32_t sdio_int1:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_cpusdio_int1_reg_t; + +/** Type of pin register + * GPIO pin configuration register + */ +typedef union { + struct { + /** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pin_sync2_bypass:2; + /** pin_pad_driver : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ + uint32_t pin_pad_driver:1; + /** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pin_sync1_bypass:2; + uint32_t reserved_5:2; + /** pin_int_type : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ + uint32_t pin_int_type:3; + /** pin_wakeup_enable : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ + uint32_t pin_wakeup_enable:1; + /** pin_config : R/W; bitpos: [12:11]; default: 0; + * reserved + */ + uint32_t pin_config:2; + /** pin_int_ena : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ + uint32_t pin_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:32; + }; + uint32_t val; +} gpio_status_next_reg_t; + +/** Type of status_next1 register + * GPIO interrupt source register for GPIO32-44 + */ +typedef union { + struct { + /** status_interrupt_next1 : RO; bitpos: [12:0]; default: 0; + * GPIO interrupt source register for GPIO32-44 + */ + uint32_t status_interrupt_next1:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} gpio_status_next1_reg_t; + +/** Type of func_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func_in_sel : R/W; bitpos: [5:0]; default: 0; + * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func_in_sel:6; + /** func_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func_in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func_in_sel_cfg_reg_t; + +/** Type of func_out_sel_cfg register + * GPIO output function select register + */ +typedef union { + struct { + /** func_out_sel : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ + uint32_t func_out_sel:8; + /** func_out_inv_sel : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ + uint32_t func_out_inv_sel:1; + /** func_oen_sel : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ + uint32_t func_oen_sel:1; + /** func_oen_inv_sel : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ + uint32_t func_oen_inv_sel:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} gpio_func_out_sel_cfg_reg_t; + +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + +/** Type of reg_date register + * GPIO version register + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 33628944; + * version register + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_reg_date_reg_t; + + +typedef struct { + volatile gpio_bt_select_reg_t bt_select; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + volatile gpio_out1_reg_t out1; + volatile gpio_out1_w1ts_reg_t out1_w1ts; + volatile gpio_out1_w1tc_reg_t out1_w1tc; + volatile gpio_sdio_select_reg_t sdio_select; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + volatile gpio_enable1_reg_t enable1; + volatile gpio_enable1_w1ts_reg_t enable1_w1ts; + volatile gpio_enable1_w1tc_reg_t enable1_w1tc; + volatile gpio_strap_reg_t strap; + volatile gpio_in_reg_t in; + volatile gpio_in1_reg_t in1; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + volatile gpio_status1_reg_t status1; + volatile gpio_status1_w1ts_reg_t status1_w1ts; + volatile gpio_status1_w1tc_reg_t status1_w1tc; + volatile gpio_pcpu_int_reg_t pcpu_int; + volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; + volatile gpio_cpusdio_int_reg_t cpusdio_int; + volatile gpio_pcpu_int1_reg_t pcpu_int1; + volatile gpio_pcpu_nmi_int1_reg_t pcpu_nmi_int1; + volatile gpio_cpusdio_int1_reg_t cpusdio_int1; + volatile gpio_pin_reg_t pin[45]; + uint32_t reserved_128[9]; + volatile gpio_status_next_reg_t status_next; + volatile gpio_status_next1_reg_t status_next1; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; + uint32_t reserved_354[128]; + volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[45]; + uint32_t reserved_608[9]; + volatile gpio_clock_gate_reg_t clock_gate; + uint32_t reserved_630[51]; + volatile gpio_reg_date_reg_t reg_date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h b/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h index e1fc5cbcd7..96ec302766 100644 --- a/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h @@ -86,28 +86,47 @@ #define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) -#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U -#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U -#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U -#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U -#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U -#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U -#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U -#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U -#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U -#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U -#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U -#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U -#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U -#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U -#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U -#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U -#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U -#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U -#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U -#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U -#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U -#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_GPIO28_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_GPIO30_U +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_GPIO31_U +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U +#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_GPIO40_U /* Value to set in IO Mux to use a pin as GPIO. */ #define PIN_FUNC_GPIO 1 @@ -130,9 +149,9 @@ #define SD_DATA2_GPIO_NUM 9 #define SD_DATA3_GPIO_NUM 10 -#define MAX_RTC_GPIO_NUM 0 -#define MAX_PAD_GPIO_NUM 22 -#define MAX_GPIO_NUM 22 +#define MAX_RTC_GPIO_NUM 5 +#define MAX_PAD_GPIO_NUM 40 +#define MAX_GPIO_NUM 44 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE #define PIN_CTRL (REG_IO_MUX_BASE +0x00) @@ -255,9 +274,93 @@ #define FUNC_U0TXD_GPIO21 1 #define FUNC_U0TXD_U0TXD 0 -#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) -#define IO_MUX_DATE 0xFFFFFFFF -#define IO_MUX_DATE_S 0 -#define IO_MUX_DATE_VERSION 0x2006050 +#define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE +0x5c) +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE +0x60) +#define FUNC_GPIO23_GPIO23 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE +0x64) +#define FUNC_GPIO24_GPIO24 1 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE +0x68) +#define FUNC_GPIO25_GPIO25 1 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE +0x6c) +#define FUNC_GPIO26_GPIO26 1 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE +0x70) +#define FUNC_GPIO27_GPIO27 1 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO28_U (REG_IO_MUX_BASE +0x74) +#define FUNC_GPIO28_GPIO28 1 +#define FUNC_GPIO28_GPIO28_0 0 + +#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE +0x78) +#define FUNC_GPIO29_GPIO29 1 +#define FUNC_GPIO29_GPIO29_0 0 + +#define PERIPHS_IO_MUX_GPIO30_U (REG_IO_MUX_BASE +0x7c) +#define FUNC_GPIO30_GPIO30 1 +#define FUNC_GPIO30_GPIO30_0 0 + +#define PERIPHS_IO_MUX_GPIO31_U (REG_IO_MUX_BASE +0x80) +#define FUNC_GPIO31_GPIO31 1 +#define FUNC_GPIO31_GPIO31_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (REG_IO_MUX_BASE +0x84) +#define FUNC_GPIO32_GPIO32 1 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (REG_IO_MUX_BASE +0xa0) +#define FUNC_GPIO39_GPIO39 1 +#define FUNC_GPIO39_GPIO39_0 0 + +#define PERIPHS_IO_MUX_GPIO40_U (REG_IO_MUX_BASE +0xa4) +#define FUNC_GPIO40_GPIO40 1 +#define FUNC_GPIO40_GPIO40_0 0 + +/** IO_MUX_DATE_REG register + * IO MUX Version Control Register + */ +#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc) +/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 33628944; + * Version control register + */ +#define IO_MUX_REG_DATE 0x0FFFFFFFU +#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) +#define IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define IO_MUX_REG_DATE_S 0 +#define IO_MUX_DATE_VERSION 0x2012310 #endif diff --git a/components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h index 723051412f..d4f7ad7c12 100644 --- a/components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h @@ -18,7 +18,7 @@ extern "C" { /** USB_SERIAL_JTAG_EP1_REG register * USB_SERIAL_JTAG_EP1_REG. */ -#define USB_SERIAL_JTAG_EP1_REG (SOC_DPORT_USB_BASE + 0x0) +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write @@ -37,7 +37,7 @@ extern "C" { /** USB_SERIAL_JTAG_CONF0_REG register * USB_SERIAL_JTAG_CONF0_REG. */ -#define USB_SERIAL_JTAG_CONF0_REG (SOC_DPORT_USB_BASE + 0x18) +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) /* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external * PHY @@ -146,7 +146,7 @@ extern "C" { /** USB_SERIAL_JTAG_TEST_REG register * USB_SERIAL_JTAG_TEST_REG. */ -#define USB_SERIAL_JTAG_TEST_REG (SOC_DPORT_USB_BASE + 0x1c) +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) /* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB * pad @@ -183,7 +183,7 @@ extern "C" { /** USB_SERIAL_JTAG_MISC_CONF_REG register * USB_SERIAL_JTAG_MISC_CONF_REG. */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (SOC_DPORT_USB_BASE + 0x44) +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) /* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when * application writes @@ -197,7 +197,7 @@ extern "C" { /** USB_SERIAL_JTAG_MEM_CONF_REG register * USB_SERIAL_JTAG_MEM_CONF_REG. */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (SOC_DPORT_USB_BASE + 0x48) +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) /* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb * memory. @@ -221,7 +221,7 @@ extern "C" { /** USB_SERIAL_JTAG_EP1_CONF_REG register * USB_SERIAL_JTAG_EP1_CONF_REG. */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (SOC_DPORT_USB_BASE + 0x4) +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) /* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. * This bit then stays 0 until data in UART Tx FIFO is read by the USB @@ -253,7 +253,7 @@ extern "C" { /** USB_SERIAL_JTAG_JFIFO_ST_REG register * USB_SERIAL_JTAG_JFIFO_ST_REG. */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (SOC_DPORT_USB_BASE + 0x20) +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) /* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0; * JTAG in fifo * counter. @@ -322,7 +322,7 @@ extern "C" { /** USB_SERIAL_JTAG_FRAM_NUM_REG register * USB_SERIAL_JTAG_FRAM_NUM_REG. */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (SOC_DPORT_USB_BASE + 0x24) +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) /* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0; * Frame index of received SOF * frame. @@ -335,7 +335,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP0_ST_REG register * USB_SERIAL_JTAG_IN_EP0_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x28) +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) /* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint * 0. @@ -364,7 +364,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP1_ST_REG register * USB_SERIAL_JTAG_IN_EP1_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x2c) +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) /* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint * 1. @@ -393,7 +393,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP2_ST_REG register * USB_SERIAL_JTAG_IN_EP2_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x30) +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) /* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint * 2. @@ -422,7 +422,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP3_ST_REG register * USB_SERIAL_JTAG_IN_EP3_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (SOC_DPORT_USB_BASE + 0x34) +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) /* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint * 3. @@ -451,7 +451,7 @@ extern "C" { /** USB_SERIAL_JTAG_OUT_EP0_ST_REG register * USB_SERIAL_JTAG_OUT_EP0_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x38) +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) /* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint * 0. @@ -482,7 +482,7 @@ extern "C" { /** USB_SERIAL_JTAG_OUT_EP1_ST_REG register * USB_SERIAL_JTAG_OUT_EP1_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x3c) +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) /* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint * 1. @@ -521,7 +521,7 @@ extern "C" { /** USB_SERIAL_JTAG_OUT_EP2_ST_REG register * USB_SERIAL_JTAG_OUT_EP2_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x40) +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) /* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint * 2. @@ -555,7 +555,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_RAW_REG register * USB_SERIAL_JTAG_INT_RAW_REG. */ -#define USB_SERIAL_JTAG_INT_RAW_REG (SOC_DPORT_USB_BASE + 0x8) +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when a flush command is * received for IN endpoint 2 of @@ -662,7 +662,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_ST_REG register * USB_SERIAL_JTAG_INT_ST_REG. */ -#define USB_SERIAL_JTAG_INT_ST_REG (SOC_DPORT_USB_BASE + 0xc) +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT * interrupt. @@ -768,7 +768,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_ENA_REG register * USB_SERIAL_JTAG_INT_ENA_REG. */ -#define USB_SERIAL_JTAG_INT_ENA_REG (SOC_DPORT_USB_BASE + 0x10) +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT * interrupt. @@ -873,7 +873,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_CLR_REG register * USB_SERIAL_JTAG_INT_CLR_REG. */ -#define USB_SERIAL_JTAG_INT_CLR_REG (SOC_DPORT_USB_BASE + 0x14) +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT * interrupt. @@ -977,7 +977,7 @@ extern "C" { /** USB_SERIAL_JTAG_DATE_REG register * USB_SERIAL_JTAG_DATE_REG. */ -#define USB_SERIAL_JTAG_DATE_REG (SOC_DPORT_USB_BASE + 0x80) +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) /* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872; * register * version. diff --git a/components/soc/esp32h2/include/rev2/soc/gpio_reg.h b/components/soc/esp32h2/include/rev2/soc/gpio_reg.h index a3d6d1c40b..b49e876545 100644 --- a/components/soc/esp32h2/include/rev2/soc/gpio_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/gpio_reg.h @@ -39,4817 +39,6539 @@ extern "C" { #define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) #define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) -#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) -/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define GPIO_BT_SEL 0xFFFFFFFF -#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) -#define GPIO_BT_SEL_V 0xFFFFFFFF +/** GPIO_BT_SELECT_REG register + * GPIO bit select register + */ +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ +#define GPIO_BT_SEL 0xFFFFFFFFU +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFFU #define GPIO_BT_SEL_S 0 -#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/* GPIO_OUT_DATA : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_OUT_DATA 0x3FFFFFFF -#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) -#define GPIO_OUT_DATA_V 0x3FFFFFFF -#define GPIO_OUT_DATA_S 0 +/** GPIO_OUT_REG register + * GPIO output register for GPIO0-29 + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/WS/WC; bitpos: [29:0]; default: 0; + * GPIO output register for GPIO0-29 + */ +#define GPIO_OUT_DATA_ORIG 0x3FFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0x3FFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 -#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/* GPIO_OUT_W1TS : WO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_OUT_W1TS 0x3FFFFFFF -#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) -#define GPIO_OUT_W1TS_V 0x3FFFFFFF +/** GPIO_OUT_W1TS_REG register + * GPIO output set register for GPIO0-29 + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [29:0]; default: 0; + * GPIO output set register for GPIO0-29 + */ +#define GPIO_OUT_W1TS 0x3FFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0x3FFFFFFFU #define GPIO_OUT_W1TS_S 0 -#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xC) -/* GPIO_OUT_W1TC : WO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_OUT_W1TC 0x3FFFFFFF -#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) -#define GPIO_OUT_W1TC_V 0x3FFFFFFF +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register for GPIO0-29 + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [29:0]; default: 0; + * GPIO output clear register for GPIO0-29 + */ +#define GPIO_OUT_W1TC 0x3FFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0x3FFFFFFFU #define GPIO_OUT_W1TC_S 0 -#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1C) -/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: .*/ -#define GPIO_SDIO_SEL 0x000000FF -#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) -#define GPIO_SDIO_SEL_V 0xFF +/** GPIO_SDIO_SELECT_REG register + * GPIO sdio select register + */ +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) +/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ +#define GPIO_SDIO_SEL 0x000000FFU +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FFU #define GPIO_SDIO_SEL_S 0 -#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) -/* GPIO_ENABLE_DATA : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_ENABLE_DATA 0x3FFFFFFF -#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) -#define GPIO_ENABLE_DATA_V 0x3FFFFFFF +/** GPIO_ENABLE_REG register + * GPIO output enable register for GPIO0-29 + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/** GPIO_ENABLE_DATA : R/W/SS; bitpos: [29:0]; default: 0; + * GPIO output enable register for GPIO0-29 + */ +#define GPIO_ENABLE_DATA 0x3FFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0x3FFFFFFFU #define GPIO_ENABLE_DATA_S 0 -#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) -/* GPIO_ENABLE_W1TS : WO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_ENABLE_W1TS 0x3FFFFFFF -#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) -#define GPIO_ENABLE_W1TS_V 0x3FFFFFFF +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register for GPIO0-29 + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/** GPIO_ENABLE_W1TS : WT; bitpos: [29:0]; default: 0; + * GPIO output enable set register for GPIO0-29 + */ +#define GPIO_ENABLE_W1TS 0x3FFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0x3FFFFFFFU #define GPIO_ENABLE_W1TS_S 0 -#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) -/* GPIO_ENABLE_W1TC : WO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_ENABLE_W1TC 0x3FFFFFFF -#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) -#define GPIO_ENABLE_W1TC_V 0x3FFFFFFF +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register for GPIO0-29 + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/** GPIO_ENABLE_W1TC : WT; bitpos: [29:0]; default: 0; + * GPIO output enable clear register for GPIO0-29 + */ +#define GPIO_ENABLE_W1TC 0x3FFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0x3FFFFFFFU #define GPIO_ENABLE_W1TC_S 0 -#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) -/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ -/*description: .*/ -#define GPIO_STRAPPING 0x0000FFFF -#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) -#define GPIO_STRAPPING_V 0xFFFF +/** GPIO_STRAP_REG register + * pad strapping register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU #define GPIO_STRAPPING_S 0 -#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3C) -/* GPIO_IN_DATA : RO ;bitpos:[29:0] ;default: ; */ -/*description: .*/ -#define GPIO_IN_DATA 0x3FFFFFFF -#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) -#define GPIO_IN_DATA_V 0x3FFFFFFF -#define GPIO_IN_DATA_S 0 +/** GPIO_IN_REG register + * GPIO input register for GPIO0-29 + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [29:0]; default: 0; + * GPIO input register for GPIO0-29 + */ +#define GPIO_IN_DATA_NEXT 0x3FFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0x3FFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 -#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) -/* GPIO_STATUS_INT : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_STATUS_INT 0x3FFFFFFF -#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) -#define GPIO_STATUS_INT_V 0x3FFFFFFF -#define GPIO_STATUS_INT_S 0 +/** GPIO_STATUS_REG register + * GPIO interrupt status register for GPIO0-29 + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_STATUS_INTERRUPT : R/W/SS; bitpos: [29:0]; default: 0; + * GPIO interrupt status register for GPIO0-29 + */ +#define GPIO_STATUS_INTERRUPT 0x3FFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0x3FFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 -#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) -/* GPIO_STATUS_W1TS : WO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_STATUS_W1TS 0x3FFFFFFF -#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) -#define GPIO_STATUS_W1TS_V 0x3FFFFFFF +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register for GPIO0-29 + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_STATUS_W1TS : WT; bitpos: [29:0]; default: 0; + * GPIO interrupt status set register for GPIO0-29 + */ +#define GPIO_STATUS_W1TS 0x3FFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0x3FFFFFFFU #define GPIO_STATUS_W1TS_S 0 -#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4C) -/* GPIO_STATUS_W1TC : WO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_STATUS_W1TC 0x3FFFFFFF -#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) -#define GPIO_STATUS_W1TC_V 0x3FFFFFFF +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register for GPIO0-29 + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) +/** GPIO_STATUS_W1TC : WT; bitpos: [29:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-29 + */ +#define GPIO_STATUS_W1TC 0x3FFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0x3FFFFFFFU #define GPIO_STATUS_W1TC_S 0 -#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) -/* GPIO_PROCPU_INT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_PROCPU_INT 0x3FFFFFFF -#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) -#define GPIO_PROCPU_INT_V 0x3FFFFFFF +/** GPIO_PCPU_INT_REG register + * GPIO PRO_CPU interrupt status register for GPIO0-29 + */ +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) +/** GPIO_PROCPU_INT : RO; bitpos: [29:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-29 + */ +#define GPIO_PROCPU_INT 0x3FFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0x3FFFFFFFU #define GPIO_PROCPU_INT_S 0 -#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) -/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_PROCPU_NMI_INT 0x3FFFFFFF -#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) -#define GPIO_PROCPU_NMI_INT_V 0x3FFFFFFF +/** GPIO_PCPU_NMI_INT_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 + */ +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/** GPIO_PROCPU_NMI_INT : RO; bitpos: [29:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 + */ +#define GPIO_PROCPU_NMI_INT 0x3FFFFFFFU +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0x3FFFFFFFU #define GPIO_PROCPU_NMI_INT_S 0 -#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) -/* GPIO_SDIO_INT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_SDIO_INT 0x3FFFFFFF -#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) -#define GPIO_SDIO_INT_V 0x3FFFFFFF +/** GPIO_CPUSDIO_INT_REG register + * GPIO CPUSDIO interrupt status register for GPIO0-29 + */ +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_SDIO_INT : RO; bitpos: [29:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-29 + */ +#define GPIO_SDIO_INT 0x3FFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0x3FFFFFFFU #define GPIO_SDIO_INT_S 0 -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) -/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_INT_ENA 0x0000001F -#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) -#define GPIO_PIN0_INT_ENA_V 0x1F -#define GPIO_PIN0_INT_ENA_S 13 -/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_CONFIG 0x00000003 -#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) -#define GPIO_PIN0_CONFIG_V 0x3 -#define GPIO_PIN0_CONFIG_S 11 -/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN0_WAKEUP_ENABLE_S 10 -/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_INT_TYPE 0x00000007 -#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) -#define GPIO_PIN0_INT_TYPE_V 0x7 -#define GPIO_PIN0_INT_TYPE_S 7 -/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) -#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN0_SYNC1_BYPASS_S 3 -/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_V 0x1 -#define GPIO_PIN0_PAD_DRIVER_S 2 -/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) -#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN0_CONFIG 0x00000003U +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003U +#define GPIO_PIN0_CONFIG_S 11 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) -/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_INT_ENA 0x0000001F -#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) -#define GPIO_PIN1_INT_ENA_V 0x1F -#define GPIO_PIN1_INT_ENA_S 13 -/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_CONFIG 0x00000003 -#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) -#define GPIO_PIN1_CONFIG_V 0x3 -#define GPIO_PIN1_CONFIG_S 11 -/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN1_WAKEUP_ENABLE_S 10 -/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_INT_TYPE 0x00000007 -#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) -#define GPIO_PIN1_INT_TYPE_V 0x7 -#define GPIO_PIN1_INT_TYPE_S 7 -/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) -#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN1_SYNC1_BYPASS_S 3 -/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_V 0x1 -#define GPIO_PIN1_PAD_DRIVER_S 2 -/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) -#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN1_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN1_CONFIG 0x00000003U +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003U +#define GPIO_PIN1_CONFIG_S 11 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7C) -/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_INT_ENA 0x0000001F -#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) -#define GPIO_PIN2_INT_ENA_V 0x1F -#define GPIO_PIN2_INT_ENA_S 13 -/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_CONFIG 0x00000003 -#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) -#define GPIO_PIN2_CONFIG_V 0x3 -#define GPIO_PIN2_CONFIG_S 11 -/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN2_WAKEUP_ENABLE_S 10 -/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_INT_TYPE 0x00000007 -#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) -#define GPIO_PIN2_INT_TYPE_V 0x7 -#define GPIO_PIN2_INT_TYPE_S 7 -/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) -#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN2_SYNC1_BYPASS_S 3 -/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_V 0x1 -#define GPIO_PIN2_PAD_DRIVER_S 2 -/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) -#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN2_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN2_CONFIG 0x00000003U +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003U +#define GPIO_PIN2_CONFIG_S 11 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) -/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_INT_ENA 0x0000001F -#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) -#define GPIO_PIN3_INT_ENA_V 0x1F -#define GPIO_PIN3_INT_ENA_S 13 -/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_CONFIG 0x00000003 -#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) -#define GPIO_PIN3_CONFIG_V 0x3 -#define GPIO_PIN3_CONFIG_S 11 -/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN3_WAKEUP_ENABLE_S 10 -/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_INT_TYPE 0x00000007 -#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) -#define GPIO_PIN3_INT_TYPE_V 0x7 -#define GPIO_PIN3_INT_TYPE_S 7 -/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) -#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN3_SYNC1_BYPASS_S 3 -/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_V 0x1 -#define GPIO_PIN3_PAD_DRIVER_S 2 -/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) -#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN3_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN3_CONFIG 0x00000003U +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003U +#define GPIO_PIN3_CONFIG_S 11 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) -/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_INT_ENA 0x0000001F -#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) -#define GPIO_PIN4_INT_ENA_V 0x1F -#define GPIO_PIN4_INT_ENA_S 13 -/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_CONFIG 0x00000003 -#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) -#define GPIO_PIN4_CONFIG_V 0x3 -#define GPIO_PIN4_CONFIG_S 11 -/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN4_WAKEUP_ENABLE_S 10 -/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_INT_TYPE 0x00000007 -#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) -#define GPIO_PIN4_INT_TYPE_V 0x7 -#define GPIO_PIN4_INT_TYPE_S 7 -/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) -#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN4_SYNC1_BYPASS_S 3 -/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_V 0x1 -#define GPIO_PIN4_PAD_DRIVER_S 2 -/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) -#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN4_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN4_CONFIG 0x00000003U +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003U +#define GPIO_PIN4_CONFIG_S 11 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) -/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_INT_ENA 0x0000001F -#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) -#define GPIO_PIN5_INT_ENA_V 0x1F -#define GPIO_PIN5_INT_ENA_S 13 -/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_CONFIG 0x00000003 -#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) -#define GPIO_PIN5_CONFIG_V 0x3 -#define GPIO_PIN5_CONFIG_S 11 -/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN5_WAKEUP_ENABLE_S 10 -/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_INT_TYPE 0x00000007 -#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) -#define GPIO_PIN5_INT_TYPE_V 0x7 -#define GPIO_PIN5_INT_TYPE_S 7 -/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) -#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN5_SYNC1_BYPASS_S 3 -/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_V 0x1 -#define GPIO_PIN5_PAD_DRIVER_S 2 -/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) -#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN5_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN5_CONFIG 0x00000003U +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003U +#define GPIO_PIN5_CONFIG_S 11 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8C) -/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_INT_ENA 0x0000001F -#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) -#define GPIO_PIN6_INT_ENA_V 0x1F -#define GPIO_PIN6_INT_ENA_S 13 -/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_CONFIG 0x00000003 -#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) -#define GPIO_PIN6_CONFIG_V 0x3 -#define GPIO_PIN6_CONFIG_S 11 -/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN6_WAKEUP_ENABLE_S 10 -/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_INT_TYPE 0x00000007 -#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) -#define GPIO_PIN6_INT_TYPE_V 0x7 -#define GPIO_PIN6_INT_TYPE_S 7 -/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) -#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN6_SYNC1_BYPASS_S 3 -/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_V 0x1 -#define GPIO_PIN6_PAD_DRIVER_S 2 -/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) -#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN6_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN6_CONFIG 0x00000003U +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003U +#define GPIO_PIN6_CONFIG_S 11 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) -/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_INT_ENA 0x0000001F -#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) -#define GPIO_PIN7_INT_ENA_V 0x1F -#define GPIO_PIN7_INT_ENA_S 13 -/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_CONFIG 0x00000003 -#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) -#define GPIO_PIN7_CONFIG_V 0x3 -#define GPIO_PIN7_CONFIG_S 11 -/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN7_WAKEUP_ENABLE_S 10 -/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_INT_TYPE 0x00000007 -#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) -#define GPIO_PIN7_INT_TYPE_V 0x7 -#define GPIO_PIN7_INT_TYPE_S 7 -/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) -#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN7_SYNC1_BYPASS_S 3 -/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_V 0x1 -#define GPIO_PIN7_PAD_DRIVER_S 2 -/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) -#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN7_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN7_CONFIG 0x00000003U +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003U +#define GPIO_PIN7_CONFIG_S 11 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) -/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_INT_ENA 0x0000001F -#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) -#define GPIO_PIN8_INT_ENA_V 0x1F -#define GPIO_PIN8_INT_ENA_S 13 -/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_CONFIG 0x00000003 -#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) -#define GPIO_PIN8_CONFIG_V 0x3 -#define GPIO_PIN8_CONFIG_S 11 -/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN8_WAKEUP_ENABLE_S 10 -/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_INT_TYPE 0x00000007 -#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) -#define GPIO_PIN8_INT_TYPE_V 0x7 -#define GPIO_PIN8_INT_TYPE_S 7 -/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) -#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN8_SYNC1_BYPASS_S 3 -/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_V 0x1 -#define GPIO_PIN8_PAD_DRIVER_S 2 -/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) -#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN8_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN8_CONFIG 0x00000003U +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003U +#define GPIO_PIN8_CONFIG_S 11 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) -/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_INT_ENA 0x0000001F -#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) -#define GPIO_PIN9_INT_ENA_V 0x1F -#define GPIO_PIN9_INT_ENA_S 13 -/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_CONFIG 0x00000003 -#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) -#define GPIO_PIN9_CONFIG_V 0x3 -#define GPIO_PIN9_CONFIG_S 11 -/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN9_WAKEUP_ENABLE_S 10 -/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_INT_TYPE 0x00000007 -#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) -#define GPIO_PIN9_INT_TYPE_V 0x7 -#define GPIO_PIN9_INT_TYPE_S 7 -/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) -#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN9_SYNC1_BYPASS_S 3 -/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_V 0x1 -#define GPIO_PIN9_PAD_DRIVER_S 2 -/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) -#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN9_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN9_CONFIG 0x00000003U +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003U +#define GPIO_PIN9_CONFIG_S 11 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9C) -/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_INT_ENA 0x0000001F -#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) -#define GPIO_PIN10_INT_ENA_V 0x1F -#define GPIO_PIN10_INT_ENA_S 13 -/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_CONFIG 0x00000003 -#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) -#define GPIO_PIN10_CONFIG_V 0x3 -#define GPIO_PIN10_CONFIG_S 11 -/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN10_WAKEUP_ENABLE_S 10 -/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_INT_TYPE 0x00000007 -#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) -#define GPIO_PIN10_INT_TYPE_V 0x7 -#define GPIO_PIN10_INT_TYPE_S 7 -/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) -#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN10_SYNC1_BYPASS_S 3 -/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_V 0x1 -#define GPIO_PIN10_PAD_DRIVER_S 2 -/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) -#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN10_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN10_CONFIG 0x00000003U +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003U +#define GPIO_PIN10_CONFIG_S 11 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xA0) -/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_INT_ENA 0x0000001F -#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) -#define GPIO_PIN11_INT_ENA_V 0x1F -#define GPIO_PIN11_INT_ENA_S 13 -/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_CONFIG 0x00000003 -#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) -#define GPIO_PIN11_CONFIG_V 0x3 -#define GPIO_PIN11_CONFIG_S 11 -/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN11_WAKEUP_ENABLE_S 10 -/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_INT_TYPE 0x00000007 -#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) -#define GPIO_PIN11_INT_TYPE_V 0x7 -#define GPIO_PIN11_INT_TYPE_S 7 -/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) -#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN11_SYNC1_BYPASS_S 3 -/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_V 0x1 -#define GPIO_PIN11_PAD_DRIVER_S 2 -/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) -#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN11_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN11_CONFIG 0x00000003U +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003U +#define GPIO_PIN11_CONFIG_S 11 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xA4) -/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_INT_ENA 0x0000001F -#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) -#define GPIO_PIN12_INT_ENA_V 0x1F -#define GPIO_PIN12_INT_ENA_S 13 -/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_CONFIG 0x00000003 -#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) -#define GPIO_PIN12_CONFIG_V 0x3 -#define GPIO_PIN12_CONFIG_S 11 -/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN12_WAKEUP_ENABLE_S 10 -/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_INT_TYPE 0x00000007 -#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) -#define GPIO_PIN12_INT_TYPE_V 0x7 -#define GPIO_PIN12_INT_TYPE_S 7 -/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) -#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN12_SYNC1_BYPASS_S 3 -/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_V 0x1 -#define GPIO_PIN12_PAD_DRIVER_S 2 -/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) -#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN12_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN12_CONFIG 0x00000003U +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003U +#define GPIO_PIN12_CONFIG_S 11 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xA8) -/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_INT_ENA 0x0000001F -#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) -#define GPIO_PIN13_INT_ENA_V 0x1F -#define GPIO_PIN13_INT_ENA_S 13 -/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_CONFIG 0x00000003 -#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) -#define GPIO_PIN13_CONFIG_V 0x3 -#define GPIO_PIN13_CONFIG_S 11 -/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN13_WAKEUP_ENABLE_S 10 -/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_INT_TYPE 0x00000007 -#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) -#define GPIO_PIN13_INT_TYPE_V 0x7 -#define GPIO_PIN13_INT_TYPE_S 7 -/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) -#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN13_SYNC1_BYPASS_S 3 -/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_V 0x1 -#define GPIO_PIN13_PAD_DRIVER_S 2 -/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) -#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN13_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN13_CONFIG 0x00000003U +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003U +#define GPIO_PIN13_CONFIG_S 11 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xAC) -/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_INT_ENA 0x0000001F -#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) -#define GPIO_PIN14_INT_ENA_V 0x1F -#define GPIO_PIN14_INT_ENA_S 13 -/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_CONFIG 0x00000003 -#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) -#define GPIO_PIN14_CONFIG_V 0x3 -#define GPIO_PIN14_CONFIG_S 11 -/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN14_WAKEUP_ENABLE_S 10 -/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_INT_TYPE 0x00000007 -#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) -#define GPIO_PIN14_INT_TYPE_V 0x7 -#define GPIO_PIN14_INT_TYPE_S 7 -/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) -#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN14_SYNC1_BYPASS_S 3 -/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_V 0x1 -#define GPIO_PIN14_PAD_DRIVER_S 2 -/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) -#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN14_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN14_CONFIG 0x00000003U +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003U +#define GPIO_PIN14_CONFIG_S 11 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xB0) -/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_INT_ENA 0x0000001F -#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) -#define GPIO_PIN15_INT_ENA_V 0x1F -#define GPIO_PIN15_INT_ENA_S 13 -/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_CONFIG 0x00000003 -#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) -#define GPIO_PIN15_CONFIG_V 0x3 -#define GPIO_PIN15_CONFIG_S 11 -/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN15_WAKEUP_ENABLE_S 10 -/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_INT_TYPE 0x00000007 -#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) -#define GPIO_PIN15_INT_TYPE_V 0x7 -#define GPIO_PIN15_INT_TYPE_S 7 -/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) -#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN15_SYNC1_BYPASS_S 3 -/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_V 0x1 -#define GPIO_PIN15_PAD_DRIVER_S 2 -/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) -#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN15_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN15_CONFIG 0x00000003U +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003U +#define GPIO_PIN15_CONFIG_S 11 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xB4) -/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_INT_ENA 0x0000001F -#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) -#define GPIO_PIN16_INT_ENA_V 0x1F -#define GPIO_PIN16_INT_ENA_S 13 -/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_CONFIG 0x00000003 -#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) -#define GPIO_PIN16_CONFIG_V 0x3 -#define GPIO_PIN16_CONFIG_S 11 -/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN16_WAKEUP_ENABLE_S 10 -/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_INT_TYPE 0x00000007 -#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) -#define GPIO_PIN16_INT_TYPE_V 0x7 -#define GPIO_PIN16_INT_TYPE_S 7 -/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) -#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN16_SYNC1_BYPASS_S 3 -/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_V 0x1 -#define GPIO_PIN16_PAD_DRIVER_S 2 -/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) -#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN16_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN16_CONFIG 0x00000003U +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003U +#define GPIO_PIN16_CONFIG_S 11 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xB8) -/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_INT_ENA 0x0000001F -#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) -#define GPIO_PIN17_INT_ENA_V 0x1F -#define GPIO_PIN17_INT_ENA_S 13 -/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_CONFIG 0x00000003 -#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) -#define GPIO_PIN17_CONFIG_V 0x3 -#define GPIO_PIN17_CONFIG_S 11 -/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN17_WAKEUP_ENABLE_S 10 -/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_INT_TYPE 0x00000007 -#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) -#define GPIO_PIN17_INT_TYPE_V 0x7 -#define GPIO_PIN17_INT_TYPE_S 7 -/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) -#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN17_SYNC1_BYPASS_S 3 -/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_V 0x1 -#define GPIO_PIN17_PAD_DRIVER_S 2 -/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) -#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN17_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN17_CONFIG 0x00000003U +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003U +#define GPIO_PIN17_CONFIG_S 11 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xBC) -/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_INT_ENA 0x0000001F -#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) -#define GPIO_PIN18_INT_ENA_V 0x1F -#define GPIO_PIN18_INT_ENA_S 13 -/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_CONFIG 0x00000003 -#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) -#define GPIO_PIN18_CONFIG_V 0x3 -#define GPIO_PIN18_CONFIG_S 11 -/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN18_WAKEUP_ENABLE_S 10 -/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_INT_TYPE 0x00000007 -#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) -#define GPIO_PIN18_INT_TYPE_V 0x7 -#define GPIO_PIN18_INT_TYPE_S 7 -/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) -#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN18_SYNC1_BYPASS_S 3 -/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_PAD_DRIVER (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_V 0x1 -#define GPIO_PIN18_PAD_DRIVER_S 2 -/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) -#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN18_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN18_CONFIG 0x00000003U +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003U +#define GPIO_PIN18_CONFIG_S 11 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xC0) -/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_INT_ENA 0x0000001F -#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) -#define GPIO_PIN19_INT_ENA_V 0x1F -#define GPIO_PIN19_INT_ENA_S 13 -/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_CONFIG 0x00000003 -#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) -#define GPIO_PIN19_CONFIG_V 0x3 -#define GPIO_PIN19_CONFIG_S 11 -/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN19_WAKEUP_ENABLE_S 10 -/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_INT_TYPE 0x00000007 -#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) -#define GPIO_PIN19_INT_TYPE_V 0x7 -#define GPIO_PIN19_INT_TYPE_S 7 -/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) -#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN19_SYNC1_BYPASS_S 3 -/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_PAD_DRIVER (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_V 0x1 -#define GPIO_PIN19_PAD_DRIVER_S 2 -/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) -#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN19_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN19_CONFIG 0x00000003U +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003U +#define GPIO_PIN19_CONFIG_S 11 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xC4) -/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_INT_ENA 0x0000001F -#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) -#define GPIO_PIN20_INT_ENA_V 0x1F -#define GPIO_PIN20_INT_ENA_S 13 -/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_CONFIG 0x00000003 -#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) -#define GPIO_PIN20_CONFIG_V 0x3 -#define GPIO_PIN20_CONFIG_S 11 -/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN20_WAKEUP_ENABLE_S 10 -/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_INT_TYPE 0x00000007 -#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) -#define GPIO_PIN20_INT_TYPE_V 0x7 -#define GPIO_PIN20_INT_TYPE_S 7 -/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) -#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN20_SYNC1_BYPASS_S 3 -/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_PAD_DRIVER (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_V 0x1 -#define GPIO_PIN20_PAD_DRIVER_S 2 -/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) -#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN20_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN20_CONFIG 0x00000003U +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003U +#define GPIO_PIN20_CONFIG_S 11 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xC8) -/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_INT_ENA 0x0000001F -#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) -#define GPIO_PIN21_INT_ENA_V 0x1F -#define GPIO_PIN21_INT_ENA_S 13 -/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_CONFIG 0x00000003 -#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) -#define GPIO_PIN21_CONFIG_V 0x3 -#define GPIO_PIN21_CONFIG_S 11 -/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN21_WAKEUP_ENABLE_S 10 -/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_INT_TYPE 0x00000007 -#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) -#define GPIO_PIN21_INT_TYPE_V 0x7 -#define GPIO_PIN21_INT_TYPE_S 7 -/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) -#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN21_SYNC1_BYPASS_S 3 -/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_PAD_DRIVER (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_V 0x1 -#define GPIO_PIN21_PAD_DRIVER_S 2 -/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) -#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN21_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN21_CONFIG 0x00000003U +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003U +#define GPIO_PIN21_CONFIG_S 11 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xCC) -/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_INT_ENA 0x0000001F -#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) -#define GPIO_PIN22_INT_ENA_V 0x1F -#define GPIO_PIN22_INT_ENA_S 13 -/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_CONFIG 0x00000003 -#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) -#define GPIO_PIN22_CONFIG_V 0x3 -#define GPIO_PIN22_CONFIG_S 11 -/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN22_WAKEUP_ENABLE_S 10 -/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_INT_TYPE 0x00000007 -#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) -#define GPIO_PIN22_INT_TYPE_V 0x7 -#define GPIO_PIN22_INT_TYPE_S 7 -/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) -#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN22_SYNC1_BYPASS_S 3 -/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_PAD_DRIVER (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_V 0x1 -#define GPIO_PIN22_PAD_DRIVER_S 2 -/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) -#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN22_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN22_CONFIG 0x00000003U +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003U +#define GPIO_PIN22_CONFIG_S 11 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xD0) -/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_INT_ENA 0x0000001F -#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) -#define GPIO_PIN23_INT_ENA_V 0x1F -#define GPIO_PIN23_INT_ENA_S 13 -/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_CONFIG 0x00000003 -#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) -#define GPIO_PIN23_CONFIG_V 0x3 -#define GPIO_PIN23_CONFIG_S 11 -/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN23_WAKEUP_ENABLE_S 10 -/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_INT_TYPE 0x00000007 -#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) -#define GPIO_PIN23_INT_TYPE_V 0x7 -#define GPIO_PIN23_INT_TYPE_S 7 -/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) -#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN23_SYNC1_BYPASS_S 3 -/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_PAD_DRIVER (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_V 0x1 -#define GPIO_PIN23_PAD_DRIVER_S 2 -/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) -#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN23_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN23_CONFIG 0x00000003U +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003U +#define GPIO_PIN23_CONFIG_S 11 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xD4) -/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_INT_ENA 0x0000001F -#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) -#define GPIO_PIN24_INT_ENA_V 0x1F -#define GPIO_PIN24_INT_ENA_S 13 -/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_CONFIG 0x00000003 -#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) -#define GPIO_PIN24_CONFIG_V 0x3 -#define GPIO_PIN24_CONFIG_S 11 -/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN24_WAKEUP_ENABLE_S 10 -/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_INT_TYPE 0x00000007 -#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) -#define GPIO_PIN24_INT_TYPE_V 0x7 -#define GPIO_PIN24_INT_TYPE_S 7 -/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) -#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN24_SYNC1_BYPASS_S 3 -/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_PAD_DRIVER (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_V 0x1 -#define GPIO_PIN24_PAD_DRIVER_S 2 -/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) -#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN24_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN24_CONFIG 0x00000003U +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003U +#define GPIO_PIN24_CONFIG_S 11 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 -#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xD8) -/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_INT_ENA 0x0000001F -#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) -#define GPIO_PIN25_INT_ENA_V 0x1F -#define GPIO_PIN25_INT_ENA_S 13 -/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_CONFIG 0x00000003 -#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) -#define GPIO_PIN25_CONFIG_V 0x3 -#define GPIO_PIN25_CONFIG_S 11 -/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN25_WAKEUP_ENABLE_S 10 -/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_INT_TYPE 0x00000007 -#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) -#define GPIO_PIN25_INT_TYPE_V 0x7 -#define GPIO_PIN25_INT_TYPE_S 7 -/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) -#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN25_SYNC1_BYPASS_S 3 -/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_PAD_DRIVER (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_V 0x1 -#define GPIO_PIN25_PAD_DRIVER_S 2 -/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) -#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN25_CONFIG 0x00000003U +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003U +#define GPIO_PIN25_CONFIG_S 11 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 -#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xDC) -/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_INT_ENA 0x0000001F -#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) -#define GPIO_PIN26_INT_ENA_V 0x1F -#define GPIO_PIN26_INT_ENA_S 13 -/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_CONFIG 0x00000003 -#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) -#define GPIO_PIN26_CONFIG_V 0x3 -#define GPIO_PIN26_CONFIG_S 11 -/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN26_WAKEUP_ENABLE_S 10 -/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_INT_TYPE 0x00000007 -#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) -#define GPIO_PIN26_INT_TYPE_V 0x7 -#define GPIO_PIN26_INT_TYPE_S 7 -/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN26_SYNC1_BYPASS_M ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S)) -#define GPIO_PIN26_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN26_SYNC1_BYPASS_S 3 -/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_PAD_DRIVER (BIT(2)) -#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN26_PAD_DRIVER_V 0x1 -#define GPIO_PIN26_PAD_DRIVER_S 2 -/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN26_SYNC2_BYPASS_M ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S)) -#define GPIO_PIN26_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN26_CONFIG 0x00000003U +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003U +#define GPIO_PIN26_CONFIG_S 11 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 -#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xE0) -/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_INT_ENA 0x0000001F -#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) -#define GPIO_PIN27_INT_ENA_V 0x1F -#define GPIO_PIN27_INT_ENA_S 13 -/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_CONFIG 0x00000003 -#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) -#define GPIO_PIN27_CONFIG_V 0x3 -#define GPIO_PIN27_CONFIG_S 11 -/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN27_WAKEUP_ENABLE_S 10 -/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_INT_TYPE 0x00000007 -#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) -#define GPIO_PIN27_INT_TYPE_V 0x7 -#define GPIO_PIN27_INT_TYPE_S 7 -/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN27_SYNC1_BYPASS_M ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S)) -#define GPIO_PIN27_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN27_SYNC1_BYPASS_S 3 -/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_PAD_DRIVER (BIT(2)) -#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN27_PAD_DRIVER_V 0x1 -#define GPIO_PIN27_PAD_DRIVER_S 2 -/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN27_SYNC2_BYPASS_M ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S)) -#define GPIO_PIN27_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN27_CONFIG 0x00000003U +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003U +#define GPIO_PIN27_CONFIG_S 11 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 -#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xE4) -/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_INT_ENA 0x0000001F -#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) -#define GPIO_PIN28_INT_ENA_V 0x1F -#define GPIO_PIN28_INT_ENA_S 13 -/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_CONFIG 0x00000003 -#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) -#define GPIO_PIN28_CONFIG_V 0x3 -#define GPIO_PIN28_CONFIG_S 11 -/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN28_WAKEUP_ENABLE_S 10 -/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_INT_TYPE 0x00000007 -#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) -#define GPIO_PIN28_INT_TYPE_V 0x7 -#define GPIO_PIN28_INT_TYPE_S 7 -/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN28_SYNC1_BYPASS_M ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S)) -#define GPIO_PIN28_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN28_SYNC1_BYPASS_S 3 -/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_PAD_DRIVER (BIT(2)) -#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN28_PAD_DRIVER_V 0x1 -#define GPIO_PIN28_PAD_DRIVER_S 2 -/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN28_SYNC2_BYPASS_M ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S)) -#define GPIO_PIN28_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN28_CONFIG 0x00000003U +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003U +#define GPIO_PIN28_CONFIG_S 11 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 -#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xE8) -/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_INT_ENA 0x0000001F -#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) -#define GPIO_PIN29_INT_ENA_V 0x1F -#define GPIO_PIN29_INT_ENA_S 13 -/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_CONFIG 0x00000003 -#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) -#define GPIO_PIN29_CONFIG_V 0x3 -#define GPIO_PIN29_CONFIG_S 11 -/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN29_WAKEUP_ENABLE_S 10 -/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_INT_TYPE 0x00000007 -#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) -#define GPIO_PIN29_INT_TYPE_V 0x7 -#define GPIO_PIN29_INT_TYPE_S 7 -/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN29_SYNC1_BYPASS_M ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S)) -#define GPIO_PIN29_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN29_SYNC1_BYPASS_S 3 -/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_PAD_DRIVER (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_V 0x1 -#define GPIO_PIN29_PAD_DRIVER_S 2 -/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: .*/ -#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN29_SYNC2_BYPASS_M ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S)) -#define GPIO_PIN29_SYNC2_BYPASS_V 0x3 +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN29_CONFIG 0x00000003U +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003U +#define GPIO_PIN29_CONFIG_S 11 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) -/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ -/*description: .*/ -#define GPIO_STATUS_INTERRUPT_NEXT 0x3FFFFFFF -#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3FFFFFFF +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register for GPIO0-29 + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-29 + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_S 0 -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) -/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG0_IN_SEL (BIT(6)) -#define GPIO_SIG0_IN_SEL_M (BIT(6)) -#define GPIO_SIG0_IN_SEL_V 0x1 -#define GPIO_SIG0_IN_SEL_S 6 -/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC0_IN_INV_SEL_V 0x1 -#define GPIO_FUNC0_IN_INV_SEL_S 5 -/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC0_IN_SEL 0x0000001F -#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) -#define GPIO_FUNC0_IN_SEL_V 0x1F +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC0_IN_SEL 0x0000001FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000001FU #define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 5 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG0_IN_SEL (BIT(6)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 6 -#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) -/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG1_IN_SEL (BIT(6)) -#define GPIO_SIG1_IN_SEL_M (BIT(6)) -#define GPIO_SIG1_IN_SEL_V 0x1 -#define GPIO_SIG1_IN_SEL_S 6 -/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC1_IN_INV_SEL_V 0x1 -#define GPIO_FUNC1_IN_INV_SEL_S 5 -/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC1_IN_SEL 0x0000001F -#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) -#define GPIO_FUNC1_IN_SEL_V 0x1F +/** GPIO_FUNC1_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) +/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC1_IN_SEL 0x0000001FU +#define GPIO_FUNC1_IN_SEL_M (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S) +#define GPIO_FUNC1_IN_SEL_V 0x0000001FU #define GPIO_FUNC1_IN_SEL_S 0 +/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_M (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S) +#define GPIO_FUNC1_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_IN_INV_SEL_S 5 +/** GPIO_SIG1_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG1_IN_SEL (BIT(6)) +#define GPIO_SIG1_IN_SEL_M (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S) +#define GPIO_SIG1_IN_SEL_V 0x00000001U +#define GPIO_SIG1_IN_SEL_S 6 -#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15C) -/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG2_IN_SEL (BIT(6)) -#define GPIO_SIG2_IN_SEL_M (BIT(6)) -#define GPIO_SIG2_IN_SEL_V 0x1 -#define GPIO_SIG2_IN_SEL_S 6 -/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC2_IN_INV_SEL_V 0x1 -#define GPIO_FUNC2_IN_INV_SEL_S 5 -/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC2_IN_SEL 0x0000001F -#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) -#define GPIO_FUNC2_IN_SEL_V 0x1F +/** GPIO_FUNC2_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) +/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC2_IN_SEL 0x0000001FU +#define GPIO_FUNC2_IN_SEL_M (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S) +#define GPIO_FUNC2_IN_SEL_V 0x0000001FU #define GPIO_FUNC2_IN_SEL_S 0 +/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_M (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S) +#define GPIO_FUNC2_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_IN_INV_SEL_S 5 +/** GPIO_SIG2_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG2_IN_SEL (BIT(6)) +#define GPIO_SIG2_IN_SEL_M (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S) +#define GPIO_SIG2_IN_SEL_V 0x00000001U +#define GPIO_SIG2_IN_SEL_S 6 -#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) -/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG3_IN_SEL (BIT(6)) -#define GPIO_SIG3_IN_SEL_M (BIT(6)) -#define GPIO_SIG3_IN_SEL_V 0x1 -#define GPIO_SIG3_IN_SEL_S 6 -/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC3_IN_INV_SEL_V 0x1 -#define GPIO_FUNC3_IN_INV_SEL_S 5 -/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC3_IN_SEL 0x0000001F -#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) -#define GPIO_FUNC3_IN_SEL_V 0x1F +/** GPIO_FUNC3_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) +/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC3_IN_SEL 0x0000001FU +#define GPIO_FUNC3_IN_SEL_M (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S) +#define GPIO_FUNC3_IN_SEL_V 0x0000001FU #define GPIO_FUNC3_IN_SEL_S 0 +/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_M (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S) +#define GPIO_FUNC3_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_IN_INV_SEL_S 5 +/** GPIO_SIG3_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG3_IN_SEL (BIT(6)) +#define GPIO_SIG3_IN_SEL_M (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S) +#define GPIO_SIG3_IN_SEL_V 0x00000001U +#define GPIO_SIG3_IN_SEL_S 6 -#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) -/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG4_IN_SEL (BIT(6)) -#define GPIO_SIG4_IN_SEL_M (BIT(6)) -#define GPIO_SIG4_IN_SEL_V 0x1 -#define GPIO_SIG4_IN_SEL_S 6 -/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC4_IN_INV_SEL_V 0x1 -#define GPIO_FUNC4_IN_INV_SEL_S 5 -/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC4_IN_SEL 0x0000001F -#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) -#define GPIO_FUNC4_IN_SEL_V 0x1F +/** GPIO_FUNC4_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) +/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC4_IN_SEL 0x0000001FU +#define GPIO_FUNC4_IN_SEL_M (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S) +#define GPIO_FUNC4_IN_SEL_V 0x0000001FU #define GPIO_FUNC4_IN_SEL_S 0 +/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_M (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S) +#define GPIO_FUNC4_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_IN_INV_SEL_S 5 +/** GPIO_SIG4_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG4_IN_SEL (BIT(6)) +#define GPIO_SIG4_IN_SEL_M (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S) +#define GPIO_SIG4_IN_SEL_V 0x00000001U +#define GPIO_SIG4_IN_SEL_S 6 -#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) -/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG5_IN_SEL (BIT(6)) -#define GPIO_SIG5_IN_SEL_M (BIT(6)) -#define GPIO_SIG5_IN_SEL_V 0x1 -#define GPIO_SIG5_IN_SEL_S 6 -/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC5_IN_INV_SEL_V 0x1 -#define GPIO_FUNC5_IN_INV_SEL_S 5 -/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC5_IN_SEL 0x0000001F -#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) -#define GPIO_FUNC5_IN_SEL_V 0x1F +/** GPIO_FUNC5_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) +/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC5_IN_SEL 0x0000001FU +#define GPIO_FUNC5_IN_SEL_M (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S) +#define GPIO_FUNC5_IN_SEL_V 0x0000001FU #define GPIO_FUNC5_IN_SEL_S 0 +/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_M (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S) +#define GPIO_FUNC5_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_IN_INV_SEL_S 5 +/** GPIO_SIG5_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG5_IN_SEL (BIT(6)) +#define GPIO_SIG5_IN_SEL_M (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S) +#define GPIO_SIG5_IN_SEL_V 0x00000001U +#define GPIO_SIG5_IN_SEL_S 6 -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16C) -/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG6_IN_SEL (BIT(6)) -#define GPIO_SIG6_IN_SEL_M (BIT(6)) -#define GPIO_SIG6_IN_SEL_V 0x1 -#define GPIO_SIG6_IN_SEL_S 6 -/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC6_IN_INV_SEL_V 0x1 -#define GPIO_FUNC6_IN_INV_SEL_S 5 -/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC6_IN_SEL 0x0000001F -#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) -#define GPIO_FUNC6_IN_SEL_V 0x1F +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC6_IN_SEL 0x0000001FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000001FU #define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 5 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG6_IN_SEL (BIT(6)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 6 -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) -/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG7_IN_SEL (BIT(6)) -#define GPIO_SIG7_IN_SEL_M (BIT(6)) -#define GPIO_SIG7_IN_SEL_V 0x1 -#define GPIO_SIG7_IN_SEL_S 6 -/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC7_IN_INV_SEL_V 0x1 -#define GPIO_FUNC7_IN_INV_SEL_S 5 -/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC7_IN_SEL 0x0000001F -#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) -#define GPIO_FUNC7_IN_SEL_V 0x1F +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC7_IN_SEL 0x0000001FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000001FU #define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 5 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG7_IN_SEL (BIT(6)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 6 -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) -/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG8_IN_SEL (BIT(6)) -#define GPIO_SIG8_IN_SEL_M (BIT(6)) -#define GPIO_SIG8_IN_SEL_V 0x1 -#define GPIO_SIG8_IN_SEL_S 6 -/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC8_IN_INV_SEL_V 0x1 -#define GPIO_FUNC8_IN_INV_SEL_S 5 -/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC8_IN_SEL 0x0000001F -#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) -#define GPIO_FUNC8_IN_SEL_V 0x1F +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC8_IN_SEL 0x0000001FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000001FU #define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 5 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG8_IN_SEL (BIT(6)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 6 -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) -/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG9_IN_SEL (BIT(6)) -#define GPIO_SIG9_IN_SEL_M (BIT(6)) -#define GPIO_SIG9_IN_SEL_V 0x1 -#define GPIO_SIG9_IN_SEL_S 6 -/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC9_IN_INV_SEL_V 0x1 -#define GPIO_FUNC9_IN_INV_SEL_S 5 -/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC9_IN_SEL 0x0000001F -#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) -#define GPIO_FUNC9_IN_SEL_V 0x1F +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC9_IN_SEL 0x0000001FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000001FU #define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 5 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG9_IN_SEL (BIT(6)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 6 -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17C) -/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG10_IN_SEL (BIT(6)) -#define GPIO_SIG10_IN_SEL_M (BIT(6)) -#define GPIO_SIG10_IN_SEL_V 0x1 -#define GPIO_SIG10_IN_SEL_S 6 -/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC10_IN_INV_SEL_V 0x1 -#define GPIO_FUNC10_IN_INV_SEL_S 5 -/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC10_IN_SEL 0x0000001F -#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) -#define GPIO_FUNC10_IN_SEL_V 0x1F +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC10_IN_SEL 0x0000001FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000001FU #define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 5 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG10_IN_SEL (BIT(6)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 6 -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) -/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG11_IN_SEL (BIT(6)) -#define GPIO_SIG11_IN_SEL_M (BIT(6)) -#define GPIO_SIG11_IN_SEL_V 0x1 -#define GPIO_SIG11_IN_SEL_S 6 -/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC11_IN_INV_SEL_V 0x1 -#define GPIO_FUNC11_IN_INV_SEL_S 5 -/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC11_IN_SEL 0x0000001F -#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) -#define GPIO_FUNC11_IN_SEL_V 0x1F +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC11_IN_SEL 0x0000001FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000001FU #define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 5 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG11_IN_SEL (BIT(6)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 6 -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) -/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG12_IN_SEL (BIT(6)) -#define GPIO_SIG12_IN_SEL_M (BIT(6)) -#define GPIO_SIG12_IN_SEL_V 0x1 -#define GPIO_SIG12_IN_SEL_S 6 -/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC12_IN_INV_SEL_V 0x1 -#define GPIO_FUNC12_IN_INV_SEL_S 5 -/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC12_IN_SEL 0x0000001F -#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) -#define GPIO_FUNC12_IN_SEL_V 0x1F +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC12_IN_SEL 0x0000001FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000001FU #define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 5 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG12_IN_SEL (BIT(6)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 6 -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) -/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG13_IN_SEL (BIT(6)) -#define GPIO_SIG13_IN_SEL_M (BIT(6)) -#define GPIO_SIG13_IN_SEL_V 0x1 -#define GPIO_SIG13_IN_SEL_S 6 -/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC13_IN_INV_SEL_V 0x1 -#define GPIO_FUNC13_IN_INV_SEL_S 5 -/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC13_IN_SEL 0x0000001F -#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) -#define GPIO_FUNC13_IN_SEL_V 0x1F +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC13_IN_SEL 0x0000001FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000001FU #define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 5 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG13_IN_SEL (BIT(6)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 6 -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18C) -/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG14_IN_SEL (BIT(6)) -#define GPIO_SIG14_IN_SEL_M (BIT(6)) -#define GPIO_SIG14_IN_SEL_V 0x1 -#define GPIO_SIG14_IN_SEL_S 6 -/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC14_IN_INV_SEL_V 0x1 -#define GPIO_FUNC14_IN_INV_SEL_S 5 -/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC14_IN_SEL 0x0000001F -#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) -#define GPIO_FUNC14_IN_SEL_V 0x1F +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC14_IN_SEL 0x0000001FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000001FU #define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 5 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG14_IN_SEL (BIT(6)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 6 -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) -/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG15_IN_SEL (BIT(6)) -#define GPIO_SIG15_IN_SEL_M (BIT(6)) -#define GPIO_SIG15_IN_SEL_V 0x1 -#define GPIO_SIG15_IN_SEL_S 6 -/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC15_IN_INV_SEL_V 0x1 -#define GPIO_FUNC15_IN_INV_SEL_S 5 -/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC15_IN_SEL 0x0000001F -#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) -#define GPIO_FUNC15_IN_SEL_V 0x1F +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC15_IN_SEL 0x0000001FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000001FU #define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 5 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG15_IN_SEL (BIT(6)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 6 -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) -/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG16_IN_SEL (BIT(6)) -#define GPIO_SIG16_IN_SEL_M (BIT(6)) -#define GPIO_SIG16_IN_SEL_V 0x1 -#define GPIO_SIG16_IN_SEL_S 6 -/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC16_IN_INV_SEL_V 0x1 -#define GPIO_FUNC16_IN_INV_SEL_S 5 -/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC16_IN_SEL 0x0000001F -#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) -#define GPIO_FUNC16_IN_SEL_V 0x1F +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC16_IN_SEL 0x0000001FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000001FU #define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 5 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG16_IN_SEL (BIT(6)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 6 -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) -/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG17_IN_SEL (BIT(6)) -#define GPIO_SIG17_IN_SEL_M (BIT(6)) -#define GPIO_SIG17_IN_SEL_V 0x1 -#define GPIO_SIG17_IN_SEL_S 6 -/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC17_IN_INV_SEL_V 0x1 -#define GPIO_FUNC17_IN_INV_SEL_S 5 -/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC17_IN_SEL 0x0000001F -#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) -#define GPIO_FUNC17_IN_SEL_V 0x1F +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC17_IN_SEL 0x0000001FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000001FU #define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 5 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG17_IN_SEL (BIT(6)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 6 -#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19C) -/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG18_IN_SEL (BIT(6)) -#define GPIO_SIG18_IN_SEL_M (BIT(6)) -#define GPIO_SIG18_IN_SEL_V 0x1 -#define GPIO_SIG18_IN_SEL_S 6 -/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC18_IN_INV_SEL_V 0x1 -#define GPIO_FUNC18_IN_INV_SEL_S 5 -/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC18_IN_SEL 0x0000001F -#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) -#define GPIO_FUNC18_IN_SEL_V 0x1F +/** GPIO_FUNC18_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) +/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC18_IN_SEL 0x0000001FU +#define GPIO_FUNC18_IN_SEL_M (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S) +#define GPIO_FUNC18_IN_SEL_V 0x0000001FU #define GPIO_FUNC18_IN_SEL_S 0 +/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_M (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S) +#define GPIO_FUNC18_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_IN_INV_SEL_S 5 +/** GPIO_SIG18_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG18_IN_SEL (BIT(6)) +#define GPIO_SIG18_IN_SEL_M (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S) +#define GPIO_SIG18_IN_SEL_V 0x00000001U +#define GPIO_SIG18_IN_SEL_S 6 -#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A0) -/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG19_IN_SEL (BIT(6)) -#define GPIO_SIG19_IN_SEL_M (BIT(6)) -#define GPIO_SIG19_IN_SEL_V 0x1 -#define GPIO_SIG19_IN_SEL_S 6 -/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC19_IN_INV_SEL_V 0x1 -#define GPIO_FUNC19_IN_INV_SEL_S 5 -/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC19_IN_SEL 0x0000001F -#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) -#define GPIO_FUNC19_IN_SEL_V 0x1F +/** GPIO_FUNC19_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) +/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC19_IN_SEL 0x0000001FU +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000001FU #define GPIO_FUNC19_IN_SEL_S 0 +/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_IN_INV_SEL_S 5 +/** GPIO_SIG19_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG19_IN_SEL (BIT(6)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001U +#define GPIO_SIG19_IN_SEL_S 6 -#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A4) -/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG20_IN_SEL (BIT(6)) -#define GPIO_SIG20_IN_SEL_M (BIT(6)) -#define GPIO_SIG20_IN_SEL_V 0x1 -#define GPIO_SIG20_IN_SEL_S 6 -/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC20_IN_INV_SEL_V 0x1 -#define GPIO_FUNC20_IN_INV_SEL_S 5 -/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC20_IN_SEL 0x0000001F -#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) -#define GPIO_FUNC20_IN_SEL_V 0x1F +/** GPIO_FUNC20_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) +/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC20_IN_SEL 0x0000001FU +#define GPIO_FUNC20_IN_SEL_M (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S) +#define GPIO_FUNC20_IN_SEL_V 0x0000001FU #define GPIO_FUNC20_IN_SEL_S 0 +/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_M (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S) +#define GPIO_FUNC20_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_IN_INV_SEL_S 5 +/** GPIO_SIG20_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG20_IN_SEL (BIT(6)) +#define GPIO_SIG20_IN_SEL_M (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S) +#define GPIO_SIG20_IN_SEL_V 0x00000001U +#define GPIO_SIG20_IN_SEL_S 6 -#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A8) -/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG21_IN_SEL (BIT(6)) -#define GPIO_SIG21_IN_SEL_M (BIT(6)) -#define GPIO_SIG21_IN_SEL_V 0x1 -#define GPIO_SIG21_IN_SEL_S 6 -/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC21_IN_INV_SEL_V 0x1 -#define GPIO_FUNC21_IN_INV_SEL_S 5 -/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC21_IN_SEL 0x0000001F -#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) -#define GPIO_FUNC21_IN_SEL_V 0x1F +/** GPIO_FUNC21_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) +/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC21_IN_SEL 0x0000001FU +#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) +#define GPIO_FUNC21_IN_SEL_V 0x0000001FU #define GPIO_FUNC21_IN_SEL_S 0 +/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) +#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_IN_INV_SEL_S 5 +/** GPIO_SIG21_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG21_IN_SEL (BIT(6)) +#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) +#define GPIO_SIG21_IN_SEL_V 0x00000001U +#define GPIO_SIG21_IN_SEL_S 6 -#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1AC) -/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG22_IN_SEL (BIT(6)) -#define GPIO_SIG22_IN_SEL_M (BIT(6)) -#define GPIO_SIG22_IN_SEL_V 0x1 -#define GPIO_SIG22_IN_SEL_S 6 -/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC22_IN_INV_SEL_V 0x1 -#define GPIO_FUNC22_IN_INV_SEL_S 5 -/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC22_IN_SEL 0x0000001F -#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) -#define GPIO_FUNC22_IN_SEL_V 0x1F +/** GPIO_FUNC22_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) +/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC22_IN_SEL 0x0000001FU +#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) +#define GPIO_FUNC22_IN_SEL_V 0x0000001FU #define GPIO_FUNC22_IN_SEL_S 0 +/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) +#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_IN_INV_SEL_S 5 +/** GPIO_SIG22_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG22_IN_SEL (BIT(6)) +#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) +#define GPIO_SIG22_IN_SEL_V 0x00000001U +#define GPIO_SIG22_IN_SEL_S 6 -#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B0) -/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG23_IN_SEL (BIT(6)) -#define GPIO_SIG23_IN_SEL_M (BIT(6)) -#define GPIO_SIG23_IN_SEL_V 0x1 -#define GPIO_SIG23_IN_SEL_S 6 -/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC23_IN_INV_SEL_V 0x1 -#define GPIO_FUNC23_IN_INV_SEL_S 5 -/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC23_IN_SEL 0x0000001F -#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) -#define GPIO_FUNC23_IN_SEL_V 0x1F +/** GPIO_FUNC23_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) +/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC23_IN_SEL 0x0000001FU +#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) +#define GPIO_FUNC23_IN_SEL_V 0x0000001FU #define GPIO_FUNC23_IN_SEL_S 0 +/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) +#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_IN_INV_SEL_S 5 +/** GPIO_SIG23_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG23_IN_SEL (BIT(6)) +#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) +#define GPIO_SIG23_IN_SEL_V 0x00000001U +#define GPIO_SIG23_IN_SEL_S 6 -#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B4) -/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG24_IN_SEL (BIT(6)) -#define GPIO_SIG24_IN_SEL_M (BIT(6)) -#define GPIO_SIG24_IN_SEL_V 0x1 -#define GPIO_SIG24_IN_SEL_S 6 -/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC24_IN_INV_SEL_V 0x1 -#define GPIO_FUNC24_IN_INV_SEL_S 5 -/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC24_IN_SEL 0x0000001F -#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) -#define GPIO_FUNC24_IN_SEL_V 0x1F +/** GPIO_FUNC24_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) +/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC24_IN_SEL 0x0000001FU +#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) +#define GPIO_FUNC24_IN_SEL_V 0x0000001FU #define GPIO_FUNC24_IN_SEL_S 0 +/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) +#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_IN_INV_SEL_S 5 +/** GPIO_SIG24_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG24_IN_SEL (BIT(6)) +#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) +#define GPIO_SIG24_IN_SEL_V 0x00000001U +#define GPIO_SIG24_IN_SEL_S 6 -#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B8) -/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG25_IN_SEL (BIT(6)) -#define GPIO_SIG25_IN_SEL_M (BIT(6)) -#define GPIO_SIG25_IN_SEL_V 0x1 -#define GPIO_SIG25_IN_SEL_S 6 -/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC25_IN_INV_SEL_V 0x1 -#define GPIO_FUNC25_IN_INV_SEL_S 5 -/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC25_IN_SEL 0x0000001F -#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) -#define GPIO_FUNC25_IN_SEL_V 0x1F +/** GPIO_FUNC25_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) +/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC25_IN_SEL 0x0000001FU +#define GPIO_FUNC25_IN_SEL_M (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S) +#define GPIO_FUNC25_IN_SEL_V 0x0000001FU #define GPIO_FUNC25_IN_SEL_S 0 +/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_M (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S) +#define GPIO_FUNC25_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_IN_INV_SEL_S 5 +/** GPIO_SIG25_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG25_IN_SEL (BIT(6)) +#define GPIO_SIG25_IN_SEL_M (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S) +#define GPIO_SIG25_IN_SEL_V 0x00000001U +#define GPIO_SIG25_IN_SEL_S 6 -#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1BC) -/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG26_IN_SEL (BIT(6)) -#define GPIO_SIG26_IN_SEL_M (BIT(6)) -#define GPIO_SIG26_IN_SEL_V 0x1 -#define GPIO_SIG26_IN_SEL_S 6 -/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC26_IN_INV_SEL_V 0x1 -#define GPIO_FUNC26_IN_INV_SEL_S 5 -/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC26_IN_SEL 0x0000001F -#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) -#define GPIO_FUNC26_IN_SEL_V 0x1F +/** GPIO_FUNC26_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) +/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC26_IN_SEL 0x0000001FU +#define GPIO_FUNC26_IN_SEL_M (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S) +#define GPIO_FUNC26_IN_SEL_V 0x0000001FU #define GPIO_FUNC26_IN_SEL_S 0 +/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_M (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S) +#define GPIO_FUNC26_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_IN_INV_SEL_S 5 +/** GPIO_SIG26_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG26_IN_SEL (BIT(6)) +#define GPIO_SIG26_IN_SEL_M (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S) +#define GPIO_SIG26_IN_SEL_V 0x00000001U +#define GPIO_SIG26_IN_SEL_S 6 -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C0) -/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG27_IN_SEL (BIT(6)) -#define GPIO_SIG27_IN_SEL_M (BIT(6)) -#define GPIO_SIG27_IN_SEL_V 0x1 -#define GPIO_SIG27_IN_SEL_S 6 -/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC27_IN_INV_SEL_V 0x1 -#define GPIO_FUNC27_IN_INV_SEL_S 5 -/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC27_IN_SEL 0x0000001F -#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) -#define GPIO_FUNC27_IN_SEL_V 0x1F +/** GPIO_FUNC27_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) +/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC27_IN_SEL 0x0000001FU +#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) +#define GPIO_FUNC27_IN_SEL_V 0x0000001FU #define GPIO_FUNC27_IN_SEL_S 0 +/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) +#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_IN_INV_SEL_S 5 +/** GPIO_SIG27_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG27_IN_SEL (BIT(6)) +#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) +#define GPIO_SIG27_IN_SEL_V 0x00000001U +#define GPIO_SIG27_IN_SEL_S 6 -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C4) -/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG28_IN_SEL (BIT(6)) -#define GPIO_SIG28_IN_SEL_M (BIT(6)) -#define GPIO_SIG28_IN_SEL_V 0x1 -#define GPIO_SIG28_IN_SEL_S 6 -/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC28_IN_INV_SEL_V 0x1 -#define GPIO_FUNC28_IN_INV_SEL_S 5 -/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC28_IN_SEL 0x0000001F -#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) -#define GPIO_FUNC28_IN_SEL_V 0x1F +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC28_IN_SEL 0x0000001FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000001FU #define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 5 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG28_IN_SEL (BIT(6)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 6 -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C8) -/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG29_IN_SEL (BIT(6)) -#define GPIO_SIG29_IN_SEL_M (BIT(6)) -#define GPIO_SIG29_IN_SEL_V 0x1 -#define GPIO_SIG29_IN_SEL_S 6 -/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC29_IN_INV_SEL_V 0x1 -#define GPIO_FUNC29_IN_INV_SEL_S 5 -/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC29_IN_SEL 0x0000001F -#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) -#define GPIO_FUNC29_IN_SEL_V 0x1F +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC29_IN_SEL 0x0000001FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000001FU #define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 5 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG29_IN_SEL (BIT(6)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 6 -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1CC) -/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG30_IN_SEL (BIT(6)) -#define GPIO_SIG30_IN_SEL_M (BIT(6)) -#define GPIO_SIG30_IN_SEL_V 0x1 -#define GPIO_SIG30_IN_SEL_S 6 -/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC30_IN_INV_SEL_V 0x1 -#define GPIO_FUNC30_IN_INV_SEL_S 5 -/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC30_IN_SEL 0x0000001F -#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) -#define GPIO_FUNC30_IN_SEL_V 0x1F +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC30_IN_SEL 0x0000001FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000001FU #define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 5 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG30_IN_SEL (BIT(6)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 6 -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D0) -/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG31_IN_SEL (BIT(6)) -#define GPIO_SIG31_IN_SEL_M (BIT(6)) -#define GPIO_SIG31_IN_SEL_V 0x1 -#define GPIO_SIG31_IN_SEL_S 6 -/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC31_IN_INV_SEL_V 0x1 -#define GPIO_FUNC31_IN_INV_SEL_S 5 -/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC31_IN_SEL 0x0000001F -#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) -#define GPIO_FUNC31_IN_SEL_V 0x1F +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC31_IN_SEL 0x0000001FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000001FU #define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 5 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG31_IN_SEL (BIT(6)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 6 -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D4) -/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG32_IN_SEL (BIT(6)) -#define GPIO_SIG32_IN_SEL_M (BIT(6)) -#define GPIO_SIG32_IN_SEL_V 0x1 -#define GPIO_SIG32_IN_SEL_S 6 -/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC32_IN_INV_SEL_V 0x1 -#define GPIO_FUNC32_IN_INV_SEL_S 5 -/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC32_IN_SEL 0x0000001F -#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) -#define GPIO_FUNC32_IN_SEL_V 0x1F +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC32_IN_SEL 0x0000001FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000001FU #define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 5 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG32_IN_SEL (BIT(6)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 6 -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D8) -/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG33_IN_SEL (BIT(6)) -#define GPIO_SIG33_IN_SEL_M (BIT(6)) -#define GPIO_SIG33_IN_SEL_V 0x1 -#define GPIO_SIG33_IN_SEL_S 6 -/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC33_IN_INV_SEL_V 0x1 -#define GPIO_FUNC33_IN_INV_SEL_S 5 -/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC33_IN_SEL 0x0000001F -#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) -#define GPIO_FUNC33_IN_SEL_V 0x1F +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC33_IN_SEL 0x0000001FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000001FU #define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 5 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG33_IN_SEL (BIT(6)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 6 -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1DC) -/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG34_IN_SEL (BIT(6)) -#define GPIO_SIG34_IN_SEL_M (BIT(6)) -#define GPIO_SIG34_IN_SEL_V 0x1 -#define GPIO_SIG34_IN_SEL_S 6 -/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC34_IN_INV_SEL_V 0x1 -#define GPIO_FUNC34_IN_INV_SEL_S 5 -/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC34_IN_SEL 0x0000001F -#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) -#define GPIO_FUNC34_IN_SEL_V 0x1F +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC34_IN_SEL 0x0000001FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000001FU #define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 5 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG34_IN_SEL (BIT(6)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 6 -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E0) -/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG35_IN_SEL (BIT(6)) -#define GPIO_SIG35_IN_SEL_M (BIT(6)) -#define GPIO_SIG35_IN_SEL_V 0x1 -#define GPIO_SIG35_IN_SEL_S 6 -/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC35_IN_INV_SEL_V 0x1 -#define GPIO_FUNC35_IN_INV_SEL_S 5 -/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC35_IN_SEL 0x0000001F -#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) -#define GPIO_FUNC35_IN_SEL_V 0x1F +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC35_IN_SEL 0x0000001FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000001FU #define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 5 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG35_IN_SEL (BIT(6)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 6 -#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E4) -/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG36_IN_SEL (BIT(6)) -#define GPIO_SIG36_IN_SEL_M (BIT(6)) -#define GPIO_SIG36_IN_SEL_V 0x1 -#define GPIO_SIG36_IN_SEL_S 6 -/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC36_IN_INV_SEL_V 0x1 -#define GPIO_FUNC36_IN_INV_SEL_S 5 -/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC36_IN_SEL 0x0000001F -#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) -#define GPIO_FUNC36_IN_SEL_V 0x1F +/** GPIO_FUNC36_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) +/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC36_IN_SEL 0x0000001FU +#define GPIO_FUNC36_IN_SEL_M (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S) +#define GPIO_FUNC36_IN_SEL_V 0x0000001FU #define GPIO_FUNC36_IN_SEL_S 0 +/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_M (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S) +#define GPIO_FUNC36_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC36_IN_INV_SEL_S 5 +/** GPIO_SIG36_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG36_IN_SEL (BIT(6)) +#define GPIO_SIG36_IN_SEL_M (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S) +#define GPIO_SIG36_IN_SEL_V 0x00000001U +#define GPIO_SIG36_IN_SEL_S 6 -#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E8) -/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG37_IN_SEL (BIT(6)) -#define GPIO_SIG37_IN_SEL_M (BIT(6)) -#define GPIO_SIG37_IN_SEL_V 0x1 -#define GPIO_SIG37_IN_SEL_S 6 -/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC37_IN_INV_SEL_V 0x1 -#define GPIO_FUNC37_IN_INV_SEL_S 5 -/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC37_IN_SEL 0x0000001F -#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) -#define GPIO_FUNC37_IN_SEL_V 0x1F +/** GPIO_FUNC37_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) +/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC37_IN_SEL 0x0000001FU +#define GPIO_FUNC37_IN_SEL_M (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S) +#define GPIO_FUNC37_IN_SEL_V 0x0000001FU #define GPIO_FUNC37_IN_SEL_S 0 +/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_M (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S) +#define GPIO_FUNC37_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC37_IN_INV_SEL_S 5 +/** GPIO_SIG37_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG37_IN_SEL (BIT(6)) +#define GPIO_SIG37_IN_SEL_M (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S) +#define GPIO_SIG37_IN_SEL_V 0x00000001U +#define GPIO_SIG37_IN_SEL_S 6 -#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1EC) -/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG38_IN_SEL (BIT(6)) -#define GPIO_SIG38_IN_SEL_M (BIT(6)) -#define GPIO_SIG38_IN_SEL_V 0x1 -#define GPIO_SIG38_IN_SEL_S 6 -/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC38_IN_INV_SEL_V 0x1 -#define GPIO_FUNC38_IN_INV_SEL_S 5 -/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC38_IN_SEL 0x0000001F -#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) -#define GPIO_FUNC38_IN_SEL_V 0x1F +/** GPIO_FUNC38_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) +/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC38_IN_SEL 0x0000001FU +#define GPIO_FUNC38_IN_SEL_M (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S) +#define GPIO_FUNC38_IN_SEL_V 0x0000001FU #define GPIO_FUNC38_IN_SEL_S 0 +/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_M (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S) +#define GPIO_FUNC38_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC38_IN_INV_SEL_S 5 +/** GPIO_SIG38_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG38_IN_SEL (BIT(6)) +#define GPIO_SIG38_IN_SEL_M (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S) +#define GPIO_SIG38_IN_SEL_V 0x00000001U +#define GPIO_SIG38_IN_SEL_S 6 -#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F0) -/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG39_IN_SEL (BIT(6)) -#define GPIO_SIG39_IN_SEL_M (BIT(6)) -#define GPIO_SIG39_IN_SEL_V 0x1 -#define GPIO_SIG39_IN_SEL_S 6 -/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC39_IN_INV_SEL_V 0x1 -#define GPIO_FUNC39_IN_INV_SEL_S 5 -/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC39_IN_SEL 0x0000001F -#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) -#define GPIO_FUNC39_IN_SEL_V 0x1F +/** GPIO_FUNC39_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) +/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC39_IN_SEL 0x0000001FU +#define GPIO_FUNC39_IN_SEL_M (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S) +#define GPIO_FUNC39_IN_SEL_V 0x0000001FU #define GPIO_FUNC39_IN_SEL_S 0 +/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_M (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S) +#define GPIO_FUNC39_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC39_IN_INV_SEL_S 5 +/** GPIO_SIG39_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG39_IN_SEL (BIT(6)) +#define GPIO_SIG39_IN_SEL_M (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S) +#define GPIO_SIG39_IN_SEL_V 0x00000001U +#define GPIO_SIG39_IN_SEL_S 6 -#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F4) -/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG40_IN_SEL (BIT(6)) -#define GPIO_SIG40_IN_SEL_M (BIT(6)) -#define GPIO_SIG40_IN_SEL_V 0x1 -#define GPIO_SIG40_IN_SEL_S 6 -/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC40_IN_INV_SEL_V 0x1 -#define GPIO_FUNC40_IN_INV_SEL_S 5 -/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC40_IN_SEL 0x0000001F -#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) -#define GPIO_FUNC40_IN_SEL_V 0x1F +/** GPIO_FUNC40_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) +/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC40_IN_SEL 0x0000001FU +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000001FU #define GPIO_FUNC40_IN_SEL_S 0 +/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_IN_INV_SEL_S 5 +/** GPIO_SIG40_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG40_IN_SEL (BIT(6)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001U +#define GPIO_SIG40_IN_SEL_S 6 -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F8) -/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG41_IN_SEL (BIT(6)) -#define GPIO_SIG41_IN_SEL_M (BIT(6)) -#define GPIO_SIG41_IN_SEL_V 0x1 -#define GPIO_SIG41_IN_SEL_S 6 -/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC41_IN_INV_SEL_V 0x1 -#define GPIO_FUNC41_IN_INV_SEL_S 5 -/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC41_IN_SEL 0x0000001F -#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) -#define GPIO_FUNC41_IN_SEL_V 0x1F +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC41_IN_SEL 0x0000001FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000001FU #define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 5 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG41_IN_SEL (BIT(6)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 6 -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1FC) -/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG42_IN_SEL (BIT(6)) -#define GPIO_SIG42_IN_SEL_M (BIT(6)) -#define GPIO_SIG42_IN_SEL_V 0x1 -#define GPIO_SIG42_IN_SEL_S 6 -/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC42_IN_INV_SEL_V 0x1 -#define GPIO_FUNC42_IN_INV_SEL_S 5 -/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC42_IN_SEL 0x0000001F -#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) -#define GPIO_FUNC42_IN_SEL_V 0x1F +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC42_IN_SEL 0x0000001FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000001FU #define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 5 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG42_IN_SEL (BIT(6)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 6 -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) -/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG43_IN_SEL (BIT(6)) -#define GPIO_SIG43_IN_SEL_M (BIT(6)) -#define GPIO_SIG43_IN_SEL_V 0x1 -#define GPIO_SIG43_IN_SEL_S 6 -/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC43_IN_INV_SEL_V 0x1 -#define GPIO_FUNC43_IN_INV_SEL_S 5 -/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC43_IN_SEL 0x0000001F -#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) -#define GPIO_FUNC43_IN_SEL_V 0x1F +/** GPIO_FUNC43_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) +/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC43_IN_SEL 0x0000001FU +#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) +#define GPIO_FUNC43_IN_SEL_V 0x0000001FU #define GPIO_FUNC43_IN_SEL_S 0 +/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) +#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC43_IN_INV_SEL_S 5 +/** GPIO_SIG43_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG43_IN_SEL (BIT(6)) +#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) +#define GPIO_SIG43_IN_SEL_V 0x00000001U +#define GPIO_SIG43_IN_SEL_S 6 -#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) -/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG44_IN_SEL (BIT(6)) -#define GPIO_SIG44_IN_SEL_M (BIT(6)) -#define GPIO_SIG44_IN_SEL_V 0x1 -#define GPIO_SIG44_IN_SEL_S 6 -/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC44_IN_INV_SEL_V 0x1 -#define GPIO_FUNC44_IN_INV_SEL_S 5 -/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC44_IN_SEL 0x0000001F -#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) -#define GPIO_FUNC44_IN_SEL_V 0x1F +/** GPIO_FUNC44_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) +/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC44_IN_SEL 0x0000001FU +#define GPIO_FUNC44_IN_SEL_M (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S) +#define GPIO_FUNC44_IN_SEL_V 0x0000001FU #define GPIO_FUNC44_IN_SEL_S 0 +/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_M (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S) +#define GPIO_FUNC44_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC44_IN_INV_SEL_S 5 +/** GPIO_SIG44_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG44_IN_SEL (BIT(6)) +#define GPIO_SIG44_IN_SEL_M (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S) +#define GPIO_SIG44_IN_SEL_V 0x00000001U +#define GPIO_SIG44_IN_SEL_S 6 -#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) -/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG45_IN_SEL (BIT(6)) -#define GPIO_SIG45_IN_SEL_M (BIT(6)) -#define GPIO_SIG45_IN_SEL_V 0x1 -#define GPIO_SIG45_IN_SEL_S 6 -/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC45_IN_INV_SEL_V 0x1 -#define GPIO_FUNC45_IN_INV_SEL_S 5 -/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC45_IN_SEL 0x0000001F -#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) -#define GPIO_FUNC45_IN_SEL_V 0x1F +/** GPIO_FUNC45_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC45_IN_SEL 0x0000001FU +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000001FU #define GPIO_FUNC45_IN_SEL_S 0 +/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC45_IN_INV_SEL_S 5 +/** GPIO_SIG45_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG45_IN_SEL (BIT(6)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001U +#define GPIO_SIG45_IN_SEL_S 6 -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20C) -/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG46_IN_SEL (BIT(6)) -#define GPIO_SIG46_IN_SEL_M (BIT(6)) -#define GPIO_SIG46_IN_SEL_V 0x1 -#define GPIO_SIG46_IN_SEL_S 6 -/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC46_IN_INV_SEL_V 0x1 -#define GPIO_FUNC46_IN_INV_SEL_S 5 -/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC46_IN_SEL 0x0000001F -#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) -#define GPIO_FUNC46_IN_SEL_V 0x1F +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC46_IN_SEL 0x0000001FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000001FU #define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 5 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG46_IN_SEL (BIT(6)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 6 -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) -/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG47_IN_SEL (BIT(6)) -#define GPIO_SIG47_IN_SEL_M (BIT(6)) -#define GPIO_SIG47_IN_SEL_V 0x1 -#define GPIO_SIG47_IN_SEL_S 6 -/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC47_IN_INV_SEL_V 0x1 -#define GPIO_FUNC47_IN_INV_SEL_S 5 -/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC47_IN_SEL 0x0000001F -#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) -#define GPIO_FUNC47_IN_SEL_V 0x1F +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC47_IN_SEL 0x0000001FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000001FU #define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 5 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG47_IN_SEL (BIT(6)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 6 -#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) -/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG48_IN_SEL (BIT(6)) -#define GPIO_SIG48_IN_SEL_M (BIT(6)) -#define GPIO_SIG48_IN_SEL_V 0x1 -#define GPIO_SIG48_IN_SEL_S 6 -/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC48_IN_INV_SEL_V 0x1 -#define GPIO_FUNC48_IN_INV_SEL_S 5 -/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC48_IN_SEL 0x0000001F -#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) -#define GPIO_FUNC48_IN_SEL_V 0x1F +/** GPIO_FUNC48_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC48_IN_SEL 0x0000001FU +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000001FU #define GPIO_FUNC48_IN_SEL_S 0 +/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC48_IN_INV_SEL_S 5 +/** GPIO_SIG48_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG48_IN_SEL (BIT(6)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001U +#define GPIO_SIG48_IN_SEL_S 6 -#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) -/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG49_IN_SEL (BIT(6)) -#define GPIO_SIG49_IN_SEL_M (BIT(6)) -#define GPIO_SIG49_IN_SEL_V 0x1 -#define GPIO_SIG49_IN_SEL_S 6 -/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC49_IN_INV_SEL_V 0x1 -#define GPIO_FUNC49_IN_INV_SEL_S 5 -/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC49_IN_SEL 0x0000001F -#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) -#define GPIO_FUNC49_IN_SEL_V 0x1F +/** GPIO_FUNC49_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC49_IN_SEL 0x0000001FU +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000001FU #define GPIO_FUNC49_IN_SEL_S 0 +/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC49_IN_INV_SEL_S 5 +/** GPIO_SIG49_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG49_IN_SEL (BIT(6)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001U +#define GPIO_SIG49_IN_SEL_S 6 -#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21C) -/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG50_IN_SEL (BIT(6)) -#define GPIO_SIG50_IN_SEL_M (BIT(6)) -#define GPIO_SIG50_IN_SEL_V 0x1 -#define GPIO_SIG50_IN_SEL_S 6 -/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC50_IN_INV_SEL_V 0x1 -#define GPIO_FUNC50_IN_INV_SEL_S 5 -/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC50_IN_SEL 0x0000001F -#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) -#define GPIO_FUNC50_IN_SEL_V 0x1F +/** GPIO_FUNC50_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) +/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC50_IN_SEL 0x0000001FU +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000001FU #define GPIO_FUNC50_IN_SEL_S 0 +/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC50_IN_INV_SEL_S 5 +/** GPIO_SIG50_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG50_IN_SEL (BIT(6)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001U +#define GPIO_SIG50_IN_SEL_S 6 -#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) -/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG51_IN_SEL (BIT(6)) -#define GPIO_SIG51_IN_SEL_M (BIT(6)) -#define GPIO_SIG51_IN_SEL_V 0x1 -#define GPIO_SIG51_IN_SEL_S 6 -/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC51_IN_INV_SEL_V 0x1 -#define GPIO_FUNC51_IN_INV_SEL_S 5 -/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC51_IN_SEL 0x0000001F -#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) -#define GPIO_FUNC51_IN_SEL_V 0x1F +/** GPIO_FUNC51_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC51_IN_SEL 0x0000001FU +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000001FU #define GPIO_FUNC51_IN_SEL_S 0 +/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC51_IN_INV_SEL_S 5 +/** GPIO_SIG51_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG51_IN_SEL (BIT(6)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001U +#define GPIO_SIG51_IN_SEL_S 6 -#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) -/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG52_IN_SEL (BIT(6)) -#define GPIO_SIG52_IN_SEL_M (BIT(6)) -#define GPIO_SIG52_IN_SEL_V 0x1 -#define GPIO_SIG52_IN_SEL_S 6 -/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC52_IN_INV_SEL_V 0x1 -#define GPIO_FUNC52_IN_INV_SEL_S 5 -/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC52_IN_SEL 0x0000001F -#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) -#define GPIO_FUNC52_IN_SEL_V 0x1F +/** GPIO_FUNC52_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC52_IN_SEL 0x0000001FU +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000001FU #define GPIO_FUNC52_IN_SEL_S 0 +/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC52_IN_INV_SEL_S 5 +/** GPIO_SIG52_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG52_IN_SEL (BIT(6)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001U +#define GPIO_SIG52_IN_SEL_S 6 -#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) -/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG53_IN_SEL (BIT(6)) -#define GPIO_SIG53_IN_SEL_M (BIT(6)) -#define GPIO_SIG53_IN_SEL_V 0x1 -#define GPIO_SIG53_IN_SEL_S 6 -/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC53_IN_INV_SEL_V 0x1 -#define GPIO_FUNC53_IN_INV_SEL_S 5 -/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC53_IN_SEL 0x0000001F -#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) -#define GPIO_FUNC53_IN_SEL_V 0x1F +/** GPIO_FUNC53_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC53_IN_SEL 0x0000001FU +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000001FU #define GPIO_FUNC53_IN_SEL_S 0 +/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC53_IN_INV_SEL_S 5 +/** GPIO_SIG53_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG53_IN_SEL (BIT(6)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001U +#define GPIO_SIG53_IN_SEL_S 6 -#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22C) -/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG54_IN_SEL (BIT(6)) -#define GPIO_SIG54_IN_SEL_M (BIT(6)) -#define GPIO_SIG54_IN_SEL_V 0x1 -#define GPIO_SIG54_IN_SEL_S 6 -/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC54_IN_INV_SEL_V 0x1 -#define GPIO_FUNC54_IN_INV_SEL_S 5 -/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC54_IN_SEL 0x0000001F -#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) -#define GPIO_FUNC54_IN_SEL_V 0x1F +/** GPIO_FUNC54_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) +/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC54_IN_SEL 0x0000001FU +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000001FU #define GPIO_FUNC54_IN_SEL_S 0 +/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC54_IN_INV_SEL_S 5 +/** GPIO_SIG54_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG54_IN_SEL (BIT(6)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001U +#define GPIO_SIG54_IN_SEL_S 6 -#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) -/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG55_IN_SEL (BIT(6)) -#define GPIO_SIG55_IN_SEL_M (BIT(6)) -#define GPIO_SIG55_IN_SEL_V 0x1 -#define GPIO_SIG55_IN_SEL_S 6 -/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC55_IN_INV_SEL_V 0x1 -#define GPIO_FUNC55_IN_INV_SEL_S 5 -/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC55_IN_SEL 0x0000001F -#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) -#define GPIO_FUNC55_IN_SEL_V 0x1F +/** GPIO_FUNC55_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC55_IN_SEL 0x0000001FU +#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) +#define GPIO_FUNC55_IN_SEL_V 0x0000001FU #define GPIO_FUNC55_IN_SEL_S 0 +/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) +#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC55_IN_INV_SEL_S 5 +/** GPIO_SIG55_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG55_IN_SEL (BIT(6)) +#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) +#define GPIO_SIG55_IN_SEL_V 0x00000001U +#define GPIO_SIG55_IN_SEL_S 6 -#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) -/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG56_IN_SEL (BIT(6)) -#define GPIO_SIG56_IN_SEL_M (BIT(6)) -#define GPIO_SIG56_IN_SEL_V 0x1 -#define GPIO_SIG56_IN_SEL_S 6 -/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC56_IN_INV_SEL_V 0x1 -#define GPIO_FUNC56_IN_INV_SEL_S 5 -/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC56_IN_SEL 0x0000001F -#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) -#define GPIO_FUNC56_IN_SEL_V 0x1F +/** GPIO_FUNC56_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC56_IN_SEL 0x0000001FU +#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) +#define GPIO_FUNC56_IN_SEL_V 0x0000001FU #define GPIO_FUNC56_IN_SEL_S 0 +/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) +#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC56_IN_INV_SEL_S 5 +/** GPIO_SIG56_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG56_IN_SEL (BIT(6)) +#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) +#define GPIO_SIG56_IN_SEL_V 0x00000001U +#define GPIO_SIG56_IN_SEL_S 6 -#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) -/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG57_IN_SEL (BIT(6)) -#define GPIO_SIG57_IN_SEL_M (BIT(6)) -#define GPIO_SIG57_IN_SEL_V 0x1 -#define GPIO_SIG57_IN_SEL_S 6 -/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC57_IN_INV_SEL_V 0x1 -#define GPIO_FUNC57_IN_INV_SEL_S 5 -/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC57_IN_SEL 0x0000001F -#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) -#define GPIO_FUNC57_IN_SEL_V 0x1F +/** GPIO_FUNC57_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) +/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC57_IN_SEL 0x0000001FU +#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) +#define GPIO_FUNC57_IN_SEL_V 0x0000001FU #define GPIO_FUNC57_IN_SEL_S 0 +/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) +#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC57_IN_INV_SEL_S 5 +/** GPIO_SIG57_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG57_IN_SEL (BIT(6)) +#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) +#define GPIO_SIG57_IN_SEL_V 0x00000001U +#define GPIO_SIG57_IN_SEL_S 6 -#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23C) -/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG58_IN_SEL (BIT(6)) -#define GPIO_SIG58_IN_SEL_M (BIT(6)) -#define GPIO_SIG58_IN_SEL_V 0x1 -#define GPIO_SIG58_IN_SEL_S 6 -/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC58_IN_INV_SEL_V 0x1 -#define GPIO_FUNC58_IN_INV_SEL_S 5 -/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC58_IN_SEL 0x0000001F -#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) -#define GPIO_FUNC58_IN_SEL_V 0x1F +/** GPIO_FUNC58_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) +/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC58_IN_SEL 0x0000001FU +#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) +#define GPIO_FUNC58_IN_SEL_V 0x0000001FU #define GPIO_FUNC58_IN_SEL_S 0 +/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) +#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC58_IN_INV_SEL_S 5 +/** GPIO_SIG58_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG58_IN_SEL (BIT(6)) +#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) +#define GPIO_SIG58_IN_SEL_V 0x00000001U +#define GPIO_SIG58_IN_SEL_S 6 -#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) -/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG59_IN_SEL (BIT(6)) -#define GPIO_SIG59_IN_SEL_M (BIT(6)) -#define GPIO_SIG59_IN_SEL_V 0x1 -#define GPIO_SIG59_IN_SEL_S 6 -/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC59_IN_INV_SEL_V 0x1 -#define GPIO_FUNC59_IN_INV_SEL_S 5 -/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC59_IN_SEL 0x0000001F -#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) -#define GPIO_FUNC59_IN_SEL_V 0x1F +/** GPIO_FUNC59_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) +/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC59_IN_SEL 0x0000001FU +#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) +#define GPIO_FUNC59_IN_SEL_V 0x0000001FU #define GPIO_FUNC59_IN_SEL_S 0 +/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) +#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC59_IN_INV_SEL_S 5 +/** GPIO_SIG59_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG59_IN_SEL (BIT(6)) +#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) +#define GPIO_SIG59_IN_SEL_V 0x00000001U +#define GPIO_SIG59_IN_SEL_S 6 -#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) -/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG60_IN_SEL (BIT(6)) -#define GPIO_SIG60_IN_SEL_M (BIT(6)) -#define GPIO_SIG60_IN_SEL_V 0x1 -#define GPIO_SIG60_IN_SEL_S 6 -/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC60_IN_INV_SEL_V 0x1 -#define GPIO_FUNC60_IN_INV_SEL_S 5 -/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC60_IN_SEL 0x0000001F -#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) -#define GPIO_FUNC60_IN_SEL_V 0x1F +/** GPIO_FUNC60_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) +/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC60_IN_SEL 0x0000001FU +#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) +#define GPIO_FUNC60_IN_SEL_V 0x0000001FU #define GPIO_FUNC60_IN_SEL_S 0 +/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) +#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC60_IN_INV_SEL_S 5 +/** GPIO_SIG60_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG60_IN_SEL (BIT(6)) +#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) +#define GPIO_SIG60_IN_SEL_V 0x00000001U +#define GPIO_SIG60_IN_SEL_S 6 -#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) -/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG61_IN_SEL (BIT(6)) -#define GPIO_SIG61_IN_SEL_M (BIT(6)) -#define GPIO_SIG61_IN_SEL_V 0x1 -#define GPIO_SIG61_IN_SEL_S 6 -/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC61_IN_INV_SEL_V 0x1 -#define GPIO_FUNC61_IN_INV_SEL_S 5 -/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC61_IN_SEL 0x0000001F -#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) -#define GPIO_FUNC61_IN_SEL_V 0x1F +/** GPIO_FUNC61_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) +/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC61_IN_SEL 0x0000001FU +#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) +#define GPIO_FUNC61_IN_SEL_V 0x0000001FU #define GPIO_FUNC61_IN_SEL_S 0 +/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) +#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC61_IN_INV_SEL_S 5 +/** GPIO_SIG61_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG61_IN_SEL (BIT(6)) +#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) +#define GPIO_SIG61_IN_SEL_V 0x00000001U +#define GPIO_SIG61_IN_SEL_S 6 -#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24C) -/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG62_IN_SEL (BIT(6)) -#define GPIO_SIG62_IN_SEL_M (BIT(6)) -#define GPIO_SIG62_IN_SEL_V 0x1 -#define GPIO_SIG62_IN_SEL_S 6 -/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC62_IN_INV_SEL_V 0x1 -#define GPIO_FUNC62_IN_INV_SEL_S 5 -/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC62_IN_SEL 0x0000001F -#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) -#define GPIO_FUNC62_IN_SEL_V 0x1F +/** GPIO_FUNC62_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) +/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC62_IN_SEL 0x0000001FU +#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) +#define GPIO_FUNC62_IN_SEL_V 0x0000001FU #define GPIO_FUNC62_IN_SEL_S 0 +/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) +#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC62_IN_INV_SEL_S 5 +/** GPIO_SIG62_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG62_IN_SEL (BIT(6)) +#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) +#define GPIO_SIG62_IN_SEL_V 0x00000001U +#define GPIO_SIG62_IN_SEL_S 6 -#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) -/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG63_IN_SEL (BIT(6)) -#define GPIO_SIG63_IN_SEL_M (BIT(6)) -#define GPIO_SIG63_IN_SEL_V 0x1 -#define GPIO_SIG63_IN_SEL_S 6 -/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC63_IN_INV_SEL_V 0x1 -#define GPIO_FUNC63_IN_INV_SEL_S 5 -/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC63_IN_SEL 0x0000001F -#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) -#define GPIO_FUNC63_IN_SEL_V 0x1F +/** GPIO_FUNC63_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC63_IN_SEL 0x0000001FU +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000001FU #define GPIO_FUNC63_IN_SEL_S 0 +/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC63_IN_INV_SEL_S 5 +/** GPIO_SIG63_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG63_IN_SEL (BIT(6)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001U +#define GPIO_SIG63_IN_SEL_S 6 -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) -/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG64_IN_SEL (BIT(6)) -#define GPIO_SIG64_IN_SEL_M (BIT(6)) -#define GPIO_SIG64_IN_SEL_V 0x1 -#define GPIO_SIG64_IN_SEL_S 6 -/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC64_IN_INV_SEL_V 0x1 -#define GPIO_FUNC64_IN_INV_SEL_S 5 -/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC64_IN_SEL 0x0000001F -#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) -#define GPIO_FUNC64_IN_SEL_V 0x1F +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC64_IN_SEL 0x0000001FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000001FU #define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 5 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG64_IN_SEL (BIT(6)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 6 -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) -/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG65_IN_SEL (BIT(6)) -#define GPIO_SIG65_IN_SEL_M (BIT(6)) -#define GPIO_SIG65_IN_SEL_V 0x1 -#define GPIO_SIG65_IN_SEL_S 6 -/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC65_IN_INV_SEL_V 0x1 -#define GPIO_FUNC65_IN_INV_SEL_S 5 -/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC65_IN_SEL 0x0000001F -#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) -#define GPIO_FUNC65_IN_SEL_V 0x1F +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC65_IN_SEL 0x0000001FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000001FU #define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 5 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG65_IN_SEL (BIT(6)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 6 -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25C) -/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG66_IN_SEL (BIT(6)) -#define GPIO_SIG66_IN_SEL_M (BIT(6)) -#define GPIO_SIG66_IN_SEL_V 0x1 -#define GPIO_SIG66_IN_SEL_S 6 -/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC66_IN_INV_SEL_V 0x1 -#define GPIO_FUNC66_IN_INV_SEL_S 5 -/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC66_IN_SEL 0x0000001F -#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) -#define GPIO_FUNC66_IN_SEL_V 0x1F +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC66_IN_SEL 0x0000001FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000001FU #define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 5 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG66_IN_SEL (BIT(6)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 6 -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) -/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG67_IN_SEL (BIT(6)) -#define GPIO_SIG67_IN_SEL_M (BIT(6)) -#define GPIO_SIG67_IN_SEL_V 0x1 -#define GPIO_SIG67_IN_SEL_S 6 -/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC67_IN_INV_SEL_V 0x1 -#define GPIO_FUNC67_IN_INV_SEL_S 5 -/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC67_IN_SEL 0x0000001F -#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) -#define GPIO_FUNC67_IN_SEL_V 0x1F +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC67_IN_SEL 0x0000001FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000001FU #define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 5 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG67_IN_SEL (BIT(6)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 6 -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) -/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG68_IN_SEL (BIT(6)) -#define GPIO_SIG68_IN_SEL_M (BIT(6)) -#define GPIO_SIG68_IN_SEL_V 0x1 -#define GPIO_SIG68_IN_SEL_S 6 -/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC68_IN_INV_SEL_V 0x1 -#define GPIO_FUNC68_IN_INV_SEL_S 5 -/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC68_IN_SEL 0x0000001F -#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) -#define GPIO_FUNC68_IN_SEL_V 0x1F +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC68_IN_SEL 0x0000001FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000001FU #define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 5 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG68_IN_SEL (BIT(6)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 6 -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) -/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG69_IN_SEL (BIT(6)) -#define GPIO_SIG69_IN_SEL_M (BIT(6)) -#define GPIO_SIG69_IN_SEL_V 0x1 -#define GPIO_SIG69_IN_SEL_S 6 -/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC69_IN_INV_SEL_V 0x1 -#define GPIO_FUNC69_IN_INV_SEL_S 5 -/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC69_IN_SEL 0x0000001F -#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) -#define GPIO_FUNC69_IN_SEL_V 0x1F +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC69_IN_SEL 0x0000001FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000001FU #define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 5 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG69_IN_SEL (BIT(6)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 6 -#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26C) -/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG70_IN_SEL (BIT(6)) -#define GPIO_SIG70_IN_SEL_M (BIT(6)) -#define GPIO_SIG70_IN_SEL_V 0x1 -#define GPIO_SIG70_IN_SEL_S 6 -/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC70_IN_INV_SEL_V 0x1 -#define GPIO_FUNC70_IN_INV_SEL_S 5 -/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC70_IN_SEL 0x0000001F -#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) -#define GPIO_FUNC70_IN_SEL_V 0x1F +/** GPIO_FUNC70_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) +/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC70_IN_SEL 0x0000001FU +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000001FU #define GPIO_FUNC70_IN_SEL_S 0 +/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC70_IN_INV_SEL_S 5 +/** GPIO_SIG70_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG70_IN_SEL (BIT(6)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001U +#define GPIO_SIG70_IN_SEL_S 6 -#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) -/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG71_IN_SEL (BIT(6)) -#define GPIO_SIG71_IN_SEL_M (BIT(6)) -#define GPIO_SIG71_IN_SEL_V 0x1 -#define GPIO_SIG71_IN_SEL_S 6 -/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC71_IN_INV_SEL_V 0x1 -#define GPIO_FUNC71_IN_INV_SEL_S 5 -/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC71_IN_SEL 0x0000001F -#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) -#define GPIO_FUNC71_IN_SEL_V 0x1F +/** GPIO_FUNC71_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC71_IN_SEL 0x0000001FU +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000001FU #define GPIO_FUNC71_IN_SEL_S 0 +/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC71_IN_INV_SEL_S 5 +/** GPIO_SIG71_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG71_IN_SEL (BIT(6)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001U +#define GPIO_SIG71_IN_SEL_S 6 -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) -/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG72_IN_SEL (BIT(6)) -#define GPIO_SIG72_IN_SEL_M (BIT(6)) -#define GPIO_SIG72_IN_SEL_V 0x1 -#define GPIO_SIG72_IN_SEL_S 6 -/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC72_IN_INV_SEL_V 0x1 -#define GPIO_FUNC72_IN_INV_SEL_S 5 -/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC72_IN_SEL 0x0000001F -#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) -#define GPIO_FUNC72_IN_SEL_V 0x1F +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC72_IN_SEL 0x0000001FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000001FU #define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 5 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG72_IN_SEL (BIT(6)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 6 -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) -/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG73_IN_SEL (BIT(6)) -#define GPIO_SIG73_IN_SEL_M (BIT(6)) -#define GPIO_SIG73_IN_SEL_V 0x1 -#define GPIO_SIG73_IN_SEL_S 6 -/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC73_IN_INV_SEL_V 0x1 -#define GPIO_FUNC73_IN_INV_SEL_S 5 -/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC73_IN_SEL 0x0000001F -#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) -#define GPIO_FUNC73_IN_SEL_V 0x1F +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC73_IN_SEL 0x0000001FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000001FU #define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 5 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG73_IN_SEL (BIT(6)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 6 -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27C) -/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG74_IN_SEL (BIT(6)) -#define GPIO_SIG74_IN_SEL_M (BIT(6)) -#define GPIO_SIG74_IN_SEL_V 0x1 -#define GPIO_SIG74_IN_SEL_S 6 -/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC74_IN_INV_SEL_V 0x1 -#define GPIO_FUNC74_IN_INV_SEL_S 5 -/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC74_IN_SEL 0x0000001F -#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) -#define GPIO_FUNC74_IN_SEL_V 0x1F +/** GPIO_FUNC74_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) +/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC74_IN_SEL 0x0000001FU +#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) +#define GPIO_FUNC74_IN_SEL_V 0x0000001FU #define GPIO_FUNC74_IN_SEL_S 0 +/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) +#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC74_IN_INV_SEL_S 5 +/** GPIO_SIG74_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG74_IN_SEL (BIT(6)) +#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) +#define GPIO_SIG74_IN_SEL_V 0x00000001U +#define GPIO_SIG74_IN_SEL_S 6 -#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) -/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG75_IN_SEL (BIT(6)) -#define GPIO_SIG75_IN_SEL_M (BIT(6)) -#define GPIO_SIG75_IN_SEL_V 0x1 -#define GPIO_SIG75_IN_SEL_S 6 -/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC75_IN_INV_SEL_V 0x1 -#define GPIO_FUNC75_IN_INV_SEL_S 5 -/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC75_IN_SEL 0x0000001F -#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) -#define GPIO_FUNC75_IN_SEL_V 0x1F +/** GPIO_FUNC75_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) +/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC75_IN_SEL 0x0000001FU +#define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) +#define GPIO_FUNC75_IN_SEL_V 0x0000001FU #define GPIO_FUNC75_IN_SEL_S 0 +/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) +#define GPIO_FUNC75_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC75_IN_INV_SEL_S 5 +/** GPIO_SIG75_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG75_IN_SEL (BIT(6)) +#define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) +#define GPIO_SIG75_IN_SEL_V 0x00000001U +#define GPIO_SIG75_IN_SEL_S 6 -#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) -/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG76_IN_SEL (BIT(6)) -#define GPIO_SIG76_IN_SEL_M (BIT(6)) -#define GPIO_SIG76_IN_SEL_V 0x1 -#define GPIO_SIG76_IN_SEL_S 6 -/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC76_IN_INV_SEL_V 0x1 -#define GPIO_FUNC76_IN_INV_SEL_S 5 -/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC76_IN_SEL 0x0000001F -#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) -#define GPIO_FUNC76_IN_SEL_V 0x1F +/** GPIO_FUNC76_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) +/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC76_IN_SEL 0x0000001FU +#define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) +#define GPIO_FUNC76_IN_SEL_V 0x0000001FU #define GPIO_FUNC76_IN_SEL_S 0 +/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) +#define GPIO_FUNC76_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC76_IN_INV_SEL_S 5 +/** GPIO_SIG76_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG76_IN_SEL (BIT(6)) +#define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) +#define GPIO_SIG76_IN_SEL_V 0x00000001U +#define GPIO_SIG76_IN_SEL_S 6 -#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) -/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG77_IN_SEL (BIT(6)) -#define GPIO_SIG77_IN_SEL_M (BIT(6)) -#define GPIO_SIG77_IN_SEL_V 0x1 -#define GPIO_SIG77_IN_SEL_S 6 -/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC77_IN_INV_SEL_V 0x1 -#define GPIO_FUNC77_IN_INV_SEL_S 5 -/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC77_IN_SEL 0x0000001F -#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) -#define GPIO_FUNC77_IN_SEL_V 0x1F +/** GPIO_FUNC77_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC77_IN_SEL 0x0000001FU +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000001FU #define GPIO_FUNC77_IN_SEL_S 0 +/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC77_IN_INV_SEL_S 5 +/** GPIO_SIG77_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG77_IN_SEL (BIT(6)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001U +#define GPIO_SIG77_IN_SEL_S 6 -#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28C) -/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG78_IN_SEL (BIT(6)) -#define GPIO_SIG78_IN_SEL_M (BIT(6)) -#define GPIO_SIG78_IN_SEL_V 0x1 -#define GPIO_SIG78_IN_SEL_S 6 -/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC78_IN_INV_SEL_V 0x1 -#define GPIO_FUNC78_IN_INV_SEL_S 5 -/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC78_IN_SEL 0x0000001F -#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) -#define GPIO_FUNC78_IN_SEL_V 0x1F +/** GPIO_FUNC78_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) +/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC78_IN_SEL 0x0000001FU +#define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) +#define GPIO_FUNC78_IN_SEL_V 0x0000001FU #define GPIO_FUNC78_IN_SEL_S 0 +/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) +#define GPIO_FUNC78_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC78_IN_INV_SEL_S 5 +/** GPIO_SIG78_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG78_IN_SEL (BIT(6)) +#define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) +#define GPIO_SIG78_IN_SEL_V 0x00000001U +#define GPIO_SIG78_IN_SEL_S 6 -#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) -/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG79_IN_SEL (BIT(6)) -#define GPIO_SIG79_IN_SEL_M (BIT(6)) -#define GPIO_SIG79_IN_SEL_V 0x1 -#define GPIO_SIG79_IN_SEL_S 6 -/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC79_IN_INV_SEL_V 0x1 -#define GPIO_FUNC79_IN_INV_SEL_S 5 -/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC79_IN_SEL 0x0000001F -#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) -#define GPIO_FUNC79_IN_SEL_V 0x1F +/** GPIO_FUNC79_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) +/** GPIO_FUNC79_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC79_IN_SEL 0x0000001FU +#define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) +#define GPIO_FUNC79_IN_SEL_V 0x0000001FU #define GPIO_FUNC79_IN_SEL_S 0 +/** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) +#define GPIO_FUNC79_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC79_IN_INV_SEL_S 5 +/** GPIO_SIG79_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG79_IN_SEL (BIT(6)) +#define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) +#define GPIO_SIG79_IN_SEL_V 0x00000001U +#define GPIO_SIG79_IN_SEL_S 6 -#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) -/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG80_IN_SEL (BIT(6)) -#define GPIO_SIG80_IN_SEL_M (BIT(6)) -#define GPIO_SIG80_IN_SEL_V 0x1 -#define GPIO_SIG80_IN_SEL_S 6 -/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC80_IN_INV_SEL_V 0x1 -#define GPIO_FUNC80_IN_INV_SEL_S 5 -/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC80_IN_SEL 0x0000001F -#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) -#define GPIO_FUNC80_IN_SEL_V 0x1F +/** GPIO_FUNC80_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) +/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC80_IN_SEL 0x0000001FU +#define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) +#define GPIO_FUNC80_IN_SEL_V 0x0000001FU #define GPIO_FUNC80_IN_SEL_S 0 +/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) +#define GPIO_FUNC80_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC80_IN_INV_SEL_S 5 +/** GPIO_SIG80_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG80_IN_SEL (BIT(6)) +#define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) +#define GPIO_SIG80_IN_SEL_V 0x00000001U +#define GPIO_SIG80_IN_SEL_S 6 -#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) -/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG81_IN_SEL (BIT(6)) -#define GPIO_SIG81_IN_SEL_M (BIT(6)) -#define GPIO_SIG81_IN_SEL_V 0x1 -#define GPIO_SIG81_IN_SEL_S 6 -/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC81_IN_INV_SEL_V 0x1 -#define GPIO_FUNC81_IN_INV_SEL_S 5 -/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC81_IN_SEL 0x0000001F -#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) -#define GPIO_FUNC81_IN_SEL_V 0x1F +/** GPIO_FUNC81_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC81_IN_SEL 0x0000001FU +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000001FU #define GPIO_FUNC81_IN_SEL_S 0 +/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC81_IN_INV_SEL_S 5 +/** GPIO_SIG81_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG81_IN_SEL (BIT(6)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001U +#define GPIO_SIG81_IN_SEL_S 6 -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29C) -/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG82_IN_SEL (BIT(6)) -#define GPIO_SIG82_IN_SEL_M (BIT(6)) -#define GPIO_SIG82_IN_SEL_V 0x1 -#define GPIO_SIG82_IN_SEL_S 6 -/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC82_IN_INV_SEL_V 0x1 -#define GPIO_FUNC82_IN_INV_SEL_S 5 -/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC82_IN_SEL 0x0000001F -#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) -#define GPIO_FUNC82_IN_SEL_V 0x1F +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC82_IN_SEL 0x0000001FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000001FU #define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 5 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG82_IN_SEL (BIT(6)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 6 -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A0) -/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG83_IN_SEL (BIT(6)) -#define GPIO_SIG83_IN_SEL_M (BIT(6)) -#define GPIO_SIG83_IN_SEL_V 0x1 -#define GPIO_SIG83_IN_SEL_S 6 -/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC83_IN_INV_SEL_V 0x1 -#define GPIO_FUNC83_IN_INV_SEL_S 5 -/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC83_IN_SEL 0x0000001F -#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) -#define GPIO_FUNC83_IN_SEL_V 0x1F +/** GPIO_FUNC83_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC83_IN_SEL 0x0000001FU +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000001FU #define GPIO_FUNC83_IN_SEL_S 0 +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC83_IN_INV_SEL_S 5 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG83_IN_SEL (BIT(6)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001U +#define GPIO_SIG83_IN_SEL_S 6 -#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A4) -/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG84_IN_SEL (BIT(6)) -#define GPIO_SIG84_IN_SEL_M (BIT(6)) -#define GPIO_SIG84_IN_SEL_V 0x1 -#define GPIO_SIG84_IN_SEL_S 6 -/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC84_IN_INV_SEL_V 0x1 -#define GPIO_FUNC84_IN_INV_SEL_S 5 -/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC84_IN_SEL 0x0000001F -#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) -#define GPIO_FUNC84_IN_SEL_V 0x1F +/** GPIO_FUNC84_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) +/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC84_IN_SEL 0x0000001FU +#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) +#define GPIO_FUNC84_IN_SEL_V 0x0000001FU #define GPIO_FUNC84_IN_SEL_S 0 +/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) +#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC84_IN_INV_SEL_S 5 +/** GPIO_SIG84_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG84_IN_SEL (BIT(6)) +#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) +#define GPIO_SIG84_IN_SEL_V 0x00000001U +#define GPIO_SIG84_IN_SEL_S 6 -#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A8) -/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG85_IN_SEL (BIT(6)) -#define GPIO_SIG85_IN_SEL_M (BIT(6)) -#define GPIO_SIG85_IN_SEL_V 0x1 -#define GPIO_SIG85_IN_SEL_S 6 -/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC85_IN_INV_SEL_V 0x1 -#define GPIO_FUNC85_IN_INV_SEL_S 5 -/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC85_IN_SEL 0x0000001F -#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) -#define GPIO_FUNC85_IN_SEL_V 0x1F +/** GPIO_FUNC85_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) +/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC85_IN_SEL 0x0000001FU +#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) +#define GPIO_FUNC85_IN_SEL_V 0x0000001FU #define GPIO_FUNC85_IN_SEL_S 0 +/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) +#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC85_IN_INV_SEL_S 5 +/** GPIO_SIG85_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG85_IN_SEL (BIT(6)) +#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) +#define GPIO_SIG85_IN_SEL_V 0x00000001U +#define GPIO_SIG85_IN_SEL_S 6 -#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2AC) -/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG86_IN_SEL (BIT(6)) -#define GPIO_SIG86_IN_SEL_M (BIT(6)) -#define GPIO_SIG86_IN_SEL_V 0x1 -#define GPIO_SIG86_IN_SEL_S 6 -/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC86_IN_INV_SEL_V 0x1 -#define GPIO_FUNC86_IN_INV_SEL_S 5 -/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC86_IN_SEL 0x0000001F -#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) -#define GPIO_FUNC86_IN_SEL_V 0x1F +/** GPIO_FUNC86_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) +/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC86_IN_SEL 0x0000001FU +#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) +#define GPIO_FUNC86_IN_SEL_V 0x0000001FU #define GPIO_FUNC86_IN_SEL_S 0 +/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) +#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC86_IN_INV_SEL_S 5 +/** GPIO_SIG86_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG86_IN_SEL (BIT(6)) +#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) +#define GPIO_SIG86_IN_SEL_V 0x00000001U +#define GPIO_SIG86_IN_SEL_S 6 -#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B0) -/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG87_IN_SEL (BIT(6)) -#define GPIO_SIG87_IN_SEL_M (BIT(6)) -#define GPIO_SIG87_IN_SEL_V 0x1 -#define GPIO_SIG87_IN_SEL_S 6 -/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC87_IN_INV_SEL_V 0x1 -#define GPIO_FUNC87_IN_INV_SEL_S 5 -/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC87_IN_SEL 0x0000001F -#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) -#define GPIO_FUNC87_IN_SEL_V 0x1F +/** GPIO_FUNC87_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) +/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC87_IN_SEL 0x0000001FU +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000001FU #define GPIO_FUNC87_IN_SEL_S 0 +/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC87_IN_INV_SEL_S 5 +/** GPIO_SIG87_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG87_IN_SEL (BIT(6)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001U +#define GPIO_SIG87_IN_SEL_S 6 -#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B4) -/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG88_IN_SEL (BIT(6)) -#define GPIO_SIG88_IN_SEL_M (BIT(6)) -#define GPIO_SIG88_IN_SEL_V 0x1 -#define GPIO_SIG88_IN_SEL_S 6 -/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC88_IN_INV_SEL_V 0x1 -#define GPIO_FUNC88_IN_INV_SEL_S 5 -/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC88_IN_SEL 0x0000001F -#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) -#define GPIO_FUNC88_IN_SEL_V 0x1F +/** GPIO_FUNC88_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) +/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC88_IN_SEL 0x0000001FU +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000001FU #define GPIO_FUNC88_IN_SEL_S 0 +/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC88_IN_INV_SEL_S 5 +/** GPIO_SIG88_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG88_IN_SEL (BIT(6)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001U +#define GPIO_SIG88_IN_SEL_S 6 -#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B8) -/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG89_IN_SEL (BIT(6)) -#define GPIO_SIG89_IN_SEL_M (BIT(6)) -#define GPIO_SIG89_IN_SEL_V 0x1 -#define GPIO_SIG89_IN_SEL_S 6 -/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC89_IN_INV_SEL_V 0x1 -#define GPIO_FUNC89_IN_INV_SEL_S 5 -/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC89_IN_SEL 0x0000001F -#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) -#define GPIO_FUNC89_IN_SEL_V 0x1F +/** GPIO_FUNC89_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) +/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC89_IN_SEL 0x0000001FU +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000001FU #define GPIO_FUNC89_IN_SEL_S 0 +/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC89_IN_INV_SEL_S 5 +/** GPIO_SIG89_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG89_IN_SEL (BIT(6)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001U +#define GPIO_SIG89_IN_SEL_S 6 -#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2BC) -/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG90_IN_SEL (BIT(6)) -#define GPIO_SIG90_IN_SEL_M (BIT(6)) -#define GPIO_SIG90_IN_SEL_V 0x1 -#define GPIO_SIG90_IN_SEL_S 6 -/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC90_IN_INV_SEL_V 0x1 -#define GPIO_FUNC90_IN_INV_SEL_S 5 -/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC90_IN_SEL 0x0000001F -#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) -#define GPIO_FUNC90_IN_SEL_V 0x1F +/** GPIO_FUNC90_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) +/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC90_IN_SEL 0x0000001FU +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000001FU #define GPIO_FUNC90_IN_SEL_S 0 +/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC90_IN_INV_SEL_S 5 +/** GPIO_SIG90_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG90_IN_SEL (BIT(6)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001U +#define GPIO_SIG90_IN_SEL_S 6 -#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C0) -/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG91_IN_SEL (BIT(6)) -#define GPIO_SIG91_IN_SEL_M (BIT(6)) -#define GPIO_SIG91_IN_SEL_V 0x1 -#define GPIO_SIG91_IN_SEL_S 6 -/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC91_IN_INV_SEL_V 0x1 -#define GPIO_FUNC91_IN_INV_SEL_S 5 -/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC91_IN_SEL 0x0000001F -#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) -#define GPIO_FUNC91_IN_SEL_V 0x1F +/** GPIO_FUNC91_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) +/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC91_IN_SEL 0x0000001FU +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000001FU #define GPIO_FUNC91_IN_SEL_S 0 +/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC91_IN_INV_SEL_S 5 +/** GPIO_SIG91_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG91_IN_SEL (BIT(6)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001U +#define GPIO_SIG91_IN_SEL_S 6 -#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C4) -/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG92_IN_SEL (BIT(6)) -#define GPIO_SIG92_IN_SEL_M (BIT(6)) -#define GPIO_SIG92_IN_SEL_V 0x1 -#define GPIO_SIG92_IN_SEL_S 6 -/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC92_IN_INV_SEL_V 0x1 -#define GPIO_FUNC92_IN_INV_SEL_S 5 -/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC92_IN_SEL 0x0000001F -#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) -#define GPIO_FUNC92_IN_SEL_V 0x1F +/** GPIO_FUNC92_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC92_IN_SEL 0x0000001FU +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000001FU #define GPIO_FUNC92_IN_SEL_S 0 +/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC92_IN_INV_SEL_S 5 +/** GPIO_SIG92_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG92_IN_SEL (BIT(6)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001U +#define GPIO_SIG92_IN_SEL_S 6 -#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C8) -/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG93_IN_SEL (BIT(6)) -#define GPIO_SIG93_IN_SEL_M (BIT(6)) -#define GPIO_SIG93_IN_SEL_V 0x1 -#define GPIO_SIG93_IN_SEL_S 6 -/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC93_IN_INV_SEL_V 0x1 -#define GPIO_FUNC93_IN_INV_SEL_S 5 -/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC93_IN_SEL 0x0000001F -#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) -#define GPIO_FUNC93_IN_SEL_V 0x1F +/** GPIO_FUNC93_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) +/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC93_IN_SEL 0x0000001FU +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000001FU #define GPIO_FUNC93_IN_SEL_S 0 +/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC93_IN_INV_SEL_S 5 +/** GPIO_SIG93_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG93_IN_SEL (BIT(6)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001U +#define GPIO_SIG93_IN_SEL_S 6 -#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2CC) -/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG94_IN_SEL (BIT(6)) -#define GPIO_SIG94_IN_SEL_M (BIT(6)) -#define GPIO_SIG94_IN_SEL_V 0x1 -#define GPIO_SIG94_IN_SEL_S 6 -/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC94_IN_INV_SEL_V 0x1 -#define GPIO_FUNC94_IN_INV_SEL_S 5 -/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC94_IN_SEL 0x0000001F -#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) -#define GPIO_FUNC94_IN_SEL_V 0x1F +/** GPIO_FUNC94_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) +/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC94_IN_SEL 0x0000001FU +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000001FU #define GPIO_FUNC94_IN_SEL_S 0 +/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC94_IN_INV_SEL_S 5 +/** GPIO_SIG94_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG94_IN_SEL (BIT(6)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001U +#define GPIO_SIG94_IN_SEL_S 6 -#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D0) -/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG95_IN_SEL (BIT(6)) -#define GPIO_SIG95_IN_SEL_M (BIT(6)) -#define GPIO_SIG95_IN_SEL_V 0x1 -#define GPIO_SIG95_IN_SEL_S 6 -/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC95_IN_INV_SEL_V 0x1 -#define GPIO_FUNC95_IN_INV_SEL_S 5 -/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC95_IN_SEL 0x0000001F -#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) -#define GPIO_FUNC95_IN_SEL_V 0x1F +/** GPIO_FUNC95_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) +/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC95_IN_SEL 0x0000001FU +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000001FU #define GPIO_FUNC95_IN_SEL_S 0 +/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC95_IN_INV_SEL_S 5 +/** GPIO_SIG95_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG95_IN_SEL (BIT(6)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001U +#define GPIO_SIG95_IN_SEL_S 6 -#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D4) -/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG96_IN_SEL (BIT(6)) -#define GPIO_SIG96_IN_SEL_M (BIT(6)) -#define GPIO_SIG96_IN_SEL_V 0x1 -#define GPIO_SIG96_IN_SEL_S 6 -/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC96_IN_INV_SEL_V 0x1 -#define GPIO_FUNC96_IN_INV_SEL_S 5 -/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC96_IN_SEL 0x0000001F -#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) -#define GPIO_FUNC96_IN_SEL_V 0x1F +/** GPIO_FUNC96_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) +/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC96_IN_SEL 0x0000001FU +#define GPIO_FUNC96_IN_SEL_M (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S) +#define GPIO_FUNC96_IN_SEL_V 0x0000001FU #define GPIO_FUNC96_IN_SEL_S 0 +/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_M (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S) +#define GPIO_FUNC96_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC96_IN_INV_SEL_S 5 +/** GPIO_SIG96_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG96_IN_SEL (BIT(6)) +#define GPIO_SIG96_IN_SEL_M (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S) +#define GPIO_SIG96_IN_SEL_V 0x00000001U +#define GPIO_SIG96_IN_SEL_S 6 -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D8) -/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG97_IN_SEL (BIT(6)) -#define GPIO_SIG97_IN_SEL_M (BIT(6)) -#define GPIO_SIG97_IN_SEL_V 0x1 -#define GPIO_SIG97_IN_SEL_S 6 -/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC97_IN_INV_SEL_V 0x1 -#define GPIO_FUNC97_IN_INV_SEL_S 5 -/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC97_IN_SEL 0x0000001F -#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) -#define GPIO_FUNC97_IN_SEL_V 0x1F +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC97_IN_SEL 0x0000001FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000001FU #define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 5 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG97_IN_SEL (BIT(6)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 6 -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2DC) -/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG98_IN_SEL (BIT(6)) -#define GPIO_SIG98_IN_SEL_M (BIT(6)) -#define GPIO_SIG98_IN_SEL_V 0x1 -#define GPIO_SIG98_IN_SEL_S 6 -/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC98_IN_INV_SEL_V 0x1 -#define GPIO_FUNC98_IN_INV_SEL_S 5 -/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC98_IN_SEL 0x0000001F -#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) -#define GPIO_FUNC98_IN_SEL_V 0x1F +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC98_IN_SEL 0x0000001FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000001FU #define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 5 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG98_IN_SEL (BIT(6)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 6 -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E0) -/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG99_IN_SEL (BIT(6)) -#define GPIO_SIG99_IN_SEL_M (BIT(6)) -#define GPIO_SIG99_IN_SEL_V 0x1 -#define GPIO_SIG99_IN_SEL_S 6 -/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC99_IN_INV_SEL_V 0x1 -#define GPIO_FUNC99_IN_INV_SEL_S 5 -/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC99_IN_SEL 0x0000001F -#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) -#define GPIO_FUNC99_IN_SEL_V 0x1F +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC99_IN_SEL 0x0000001FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000001FU #define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 5 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG99_IN_SEL (BIT(6)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 6 -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E4) -/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG100_IN_SEL (BIT(6)) -#define GPIO_SIG100_IN_SEL_M (BIT(6)) -#define GPIO_SIG100_IN_SEL_V 0x1 -#define GPIO_SIG100_IN_SEL_S 6 -/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC100_IN_INV_SEL_V 0x1 -#define GPIO_FUNC100_IN_INV_SEL_S 5 -/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC100_IN_SEL 0x0000001F -#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) -#define GPIO_FUNC100_IN_SEL_V 0x1F +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC100_IN_SEL 0x0000001FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000001FU #define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 5 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG100_IN_SEL (BIT(6)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 6 -#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E8) -/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG101_IN_SEL (BIT(6)) -#define GPIO_SIG101_IN_SEL_M (BIT(6)) -#define GPIO_SIG101_IN_SEL_V 0x1 -#define GPIO_SIG101_IN_SEL_S 6 -/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC101_IN_INV_SEL_V 0x1 -#define GPIO_FUNC101_IN_INV_SEL_S 5 -/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC101_IN_SEL 0x0000001F -#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) -#define GPIO_FUNC101_IN_SEL_V 0x1F +/** GPIO_FUNC101_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC101_IN_SEL 0x0000001FU +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000001FU #define GPIO_FUNC101_IN_SEL_S 0 +/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC101_IN_INV_SEL_S 5 +/** GPIO_SIG101_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG101_IN_SEL (BIT(6)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001U +#define GPIO_SIG101_IN_SEL_S 6 -#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2EC) -/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG102_IN_SEL (BIT(6)) -#define GPIO_SIG102_IN_SEL_M (BIT(6)) -#define GPIO_SIG102_IN_SEL_V 0x1 -#define GPIO_SIG102_IN_SEL_S 6 -/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC102_IN_INV_SEL_V 0x1 -#define GPIO_FUNC102_IN_INV_SEL_S 5 -/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC102_IN_SEL 0x0000001F -#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) -#define GPIO_FUNC102_IN_SEL_V 0x1F +/** GPIO_FUNC102_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC102_IN_SEL 0x0000001FU +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000001FU #define GPIO_FUNC102_IN_SEL_S 0 +/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC102_IN_INV_SEL_S 5 +/** GPIO_SIG102_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG102_IN_SEL (BIT(6)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001U +#define GPIO_SIG102_IN_SEL_S 6 -#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F0) -/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG103_IN_SEL (BIT(6)) -#define GPIO_SIG103_IN_SEL_M (BIT(6)) -#define GPIO_SIG103_IN_SEL_V 0x1 -#define GPIO_SIG103_IN_SEL_S 6 -/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC103_IN_INV_SEL_V 0x1 -#define GPIO_FUNC103_IN_INV_SEL_S 5 -/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC103_IN_SEL 0x0000001F -#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) -#define GPIO_FUNC103_IN_SEL_V 0x1F +/** GPIO_FUNC103_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC103_IN_SEL 0x0000001FU +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000001FU #define GPIO_FUNC103_IN_SEL_S 0 +/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC103_IN_INV_SEL_S 5 +/** GPIO_SIG103_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG103_IN_SEL (BIT(6)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001U +#define GPIO_SIG103_IN_SEL_S 6 -#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F4) -/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG104_IN_SEL (BIT(6)) -#define GPIO_SIG104_IN_SEL_M (BIT(6)) -#define GPIO_SIG104_IN_SEL_V 0x1 -#define GPIO_SIG104_IN_SEL_S 6 -/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC104_IN_INV_SEL_V 0x1 -#define GPIO_FUNC104_IN_INV_SEL_S 5 -/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC104_IN_SEL 0x0000001F -#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) -#define GPIO_FUNC104_IN_SEL_V 0x1F +/** GPIO_FUNC104_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC104_IN_SEL 0x0000001FU +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000001FU #define GPIO_FUNC104_IN_SEL_S 0 +/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC104_IN_INV_SEL_S 5 +/** GPIO_SIG104_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG104_IN_SEL (BIT(6)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001U +#define GPIO_SIG104_IN_SEL_S 6 -#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F8) -/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG105_IN_SEL (BIT(6)) -#define GPIO_SIG105_IN_SEL_M (BIT(6)) -#define GPIO_SIG105_IN_SEL_V 0x1 -#define GPIO_SIG105_IN_SEL_S 6 -/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC105_IN_INV_SEL_V 0x1 -#define GPIO_FUNC105_IN_INV_SEL_S 5 -/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC105_IN_SEL 0x0000001F -#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) -#define GPIO_FUNC105_IN_SEL_V 0x1F +/** GPIO_FUNC105_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC105_IN_SEL 0x0000001FU +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000001FU #define GPIO_FUNC105_IN_SEL_S 0 +/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC105_IN_INV_SEL_S 5 +/** GPIO_SIG105_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG105_IN_SEL (BIT(6)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001U +#define GPIO_SIG105_IN_SEL_S 6 -#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2FC) -/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG106_IN_SEL (BIT(6)) -#define GPIO_SIG106_IN_SEL_M (BIT(6)) -#define GPIO_SIG106_IN_SEL_V 0x1 -#define GPIO_SIG106_IN_SEL_S 6 -/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC106_IN_INV_SEL_V 0x1 -#define GPIO_FUNC106_IN_INV_SEL_S 5 -/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC106_IN_SEL 0x0000001F -#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) -#define GPIO_FUNC106_IN_SEL_V 0x1F +/** GPIO_FUNC106_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC106_IN_SEL 0x0000001FU +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000001FU #define GPIO_FUNC106_IN_SEL_S 0 +/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC106_IN_INV_SEL_S 5 +/** GPIO_SIG106_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG106_IN_SEL (BIT(6)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001U +#define GPIO_SIG106_IN_SEL_S 6 -#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG107_IN_SEL (BIT(6)) -#define GPIO_SIG107_IN_SEL_M (BIT(6)) -#define GPIO_SIG107_IN_SEL_V 0x1 -#define GPIO_SIG107_IN_SEL_S 6 -/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC107_IN_INV_SEL_V 0x1 -#define GPIO_FUNC107_IN_INV_SEL_S 5 -/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC107_IN_SEL 0x0000001F -#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) -#define GPIO_FUNC107_IN_SEL_V 0x1F +/** GPIO_FUNC107_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC107_IN_SEL 0x0000001FU +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000001FU #define GPIO_FUNC107_IN_SEL_S 0 +/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC107_IN_INV_SEL_S 5 +/** GPIO_SIG107_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG107_IN_SEL (BIT(6)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001U +#define GPIO_SIG107_IN_SEL_S 6 -#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG108_IN_SEL (BIT(6)) -#define GPIO_SIG108_IN_SEL_M (BIT(6)) -#define GPIO_SIG108_IN_SEL_V 0x1 -#define GPIO_SIG108_IN_SEL_S 6 -/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC108_IN_INV_SEL_V 0x1 -#define GPIO_FUNC108_IN_INV_SEL_S 5 -/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC108_IN_SEL 0x0000001F -#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) -#define GPIO_FUNC108_IN_SEL_V 0x1F +/** GPIO_FUNC108_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC108_IN_SEL 0x0000001FU +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000001FU #define GPIO_FUNC108_IN_SEL_S 0 +/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC108_IN_INV_SEL_S 5 +/** GPIO_SIG108_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG108_IN_SEL (BIT(6)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001U +#define GPIO_SIG108_IN_SEL_S 6 -#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG109_IN_SEL (BIT(6)) -#define GPIO_SIG109_IN_SEL_M (BIT(6)) -#define GPIO_SIG109_IN_SEL_V 0x1 -#define GPIO_SIG109_IN_SEL_S 6 -/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC109_IN_INV_SEL_V 0x1 -#define GPIO_FUNC109_IN_INV_SEL_S 5 -/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC109_IN_SEL 0x0000001F -#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) -#define GPIO_FUNC109_IN_SEL_V 0x1F +/** GPIO_FUNC109_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC109_IN_SEL 0x0000001FU +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000001FU #define GPIO_FUNC109_IN_SEL_S 0 +/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC109_IN_INV_SEL_S 5 +/** GPIO_SIG109_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG109_IN_SEL (BIT(6)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001U +#define GPIO_SIG109_IN_SEL_S 6 -#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30C) -/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG110_IN_SEL (BIT(6)) -#define GPIO_SIG110_IN_SEL_M (BIT(6)) -#define GPIO_SIG110_IN_SEL_V 0x1 -#define GPIO_SIG110_IN_SEL_S 6 -/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC110_IN_INV_SEL_V 0x1 -#define GPIO_FUNC110_IN_INV_SEL_S 5 -/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC110_IN_SEL 0x0000001F -#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) -#define GPIO_FUNC110_IN_SEL_V 0x1F +/** GPIO_FUNC110_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC110_IN_SEL 0x0000001FU +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000001FU #define GPIO_FUNC110_IN_SEL_S 0 +/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC110_IN_INV_SEL_S 5 +/** GPIO_SIG110_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG110_IN_SEL (BIT(6)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001U +#define GPIO_SIG110_IN_SEL_S 6 -#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) -/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG111_IN_SEL (BIT(6)) -#define GPIO_SIG111_IN_SEL_M (BIT(6)) -#define GPIO_SIG111_IN_SEL_V 0x1 -#define GPIO_SIG111_IN_SEL_S 6 -/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC111_IN_INV_SEL_V 0x1 -#define GPIO_FUNC111_IN_INV_SEL_S 5 -/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC111_IN_SEL 0x0000001F -#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) -#define GPIO_FUNC111_IN_SEL_V 0x1F +/** GPIO_FUNC111_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC111_IN_SEL 0x0000001FU +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000001FU #define GPIO_FUNC111_IN_SEL_S 0 +/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC111_IN_INV_SEL_S 5 +/** GPIO_SIG111_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG111_IN_SEL (BIT(6)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001U +#define GPIO_SIG111_IN_SEL_S 6 -#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) -/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG112_IN_SEL (BIT(6)) -#define GPIO_SIG112_IN_SEL_M (BIT(6)) -#define GPIO_SIG112_IN_SEL_V 0x1 -#define GPIO_SIG112_IN_SEL_S 6 -/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC112_IN_INV_SEL_V 0x1 -#define GPIO_FUNC112_IN_INV_SEL_S 5 -/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC112_IN_SEL 0x0000001F -#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) -#define GPIO_FUNC112_IN_SEL_V 0x1F +/** GPIO_FUNC112_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC112_IN_SEL 0x0000001FU +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000001FU #define GPIO_FUNC112_IN_SEL_S 0 +/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC112_IN_INV_SEL_S 5 +/** GPIO_SIG112_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG112_IN_SEL (BIT(6)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001U +#define GPIO_SIG112_IN_SEL_S 6 -#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) -/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG113_IN_SEL (BIT(6)) -#define GPIO_SIG113_IN_SEL_M (BIT(6)) -#define GPIO_SIG113_IN_SEL_V 0x1 -#define GPIO_SIG113_IN_SEL_S 6 -/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC113_IN_INV_SEL_V 0x1 -#define GPIO_FUNC113_IN_INV_SEL_S 5 -/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC113_IN_SEL 0x0000001F -#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) -#define GPIO_FUNC113_IN_SEL_V 0x1F +/** GPIO_FUNC113_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC113_IN_SEL 0x0000001FU +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000001FU #define GPIO_FUNC113_IN_SEL_S 0 +/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC113_IN_INV_SEL_S 5 +/** GPIO_SIG113_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG113_IN_SEL (BIT(6)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001U +#define GPIO_SIG113_IN_SEL_S 6 -#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31C) -/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG114_IN_SEL (BIT(6)) -#define GPIO_SIG114_IN_SEL_M (BIT(6)) -#define GPIO_SIG114_IN_SEL_V 0x1 -#define GPIO_SIG114_IN_SEL_S 6 -/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC114_IN_INV_SEL_V 0x1 -#define GPIO_FUNC114_IN_INV_SEL_S 5 -/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC114_IN_SEL 0x0000001F -#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) -#define GPIO_FUNC114_IN_SEL_V 0x1F +/** GPIO_FUNC114_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) +/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC114_IN_SEL 0x0000001FU +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000001FU #define GPIO_FUNC114_IN_SEL_S 0 +/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC114_IN_INV_SEL_S 5 +/** GPIO_SIG114_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG114_IN_SEL (BIT(6)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001U +#define GPIO_SIG114_IN_SEL_S 6 -#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) -/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG115_IN_SEL (BIT(6)) -#define GPIO_SIG115_IN_SEL_M (BIT(6)) -#define GPIO_SIG115_IN_SEL_V 0x1 -#define GPIO_SIG115_IN_SEL_S 6 -/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC115_IN_INV_SEL_V 0x1 -#define GPIO_FUNC115_IN_INV_SEL_S 5 -/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC115_IN_SEL 0x0000001F -#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) -#define GPIO_FUNC115_IN_SEL_V 0x1F +/** GPIO_FUNC115_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC115_IN_SEL 0x0000001FU +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000001FU #define GPIO_FUNC115_IN_SEL_S 0 +/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC115_IN_INV_SEL_S 5 +/** GPIO_SIG115_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG115_IN_SEL (BIT(6)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001U +#define GPIO_SIG115_IN_SEL_S 6 -#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) -/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG116_IN_SEL (BIT(6)) -#define GPIO_SIG116_IN_SEL_M (BIT(6)) -#define GPIO_SIG116_IN_SEL_V 0x1 -#define GPIO_SIG116_IN_SEL_S 6 -/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC116_IN_INV_SEL_V 0x1 -#define GPIO_FUNC116_IN_INV_SEL_S 5 -/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC116_IN_SEL 0x0000001F -#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) -#define GPIO_FUNC116_IN_SEL_V 0x1F +/** GPIO_FUNC116_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC116_IN_SEL 0x0000001FU +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000001FU #define GPIO_FUNC116_IN_SEL_S 0 +/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC116_IN_INV_SEL_S 5 +/** GPIO_SIG116_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG116_IN_SEL (BIT(6)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001U +#define GPIO_SIG116_IN_SEL_S 6 -#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) -/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG117_IN_SEL (BIT(6)) -#define GPIO_SIG117_IN_SEL_M (BIT(6)) -#define GPIO_SIG117_IN_SEL_V 0x1 -#define GPIO_SIG117_IN_SEL_S 6 -/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC117_IN_INV_SEL_V 0x1 -#define GPIO_FUNC117_IN_INV_SEL_S 5 -/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC117_IN_SEL 0x0000001F -#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) -#define GPIO_FUNC117_IN_SEL_V 0x1F +/** GPIO_FUNC117_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC117_IN_SEL 0x0000001FU +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000001FU #define GPIO_FUNC117_IN_SEL_S 0 +/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC117_IN_INV_SEL_S 5 +/** GPIO_SIG117_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG117_IN_SEL (BIT(6)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001U +#define GPIO_SIG117_IN_SEL_S 6 -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32C) -/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG118_IN_SEL (BIT(6)) -#define GPIO_SIG118_IN_SEL_M (BIT(6)) -#define GPIO_SIG118_IN_SEL_V 0x1 -#define GPIO_SIG118_IN_SEL_S 6 -/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC118_IN_INV_SEL_V 0x1 -#define GPIO_FUNC118_IN_INV_SEL_S 5 -/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC118_IN_SEL 0x0000001F -#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) -#define GPIO_FUNC118_IN_SEL_V 0x1F +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC118_IN_SEL 0x0000001FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000001FU #define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 5 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG118_IN_SEL (BIT(6)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 6 -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG119_IN_SEL (BIT(6)) -#define GPIO_SIG119_IN_SEL_M (BIT(6)) -#define GPIO_SIG119_IN_SEL_V 0x1 -#define GPIO_SIG119_IN_SEL_S 6 -/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC119_IN_INV_SEL_V 0x1 -#define GPIO_FUNC119_IN_INV_SEL_S 5 -/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC119_IN_SEL 0x0000001F -#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) -#define GPIO_FUNC119_IN_SEL_V 0x1F +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC119_IN_SEL 0x0000001FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000001FU #define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 5 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG119_IN_SEL (BIT(6)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 6 -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG120_IN_SEL (BIT(6)) -#define GPIO_SIG120_IN_SEL_M (BIT(6)) -#define GPIO_SIG120_IN_SEL_V 0x1 -#define GPIO_SIG120_IN_SEL_S 6 -/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC120_IN_INV_SEL_V 0x1 -#define GPIO_FUNC120_IN_INV_SEL_S 5 -/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC120_IN_SEL 0x0000001F -#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) -#define GPIO_FUNC120_IN_SEL_V 0x1F +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC120_IN_SEL 0x0000001FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000001FU #define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 5 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG120_IN_SEL (BIT(6)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 6 -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG121_IN_SEL (BIT(6)) -#define GPIO_SIG121_IN_SEL_M (BIT(6)) -#define GPIO_SIG121_IN_SEL_V 0x1 -#define GPIO_SIG121_IN_SEL_S 6 -/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC121_IN_INV_SEL_V 0x1 -#define GPIO_FUNC121_IN_INV_SEL_S 5 -/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC121_IN_SEL 0x0000001F -#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) -#define GPIO_FUNC121_IN_SEL_V 0x1F +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC121_IN_SEL 0x0000001FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000001FU #define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 5 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG121_IN_SEL (BIT(6)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 6 -#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33C) -/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG122_IN_SEL (BIT(6)) -#define GPIO_SIG122_IN_SEL_M (BIT(6)) -#define GPIO_SIG122_IN_SEL_V 0x1 -#define GPIO_SIG122_IN_SEL_S 6 -/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC122_IN_INV_SEL_V 0x1 -#define GPIO_FUNC122_IN_INV_SEL_S 5 -/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC122_IN_SEL 0x0000001F -#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) -#define GPIO_FUNC122_IN_SEL_V 0x1F +/** GPIO_FUNC122_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC122_IN_SEL 0x0000001FU +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000001FU #define GPIO_FUNC122_IN_SEL_S 0 +/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC122_IN_INV_SEL_S 5 +/** GPIO_SIG122_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG122_IN_SEL (BIT(6)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001U +#define GPIO_SIG122_IN_SEL_S 6 -#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG123_IN_SEL (BIT(6)) -#define GPIO_SIG123_IN_SEL_M (BIT(6)) -#define GPIO_SIG123_IN_SEL_V 0x1 -#define GPIO_SIG123_IN_SEL_S 6 -/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC123_IN_INV_SEL_V 0x1 -#define GPIO_FUNC123_IN_INV_SEL_S 5 -/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC123_IN_SEL 0x0000001F -#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) -#define GPIO_FUNC123_IN_SEL_V 0x1F +/** GPIO_FUNC123_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC123_IN_SEL 0x0000001FU +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000001FU #define GPIO_FUNC123_IN_SEL_S 0 +/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC123_IN_INV_SEL_S 5 +/** GPIO_SIG123_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG123_IN_SEL (BIT(6)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001U +#define GPIO_SIG123_IN_SEL_S 6 -#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG124_IN_SEL (BIT(6)) -#define GPIO_SIG124_IN_SEL_M (BIT(6)) -#define GPIO_SIG124_IN_SEL_V 0x1 -#define GPIO_SIG124_IN_SEL_S 6 -/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC124_IN_INV_SEL_V 0x1 -#define GPIO_FUNC124_IN_INV_SEL_S 5 -/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC124_IN_SEL 0x0000001F -#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) -#define GPIO_FUNC124_IN_SEL_V 0x1F +/** GPIO_FUNC124_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC124_IN_SEL 0x0000001FU +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000001FU #define GPIO_FUNC124_IN_SEL_S 0 +/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC124_IN_INV_SEL_S 5 +/** GPIO_SIG124_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG124_IN_SEL (BIT(6)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001U +#define GPIO_SIG124_IN_SEL_S 6 -#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG125_IN_SEL (BIT(6)) -#define GPIO_SIG125_IN_SEL_M (BIT(6)) -#define GPIO_SIG125_IN_SEL_V 0x1 -#define GPIO_SIG125_IN_SEL_S 6 -/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC125_IN_INV_SEL_V 0x1 -#define GPIO_FUNC125_IN_INV_SEL_S 5 -/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC125_IN_SEL 0x0000001F -#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) -#define GPIO_FUNC125_IN_SEL_V 0x1F +/** GPIO_FUNC125_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/** GPIO_FUNC125_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC125_IN_SEL 0x0000001FU +#define GPIO_FUNC125_IN_SEL_M (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S) +#define GPIO_FUNC125_IN_SEL_V 0x0000001FU #define GPIO_FUNC125_IN_SEL_S 0 +/** GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_M (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S) +#define GPIO_FUNC125_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC125_IN_INV_SEL_S 5 +/** GPIO_SIG125_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG125_IN_SEL (BIT(6)) +#define GPIO_SIG125_IN_SEL_M (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S) +#define GPIO_SIG125_IN_SEL_V 0x00000001U +#define GPIO_SIG125_IN_SEL_S 6 -#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34C) -/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG126_IN_SEL (BIT(6)) -#define GPIO_SIG126_IN_SEL_M (BIT(6)) -#define GPIO_SIG126_IN_SEL_V 0x1 -#define GPIO_SIG126_IN_SEL_S 6 -/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC126_IN_INV_SEL_V 0x1 -#define GPIO_FUNC126_IN_INV_SEL_S 5 -/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC126_IN_SEL 0x0000001F -#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) -#define GPIO_FUNC126_IN_SEL_V 0x1F +/** GPIO_FUNC126_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) +/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC126_IN_SEL 0x0000001FU +#define GPIO_FUNC126_IN_SEL_M (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S) +#define GPIO_FUNC126_IN_SEL_V 0x0000001FU #define GPIO_FUNC126_IN_SEL_S 0 +/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_M (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S) +#define GPIO_FUNC126_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC126_IN_INV_SEL_S 5 +/** GPIO_SIG126_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG126_IN_SEL (BIT(6)) +#define GPIO_SIG126_IN_SEL_M (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S) +#define GPIO_SIG126_IN_SEL_V 0x00000001U +#define GPIO_SIG126_IN_SEL_S 6 -#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_SIG127_IN_SEL (BIT(6)) -#define GPIO_SIG127_IN_SEL_M (BIT(6)) -#define GPIO_SIG127_IN_SEL_V 0x1 -#define GPIO_SIG127_IN_SEL_S 6 -/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC127_IN_INV_SEL_V 0x1 -#define GPIO_FUNC127_IN_INV_SEL_S 5 -/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: .*/ -#define GPIO_FUNC127_IN_SEL 0x0000001F -#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) -#define GPIO_FUNC127_IN_SEL_V 0x1F +/** GPIO_FUNC127_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC127_IN_SEL 0x0000001FU +#define GPIO_FUNC127_IN_SEL_M (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S) +#define GPIO_FUNC127_IN_SEL_V 0x0000001FU #define GPIO_FUNC127_IN_SEL_S 0 +/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_M (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S) +#define GPIO_FUNC127_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC127_IN_INV_SEL_S 5 +/** GPIO_SIG127_IN_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG127_IN_SEL (BIT(6)) +#define GPIO_SIG127_IN_SEL_M (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S) +#define GPIO_SIG127_IN_SEL_V 0x00000001U +#define GPIO_SIG127_IN_SEL_S 6 -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) -/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC0_OEN_INV_SEL_S 10 -/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC0_OEN_SEL (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_V 0x1 -#define GPIO_FUNC0_OEN_SEL_S 9 -/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC0_OUT_INV_SEL_S 8 -/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC0_OUT_SEL 0x000000FF -#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) -#define GPIO_FUNC0_OUT_SEL_V 0xFF +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/** GPIO_FUNC0_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC0_OUT_SEL 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU #define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_SEL_S 9 +/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_INV_SEL_S 10 -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) -/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC1_OEN_INV_SEL_S 10 -/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC1_OEN_SEL (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_V 0x1 -#define GPIO_FUNC1_OEN_SEL_S 9 -/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC1_OUT_INV_SEL_S 8 -/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC1_OUT_SEL 0x000000FF -#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) -#define GPIO_FUNC1_OUT_SEL_V 0xFF +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/** GPIO_FUNC1_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC1_OUT_SEL 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU #define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_SEL_S 9 +/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_INV_SEL_S 10 -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55C) -/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC2_OEN_INV_SEL_S 10 -/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC2_OEN_SEL (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_V 0x1 -#define GPIO_FUNC2_OEN_SEL_S 9 -/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC2_OUT_INV_SEL_S 8 -/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC2_OUT_SEL 0x000000FF -#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) -#define GPIO_FUNC2_OUT_SEL_V 0xFF +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) +/** GPIO_FUNC2_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC2_OUT_SEL 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU #define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_SEL_S 9 +/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_INV_SEL_S 10 -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) -/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC3_OEN_INV_SEL_S 10 -/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC3_OEN_SEL (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_V 0x1 -#define GPIO_FUNC3_OEN_SEL_S 9 -/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC3_OUT_INV_SEL_S 8 -/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC3_OUT_SEL 0x000000FF -#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) -#define GPIO_FUNC3_OUT_SEL_V 0xFF +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/** GPIO_FUNC3_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC3_OUT_SEL 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU #define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_SEL_S 9 +/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_INV_SEL_S 10 -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) -/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC4_OEN_INV_SEL_S 10 -/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC4_OEN_SEL (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_V 0x1 -#define GPIO_FUNC4_OEN_SEL_S 9 -/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC4_OUT_INV_SEL_S 8 -/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC4_OUT_SEL 0x000000FF -#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) -#define GPIO_FUNC4_OUT_SEL_V 0xFF +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/** GPIO_FUNC4_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC4_OUT_SEL 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU #define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_SEL_S 9 +/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_INV_SEL_S 10 -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) -/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC5_OEN_INV_SEL_S 10 -/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC5_OEN_SEL (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_V 0x1 -#define GPIO_FUNC5_OEN_SEL_S 9 -/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC5_OUT_INV_SEL_S 8 -/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC5_OUT_SEL 0x000000FF -#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) -#define GPIO_FUNC5_OUT_SEL_V 0xFF +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/** GPIO_FUNC5_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC5_OUT_SEL 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU #define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_SEL_S 9 +/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_INV_SEL_S 10 -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56C) -/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC6_OEN_INV_SEL_S 10 -/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC6_OEN_SEL (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_V 0x1 -#define GPIO_FUNC6_OEN_SEL_S 9 -/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC6_OUT_INV_SEL_S 8 -/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC6_OUT_SEL 0x000000FF -#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) -#define GPIO_FUNC6_OUT_SEL_V 0xFF +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) +/** GPIO_FUNC6_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC6_OUT_SEL 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU #define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_SEL_S 9 +/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_INV_SEL_S 10 -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) -/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC7_OEN_INV_SEL_S 10 -/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC7_OEN_SEL (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_V 0x1 -#define GPIO_FUNC7_OEN_SEL_S 9 -/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC7_OUT_INV_SEL_S 8 -/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC7_OUT_SEL 0x000000FF -#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) -#define GPIO_FUNC7_OUT_SEL_V 0xFF +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/** GPIO_FUNC7_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC7_OUT_SEL 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU #define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_SEL_S 9 +/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_INV_SEL_S 10 -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) -/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC8_OEN_INV_SEL_S 10 -/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC8_OEN_SEL (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_V 0x1 -#define GPIO_FUNC8_OEN_SEL_S 9 -/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC8_OUT_INV_SEL_S 8 -/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC8_OUT_SEL 0x000000FF -#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) -#define GPIO_FUNC8_OUT_SEL_V 0xFF +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/** GPIO_FUNC8_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC8_OUT_SEL 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU #define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_SEL_S 9 +/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_INV_SEL_S 10 -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) -/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC9_OEN_INV_SEL_S 10 -/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC9_OEN_SEL (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_V 0x1 -#define GPIO_FUNC9_OEN_SEL_S 9 -/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC9_OUT_INV_SEL_S 8 -/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC9_OUT_SEL 0x000000FF -#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) -#define GPIO_FUNC9_OUT_SEL_V 0xFF +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/** GPIO_FUNC9_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC9_OUT_SEL 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU #define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_SEL_S 9 +/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_INV_SEL_S 10 -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57C) -/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC10_OEN_INV_SEL_S 10 -/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC10_OEN_SEL (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_V 0x1 -#define GPIO_FUNC10_OEN_SEL_S 9 -/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC10_OUT_INV_SEL_S 8 -/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC10_OUT_SEL 0x000000FF -#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) -#define GPIO_FUNC10_OUT_SEL_V 0xFF +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) +/** GPIO_FUNC10_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC10_OUT_SEL 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU #define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_SEL_S 9 +/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_INV_SEL_S 10 -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) -/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC11_OEN_INV_SEL_S 10 -/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC11_OEN_SEL (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_V 0x1 -#define GPIO_FUNC11_OEN_SEL_S 9 -/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC11_OUT_INV_SEL_S 8 -/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC11_OUT_SEL 0x000000FF -#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) -#define GPIO_FUNC11_OUT_SEL_V 0xFF +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/** GPIO_FUNC11_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC11_OUT_SEL 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU #define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_SEL_S 9 +/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_INV_SEL_S 10 -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) -/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC12_OEN_INV_SEL_S 10 -/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC12_OEN_SEL (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_V 0x1 -#define GPIO_FUNC12_OEN_SEL_S 9 -/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC12_OUT_INV_SEL_S 8 -/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC12_OUT_SEL 0x000000FF -#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) -#define GPIO_FUNC12_OUT_SEL_V 0xFF +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/** GPIO_FUNC12_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC12_OUT_SEL 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU #define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_SEL_S 9 +/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_INV_SEL_S 10 -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) -/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC13_OEN_INV_SEL_S 10 -/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC13_OEN_SEL (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_V 0x1 -#define GPIO_FUNC13_OEN_SEL_S 9 -/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC13_OUT_INV_SEL_S 8 -/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC13_OUT_SEL 0x000000FF -#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) -#define GPIO_FUNC13_OUT_SEL_V 0xFF +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/** GPIO_FUNC13_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC13_OUT_SEL 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU #define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_SEL_S 9 +/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_INV_SEL_S 10 -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58C) -/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC14_OEN_INV_SEL_S 10 -/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC14_OEN_SEL (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_V 0x1 -#define GPIO_FUNC14_OEN_SEL_S 9 -/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC14_OUT_INV_SEL_S 8 -/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC14_OUT_SEL 0x000000FF -#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) -#define GPIO_FUNC14_OUT_SEL_V 0xFF +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) +/** GPIO_FUNC14_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC14_OUT_SEL 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU #define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_SEL_S 9 +/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_INV_SEL_S 10 -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) -/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC15_OEN_INV_SEL_S 10 -/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC15_OEN_SEL (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_V 0x1 -#define GPIO_FUNC15_OEN_SEL_S 9 -/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC15_OUT_INV_SEL_S 8 -/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC15_OUT_SEL 0x000000FF -#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) -#define GPIO_FUNC15_OUT_SEL_V 0xFF +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/** GPIO_FUNC15_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC15_OUT_SEL 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU #define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_SEL_S 9 +/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_INV_SEL_S 10 -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) -/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC16_OEN_INV_SEL_S 10 -/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC16_OEN_SEL (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_V 0x1 -#define GPIO_FUNC16_OEN_SEL_S 9 -/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC16_OUT_INV_SEL_S 8 -/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC16_OUT_SEL 0x000000FF -#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) -#define GPIO_FUNC16_OUT_SEL_V 0xFF +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/** GPIO_FUNC16_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC16_OUT_SEL 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU #define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_SEL_S 9 +/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_INV_SEL_S 10 -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) -/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC17_OEN_INV_SEL_S 10 -/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC17_OEN_SEL (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_V 0x1 -#define GPIO_FUNC17_OEN_SEL_S 9 -/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC17_OUT_INV_SEL_S 8 -/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC17_OUT_SEL 0x000000FF -#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) -#define GPIO_FUNC17_OUT_SEL_V 0xFF +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/** GPIO_FUNC17_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC17_OUT_SEL 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU #define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_SEL_S 9 +/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_INV_SEL_S 10 -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59C) -/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC18_OEN_INV_SEL_S 10 -/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC18_OEN_SEL (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_V 0x1 -#define GPIO_FUNC18_OEN_SEL_S 9 -/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC18_OUT_INV_SEL_S 8 -/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC18_OUT_SEL 0x000000FF -#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) -#define GPIO_FUNC18_OUT_SEL_V 0xFF +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) +/** GPIO_FUNC18_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC18_OUT_SEL 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU #define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_SEL_S 9 +/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_INV_SEL_S 10 -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A0) -/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC19_OEN_INV_SEL_S 10 -/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC19_OEN_SEL (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_V 0x1 -#define GPIO_FUNC19_OEN_SEL_S 9 -/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC19_OUT_INV_SEL_S 8 -/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC19_OUT_SEL 0x000000FF -#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) -#define GPIO_FUNC19_OUT_SEL_V 0xFF +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) +/** GPIO_FUNC19_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC19_OUT_SEL 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU #define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_SEL_S 9 +/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_INV_SEL_S 10 -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A4) -/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC20_OEN_INV_SEL_S 10 -/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC20_OEN_SEL (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_V 0x1 -#define GPIO_FUNC20_OEN_SEL_S 9 -/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC20_OUT_INV_SEL_S 8 -/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC20_OUT_SEL 0x000000FF -#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) -#define GPIO_FUNC20_OUT_SEL_V 0xFF +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) +/** GPIO_FUNC20_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC20_OUT_SEL 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU #define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_SEL_S 9 +/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_INV_SEL_S 10 -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A8) -/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC21_OEN_INV_SEL_S 10 -/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC21_OEN_SEL (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_V 0x1 -#define GPIO_FUNC21_OEN_SEL_S 9 -/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC21_OUT_INV_SEL_S 8 -/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC21_OUT_SEL 0x000000FF -#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) -#define GPIO_FUNC21_OUT_SEL_V 0xFF +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) +/** GPIO_FUNC21_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC21_OUT_SEL 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU #define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_SEL_S 9 +/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_INV_SEL_S 10 -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5AC) -/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC22_OEN_INV_SEL_S 10 -/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC22_OEN_SEL (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_V 0x1 -#define GPIO_FUNC22_OEN_SEL_S 9 -/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC22_OUT_INV_SEL_S 8 -/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC22_OUT_SEL 0x000000FF -#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) -#define GPIO_FUNC22_OUT_SEL_V 0xFF +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) +/** GPIO_FUNC22_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC22_OUT_SEL 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU #define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_SEL_S 9 +/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_INV_SEL_S 10 -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B0) -/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC23_OEN_INV_SEL_S 10 -/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC23_OEN_SEL (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_V 0x1 -#define GPIO_FUNC23_OEN_SEL_S 9 -/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC23_OUT_INV_SEL_S 8 -/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC23_OUT_SEL 0x000000FF -#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) -#define GPIO_FUNC23_OUT_SEL_V 0xFF +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) +/** GPIO_FUNC23_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC23_OUT_SEL 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU #define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_SEL_S 9 +/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_INV_SEL_S 10 -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B4) -/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC24_OEN_INV_SEL_S 10 -/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC24_OEN_SEL (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_V 0x1 -#define GPIO_FUNC24_OEN_SEL_S 9 -/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC24_OUT_INV_SEL_S 8 -/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC24_OUT_SEL 0x000000FF -#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) -#define GPIO_FUNC24_OUT_SEL_V 0xFF +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) +/** GPIO_FUNC24_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC24_OUT_SEL 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU #define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_SEL_S 9 +/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_INV_SEL_S 10 -#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B8) -/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC25_OEN_INV_SEL_S 10 -/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC25_OEN_SEL (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_V 0x1 -#define GPIO_FUNC25_OEN_SEL_S 9 -/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC25_OUT_INV_SEL_S 8 -/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC25_OUT_SEL 0x000000FF -#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) -#define GPIO_FUNC25_OUT_SEL_V 0xFF +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) +/** GPIO_FUNC25_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU #define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_SEL_S 9 +/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_INV_SEL_S 10 -#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5BC) -/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC26_OEN_INV_SEL_S 10 -/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC26_OEN_SEL (BIT(9)) -#define GPIO_FUNC26_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC26_OEN_SEL_V 0x1 -#define GPIO_FUNC26_OEN_SEL_S 9 -/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC26_OUT_INV_SEL_S 8 -/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC26_OUT_SEL 0x000000FF -#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) -#define GPIO_FUNC26_OUT_SEL_V 0xFF +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) +/** GPIO_FUNC26_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU #define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_SEL_S 9 +/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_INV_SEL_S 10 -#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C0) -/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC27_OEN_INV_SEL_S 10 -/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC27_OEN_SEL (BIT(9)) -#define GPIO_FUNC27_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC27_OEN_SEL_V 0x1 -#define GPIO_FUNC27_OEN_SEL_S 9 -/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC27_OUT_INV_SEL_S 8 -/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC27_OUT_SEL 0x000000FF -#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) -#define GPIO_FUNC27_OUT_SEL_V 0xFF +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) +/** GPIO_FUNC27_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU #define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_SEL_S 9 +/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_INV_SEL_S 10 -#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C4) -/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC28_OEN_INV_SEL_S 10 -/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC28_OEN_SEL (BIT(9)) -#define GPIO_FUNC28_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC28_OEN_SEL_V 0x1 -#define GPIO_FUNC28_OEN_SEL_S 9 -/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC28_OUT_INV_SEL_S 8 -/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC28_OUT_SEL 0x000000FF -#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) -#define GPIO_FUNC28_OUT_SEL_V 0xFF +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) +/** GPIO_FUNC28_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU #define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_SEL_S 9 +/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_INV_SEL_S 10 -#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C8) -/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC29_OEN_INV_SEL_S 10 -/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC29_OEN_SEL (BIT(9)) -#define GPIO_FUNC29_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC29_OEN_SEL_V 0x1 -#define GPIO_FUNC29_OEN_SEL_S 9 -/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: .*/ -#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC29_OUT_INV_SEL_S 8 -/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ -/*description: .*/ -#define GPIO_FUNC29_OUT_SEL 0x000000FF -#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) -#define GPIO_FUNC29_OUT_SEL_V 0xFF +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) +/** GPIO_FUNC29_OUT_SEL : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU #define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_SEL_S 9 +/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_INV_SEL_S 10 -#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62C) -/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ #define GPIO_CLK_EN (BIT(0)) -#define GPIO_CLK_EN_M (BIT(0)) -#define GPIO_CLK_EN_V 0x1 +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U #define GPIO_CLK_EN_S 0 -#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) -/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2109090 ; */ -/*description: .*/ -#define GPIO_DATE 0x0FFFFFFF -#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) -#define GPIO_DATE_V 0xFFFFFFF -#define GPIO_DATE_S 0 +/** GPIO_REG_DATE_REG register + * GPIO version register + */ +#define GPIO_REG_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) +/** GPIO_REG_DATE : R/W; bitpos: [27:0]; default: 34640016; + * version register + */ +#define GPIO_REG_DATE 0x0FFFFFFFU +#define GPIO_REG_DATE_M (GPIO_REG_DATE_V << GPIO_REG_DATE_S) +#define GPIO_REG_DATE_V 0x0FFFFFFFU +#define GPIO_REG_DATE_S 0 #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/rev2/soc/gpio_struct.h b/components/soc/esp32h2/include/rev2/soc/gpio_struct.h new file mode 100644 index 0000000000..7e1516e42c --- /dev/null +++ b/components/soc/esp32h2/include/rev2/soc/gpio_struct.h @@ -0,0 +1,420 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration register */ +/** Type of bt_select register + * GPIO bit select register + */ +typedef union { + struct { + /** bt_sel : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ + uint32_t bt_sel:32; + }; + uint32_t val; +} gpio_bt_select_reg_t; + +/** Type of out register + * GPIO output register for GPIO0-29 + */ +typedef union { + struct { + /** out_data_orig : R/W/WS/WC; bitpos: [29:0]; default: 0; + * GPIO output register for GPIO0-29 + */ + uint32_t out_data_orig:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register for GPIO0-29 + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [29:0]; default: 0; + * GPIO output set register for GPIO0-29 + */ + uint32_t out_w1ts:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register for GPIO0-29 + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [29:0]; default: 0; + * GPIO output clear register for GPIO0-29 + */ + uint32_t out_w1tc:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of sdio_select register + * GPIO sdio select register + */ +typedef union { + struct { + /** sdio_sel : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ + uint32_t sdio_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_sdio_select_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-29 + */ +typedef union { + struct { + /** enable_data : R/W/SS; bitpos: [29:0]; default: 0; + * GPIO output enable register for GPIO0-29 + */ + uint32_t enable_data:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register for GPIO0-29 + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [29:0]; default: 0; + * GPIO output enable set register for GPIO0-29 + */ + uint32_t enable_w1ts:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register for GPIO0-29 + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [29:0]; default: 0; + * GPIO output enable clear register for GPIO0-29 + */ + uint32_t enable_w1tc:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of strap register + * pad strapping register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-29 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [29:0]; default: 0; + * GPIO input register for GPIO0-29 + */ + uint32_t in_data_next:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_in_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-29 + */ +typedef union { + struct { + /** status_interrupt : R/W/SS; bitpos: [29:0]; default: 0; + * GPIO interrupt status register for GPIO0-29 + */ + uint32_t status_interrupt:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register for GPIO0-29 + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [29:0]; default: 0; + * GPIO interrupt status set register for GPIO0-29 + */ + uint32_t status_w1ts:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register for GPIO0-29 + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [29:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-29 + */ + uint32_t status_w1tc:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of pin register + * GPIO pin configuration register + */ +typedef union { + struct { + /** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pin_sync2_bypass:2; + /** pin_pad_driver : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ + uint32_t pin_pad_driver:1; + /** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pin_sync1_bypass:2; + uint32_t reserved_5:2; + /** pin_int_type : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ + uint32_t pin_int_type:3; + /** pin_wakeup_enable : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ + uint32_t pin_wakeup_enable:1; + /** pin_config : R/W; bitpos: [12:11]; default: 0; + * reserved + */ + uint32_t pin_config:2; + /** pin_int_ena : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ + uint32_t pin_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-29 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-29 + */ + uint32_t status_interrupt_next:32; + }; + uint32_t val; +} gpio_status_next_reg_t; + +/** Type of func_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func_in_sel : R/W; bitpos: [4:0]; default: 0; + * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func_in_sel:5; + /** func_in_inv_sel : R/W; bitpos: [5]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func_in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [6]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig_in_sel:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gpio_func_in_sel_cfg_reg_t; + +/** Type of func_out_sel_cfg register + * GPIO output function select register + */ +typedef union { + struct { + /** func_out_sel : R/W; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ + uint32_t func_out_sel:8; + /** func_out_inv_sel : R/W; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ + uint32_t func_out_inv_sel:1; + /** func_oen_sel : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ + uint32_t func_oen_sel:1; + /** func_oen_inv_sel : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ + uint32_t func_oen_inv_sel:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} gpio_func_out_sel_cfg_reg_t; + +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + +/** Type of reg_date register + * GPIO version register + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 34640016; + * version register + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_reg_date_reg_t; + + +/** Group: interrupt register */ +/** Type of pcpu_int register + * GPIO PRO_CPU interrupt status register for GPIO0-29 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [29:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-29 + */ + uint32_t procpu_int:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_pcpu_int_reg_t; + +/** Type of pcpu_nmi_int register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 + */ +typedef union { + struct { + /** procpu_nmi_int : RO; bitpos: [29:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 + */ + uint32_t procpu_nmi_int:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_pcpu_nmi_int_reg_t; + +/** Type of cpusdio_int register + * GPIO CPUSDIO interrupt status register for GPIO0-29 + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [29:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-29 + */ + uint32_t sdio_int:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_cpusdio_int_reg_t; + + +typedef struct { + volatile gpio_bt_select_reg_t bt_select; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + uint32_t reserved_010[3]; + volatile gpio_sdio_select_reg_t sdio_select; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + uint32_t reserved_02c[3]; + volatile gpio_strap_reg_t strap; + volatile gpio_in_reg_t in; + uint32_t reserved_040; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + uint32_t reserved_050[3]; + volatile gpio_pcpu_int_reg_t pcpu_int; + volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; + volatile gpio_cpusdio_int_reg_t cpusdio_int; + uint32_t reserved_068[3]; + volatile gpio_pin_reg_t pin[30]; + uint32_t reserved_0ec[24]; + volatile gpio_status_next_reg_t status_next; + uint32_t reserved_150; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; + uint32_t reserved_354[128]; + volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[30]; + uint32_t reserved_5cc[24]; + volatile gpio_clock_gate_reg_t clock_gate; + uint32_t reserved_630[51]; + volatile gpio_reg_date_reg_t reg_date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h b/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h index cf62a85b3c..26d6fba79c 100644 --- a/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #pragma once + #include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ @@ -110,7 +111,6 @@ #define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U #define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U -#define FUNC_GPIO_GPIO 1 #define PIN_FUNC_GPIO 1 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) @@ -124,9 +124,9 @@ #define SPI_D_GPIO_NUM 18 #define SPI_Q_GPIO_NUM 14 -#define MAX_RTC_GPIO_NUM 5 -#define MAX_PAD_GPIO_NUM 20 -#define MAX_GPIO_NUM 24 +#define MAX_RTC_GPIO_NUM 12 // GPIO7~12 are the rtc_io pads +#define MAX_PAD_GPIO_NUM 25 +#define MAX_GPIO_NUM 29 #define DIG_IO_HOLD_BIT_SHIFT 0 diff --git a/components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_reg.h index 7af27bc3b6..f65e780350 100644 --- a/components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** USB_SERIAL_JTAG_EP1_REG register * FIFO access for the CDC-ACM data IN and OUT endpoints. */ -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. When * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 @@ -30,7 +30,7 @@ extern "C" { /** USB_SERIAL_JTAG_EP1_CONF_REG register * Configuration and control registers for the CDC-ACM FIFOs. */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) /** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. */ @@ -58,7 +58,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_RAW_REG register * Interrupt raw status register. */ -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when flush cmd is received for IN * endpoint 2 of JTAG. @@ -152,7 +152,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_ST_REG register * Interrupt status register. */ -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ @@ -245,7 +245,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_ENA_REG register * Interrupt enable status register. */ -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ @@ -334,7 +334,7 @@ extern "C" { /** USB_SERIAL_JTAG_INT_CLR_REG register * Interrupt clear status register. */ -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. */ @@ -423,7 +423,7 @@ extern "C" { /** USB_SERIAL_JTAG_CONF0_REG register * PHY hardware configuration. */ -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) /** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY */ @@ -534,7 +534,7 @@ extern "C" { /** USB_SERIAL_JTAG_TEST_REG register * Registers used for debugging the PHY. */ -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) /** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB pad */ @@ -588,7 +588,7 @@ extern "C" { /** USB_SERIAL_JTAG_JFIFO_ST_REG register * JTAG FIFO status and control registers. */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) /** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; * JTAT in fifo counter. */ @@ -649,7 +649,7 @@ extern "C" { /** USB_SERIAL_JTAG_FRAM_NUM_REG register * Last received SOF frame index register. */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) /** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; * Frame index of received SOF frame. */ @@ -661,7 +661,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP0_ST_REG register * Control IN endpoint status information. */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) /** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 0. */ @@ -687,7 +687,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP1_ST_REG register * CDC-ACM IN endpoint status information. */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) /** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 1. */ @@ -713,7 +713,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP2_ST_REG register * CDC-ACM interrupt IN endpoint status information. */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) /** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 2. */ @@ -739,7 +739,7 @@ extern "C" { /** USB_SERIAL_JTAG_IN_EP3_ST_REG register * JTAG IN endpoint status information. */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) /** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 3. */ @@ -765,7 +765,7 @@ extern "C" { /** USB_SERIAL_JTAG_OUT_EP0_ST_REG register * Control OUT endpoint status information. */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) /** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 0. */ @@ -792,7 +792,7 @@ extern "C" { /** USB_SERIAL_JTAG_OUT_EP1_ST_REG register * CDC-ACM OUT endpoint status information. */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) /** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 1. */ @@ -826,7 +826,7 @@ extern "C" { /** USB_SERIAL_JTAG_OUT_EP2_ST_REG register * JTAG OUT endpoint status information. */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) /** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 2. */ @@ -853,7 +853,7 @@ extern "C" { /** USB_SERIAL_JTAG_MISC_CONF_REG register * Clock enable control */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) /** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes * registers. @@ -866,7 +866,7 @@ extern "C" { /** USB_SERIAL_JTAG_MEM_CONF_REG register * Memory power control */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) /** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb memory. */ @@ -885,7 +885,7 @@ extern "C" { /** USB_SERIAL_JTAG_DATE_REG register * Date register */ -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80) +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) /** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34607505; * register version. */ diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 20bb3eb969..fa9b10a030 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -213,7 +213,7 @@ config SOC_GPIO_PORT config SOC_GPIO_PIN_COUNT int - default 22 + default 41 config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT bool diff --git a/components/soc/esp32h2/include/soc/gpio_struct.h b/components/soc/esp32h2/include/soc/gpio_struct.h deleted file mode 100644 index 45f5e55412..0000000000 --- a/components/soc/esp32h2/include/soc/gpio_struct.h +++ /dev/null @@ -1,437 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_GPIO_STRUCT_H_ -#define _SOC_GPIO_STRUCT_H_ -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct gpio_dev_s { - uint32_t bt_select; /**/ - union { - struct { - uint32_t data: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } out; - union { - struct { - uint32_t out_w1ts: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } out_w1ts; - union { - struct { - uint32_t out_w1tc: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } out_w1tc; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - union { - struct { - uint32_t sel: 8; - uint32_t reserved8: 24; - }; - uint32_t val; - } sdio_select; - union { - struct { - uint32_t data: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } enable; - union { - struct { - uint32_t enable_w1ts:26; - uint32_t reserved26: 6; - }; - uint32_t val; - } enable_w1ts; - union { - struct { - uint32_t enable_w1tc:26; - uint32_t reserved26: 6; - }; - uint32_t val; - } enable_w1tc; - uint32_t reserved_2c; - uint32_t reserved_30; - uint32_t reserved_34; - union { - struct { - uint32_t strapping: 16; - uint32_t reserved16:16; - }; - uint32_t val; - } strap; - union { - struct { - uint32_t data: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } in; - uint32_t reserved_40; - union { - struct { - uint32_t intr_st: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } status; - union { - struct { - uint32_t status_w1ts:26; - uint32_t reserved26: 6; - }; - uint32_t val; - } status_w1ts; - union { - struct { - uint32_t status_w1tc:26; - uint32_t reserved26: 6; - }; - uint32_t val; - } status_w1tc; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - union { - struct { - uint32_t intr: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } pcpu_int; - union { - struct { - uint32_t intr: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } pcpu_nmi_int; - union { - struct { - uint32_t intr: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } cpusdio_int; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - union { - struct { - uint32_t sync2_bypass: 2; - uint32_t pad_driver: 1; - uint32_t sync1_bypass: 2; - uint32_t reserved5: 2; - uint32_t int_type: 3; - uint32_t wakeup_enable: 1; - uint32_t config: 2; - uint32_t int_ena: 5; - uint32_t reserved18: 14; - }; - uint32_t val; - } pin[26]; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - union { - struct { - uint32_t intr_st_next: 26; - uint32_t reserved26: 6; - }; - uint32_t val; - } status_next; - uint32_t reserved_150; - union { - struct { - uint32_t func_sel: 5; - uint32_t sig_in_inv: 1; - uint32_t sig_in_sel: 1; - uint32_t reserved7: 25; - }; - uint32_t val; - } func_in_sel_cfg[128]; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t reserved_400; - uint32_t reserved_404; - uint32_t reserved_408; - uint32_t reserved_40c; - uint32_t reserved_410; - uint32_t reserved_414; - uint32_t reserved_418; - uint32_t reserved_41c; - uint32_t reserved_420; - uint32_t reserved_424; - uint32_t reserved_428; - uint32_t reserved_42c; - uint32_t reserved_430; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - uint32_t reserved_47c; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t reserved_500; - uint32_t reserved_504; - uint32_t reserved_508; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t reserved_540; - uint32_t reserved_544; - uint32_t reserved_548; - uint32_t reserved_54c; - uint32_t reserved_550; - union { - struct { - uint32_t func_sel: 8; - uint32_t inv_sel: 1; - uint32_t oen_sel: 1; - uint32_t oen_inv_sel: 1; - uint32_t reserved11: 21; - }; - uint32_t val; - } func_out_sel_cfg[26]; - uint32_t reserved_5bc; - uint32_t reserved_5c0; - uint32_t reserved_5c4; - uint32_t reserved_5c8; - uint32_t reserved_5cc; - uint32_t reserved_5d0; - uint32_t reserved_5d4; - uint32_t reserved_5d8; - uint32_t reserved_5dc; - uint32_t reserved_5e0; - uint32_t reserved_5e4; - uint32_t reserved_5e8; - uint32_t reserved_5ec; - uint32_t reserved_5f0; - uint32_t reserved_5f4; - uint32_t reserved_5f8; - uint32_t reserved_5fc; - uint32_t reserved_600; - uint32_t reserved_604; - uint32_t reserved_608; - uint32_t reserved_60c; - uint32_t reserved_610; - uint32_t reserved_614; - uint32_t reserved_618; - uint32_t reserved_61c; - uint32_t reserved_620; - uint32_t reserved_624; - uint32_t reserved_628; - union { - struct { - uint32_t clk_en: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } clock_gate; - uint32_t reserved_630; - uint32_t reserved_634; - uint32_t reserved_638; - uint32_t reserved_63c; - uint32_t reserved_640; - uint32_t reserved_644; - uint32_t reserved_648; - uint32_t reserved_64c; - uint32_t reserved_650; - uint32_t reserved_654; - uint32_t reserved_658; - uint32_t reserved_65c; - uint32_t reserved_660; - uint32_t reserved_664; - uint32_t reserved_668; - uint32_t reserved_66c; - uint32_t reserved_670; - uint32_t reserved_674; - uint32_t reserved_678; - uint32_t reserved_67c; - uint32_t reserved_680; - uint32_t reserved_684; - uint32_t reserved_688; - uint32_t reserved_68c; - uint32_t reserved_690; - uint32_t reserved_694; - uint32_t reserved_698; - uint32_t reserved_69c; - uint32_t reserved_6a0; - uint32_t reserved_6a4; - uint32_t reserved_6a8; - uint32_t reserved_6ac; - uint32_t reserved_6b0; - uint32_t reserved_6b4; - uint32_t reserved_6b8; - uint32_t reserved_6bc; - uint32_t reserved_6c0; - uint32_t reserved_6c4; - uint32_t reserved_6c8; - uint32_t reserved_6cc; - uint32_t reserved_6d0; - uint32_t reserved_6d4; - uint32_t reserved_6d8; - uint32_t reserved_6dc; - uint32_t reserved_6e0; - uint32_t reserved_6e4; - uint32_t reserved_6e8; - uint32_t reserved_6ec; - uint32_t reserved_6f0; - uint32_t reserved_6f4; - uint32_t reserved_6f8; - union { - struct { - uint32_t date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } date; -} gpio_dev_t; -extern gpio_dev_t GPIO; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h index 95ce211072..fc83c6d305 100644 --- a/components/soc/esp32h2/include/soc/reg_base.h +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -70,5 +70,5 @@ #define DR_REG_APB_SARADC_BASE 0x60040000 #define DR_REG_LCD_CAM_BASE 0x60041000 #define DR_REG_AES_XTS_BASE 0x600CC000 -#define DR_REG_USB_DEVICE_BASE 0x60043000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 #define DR_REG_CLKRST_BASE 0x6004B000 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 4c5862d2bf..9aa06458fc 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -23,6 +23,15 @@ #pragma once +#ifdef __has_include +# if __has_include("sdkconfig.h") +# include "sdkconfig.h" +# else +# warning Chip version cannot be determined. Default chip to ESP32H2_BETA_VERSION_1. +# define CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 1 +# endif +#endif + /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_CPU_CORES_NUM 1 #define SOC_ADC_SUPPORTED 1 @@ -110,21 +119,29 @@ #define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number /*-------------------------- GPIO CAPS ---------------------------------------*/ -// ESP32-C3 has 1 GPIO peripheral +// ESP32-H2 has 1 GPIO peripheral #define SOC_GPIO_PORT (1U) -#define SOC_GPIO_PIN_COUNT (22) +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 +#define SOC_GPIO_PIN_COUNT (41) +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 +#define SOC_GPIO_PIN_COUNT (26) +#endif // Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC -// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. +// On ESP32-H2, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. #define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1) -// Force hold is a new function of ESP32-C3 +// Force hold is a new function of ESP32-H2 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup +// GPIO0~5 on ESP32H2Beta1 / GPIO7~12 on ESP32H2Beta2 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) -#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3)) /*-------------------------- RTCIO CAPS --------------------------------------*/ -/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported +/* No dedicated RTCIO subsystem on ESP32-H2. RTC functions are still supported * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ #define SOC_RTCIO_PIN_COUNT (0U) @@ -267,7 +284,7 @@ #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ -#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ +#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-H2 */ /*-------------------------- TWAI CAPS ---------------------------------------*/ #define SOC_TWAI_BRP_MIN 2 diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/include/soc/reg_base.h index c0fcb9c2a0..9beea9fde3 100644 --- a/components/soc/esp32s3/include/soc/reg_base.h +++ b/components/soc/esp32s3/include/soc/reg_base.h @@ -46,7 +46,7 @@ #define DR_REG_PWM1_BASE 0x6002C000 #define DR_REG_I2S1_BASE 0x6002D000 #define DR_REG_UART2_BASE 0x6002E000 -#define DR_REG_USB_DEVICE_BASE 0x60038000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x60038000 #define DR_REG_USB_WRAP_BASE 0x60039000 #define DR_REG_AES_BASE 0x6003A000 #define DR_REG_SHA_BASE 0x6003B000 diff --git a/components/soc/esp32s3/include/soc/usb_device_reg.h b/components/soc/esp32s3/include/soc/usb_device_reg.h deleted file mode 100644 index efb6bc5476..0000000000 --- a/components/soc/esp32s3/include/soc/usb_device_reg.h +++ /dev/null @@ -1,737 +0,0 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_USB_DEVICE_REG_H_ -#define _SOC_USB_DEVICE_REG_H_ - - -#include "soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) -/* USB_DEVICE_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE -VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into -UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB -_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is rece -ived, then read data from UART Rx FIFO..*/ -#define USB_DEVICE_RDWR_BYTE 0x000000FF -#define USB_DEVICE_RDWR_BYTE_M ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S)) -#define USB_DEVICE_RDWR_BYTE_V 0xFF -#define USB_DEVICE_RDWR_BYTE_S 0 - -#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) -/* USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/ -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_V 0x1 -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_S 2 -/* USB_DEVICE_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin -g USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by -USB Host..*/ -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_M (BIT(1)) -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_V 0x1 -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_S 1 -/* USB_DEVICE_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/ -#define USB_DEVICE_WR_DONE (BIT(0)) -#define USB_DEVICE_WR_DONE_M (BIT(0)) -#define USB_DEVICE_WR_DONE_V 0x1 -#define USB_DEVICE_WR_DONE_S 0 - -#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi -th zero palyload..*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi -th zero palyload..*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/ -#define USB_DEVICE_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_RAW_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_RAW_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_RAW_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec -eived..*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/* USB_DEVICE_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when stuff error is detected..*/ -#define USB_DEVICE_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_RAW_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_RAW_S 7 -/* USB_DEVICE_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/ -#define USB_DEVICE_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_RAW_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_RAW_S 6 -/* USB_DEVICE_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/ -#define USB_DEVICE_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_RAW_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_RAW_S 5 -/* USB_DEVICE_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when pid error is detected..*/ -#define USB_DEVICE_PID_ERR_INT_RAW (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_RAW_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_PID_ERR_INT_RAW_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */ -/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received - one packet..*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/* USB_DEVICE_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when SOF frame is received..*/ -#define USB_DEVICE_SOF_INT_RAW (BIT(1)) -#define USB_DEVICE_SOF_INT_RAW_M (BIT(1)) -#define USB_DEVICE_SOF_INT_RAW_V 0x1 -#define USB_DEVICE_SOF_INT_RAW_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp -oint 2 of JTAG..*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_S 0 - -#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xC) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interru -pt..*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interru -pt..*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/ -#define USB_DEVICE_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ST_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ST_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_ST_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrup -t..*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/* USB_DEVICE_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/ -#define USB_DEVICE_STUFF_ERR_INT_ST (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ST_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ST_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_ST_S 7 -/* USB_DEVICE_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/ -#define USB_DEVICE_CRC16_ERR_INT_ST (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ST_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ST_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_ST_S 6 -/* USB_DEVICE_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/ -#define USB_DEVICE_CRC5_ERR_INT_ST (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ST_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ST_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_ST_S 5 -/* USB_DEVICE_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt..*/ -#define USB_DEVICE_PID_ERR_INT_ST (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ST_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ST_V 0x1 -#define USB_DEVICE_PID_ERR_INT_ST_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrup -t..*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/* USB_DEVICE_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt..*/ -#define USB_DEVICE_SOF_INT_ST (BIT(1)) -#define USB_DEVICE_SOF_INT_ST_M (BIT(1)) -#define USB_DEVICE_SOF_INT_ST_V 0x1 -#define USB_DEVICE_SOF_INT_ST_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_S 0 - -#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/ -#define USB_DEVICE_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ENA_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ENA_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_ENA_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt..*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/* USB_DEVICE_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/ -#define USB_DEVICE_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ENA_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_ENA_S 7 -/* USB_DEVICE_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/ -#define USB_DEVICE_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ENA_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_ENA_S 6 -/* USB_DEVICE_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/ -#define USB_DEVICE_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ENA_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_ENA_S 5 -/* USB_DEVICE_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt..*/ -#define USB_DEVICE_PID_ERR_INT_ENA (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ENA_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_PID_ERR_INT_ENA_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/* USB_DEVICE_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt..*/ -#define USB_DEVICE_SOF_INT_ENA (BIT(1)) -#define USB_DEVICE_SOF_INT_ENA_M (BIT(1)) -#define USB_DEVICE_SOF_INT_ENA_V 0x1 -#define USB_DEVICE_SOF_INT_ENA_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_S 0 - -#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/ -#define USB_DEVICE_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_CLR_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_CLR_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_CLR_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt..*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/* USB_DEVICE_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt..*/ -#define USB_DEVICE_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_CLR_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_CLR_S 7 -/* USB_DEVICE_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt..*/ -#define USB_DEVICE_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_CLR_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_CLR_S 6 -/* USB_DEVICE_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt..*/ -#define USB_DEVICE_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_CLR_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_CLR_S 5 -/* USB_DEVICE_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt..*/ -#define USB_DEVICE_PID_ERR_INT_CLR (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_CLR_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_PID_ERR_INT_CLR_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/* USB_DEVICE_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt..*/ -#define USB_DEVICE_SOF_INT_CLR (BIT(1)) -#define USB_DEVICE_SOF_INT_CLR_M (BIT(1)) -#define USB_DEVICE_SOF_INT_CLR_V 0x1 -#define USB_DEVICE_SOF_INT_CLR_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_S 0 - -#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) -/* USB_DEVICE_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/ -#define USB_DEVICE_PHY_TX_EDGE_SEL (BIT(15)) -#define USB_DEVICE_PHY_TX_EDGE_SEL_M (BIT(15)) -#define USB_DEVICE_PHY_TX_EDGE_SEL_V 0x1 -#define USB_DEVICE_PHY_TX_EDGE_SEL_S 15 -/* USB_DEVICE_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: Enable USB pad function..*/ -#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) -#define USB_DEVICE_USB_PAD_ENABLE_M (BIT(14)) -#define USB_DEVICE_USB_PAD_ENABLE_V 0x1 -#define USB_DEVICE_USB_PAD_ENABLE_S 14 -/* USB_DEVICE_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Control pull up value..*/ -#define USB_DEVICE_PULLUP_VALUE (BIT(13)) -#define USB_DEVICE_PULLUP_VALUE_M (BIT(13)) -#define USB_DEVICE_PULLUP_VALUE_V 0x1 -#define USB_DEVICE_PULLUP_VALUE_S 13 -/* USB_DEVICE_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Control USB D- pull down..*/ -#define USB_DEVICE_DM_PULLDOWN (BIT(12)) -#define USB_DEVICE_DM_PULLDOWN_M (BIT(12)) -#define USB_DEVICE_DM_PULLDOWN_V 0x1 -#define USB_DEVICE_DM_PULLDOWN_S 12 -/* USB_DEVICE_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Control USB D- pull up..*/ -#define USB_DEVICE_DM_PULLUP (BIT(11)) -#define USB_DEVICE_DM_PULLUP_M (BIT(11)) -#define USB_DEVICE_DM_PULLUP_V 0x1 -#define USB_DEVICE_DM_PULLUP_S 11 -/* USB_DEVICE_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Control USB D+ pull down..*/ -#define USB_DEVICE_DP_PULLDOWN (BIT(10)) -#define USB_DEVICE_DP_PULLDOWN_M (BIT(10)) -#define USB_DEVICE_DP_PULLDOWN_V 0x1 -#define USB_DEVICE_DP_PULLDOWN_S 10 -/* USB_DEVICE_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: Control USB D+ pull up..*/ -#define USB_DEVICE_DP_PULLUP (BIT(9)) -#define USB_DEVICE_DP_PULLUP_M (BIT(9)) -#define USB_DEVICE_DP_PULLUP_V 0x1 -#define USB_DEVICE_DP_PULLUP_S 9 -/* USB_DEVICE_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Enable software control USB D+ D- pullup pulldown.*/ -#define USB_DEVICE_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_DEVICE_PAD_PULL_OVERRIDE_M (BIT(8)) -#define USB_DEVICE_PAD_PULL_OVERRIDE_V 0x1 -#define USB_DEVICE_PAD_PULL_OVERRIDE_S 8 -/* USB_DEVICE_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Enable software control input threshold.*/ -#define USB_DEVICE_VREF_OVERRIDE (BIT(7)) -#define USB_DEVICE_VREF_OVERRIDE_M (BIT(7)) -#define USB_DEVICE_VREF_OVERRIDE_V 0x1 -#define USB_DEVICE_VREF_OVERRIDE_S 7 -/* USB_DEVICE_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ -/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/ -#define USB_DEVICE_VREFL 0x00000003 -#define USB_DEVICE_VREFL_M ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S)) -#define USB_DEVICE_VREFL_V 0x3 -#define USB_DEVICE_VREFL_S 5 -/* USB_DEVICE_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/ -#define USB_DEVICE_VREFH 0x00000003 -#define USB_DEVICE_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S)) -#define USB_DEVICE_VREFH_V 0x3 -#define USB_DEVICE_VREFH_S 3 -/* USB_DEVICE_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: USB D+ D- exchange.*/ -#define USB_DEVICE_EXCHG_PINS (BIT(2)) -#define USB_DEVICE_EXCHG_PINS_M (BIT(2)) -#define USB_DEVICE_EXCHG_PINS_V 0x1 -#define USB_DEVICE_EXCHG_PINS_S 2 -/* USB_DEVICE_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Enable software control USB D+ D- exchange.*/ -#define USB_DEVICE_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_DEVICE_EXCHG_PINS_OVERRIDE_M (BIT(1)) -#define USB_DEVICE_EXCHG_PINS_OVERRIDE_V 0x1 -#define USB_DEVICE_EXCHG_PINS_OVERRIDE_S 1 -/* USB_DEVICE_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Select internal/external PHY.*/ -#define USB_DEVICE_PHY_SEL (BIT(0)) -#define USB_DEVICE_PHY_SEL_M (BIT(0)) -#define USB_DEVICE_PHY_SEL_V 0x1 -#define USB_DEVICE_PHY_SEL_S 0 - -#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1C) -/* USB_DEVICE_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: USB D- rx value in test.*/ -#define USB_DEVICE_TEST_RX_DM (BIT(6)) -#define USB_DEVICE_TEST_RX_DM_M (BIT(6)) -#define USB_DEVICE_TEST_RX_DM_V 0x1 -#define USB_DEVICE_TEST_RX_DM_S 6 -/* USB_DEVICE_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: USB D+ rx value in test.*/ -#define USB_DEVICE_TEST_RX_DP (BIT(5)) -#define USB_DEVICE_TEST_RX_DP_M (BIT(5)) -#define USB_DEVICE_TEST_RX_DP_V 0x1 -#define USB_DEVICE_TEST_RX_DP_S 5 -/* USB_DEVICE_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: USB differential rx value in test.*/ -#define USB_DEVICE_TEST_RX_RCV (BIT(4)) -#define USB_DEVICE_TEST_RX_RCV_M (BIT(4)) -#define USB_DEVICE_TEST_RX_RCV_V 0x1 -#define USB_DEVICE_TEST_RX_RCV_S 4 -/* USB_DEVICE_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: USB D- tx value in test.*/ -#define USB_DEVICE_TEST_TX_DM (BIT(3)) -#define USB_DEVICE_TEST_TX_DM_M (BIT(3)) -#define USB_DEVICE_TEST_TX_DM_V 0x1 -#define USB_DEVICE_TEST_TX_DM_S 3 -/* USB_DEVICE_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: USB D+ tx value in test.*/ -#define USB_DEVICE_TEST_TX_DP (BIT(2)) -#define USB_DEVICE_TEST_TX_DP_M (BIT(2)) -#define USB_DEVICE_TEST_TX_DP_V 0x1 -#define USB_DEVICE_TEST_TX_DP_S 2 -/* USB_DEVICE_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: USB pad oen in test.*/ -#define USB_DEVICE_TEST_USB_OE (BIT(1)) -#define USB_DEVICE_TEST_USB_OE_M (BIT(1)) -#define USB_DEVICE_TEST_USB_OE_V 0x1 -#define USB_DEVICE_TEST_USB_OE_S 1 -/* USB_DEVICE_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Enable test of the USB pad.*/ -#define USB_DEVICE_TEST_ENABLE (BIT(0)) -#define USB_DEVICE_TEST_ENABLE_M (BIT(0)) -#define USB_DEVICE_TEST_ENABLE_V 0x1 -#define USB_DEVICE_TEST_ENABLE_S 0 - -#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) -/* USB_DEVICE_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Write 1 to reset JTAG out fifo..*/ -#define USB_DEVICE_OUT_FIFO_RESET (BIT(9)) -#define USB_DEVICE_OUT_FIFO_RESET_M (BIT(9)) -#define USB_DEVICE_OUT_FIFO_RESET_V 0x1 -#define USB_DEVICE_OUT_FIFO_RESET_S 9 -/* USB_DEVICE_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Write 1 to reset JTAG in fifo..*/ -#define USB_DEVICE_IN_FIFO_RESET (BIT(8)) -#define USB_DEVICE_IN_FIFO_RESET_M (BIT(8)) -#define USB_DEVICE_IN_FIFO_RESET_V 0x1 -#define USB_DEVICE_IN_FIFO_RESET_S 8 -/* USB_DEVICE_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 1: JTAG out fifo is full..*/ -#define USB_DEVICE_OUT_FIFO_FULL (BIT(7)) -#define USB_DEVICE_OUT_FIFO_FULL_M (BIT(7)) -#define USB_DEVICE_OUT_FIFO_FULL_V 0x1 -#define USB_DEVICE_OUT_FIFO_FULL_S 7 -/* USB_DEVICE_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */ -/*description: 1: JTAG out fifo is empty..*/ -#define USB_DEVICE_OUT_FIFO_EMPTY (BIT(6)) -#define USB_DEVICE_OUT_FIFO_EMPTY_M (BIT(6)) -#define USB_DEVICE_OUT_FIFO_EMPTY_V 0x1 -#define USB_DEVICE_OUT_FIFO_EMPTY_S 6 -/* USB_DEVICE_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: JTAT out fifo counter..*/ -#define USB_DEVICE_OUT_FIFO_CNT 0x00000003 -#define USB_DEVICE_OUT_FIFO_CNT_M ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S)) -#define USB_DEVICE_OUT_FIFO_CNT_V 0x3 -#define USB_DEVICE_OUT_FIFO_CNT_S 4 -/* USB_DEVICE_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 1: JTAG in fifo is full..*/ -#define USB_DEVICE_IN_FIFO_FULL (BIT(3)) -#define USB_DEVICE_IN_FIFO_FULL_M (BIT(3)) -#define USB_DEVICE_IN_FIFO_FULL_V 0x1 -#define USB_DEVICE_IN_FIFO_FULL_S 3 -/* USB_DEVICE_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */ -/*description: 1: JTAG in fifo is empty..*/ -#define USB_DEVICE_IN_FIFO_EMPTY (BIT(2)) -#define USB_DEVICE_IN_FIFO_EMPTY_M (BIT(2)) -#define USB_DEVICE_IN_FIFO_EMPTY_V 0x1 -#define USB_DEVICE_IN_FIFO_EMPTY_S 2 -/* USB_DEVICE_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: JTAT in fifo counter..*/ -#define USB_DEVICE_IN_FIFO_CNT 0x00000003 -#define USB_DEVICE_IN_FIFO_CNT_M ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S)) -#define USB_DEVICE_IN_FIFO_CNT_V 0x3 -#define USB_DEVICE_IN_FIFO_CNT_S 0 - -#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) -/* USB_DEVICE_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */ -/*description: Frame index of received SOF frame..*/ -#define USB_DEVICE_SOF_FRAME_INDEX 0x000007FF -#define USB_DEVICE_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S)) -#define USB_DEVICE_SOF_FRAME_INDEX_V 0x7FF -#define USB_DEVICE_SOF_FRAME_INDEX_S 0 - -#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) -/* USB_DEVICE_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 0..*/ -#define USB_DEVICE_IN_EP0_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP0_RD_ADDR_M ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S)) -#define USB_DEVICE_IN_EP0_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP0_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 0..*/ -#define USB_DEVICE_IN_EP0_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP0_WR_ADDR_M ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S)) -#define USB_DEVICE_IN_EP0_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP0_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 0..*/ -#define USB_DEVICE_IN_EP0_STATE 0x00000003 -#define USB_DEVICE_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S)) -#define USB_DEVICE_IN_EP0_STATE_V 0x3 -#define USB_DEVICE_IN_EP0_STATE_S 0 - -#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2C) -/* USB_DEVICE_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 1..*/ -#define USB_DEVICE_IN_EP1_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP1_RD_ADDR_M ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S)) -#define USB_DEVICE_IN_EP1_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP1_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 1..*/ -#define USB_DEVICE_IN_EP1_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP1_WR_ADDR_M ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S)) -#define USB_DEVICE_IN_EP1_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP1_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 1..*/ -#define USB_DEVICE_IN_EP1_STATE 0x00000003 -#define USB_DEVICE_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S)) -#define USB_DEVICE_IN_EP1_STATE_V 0x3 -#define USB_DEVICE_IN_EP1_STATE_S 0 - -#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) -/* USB_DEVICE_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 2..*/ -#define USB_DEVICE_IN_EP2_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP2_RD_ADDR_M ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S)) -#define USB_DEVICE_IN_EP2_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP2_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 2..*/ -#define USB_DEVICE_IN_EP2_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP2_WR_ADDR_M ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S)) -#define USB_DEVICE_IN_EP2_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP2_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 2..*/ -#define USB_DEVICE_IN_EP2_STATE 0x00000003 -#define USB_DEVICE_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S)) -#define USB_DEVICE_IN_EP2_STATE_V 0x3 -#define USB_DEVICE_IN_EP2_STATE_S 0 - -#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) -/* USB_DEVICE_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 3..*/ -#define USB_DEVICE_IN_EP3_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP3_RD_ADDR_M ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S)) -#define USB_DEVICE_IN_EP3_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP3_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 3..*/ -#define USB_DEVICE_IN_EP3_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP3_WR_ADDR_M ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S)) -#define USB_DEVICE_IN_EP3_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP3_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 3..*/ -#define USB_DEVICE_IN_EP3_STATE 0x00000003 -#define USB_DEVICE_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S)) -#define USB_DEVICE_IN_EP3_STATE_V 0x3 -#define USB_DEVICE_IN_EP3_STATE_S 0 - -#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) -/* USB_DEVICE_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of OUT endpoint 0..*/ -#define USB_DEVICE_OUT_EP0_RD_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP0_RD_ADDR_M ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S)) -#define USB_DEVICE_OUT_EP0_RD_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP0_RD_ADDR_S 9 -/* USB_DEVICE_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/ -#define USB_DEVICE_OUT_EP0_WR_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP0_WR_ADDR_M ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S)) -#define USB_DEVICE_OUT_EP0_WR_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP0_WR_ADDR_S 2 -/* USB_DEVICE_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: State of OUT Endpoint 0..*/ -#define USB_DEVICE_OUT_EP0_STATE 0x00000003 -#define USB_DEVICE_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S)) -#define USB_DEVICE_OUT_EP0_STATE_V 0x3 -#define USB_DEVICE_OUT_EP0_STATE_S 0 - -#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3C) -/* USB_DEVICE_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */ -/*description: Data count in OUT endpoint 1 when one packet is received..*/ -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT 0x0000007F -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_M ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S)) -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_V 0x7F -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_S 16 -/* USB_DEVICE_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of OUT endpoint 1..*/ -#define USB_DEVICE_OUT_EP1_RD_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP1_RD_ADDR_M ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S)) -#define USB_DEVICE_OUT_EP1_RD_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP1_RD_ADDR_S 9 -/* USB_DEVICE_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/ -#define USB_DEVICE_OUT_EP1_WR_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S)) -#define USB_DEVICE_OUT_EP1_WR_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP1_WR_ADDR_S 2 -/* USB_DEVICE_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: State of OUT Endpoint 1..*/ -#define USB_DEVICE_OUT_EP1_STATE 0x00000003 -#define USB_DEVICE_OUT_EP1_STATE_M ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S)) -#define USB_DEVICE_OUT_EP1_STATE_V 0x3 -#define USB_DEVICE_OUT_EP1_STATE_S 0 - -#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) -/* USB_DEVICE_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of OUT endpoint 2..*/ -#define USB_DEVICE_OUT_EP2_RD_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP2_RD_ADDR_M ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S)) -#define USB_DEVICE_OUT_EP2_RD_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP2_RD_ADDR_S 9 -/* USB_DEVICE_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is - detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/ -#define USB_DEVICE_OUT_EP2_WR_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S)) -#define USB_DEVICE_OUT_EP2_WR_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP2_WR_ADDR_S 2 -/* USB_DEVICE_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: State of OUT Endpoint 2..*/ -#define USB_DEVICE_OUT_EP2_STATE 0x00000003 -#define USB_DEVICE_OUT_EP2_STATE_M ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S)) -#define USB_DEVICE_OUT_EP2_STATE_V 0x3 -#define USB_DEVICE_OUT_EP2_STATE_S 0 - -#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) -/* USB_DEVICE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri -tes registers..*/ -#define USB_DEVICE_CLK_EN (BIT(0)) -#define USB_DEVICE_CLK_EN_M (BIT(0)) -#define USB_DEVICE_CLK_EN_V 0x1 -#define USB_DEVICE_CLK_EN_S 0 - -#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) -/* USB_DEVICE_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1: Force clock on for usb memory..*/ -#define USB_DEVICE_USB_MEM_CLK_EN (BIT(1)) -#define USB_DEVICE_USB_MEM_CLK_EN_M (BIT(1)) -#define USB_DEVICE_USB_MEM_CLK_EN_V 0x1 -#define USB_DEVICE_USB_MEM_CLK_EN_S 1 -/* USB_DEVICE_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: power down usb memory..*/ -#define USB_DEVICE_USB_MEM_PD (BIT(0)) -#define USB_DEVICE_USB_MEM_PD_M (BIT(0)) -#define USB_DEVICE_USB_MEM_PD_V 0x1 -#define USB_DEVICE_USB_MEM_PD_S 0 - -#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80) -/* USB_DEVICE_DATE : R/W ;bitpos:[31:0] ;default: 32'h2011190 ; */ -/*description: register version..*/ -#define USB_DEVICE_DATE 0xFFFFFFFF -#define USB_DEVICE_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S)) -#define USB_DEVICE_DATE_V 0xFFFFFFFF -#define USB_DEVICE_DATE_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_USB_DEVICE_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h index 44a617806e..5774f2d711 100644 --- a/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h @@ -1,18 +1,9 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_USB_DEVICE_REG_H_ -#define _SOC_USB_DEVICE_REG_H_ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once #ifdef __cplusplus @@ -20,7 +11,7 @@ extern "C" { #endif #include "soc.h" -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into @@ -32,7 +23,7 @@ ived, then read data from UART Rx FIFO..*/ #define USB_SERIAL_JTAG_RDWR_BYTE_V 0xFF #define USB_SERIAL_JTAG_RDWR_BYTE_S 0 -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) /* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: 1'b1: Indicate there is data in UART Rx FIFO..*/ #define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) @@ -54,7 +45,7 @@ USB Host..*/ #define USB_SERIAL_JTAG_WR_DONE_V 0x1 #define USB_SERIAL_JTAG_WR_DONE_S 0 -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi th zero palyload..*/ @@ -133,7 +124,7 @@ oint 2 of JTAG..*/ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x1 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xC) +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xC) /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interru pt..*/ @@ -211,7 +202,7 @@ t..*/ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x1 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ /*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) @@ -285,7 +276,7 @@ t..*/ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x1 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ /*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/ #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) @@ -359,7 +350,7 @@ t..*/ #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x1 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) /* USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ /*description: Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disc onnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input thr @@ -453,7 +444,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_PHY_SEL_V 0x1 #define USB_SERIAL_JTAG_PHY_SEL_S 0 -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1C) +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1C) /* USB_SERIAL_JTAG_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: USB D- rx value in test.*/ #define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) @@ -497,7 +488,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_TEST_ENABLE_V 0x1 #define USB_SERIAL_JTAG_TEST_ENABLE_S 0 -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) /* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */ /*description: Write 1 to reset JTAG out fifo..*/ #define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) @@ -547,7 +538,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x3 #define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) /* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */ /*description: Frame index of received SOF frame..*/ #define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF @@ -555,7 +546,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x7FF #define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) /* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ /*description: Read data address of IN endpoint 0..*/ #define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F @@ -575,7 +566,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x3 #define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2C) +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2C) /* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ /*description: Read data address of IN endpoint 1..*/ #define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F @@ -595,7 +586,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x3 #define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) /* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ /*description: Read data address of IN endpoint 2..*/ #define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F @@ -615,7 +606,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x3 #define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) /* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ /*description: Read data address of IN endpoint 3..*/ #define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F @@ -635,7 +626,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x3 #define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) /* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ /*description: Read data address of OUT endpoint 0..*/ #define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F @@ -656,7 +647,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x3 #define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3C) +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3C) /* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */ /*description: Data count in OUT endpoint 1 when one packet is received..*/ #define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F @@ -683,7 +674,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x3 #define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) /* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ /*description: Read data address of OUT endpoint 2..*/ #define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F @@ -704,7 +695,7 @@ ough GPIO Matrix..*/ #define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x3 #define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) /* USB_SERIAL_JTAG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri tes registers..*/ @@ -713,7 +704,7 @@ tes registers..*/ #define USB_SERIAL_JTAG_CLK_EN_V 0x1 #define USB_SERIAL_JTAG_CLK_EN_S 0 -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) /* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ /*description: 1: Force clock on for usb memory..*/ #define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) @@ -727,7 +718,7 @@ tes registers..*/ #define USB_SERIAL_JTAG_USB_MEM_PD_V 0x1 #define USB_SERIAL_JTAG_USB_MEM_PD_S 0 -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80) +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) /* USB_SERIAL_JTAG_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101200 ; */ /*description: register version..*/ #define USB_SERIAL_JTAG_DATE 0xFFFFFFFF @@ -739,7 +730,3 @@ tes registers..*/ #ifdef __cplusplus } #endif - - - -#endif /*_SOC_USB_DEVICE_REG_H_ */ diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 898236cf2f..4dcb5e29b2 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -144,6 +144,9 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id]; int spics_func = spi_periph_signal[config->host_id].func; uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num]; + gpio_hal_context_t gpio_hal = { + .dev = GPIO_HAL_GET_HW(GPIO_PORT_0) + }; //To avoid the panic caused by flash data line conflicts during cs line //initialization, disable the cache temporarily @@ -152,16 +155,8 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f if (use_iomux) { gpio_hal_iomux_func_sel(iomux_reg, spics_func); } else { -#if SOC_GPIO_PIN_COUNT <= 32 - GPIO.enable_w1ts.val = (0x1 << cs_io_num); -#else - if (cs_io_num < 32) { - GPIO.enable_w1ts = (0x1 << cs_io_num); - } else { - GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32)); - } -#endif - GPIO.pin[cs_io_num].pad_driver = 0; + gpio_hal_output_enable(&gpio_hal, cs_io_num); + gpio_hal_od_disable(&gpio_hal, cs_io_num); esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false); if (cs_id == 0) { esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false); diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index 9a3aa45732..32112974d5 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -33,16 +33,18 @@ menu "Example Configuration" default y depends on SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP help - This option enables wake up from GPIO, only GPIO0~5 can be used to wake up. Be aware that if you use low - level to trigger wakeup, we strongly recommand you to connect external pull-up resistance. + This option enables wake up from GPIO. Be aware that if you use low level to trigger wakeup, we strongly + recommand you to connect external pull-up resistance. menu "GPIO wakeup configuration" visible if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config EXAMPLE_GPIO_WAKEUP_PIN int "Enable wakeup from GPIO" - default 0 - range 0 5 + default 0 if !IDF_TARGET_ESP32H2_BETA_VERSION_2 + default 7 if IDF_TARGET_ESP32H2_BETA_VERSION_2 + range 0 5 if !IDF_TARGET_ESP32H2_BETA_VERSION_2 + range 7 12 if IDF_TARGET_ESP32H2_BETA_VERSION_2 config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL bool "Enable GPIO high-level wakeup" diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 020430934f..f918008c06 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1444,7 +1444,6 @@ components/soc/esp32h2/include/soc/fe_reg.h components/soc/esp32h2/include/soc/gpio_pins.h components/soc/esp32h2/include/soc/gpio_sd_reg.h components/soc/esp32h2/include/soc/gpio_sd_struct.h -components/soc/esp32h2/include/soc/gpio_struct.h components/soc/esp32h2/include/soc/hwcrypto_reg.h components/soc/esp32h2/include/soc/interrupt_reg.h components/soc/esp32h2/include/soc/ledc_reg.h @@ -1647,10 +1646,8 @@ components/soc/esp32s3/include/soc/uart_reg.h components/soc/esp32s3/include/soc/uart_struct.h components/soc/esp32s3/include/soc/uhci_reg.h components/soc/esp32s3/include/soc/uhci_struct.h -components/soc/esp32s3/include/soc/usb_device_reg.h components/soc/esp32s3/include/soc/usb_pins.h components/soc/esp32s3/include/soc/usb_reg.h -components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h components/soc/esp32s3/include/soc/usb_struct.h components/soc/esp32s3/include/soc/usb_types.h