From a329b15e7ef40e1c86594641309a41d3598833ab Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Tue, 13 Jun 2023 11:10:26 +0800 Subject: [PATCH] Power Management: support pu xtal in light sleep for esp32h2 --- .../port/esp32c6/private_include/pmu_param.h | 124 +++++++++++ .../esp_hw_support/port/esp32h2/pmu_sleep.c | 13 ++ .../port/esp32h2/private_include/pmu_param.h | 197 ++++++++++++++---- components/hal/include/hal/pmu_types.h | 123 ----------- 4 files changed, 297 insertions(+), 160 deletions(-) diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h index 298fdf1b44..2608204a7a 100644 --- a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h @@ -62,6 +62,8 @@ typedef struct { const pmu_lp_system_power_param_t* pmu_lp_system_power_param_default(pmu_lp_mode_t mode); + + typedef struct { pmu_lp_bias_reg_t bias; pmu_lp_regulator0_reg_t regulator0; @@ -70,6 +72,128 @@ typedef struct { const pmu_lp_system_analog_param_t* pmu_lp_system_analog_param_default(pmu_lp_mode_t mode); + + +/* Following software configuration instance type from pmu_struct.h used for the PMU state machine in sleep flow*/ +typedef union { + struct { + uint32_t reserved0 : 21; + uint32_t vdd_spi_pd_en: 1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t reserved1 : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; + }; + struct { + uint32_t reserved2 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved3 : 1; + }; + struct { + uint32_t reserved4 : 31; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_hp_power_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en: 1; + }; + struct { + uint32_t reserved1 : 28; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; + }; + struct { + uint32_t reserved2 : 31; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_lp_power_t; + +typedef struct { + struct { + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; + }; + struct { + uint32_t reserved1 : 16; + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias: 4; + uint32_t dbias : 5; + }; + struct { + uint32_t reserved2: 8; + uint32_t drv_b : 24; + }; +} pmu_hp_analog_t; + +typedef struct { + struct { + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; + }; + struct { + uint32_t reserved1: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; + }; + struct { + uint32_t reserved2: 28; + uint32_t drv_b : 4; + }; +} pmu_lp_analog_t; + +typedef struct { + uint32_t modem_wakeup_wait_cycle; + uint16_t analog_wait_target_cycle; + uint16_t digital_power_down_wait_cycle; + uint16_t digital_power_supply_wait_cycle; + uint16_t digital_power_up_wait_cycle; + uint16_t pll_stable_wait_cycle; + uint8_t modify_icg_cntl_wait_cycle; + uint8_t switch_icg_cntl_wait_cycle; + uint8_t min_slp_slow_clk_cycle; +} pmu_hp_param_t; + +typedef struct { + uint16_t digital_power_supply_wait_cycle; + uint8_t min_slp_slow_clk_cycle; + uint8_t analog_wait_target_cycle; + uint8_t digital_power_down_wait_cycle; + uint8_t digital_power_up_wait_cycle; +} pmu_lp_param_t; + +typedef struct { + union { + uint16_t xtal_stable_wait_slow_clk_cycle; + uint16_t xtal_stable_wait_cycle; + }; +} pmu_hp_lp_param_t; + #define PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES (10) #define PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES (10) diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c index 117ff51adb..6e9c27324e 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c @@ -123,6 +123,18 @@ const pmu_sleep_config_t* pmu_sleep_config_default( analog_default.hp_sys.analog.xpd = 1; analog_default.hp_sys.analog.dbias = 2; } + if (!(pd_flags & PMU_SLEEP_PD_XTAL)){ + analog_default.hp_sys.analog.xpd_trx = 1; + analog_default.hp_sys.analog.xpd = 1; + analog_default.hp_sys.analog.dbias = 25; + analog_default.hp_sys.analog.pd_cur = 0; + analog_default.hp_sys.analog.bias_sleep = 0; + + analog_default.lp_sys[LP(SLEEP)].analog.xpd = 1; + analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = 0; + analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = 0; + analog_default.lp_sys[LP(SLEEP)].analog.dbias = 26; + } config->analog = analog_default; } return config; @@ -159,6 +171,7 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias); pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); + pmu_ll_hp_set_trx_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd_trx); pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_xpd); pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_dbias); diff --git a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h index 57bea2061c..22ca4216e4 100644 --- a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h @@ -70,6 +70,129 @@ typedef struct { const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_mode_t mode); + + +/* Following software configuration instance type from pmu_struct.h used for the PMU state machine in sleep flow*/ +typedef union { + struct { + uint32_t reserved0 : 21; + uint32_t vdd_spi_pd_en: 1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t reserved1 : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; + }; + struct { + uint32_t reserved2 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved3 : 1; + }; + struct { + uint32_t reserved4 : 31; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_hp_power_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en: 1; + }; + struct { + uint32_t reserved1 : 28; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; + }; + struct { + uint32_t reserved2 : 31; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_lp_power_t; + +typedef struct { + struct { + uint32_t reserved0 : 24; + uint32_t xpd_trx : 1; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; + }; + struct { + uint32_t reserved2 : 16; + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias: 4; + uint32_t dbias : 5; + }; + struct { + uint32_t reserved3: 8; + uint32_t drv_b : 24; + }; +} pmu_hp_analog_t; + +typedef struct { + struct { + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; + }; + struct { + uint32_t reserved1: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; + }; + struct { + uint32_t reserved2: 28; + uint32_t drv_b : 4; + }; +} pmu_lp_analog_t; + +typedef struct { + uint32_t modem_wakeup_wait_cycle; + uint16_t analog_wait_target_cycle; + uint16_t digital_power_down_wait_cycle; + uint16_t digital_power_supply_wait_cycle; + uint16_t digital_power_up_wait_cycle; + uint16_t pll_stable_wait_cycle; + uint8_t modify_icg_cntl_wait_cycle; + uint8_t switch_icg_cntl_wait_cycle; + uint8_t min_slp_slow_clk_cycle; +} pmu_hp_param_t; + +typedef struct { + uint16_t digital_power_supply_wait_cycle; + uint8_t min_slp_slow_clk_cycle; + uint8_t analog_wait_target_cycle; + uint8_t digital_power_down_wait_cycle; + uint8_t digital_power_up_wait_cycle; +} pmu_lp_param_t; + +typedef struct { + union { + uint16_t xtal_stable_wait_slow_clk_cycle; + uint16_t xtal_stable_wait_cycle; + }; +} pmu_hp_lp_param_t; + #define PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES (10) #define PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES (10) @@ -168,49 +291,49 @@ typedef struct { } lp_sys[PMU_MODE_LP_MAX]; } pmu_sleep_analog_config_t; -#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) { \ - .hp_sys = { \ - .analog = { \ - .xpd_bias = 0x0, \ - .pd_cur = 1, \ - .bias_sleep = 1, \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .xpd = 1, \ - .dbias = 0, \ - .drv_b = 0xFFFFF8 \ - } \ - }, \ - .lp_sys[PMU_MODE_LP_ACTIVE] = { \ - .analog = { \ - .slp_xpd = 0, \ - .slp_dbias = 0x0, \ - .xpd = 1, \ - .dbias = 0xe, \ - .drv_b = 0x0 \ - } \ - }, \ - .lp_sys[PMU_MODE_LP_SLEEP] = { \ - .analog = { \ - .xpd_bias = 0, \ - .pd_cur = 1, \ - .bias_sleep = 1, \ - .xpd = 0, \ - .dbias = 0, \ - .slp_xpd = 1, \ - .slp_dbias = 0x5, \ - .drv_b = 0x7 \ - } \ - } \ +#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) { \ + .hp_sys = { \ + .analog = { \ + .xpd_trx = 0, \ + .xpd_bias = 0x0, \ + .pd_cur = 1, \ + .bias_sleep = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .xpd = 1, \ + .dbias = 0, \ + .drv_b = 0xFFFFF8 \ + } \ + }, \ + .lp_sys[PMU_MODE_LP_ACTIVE] = { \ + .analog = { \ + .slp_xpd = 0, \ + .slp_dbias = 0x0, \ + .xpd = 1, \ + .dbias = 0xe, \ + .drv_b = 0x0 \ + } \ + }, \ + .lp_sys[PMU_MODE_LP_SLEEP] = { \ + .analog = { \ + .xpd_bias = 0, \ + .pd_cur = 1, \ + .bias_sleep = 1, \ + .xpd = 0, \ + .dbias = 0, \ + .slp_xpd = 1, \ + .slp_dbias = 0x5, \ + .drv_b = 0x7 \ + } \ + } \ } #define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) { \ .hp_sys = { \ .analog = { \ .xpd_bias = 0, \ - .dbg_atten = 0x3, \ .pd_cur = 1, \ .bias_sleep = 1, \ .xpd = 0, \ diff --git a/components/hal/include/hal/pmu_types.h b/components/hal/include/hal/pmu_types.h index 5c4c44e81f..cd21975232 100644 --- a/components/hal/include/hal/pmu_types.h +++ b/components/hal/include/hal/pmu_types.h @@ -42,129 +42,6 @@ typedef enum { PMU_HP_PD_WIFI = 4, /*!< Power domain of WIFI */ } pmu_hp_power_domain_t; - -/* Software configuration instance type from pmu_struct.h */ -typedef union { - struct { - uint32_t reserved0 : 21; - uint32_t vdd_spi_pd_en: 1; - uint32_t mem_dslp : 1; - uint32_t mem_pd_en : 4; - uint32_t wifi_pd_en : 1; - uint32_t reserved1 : 1; - uint32_t cpu_pd_en : 1; - uint32_t aon_pd_en : 1; - uint32_t top_pd_en : 1; - }; - struct { - uint32_t reserved2 : 26; - uint32_t i2c_iso_en : 1; - uint32_t i2c_retention: 1; - uint32_t xpd_bb_i2c : 1; - uint32_t xpd_bbpll_i2c: 1; - uint32_t xpd_bbpll : 1; - uint32_t reserved3 : 1; - }; - struct { - uint32_t reserved4 : 31; - uint32_t xpd_xtal : 1; - }; - uint32_t val; -} pmu_hp_power_t; - -typedef union { - struct { - uint32_t reserved0 : 30; - uint32_t mem_dslp : 1; - uint32_t peri_pd_en: 1; - }; - struct { - uint32_t reserved1 : 28; - uint32_t xpd_xtal32k: 1; - uint32_t xpd_rc32k : 1; - uint32_t xpd_fosc : 1; - uint32_t pd_osc : 1; - }; - struct { - uint32_t reserved2 : 31; - uint32_t xpd_xtal : 1; - }; - uint32_t val; -} pmu_lp_power_t; - -typedef struct { - struct { - uint32_t reserved0 : 25; - uint32_t xpd_bias : 1; - uint32_t dbg_atten : 4; - uint32_t pd_cur : 1; - uint32_t bias_sleep: 1; - }; - struct { - uint32_t reserved1 : 16; - uint32_t slp_mem_xpd : 1; - uint32_t slp_logic_xpd : 1; - uint32_t xpd : 1; - uint32_t slp_mem_dbias : 4; - uint32_t slp_logic_dbias: 4; - uint32_t dbias : 5; - }; - struct { - uint32_t reserved2: 8; - uint32_t drv_b : 24; - }; -} pmu_hp_analog_t; - -typedef struct { - struct { - uint32_t reserved0 : 25; - uint32_t xpd_bias : 1; - uint32_t dbg_atten : 4; - uint32_t pd_cur : 1; - uint32_t bias_sleep: 1; - }; - struct { - uint32_t reserved1: 21; - uint32_t slp_xpd : 1; - uint32_t xpd : 1; - uint32_t slp_dbias: 4; - uint32_t dbias : 5; - }; - struct { - uint32_t reserved2: 28; - uint32_t drv_b : 4; - }; -} pmu_lp_analog_t; - -typedef struct { -#if SOC_PM_SUPPORT_PMU_MODEM_STATE - uint32_t modem_wakeup_wait_cycle; -#endif - uint16_t analog_wait_target_cycle; - uint16_t digital_power_down_wait_cycle; - uint16_t digital_power_supply_wait_cycle; - uint16_t digital_power_up_wait_cycle; - uint16_t pll_stable_wait_cycle; - uint8_t modify_icg_cntl_wait_cycle; - uint8_t switch_icg_cntl_wait_cycle; - uint8_t min_slp_slow_clk_cycle; -} pmu_hp_param_t; - -typedef struct { - uint16_t digital_power_supply_wait_cycle; - uint8_t min_slp_slow_clk_cycle; - uint8_t analog_wait_target_cycle; - uint8_t digital_power_down_wait_cycle; - uint8_t digital_power_up_wait_cycle; -} pmu_lp_param_t; - -typedef struct { - union { - uint16_t xtal_stable_wait_slow_clk_cycle; - uint16_t xtal_stable_wait_cycle; - }; -} pmu_hp_lp_param_t; - #ifdef __cplusplus } #endif