diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/src/bootloader_flash_config_esp32s3.c index 6266a74e8c..357de775a5 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32s3.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32s3.c @@ -33,18 +33,18 @@ void bootloader_flash_update_id() void IRAM_ATTR bootloader_flash_cs_timing_config() { - // SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for FLASH/PSRAM, so we only need to set SPI0 related registers here + //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for FLASH, so we only need to set SPI0 related registers here +#if CONFIG_ESPTOOLPY_OCT_FLASH SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, FLASH_CS_HOLD_TIME, SPI_MEM_CS_HOLD_TIME_S); SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, FLASH_CS_SETUP_TIME, SPI_MEM_CS_SETUP_TIME_S); - - SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); - SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, FLASH_CS_HOLD_TIME, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, FLASH_CS_SETUP_TIME, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); - - // cs high time + //CS high time SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_DELAY_V, FLASH_CS_HOLD_DELAY, SPI_MEM_CS_HOLD_DELAY_S); - SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V, FLASH_CS_HOLD_DELAY, SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S); +#else + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); +#endif } void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig index 2205b88470..044d7c593c 100644 --- a/components/esp32s3/Kconfig +++ b/components/esp32s3/Kconfig @@ -246,6 +246,9 @@ menu "ESP32S3-Specific" help Select the speed for the SPI RAM chip. + config SPIRAM_SPEED_120M + depends on SPIRAM_MODE_QUAD + bool "120MHz clock speed" config SPIRAM_SPEED_80M bool "80MHz clock speed" config SPIRAM_SPEED_40M diff --git a/components/esp_hw_support/port/esp32s3/opiram_psram.c b/components/esp_hw_support/port/esp32s3/opiram_psram.c index 6c45cb4f1f..584f45ce3a 100644 --- a/components/esp_hw_support/port/esp32s3/opiram_psram.c +++ b/components/esp_hw_support/port/esp32s3/opiram_psram.c @@ -40,6 +40,10 @@ #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) #define OCT_PSRAM_CS1_IO 26 +#define OCT_PSRAM_CS_SETUP_TIME 3 +#define OCT_PSRAM_CS_HOLD_TIME 3 +#define OCT_PSRAM_CS_HOLD_DELAY 2 + typedef struct { union { struct { @@ -96,7 +100,7 @@ typedef struct { static const char* TAG = "opi psram"; static DRAM_ATTR psram_size_t s_psram_size; -static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode); +static void IRAM_ATTR s_config_psram_spi_phases(void); /** * Initialise mode registers of the PSRAM @@ -205,6 +209,16 @@ static void IRAM_ATTR s_print_psram_info(opi_psram_mode_reg_t *reg_val) reg_val->mr0.drive_str == 0x02 ? 4 : 8); } +static void psram_set_cs_timing(void) +{ + //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for PSRAM, so we only need to set SPI0 related registers here + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, OCT_PSRAM_CS_HOLD_TIME, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, OCT_PSRAM_CS_SETUP_TIME, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + //CS1 high time + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V, OCT_PSRAM_CS_HOLD_DELAY, SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S); +} + static void IRAM_ATTR s_init_psram_pins(void) { //Set cs1 pin function @@ -218,9 +232,10 @@ static void IRAM_ATTR s_init_psram_pins(void) esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) { s_init_psram_pins(); + psram_set_cs_timing(); //enter MSPI slow mode to init PSRAM device registers - spi_timing_enter_mspi_low_speed_mode(); + spi_timing_enter_mspi_low_speed_mode(true); //set to variable dummy mode SET_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY); @@ -245,10 +260,10 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad #if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC && CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR esp_rom_spi_set_dtr_swap_mode(1, true, true); #endif - + //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly spi_timing_psram_tuning(); - - spi_timing_enter_mspi_high_speed_mode(); + ////Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly + spi_timing_enter_mspi_high_speed_mode(true); /** * Tuning may change SPI1 regs, whereas legacy spi_flash APIs rely on these regs. @@ -256,12 +271,12 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad */ spi_flash_set_rom_required_regs(); - psram_cache_init(mode, vaddrmode); + s_config_psram_spi_phases(); return ESP_OK; } -//register initialization for sram cache params and r/w commands -static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode) +//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement +static void IRAM_ATTR s_config_psram_spi_phases(void) { //Config Write CMD phase for SPI0 to access PSRAM SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); diff --git a/components/esp_hw_support/port/esp32s3/spiram.c b/components/esp_hw_support/port/esp32s3/spiram.c index f554cb096c..e713fab3e3 100644 --- a/components/esp_hw_support/port/esp32s3/spiram.c +++ b/components/esp_hw_support/port/esp32s3/spiram.c @@ -36,10 +36,8 @@ static const char *TAG = "spiram"; #if CONFIG_SPIRAM_SPEED_40M #define PSRAM_SPEED PSRAM_CACHE_S40M -#elif CONFIG_SPIRAM_SPEED_80M +#else //#if CONFIG_SPIRAM_SPEED_80M #define PSRAM_SPEED PSRAM_CACHE_S80M -#else -#define PSRAM_SPEED PSRAM_CACHE_S20M #endif static bool s_spiram_inited = false; @@ -247,8 +245,7 @@ esp_err_t esp_spiram_init(void) ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device", (esp_spiram_get_size() * 8) / (1024 * 1024)); - ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : \ - PSRAM_SPEED == PSRAM_CACHE_S80M ? "sram 80m" : "sram 20m"); + ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : "sram 80m"); ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \ (PSRAM_MODE == PSRAM_VADDR_MODE_EVENODD) ? "even/odd (2-core)" : \ (PSRAM_MODE == PSRAM_VADDR_MODE_LOWHIGH) ? "low/high (2-core)" : \ diff --git a/components/esp_hw_support/port/esp32s3/spiram_psram.c b/components/esp_hw_support/port/esp32s3/spiram_psram.c index 45214a7da8..b0e07abd19 100644 --- a/components/esp_hw_support/port/esp32s3/spiram_psram.c +++ b/components/esp_hw_support/port/esp32s3/spiram_psram.c @@ -39,15 +39,14 @@ #if CONFIG_SPIRAM_MODE_QUAD #include "soc/rtc.h" +#include "spi_flash_private.h" static const char* TAG = "psram"; //Commands for PSRAM chip #define PSRAM_READ 0x03 #define PSRAM_FAST_READ 0x0B -#define PSRAM_FAST_READ_DUMMY 0x3 #define PSRAM_FAST_READ_QUAD 0xEB -#define PSRAM_FAST_READ_QUAD_DUMMY 0x5 #define PSRAM_WRITE 0x02 #define PSRAM_QUAD_WRITE 0x38 #define PSRAM_ENTER_QMODE 0x35 @@ -56,6 +55,10 @@ static const char* TAG = "psram"; #define PSRAM_RESET 0x99 #define PSRAM_SET_BURST_LEN 0xC0 #define PSRAM_DEVICE_ID 0x9F + +#define PSRAM_FAST_READ_DUMMY 4 +#define PSRAM_FAST_READ_QUAD_DUMMY 6 + // ID #define PSRAM_ID_KGD_M 0xff #define PSRAM_ID_KGD_S 8 @@ -78,8 +81,6 @@ static const char* TAG = "psram"; #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) -// For the old version 32Mbit psram, using the spicial driver */ -#define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20) #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) // IO-pins for PSRAM. @@ -99,22 +100,8 @@ static const char* TAG = "psram"; #define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M #define CS_FLASH_SEL SPI_MEM_CS0_DIS_M -#define PSRAM_IO_MATRIX_DUMMY_20M 0 -#define PSRAM_IO_MATRIX_DUMMY_40M 0 -#define PSRAM_IO_MATRIX_DUMMY_80M 0 -#define _SPI_CACHE_PORT 0 -#define _SPI_FLASH_PORT 1 -#define _SPI_80M_CLK_DIV 1 -#define _SPI_40M_CLK_DIV 2 -#define _SPI_20M_CLK_DIV 4 - -typedef enum { - PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */ - PSRAM_CLK_MODE_A1C, /*!< ONE extra clock cycles after CS is set high level */ - PSRAM_CLK_MODE_A2C, /*!< Two extra clock cycles after CS is set high level */ - PSRAM_CLK_MODE_ALON, /*!< clock always on */ - PSRAM_CLK_MODE_MAX, -} psram_clk_mode_t; +#define SPI1_NUM 1 +#define SPI0_NUM 0 typedef enum { @@ -123,35 +110,6 @@ typedef enum { PSRAM_EID_SIZE_64MBITS = 2, } psram_eid_size_t; -typedef struct { - uint8_t flash_clk_io; - uint8_t flash_cs_io; - uint8_t psram_clk_io; - uint8_t psram_cs_io; - uint8_t psram_spiq_sd0_io; - uint8_t psram_spid_sd1_io; - uint8_t psram_spiwp_sd3_io; - uint8_t psram_spihd_sd2_io; -} psram_io_t; - -#define PSRAM_IO_CONF_DEFAULT() { \ - .flash_clk_io = FLASH_CLK_IO, \ - .flash_cs_io = FLASH_CS_IO, \ - .psram_clk_io = PSRAM_CLK_IO, \ - .psram_cs_io = PSRAM_CS_IO, \ - .psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \ - .psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \ - .psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \ - .psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \ -} - -typedef enum { - PSRAM_SPI_1 = 0x1, - /* PSRAM_SPI_2, */ - /* PSRAM_SPI_3, */ - PSRAM_SPI_MAX , -} psram_spi_num_t; - typedef enum { PSRAM_CMD_QPI, PSRAM_CMD_SPI, @@ -160,7 +118,7 @@ typedef enum { typedef esp_rom_spi_cmd_t psram_cmd_t; static uint32_t s_psram_id = 0; -static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode); +static void IRAM_ATTR config_psram_spi_phases(void); extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode) @@ -275,7 +233,7 @@ esp_err_t psram_enable_wrap(uint32_t wrap_size) switch (wrap_size) { case 32: case 0: - psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); + psram_set_wrap_burst_length(1, PSRAM_CMD_QPI); current_wrap_size = wrap_size; return ESP_OK; case 16: @@ -299,7 +257,7 @@ bool psram_support_wrap_size(uint32_t wrap_size) } -//read psram id, should issue `psram_disable_qio_mode` before calling this +//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this static void psram_read_id(int spi_num, uint32_t* dev_id) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, @@ -325,58 +283,36 @@ static void IRAM_ATTR psram_enable_qio_mode(int spi_num) false); /* whether is program/erase operation */ } -static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode) +static void psram_set_cs_timing(void) { - if (clk_mode == PSRAM_CLK_MODE_NORM) { - // SPI1 Flash Operation port - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); - SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); - } else { - SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); - } + //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); } -static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode) +static void IRAM_ATTR psram_gpio_config(void) { - if (clk_mode == PSRAM_CLK_MODE_NORM) { - // SPI0 SRAM Cache port - SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); - SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); - // SPI0 Flash Cache port - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); - SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + //CS1 + uint8_t cs1_io = PSRAM_CS_IO; + if (cs1_io == SPI_CS1_GPIO_NUM) { + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], FUNC_SPICS1_SPICS1); } else { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M); + esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, 0, 0); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO); } -} -//psram gpio init , different working frequency we have different solutions -static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) -{ - psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT(); + //WP HD + uint8_t wp_io = PSRAM_SPIWP_SD3_IO; const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { - /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */ + // MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader. } else { - // FLASH pins are all configured via GPIO matrix in ROM. - psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig); - psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig); - psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig); - psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig); - psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig); - psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio(); - } - esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); - - if (psram_io.psram_cs_io == SPI_CS1_GPIO_NUM) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], FUNC_SPICS1_SPICS1); - } else { - esp_rom_gpio_connect_out_signal(psram_io.psram_cs_io, SPICS1_OUT_IDX, 0, 0); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io.psram_cs_io], PIN_FUNC_GPIO); + // MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader. + wp_io = esp_rom_efuse_get_flash_wp_gpio(); } + //This ROM function will init both WP and HD pins. + esp_rom_spiflash_select_qio_pins(wp_io, spiconfig); } psram_size_t psram_get_size(void) @@ -393,21 +329,6 @@ psram_size_t psram_get_size(void) return PSRAM_SIZE_MAX; } -//used in UT only -bool psram_is_32mbit_ver0(void) -{ - return PSRAM_IS_32MBIT_VER0(s_psram_id); -} - -static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode) -{ - if (spi_num == _SPI_CACHE_PORT) { - REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode); - } else if (spi_num == _SPI_FLASH_PORT) { - REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode); - } -} - /* * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA. * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode. @@ -415,119 +336,67 @@ static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode) esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init { assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now."); - // GPIO related settings - psram_gpio_config(mode); - /* SPI1: set spi1 clk mode, in order to send commands on SPI1 */ - /* SPI1: set cs timing(hold time) in order to send commands on SPI1 */ - psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C); - psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C); + psram_gpio_config(); + psram_set_cs_timing(); - int spi_num = PSRAM_SPI_1; - psram_disable_qio_mode(spi_num); - psram_read_id(spi_num, &s_psram_id); + //enter MSPI slow mode to init PSRAM device registers + spi_timing_enter_mspi_low_speed_mode(true); + + //We use SPI1 to init PSRAM + psram_disable_qio_mode(SPI1_NUM); + psram_read_id(SPI1_NUM, &s_psram_id); if (!PSRAM_IS_VALID(s_psram_id)) { /* 16Mbit psram ID read error workaround: * treat the first read id as a dummy one as the pre-condition, * Send Read ID command again */ - psram_read_id(spi_num, &s_psram_id); + psram_read_id(SPI1_NUM, &s_psram_id); if (!PSRAM_IS_VALID(s_psram_id)) { ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id); return ESP_FAIL; } } - psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX; - if (psram_is_32mbit_ver0()) { - clk_mode = PSRAM_CLK_MODE_A1C; - // SPI1: keep clock mode and cs timing for spi1 - } else { - // For other psram, we don't need any extra clock cycles after cs get back to high level - clk_mode = PSRAM_CLK_MODE_NORM; - // SPI1: set clock mode and cs timing to normal mode - psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); - psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); - } + //SPI1: send psram reset command + psram_reset_mode(SPI1_NUM); + //SPI1: send QPI enable command + psram_enable_qio_mode(SPI1_NUM); - /* SPI1: send psram reset command */ - /* SPI1: send QPI enable command */ - psram_reset_mode(PSRAM_SPI_1); - psram_enable_qio_mode(PSRAM_SPI_1); + //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly + spi_timing_psram_tuning(); - // after sending commands, set spi1 clock mode and cs timing to normal mode. - // since all the operations are sent via SPI0 Cache - /* SPI1: set clock mode to normal mode. */ - /* SPI1: set cs timing to normal */ - psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); - psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); - - /* SPI0: set spi0 clock mode */ - /* SPI0: set spi0 flash/cache cs timing */ - psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode); - psram_set_spi0_cache_cs_timing(clk_mode); - - // SPI0: init SPI commands for Cache - psram_cache_init(mode, vaddrmode); + //Configure SPI0 PSRAM related SPI Phases + config_psram_spi_phases(); + //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly + spi_timing_enter_mspi_high_speed_mode(true); return ESP_OK; } -static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv) +//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement +static void IRAM_ATTR config_psram_spi_phases(void) { - uint32_t freqbits; - if (1 >= freqdiv) { - WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); - } else { - freqbits = (((freqdiv-1)< 0); if (freqdiv == 1) { @@ -76,7 +86,43 @@ void IRAM_ATTR spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqd } } -void IRAM_ATTR spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num) +void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv) +{ + if (freqdiv == 1) { + WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); + } else { + uint32_t freqbits = (((freqdiv-1)< 0) { SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M); SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy, @@ -101,20 +148,50 @@ void IRAM_ATTR spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0, SPI_MEM_EXTRA_DUMMY_CYCLELEN_S); } -} - -//-------------------------------------PSRAM timing tuning-------------------------------------// -void IRAM_ATTR spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv) -{ - if (freqdiv == 1) { - WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); - } else { - uint32_t freqbits = (((freqdiv-1)< 0) { SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M); SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy, @@ -139,10 +217,14 @@ void IRAM_ATTR spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0, SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S); } +#elif CONFIG_SPIRAM_MODE_QUAD + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M); + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (QPI_PSRAM_FAST_READ_DUMMY + extra_dummy - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); +#endif } //-------------------------------------------FLASH/PSRAM Read/Write------------------------------------------// -void IRAM_ATTR spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) { #if CONFIG_ESPTOOLPY_OCT_FLASH // note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state. @@ -153,27 +235,34 @@ void IRAM_ATTR spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, } esp_rom_opiflash_read_raw(addr, buf, len); #else - abort(); + esp_rom_spiflash_read(addr, (uint32_t *)buf, len); #endif } -static void IRAM_ATTR s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +static void s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) { #if CONFIG_SPIRAM_MODE_OCT esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE, OPI_PSRAM_SYNC_WRITE, 16, addr, 32, OCT_PSRAM_WR_DUMMY_NUM, - buf, 8 * len, + buf, len * 8, NULL, 0, BIT(1), false); -#else - abort(); +#elif CONFIG_SPIRAM_MODE_QUAD + psram_exec_cmd(spi_num, 0, + QPI_PSRAM_WRITE, 8, + addr, 24, + 0, + buf, len * 8, + NULL, 0, + SPI_MEM_CS1_DIS_M, + false); #endif } -static void IRAM_ATTR s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +static void s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) { #if CONFIG_SPIRAM_MODE_OCT for (int i = 0; i < 16; i++) { @@ -184,15 +273,22 @@ static void IRAM_ATTR s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, 32, OCT_PSRAM_RD_DUMMY_NUM, NULL, 0, - buf, 8 * len, + buf, len * 8, BIT(1), false); -#else - abort(); +#elif CONFIG_SPIRAM_MODE_QUAD + psram_exec_cmd(spi_num, 0, + QPI_PSRAM_FAST_READ, 8, + addr, 24, + QPI_PSRAM_FAST_READ_DUMMY + s_psram_extra_dummy, + NULL, 0, + buf, len * 8, + SPI_MEM_CS1_DIS_M, + false); #endif } -static void IRAM_ATTR s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read) +static void s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read) { while (len) { uint32_t length = MIN(len, 32); @@ -207,14 +303,58 @@ static void IRAM_ATTR s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t } } -void IRAM_ATTR spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) { s_psram_execution(spi_num, buf, addr, len, false); } -void IRAM_ATTR spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +void spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) { s_psram_execution(spi_num, buf, addr, len, true); } + +/*------------------------------------------------------------------------------------------------- + * SPI1 Timing Tuning APIs + * These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for + * configuring SPI1 timing tuning related registers to find best tuning parameter + *-------------------------------------------------------------------------------------------------*/ +void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num) +{ + /** + * 1. SPI_MEM_DINx_MODE(1), SPI_MEM_DINx_NUM(1) are meaningless + * SPI0 and SPI1 share the SPI_MEM_DINx_MODE(0), SPI_MEM_DINx_NUM(0) for FLASH timing tuning + * 2. We use SPI1 to get the best Flash timing tuning (mode and num) config + */ + spi_timing_config_flash_set_din_mode_num(0, din_mode, din_num); +} + +void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy) +{ + spi_timing_config_flash_set_extra_dummy(1, extra_dummy); +} + +void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num) +{ + /** + * 1. SPI_MEM_SPI_SMEM_DINx_MODE(1), SPI_MEM_SPI_SMEM_DINx_NUM(1) are meaningless + * SPI0 and SPI1 share the SPI_MEM_SPI_SMEM_DINx_MODE(0), SPI_MEM_SPI_SMEM_DINx_NUM(0) for PSRAM timing tuning + * 2. We use SPI1 to get the best PSRAM timing tuning (mode and num) config + */ + spi_timing_config_psram_set_din_mode_num(0, din_mode, din_num); +} + +void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy) +{ +#if CONFIG_SPIRAM_MODE_OCT + //On 728, for SPI1, flash and psram share the extra dummy register + spi_timing_config_flash_set_extra_dummy(1, extra_dummy); +#elif CONFIG_SPIRAM_MODE_QUAD + //Update this `s_psram_extra_dummy`, the `s_psram_read_data` will set dummy according to this `s_psram_extra_dummy` + s_psram_extra_dummy = extra_dummy; + SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_USR_DUMMY); // dummy en + SET_PERI_REG_BITS(SPI_MEM_USER1_REG(1), SPI_MEM_USR_DUMMY_CYCLELEN_V, extra_dummy - 1, SPI_MEM_USR_DUMMY_CYCLELEN_S); +#endif +} + #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING diff --git a/components/spi_flash/esp32s3/spi_timing_config.h b/components/spi_flash/esp32s3/spi_timing_config.h index 6883c28c18..404b51f46c 100644 --- a/components/spi_flash/esp32s3/spi_timing_config.h +++ b/components/spi_flash/esp32s3/spi_timing_config.h @@ -18,81 +18,163 @@ extern "C" { #define SPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num #define SPI_TIMING_TEST_DATA_LEN 64 - #define SPI_TIMING_PSRAM_TEST_DATA_ADDR 0 #define SPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET +/** + * @note BACKGOURND: + * + * The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock: + * + * PLL ----| |---- FLASH Module Clock + * XTAL ----|----> Core Clock ---->| + * RTC8M ----| |---- PSRAM Module Clock + * + * + * DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped will be doubled. + * Speed from high to low: 120M DDR > 80M DDR > 120 SDR > 80M SDR > ... + * + * Module with speed lower than 120M SDR doesn't need to be tuned + * + * @note LIMITATION: + * How to determine the core clock on 728. There are 2 limitations. + * + * 1. MSPI FLASH and PSRAM share the core clock register. Therefore: + * SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ + * + * 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. + */ +//--------------------------------------FLASH Sampling Mode --------------------------------------// +#define SPI_TIMING_FLASH_DTR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_DTR) +#define SPI_TIMING_FLASH_STR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR || !CONFIG_ESPTOOLPY_OCT_FLASH) +//--------------------------------------FLASH Module Clock --------------------------------------// +#if CONFIG_ESPTOOLPY_FLASHFREQ_20M +#define SPI_TIMING_FLASH_MODULE_CLOCK 20 +#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M +#define SPI_TIMING_FLASH_MODULE_CLOCK 40 +#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define SPI_TIMING_FLASH_MODULE_CLOCK 80 +#else //CONFIG_ESPTOOLPY_FLASHFREQ_120M +#define SPI_TIMING_FLASH_MODULE_CLOCK 120 +#endif +//------------------------------------FLASH Needs Tuning or not-------------------------------------// +#if SPI_TIMING_FLASH_DTR_MODE +#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 40) +#elif SPI_TIMING_FLASH_STR_MODE +#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 80) +#endif -//-------------------------------------------FLASH Operation Mode and Corresponding Timing Tuning Parameter Table --------------------------------------// -#define SPI_TIMING_FLASH_DTR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_DTR) -#define SPI_TIMING_FLASH_STR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR || !CONFIG_ESPTOOLPY_OCT_FLASH) +//--------------------------------------PSRAM Sampling Mode --------------------------------------// +#define SPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT +#define SPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT +//--------------------------------------PSRAM Module Clock --------------------------------------// +#if CONFIG_ESP32S3_SPIRAM_SUPPORT +#if CONFIG_SPIRAM_SPEED_40M +#define SPI_TIMING_PSRAM_MODULE_CLOCK 40 +#elif CONFIG_SPIRAM_SPEED_80M +#define SPI_TIMING_PSRAM_MODULE_CLOCK 80 +#else //CONFIG_SPIRAM_SPEED_120M +#define SPI_TIMING_PSRAM_MODULE_CLOCK 120 +#endif +#else //Disable PSRAM +#define SPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz, because we rely on `SPI_TIMING_PSRAM_MODULE_CLOCK` macro for calculation and check below, see `Determine the Core Clock` chapter +#endif +//------------------------------------PSRAM Needs Tuning or not-------------------------------------// +#if SPI_TIMING_PSRAM_DTR_MODE +#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 40) +#elif SPI_TIMING_PSRAM_STR_MODE +#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 80) +#endif -/* Determine A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ*/ -//OCTAL FLASH -#if CONFIG_ESPTOOLPY_OCT_FLASH -//OCT FLASH 80M DTR +/** + * @note Define A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ + */ +/** + * Due to MSPI core clock is used by both MSPI Flash and PSRAM clock, + * define the STR/DTR mode here for selecting the core clock: + * @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2 + */ +#if (SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE) +#define SPI_TIMING_CORE_CLOCK_DIV 2 +#else //#if (SPI_TIMING_FLASH_STR_MODE && (SPI_TIMING_PSRAM_STR_MODE || !CONFIG_ESP32S3_SPIRAM_SUPPORT)) +#define SPI_TIMING_CORE_CLOCK_DIV 1 +#endif + +///////////////////////////////////// FLASH CORE CLOCK ///////////////////////////////////// +//FLASH 80M DTR #if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160 +#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160 #endif -//OCT FLASH 120M DTR +//FLASH 120M DTR #if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 +#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 #endif -//OCT FLASH 120M STR +//FLASH 120M STR #if SPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 +#if (SPI_TIMING_CORE_CLOCK_DIV == 2) +#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 +#elif (SPI_TIMING_CORE_CLOCK_DIV == 1) +#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120 #endif +#endif //FLASH 120M STR -#endif //#if CONFIG_ESPTOOLPY_OCT_FLASH -/* QUAD FLASH Operation Mode should be added here if needed */ - - -//---------------------------------------PSRAM Operation Mode and Corresponding Timing Tuning Parameter Table--------------------------------------// -#define SPI_TIMING_PSRAM_DTR_MODE 1 //Currently we only support DTR Octal PSRAM -#define SPI_TIMING_PSRAM_STR_MODE 0 - -//OCTAL PSRAM -#if CONFIG_SPIRAM_MODE_OCT - -//OCT 80M PSRAM +///////////////////////////////////// PSRAM CORE CLOCK ///////////////////////////////////// +//PSRAM 80M DTR #if SPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M -#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160 +#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160 #endif -#endif //#if CONFIG_SPIRAM_MODE_OCT -/* QUAD PSRAM Operation Mode should be added here if needed */ - - -//------------------------------------------Get the timing tuning config-----------------------------------------------// -#ifdef SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ -//FLASH needs tuning, and it expects this core clock: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ -#define SPI_TIMING_FLASH_NEEDS_TUNING 1 +//PSRAM 120M STR +#if SPI_TIMING_PSRAM_STR_MODE && CONFIG_SPIRAM_SPEED_120M +#if (SPI_TIMING_CORE_CLOCK_DIV == 2) +#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 +#elif (SPI_TIMING_CORE_CLOCK_DIV == 1) +#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120 #endif +#endif //PSRAM 120M STR -#ifdef SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ -//PSRAM needs tuning, and it expects this core clock: SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ -#define SPI_TIMING_PSRAM_NEEDS_TUNING 1 -#endif -//If both FLASH and PSRAM need tuning, the core clock should be same +//------------------------------------------Determine the Core Clock-----------------------------------------------// +/** + * @note + * Limitation 1: + * On 728, MSPI FLASH and PSRAM share the core clock register. Therefore, + * the expected CORE CLOCK frequencies should be the same. + */ #if SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING _Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported"); -#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ +#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ -//If only FLASH needs tuning, the core clock could be as FLASH expected +//If only FLASH needs tuning, the core clock COULD be as FLASH expected #elif SPI_TIMING_FLASH_NEEDS_TUNING && !SPI_TIMING_PSRAM_NEEDS_TUNING -#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ +_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); +#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ -//If only PSRAM needs tuning, the core clock could be as PSRAM expected +//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected #elif !SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING -#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ +_Static_assert(SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); +#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ #else #define SPI_TIMING_CORE_CLOCK_MHZ 80 #endif +/** + * @note + * Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. + */ +#define CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n)) + +#if SPI_TIMING_FLASH_DTR_MODE +_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); +#endif +#if SPI_TIMING_PSRAM_DTR_MODE +_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); +#endif + + //------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------// #define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \ (spi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ @@ -151,6 +233,15 @@ void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dumm void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len); void spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, uint32_t addr, uint32_t len); +/*------------------------------------------------------------------------------------------------- + * SPI1 Timing Tuning APIs + * These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for + * configuring SPI1 timing tuning related registers to find best tuning parameter + *-------------------------------------------------------------------------------------------------*/ +void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num); +void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy); +void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num); +void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy); #ifdef __cplusplus } #endif diff --git a/components/spi_flash/include/spi_flash_private.h b/components/spi_flash/include/spi_flash_private.h index 7435359f3e..1a8ad6f231 100644 --- a/components/spi_flash/include/spi_flash_private.h +++ b/components/spi_flash/include/spi_flash_private.h @@ -31,6 +31,18 @@ extern "C" { #endif +/** + * This struct provide MSPI Flash necessary timing related config + */ +typedef struct { + uint8_t flash_clk_div; /*!< clock divider of Flash module. */ + uint8_t flash_extra_dummy; /*!< timing required extra dummy length for Flash */ + bool flash_setup_en; /*!< SPI0/1 Flash setup enable or not */ + uint8_t flash_setup_time; /*!< SPI0/1 Flash setup time. This value should be set to register directly */ + bool flash_hold_en; /*!< SPI0/1 Flash hold enable or not */ + uint8_t flash_hold_time; /*!< SPI0/1 Flash hold time. This value should be set to register directly */ +} spi_timing_flash_config_t; + /** * @brief Register ROM functions and init flash device registers to make use of octal flash */ @@ -38,13 +50,15 @@ esp_err_t esp_opiflash_init(void); /** * @brief Make MSPI work under 20Mhz + * @param control_spi1 Select whether to control SPI1. For tuning, we need to use SPI1. After tuning (during startup stage), let the flash driver to control SPI1 */ -void spi_timing_enter_mspi_low_speed_mode(void); +void spi_timing_enter_mspi_low_speed_mode(bool control_spi1); /** * @brief Make MSPI work under the frequency as users set + * @param control_spi1 Select whether to control SPI1. For tuning, we need to use SPI1. After tuning (during startup stage), let the flash driver to control SPI1 */ -void spi_timing_enter_mspi_high_speed_mode(void); +void spi_timing_enter_mspi_high_speed_mode(bool control_spi1); /** * @brief Tune MSPI flash timing to make it work under high frequency @@ -67,6 +81,12 @@ void esp_mspi_pin_init(void); */ void spi_flash_set_rom_required_regs(void); +/** + * @brief Get MSPI Flash necessary timing related config + * @param config see `spi_timing_flash_config_t` + */ +void spi_timing_get_flash_regs(spi_timing_flash_config_t *config); + #ifdef __cplusplus } #endif diff --git a/components/spi_flash/linker.lf b/components/spi_flash/linker.lf index ae285a1c2c..ee60692de1 100644 --- a/components/spi_flash/linker.lf +++ b/components/spi_flash/linker.lf @@ -14,6 +14,7 @@ entries: if IDF_TARGET_ESP32S3 = y: spi_flash_timing_tuning (noflash) + spi_timing_config (noflash) if IDF_TARGET_ESP32S3 = y && ESPTOOLPY_OCT_FLASH = y: spi_flash_oct_flash_init (noflash) diff --git a/components/spi_flash/spi_flash_timing_tuning.c b/components/spi_flash/spi_flash_timing_tuning.c index 03e055ffcc..0c46788e0a 100644 --- a/components/spi_flash/spi_flash_timing_tuning.c +++ b/components/spi_flash/spi_flash_timing_tuning.c @@ -20,6 +20,12 @@ #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(*(arr))) +#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +const static char *TAG = "MSPI Timing"; +static spi_timing_tuning_param_t s_flash_best_timing_tuning_config; +static spi_timing_tuning_param_t s_psram_best_timing_tuning_config; +#endif + /*------------------------------------------------------------------------------ * Common settings *----------------------------------------------------------------------------*/ @@ -41,11 +47,6 @@ void spi_timing_set_pin_drive_strength(void) } } -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING -static char *TAG = "MSPI Timing"; -static spi_timing_tuning_param_t s_flash_best_timing_tuning_config; -static spi_timing_tuning_param_t s_psram_best_timing_tuning_config; - /*------------------------------------------------------------------------------ * Static functions to get clock configs *----------------------------------------------------------------------------*/ @@ -75,12 +76,15 @@ static uint32_t get_psram_clock_divider(void) return SPI_TIMING_CORE_CLOCK_MHZ / 40; #elif CONFIG_SPIRAM_SPEED_80M return SPI_TIMING_CORE_CLOCK_MHZ / 80; +#elif CONFIG_SPIRAM_SPEED_120M + return SPI_TIMING_CORE_CLOCK_MHZ / 120; #else //Will enter this branch only if PSRAM is not enable return 0; #endif } +#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING /*------------------------------------------------------------------------------ * Static functions to do timing tuning *----------------------------------------------------------------------------*/ @@ -121,25 +125,15 @@ static void sweep_for_success_sample_points(uint8_t *reference_data, const spi_t memset(read_data, 0, SPI_TIMING_TEST_DATA_LEN); #if SPI_TIMING_FLASH_NEEDS_TUNING if (is_flash) { - /** - * 1. SPI_MEM_DINx_MODE(1), SPI_MEM_DINx_NUM(1) are meaningless - * SPI0 and SPI1 share the SPI_MEM_DINx_MODE(0), SPI_MEM_DINx_NUM(0) for FLASH timing tuning - * 2. We use SPI1 to get the best Flash timing tuning (mode and num) config - */ - spi_timing_config_flash_set_din_mode_num(0, config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); - spi_timing_config_flash_set_extra_dummy(1, config->tuning_config_table[config_idx].extra_dummy_len); + spi_timing_config_flash_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); + spi_timing_config_flash_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len); spi_timing_config_flash_read_data(1, read_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(read_data)); } #endif #if SPI_TIMING_PSRAM_NEEDS_TUNING if (!is_flash) { - /** - * 1. SPI_MEM_SPI_SMEM_DINx_MODE(1), SPI_MEM_SPI_SMEM_DINx_NUM(1) are meaningless - * SPI0 and SPI1 share the SPI_MEM_SPI_SMEM_DINx_MODE(0), SPI_MEM_SPI_SMEM_DINx_NUM(0) for PSRAM timing tuning - * 2. We use SPI1 to get the best PSRAM timing tuning (mode and num) config - */ - spi_timing_config_psram_set_din_mode_num(0, config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); - spi_timing_config_flash_set_extra_dummy(1, config->tuning_config_table[config_idx].extra_dummy_len); + spi_timing_config_psram_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); + spi_timing_config_psram_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len); spi_timing_config_psram_read_data(1, read_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN); } #endif @@ -304,9 +298,9 @@ void spi_timing_flash_tuning(void) ESP_EARLY_LOGW("FLASH", "DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version."); /** * set SPI01 related regs to 20mhz configuration, to get reference data from FLASH - * see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode) + * see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode`) */ - spi_timing_enter_mspi_low_speed_mode(); + spi_timing_enter_mspi_low_speed_mode(true); //Disable the variable dummy mode when doing timing tuning CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY); //GD flash will read error in variable mode with 20MHz @@ -317,7 +311,7 @@ void spi_timing_flash_tuning(void) get_flash_tuning_configs(&timing_configs); do_tuning(reference_data, &timing_configs, true); - spi_timing_enter_mspi_high_speed_mode(); + spi_timing_enter_mspi_high_speed_mode(true); } #else void spi_timing_flash_tuning(void) @@ -343,6 +337,8 @@ static void get_psram_tuning_configs(spi_timing_config_t *config) *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, PSRAM_MODE); #elif CONFIG_SPIRAM_SPEED_80M *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE); +#elif CONFIG_SPIRAM_SPEED_120M + *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE); #endif #undef PSRAM_MODE @@ -353,9 +349,9 @@ void spi_timing_psram_tuning(void) ESP_EARLY_LOGW("PSRAM", "DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version."); /** * set SPI01 related regs to 20mhz configuration, to write reference data to PSRAM - * see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode) + * see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode`) */ - spi_timing_enter_mspi_low_speed_mode(); + spi_timing_enter_mspi_low_speed_mode(true); // write data into psram, used to do timing tuning test. uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN]; @@ -370,7 +366,7 @@ void spi_timing_psram_tuning(void) CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY); //Get required config, and set them to PSRAM related registers do_tuning(reference_data, &timing_configs, false); - spi_timing_enter_mspi_high_speed_mode(); + spi_timing_enter_mspi_high_speed_mode(true); } #else @@ -381,20 +377,23 @@ void spi_timing_psram_tuning(void) #endif //SPI_TIMING_PSRAM_NEEDS_TUNING /*------------------------------------------------------------------------------ - * APIs to make SPI0 and SPI1 FLASH work for high/low freq + * APIs to make SPI0 (and SPI1) FLASH work for high/low freq *----------------------------------------------------------------------------*/ #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING -static void clear_timing_tuning_regs(void) +static void clear_timing_tuning_regs(bool control_spi1) { spi_timing_config_flash_set_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg spi_timing_config_flash_set_extra_dummy(0, 0); - spi_timing_config_flash_set_extra_dummy(1, 0); + if (control_spi1) { + spi_timing_config_flash_set_extra_dummy(1, 0); + } else { + //Won't touch SPI1 registers + } } #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING -void spi_timing_enter_mspi_low_speed_mode(void) +void spi_timing_enter_mspi_low_speed_mode(bool control_spi1) { -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING /** * Here we are going to slow the SPI1 frequency to 20Mhz, so we need to set SPI1 din_num and din_mode regs. * @@ -406,22 +405,26 @@ void spi_timing_enter_mspi_low_speed_mode(void) //Switch SPI1 and SPI0 clock as 20MHz, set its SPIMEM core clock as 80M and set clock division as 4 spi_timing_config_set_core_clock(0, SPI_TIMING_CONFIG_CORE_CLOCK_80M); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. - spi_timing_config_set_flash_clock(1, 4); spi_timing_config_set_flash_clock(0, 4); + if (control_spi1) { + //After tuning, won't touch SPI1 again + spi_timing_config_set_flash_clock(1, 4); + } - clear_timing_tuning_regs(); -#else - //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned +#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING + clear_timing_tuning_regs(control_spi1); #endif } #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING -static void set_timing_tuning_regs_as_required(void) +static void set_timing_tuning_regs_as_required(bool control_spi1) { //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg spi_timing_config_flash_set_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num); spi_timing_config_flash_set_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len); - spi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len); + if (control_spi1) { + spi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len); + } spi_timing_config_psram_set_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num); spi_timing_config_psram_set_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len); @@ -429,14 +432,14 @@ static void set_timing_tuning_regs_as_required(void) #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING /** - * Set SPI0 and SPI1 flash module clock, din_num, din_mode and extra dummy, + * Set SPI0 FLASH and PSRAM module clock, din_num, din_mode and extra dummy, * according to the configuration got from timing tuning function (`calculate_best_flash_tuning_config`). + * iF control_spi1 == 1, will also update SPI1 timing registers. Should only be set to 1 when do tuning. * * This function should always be called after `spi_timing_flash_tuning` or `calculate_best_flash_tuning_config` */ -void spi_timing_enter_mspi_high_speed_mode(void) +void spi_timing_enter_mspi_high_speed_mode(bool control_spi1) { -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING spi_timing_config_core_clock_t core_clock = get_mspi_core_clock(); uint32_t flash_div = get_flash_clock_divider(); uint32_t psram_div = get_psram_clock_divider(); @@ -445,12 +448,31 @@ void spi_timing_enter_mspi_high_speed_mode(void) spi_timing_config_set_core_clock(0, core_clock); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. //Set FLASH module clock spi_timing_config_set_flash_clock(0, flash_div); - spi_timing_config_set_flash_clock(1, flash_div); + if (control_spi1) { + spi_timing_config_set_flash_clock(1, flash_div); + } //Set PSRAM module clock spi_timing_config_set_psram_clock(0, psram_div); - set_timing_tuning_regs_as_required(); -#else - //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned +#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING + set_timing_tuning_regs_as_required(true); #endif } + +/** + * Should be only used by SPI1 Flash driver to know the necessary timing registers + */ +void spi_timing_get_flash_regs(spi_timing_flash_config_t *config) +{ + config->flash_clk_div = get_flash_clock_divider(); +#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING + config->flash_extra_dummy = s_flash_best_timing_tuning_config.extra_dummy_len; +#else + config->flash_extra_dummy = 0; +#endif + config->flash_setup_en = REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_SETUP); + config->flash_setup_time = REG_GET_FIELD(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME); + + config->flash_hold_en = REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD); + config->flash_hold_time = REG_GET_FIELD(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME); +}