From 1a7c52a2303103272494fdbd60c00bad24aa9bd5 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Fri, 27 Dec 2024 16:10:38 +0530 Subject: [PATCH 1/2] feat(hal/aes): Support AES pseudo rounds function in ESP32-H2 ECO5 --- components/hal/aes_hal.c | 4 +- components/hal/esp32c5/include/hal/aes_ll.h | 8 +++ components/hal/esp32h2/include/hal/aes_ll.h | 35 ++++++++++ .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32h2/include/soc/soc_caps.h | 2 + components/soc/esp32h2/register/soc/aes_reg.h | 59 ++++++++++++++++- .../soc/esp32h2/register/soc/aes_struct.h | 64 ++++++++++++++++++- 7 files changed, 172 insertions(+), 4 deletions(-) diff --git a/components/hal/aes_hal.c b/components/hal/aes_hal.c index 92760958e0..f70ed1b987 100644 --- a/components/hal/aes_hal.c +++ b/components/hal/aes_hal.c @@ -43,7 +43,9 @@ void aes_hal_transform_block(const void *input_block, void *output_block) #ifdef SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION void aes_hal_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { - aes_ll_enable_pseudo_rounds(enable, base, increment, key_rng_cnt); + if (aes_ll_is_pseudo_rounds_function_supported()) { + aes_ll_enable_pseudo_rounds(enable, base, increment, key_rng_cnt); + } } #endif // SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION diff --git a/components/hal/esp32c5/include/hal/aes_ll.h b/components/hal/esp32c5/include/hal/aes_ll.h index 7051bc3189..0b6b169803 100644 --- a/components/hal/esp32c5/include/hal/aes_ll.h +++ b/components/hal/esp32c5/include/hal/aes_ll.h @@ -264,6 +264,14 @@ static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_ } } +/** + * @brief Check if the pseudo round function is supported + */ +static inline bool aes_ll_is_pseudo_rounds_function_supported(void) +{ + return true; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/aes_ll.h b/components/hal/esp32h2/include/hal/aes_ll.h index f13d417eb5..7c505e71fe 100644 --- a/components/hal/esp32h2/include/hal/aes_ll.h +++ b/components/hal/esp32h2/include/hal/aes_ll.h @@ -12,6 +12,9 @@ #include "soc/pcr_struct.h" #include "hal/aes_types.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" + #ifdef __cplusplus extern "C" { #endif @@ -241,6 +244,38 @@ static inline void aes_ll_interrupt_clear(void) REG_WRITE(AES_INT_CLEAR_REG, 1); } +/** + * @brief Enable the pseudo-round function during AES operations + * + * @param enable true to enable, false to disable + * @param base basic number of pseudo rounds, zero if disable + * @param increment increment number of pseudo rounds, zero if disable + * @param key_rng_cnt update frequency of the pseudo-key, zero if disable + */ +static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +{ + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable); + + if (enable) { + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt); + } else { + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0); + } +} + +/** + * @brief Check if the pseudo round function is supported + * The AES pseudo round function is only avliable in chip version + * above 1.2 in ESP32-H2 + */ +static inline bool aes_ll_is_pseudo_rounds_function_supported(void) +{ + return ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102); +} #ifdef __cplusplus } diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index c88a1151b5..96069dfddd 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -255,6 +255,10 @@ config SOC_AES_SUPPORT_AES_256 bool default y +config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION + bool + default y + config SOC_ADC_DIG_CTRL_SUPPORTED bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 7bfcd16fc2..589531d588 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -104,6 +104,8 @@ #define SOC_AES_SUPPORT_AES_128 (1) #define SOC_AES_SUPPORT_AES_256 (1) +#define SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION (1) /*!< Only avliable in chip version above 1.2*/ + /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ #define SOC_ADC_DIG_CTRL_SUPPORTED 1 diff --git a/components/soc/esp32h2/register/soc/aes_reg.h b/components/soc/esp32h2/register/soc/aes_reg.h index c096489ca4..bf09b4b34a 100644 --- a/components/soc/esp32h2/register/soc/aes_reg.h +++ b/components/soc/esp32h2/register/soc/aes_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -412,6 +412,63 @@ extern "C" { #define AES_DMA_EXIT_V 0x00000001U #define AES_DMA_EXIT_S 0 +/** AES_RX_RESET_REG register + * AES-DMA reset rx-fifo register + */ +#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0) +/** AES_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset rx_fifo under dma_aes working mode. + */ +#define AES_RX_RESET (BIT(0)) +#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S) +#define AES_RX_RESET_V 0x00000001U +#define AES_RX_RESET_S 0 + +/** AES_TX_RESET_REG register + * AES-DMA reset tx-fifo register + */ +#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4) +/** AES_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset tx_fifo under dma_aes working mode. + */ +#define AES_TX_RESET (BIT(0)) +#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S) +#define AES_TX_RESET_V 0x00000001U +#define AES_TX_RESET_S 0 + +/** AES_PSEUDO_REG register + * AES PSEUDO function configure register + */ +#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0) +/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0; + * This bit decides whether the pseudo round function is enable or not. + */ +#define AES_PSEUDO_EN (BIT(0)) +#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S) +#define AES_PSEUDO_EN_V 0x00000001U +#define AES_PSEUDO_EN_S 0 +/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2; + * Those bits decides the basic number of pseudo round number. + */ +#define AES_PSEUDO_BASE 0x0000000FU +#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S) +#define AES_PSEUDO_BASE_V 0x0000000FU +#define AES_PSEUDO_BASE_S 1 +/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2; + * Those bits decides the increment number of pseudo round number + */ +#define AES_PSEUDO_INC 0x00000003U +#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S) +#define AES_PSEUDO_INC_V 0x00000003U +#define AES_PSEUDO_INC_S 5 +/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7; + * Those bits decides the update frequency of the pseudo-key. + */ +#define AES_PSEUDO_RNG_CNT 0x00000007U +#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S) +#define AES_PSEUDO_RNG_CNT_V 0x00000007U +#define AES_PSEUDO_RNG_CNT_S 7 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/register/soc/aes_struct.h b/components/soc/esp32h2/register/soc/aes_struct.h index 716d9a5abd..55474adf35 100644 --- a/components/soc/esp32h2/register/soc/aes_struct.h +++ b/components/soc/esp32h2/register/soc/aes_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -398,6 +398,61 @@ typedef union { uint32_t val; } aes_dma_exit_reg_t; +/** Type of rx_reset register + * AES-DMA reset rx-fifo register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset rx_fifo under dma_aes working mode. + */ + uint32_t rx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_rx_reset_reg_t; + +/** Type of tx_reset register + * AES-DMA reset tx-fifo register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset tx_fifo under dma_aes working mode. + */ + uint32_t tx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_tx_reset_reg_t; + + +/** Group: Configuration register */ +/** Type of pseudo register + * AES PSEUDO function configure register + */ +typedef union { + struct { + /** pseudo_en : R/W; bitpos: [0]; default: 0; + * This bit decides whether the pseudo round function is enable or not. + */ + uint32_t pseudo_en:1; + /** pseudo_base : R/W; bitpos: [4:1]; default: 2; + * Those bits decides the basic number of pseudo round number. + */ + uint32_t pseudo_base:4; + /** pseudo_inc : R/W; bitpos: [6:5]; default: 2; + * Those bits decides the increment number of pseudo round number + */ + uint32_t pseudo_inc:2; + /** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7; + * Those bits decides the update frequency of the pseudo-key. + */ + uint32_t pseudo_rng_cnt:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} aes_pseudo_reg_t; /** Group: memory type */ @@ -483,12 +538,17 @@ typedef struct { volatile aes_int_ena_reg_t int_ena; volatile aes_date_reg_t date; volatile aes_dma_exit_reg_t dma_exit; + uint32_t reserved_0bc; + volatile aes_rx_reset_reg_t rx_reset; + volatile aes_tx_reset_reg_t tx_reset; + uint32_t reserved_0c8[2]; + volatile aes_pseudo_reg_t pseudo; } aes_dev_t; extern aes_dev_t AES; #ifndef __cplusplus -_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure"); +_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure"); #endif #ifdef __cplusplus From b26109cede8b6c232f04d07ff9016db953ef2547 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Fri, 27 Dec 2024 17:15:33 +0530 Subject: [PATCH 2/2] feat(hal/spi_flash_encrypted): Support AES pseudo rounds function in ESP32-H2 ECO5 --- .../include/hal/spi_flash_encrypted_ll.h | 8 ++++ .../include/hal/spi_flash_encrypted_ll.h | 8 ++++ .../include/hal/spi_flash_encrypted_ll.h | 42 +++++++++++++++++-- components/hal/spi_flash_encrypt_hal_iram.c | 4 +- .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32h2/include/soc/soc_caps.h | 1 + .../soc/esp32h2/register/soc/spi_mem_struct.h | 13 +++++- .../soc/esp32h2/register/soc/xts_aes_reg.h | 38 ++++++++++++++++- 8 files changed, 111 insertions(+), 7 deletions(-) diff --git a/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h index 49239efd27..59b66cecda 100644 --- a/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h @@ -169,6 +169,14 @@ static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8 } } +/** + * @brief Check if the pseudo round function is supported + */ +static inline bool spi_flash_encrypt_ll_is_pseudo_rounds_function_supported(void) +{ + return true; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h index 0d79cbd678..88fdee0486 100644 --- a/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h @@ -169,6 +169,14 @@ static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8 } } +/** + * @brief Check if the pseudo round function is supported + */ +static inline bool spi_flash_encrypt_ll_is_pseudo_rounds_function_supported(void) +{ + return true; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h index 20c303344a..93a707e76c 100644 --- a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,11 +20,14 @@ #include "soc/soc_caps.h" #include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" + #ifdef __cplusplus extern "C" { #endif -/// Choose type of chip you want to encrypt manully +/// Choose type of chip you want to encrypt manually typedef enum { FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip. @@ -51,7 +54,7 @@ static inline void spi_flash_encrypt_ll_disable(void) } /** - * Choose type of chip you want to encrypt manully + * Choose type of chip you want to encrypt manually * * @param type The type of chip to be encrypted * @@ -146,6 +149,39 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) return ((address % length) == 0) ? true : false; } +/** + * @brief Enable the pseudo-round function during XTS-AES operations + * + * @param mode set the mode for pseudo rounds, zero to disable, with increasing security upto three. + * @param base basic number of pseudo rounds, zero if disable + * @param increment increment number of pseudo rounds, zero if disable + * @param key_rng_cnt update frequency of the pseudo-key, zero if disable + */ +static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +{ + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_MODE_PSEUDO, mode); + + if (mode) { + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_BASE, base); + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_INC, increment); + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_RNG_CNT, key_rng_cnt); + } else { + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_BASE, 0); + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_INC, 0); + REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_RNG_CNT, 0); + } +} + +/** + * @brief Check if the pseudo round function is supported + * The XTS-AES pseudo round function is only avliable in chip version + * above 1.2 in ESP32-H2 + */ +static inline bool spi_flash_encrypt_ll_is_pseudo_rounds_function_supported(void) +{ + return ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/spi_flash_encrypt_hal_iram.c b/components/hal/spi_flash_encrypt_hal_iram.c index 68a309a92d..9feb151db5 100644 --- a/components/hal/spi_flash_encrypt_hal_iram.c +++ b/components/hal/spi_flash_encrypt_hal_iram.c @@ -54,6 +54,8 @@ bool spi_flash_encryption_hal_check(uint32_t address, uint32_t length) #ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND void spi_flash_encryption_hal_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) { - spi_flash_encrypt_ll_enable_pseudo_rounds(mode, base, increment, key_rng_cnt); + if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { + spi_flash_encrypt_ll_enable_pseudo_rounds(mode, base, increment, key_rng_cnt); + } } #endif /* SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND */ diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 96069dfddd..7b30cf6742 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1291,6 +1291,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128 bool default y +config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND + bool + default y + config SOC_APM_CTRL_FILTER_SUPPORTED bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 589531d588..238264020a 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -512,6 +512,7 @@ #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) #define SOC_FLASH_ENCRYPTION_XTS_AES 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1 /*!< Only avliable in chip version above 1.2*/ /*-------------------------- APM CAPS ----------------------------------------*/ #define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ diff --git a/components/soc/esp32h2/register/soc/spi_mem_struct.h b/components/soc/esp32h2/register/soc/spi_mem_struct.h index 45810eb9af..189a7db5eb 100644 --- a/components/soc/esp32h2/register/soc/spi_mem_struct.h +++ b/components/soc/esp32h2/register/soc/spi_mem_struct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1033,7 +1033,16 @@ typedef volatile struct spi_mem_dev_s { }; uint32_t val; } dpa_ctrl; - uint32_t reserved_38c; + union { + struct { + uint32_t reg_mode_pseudo : 2; /*Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. 2'b11: crypto with pseudo.*/ + uint32_t reg_pseudo_rng_cnt : 3; /*xts aes peseudo function base round that must be performed.*/ + uint32_t reg_pseudo_base : 4; /*xts aes peseudo function base round that must be performed.*/ + uint32_t reg_pseudo_inc : 2; /*xts aes peseudo function increment round that will be performed randomly between 0 & 2**(inc+1).*/ + uint32_t reserved11 : 27; /*reserved*/ + }; + uint32_t val; + } xts_pseudo_round_conf; uint32_t reserved_390; uint32_t reserved_394; uint32_t reserved_398; diff --git a/components/soc/esp32h2/register/soc/xts_aes_reg.h b/components/soc/esp32h2/register/soc/xts_aes_reg.h index 921701bc74..b81c0a3f38 100644 --- a/components/soc/esp32h2/register/soc/xts_aes_reg.h +++ b/components/soc/esp32h2/register/soc/xts_aes_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -124,6 +124,42 @@ formance of cryption will decrease together with this number increasing).*/ #define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7 #define XTS_AES_CRYPT_SECURITY_LEVEL_S 0 +/** XTS_AES_PSEUDO_ROUND_CONF_REG register + * SPI memory encryption PSEUDO register + */ +#define XTS_AES_PSEUDO_ROUND_CONF_REG(i) (REG_SPI_MEM_BASE(i) + 0x38c) +/** XTS_AES_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define XTS_AES_MODE_PSEUDO 0x00000003U +#define XTS_AES_MODE_PSEUDO_M (XTS_AES_MODE_PSEUDO_V << XTS_AES_MODE_PSEUDO_S) +#define XTS_AES_MODE_PSEUDO_V 0x00000003U +#define XTS_AES_MODE_PSEUDO_S 0 +/** XTS_AES_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define XTS_AES_PSEUDO_RNG_CNT 0x00000007U +#define XTS_AES_PSEUDO_RNG_CNT_M (XTS_AES_PSEUDO_RNG_CNT_V << XTS_AES_PSEUDO_RNG_CNT_S) +#define XTS_AES_PSEUDO_RNG_CNT_V 0x00000007U +#define XTS_AES_PSEUDO_RNG_CNT_S 2 +/** XTS_AES_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ +#define XTS_AES_PSEUDO_BASE 0x0000000FU +#define XTS_AES_PSEUDO_BASE_M (XTS_AES_PSEUDO_BASE_V << XTS_AES_PSEUDO_BASE_S) +#define XTS_AES_PSEUDO_BASE_V 0x0000000FU +#define XTS_AES_PSEUDO_BASE_S 5 +/** XTS_AES_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ +#define XTS_AES_PSEUDO_INC 0x00000003U +#define XTS_AES_PSEUDO_INC_M (XTS_AES_PSEUDO_INC_V << XTS_AES_PSEUDO_INC_S) +#define XTS_AES_PSEUDO_INC_V 0x00000003U +#define XTS_AES_PSEUDO_INC_S 9 + #ifdef __cplusplus } #endif